Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.66 98.25 93.91 97.02 92.44 96.37 99.77 91.89


Total test records in report: 1130
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T1017 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2746994203 Jul 01 10:45:25 AM PDT 24 Jul 01 10:45:26 AM PDT 24 31519582 ps
T282 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1180951977 Jul 01 10:45:19 AM PDT 24 Jul 01 10:45:21 AM PDT 24 23252673 ps
T274 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.742110776 Jul 01 10:45:15 AM PDT 24 Jul 01 10:45:20 AM PDT 24 258256137 ps
T1018 /workspace/coverage/cover_reg_top/13.edn_intr_test.2341193435 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 17185663 ps
T1019 /workspace/coverage/cover_reg_top/4.edn_intr_test.204247230 Jul 01 10:45:09 AM PDT 24 Jul 01 10:45:10 AM PDT 24 10697039 ps
T1020 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2064345666 Jul 01 10:45:31 AM PDT 24 Jul 01 10:45:35 AM PDT 24 871713117 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_intr_test.1006252988 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:49 AM PDT 24 16580649 ps
T1022 /workspace/coverage/cover_reg_top/33.edn_intr_test.2150839740 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:49 AM PDT 24 59224473 ps
T1023 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3314691638 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 34514931 ps
T283 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1523964604 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:38 AM PDT 24 27389670 ps
T284 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1366277417 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 34812284 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4012293683 Jul 01 10:45:17 AM PDT 24 Jul 01 10:45:19 AM PDT 24 22550556 ps
T1025 /workspace/coverage/cover_reg_top/7.edn_intr_test.2224774044 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:27 AM PDT 24 12248211 ps
T1026 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2389480594 Jul 01 10:45:25 AM PDT 24 Jul 01 10:45:30 AM PDT 24 124995199 ps
T1027 /workspace/coverage/cover_reg_top/34.edn_intr_test.68195373 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:41 AM PDT 24 14926987 ps
T298 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.694057585 Jul 01 10:45:13 AM PDT 24 Jul 01 10:45:16 AM PDT 24 328571005 ps
T1028 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3999920158 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:14 AM PDT 24 164321786 ps
T275 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4254210986 Jul 01 10:45:19 AM PDT 24 Jul 01 10:45:26 AM PDT 24 437541070 ps
T285 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4014544234 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:42 AM PDT 24 42791907 ps
T1029 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2681968549 Jul 01 10:45:11 AM PDT 24 Jul 01 10:45:13 AM PDT 24 301660383 ps
T1030 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2554927681 Jul 01 10:45:07 AM PDT 24 Jul 01 10:45:09 AM PDT 24 130985509 ps
T1031 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3055333553 Jul 01 10:45:15 AM PDT 24 Jul 01 10:45:17 AM PDT 24 50206597 ps
T1032 /workspace/coverage/cover_reg_top/49.edn_intr_test.1179577276 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:46 AM PDT 24 23064791 ps
T1033 /workspace/coverage/cover_reg_top/8.edn_intr_test.1609546271 Jul 01 10:45:19 AM PDT 24 Jul 01 10:45:21 AM PDT 24 12842609 ps
T1034 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2684322664 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:48 AM PDT 24 169195677 ps
T1035 /workspace/coverage/cover_reg_top/48.edn_intr_test.2007106264 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 13206006 ps
T1036 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.519812586 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:19 AM PDT 24 205235131 ps
T1037 /workspace/coverage/cover_reg_top/46.edn_intr_test.2738410142 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 15499039 ps
T1038 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1739203575 Jul 01 10:45:13 AM PDT 24 Jul 01 10:45:15 AM PDT 24 23291514 ps
T267 /workspace/coverage/cover_reg_top/5.edn_csr_rw.4138443554 Jul 01 10:45:16 AM PDT 24 Jul 01 10:45:17 AM PDT 24 17653552 ps
T1039 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3453516712 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:43 AM PDT 24 55207391 ps
T268 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3380513029 Jul 01 10:45:07 AM PDT 24 Jul 01 10:45:09 AM PDT 24 75188589 ps
T1040 /workspace/coverage/cover_reg_top/10.edn_intr_test.1423902352 Jul 01 10:45:23 AM PDT 24 Jul 01 10:45:25 AM PDT 24 40310997 ps
T1041 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1217163972 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:45 AM PDT 24 196092980 ps
T1042 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4001040250 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:42 AM PDT 24 176015004 ps
T1043 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.177347916 Jul 01 10:45:00 AM PDT 24 Jul 01 10:45:02 AM PDT 24 21142592 ps
T1044 /workspace/coverage/cover_reg_top/3.edn_intr_test.872668441 Jul 01 10:45:22 AM PDT 24 Jul 01 10:45:23 AM PDT 24 40780704 ps
T1045 /workspace/coverage/cover_reg_top/17.edn_intr_test.1121397764 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 12752400 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_intr_test.4217396515 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 81085578 ps
T1047 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1402564832 Jul 01 10:45:28 AM PDT 24 Jul 01 10:45:29 AM PDT 24 46670042 ps
T1048 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2947033344 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:41 AM PDT 24 65223877 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_tl_errors.976375798 Jul 01 10:45:13 AM PDT 24 Jul 01 10:45:15 AM PDT 24 193093876 ps
T1050 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2430830167 Jul 01 10:45:04 AM PDT 24 Jul 01 10:45:05 AM PDT 24 33598279 ps
T1051 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3720732966 Jul 01 10:45:19 AM PDT 24 Jul 01 10:45:23 AM PDT 24 169289883 ps
T1052 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3307809380 Jul 01 10:45:16 AM PDT 24 Jul 01 10:45:17 AM PDT 24 89337668 ps
T1053 /workspace/coverage/cover_reg_top/11.edn_csr_rw.340691776 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:22 AM PDT 24 34526220 ps
T1054 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3723951592 Jul 01 10:45:00 AM PDT 24 Jul 01 10:45:02 AM PDT 24 61696049 ps
T1055 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1160093757 Jul 01 10:45:02 AM PDT 24 Jul 01 10:45:03 AM PDT 24 82100140 ps
T1056 /workspace/coverage/cover_reg_top/2.edn_intr_test.359403716 Jul 01 10:45:22 AM PDT 24 Jul 01 10:45:30 AM PDT 24 13329825 ps
T1057 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4181230854 Jul 01 10:45:10 AM PDT 24 Jul 01 10:45:12 AM PDT 24 68664700 ps
T1058 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.655080476 Jul 01 10:45:14 AM PDT 24 Jul 01 10:45:16 AM PDT 24 55555517 ps
T276 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2305290398 Jul 01 10:45:19 AM PDT 24 Jul 01 10:45:27 AM PDT 24 4159845028 ps
T1059 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1020866369 Jul 01 10:45:11 AM PDT 24 Jul 01 10:45:13 AM PDT 24 107145080 ps
T1060 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3485393956 Jul 01 10:45:22 AM PDT 24 Jul 01 10:45:24 AM PDT 24 28424121 ps
T1061 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.586992907 Jul 01 10:45:08 AM PDT 24 Jul 01 10:45:09 AM PDT 24 69988445 ps
T1062 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2338887030 Jul 01 10:44:59 AM PDT 24 Jul 01 10:45:01 AM PDT 24 59965357 ps
T1063 /workspace/coverage/cover_reg_top/36.edn_intr_test.3124372830 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:22 AM PDT 24 25650027 ps
T1064 /workspace/coverage/cover_reg_top/30.edn_intr_test.1877176594 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:30 AM PDT 24 24577567 ps
T1065 /workspace/coverage/cover_reg_top/23.edn_intr_test.3236578467 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:50 AM PDT 24 14889665 ps
T1066 /workspace/coverage/cover_reg_top/8.edn_tl_errors.779997821 Jul 01 10:45:10 AM PDT 24 Jul 01 10:45:12 AM PDT 24 256368927 ps
T1067 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2859498785 Jul 01 10:45:23 AM PDT 24 Jul 01 10:45:28 AM PDT 24 495793853 ps
T1068 /workspace/coverage/cover_reg_top/11.edn_intr_test.2574258045 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 34724047 ps
T1069 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3857855996 Jul 01 10:45:14 AM PDT 24 Jul 01 10:45:16 AM PDT 24 83793643 ps
T1070 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3887523738 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:39 AM PDT 24 13441849 ps
T1071 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1437163136 Jul 01 10:45:10 AM PDT 24 Jul 01 10:45:11 AM PDT 24 66765089 ps
T1072 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2273827813 Jul 01 10:45:33 AM PDT 24 Jul 01 10:45:36 AM PDT 24 60965612 ps
T1073 /workspace/coverage/cover_reg_top/39.edn_intr_test.994462935 Jul 01 10:45:17 AM PDT 24 Jul 01 10:45:18 AM PDT 24 25692835 ps
T1074 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1660294646 Jul 01 10:45:18 AM PDT 24 Jul 01 10:45:21 AM PDT 24 251736622 ps
T1075 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1982471588 Jul 01 10:45:18 AM PDT 24 Jul 01 10:45:19 AM PDT 24 90227480 ps
T1076 /workspace/coverage/cover_reg_top/41.edn_intr_test.3162842635 Jul 01 10:45:34 AM PDT 24 Jul 01 10:45:36 AM PDT 24 72370659 ps
T1077 /workspace/coverage/cover_reg_top/43.edn_intr_test.2693625554 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:42 AM PDT 24 48532868 ps
T1078 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3935386747 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:14 AM PDT 24 41256828 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_tl_errors.688073873 Jul 01 10:45:02 AM PDT 24 Jul 01 10:45:04 AM PDT 24 54007235 ps
T1080 /workspace/coverage/cover_reg_top/14.edn_csr_rw.589694447 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:13 AM PDT 24 35349650 ps
T1081 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2536318998 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:41 AM PDT 24 28432166 ps
T1082 /workspace/coverage/cover_reg_top/5.edn_intr_test.1933604162 Jul 01 10:45:17 AM PDT 24 Jul 01 10:45:18 AM PDT 24 42800974 ps
T1083 /workspace/coverage/cover_reg_top/16.edn_csr_rw.68466743 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:49 AM PDT 24 27927800 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.699627212 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 24595888 ps
T1085 /workspace/coverage/cover_reg_top/32.edn_intr_test.1141373118 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:51 AM PDT 24 23850110 ps
T1086 /workspace/coverage/cover_reg_top/29.edn_intr_test.2789597597 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:39 AM PDT 24 54902593 ps
T1087 /workspace/coverage/cover_reg_top/22.edn_intr_test.1600501995 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:40 AM PDT 24 27102509 ps
T1088 /workspace/coverage/cover_reg_top/26.edn_intr_test.42025441 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:46 AM PDT 24 14615282 ps
T1089 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2147688255 Jul 01 10:45:30 AM PDT 24 Jul 01 10:45:32 AM PDT 24 219953124 ps
T1090 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1901244052 Jul 01 10:45:45 AM PDT 24 Jul 01 10:45:50 AM PDT 24 80802855 ps
T1091 /workspace/coverage/cover_reg_top/37.edn_intr_test.4155040210 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:22 AM PDT 24 65715859 ps
T1092 /workspace/coverage/cover_reg_top/45.edn_intr_test.3314958477 Jul 01 10:45:23 AM PDT 24 Jul 01 10:45:25 AM PDT 24 57516277 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2173260266 Jul 01 10:45:18 AM PDT 24 Jul 01 10:45:22 AM PDT 24 84993105 ps
T1094 /workspace/coverage/cover_reg_top/31.edn_intr_test.2042142887 Jul 01 10:45:24 AM PDT 24 Jul 01 10:45:26 AM PDT 24 17156417 ps
T1095 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4162897983 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:49 AM PDT 24 62427844 ps
T269 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2788175822 Jul 01 10:45:24 AM PDT 24 Jul 01 10:45:25 AM PDT 24 55833811 ps
T1096 /workspace/coverage/cover_reg_top/6.edn_intr_test.2330354648 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:44 AM PDT 24 51704172 ps
T1097 /workspace/coverage/cover_reg_top/27.edn_intr_test.1514418115 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:49 AM PDT 24 16962663 ps
T270 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3495175216 Jul 01 10:45:20 AM PDT 24 Jul 01 10:45:27 AM PDT 24 1992247102 ps
T1098 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2266876190 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:23 AM PDT 24 29569085 ps
T271 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2142448723 Jul 01 10:45:11 AM PDT 24 Jul 01 10:45:12 AM PDT 24 33763201 ps
T300 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4174433433 Jul 01 10:45:02 AM PDT 24 Jul 01 10:45:05 AM PDT 24 253738798 ps
T272 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2359964520 Jul 01 10:45:11 AM PDT 24 Jul 01 10:45:12 AM PDT 24 23725806 ps
T1099 /workspace/coverage/cover_reg_top/12.edn_intr_test.98260606 Jul 01 10:45:17 AM PDT 24 Jul 01 10:45:18 AM PDT 24 89991764 ps
T1100 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2831236374 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:37 AM PDT 24 517801811 ps
T1101 /workspace/coverage/cover_reg_top/16.edn_intr_test.627807475 Jul 01 10:45:15 AM PDT 24 Jul 01 10:45:16 AM PDT 24 42146065 ps
T1102 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.239582287 Jul 01 10:45:15 AM PDT 24 Jul 01 10:45:16 AM PDT 24 47792232 ps
T1103 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1178180017 Jul 01 10:45:34 AM PDT 24 Jul 01 10:45:36 AM PDT 24 28786380 ps
T1104 /workspace/coverage/cover_reg_top/9.edn_intr_test.1813339885 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:22 AM PDT 24 44216272 ps
T1105 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2230875265 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:33 AM PDT 24 130993214 ps
T1106 /workspace/coverage/cover_reg_top/18.edn_tl_errors.677258674 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:32 AM PDT 24 85095215 ps
T1107 /workspace/coverage/cover_reg_top/1.edn_csr_rw.315514431 Jul 01 10:45:06 AM PDT 24 Jul 01 10:45:07 AM PDT 24 23899204 ps
T1108 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1754093327 Jul 01 10:45:00 AM PDT 24 Jul 01 10:45:02 AM PDT 24 369998833 ps
T1109 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2574648613 Jul 01 10:45:08 AM PDT 24 Jul 01 10:45:09 AM PDT 24 55983499 ps
T1110 /workspace/coverage/cover_reg_top/20.edn_intr_test.3894407541 Jul 01 10:45:27 AM PDT 24 Jul 01 10:45:29 AM PDT 24 27852168 ps
T273 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1079437058 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:14 AM PDT 24 29545037 ps
T1111 /workspace/coverage/cover_reg_top/19.edn_csr_rw.566807278 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 38624815 ps
T1112 /workspace/coverage/cover_reg_top/1.edn_intr_test.4090325380 Jul 01 10:45:22 AM PDT 24 Jul 01 10:45:23 AM PDT 24 25713545 ps
T1113 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.404919378 Jul 01 10:45:22 AM PDT 24 Jul 01 10:45:25 AM PDT 24 43443118 ps
T1114 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1384619205 Jul 01 10:45:13 AM PDT 24 Jul 01 10:45:16 AM PDT 24 220325768 ps
T1115 /workspace/coverage/cover_reg_top/42.edn_intr_test.1970983502 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:41 AM PDT 24 31498989 ps
T1116 /workspace/coverage/cover_reg_top/28.edn_intr_test.2563835357 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 15072069 ps
T1117 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.780059398 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:30 AM PDT 24 20472458 ps
T1118 /workspace/coverage/cover_reg_top/11.edn_tl_errors.481995414 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:43 AM PDT 24 31080795 ps
T1119 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2867111215 Jul 01 10:45:14 AM PDT 24 Jul 01 10:45:17 AM PDT 24 145375546 ps
T1120 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2811389951 Jul 01 10:45:28 AM PDT 24 Jul 01 10:45:30 AM PDT 24 112903740 ps
T1121 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1004396706 Jul 01 10:45:20 AM PDT 24 Jul 01 10:45:23 AM PDT 24 84161342 ps
T1122 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1153504124 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:44 AM PDT 24 73539575 ps
T1123 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1137888587 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:38 AM PDT 24 14048979 ps
T1124 /workspace/coverage/cover_reg_top/35.edn_intr_test.825003350 Jul 01 10:45:23 AM PDT 24 Jul 01 10:45:25 AM PDT 24 16794870 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3597942990 Jul 01 10:45:07 AM PDT 24 Jul 01 10:45:08 AM PDT 24 39513973 ps
T1126 /workspace/coverage/cover_reg_top/38.edn_intr_test.604531262 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:39 AM PDT 24 50090831 ps
T1127 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1659712156 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:31 AM PDT 24 13782451 ps
T1128 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3953252823 Jul 01 10:45:13 AM PDT 24 Jul 01 10:45:16 AM PDT 24 158888735 ps
T1129 /workspace/coverage/cover_reg_top/0.edn_intr_test.1519785041 Jul 01 10:45:12 AM PDT 24 Jul 01 10:45:14 AM PDT 24 119816287 ps
T1130 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3021254856 Jul 01 10:45:14 AM PDT 24 Jul 01 10:45:15 AM PDT 24 24856109 ps

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4146972352
Short name T4
Test name
Test status
Simulation time 92011397968 ps
CPU time 1140.93 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:29:20 AM PDT 24
Peak memory 225228 kb
Host smart-f01e773d-acba-4a60-81e2-28907efd17f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146972352 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4146972352
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_genbits.677059608
Short name T10
Test name
Test status
Simulation time 66674079 ps
CPU time 2.26 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 220560 kb
Host smart-821614cc-b351-447d-8f1b-90a6fb967e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677059608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.677059608
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1329798001
Short name T15
Test name
Test status
Simulation time 49346829 ps
CPU time 1.06 seconds
Started Jul 01 11:10:44 AM PDT 24
Finished Jul 01 11:10:46 AM PDT 24
Peak memory 224028 kb
Host smart-0e205b1a-ce6c-4a9d-bbc0-ce9d2a4e9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329798001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1329798001
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2876876218
Short name T20
Test name
Test status
Simulation time 953021001 ps
CPU time 7.78 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 236564 kb
Host smart-cfd9b420-c26a-4ab7-b657-d0be39025b4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876876218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2876876218
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/183.edn_alert.1625404746
Short name T32
Test name
Test status
Simulation time 24648161 ps
CPU time 1.14 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220072 kb
Host smart-4a6e544b-9fe1-4244-9231-ce53efc29058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625404746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1625404746
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2663989002
Short name T24
Test name
Test status
Simulation time 27191388 ps
CPU time 1.04 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 218576 kb
Host smart-67cfc87b-7f40-443b-bfb4-c960c77ded8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663989002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2663989002
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_intr.3984978918
Short name T5
Test name
Test status
Simulation time 27934843 ps
CPU time 1.01 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 215740 kb
Host smart-8ab335bd-8de9-4419-b1e8-c832ee0c89dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984978918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3984978918
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/106.edn_alert.3603083380
Short name T90
Test name
Test status
Simulation time 96881117 ps
CPU time 1.15 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 218764 kb
Host smart-ea2f921a-6c25-4ec0-8f03-78f792c3dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603083380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3603083380
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/89.edn_alert.1344485118
Short name T157
Test name
Test status
Simulation time 66200386 ps
CPU time 1.36 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 216008 kb
Host smart-a6af0a80-6794-459a-995c-742124403df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344485118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1344485118
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1866984571
Short name T49
Test name
Test status
Simulation time 30787054 ps
CPU time 0.87 seconds
Started Jul 01 11:09:38 AM PDT 24
Finished Jul 01 11:09:40 AM PDT 24
Peak memory 216476 kb
Host smart-1a6da588-0969-483a-a91c-243056921233
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866984571 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1866984571
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/82.edn_alert.301811889
Short name T85
Test name
Test status
Simulation time 135469577 ps
CPU time 1.11 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 221036 kb
Host smart-d1720fa5-450d-45b8-99b6-a5d85468373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301811889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.301811889
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.3648934004
Short name T29
Test name
Test status
Simulation time 17831973 ps
CPU time 1.02 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:35 AM PDT 24
Peak memory 207432 kb
Host smart-e128dc78-1232-4844-8da4-9adad4394c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648934004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3648934004
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1242630442
Short name T235
Test name
Test status
Simulation time 66885920396 ps
CPU time 410.14 seconds
Started Jul 01 11:09:25 AM PDT 24
Finished Jul 01 11:16:17 AM PDT 24
Peak memory 218476 kb
Host smart-67ad3e9d-241e-4017-beef-cc48ba1a2414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242630442 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1242630442
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3776727395
Short name T288
Test name
Test status
Simulation time 261842002 ps
CPU time 2.14 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 215044 kb
Host smart-efd9f827-5da2-42b9-ade1-175d33377fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776727395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3776727395
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/16.edn_disable.1893091683
Short name T214
Test name
Test status
Simulation time 10708947 ps
CPU time 0.84 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 216560 kb
Host smart-1af33a96-addd-473e-b664-a5cb3f24d602
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893091683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1893091683
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.2173958232
Short name T206
Test name
Test status
Simulation time 12276447 ps
CPU time 0.85 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 216708 kb
Host smart-4bec334c-af7b-4256-88ad-870fdbfc8e32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173958232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2173958232
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1046947295
Short name T156
Test name
Test status
Simulation time 117394388 ps
CPU time 1.07 seconds
Started Jul 01 11:09:59 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 217328 kb
Host smart-ed5ca8c0-15c4-4821-a4a2-3eae2d707efc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046947295 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1046947295
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3493911929
Short name T722
Test name
Test status
Simulation time 109685601 ps
CPU time 1.02 seconds
Started Jul 01 11:09:36 AM PDT 24
Finished Jul 01 11:09:40 AM PDT 24
Peak memory 217220 kb
Host smart-d3682dec-250a-4c72-acde-91f9da419197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493911929 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3493911929
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4138443554
Short name T267
Test name
Test status
Simulation time 17653552 ps
CPU time 0.98 seconds
Started Jul 01 10:45:16 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 206904 kb
Host smart-f0b8b341-dec2-40a0-9e82-87f0da124ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138443554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4138443554
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/default/149.edn_alert.1478416655
Short name T341
Test name
Test status
Simulation time 86513346 ps
CPU time 1.22 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 221184 kb
Host smart-c593313a-939c-4161-a1db-2951346b36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478416655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1478416655
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/56.edn_alert.300024159
Short name T959
Test name
Test status
Simulation time 134392451 ps
CPU time 1.29 seconds
Started Jul 01 11:10:41 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 218896 kb
Host smart-e5137616-53c1-4589-9bc9-a91d967e3de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300024159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.300024159
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.518292807
Short name T370
Test name
Test status
Simulation time 62507088 ps
CPU time 1.25 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 219264 kb
Host smart-4c215224-cca9-4ce3-ae05-bc8d6c95a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518292807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.518292807
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2806826998
Short name T326
Test name
Test status
Simulation time 42268388 ps
CPU time 1.45 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 218704 kb
Host smart-6ce72eb1-4d35-4ec2-b251-95aa607f8129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806826998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2806826998
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.908631994
Short name T122
Test name
Test status
Simulation time 250452372 ps
CPU time 1.26 seconds
Started Jul 01 11:10:53 AM PDT 24
Finished Jul 01 11:10:55 AM PDT 24
Peak memory 220792 kb
Host smart-21569d27-ac24-4a3b-b7b7-bc3de005e12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908631994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.908631994
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.349325722
Short name T495
Test name
Test status
Simulation time 26720664 ps
CPU time 1.18 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 221024 kb
Host smart-11bebb79-572b-47eb-8b4e-3052b6947fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349325722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.349325722
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.1636715630
Short name T737
Test name
Test status
Simulation time 72409974 ps
CPU time 1.16 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 220036 kb
Host smart-c8aca328-f1cd-4bf0-8955-1a8150f12dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636715630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1636715630
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.1377204221
Short name T405
Test name
Test status
Simulation time 41521516 ps
CPU time 1.13 seconds
Started Jul 01 11:11:24 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 219140 kb
Host smart-2c2bf7fa-e375-4b05-8292-3667322e7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377204221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1377204221
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3703058108
Short name T44
Test name
Test status
Simulation time 51189357 ps
CPU time 1.15 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 217184 kb
Host smart-7f8862b8-c57e-41c1-bff8-054ee5b96d26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703058108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3703058108
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_alert.3499577667
Short name T545
Test name
Test status
Simulation time 48392389 ps
CPU time 1.53 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 215968 kb
Host smart-3cf2a11d-d500-4fd9-a5f5-6b7ea93307ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499577667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3499577667
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.1808040363
Short name T109
Test name
Test status
Simulation time 86491651 ps
CPU time 1.17 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:03 AM PDT 24
Peak memory 221068 kb
Host smart-f9f77744-1034-4c5d-ba3f-20f5ed01d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808040363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1808040363
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/150.edn_alert.196078597
Short name T140
Test name
Test status
Simulation time 38540766 ps
CPU time 1.19 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 218908 kb
Host smart-60efc96c-a684-422c-ad35-0f427c3fba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196078597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.196078597
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/199.edn_alert.526211354
Short name T340
Test name
Test status
Simulation time 51711202 ps
CPU time 1.2 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 219904 kb
Host smart-a03fea7d-8585-40fa-a934-3da5f59c4aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526211354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.526211354
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/13.edn_intr.3200970889
Short name T33
Test name
Test status
Simulation time 22278023 ps
CPU time 1.07 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 216284 kb
Host smart-d1903186-f9c1-4242-9875-e22ffcf1cea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200970889 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3200970889
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/113.edn_genbits.1092916844
Short name T14
Test name
Test status
Simulation time 35289018 ps
CPU time 1.44 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 217756 kb
Host smart-eeb059ad-e0ca-4116-83c7-2324da2322f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092916844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1092916844
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3424420860
Short name T38
Test name
Test status
Simulation time 58447031 ps
CPU time 0.83 seconds
Started Jul 01 11:09:53 AM PDT 24
Finished Jul 01 11:09:54 AM PDT 24
Peak memory 215740 kb
Host smart-0dc1604a-a9f0-4e2c-a266-a8bb3f383fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424420860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3424420860
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/1.edn_err.1723488437
Short name T190
Test name
Test status
Simulation time 22476352 ps
CPU time 1.04 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 218984 kb
Host smart-b793e0a4-a783-45a5-9256-4af96737848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723488437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1723488437
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3404307453
Short name T144
Test name
Test status
Simulation time 164369307 ps
CPU time 0.99 seconds
Started Jul 01 11:09:48 AM PDT 24
Finished Jul 01 11:09:49 AM PDT 24
Peak memory 219920 kb
Host smart-f80493dd-7c3c-4032-b1c6-81cf2cc52227
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404307453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3404307453
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable.1682760963
Short name T87
Test name
Test status
Simulation time 22469771 ps
CPU time 0.92 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 216516 kb
Host smart-00b277d5-faa0-4fa3-833c-7c23325e51dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682760963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1682760963
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.3488550606
Short name T221
Test name
Test status
Simulation time 13773778 ps
CPU time 0.91 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 216936 kb
Host smart-32625bf8-392d-4dc2-9470-8fb8a221c767
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488550606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3488550606
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/134.edn_alert.1429056325
Short name T786
Test name
Test status
Simulation time 34188121 ps
CPU time 1.11 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 220124 kb
Host smart-061e179f-0deb-487d-a12a-a37462c7090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429056325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1429056325
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.2611272548
Short name T413
Test name
Test status
Simulation time 115897717 ps
CPU time 0.92 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:46 AM PDT 24
Peak memory 215628 kb
Host smart-9f259bc5-328c-4d21-b5ea-70340251df79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611272548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2611272548
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.1005451134
Short name T217
Test name
Test status
Simulation time 20669977 ps
CPU time 0.86 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 216496 kb
Host smart-68c2b4eb-1c54-45bb-8fa5-b764007371a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005451134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1005451134
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/196.edn_alert.1258968822
Short name T70
Test name
Test status
Simulation time 72153024 ps
CPU time 1.09 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 220632 kb
Host smart-cd24e1d3-2353-4fc0-b510-54f7efaa7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258968822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1258968822
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable.2112348316
Short name T209
Test name
Test status
Simulation time 21587716 ps
CPU time 0.85 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 216612 kb
Host smart-15115816-a7a2-4733-9b2c-6dcaa366b4e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112348316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2112348316
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1236061349
Short name T893
Test name
Test status
Simulation time 76753833 ps
CPU time 1.06 seconds
Started Jul 01 11:10:08 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 217224 kb
Host smart-12fceb17-67be-4589-9610-36f10d956160
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236061349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1236061349
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3136408163
Short name T202
Test name
Test status
Simulation time 24943972 ps
CPU time 1.05 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 229912 kb
Host smart-ee48e413-126d-41ef-83d8-c196ae17bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136408163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3136408163
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/30.edn_err.3613518772
Short name T198
Test name
Test status
Simulation time 28390894 ps
CPU time 0.87 seconds
Started Jul 01 11:10:12 AM PDT 24
Finished Jul 01 11:10:13 AM PDT 24
Peak memory 218504 kb
Host smart-0cd87c1b-00fc-4fac-98e1-9a5e019896e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613518772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3613518772
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/37.edn_disable.953199197
Short name T203
Test name
Test status
Simulation time 13133309 ps
CPU time 0.88 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 216840 kb
Host smart-56d29f6d-6acb-46d8-8d25-5234f1a900e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953199197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.953199197
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable.3317166907
Short name T194
Test name
Test status
Simulation time 18905288 ps
CPU time 0.87 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 216580 kb
Host smart-525a494e-75f2-4166-9abc-eea12b5bbce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317166907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3317166907
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1413967825
Short name T233
Test name
Test status
Simulation time 37475127482 ps
CPU time 514.91 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:18:45 AM PDT 24
Peak memory 224024 kb
Host smart-e4f8366f-b3ba-4dfe-b55f-98b40e7624f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413967825 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1413967825
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_genbits.719139358
Short name T353
Test name
Test status
Simulation time 55064040 ps
CPU time 1.3 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 220312 kb
Host smart-0ae769cf-8e50-42fe-bb5d-258a466a91a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719139358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.719139358
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1415149460
Short name T234
Test name
Test status
Simulation time 37804455463 ps
CPU time 390.7 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:17:00 AM PDT 24
Peak memory 217816 kb
Host smart-c508b074-76eb-4d8c-aa48-9dae9319b5dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415149460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1415149460
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert_test.2882286817
Short name T111
Test name
Test status
Simulation time 18265682 ps
CPU time 0.99 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 206968 kb
Host smart-de86e36d-5769-43dc-a730-963f6cf152ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882286817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2882286817
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/122.edn_alert.2584052118
Short name T50
Test name
Test status
Simulation time 157967860 ps
CPU time 1.12 seconds
Started Jul 01 11:11:22 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 219784 kb
Host smart-23986f39-7de9-4e2a-be6f-2e727c5e0943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584052118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2584052118
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.212288048
Short name T307
Test name
Test status
Simulation time 26532668 ps
CPU time 1.22 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:04 AM PDT 24
Peak memory 217524 kb
Host smart-c61b2f7a-a54a-4d8d-a312-5895f3edec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212288048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.212288048
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3053514339
Short name T320
Test name
Test status
Simulation time 304773735 ps
CPU time 3.3 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 220420 kb
Host smart-903bfc2a-ba3a-48ad-8e20-a19f1981fa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053514339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3053514339
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1727192034
Short name T291
Test name
Test status
Simulation time 29293772 ps
CPU time 1.38 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 218836 kb
Host smart-af30f771-41a2-4f46-bb3c-b104ed9f878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727192034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1727192034
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert.1482733026
Short name T165
Test name
Test status
Simulation time 42407964 ps
CPU time 1.15 seconds
Started Jul 01 11:10:00 AM PDT 24
Finished Jul 01 11:10:02 AM PDT 24
Peak memory 219940 kb
Host smart-ade4297d-6786-4431-904f-3dff5a67da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482733026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1482733026
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/10.edn_intr.3902782403
Short name T36
Test name
Test status
Simulation time 22949993 ps
CPU time 1.04 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:45 AM PDT 24
Peak memory 216160 kb
Host smart-6f00ed6e-6d4b-4894-a96e-08c8cc072d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902782403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3902782403
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2803819105
Short name T278
Test name
Test status
Simulation time 13494523 ps
CPU time 0.85 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 206904 kb
Host smart-2d651345-9083-4b0d-b78f-0cb6b0af787b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803819105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2803819105
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4174433433
Short name T300
Test name
Test status
Simulation time 253738798 ps
CPU time 2.28 seconds
Started Jul 01 10:45:02 AM PDT 24
Finished Jul 01 10:45:05 AM PDT 24
Peak memory 215180 kb
Host smart-5bb46092-1651-4ddd-9515-aaa559e2abf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174433433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4174433433
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/101.edn_genbits.3951295977
Short name T348
Test name
Test status
Simulation time 36454062 ps
CPU time 1.31 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 217616 kb
Host smart-43b4215e-8b8d-400f-9ba4-907ff520f34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951295977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3951295977
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.770487183
Short name T492
Test name
Test status
Simulation time 55507755 ps
CPU time 1.18 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:18 AM PDT 24
Peak memory 217708 kb
Host smart-009f4667-cebc-4b41-87bf-40d6b155b9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770487183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.770487183
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3526399230
Short name T304
Test name
Test status
Simulation time 245135136 ps
CPU time 2.86 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 218960 kb
Host smart-7b56970f-04ea-4c65-bf44-5a1fc5b2f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526399230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3526399230
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3259650844
Short name T323
Test name
Test status
Simulation time 38565472 ps
CPU time 1.6 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 218732 kb
Host smart-d625b340-d6d5-45a8-baa1-8ff9c29e788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259650844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3259650844
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.2033383550
Short name T328
Test name
Test status
Simulation time 35581630 ps
CPU time 1.19 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 218944 kb
Host smart-919741ec-1db4-404c-816c-46e77faf1ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033383550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2033383550
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1795068268
Short name T742
Test name
Test status
Simulation time 78233110 ps
CPU time 1.33 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 218900 kb
Host smart-602196fb-9d5c-4b2b-b7d9-e60a748339ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795068268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1795068268
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3938958676
Short name T325
Test name
Test status
Simulation time 70360542 ps
CPU time 1.12 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 220088 kb
Host smart-ee03bc7d-37e8-4961-a547-5d15d166b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938958676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3938958676
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.823601477
Short name T321
Test name
Test status
Simulation time 45263156 ps
CPU time 1.45 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 218704 kb
Host smart-dd58c4b3-fc88-4481-8bc4-7ce7ee3f5507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823601477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.823601477
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1184818125
Short name T319
Test name
Test status
Simulation time 41856040 ps
CPU time 1.51 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:38 AM PDT 24
Peak memory 218928 kb
Host smart-47be3a50-f848-4ae3-a927-5456fe13a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184818125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1184818125
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1986936044
Short name T101
Test name
Test status
Simulation time 21167936 ps
CPU time 1.11 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 216144 kb
Host smart-75231da7-b7e0-475f-9f74-e42f94d1cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986936044 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1986936044
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/123.edn_alert.2391245090
Short name T121
Test name
Test status
Simulation time 52163848 ps
CPU time 1.21 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 219048 kb
Host smart-142d546f-b7f2-4d86-aa50-5d8b282d137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391245090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2391245090
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/2.edn_err.3447377065
Short name T377
Test name
Test status
Simulation time 100590221 ps
CPU time 1.31 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:31 AM PDT 24
Peak memory 220052 kb
Host smart-5697cc3a-e02a-49e3-906d-859f22766c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447377065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3447377065
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1079437058
Short name T273
Test name
Test status
Simulation time 29545037 ps
CPU time 1.2 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:14 AM PDT 24
Peak memory 206988 kb
Host smart-b7f53c51-ab9b-4942-8122-951cf0061d08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079437058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1079437058
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4254210986
Short name T275
Test name
Test status
Simulation time 437541070 ps
CPU time 5.75 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:26 AM PDT 24
Peak memory 206960 kb
Host smart-fad1f8bc-286e-4dfb-9230-fff9afb2e5a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254210986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4254210986
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.177347916
Short name T1043
Test name
Test status
Simulation time 21142592 ps
CPU time 1.02 seconds
Started Jul 01 10:45:00 AM PDT 24
Finished Jul 01 10:45:02 AM PDT 24
Peak memory 206892 kb
Host smart-0c3ed884-7c0c-4980-89dc-5aa974694cd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177347916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.177347916
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2266876190
Short name T1098
Test name
Test status
Simulation time 29569085 ps
CPU time 1.95 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 215164 kb
Host smart-977fbe3d-433a-4496-a267-10e340d34750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266876190 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2266876190
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2574648613
Short name T1109
Test name
Test status
Simulation time 55983499 ps
CPU time 0.84 seconds
Started Jul 01 10:45:08 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 206740 kb
Host smart-ca75b5bb-3d5b-4a23-9bf1-09eead7b86bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574648613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2574648613
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1519785041
Short name T1129
Test name
Test status
Simulation time 119816287 ps
CPU time 0.94 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:14 AM PDT 24
Peak memory 206812 kb
Host smart-24214ec3-c3d7-40db-b255-ad7794b13490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519785041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1519785041
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.404919378
Short name T1113
Test name
Test status
Simulation time 43443118 ps
CPU time 1.02 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206872 kb
Host smart-dbaf216a-2cb2-491a-bea4-ce153c8f81c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404919378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.404919378
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3720732966
Short name T1051
Test name
Test status
Simulation time 169289883 ps
CPU time 3.12 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 223376 kb
Host smart-0b0c902c-e055-4552-99f3-69ffc883867b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720732966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3720732966
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2142448723
Short name T271
Test name
Test status
Simulation time 33763201 ps
CPU time 1.19 seconds
Started Jul 01 10:45:11 AM PDT 24
Finished Jul 01 10:45:12 AM PDT 24
Peak memory 206972 kb
Host smart-ba15db98-9994-42ed-8317-d550d79e68ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142448723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2142448723
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2831236374
Short name T1100
Test name
Test status
Simulation time 517801811 ps
CPU time 6.86 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:37 AM PDT 24
Peak memory 206896 kb
Host smart-c5445bee-96ee-41e4-94e5-b188f466bf62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831236374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2831236374
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2359964520
Short name T272
Test name
Test status
Simulation time 23725806 ps
CPU time 0.88 seconds
Started Jul 01 10:45:11 AM PDT 24
Finished Jul 01 10:45:12 AM PDT 24
Peak memory 206912 kb
Host smart-1b2efe95-6020-492e-a6f4-07e2b55caf79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359964520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2359964520
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2338887030
Short name T1062
Test name
Test status
Simulation time 59965357 ps
CPU time 1.11 seconds
Started Jul 01 10:44:59 AM PDT 24
Finished Jul 01 10:45:01 AM PDT 24
Peak memory 215224 kb
Host smart-0fbbec44-296b-4509-b814-88f3e0f9d132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338887030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2338887030
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.315514431
Short name T1107
Test name
Test status
Simulation time 23899204 ps
CPU time 0.93 seconds
Started Jul 01 10:45:06 AM PDT 24
Finished Jul 01 10:45:07 AM PDT 24
Peak memory 206868 kb
Host smart-52dbac19-61ff-4a5c-ba7a-2987f2c49bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315514431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.315514431
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.4090325380
Short name T1112
Test name
Test status
Simulation time 25713545 ps
CPU time 0.9 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 206884 kb
Host smart-35f4faee-213b-4238-b2bc-70fa3e2585d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090325380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4090325380
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.586992907
Short name T1061
Test name
Test status
Simulation time 69988445 ps
CPU time 0.93 seconds
Started Jul 01 10:45:08 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 206940 kb
Host smart-2a5d386d-998c-4db9-9be3-b3ce45676d2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586992907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.586992907
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.976375798
Short name T1049
Test name
Test status
Simulation time 193093876 ps
CPU time 2.19 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:15 AM PDT 24
Peak memory 215212 kb
Host smart-abb344c6-9dc7-4482-8baf-2b8741c2bc0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976375798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.976375798
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2230875265
Short name T1105
Test name
Test status
Simulation time 130993214 ps
CPU time 2.99 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:33 AM PDT 24
Peak memory 215124 kb
Host smart-c2288ee6-8867-4a3f-bc69-be678d7335da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230875265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2230875265
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1020866369
Short name T1059
Test name
Test status
Simulation time 107145080 ps
CPU time 1.48 seconds
Started Jul 01 10:45:11 AM PDT 24
Finished Jul 01 10:45:13 AM PDT 24
Peak memory 215116 kb
Host smart-83f207b0-0397-4b27-87a9-55ca0edf96d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020866369 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1020866369
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1659712156
Short name T1127
Test name
Test status
Simulation time 13782451 ps
CPU time 0.93 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 206824 kb
Host smart-0e4f0206-e06a-4755-94fe-c5b0d40f5f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659712156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1659712156
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1423902352
Short name T1040
Test name
Test status
Simulation time 40310997 ps
CPU time 0.8 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206632 kb
Host smart-57b80278-8a2d-4c9f-856d-d62020fe16df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423902352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1423902352
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2681968549
Short name T1029
Test name
Test status
Simulation time 301660383 ps
CPU time 1.38 seconds
Started Jul 01 10:45:11 AM PDT 24
Finished Jul 01 10:45:13 AM PDT 24
Peak memory 206864 kb
Host smart-dd68389f-e3c9-4544-9901-ea17aa80bf3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681968549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2681968549
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3055333553
Short name T1031
Test name
Test status
Simulation time 50206597 ps
CPU time 1.82 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 223412 kb
Host smart-6d83d28f-9dcf-4ae9-9106-03443268b34a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055333553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3055333553
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4181230854
Short name T1057
Test name
Test status
Simulation time 68664700 ps
CPU time 1.92 seconds
Started Jul 01 10:45:10 AM PDT 24
Finished Jul 01 10:45:12 AM PDT 24
Peak memory 207116 kb
Host smart-4a65fc80-58b4-4cc3-a0bf-58ad6abbedb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181230854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4181230854
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1982471588
Short name T1075
Test name
Test status
Simulation time 90227480 ps
CPU time 1.55 seconds
Started Jul 01 10:45:18 AM PDT 24
Finished Jul 01 10:45:19 AM PDT 24
Peak memory 219000 kb
Host smart-e58a0695-a7fd-47ff-b82f-6e4343c1a537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982471588 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1982471588
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.340691776
Short name T1053
Test name
Test status
Simulation time 34526220 ps
CPU time 0.81 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 206744 kb
Host smart-04e675a0-d20b-4a95-a273-6441b63dcf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340691776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.340691776
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2574258045
Short name T1068
Test name
Test status
Simulation time 34724047 ps
CPU time 0.86 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206688 kb
Host smart-12e5a005-fdfb-4bbb-b8c2-afb39b0686b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574258045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2574258045
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3887523738
Short name T1070
Test name
Test status
Simulation time 13441849 ps
CPU time 0.95 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 207000 kb
Host smart-72cf3601-36ef-47c9-b2b2-c84d3c35387c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887523738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3887523738
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.481995414
Short name T1118
Test name
Test status
Simulation time 31080795 ps
CPU time 2.14 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 223380 kb
Host smart-c7fb47ab-6de3-46b5-a359-bc0752648f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481995414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.481995414
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2982022745
Short name T289
Test name
Test status
Simulation time 183265298 ps
CPU time 1.56 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 215152 kb
Host smart-e691ef9c-f760-4c78-820e-94f48519dfbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982022745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2982022745
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1009160783
Short name T1016
Test name
Test status
Simulation time 14471390 ps
CPU time 0.91 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 206904 kb
Host smart-a7ab9d00-d6a8-4fbc-af89-3f1591ad09ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009160783 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1009160783
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.98260606
Short name T1099
Test name
Test status
Simulation time 89991764 ps
CPU time 0.87 seconds
Started Jul 01 10:45:17 AM PDT 24
Finished Jul 01 10:45:18 AM PDT 24
Peak memory 206724 kb
Host smart-c3728ffa-c01e-4b67-b375-5f056abb9fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98260606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.98260606
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4014544234
Short name T285
Test name
Test status
Simulation time 42791907 ps
CPU time 1.11 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 206952 kb
Host smart-b5ea52b1-f420-453f-95cc-322db9fdc5ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014544234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4014544234
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3893203937
Short name T1011
Test name
Test status
Simulation time 116354400 ps
CPU time 3.89 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215216 kb
Host smart-02150421-9fc8-476c-a6d9-53224b124535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893203937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3893203937
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2947033344
Short name T1048
Test name
Test status
Simulation time 65223877 ps
CPU time 1.84 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 207176 kb
Host smart-731ded63-f386-4a9a-aa4d-1b3e9e9aedd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947033344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2947033344
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3953252823
Short name T1128
Test name
Test status
Simulation time 158888735 ps
CPU time 1.7 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 215220 kb
Host smart-b61fa167-b5d0-419d-b99f-8488ed22ed43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953252823 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3953252823
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2519409123
Short name T996
Test name
Test status
Simulation time 16189555 ps
CPU time 1 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 206896 kb
Host smart-77f92c95-6673-4aff-92c6-709742f874dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519409123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2519409123
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2341193435
Short name T1018
Test name
Test status
Simulation time 17185663 ps
CPU time 0.89 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 206856 kb
Host smart-b1fa6f32-7137-4c9e-b737-89a677009960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341193435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2341193435
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2509058161
Short name T280
Test name
Test status
Simulation time 35378053 ps
CPU time 1.03 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 206988 kb
Host smart-e76c6de4-fc53-4418-85ef-43c99ed6d25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509058161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2509058161
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2269517470
Short name T999
Test name
Test status
Simulation time 92548592 ps
CPU time 2.74 seconds
Started Jul 01 10:45:14 AM PDT 24
Finished Jul 01 10:45:18 AM PDT 24
Peak memory 215248 kb
Host smart-793b8be3-6375-429b-8585-5353a2c40389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269517470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2269517470
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1182541286
Short name T1012
Test name
Test status
Simulation time 57533332 ps
CPU time 1.67 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:44 AM PDT 24
Peak memory 215396 kb
Host smart-b7e133c8-5a31-4bc8-8746-015ad05bac9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182541286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1182541286
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2760915340
Short name T1009
Test name
Test status
Simulation time 21485471 ps
CPU time 1.48 seconds
Started Jul 01 10:45:36 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 219308 kb
Host smart-69c73367-25ac-4206-ba48-620cc3a5985c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760915340 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2760915340
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.589694447
Short name T1080
Test name
Test status
Simulation time 35349650 ps
CPU time 0.86 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:13 AM PDT 24
Peak memory 206692 kb
Host smart-06fc4710-7bee-4a0d-840d-9a3e9ec673ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589694447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.589694447
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.688164883
Short name T1013
Test name
Test status
Simulation time 36801124 ps
CPU time 0.81 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 206812 kb
Host smart-ea0fc811-ae1c-4b03-b587-ba12ad0331be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688164883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.688164883
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.780059398
Short name T1117
Test name
Test status
Simulation time 20472458 ps
CPU time 1.09 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:30 AM PDT 24
Peak memory 206952 kb
Host smart-fcd56df7-ba0f-4bff-ae8f-134abc6e0973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780059398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.780059398
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4001040250
Short name T1042
Test name
Test status
Simulation time 176015004 ps
CPU time 1.95 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 215136 kb
Host smart-0682f4fc-e8dd-4217-8792-548bc4accd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001040250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4001040250
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.223619639
Short name T1010
Test name
Test status
Simulation time 70953202 ps
CPU time 2.06 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 207140 kb
Host smart-60708413-ebfe-4520-966d-f4a56a3442ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223619639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.223619639
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3307809380
Short name T1052
Test name
Test status
Simulation time 89337668 ps
CPU time 1.11 seconds
Started Jul 01 10:45:16 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 216968 kb
Host smart-9eff4ca4-b530-4f59-a73f-0d96a7754458
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307809380 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3307809380
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1901244052
Short name T1090
Test name
Test status
Simulation time 80802855 ps
CPU time 0.87 seconds
Started Jul 01 10:45:45 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 206896 kb
Host smart-34bcee7c-7fd4-4525-b641-0e83c04dcc0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901244052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1901244052
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1006252988
Short name T1021
Test name
Test status
Simulation time 16580649 ps
CPU time 0.94 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 206816 kb
Host smart-df49c484-fc35-4653-8502-9917c1dc0b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006252988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1006252988
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.655080476
Short name T1058
Test name
Test status
Simulation time 55555517 ps
CPU time 1.29 seconds
Started Jul 01 10:45:14 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 206900 kb
Host smart-93e30cb6-d2b0-49e3-a549-0908a1315802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655080476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.655080476
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1153504124
Short name T1122
Test name
Test status
Simulation time 73539575 ps
CPU time 2.61 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:44 AM PDT 24
Peak memory 215188 kb
Host smart-2c6d45c0-1f35-4adb-baff-b6ad8da87c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153504124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1153504124
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3453516712
Short name T1039
Test name
Test status
Simulation time 55207391 ps
CPU time 1.08 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 215268 kb
Host smart-de30b669-81ef-4242-b650-249087b63403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453516712 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3453516712
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.68466743
Short name T1083
Test name
Test status
Simulation time 27927800 ps
CPU time 0.84 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 206936 kb
Host smart-52e38680-17dc-4cd4-9d71-348878383a20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68466743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.68466743
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.627807475
Short name T1101
Test name
Test status
Simulation time 42146065 ps
CPU time 0.83 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 206812 kb
Host smart-b21a302e-db4d-4659-a20a-ef6c7c8f6ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627807475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.627807475
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3200983033
Short name T281
Test name
Test status
Simulation time 31457716 ps
CPU time 1.03 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 206952 kb
Host smart-aa7cdf71-aabb-4dec-9ca7-220344155fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200983033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3200983033
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1217163972
Short name T1041
Test name
Test status
Simulation time 196092980 ps
CPU time 2.01 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:45 AM PDT 24
Peak memory 215316 kb
Host smart-e3ee7bd6-890b-451b-9cef-49efb8c4518d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217163972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1217163972
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2147688255
Short name T1089
Test name
Test status
Simulation time 219953124 ps
CPU time 1.47 seconds
Started Jul 01 10:45:30 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 206992 kb
Host smart-5216d510-4341-478f-b70b-1841cede4e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147688255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2147688255
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2684322664
Short name T1034
Test name
Test status
Simulation time 169195677 ps
CPU time 1.28 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215236 kb
Host smart-967f9c8e-6aed-4ccc-b523-4f81c729524b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684322664 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2684322664
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2536318998
Short name T1081
Test name
Test status
Simulation time 28432166 ps
CPU time 0.88 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 206920 kb
Host smart-6dffa998-8f6e-4400-97a9-a023675276f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536318998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2536318998
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1121397764
Short name T1045
Test name
Test status
Simulation time 12752400 ps
CPU time 0.88 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 206876 kb
Host smart-842cb1f2-c574-4fd4-a258-36a0a4a5b47d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121397764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1121397764
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3935386747
Short name T1078
Test name
Test status
Simulation time 41256828 ps
CPU time 1.35 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:14 AM PDT 24
Peak memory 206860 kb
Host smart-a15514cb-8b0b-4c43-add3-e7bca13dccbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935386747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3935386747
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3999920158
Short name T1028
Test name
Test status
Simulation time 164321786 ps
CPU time 1.82 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:14 AM PDT 24
Peak memory 215216 kb
Host smart-64a99b1f-c371-49e1-9ec1-c50feb368bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999920158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3999920158
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1590282506
Short name T297
Test name
Test status
Simulation time 189340992 ps
CPU time 2.61 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 206940 kb
Host smart-466c0b93-2dfd-48bd-b439-d773bf072fee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590282506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1590282506
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.625273961
Short name T1007
Test name
Test status
Simulation time 81046501 ps
CPU time 1.5 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215168 kb
Host smart-c5c91c60-e13e-4e92-b369-d37d4feeb2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625273961 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.625273961
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1180951977
Short name T282
Test name
Test status
Simulation time 23252673 ps
CPU time 0.86 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 206896 kb
Host smart-0d31e4fb-7540-4c5f-a48d-4c466cd4a613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180951977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1180951977
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1905002248
Short name T1008
Test name
Test status
Simulation time 42626504 ps
CPU time 0.87 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 206900 kb
Host smart-f0d86427-8aa0-405a-9e33-15339928484b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905002248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1905002248
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4162897983
Short name T1095
Test name
Test status
Simulation time 62427844 ps
CPU time 1.27 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 206860 kb
Host smart-432a884a-fa01-4fc7-8b2d-55d9b7cc91c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162897983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4162897983
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.677258674
Short name T1106
Test name
Test status
Simulation time 85095215 ps
CPU time 2.42 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 215140 kb
Host smart-a95da507-0cb0-42bf-b752-1c219052f33b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677258674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.677258674
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2185805080
Short name T290
Test name
Test status
Simulation time 96228120 ps
CPU time 2.58 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 206880 kb
Host smart-f3525a6c-0e03-4fcd-83ed-5b1a1db78b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185805080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2185805080
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3765207036
Short name T1003
Test name
Test status
Simulation time 127397064 ps
CPU time 1.55 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215400 kb
Host smart-f09b6ce0-710f-4ac8-848a-8ee076abe324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765207036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3765207036
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.566807278
Short name T1111
Test name
Test status
Simulation time 38624815 ps
CPU time 0.78 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 206672 kb
Host smart-f5d05d98-e8cc-4a46-ac8f-8add96d9550e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566807278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.566807278
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4217396515
Short name T1046
Test name
Test status
Simulation time 81085578 ps
CPU time 0.79 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 206852 kb
Host smart-ac05d0ef-348b-4448-bd26-98670747974c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217396515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4217396515
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3485393956
Short name T1060
Test name
Test status
Simulation time 28424121 ps
CPU time 1.05 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:24 AM PDT 24
Peak memory 206856 kb
Host smart-b8b0b1c5-4187-4e23-944a-a6db8e674469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485393956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3485393956
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2273827813
Short name T1072
Test name
Test status
Simulation time 60965612 ps
CPU time 2.48 seconds
Started Jul 01 10:45:33 AM PDT 24
Finished Jul 01 10:45:36 AM PDT 24
Peak memory 215172 kb
Host smart-33c91757-dcfd-4c98-9043-ed5fbfbc513e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273827813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2273827813
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3099576601
Short name T1005
Test name
Test status
Simulation time 336457337 ps
CPU time 2.23 seconds
Started Jul 01 10:45:25 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206900 kb
Host smart-ac605d27-fe62-458c-8c17-81f2ff04d8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099576601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3099576601
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.519812586
Short name T1036
Test name
Test status
Simulation time 205235131 ps
CPU time 1.13 seconds
Started Jul 01 10:45:12 AM PDT 24
Finished Jul 01 10:45:19 AM PDT 24
Peak memory 206796 kb
Host smart-f22ac901-3698-495f-a3fd-dbd40641a043
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519812586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.519812586
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3495175216
Short name T270
Test name
Test status
Simulation time 1992247102 ps
CPU time 5.74 seconds
Started Jul 01 10:45:20 AM PDT 24
Finished Jul 01 10:45:27 AM PDT 24
Peak memory 207036 kb
Host smart-c2fdd9b5-ad2d-430b-9560-457e066fa461
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495175216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3495175216
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3314691638
Short name T1023
Test name
Test status
Simulation time 34514931 ps
CPU time 0.99 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206904 kb
Host smart-8903529d-3961-4475-bfd7-261ef16170fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314691638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3314691638
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.239582287
Short name T1102
Test name
Test status
Simulation time 47792232 ps
CPU time 1.36 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 223332 kb
Host smart-90e1ee7c-c05a-416b-91ad-5abb13ec2705
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239582287 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.239582287
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2746994203
Short name T1017
Test name
Test status
Simulation time 31519582 ps
CPU time 0.89 seconds
Started Jul 01 10:45:25 AM PDT 24
Finished Jul 01 10:45:26 AM PDT 24
Peak memory 206936 kb
Host smart-c8df3432-a3c5-45ef-83a7-40ddc33492ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746994203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2746994203
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.359403716
Short name T1056
Test name
Test status
Simulation time 13329825 ps
CPU time 0.85 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:30 AM PDT 24
Peak memory 206736 kb
Host smart-3d6af615-4949-4370-8f98-b95505d015cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359403716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.359403716
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1137888587
Short name T1123
Test name
Test status
Simulation time 14048979 ps
CPU time 1.04 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 207000 kb
Host smart-f45c9a92-e743-4110-9855-ab11625f1730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137888587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1137888587
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2064345666
Short name T1020
Test name
Test status
Simulation time 871713117 ps
CPU time 3.42 seconds
Started Jul 01 10:45:31 AM PDT 24
Finished Jul 01 10:45:35 AM PDT 24
Peak memory 215064 kb
Host smart-c8d6c0e0-5d9c-44d0-9ba9-39d5da9dedaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064345666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2064345666
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.383952325
Short name T1015
Test name
Test status
Simulation time 182306753 ps
CPU time 1.39 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:26 AM PDT 24
Peak memory 206936 kb
Host smart-88b5f317-18dd-49a7-89d3-5fa066ca26c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383952325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.383952325
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3894407541
Short name T1110
Test name
Test status
Simulation time 27852168 ps
CPU time 0.86 seconds
Started Jul 01 10:45:27 AM PDT 24
Finished Jul 01 10:45:29 AM PDT 24
Peak memory 206664 kb
Host smart-d77f3b65-7f76-47e4-ae58-84dcf2d91155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894407541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3894407541
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.293899192
Short name T1001
Test name
Test status
Simulation time 12247665 ps
CPU time 0.84 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 206832 kb
Host smart-a3c3e96f-f323-4053-a7e2-8dcb54353902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293899192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.293899192
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1600501995
Short name T1087
Test name
Test status
Simulation time 27102509 ps
CPU time 0.93 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 206904 kb
Host smart-e67cfa95-3b99-4a25-9e24-1ae7834cf621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600501995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1600501995
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3236578467
Short name T1065
Test name
Test status
Simulation time 14889665 ps
CPU time 0.96 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 206872 kb
Host smart-9dc1b33d-1264-4831-bd7b-6f6fb2085e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236578467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3236578467
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2112467292
Short name T1006
Test name
Test status
Simulation time 11566017 ps
CPU time 0.85 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 206832 kb
Host smart-28cb5e4a-b727-4108-9cc8-623c9761b8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112467292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2112467292
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2010416393
Short name T1002
Test name
Test status
Simulation time 21812821 ps
CPU time 0.86 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 206856 kb
Host smart-f286b45e-ce19-44e6-87d6-3d5def8bd991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010416393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2010416393
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.42025441
Short name T1088
Test name
Test status
Simulation time 14615282 ps
CPU time 0.93 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 206940 kb
Host smart-c2d46862-b275-448e-a311-61f54111e171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42025441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.42025441
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1514418115
Short name T1097
Test name
Test status
Simulation time 16962663 ps
CPU time 0.84 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 206848 kb
Host smart-b9a4884f-c966-472e-93f1-8241b8b87107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514418115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1514418115
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2563835357
Short name T1116
Test name
Test status
Simulation time 15072069 ps
CPU time 0.92 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 206752 kb
Host smart-a1d091ae-bb37-40b4-bc1f-ca27d0aca737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563835357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2563835357
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2789597597
Short name T1086
Test name
Test status
Simulation time 54902593 ps
CPU time 0.91 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 206852 kb
Host smart-87ffc8a0-7f1a-495b-afce-f2d108c2a251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789597597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2789597597
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3380513029
Short name T268
Test name
Test status
Simulation time 75188589 ps
CPU time 1.61 seconds
Started Jul 01 10:45:07 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 206968 kb
Host smart-b9355750-0106-4bca-a265-574d63f64787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380513029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3380513029
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2305290398
Short name T276
Test name
Test status
Simulation time 4159845028 ps
CPU time 8.32 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:27 AM PDT 24
Peak memory 207016 kb
Host smart-cf1c91bc-cb9d-4f2d-8000-64cf9bbee4bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305290398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2305290398
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4012293683
Short name T1024
Test name
Test status
Simulation time 22550556 ps
CPU time 0.99 seconds
Started Jul 01 10:45:17 AM PDT 24
Finished Jul 01 10:45:19 AM PDT 24
Peak memory 206928 kb
Host smart-27eabeaa-b7af-4809-916e-52617dc6a8d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012293683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4012293683
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2811389951
Short name T1120
Test name
Test status
Simulation time 112903740 ps
CPU time 2.09 seconds
Started Jul 01 10:45:28 AM PDT 24
Finished Jul 01 10:45:30 AM PDT 24
Peak memory 215188 kb
Host smart-79d47df8-f72a-4ad5-9c06-8c3bd6f7b306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811389951 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2811389951
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1437163136
Short name T1071
Test name
Test status
Simulation time 66765089 ps
CPU time 0.92 seconds
Started Jul 01 10:45:10 AM PDT 24
Finished Jul 01 10:45:11 AM PDT 24
Peak memory 206904 kb
Host smart-eb8deb3d-0a7f-4189-aca6-c0f4ea7c5919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437163136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1437163136
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.872668441
Short name T1044
Test name
Test status
Simulation time 40780704 ps
CPU time 0.9 seconds
Started Jul 01 10:45:22 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 206808 kb
Host smart-f0623f97-dce6-49ce-ac3f-f164fa87b2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872668441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.872668441
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1160093757
Short name T1055
Test name
Test status
Simulation time 82100140 ps
CPU time 1.09 seconds
Started Jul 01 10:45:02 AM PDT 24
Finished Jul 01 10:45:03 AM PDT 24
Peak memory 207012 kb
Host smart-8bd35504-034d-402f-a4ce-1e2c43a02edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160093757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1160093757
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.688073873
Short name T1079
Test name
Test status
Simulation time 54007235 ps
CPU time 2 seconds
Started Jul 01 10:45:02 AM PDT 24
Finished Jul 01 10:45:04 AM PDT 24
Peak memory 215396 kb
Host smart-8f6b0f2f-5f09-46ce-b0a4-e41639f72b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688073873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.688073873
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1754093327
Short name T1108
Test name
Test status
Simulation time 369998833 ps
CPU time 1.51 seconds
Started Jul 01 10:45:00 AM PDT 24
Finished Jul 01 10:45:02 AM PDT 24
Peak memory 215132 kb
Host smart-882b2223-7c9f-4bb4-80d4-2f0dc3f53c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754093327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1754093327
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1877176594
Short name T1064
Test name
Test status
Simulation time 24577567 ps
CPU time 0.88 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:30 AM PDT 24
Peak memory 206840 kb
Host smart-14467d73-bc17-49f6-b3b7-bceb2d441d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877176594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1877176594
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2042142887
Short name T1094
Test name
Test status
Simulation time 17156417 ps
CPU time 0.98 seconds
Started Jul 01 10:45:24 AM PDT 24
Finished Jul 01 10:45:26 AM PDT 24
Peak memory 206800 kb
Host smart-dc7b9b09-e339-4f13-95f7-243abbd717b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042142887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2042142887
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1141373118
Short name T1085
Test name
Test status
Simulation time 23850110 ps
CPU time 0.84 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 206616 kb
Host smart-0302ea8a-192b-4a2d-9a2e-44256fa391ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141373118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1141373118
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2150839740
Short name T1022
Test name
Test status
Simulation time 59224473 ps
CPU time 0.84 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 206876 kb
Host smart-bbf7a361-afad-4636-a3ed-61e2996ecc75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150839740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2150839740
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.68195373
Short name T1027
Test name
Test status
Simulation time 14926987 ps
CPU time 0.94 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 206872 kb
Host smart-0e7e1549-9f1f-4786-a24f-3341ba604258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68195373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.68195373
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.825003350
Short name T1124
Test name
Test status
Simulation time 16794870 ps
CPU time 0.93 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206812 kb
Host smart-df0ae627-a779-4fe4-83b2-63daf21fbfb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825003350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.825003350
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3124372830
Short name T1063
Test name
Test status
Simulation time 25650027 ps
CPU time 0.9 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 206876 kb
Host smart-831bb9ca-e37c-491b-a9df-fea64781ace1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124372830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3124372830
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4155040210
Short name T1091
Test name
Test status
Simulation time 65715859 ps
CPU time 0.86 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 206888 kb
Host smart-23e11609-aece-4723-8b74-ea70f20eb9d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155040210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4155040210
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.604531262
Short name T1126
Test name
Test status
Simulation time 50090831 ps
CPU time 0.85 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 206764 kb
Host smart-d256aef5-5d2b-480d-a774-98a014ae397f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604531262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.604531262
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.994462935
Short name T1073
Test name
Test status
Simulation time 25692835 ps
CPU time 0.84 seconds
Started Jul 01 10:45:17 AM PDT 24
Finished Jul 01 10:45:18 AM PDT 24
Peak memory 206832 kb
Host smart-10a9b3aa-6a53-49ed-a803-56a51c1a06b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994462935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.994462935
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.872141405
Short name T265
Test name
Test status
Simulation time 60293162 ps
CPU time 1.31 seconds
Started Jul 01 10:45:01 AM PDT 24
Finished Jul 01 10:45:02 AM PDT 24
Peak memory 206908 kb
Host smart-43690121-8b24-453f-9994-4f415dbdbde0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872141405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.872141405
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.742110776
Short name T274
Test name
Test status
Simulation time 258256137 ps
CPU time 3.83 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:20 AM PDT 24
Peak memory 206864 kb
Host smart-0c076aa0-73a0-47d3-86a8-bb3853236e59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742110776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.742110776
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4065568453
Short name T1014
Test name
Test status
Simulation time 42563470 ps
CPU time 0.83 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:20 AM PDT 24
Peak memory 206672 kb
Host smart-7b452d70-b93d-4213-98cf-5438126bb163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065568453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4065568453
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1178180017
Short name T1103
Test name
Test status
Simulation time 28786380 ps
CPU time 1.09 seconds
Started Jul 01 10:45:34 AM PDT 24
Finished Jul 01 10:45:36 AM PDT 24
Peak memory 215228 kb
Host smart-76dee70a-e46c-4bbd-a806-1c48cc8fa5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178180017 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1178180017
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2788175822
Short name T269
Test name
Test status
Simulation time 55833811 ps
CPU time 0.96 seconds
Started Jul 01 10:45:24 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206920 kb
Host smart-84184026-608e-461d-807a-0ba473639e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788175822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2788175822
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.204247230
Short name T1019
Test name
Test status
Simulation time 10697039 ps
CPU time 0.81 seconds
Started Jul 01 10:45:09 AM PDT 24
Finished Jul 01 10:45:10 AM PDT 24
Peak memory 206832 kb
Host smart-96ea2dd3-0fdb-4278-9a61-4957b5822ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204247230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.204247230
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1366277417
Short name T284
Test name
Test status
Simulation time 34812284 ps
CPU time 1.48 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206928 kb
Host smart-67df57ad-a9d7-4ba5-8f96-c90effd6d511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366277417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1366277417
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1660294646
Short name T1074
Test name
Test status
Simulation time 251736622 ps
CPU time 2.66 seconds
Started Jul 01 10:45:18 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 215172 kb
Host smart-4c84a48b-4a1c-40ad-bea1-f34fe702e383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660294646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1660294646
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.945779737
Short name T296
Test name
Test status
Simulation time 176269867 ps
CPU time 1.71 seconds
Started Jul 01 10:45:20 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 206872 kb
Host smart-7c24b910-3e4d-422b-8585-897e0090329d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945779737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.945779737
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2914500461
Short name T1000
Test name
Test status
Simulation time 23611699 ps
CPU time 0.85 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:24 AM PDT 24
Peak memory 206836 kb
Host smart-830a5b34-6044-4ff7-a033-2c24b826031c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914500461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2914500461
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3162842635
Short name T1076
Test name
Test status
Simulation time 72370659 ps
CPU time 0.9 seconds
Started Jul 01 10:45:34 AM PDT 24
Finished Jul 01 10:45:36 AM PDT 24
Peak memory 206852 kb
Host smart-8abc085c-d663-45ca-8542-d06dd0f4b7ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162842635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3162842635
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1970983502
Short name T1115
Test name
Test status
Simulation time 31498989 ps
CPU time 0.85 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 206860 kb
Host smart-b0c39c4f-e4eb-469f-988a-d4ebe6488348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970983502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1970983502
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2693625554
Short name T1077
Test name
Test status
Simulation time 48532868 ps
CPU time 0.79 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 206680 kb
Host smart-30718057-5cbf-426d-8d80-22cdc3ac0c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693625554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2693625554
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3967561432
Short name T995
Test name
Test status
Simulation time 28202998 ps
CPU time 0.8 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206696 kb
Host smart-e9926887-6c3c-4d33-b92c-21903f9846e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967561432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3967561432
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3314958477
Short name T1092
Test name
Test status
Simulation time 57516277 ps
CPU time 0.88 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:25 AM PDT 24
Peak memory 206724 kb
Host smart-8ed16905-de88-4fdb-924a-5392d323c534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314958477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3314958477
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2738410142
Short name T1037
Test name
Test status
Simulation time 15499039 ps
CPU time 0.85 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 206908 kb
Host smart-c067db7c-3715-46a0-bc63-48231be38453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738410142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2738410142
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.768922803
Short name T1004
Test name
Test status
Simulation time 43921542 ps
CPU time 0.81 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 206864 kb
Host smart-130ae08e-d13e-4d9e-995c-e67fa8b94058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768922803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.768922803
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2007106264
Short name T1035
Test name
Test status
Simulation time 13206006 ps
CPU time 0.86 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 206836 kb
Host smart-6f8555cb-4fb8-4812-a7d0-266d11d022ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007106264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2007106264
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1179577276
Short name T1032
Test name
Test status
Simulation time 23064791 ps
CPU time 0.87 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 206880 kb
Host smart-cee60f96-b560-4ca7-9ea2-a41e5916f920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179577276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1179577276
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1824209189
Short name T997
Test name
Test status
Simulation time 86227228 ps
CPU time 1.23 seconds
Started Jul 01 10:45:15 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 223220 kb
Host smart-c2c85210-1d6e-42ff-b751-56cb8a3422ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824209189 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1824209189
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1933604162
Short name T1082
Test name
Test status
Simulation time 42800974 ps
CPU time 0.84 seconds
Started Jul 01 10:45:17 AM PDT 24
Finished Jul 01 10:45:18 AM PDT 24
Peak memory 206856 kb
Host smart-523f2be9-3cbe-45d9-bbe2-e5753bd30f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933604162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1933604162
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1029070313
Short name T279
Test name
Test status
Simulation time 131805919 ps
CPU time 1.14 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206940 kb
Host smart-573e6d66-ccf0-4638-ba69-a9095459ade7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029070313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1029070313
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2173260266
Short name T1093
Test name
Test status
Simulation time 84993105 ps
CPU time 3.02 seconds
Started Jul 01 10:45:18 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 215320 kb
Host smart-1f3439b5-9466-4b92-ae80-21f3ba80ea45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173260266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2173260266
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4012808857
Short name T299
Test name
Test status
Simulation time 138251691 ps
CPU time 3.05 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 207196 kb
Host smart-b27c1bcf-b954-4b81-9eef-e058f6f64fce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012808857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4012808857
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1402564832
Short name T1047
Test name
Test status
Simulation time 46670042 ps
CPU time 0.92 seconds
Started Jul 01 10:45:28 AM PDT 24
Finished Jul 01 10:45:29 AM PDT 24
Peak memory 207116 kb
Host smart-a88b039e-9d3c-411f-8e86-b8e1f88eeae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402564832 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1402564832
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3362653455
Short name T266
Test name
Test status
Simulation time 21243206 ps
CPU time 0.96 seconds
Started Jul 01 10:45:32 AM PDT 24
Finished Jul 01 10:45:34 AM PDT 24
Peak memory 207052 kb
Host smart-eadf0f01-d62a-4084-be1f-ac1e1add26fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362653455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3362653455
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2330354648
Short name T1096
Test name
Test status
Simulation time 51704172 ps
CPU time 0.87 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:44 AM PDT 24
Peak memory 206828 kb
Host smart-9f75f88c-6c89-4111-8cec-7e49df92c6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330354648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2330354648
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3597942990
Short name T1125
Test name
Test status
Simulation time 39513973 ps
CPU time 1.14 seconds
Started Jul 01 10:45:07 AM PDT 24
Finished Jul 01 10:45:08 AM PDT 24
Peak memory 206928 kb
Host smart-903adb0a-1ed8-409d-85c3-8943449a0abf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597942990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3597942990
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2867111215
Short name T1119
Test name
Test status
Simulation time 145375546 ps
CPU time 2.87 seconds
Started Jul 01 10:45:14 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 215112 kb
Host smart-2af31169-6883-4ebe-8a89-52cdfd5cce68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867111215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2867111215
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1004396706
Short name T1121
Test name
Test status
Simulation time 84161342 ps
CPU time 2.44 seconds
Started Jul 01 10:45:20 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 206808 kb
Host smart-6b70b668-c4cb-4035-b91b-239fef70794b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004396706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1004396706
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1739203575
Short name T1038
Test name
Test status
Simulation time 23291514 ps
CPU time 1.16 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:15 AM PDT 24
Peak memory 215248 kb
Host smart-400f9bc8-a346-4aad-8d0e-8da8df3268c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739203575 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1739203575
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2430830167
Short name T1050
Test name
Test status
Simulation time 33598279 ps
CPU time 0.85 seconds
Started Jul 01 10:45:04 AM PDT 24
Finished Jul 01 10:45:05 AM PDT 24
Peak memory 206728 kb
Host smart-e1f66433-7f40-43ae-901a-b7d581736f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430830167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2430830167
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2224774044
Short name T1025
Test name
Test status
Simulation time 12248211 ps
CPU time 0.84 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:27 AM PDT 24
Peak memory 206984 kb
Host smart-aa2c68f1-8a5f-4046-a9e9-20890765af99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224774044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2224774044
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.699627212
Short name T1084
Test name
Test status
Simulation time 24595888 ps
CPU time 1.26 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 206864 kb
Host smart-e59144d9-f5a8-4cd9-ab35-5a75c71d7d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699627212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.699627212
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2389480594
Short name T1026
Test name
Test status
Simulation time 124995199 ps
CPU time 4.44 seconds
Started Jul 01 10:45:25 AM PDT 24
Finished Jul 01 10:45:30 AM PDT 24
Peak memory 215136 kb
Host smart-d5abf433-44f6-4355-b2d6-1ad88de7e122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389480594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2389480594
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1384619205
Short name T1114
Test name
Test status
Simulation time 220325768 ps
CPU time 2.04 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 206864 kb
Host smart-93ad508d-2253-4c12-9274-05183e499f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384619205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1384619205
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3857855996
Short name T1069
Test name
Test status
Simulation time 83793643 ps
CPU time 1.4 seconds
Started Jul 01 10:45:14 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 215124 kb
Host smart-325ce250-113f-40c9-9f7c-2ca8372752b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857855996 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3857855996
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3021254856
Short name T1130
Test name
Test status
Simulation time 24856109 ps
CPU time 0.96 seconds
Started Jul 01 10:45:14 AM PDT 24
Finished Jul 01 10:45:15 AM PDT 24
Peak memory 206860 kb
Host smart-0164f650-c791-4dbd-b4e0-a77b0dd58222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021254856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3021254856
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1609546271
Short name T1033
Test name
Test status
Simulation time 12842609 ps
CPU time 0.87 seconds
Started Jul 01 10:45:19 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 206808 kb
Host smart-d901e0ff-e2e0-4323-bd26-9bfb9505ab07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609546271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1609546271
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3864951513
Short name T277
Test name
Test status
Simulation time 38429202 ps
CPU time 1.43 seconds
Started Jul 01 10:45:31 AM PDT 24
Finished Jul 01 10:45:33 AM PDT 24
Peak memory 207124 kb
Host smart-469ccfd5-510e-46ca-990f-abad26547f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864951513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3864951513
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.779997821
Short name T1066
Test name
Test status
Simulation time 256368927 ps
CPU time 2.17 seconds
Started Jul 01 10:45:10 AM PDT 24
Finished Jul 01 10:45:12 AM PDT 24
Peak memory 215260 kb
Host smart-69f1e999-6b31-4a77-b144-ca9ed85d3c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779997821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.779997821
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.694057585
Short name T298
Test name
Test status
Simulation time 328571005 ps
CPU time 2.19 seconds
Started Jul 01 10:45:13 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 206904 kb
Host smart-933f5e5c-5651-411f-8347-146e6f19e0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694057585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.694057585
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1642074195
Short name T998
Test name
Test status
Simulation time 121543685 ps
CPU time 1.47 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 215232 kb
Host smart-1f6482fb-1231-4cae-b6f6-b6265be63e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642074195 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1642074195
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3723951592
Short name T1054
Test name
Test status
Simulation time 61696049 ps
CPU time 0.88 seconds
Started Jul 01 10:45:00 AM PDT 24
Finished Jul 01 10:45:02 AM PDT 24
Peak memory 206728 kb
Host smart-256a94ef-910b-4870-8d1e-5b0a7e5055b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723951592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3723951592
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1813339885
Short name T1104
Test name
Test status
Simulation time 44216272 ps
CPU time 0.9 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 206788 kb
Host smart-c0e55eb2-4f2b-4e68-baed-9add9114f257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813339885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1813339885
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1523964604
Short name T283
Test name
Test status
Simulation time 27389670 ps
CPU time 1.13 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 207148 kb
Host smart-6c7b59c2-054a-4d3e-a691-28bc97578da9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523964604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1523964604
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2859498785
Short name T1067
Test name
Test status
Simulation time 495793853 ps
CPU time 4.12 seconds
Started Jul 01 10:45:23 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 215136 kb
Host smart-165365ec-aea6-452c-ae95-ef2fd2657f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859498785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2859498785
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2554927681
Short name T1030
Test name
Test status
Simulation time 130985509 ps
CPU time 1.39 seconds
Started Jul 01 10:45:07 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 215332 kb
Host smart-1dc49795-945b-4b06-9941-9f14c9eba3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554927681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2554927681
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2642842508
Short name T825
Test name
Test status
Simulation time 101561265 ps
CPU time 1.1 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 219116 kb
Host smart-55e48d96-2398-4ba7-818b-9b1e8418b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642842508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2642842508
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.120190923
Short name T558
Test name
Test status
Simulation time 22548563 ps
CPU time 0.82 seconds
Started Jul 01 11:09:23 AM PDT 24
Finished Jul 01 11:09:25 AM PDT 24
Peak memory 207024 kb
Host smart-fcda7f55-1cf4-4f2a-97e6-f0a45a9b1744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120190923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.120190923
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3876925072
Short name T513
Test name
Test status
Simulation time 14174690 ps
CPU time 0.9 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 216880 kb
Host smart-6f32fcb9-5478-4f5d-929c-772ef73e35c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876925072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3876925072
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3006043155
Short name T26
Test name
Test status
Simulation time 71174119 ps
CPU time 1.04 seconds
Started Jul 01 11:09:29 AM PDT 24
Finished Jul 01 11:09:36 AM PDT 24
Peak memory 220020 kb
Host smart-841fff6d-6193-4dfa-a827-ce48377c717d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006043155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3006043155
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2702057303
Short name T125
Test name
Test status
Simulation time 34445384 ps
CPU time 0.88 seconds
Started Jul 01 11:09:25 AM PDT 24
Finished Jul 01 11:09:28 AM PDT 24
Peak memory 219824 kb
Host smart-4697326e-63cf-4107-9147-435e29d3034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702057303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2702057303
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1078516150
Short name T292
Test name
Test status
Simulation time 41753516 ps
CPU time 1.4 seconds
Started Jul 01 11:09:30 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 219008 kb
Host smart-56bdb098-b8bb-48bd-a8cc-a715573d923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078516150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1078516150
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3330321698
Short name T119
Test name
Test status
Simulation time 33469360 ps
CPU time 0.83 seconds
Started Jul 01 11:09:30 AM PDT 24
Finished Jul 01 11:09:36 AM PDT 24
Peak memory 215784 kb
Host smart-4020f3c4-4945-48be-8c1c-b5ce4ec1a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330321698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3330321698
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1863982669
Short name T746
Test name
Test status
Simulation time 26978570 ps
CPU time 0.9 seconds
Started Jul 01 11:09:39 AM PDT 24
Finished Jul 01 11:09:41 AM PDT 24
Peak memory 207452 kb
Host smart-88e9e068-e2bc-4008-b58d-6d690d0358bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863982669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1863982669
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.620941132
Short name T21
Test name
Test status
Simulation time 251440458 ps
CPU time 3.87 seconds
Started Jul 01 11:09:24 AM PDT 24
Finished Jul 01 11:09:28 AM PDT 24
Peak memory 236944 kb
Host smart-7460c7e7-8610-4e42-849d-269f6fbb6b7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620941132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.620941132
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2625336621
Short name T851
Test name
Test status
Simulation time 19605396 ps
CPU time 0.91 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 215612 kb
Host smart-6786747b-8eff-4aa9-9ac3-f2489bb0e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625336621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2625336621
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1284044703
Short name T774
Test name
Test status
Simulation time 360564117 ps
CPU time 6.93 seconds
Started Jul 01 11:09:25 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 220240 kb
Host smart-b74423d8-c249-486f-87a3-1c243b34627e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284044703 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1284044703
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3759031867
Short name T643
Test name
Test status
Simulation time 245889959698 ps
CPU time 1586.56 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:36:03 AM PDT 24
Peak memory 226080 kb
Host smart-a5019c83-d0bf-45b6-8289-da22647457c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759031867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3759031867
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1245611758
Short name T914
Test name
Test status
Simulation time 33739843 ps
CPU time 1.17 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:09:49 AM PDT 24
Peak memory 220320 kb
Host smart-c06e51ec-25f6-4799-963d-1fb18a29226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245611758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1245611758
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.60194452
Short name T461
Test name
Test status
Simulation time 25886914 ps
CPU time 1 seconds
Started Jul 01 11:09:46 AM PDT 24
Finished Jul 01 11:09:47 AM PDT 24
Peak memory 215236 kb
Host smart-56545da0-bf74-4afc-86f4-263d45e13320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60194452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.60194452
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1313875932
Short name T362
Test name
Test status
Simulation time 13480680 ps
CPU time 0.94 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 216552 kb
Host smart-61cb5619-3d5d-492b-bf33-a6dc6a0b4aa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313875932 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1313875932
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2202818469
Short name T444
Test name
Test status
Simulation time 27316289 ps
CPU time 1.1 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 218748 kb
Host smart-c409893d-1677-4d11-afcf-971d44253f41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202818469 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2202818469
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.415901202
Short name T629
Test name
Test status
Simulation time 52949926 ps
CPU time 0.94 seconds
Started Jul 01 11:09:35 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 217608 kb
Host smart-bbe3eaaa-0425-4c17-8f75-1b9c4ac8bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415901202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.415901202
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.997814877
Short name T471
Test name
Test status
Simulation time 35938591 ps
CPU time 0.94 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 224132 kb
Host smart-495f9ee5-fd65-4a9f-ab13-2d7d1a8a4ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997814877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.997814877
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2629908526
Short name T841
Test name
Test status
Simulation time 27756255 ps
CPU time 0.91 seconds
Started Jul 01 11:09:25 AM PDT 24
Finished Jul 01 11:09:28 AM PDT 24
Peak memory 207432 kb
Host smart-6f9d0d4a-ac75-4941-a803-1f173bfe0689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629908526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2629908526
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2292565631
Short name T22
Test name
Test status
Simulation time 471812679 ps
CPU time 6.87 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:43 AM PDT 24
Peak memory 236828 kb
Host smart-8ab8c426-f7ff-4f42-b720-f32da03576e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292565631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2292565631
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.989209244
Short name T372
Test name
Test status
Simulation time 32408010 ps
CPU time 0.93 seconds
Started Jul 01 11:09:25 AM PDT 24
Finished Jul 01 11:09:28 AM PDT 24
Peak memory 215508 kb
Host smart-7aff0ddb-751c-445b-9126-f7633bf64884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989209244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.989209244
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1292982153
Short name T255
Test name
Test status
Simulation time 361290689 ps
CPU time 3.68 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 220500 kb
Host smart-e5f89989-cdeb-4d43-9ce2-2fb7abfe627f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292982153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1292982153
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3019839513
Short name T260
Test name
Test status
Simulation time 279684072 ps
CPU time 1.34 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:51 AM PDT 24
Peak memory 218892 kb
Host smart-0c3c359e-fc03-42db-96cf-900f51ae8b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019839513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3019839513
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3336604569
Short name T566
Test name
Test status
Simulation time 13352662 ps
CPU time 0.86 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 207076 kb
Host smart-4f710b3d-8502-445b-b48b-91456276e765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336604569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3336604569
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.215771841
Short name T182
Test name
Test status
Simulation time 42511337 ps
CPU time 0.97 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:09:48 AM PDT 24
Peak memory 224112 kb
Host smart-0fbc98a8-2c12-4d01-b6ef-6095e61bd914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215771841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.215771841
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3562368076
Short name T927
Test name
Test status
Simulation time 88019726 ps
CPU time 1.03 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:18 AM PDT 24
Peak memory 217516 kb
Host smart-97ec485d-e35f-46e4-8e5d-f8c025bdb807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562368076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3562368076
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.2278369962
Short name T543
Test name
Test status
Simulation time 27615110 ps
CPU time 1 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 215564 kb
Host smart-53881ab8-ce60-4685-a43e-620d75b7e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278369962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2278369962
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4010444601
Short name T809
Test name
Test status
Simulation time 409351812 ps
CPU time 2.63 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 215664 kb
Host smart-2dcd4781-aebc-4e73-82b1-35101fea920a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010444601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4010444601
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2683266137
Short name T979
Test name
Test status
Simulation time 60490326504 ps
CPU time 757.9 seconds
Started Jul 01 11:09:36 AM PDT 24
Finished Jul 01 11:22:17 AM PDT 24
Peak memory 224080 kb
Host smart-2afb2d5e-f927-4021-b152-5a4f883b4140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683266137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2683266137
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2375568923
Short name T869
Test name
Test status
Simulation time 137003036 ps
CPU time 1.23 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 219784 kb
Host smart-2d944701-35c3-417c-9e6f-4b213cbed21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375568923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2375568923
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.4252548289
Short name T252
Test name
Test status
Simulation time 151186725 ps
CPU time 3.07 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 220404 kb
Host smart-a0d16469-cd3c-4b3b-9f3e-75ccac66584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252548289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4252548289
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.785563000
Short name T739
Test name
Test status
Simulation time 313981477 ps
CPU time 1.16 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:04 AM PDT 24
Peak memory 218916 kb
Host smart-481d74b4-ba1b-42c3-9ae1-c90b451b675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785563000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.785563000
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.8849207
Short name T309
Test name
Test status
Simulation time 86860443 ps
CPU time 1.04 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 217628 kb
Host smart-e412112e-7331-4404-bb4b-48815278ed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8849207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.8849207
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2608141603
Short name T227
Test name
Test status
Simulation time 75279617 ps
CPU time 1.12 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 216020 kb
Host smart-b355de30-c6ac-4166-a391-95fb19e1c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608141603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2608141603
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2072073139
Short name T475
Test name
Test status
Simulation time 60529949 ps
CPU time 1.19 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 217544 kb
Host smart-cfb33fdc-2995-4c45-af1b-ef2922ed544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072073139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2072073139
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1953619351
Short name T303
Test name
Test status
Simulation time 39943109 ps
CPU time 1.13 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:03 AM PDT 24
Peak memory 220536 kb
Host smart-4562634c-a0a6-4921-868f-dc3b94449f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953619351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1953619351
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.1512418392
Short name T834
Test name
Test status
Simulation time 24238937 ps
CPU time 1.22 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 219020 kb
Host smart-45d631c4-b0bd-4fdf-a3d7-2beebf3d58ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512418392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1512418392
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.720480467
Short name T803
Test name
Test status
Simulation time 41823174 ps
CPU time 1.11 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 217644 kb
Host smart-ec46b37b-32d7-4f19-830f-6f2133246fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720480467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.720480467
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.4138332119
Short name T591
Test name
Test status
Simulation time 82515262 ps
CPU time 1.16 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 218968 kb
Host smart-4313eac5-7028-4f96-9ac9-aa5140a165be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138332119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.4138332119
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.540963311
Short name T807
Test name
Test status
Simulation time 41388016 ps
CPU time 1.39 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 217796 kb
Host smart-fd888cf7-42af-441e-8626-636c6425056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540963311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.540963311
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2269240738
Short name T100
Test name
Test status
Simulation time 35962262 ps
CPU time 1.09 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 221276 kb
Host smart-0abd28ca-8ca5-40c3-8e86-270a2cd5386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269240738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2269240738
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2045266240
Short name T872
Test name
Test status
Simulation time 74691409 ps
CPU time 1.08 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 217492 kb
Host smart-3ebb6afe-1bf1-4a5b-b747-81d8b881013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045266240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2045266240
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3036747398
Short name T867
Test name
Test status
Simulation time 115079459 ps
CPU time 1.29 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:51 AM PDT 24
Peak memory 216016 kb
Host smart-a1e190e6-be0a-4899-b0bf-ef8fcb667e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036747398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3036747398
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.277383516
Short name T784
Test name
Test status
Simulation time 14779647 ps
CPU time 0.91 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:54 AM PDT 24
Peak memory 215104 kb
Host smart-b082e2fd-cf9a-42f7-be9b-9f6b26a52396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277383516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.277383516
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1040524105
Short name T604
Test name
Test status
Simulation time 56211344 ps
CPU time 1.18 seconds
Started Jul 01 11:09:46 AM PDT 24
Finished Jul 01 11:09:48 AM PDT 24
Peak memory 218524 kb
Host smart-bd431ee2-806d-4d66-aa64-e3e9911c8441
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040524105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1040524105
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3048108719
Short name T138
Test name
Test status
Simulation time 33229283 ps
CPU time 0.92 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:47 AM PDT 24
Peak memory 220016 kb
Host smart-40946e7f-b14e-4ca8-a47a-438515d380fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048108719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3048108719
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1188944031
Short name T963
Test name
Test status
Simulation time 56974059 ps
CPU time 0.99 seconds
Started Jul 01 11:09:38 AM PDT 24
Finished Jul 01 11:09:40 AM PDT 24
Peak memory 219468 kb
Host smart-8fa59ff4-7ef3-4ac8-b420-e4a01cf6c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188944031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1188944031
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3686113209
Short name T463
Test name
Test status
Simulation time 25754037 ps
CPU time 1.01 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 215748 kb
Host smart-a72edd13-253c-420e-9df4-d8a04423b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686113209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3686113209
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1453470077
Short name T473
Test name
Test status
Simulation time 17927246 ps
CPU time 1.01 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:54 AM PDT 24
Peak memory 215564 kb
Host smart-554719aa-e54b-42de-90b7-50e71ca40931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453470077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1453470077
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4077898602
Short name T256
Test name
Test status
Simulation time 168531845 ps
CPU time 1.32 seconds
Started Jul 01 11:09:48 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 215676 kb
Host smart-b3d3b2fc-bd9b-4884-82be-47dc1171f01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077898602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4077898602
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.475541783
Short name T665
Test name
Test status
Simulation time 407950264395 ps
CPU time 2435.68 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:50:29 AM PDT 24
Peak memory 228304 kb
Host smart-1ebaf347-cd40-488d-aa37-72e1b20b1a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475541783 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.475541783
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2771435316
Short name T27
Test name
Test status
Simulation time 101345357 ps
CPU time 1.14 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 218784 kb
Host smart-41bc538c-4393-49ab-b0c4-967bbfd2b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771435316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2771435316
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.2253973386
Short name T849
Test name
Test status
Simulation time 24210460 ps
CPU time 1.18 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 218992 kb
Host smart-e7248cbd-de59-4645-93d1-e27ab66f7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253973386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2253973386
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1781093281
Short name T432
Test name
Test status
Simulation time 73713295 ps
CPU time 1.47 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:25 AM PDT 24
Peak memory 219148 kb
Host smart-9ac13076-e3d6-49e8-ba09-7e09889d3193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781093281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1781093281
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3965184933
Short name T141
Test name
Test status
Simulation time 189843617 ps
CPU time 1.14 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 219012 kb
Host smart-0aac0c05-54da-4cef-ac9c-35c20b5a74c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965184933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3965184933
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3002903134
Short name T437
Test name
Test status
Simulation time 37760860 ps
CPU time 1.34 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 218836 kb
Host smart-010139eb-d49e-4677-8eae-0ed00e910ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002903134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3002903134
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3695354507
Short name T19
Test name
Test status
Simulation time 53337175 ps
CPU time 1.3 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 215496 kb
Host smart-d91018c9-0c0b-44b3-a2db-86f2ce53ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695354507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3695354507
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.4203619190
Short name T18
Test name
Test status
Simulation time 73617299 ps
CPU time 1.15 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 215960 kb
Host smart-5cf562bb-2027-41aa-97c2-5480d0434c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203619190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4203619190
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1905084578
Short name T730
Test name
Test status
Simulation time 56623189 ps
CPU time 1.18 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 217792 kb
Host smart-02a2d139-62ff-4a71-801f-1d1ff9e32fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905084578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1905084578
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3254443073
Short name T301
Test name
Test status
Simulation time 50144867 ps
CPU time 1.23 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 220244 kb
Host smart-cb29e25e-6016-4915-9749-3514c4a34363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254443073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3254443073
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2110177527
Short name T802
Test name
Test status
Simulation time 29812314 ps
CPU time 1.31 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 218976 kb
Host smart-f76c2231-57de-4b47-9148-ad33ad3a3682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110177527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2110177527
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1031037522
Short name T431
Test name
Test status
Simulation time 42050349 ps
CPU time 1.55 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 220512 kb
Host smart-1dc5e593-6b31-48c6-b8a9-9f5aea461ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031037522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1031037522
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.228208990
Short name T446
Test name
Test status
Simulation time 24802417 ps
CPU time 1.15 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:04 AM PDT 24
Peak memory 220268 kb
Host smart-bf72d341-53e9-468b-84a2-22b24e2ca5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228208990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.228208990
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3813174908
Short name T690
Test name
Test status
Simulation time 52025908 ps
CPU time 1.29 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 217424 kb
Host smart-a4b38080-f83e-4b9c-8757-7762d37274ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813174908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3813174908
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3851556460
Short name T158
Test name
Test status
Simulation time 30608728 ps
CPU time 1.28 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 220832 kb
Host smart-1f229dcc-21f0-4ec4-954a-354b8093703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851556460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3851556460
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3105988104
Short name T72
Test name
Test status
Simulation time 52028250 ps
CPU time 1.3 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 218900 kb
Host smart-6899390f-b6d5-46c7-8cc5-17d65a30a213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105988104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3105988104
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2861858056
Short name T734
Test name
Test status
Simulation time 29747230 ps
CPU time 1.06 seconds
Started Jul 01 11:11:17 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 219048 kb
Host smart-5f2a258c-d170-440c-8988-2f5b133f2e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861858056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2861858056
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3460763262
Short name T694
Test name
Test status
Simulation time 42134491 ps
CPU time 1.54 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:26 AM PDT 24
Peak memory 218804 kb
Host smart-f0977be8-6d6f-49ac-91ee-eb48ab814b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460763262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3460763262
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1127449913
Short name T460
Test name
Test status
Simulation time 50830048 ps
CPU time 1.25 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 220192 kb
Host smart-4bae8040-02b2-49bd-bb4a-a0a91fc8830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127449913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1127449913
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.817255728
Short name T833
Test name
Test status
Simulation time 152662065 ps
CPU time 0.93 seconds
Started Jul 01 11:09:46 AM PDT 24
Finished Jul 01 11:09:47 AM PDT 24
Peak memory 215168 kb
Host smart-816bb383-4c9b-40bb-8748-afc444606ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817255728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.817255728
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1501254472
Short name T595
Test name
Test status
Simulation time 84026818 ps
CPU time 1.13 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:47 AM PDT 24
Peak memory 218528 kb
Host smart-f3ce4061-14b9-4587-9516-2e488480376d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501254472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1501254472
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.4194419601
Short name T854
Test name
Test status
Simulation time 39295451 ps
CPU time 0.84 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 218788 kb
Host smart-7bef24ad-4eb3-48b8-b8cf-e1947e38852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194419601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4194419601
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4290255061
Short name T549
Test name
Test status
Simulation time 79592817 ps
CPU time 1.34 seconds
Started Jul 01 11:09:41 AM PDT 24
Finished Jul 01 11:09:43 AM PDT 24
Peak memory 219440 kb
Host smart-775c65dd-a2e9-4065-ac54-61d009c6dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290255061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4290255061
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1085522758
Short name T890
Test name
Test status
Simulation time 20821681 ps
CPU time 1.16 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 224340 kb
Host smart-47b31d71-e266-4933-a728-e5742108e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085522758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1085522758
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.715119666
Short name T917
Test name
Test status
Simulation time 17702133 ps
CPU time 0.96 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 215628 kb
Host smart-502c84cb-547c-48a3-9795-eff4386e0ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715119666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.715119666
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4104001808
Short name T330
Test name
Test status
Simulation time 218361822 ps
CPU time 4.93 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 218996 kb
Host smart-c5dcf42c-85f6-4114-b9cb-937759ea1187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104001808 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4104001808
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2213129644
Short name T650
Test name
Test status
Simulation time 57170776148 ps
CPU time 539.18 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:18:47 AM PDT 24
Peak memory 224016 kb
Host smart-1b99a145-1226-420c-92a1-7cb7e25d34f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213129644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2213129644
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.151722005
Short name T91
Test name
Test status
Simulation time 75463204 ps
CPU time 1.04 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:04 AM PDT 24
Peak memory 219012 kb
Host smart-36ccac1b-ab72-4a95-a294-d28e28368674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151722005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.151722005
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2174807267
Short name T608
Test name
Test status
Simulation time 49285649 ps
CPU time 1.54 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 218940 kb
Host smart-dc1a51c0-6653-4058-aecf-75f437579170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174807267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2174807267
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2281194043
Short name T295
Test name
Test status
Simulation time 86331831 ps
CPU time 1.45 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 219420 kb
Host smart-752ea5c9-7ec3-4f37-8949-ee142b909b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281194043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2281194043
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1413997278
Short name T933
Test name
Test status
Simulation time 40383600 ps
CPU time 1.52 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 220252 kb
Host smart-2a723637-baea-480d-8e49-50074566dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413997278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1413997278
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1074475322
Short name T814
Test name
Test status
Simulation time 39657182 ps
CPU time 1.35 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220048 kb
Host smart-4d5e1c72-bc6f-4605-9a05-21c7fac6b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074475322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1074475322
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1828575505
Short name T178
Test name
Test status
Simulation time 49116639 ps
CPU time 1.15 seconds
Started Jul 01 11:11:18 AM PDT 24
Finished Jul 01 11:11:25 AM PDT 24
Peak memory 221060 kb
Host smart-e0584257-529b-4d23-a2a4-b823f6f6f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828575505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1828575505
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3303935806
Short name T2
Test name
Test status
Simulation time 76937953 ps
CPU time 2.43 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 220424 kb
Host smart-a46fe406-0186-4863-9248-14a3f0772d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303935806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3303935806
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2523679448
Short name T705
Test name
Test status
Simulation time 36382031 ps
CPU time 1.07 seconds
Started Jul 01 11:11:17 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 220104 kb
Host smart-d586e237-18ff-4d00-8410-90973e1e1281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523679448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2523679448
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1219116902
Short name T915
Test name
Test status
Simulation time 73130455 ps
CPU time 1.05 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 215680 kb
Host smart-7e6348bf-2788-478d-89e2-cb34130e5177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219116902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1219116902
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.4212381951
Short name T114
Test name
Test status
Simulation time 26379390 ps
CPU time 1.27 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 220032 kb
Host smart-cab73481-06f8-4a05-997b-28e03e578dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212381951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.4212381951
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.406192538
Short name T46
Test name
Test status
Simulation time 35299494 ps
CPU time 1.39 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 217708 kb
Host smart-adffdea5-2b72-468f-8e6d-df8a5eb08d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406192538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.406192538
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3719955337
Short name T839
Test name
Test status
Simulation time 81762619 ps
CPU time 1.21 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 220628 kb
Host smart-286f6bee-a193-454c-a53f-43d219b09872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719955337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3719955337
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1430324279
Short name T78
Test name
Test status
Simulation time 90592098 ps
CPU time 1.06 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 217664 kb
Host smart-a119fcc1-5244-4ed5-9f03-00ec186188d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430324279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1430324279
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2713868396
Short name T679
Test name
Test status
Simulation time 203681767 ps
CPU time 1.18 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 220172 kb
Host smart-c1a71dd0-1c8d-40ad-940c-20864eb41b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713868396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2713868396
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2205135993
Short name T586
Test name
Test status
Simulation time 303039262 ps
CPU time 3.77 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 219500 kb
Host smart-e8afb470-905e-4c39-9d1c-197516690b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205135993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2205135993
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1936057128
Short name T680
Test name
Test status
Simulation time 42680332 ps
CPU time 1.18 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 220364 kb
Host smart-c0425aae-da8d-4d6e-820e-3992d73d6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936057128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1936057128
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2246985762
Short name T661
Test name
Test status
Simulation time 31079542 ps
CPU time 1.26 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 218792 kb
Host smart-17217e27-12c9-4ae1-8b41-b92a7c26eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246985762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2246985762
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2426278310
Short name T721
Test name
Test status
Simulation time 39774639 ps
CPU time 1.33 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 219532 kb
Host smart-4a15659c-0d63-4c81-bc69-94b69040a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426278310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2426278310
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.519967778
Short name T816
Test name
Test status
Simulation time 36158526 ps
CPU time 0.86 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:46 AM PDT 24
Peak memory 214936 kb
Host smart-58831bf1-f52e-4f17-9e79-326ff53c7f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519967778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.519967778
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.210733554
Short name T922
Test name
Test status
Simulation time 48165402 ps
CPU time 1.04 seconds
Started Jul 01 11:09:50 AM PDT 24
Finished Jul 01 11:09:52 AM PDT 24
Peak memory 218712 kb
Host smart-60f91610-08fc-4213-a1d8-4692e4561ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210733554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.210733554
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2662029934
Short name T970
Test name
Test status
Simulation time 24260301 ps
CPU time 1.13 seconds
Started Jul 01 11:09:33 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 217712 kb
Host smart-5a692fc5-4078-4ca2-852b-83cf09777455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662029934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2662029934
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1648539763
Short name T994
Test name
Test status
Simulation time 47254052 ps
CPU time 0.94 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 215608 kb
Host smart-1b709dd7-b0e6-40c1-a8a3-48777bf305de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648539763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1648539763
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1027495459
Short name T484
Test name
Test status
Simulation time 176374588 ps
CPU time 3.67 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 217492 kb
Host smart-f208ff4b-f7bb-4c17-aa65-f2d04822c837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027495459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1027495459
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3478673651
Short name T103
Test name
Test status
Simulation time 167411591631 ps
CPU time 1338.84 seconds
Started Jul 01 11:09:41 AM PDT 24
Finished Jul 01 11:32:00 AM PDT 24
Peak memory 223480 kb
Host smart-870e9e8a-fab2-4698-8767-7e9226678d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478673651 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3478673651
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.921379591
Short name T882
Test name
Test status
Simulation time 30095859 ps
CPU time 1.26 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 220340 kb
Host smart-794525a3-7446-4bdb-942e-7a7fa2b1dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921379591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.921379591
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1086193663
Short name T771
Test name
Test status
Simulation time 130711379 ps
CPU time 1.38 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 220392 kb
Host smart-fa2bca39-3dac-4178-bab3-c4c0b596779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086193663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1086193663
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.239835301
Short name T68
Test name
Test status
Simulation time 36964772 ps
CPU time 1.1 seconds
Started Jul 01 11:11:17 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 219296 kb
Host smart-a57dcfa0-2fc7-4daf-860a-ac2f4fbe790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239835301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.239835301
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.3767881965
Short name T115
Test name
Test status
Simulation time 47337853 ps
CPU time 1.2 seconds
Started Jul 01 11:11:30 AM PDT 24
Finished Jul 01 11:11:33 AM PDT 24
Peak memory 221316 kb
Host smart-1259afd8-3c05-43d4-a7e1-593ec580d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767881965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3767881965
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1847864560
Short name T83
Test name
Test status
Simulation time 36739351 ps
CPU time 1.42 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 217868 kb
Host smart-90e7a3c9-b013-47cf-83d1-097e46c197dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847864560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1847864560
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1501594710
Short name T785
Test name
Test status
Simulation time 34164108 ps
CPU time 1.31 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 218872 kb
Host smart-f034b067-577d-47f8-b2f1-682d5186f1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501594710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1501594710
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2208836598
Short name T817
Test name
Test status
Simulation time 58125773 ps
CPU time 1.26 seconds
Started Jul 01 11:11:20 AM PDT 24
Finished Jul 01 11:11:26 AM PDT 24
Peak memory 217644 kb
Host smart-d32e2df3-d4ab-474e-aeae-c3998519914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208836598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2208836598
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2978680206
Short name T755
Test name
Test status
Simulation time 63140657 ps
CPU time 1.02 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 221192 kb
Host smart-7f842374-d393-4438-b03d-69b22bb1c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978680206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2978680206
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2692780379
Short name T462
Test name
Test status
Simulation time 129276195 ps
CPU time 1.25 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 217800 kb
Host smart-56d8f061-8523-4c7d-9f63-498a6b871d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692780379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2692780379
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.307386258
Short name T187
Test name
Test status
Simulation time 44098028 ps
CPU time 1.06 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 219980 kb
Host smart-1e1f3d19-accb-4b38-8370-46db3105b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307386258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.307386258
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2511281004
Short name T506
Test name
Test status
Simulation time 32719764 ps
CPU time 1.29 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 218976 kb
Host smart-15403712-f95f-47e9-bc95-38314b096d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511281004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2511281004
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.214634622
Short name T925
Test name
Test status
Simulation time 42494691 ps
CPU time 1.16 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 220176 kb
Host smart-5392720b-09a8-4090-849e-0ac120e76db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214634622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.214634622
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.4056541787
Short name T524
Test name
Test status
Simulation time 57396965 ps
CPU time 1.19 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 218632 kb
Host smart-881a6f8e-9e85-4831-9641-a62f7db54fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056541787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4056541787
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3061589407
Short name T305
Test name
Test status
Simulation time 42654961 ps
CPU time 1.35 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 217712 kb
Host smart-772089c9-c1ea-4fc4-a8ea-d54e302a59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061589407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3061589407
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3943118282
Short name T332
Test name
Test status
Simulation time 39184238 ps
CPU time 1.14 seconds
Started Jul 01 11:11:18 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 219952 kb
Host smart-1bad5224-1698-40c7-8aa1-7c4775af93b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943118282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3943118282
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2227375514
Short name T940
Test name
Test status
Simulation time 30927044 ps
CPU time 1.42 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 217512 kb
Host smart-bc921e61-8b20-4446-be7f-d71073969486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227375514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2227375514
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1019316975
Short name T588
Test name
Test status
Simulation time 83845574 ps
CPU time 1.16 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 220164 kb
Host smart-459a8ed9-55f8-4ddf-9680-dea48c942af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019316975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1019316975
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2195427014
Short name T499
Test name
Test status
Simulation time 20361708 ps
CPU time 0.83 seconds
Started Jul 01 11:09:40 AM PDT 24
Finished Jul 01 11:09:42 AM PDT 24
Peak memory 207028 kb
Host smart-e6ab594b-ea89-4382-a678-b8ea44adaeb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195427014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2195427014
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.4189934425
Short name T84
Test name
Test status
Simulation time 35664235 ps
CPU time 0.87 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 216684 kb
Host smart-929e1516-597c-4375-a410-71563ca3ca01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189934425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.4189934425
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.291483678
Short name T791
Test name
Test status
Simulation time 340194496 ps
CPU time 1.41 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 218696 kb
Host smart-ccac4067-de77-4f05-ab30-cb2297f5ab31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291483678 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.291483678
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3404058743
Short name T710
Test name
Test status
Simulation time 27241393 ps
CPU time 1.17 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 221020 kb
Host smart-973259fc-0dde-40d9-963a-0c762eb05bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404058743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3404058743
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.867403721
Short name T343
Test name
Test status
Simulation time 108096865 ps
CPU time 1.64 seconds
Started Jul 01 11:09:55 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 219216 kb
Host smart-c5a79545-1921-4d7a-83ab-772aa90e02c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867403721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.867403721
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3664548416
Short name T75
Test name
Test status
Simulation time 26156955 ps
CPU time 0.88 seconds
Started Jul 01 11:09:54 AM PDT 24
Finished Jul 01 11:09:55 AM PDT 24
Peak memory 215740 kb
Host smart-d7c438d7-4147-4185-bcf0-2806d6129ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664548416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3664548416
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3738298026
Short name T806
Test name
Test status
Simulation time 17757025 ps
CPU time 1.04 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 215580 kb
Host smart-f2be5e5a-fc3d-4b74-8386-f84ab495810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738298026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3738298026
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1702839366
Short name T902
Test name
Test status
Simulation time 236948734 ps
CPU time 3.31 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:52 AM PDT 24
Peak memory 217600 kb
Host smart-38719a62-6c6c-409a-8da7-0917367cd573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702839366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1702839366
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1748816674
Short name T975
Test name
Test status
Simulation time 101631563200 ps
CPU time 616.72 seconds
Started Jul 01 11:09:55 AM PDT 24
Finished Jul 01 11:20:13 AM PDT 24
Peak memory 219672 kb
Host smart-bc11db39-6e37-4316-a9b0-098c60c20dc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748816674 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1748816674
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3380759680
Short name T116
Test name
Test status
Simulation time 174808483 ps
CPU time 1.2 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 215956 kb
Host smart-d2a7ca11-c1d9-4248-8eaa-ef9ada64809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380759680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3380759680
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2888859033
Short name T371
Test name
Test status
Simulation time 92921864 ps
CPU time 1.12 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 217656 kb
Host smart-9e56f591-36b6-490f-b7b9-6ce2429ec0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888859033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2888859033
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1151644067
Short name T542
Test name
Test status
Simulation time 77392099 ps
CPU time 1.05 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 218852 kb
Host smart-c4d4664f-42a2-4b3c-884f-d736378a7134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151644067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1151644067
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2319100629
Short name T678
Test name
Test status
Simulation time 42396387 ps
CPU time 1.45 seconds
Started Jul 01 11:11:18 AM PDT 24
Finished Jul 01 11:11:25 AM PDT 24
Peak memory 218772 kb
Host smart-8997fbaa-2aaa-47fc-a594-19b2d419d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319100629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2319100629
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2791266864
Short name T860
Test name
Test status
Simulation time 71071727 ps
CPU time 1.14 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220612 kb
Host smart-11d54129-175e-4b52-bc6c-c89999217a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791266864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2791266864
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1229839059
Short name T379
Test name
Test status
Simulation time 29907880 ps
CPU time 1.36 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 220536 kb
Host smart-a95bbd20-8560-4de7-9318-d49bdca65e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229839059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1229839059
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.873114577
Short name T986
Test name
Test status
Simulation time 103305083 ps
CPU time 1.2 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 220016 kb
Host smart-f0535250-cdd8-4833-bf26-23a8db548f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873114577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.873114577
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4073429666
Short name T418
Test name
Test status
Simulation time 37758297 ps
CPU time 1.7 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 217700 kb
Host smart-f8fdf6e4-4e17-4c59-b12e-1b94fba5735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073429666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4073429666
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3920858678
Short name T452
Test name
Test status
Simulation time 147301009 ps
CPU time 1.33 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 221980 kb
Host smart-23bde4a3-8d44-4b97-a393-198687a03791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920858678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3920858678
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.602440155
Short name T391
Test name
Test status
Simulation time 46825072 ps
CPU time 1.45 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 218652 kb
Host smart-fa9bbbe0-4abe-4a76-a347-96ed2f52c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602440155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.602440155
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2629059858
Short name T843
Test name
Test status
Simulation time 31288297 ps
CPU time 1.28 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 220280 kb
Host smart-d592e3cf-e859-4a98-bf31-43e3eb63e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629059858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2629059858
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.823136017
Short name T674
Test name
Test status
Simulation time 316564677 ps
CPU time 1.18 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 217592 kb
Host smart-ac58b754-e125-4ac9-bd23-297cbe6d2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823136017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.823136017
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.427490234
Short name T656
Test name
Test status
Simulation time 38750339 ps
CPU time 1.16 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:09 AM PDT 24
Peak memory 219068 kb
Host smart-6a45a506-53c7-4584-9232-d84109620799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427490234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.427490234
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.991743746
Short name T598
Test name
Test status
Simulation time 30205366 ps
CPU time 1.35 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:03 AM PDT 24
Peak memory 220704 kb
Host smart-0c29ed12-1ca6-4aa9-ada7-8b4905f036a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991743746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.991743746
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.930852527
Short name T248
Test name
Test status
Simulation time 124934003 ps
CPU time 2.35 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 218844 kb
Host smart-e7bdbf7b-ee78-4cdb-8ce7-8c94786e0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930852527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.930852527
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3066545838
Short name T840
Test name
Test status
Simulation time 41022710 ps
CPU time 1.16 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 220072 kb
Host smart-d5c02bf3-3ff8-460a-b36a-d61e37f48058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066545838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3066545838
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.898315117
Short name T538
Test name
Test status
Simulation time 70936600 ps
CPU time 1.67 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:44 AM PDT 24
Peak memory 220644 kb
Host smart-4e4fd9bb-a049-4cc0-a04b-59bbf9fc7928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898315117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.898315117
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1707807625
Short name T472
Test name
Test status
Simulation time 33889647 ps
CPU time 1.45 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 219212 kb
Host smart-84d8247d-ae78-448f-9df6-9d1647229c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707807625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1707807625
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2502204340
Short name T427
Test name
Test status
Simulation time 41622077 ps
CPU time 1.23 seconds
Started Jul 01 11:09:38 AM PDT 24
Finished Jul 01 11:09:41 AM PDT 24
Peak memory 216024 kb
Host smart-0914cdf5-922a-48d8-b57d-387bcdb0729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502204340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2502204340
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1901851062
Short name T991
Test name
Test status
Simulation time 45836949 ps
CPU time 0.9 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:03 AM PDT 24
Peak memory 207124 kb
Host smart-416480b0-dcaa-48d2-95ae-89271e4e9d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901851062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1901851062
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.3710841572
Short name T62
Test name
Test status
Simulation time 23491056 ps
CPU time 1.07 seconds
Started Jul 01 11:09:42 AM PDT 24
Finished Jul 01 11:09:43 AM PDT 24
Peak memory 218632 kb
Host smart-57262c18-6e13-4510-b622-6755c78cc668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710841572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3710841572
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.364812155
Short name T949
Test name
Test status
Simulation time 31189287 ps
CPU time 1.31 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:51 AM PDT 24
Peak memory 219956 kb
Host smart-8fc2a86c-c1af-41d0-9706-a1ffcbbddbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364812155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.364812155
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2104032450
Short name T836
Test name
Test status
Simulation time 38056420 ps
CPU time 1 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:52 AM PDT 24
Peak memory 224400 kb
Host smart-312e570a-bfe2-418e-8ed0-dffd92a223d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104032450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2104032450
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3341114721
Short name T612
Test name
Test status
Simulation time 33623655 ps
CPU time 0.9 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 215564 kb
Host smart-7945fb45-9f74-490f-9c4b-3811f077940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341114721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3341114721
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3557174504
Short name T976
Test name
Test status
Simulation time 350957197 ps
CPU time 6.25 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 215612 kb
Host smart-219346e3-d087-46c6-b4c0-0488bbb42288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557174504 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3557174504
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4179843851
Short name T104
Test name
Test status
Simulation time 424878331937 ps
CPU time 2566.07 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 232468 kb
Host smart-82306435-cb9f-4058-9883-8579f60d5e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179843851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4179843851
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.210813476
Short name T703
Test name
Test status
Simulation time 46259454 ps
CPU time 1.4 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 218872 kb
Host smart-9696ea24-fc6f-4afc-b506-fc0051d9452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210813476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.210813476
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.4194988322
Short name T648
Test name
Test status
Simulation time 108551354 ps
CPU time 1.3 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 221252 kb
Host smart-725bbce9-085a-46a6-a34a-027b1558345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194988322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.4194988322
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2694945367
Short name T396
Test name
Test status
Simulation time 33706580 ps
CPU time 1.57 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 218860 kb
Host smart-ecf3782d-64ab-4d8e-9983-8e88b626d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694945367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2694945367
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3397475358
Short name T120
Test name
Test status
Simulation time 47587306 ps
CPU time 1.22 seconds
Started Jul 01 11:11:25 AM PDT 24
Finished Jul 01 11:11:28 AM PDT 24
Peak memory 220776 kb
Host smart-c5720d2a-a976-43fb-9bf5-22e3b522ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397475358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3397475358
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3895655336
Short name T874
Test name
Test status
Simulation time 236605466 ps
CPU time 1.36 seconds
Started Jul 01 11:11:20 AM PDT 24
Finished Jul 01 11:11:26 AM PDT 24
Peak memory 217700 kb
Host smart-f883e321-ce34-4c4c-be0f-79135a6c317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895655336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3895655336
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3851959722
Short name T666
Test name
Test status
Simulation time 75143359 ps
CPU time 1.23 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 218604 kb
Host smart-dee44b9c-bb73-4095-b11b-d9d1d40061f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851959722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3851959722
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3730445943
Short name T387
Test name
Test status
Simulation time 57180361 ps
CPU time 0.91 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 217560 kb
Host smart-975e4efa-91b1-471c-b50c-803bfc43cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730445943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3730445943
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3955666268
Short name T699
Test name
Test status
Simulation time 344414746 ps
CPU time 1.51 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 220036 kb
Host smart-d5b0af36-0485-4fd3-8c4e-bcb6d5215d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955666268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3955666268
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1426232866
Short name T354
Test name
Test status
Simulation time 53665472 ps
CPU time 1.26 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 217588 kb
Host smart-8ea96535-8a2c-4148-aa97-55f3c6a61165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426232866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1426232866
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1271572769
Short name T448
Test name
Test status
Simulation time 93697949 ps
CPU time 1.18 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 220512 kb
Host smart-63faa9b7-eebd-447e-8782-0d3cbdabf582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271572769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1271572769
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1588840077
Short name T509
Test name
Test status
Simulation time 36496961 ps
CPU time 1.41 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 218828 kb
Host smart-c674fa83-e945-4ae1-a387-136af3da11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588840077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1588840077
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1630697361
Short name T552
Test name
Test status
Simulation time 77160227 ps
CPU time 1.13 seconds
Started Jul 01 11:11:41 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 219584 kb
Host smart-81925bb6-f8f0-4aea-a45e-ba3915194718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630697361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1630697361
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.3636685580
Short name T918
Test name
Test status
Simulation time 77017679 ps
CPU time 1.26 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 218924 kb
Host smart-f4d06668-c68c-4bc0-9276-2e632adeadec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636685580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3636685580
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.860646278
Short name T726
Test name
Test status
Simulation time 24986181 ps
CPU time 1.15 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 216024 kb
Host smart-3b903b3c-5e43-44a4-a597-b0a8530dc95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860646278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.860646278
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1100362801
Short name T861
Test name
Test status
Simulation time 148040680 ps
CPU time 1.14 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 217836 kb
Host smart-5d0b4d42-eac9-46c4-996b-a945c0087cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100362801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1100362801
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2221511601
Short name T957
Test name
Test status
Simulation time 21680101 ps
CPU time 1.1 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 218724 kb
Host smart-e60fe398-8de2-47df-aca3-c737531b8f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221511601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2221511601
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.179610340
Short name T942
Test name
Test status
Simulation time 35259347 ps
CPU time 1.39 seconds
Started Jul 01 11:11:18 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 217924 kb
Host smart-33d7dbd6-49db-4200-a243-d6f90407e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179610340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.179610340
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4265908904
Short name T757
Test name
Test status
Simulation time 25048177 ps
CPU time 1.19 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 221156 kb
Host smart-3af6cd28-4d60-426b-bd47-ac564135693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265908904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4265908904
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1249350329
Short name T941
Test name
Test status
Simulation time 13682721 ps
CPU time 0.89 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 206884 kb
Host smart-8fd5a217-6acb-445b-ad98-6d819101ad80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249350329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1249350329
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.986925109
Short name T850
Test name
Test status
Simulation time 28241510 ps
CPU time 1.12 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 218672 kb
Host smart-112c5426-8870-44b9-b1cd-5ec4b5bb5e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986925109 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.986925109
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1951661341
Short name T6
Test name
Test status
Simulation time 34258989 ps
CPU time 0.92 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 218372 kb
Host smart-03fd1b90-4fb7-4785-b507-9365b4ca178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951661341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1951661341
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1165420095
Short name T247
Test name
Test status
Simulation time 71117664 ps
CPU time 1.49 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 219044 kb
Host smart-415a3a3d-2535-43c3-8fff-547dfb0eab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165420095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1165420095
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.892394441
Short name T35
Test name
Test status
Simulation time 50881098 ps
CPU time 0.79 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215772 kb
Host smart-665e7a98-94d0-45ef-be78-a6ec0f6e40f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892394441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.892394441
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3612386771
Short name T502
Test name
Test status
Simulation time 97168428 ps
CPU time 0.86 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:16 AM PDT 24
Peak memory 215640 kb
Host smart-1db13b14-c52c-47c8-911b-887085d38bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612386771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3612386771
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.690693628
Short name T204
Test name
Test status
Simulation time 227935877 ps
CPU time 4.62 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 220764 kb
Host smart-e6093bb1-7d31-4398-a6b4-a04b5803cfae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690693628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.690693628
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2050348027
Short name T856
Test name
Test status
Simulation time 182396712787 ps
CPU time 533.12 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:19:11 AM PDT 24
Peak memory 219960 kb
Host smart-8c65cdc6-0d82-47d5-8d7d-feb9dc44ce1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050348027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2050348027
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.4048924924
Short name T900
Test name
Test status
Simulation time 43407695 ps
CPU time 1.2 seconds
Started Jul 01 11:11:26 AM PDT 24
Finished Jul 01 11:11:29 AM PDT 24
Peak memory 220096 kb
Host smart-337d2f96-c4a6-4152-8aba-9d6c961f3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048924924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4048924924
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3344417678
Short name T813
Test name
Test status
Simulation time 33843392 ps
CPU time 1.49 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 217672 kb
Host smart-44e4b057-5d3f-464d-8577-20bed1d72b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344417678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3344417678
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3398366288
Short name T758
Test name
Test status
Simulation time 56416395 ps
CPU time 1.1 seconds
Started Jul 01 11:11:28 AM PDT 24
Finished Jul 01 11:11:30 AM PDT 24
Peak memory 219136 kb
Host smart-096338fe-a66a-4eaf-9593-bb862e1a2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398366288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3398366288
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.4119770608
Short name T635
Test name
Test status
Simulation time 45653871 ps
CPU time 1.24 seconds
Started Jul 01 11:11:41 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 220256 kb
Host smart-61692ef0-10cc-4055-b7a9-d79ca9855402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119770608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4119770608
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1420442279
Short name T537
Test name
Test status
Simulation time 30302537 ps
CPU time 1.22 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 218772 kb
Host smart-3b971194-5134-44de-9121-724131859040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420442279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1420442279
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2775312764
Short name T960
Test name
Test status
Simulation time 37453619 ps
CPU time 1.06 seconds
Started Jul 01 11:11:26 AM PDT 24
Finished Jul 01 11:11:29 AM PDT 24
Peak memory 217696 kb
Host smart-ec2d1cc6-c8b7-4ed4-a5da-a450b256ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775312764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2775312764
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.977429246
Short name T696
Test name
Test status
Simulation time 26873488 ps
CPU time 1.24 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 218984 kb
Host smart-b5ffe8df-0a9d-4e26-8d0f-15d8eedfedb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977429246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.977429246
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2360113416
Short name T871
Test name
Test status
Simulation time 35444660 ps
CPU time 1.29 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 218884 kb
Host smart-c1ac974b-99d2-4c36-8b55-424f8c83bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360113416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2360113416
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1140983879
Short name T865
Test name
Test status
Simulation time 45236557 ps
CPU time 1.18 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 218960 kb
Host smart-6d2292fa-73bc-4363-8be2-411fa7038319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140983879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1140983879
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2357065429
Short name T311
Test name
Test status
Simulation time 133812012 ps
CPU time 1.39 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 219556 kb
Host smart-084b7c52-e211-4e8b-be05-e5d2c0213b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357065429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2357065429
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2145836572
Short name T77
Test name
Test status
Simulation time 31474146 ps
CPU time 1.14 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:38 AM PDT 24
Peak memory 218732 kb
Host smart-f1746f91-cfd2-4f25-8474-16f3fae6be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145836572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2145836572
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.223715847
Short name T528
Test name
Test status
Simulation time 33746211 ps
CPU time 1.49 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 217744 kb
Host smart-1377aee6-5ab5-4043-a684-f1a6cb5ef30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223715847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.223715847
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3134027742
Short name T469
Test name
Test status
Simulation time 67840369 ps
CPU time 1.11 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 218888 kb
Host smart-ba064efc-1670-4741-8793-2d5e0514a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134027742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3134027742
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.634352458
Short name T496
Test name
Test status
Simulation time 86731539 ps
CPU time 1.24 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:00 AM PDT 24
Peak memory 219032 kb
Host smart-16ff3203-69de-4d17-b0d4-10602f1cd180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634352458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.634352458
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1816841981
Short name T910
Test name
Test status
Simulation time 26148750 ps
CPU time 1.24 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220092 kb
Host smart-8dbd9dab-c424-4a74-80d1-7d00ad76f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816841981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1816841981
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1552518006
Short name T689
Test name
Test status
Simulation time 106949129 ps
CPU time 1.21 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 217904 kb
Host smart-f3103ea2-48cc-4869-8201-d5bebd07949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552518006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1552518006
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.4268831703
Short name T129
Test name
Test status
Simulation time 25913240 ps
CPU time 1.24 seconds
Started Jul 01 11:11:26 AM PDT 24
Finished Jul 01 11:11:29 AM PDT 24
Peak memory 219712 kb
Host smart-b6720a64-42d9-4c11-9f99-f9a9fc4a5c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268831703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.4268831703
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1781228777
Short name T306
Test name
Test status
Simulation time 178370048 ps
CPU time 0.95 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 217640 kb
Host smart-af3d444e-e418-431e-982a-5b971b967558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781228777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1781228777
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.571668229
Short name T339
Test name
Test status
Simulation time 26640135 ps
CPU time 1.22 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:35 AM PDT 24
Peak memory 216028 kb
Host smart-dadadea6-c9be-4145-9d9d-5b99bf525718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571668229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.571668229
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.786439247
Short name T69
Test name
Test status
Simulation time 48729918 ps
CPU time 1.16 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 218836 kb
Host smart-5ad7458f-0fb2-4411-9902-6160d46c55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786439247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.786439247
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4036345803
Short name T338
Test name
Test status
Simulation time 35985130 ps
CPU time 1.06 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 218792 kb
Host smart-8d0b13e4-ff30-49b2-8a46-e53522c8daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036345803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4036345803
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable.80778424
Short name T546
Test name
Test status
Simulation time 12552137 ps
CPU time 0.88 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:03 AM PDT 24
Peak memory 216736 kb
Host smart-04ca12c4-2e56-48ab-bc97-1f9dab51e10b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80778424 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.80778424
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2789341023
Short name T913
Test name
Test status
Simulation time 50184072 ps
CPU time 0.96 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:09 AM PDT 24
Peak memory 218768 kb
Host smart-15071103-d7ad-421e-99f5-4bf3692246ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789341023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2789341023
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4147933722
Short name T150
Test name
Test status
Simulation time 57612195 ps
CPU time 1.1 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 224196 kb
Host smart-00ebc24f-69b8-4d9f-83fb-150289fe2120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147933722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4147933722
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1275618777
Short name T410
Test name
Test status
Simulation time 87585430 ps
CPU time 3.33 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:56 AM PDT 24
Peak memory 219804 kb
Host smart-10fab55a-0e39-43ba-86d2-d1f353397c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275618777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1275618777
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1433398096
Short name T870
Test name
Test status
Simulation time 33107674 ps
CPU time 0.86 seconds
Started Jul 01 11:10:13 AM PDT 24
Finished Jul 01 11:10:14 AM PDT 24
Peak memory 215976 kb
Host smart-bfa55a19-beaf-4e3f-a9e0-21ad125287f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433398096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1433398096
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.939439971
Short name T346
Test name
Test status
Simulation time 18724533 ps
CPU time 1.02 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 215636 kb
Host smart-8a6a76e8-9645-4c8d-bbbc-32b1d31b2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939439971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.939439971
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.104502580
Short name T947
Test name
Test status
Simulation time 215857868 ps
CPU time 2.58 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 215668 kb
Host smart-18ba502a-5bdb-4b2a-a976-820d37fa9c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104502580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.104502580
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2021660297
Short name T617
Test name
Test status
Simulation time 42562631907 ps
CPU time 1024.53 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:27:20 AM PDT 24
Peak memory 224080 kb
Host smart-d82f688c-727d-424a-beb7-ec678f035d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021660297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2021660297
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2273974327
Short name T510
Test name
Test status
Simulation time 42732118 ps
CPU time 1.14 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 220684 kb
Host smart-005782ef-e5a2-4bb5-a03b-e1b573076220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273974327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2273974327
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1093455573
Short name T676
Test name
Test status
Simulation time 27159261 ps
CPU time 1.32 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 220352 kb
Host smart-1ee87798-f23e-4466-9b72-648aaf1e8ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093455573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1093455573
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.983576774
Short name T770
Test name
Test status
Simulation time 46917446 ps
CPU time 1.21 seconds
Started Jul 01 11:11:41 AM PDT 24
Finished Jul 01 11:11:48 AM PDT 24
Peak memory 219088 kb
Host smart-3366f939-5c42-4ad1-a520-947bc0fa0f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983576774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.983576774
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.5796928
Short name T533
Test name
Test status
Simulation time 81134700 ps
CPU time 2.79 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 217784 kb
Host smart-bc09b93e-c1a2-467e-9b10-ebabc622b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5796928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.5796928
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1390650421
Short name T23
Test name
Test status
Simulation time 27137248 ps
CPU time 1.23 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220276 kb
Host smart-27a13453-47f1-492e-ad8a-ed3ec8f6fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390650421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1390650421
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4115000199
Short name T82
Test name
Test status
Simulation time 64924887 ps
CPU time 1.08 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 219076 kb
Host smart-47bb88ed-98c5-4ae7-9bed-6c2bc6e8f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115000199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4115000199
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.780038139
Short name T977
Test name
Test status
Simulation time 22714998 ps
CPU time 1.12 seconds
Started Jul 01 11:11:35 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 218884 kb
Host smart-2f13011e-4797-42de-8620-286e0bb7ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780038139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.780038139
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1310942757
Short name T973
Test name
Test status
Simulation time 166501796 ps
CPU time 1.65 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 219032 kb
Host smart-97f7bf2f-8b01-4cc2-a63e-d77873e5b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310942757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1310942757
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2515739045
Short name T175
Test name
Test status
Simulation time 201900020 ps
CPU time 1.22 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 220604 kb
Host smart-3b2c5392-7051-4dea-a5bf-73f121a84cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515739045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2515739045
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2776380246
Short name T230
Test name
Test status
Simulation time 72447729 ps
CPU time 1.1 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 218016 kb
Host smart-aaefc80a-adab-4b27-8e39-dd282898397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776380246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2776380246
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.801498537
Short name T797
Test name
Test status
Simulation time 25315013 ps
CPU time 1.19 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 220036 kb
Host smart-3a023455-7a5b-4f77-b0cd-3cf2f8ace02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801498537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.801498537
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.488991010
Short name T442
Test name
Test status
Simulation time 32261160 ps
CPU time 1.21 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 218744 kb
Host smart-906358ca-5162-41a6-8fd3-d57dc7040ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488991010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.488991010
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2239031051
Short name T627
Test name
Test status
Simulation time 23542821 ps
CPU time 1.13 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 220076 kb
Host smart-b181fc98-0a45-49d0-ab4e-134cb0e0b147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239031051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2239031051
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.4258903957
Short name T449
Test name
Test status
Simulation time 48187231 ps
CPU time 1.26 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 219156 kb
Host smart-cba161a4-994f-4ad1-80e8-70808f1718da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258903957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4258903957
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2039647950
Short name T89
Test name
Test status
Simulation time 166136614 ps
CPU time 1.22 seconds
Started Jul 01 11:11:45 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 219960 kb
Host smart-abe625dd-6314-47fc-9c45-568d73688668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039647950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2039647950
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1431178907
Short name T750
Test name
Test status
Simulation time 210189638 ps
CPU time 3.07 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:47 AM PDT 24
Peak memory 220108 kb
Host smart-b875c0d1-f258-481f-b243-84b7183cf0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431178907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1431178907
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2964136381
Short name T688
Test name
Test status
Simulation time 149753436 ps
CPU time 1.2 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 215988 kb
Host smart-3e762e9e-b832-45cc-a8af-f5b661a4feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964136381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2964136381
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3920609832
Short name T12
Test name
Test status
Simulation time 75182513 ps
CPU time 1.53 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 220224 kb
Host smart-598700e9-030d-46c3-be63-152c177581ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920609832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3920609832
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2662895426
Short name T464
Test name
Test status
Simulation time 21594654 ps
CPU time 1.11 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 218676 kb
Host smart-0483d9de-ea82-4db4-9b06-6c31bc7a2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662895426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2662895426
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.725391409
Short name T720
Test name
Test status
Simulation time 44744034 ps
CPU time 1.76 seconds
Started Jul 01 11:11:15 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 218880 kb
Host smart-6f79fa37-f7b9-4cec-844c-bb0cbc6bb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725391409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.725391409
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3378437151
Short name T686
Test name
Test status
Simulation time 420616827 ps
CPU time 1.35 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:54 AM PDT 24
Peak memory 218696 kb
Host smart-e4d6ef6d-8a49-46f6-b79b-e588ffa2883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378437151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3378437151
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2861244888
Short name T683
Test name
Test status
Simulation time 12353745 ps
CPU time 0.84 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:18 AM PDT 24
Peak memory 206992 kb
Host smart-dbd314bb-6a1f-40db-8c7f-a3f44bfc3450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861244888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2861244888
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1413666106
Short name T701
Test name
Test status
Simulation time 28274823 ps
CPU time 0.9 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:21 AM PDT 24
Peak memory 216552 kb
Host smart-890fb119-516b-4f30-a04f-54b75e5cd82e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413666106 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1413666106
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1383040489
Short name T162
Test name
Test status
Simulation time 89653474 ps
CPU time 1.06 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 217224 kb
Host smart-dd54ca9c-9661-4e60-b82a-5bf6b3fecfae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383040489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1383040489
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1631729733
Short name T748
Test name
Test status
Simulation time 33985635 ps
CPU time 1.03 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:16 AM PDT 24
Peak memory 224388 kb
Host smart-eb40dba3-84ef-4812-b725-59da12dd76ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631729733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1631729733
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1181986908
Short name T929
Test name
Test status
Simulation time 57487334 ps
CPU time 1.47 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 218664 kb
Host smart-1a500d44-94d5-4a95-a74f-0ad02f293986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181986908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1181986908
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2682005589
Short name T736
Test name
Test status
Simulation time 46935107 ps
CPU time 0.92 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215632 kb
Host smart-1759717b-4702-4dfd-b376-bd231efc4938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682005589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2682005589
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.41005298
Short name T436
Test name
Test status
Simulation time 517055877 ps
CPU time 3.43 seconds
Started Jul 01 11:09:55 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 217664 kb
Host smart-2f74edc5-1366-47aa-bd56-db836f64db32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005298 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.41005298
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.934978481
Short name T136
Test name
Test status
Simulation time 54693708 ps
CPU time 1.31 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 220340 kb
Host smart-b977e288-9447-4b14-998e-29a03d74992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934978481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.934978481
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1384167627
Short name T406
Test name
Test status
Simulation time 247699791 ps
CPU time 3.39 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:03 AM PDT 24
Peak memory 219960 kb
Host smart-4e586b79-8b90-4bb5-b585-cc0a83727957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384167627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1384167627
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3401120222
Short name T335
Test name
Test status
Simulation time 40271780 ps
CPU time 1.07 seconds
Started Jul 01 11:12:00 AM PDT 24
Finished Jul 01 11:12:17 AM PDT 24
Peak memory 218952 kb
Host smart-1ae25fb3-8fdd-447c-9cb0-18e1cbf68f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401120222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3401120222
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.233054797
Short name T673
Test name
Test status
Simulation time 45714941 ps
CPU time 1.51 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 218896 kb
Host smart-b92f4581-3348-4a3f-9da0-b10ed692b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233054797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.233054797
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3626018411
Short name T630
Test name
Test status
Simulation time 134210524 ps
CPU time 1.17 seconds
Started Jul 01 11:11:42 AM PDT 24
Finished Jul 01 11:11:50 AM PDT 24
Peak memory 219916 kb
Host smart-7f0b6b5e-4972-4226-adc6-8c78d8a45e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626018411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3626018411
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2464163805
Short name T570
Test name
Test status
Simulation time 52410175 ps
CPU time 1.83 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 219000 kb
Host smart-5b76a967-1622-43a4-8aa3-b8da5a86e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464163805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2464163805
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2255197973
Short name T964
Test name
Test status
Simulation time 54439535 ps
CPU time 1.25 seconds
Started Jul 01 11:11:53 AM PDT 24
Finished Jul 01 11:12:03 AM PDT 24
Peak memory 219112 kb
Host smart-05358fb7-6f4a-4cda-aa07-aac0d3d8bdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255197973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2255197973
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.195928250
Short name T768
Test name
Test status
Simulation time 78281378 ps
CPU time 1.02 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 220160 kb
Host smart-d0d7b3bf-ff15-4521-aae0-cf9fd2d9b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195928250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.195928250
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.931706626
Short name T439
Test name
Test status
Simulation time 867089650 ps
CPU time 6.95 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:32 AM PDT 24
Peak memory 219180 kb
Host smart-ac14fb95-152c-467a-adb5-8661571d017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931706626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.931706626
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.225448528
Short name T820
Test name
Test status
Simulation time 49371489 ps
CPU time 1.21 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 219888 kb
Host smart-ad8ba2c3-32dd-4b9f-94a3-598b239c5370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225448528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.225448528
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.2350592457
Short name T176
Test name
Test status
Simulation time 20983621 ps
CPU time 1.18 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220084 kb
Host smart-48125316-e7c9-4895-8d7c-70341b7ab83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350592457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2350592457
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.683986067
Short name T654
Test name
Test status
Simulation time 122165268 ps
CPU time 1.12 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 217724 kb
Host smart-03cd0492-fcb6-4151-9b1d-3a3a12853f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683986067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.683986067
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3867341110
Short name T728
Test name
Test status
Simulation time 28970827 ps
CPU time 1.24 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 220168 kb
Host smart-176c1320-e70f-416b-a8d9-7a34c4171a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867341110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3867341110
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2898524077
Short name T657
Test name
Test status
Simulation time 70636725 ps
CPU time 1.43 seconds
Started Jul 01 11:11:30 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 218928 kb
Host smart-d5701941-a063-49f4-8d0c-c58394bfb2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898524077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2898524077
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2182565713
Short name T106
Test name
Test status
Simulation time 89196191 ps
CPU time 1.2 seconds
Started Jul 01 11:11:29 AM PDT 24
Finished Jul 01 11:11:32 AM PDT 24
Peak memory 218768 kb
Host smart-b3522347-c297-4506-9cf9-a84cec6abc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182565713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2182565713
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.623157181
Short name T486
Test name
Test status
Simulation time 219758567 ps
CPU time 1.26 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:23 AM PDT 24
Peak memory 219088 kb
Host smart-1b39fab7-fc6a-4913-bf1d-a2aebeea6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623157181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.623157181
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3223799826
Short name T955
Test name
Test status
Simulation time 53219939 ps
CPU time 1.21 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:18 AM PDT 24
Peak memory 220260 kb
Host smart-202b786e-ff34-473f-bf48-774b182586b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223799826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3223799826
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2940573768
Short name T781
Test name
Test status
Simulation time 102629969 ps
CPU time 1.2 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 217688 kb
Host smart-b0be3254-4de8-4301-bd77-e8fdd256c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940573768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2940573768
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1864201970
Short name T186
Test name
Test status
Simulation time 130347034 ps
CPU time 1.11 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 218852 kb
Host smart-0bf52658-60b3-4061-9aa1-4da44df087dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864201970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1864201970
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3163479964
Short name T249
Test name
Test status
Simulation time 30294729 ps
CPU time 0.94 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 215432 kb
Host smart-69b4d405-601f-4770-b0e3-5516a8666338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163479964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3163479964
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.614865877
Short name T154
Test name
Test status
Simulation time 18999224 ps
CPU time 0.99 seconds
Started Jul 01 11:09:53 AM PDT 24
Finished Jul 01 11:09:55 AM PDT 24
Peak memory 217312 kb
Host smart-09faea6f-69ce-40d0-9500-7eb7572fd73b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614865877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.614865877
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4075922297
Short name T514
Test name
Test status
Simulation time 25399444 ps
CPU time 0.93 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:03 AM PDT 24
Peak memory 219008 kb
Host smart-a05ec9dc-8d42-4c61-be96-fb98c8b0989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075922297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4075922297
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3005141573
Short name T695
Test name
Test status
Simulation time 44087567 ps
CPU time 1.26 seconds
Started Jul 01 11:09:59 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 218680 kb
Host smart-622c5da5-bc58-43c2-ab96-094dec9bc540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005141573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3005141573
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1850152156
Short name T920
Test name
Test status
Simulation time 23886962 ps
CPU time 0.99 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 216188 kb
Host smart-563be5a2-ab53-490f-b065-d7c1b2fb4f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850152156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1850152156
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.855995696
Short name T547
Test name
Test status
Simulation time 23944807 ps
CPU time 0.95 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 215616 kb
Host smart-dfaed811-744f-4569-9760-f571ef8a49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855995696 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.855995696
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3341599730
Short name T907
Test name
Test status
Simulation time 495387664 ps
CPU time 2.83 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 217420 kb
Host smart-420c6550-19fe-46fe-adfa-0fe736085dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341599730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3341599730
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1223742206
Short name T965
Test name
Test status
Simulation time 151418878922 ps
CPU time 308.92 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:15:18 AM PDT 24
Peak memory 224096 kb
Host smart-be11edb9-1a3b-45eb-a06f-74ee109e2386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223742206 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1223742206
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4089601564
Short name T147
Test name
Test status
Simulation time 66031190 ps
CPU time 1.17 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220960 kb
Host smart-562f4845-dd22-4df0-9e78-40327d717c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089601564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4089601564
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.902333309
Short name T516
Test name
Test status
Simulation time 32585321 ps
CPU time 1.42 seconds
Started Jul 01 11:11:23 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 219084 kb
Host smart-515d507e-63f6-4dc9-bf1e-5f19edcbda6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902333309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.902333309
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3119107977
Short name T261
Test name
Test status
Simulation time 89403427 ps
CPU time 1.23 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:59 AM PDT 24
Peak memory 218744 kb
Host smart-ffae4b53-3086-410d-966b-f5c5d1f5897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119107977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3119107977
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3627165022
Short name T80
Test name
Test status
Simulation time 79377392 ps
CPU time 1.18 seconds
Started Jul 01 11:11:41 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 217616 kb
Host smart-0b3918d2-c147-4374-804a-7e6b19d7061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627165022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3627165022
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2876065972
Short name T159
Test name
Test status
Simulation time 259591326 ps
CPU time 1.24 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220092 kb
Host smart-017a734b-00d1-4bbe-a244-41d9c3c1dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876065972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2876065972
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2438991942
Short name T919
Test name
Test status
Simulation time 37669898 ps
CPU time 1.67 seconds
Started Jul 01 11:11:43 AM PDT 24
Finished Jul 01 11:11:51 AM PDT 24
Peak memory 217896 kb
Host smart-a7d3740e-c5c6-4169-ba7b-8982ecda48bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438991942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2438991942
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.4119716212
Short name T982
Test name
Test status
Simulation time 22456083 ps
CPU time 1.23 seconds
Started Jul 01 11:11:47 AM PDT 24
Finished Jul 01 11:11:56 AM PDT 24
Peak memory 219576 kb
Host smart-d874d451-bbb1-4a6d-87b2-a82b01c1098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119716212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4119716212
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1775911505
Short name T378
Test name
Test status
Simulation time 66971696 ps
CPU time 1.05 seconds
Started Jul 01 11:11:44 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 219188 kb
Host smart-4835e210-d81e-4a87-98a9-292b8a82bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775911505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1775911505
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2772513907
Short name T953
Test name
Test status
Simulation time 48245179 ps
CPU time 1.13 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 216008 kb
Host smart-03f57f6e-b115-44a9-b0f1-624d677b6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772513907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2772513907
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.817971811
Short name T754
Test name
Test status
Simulation time 41266597 ps
CPU time 1.52 seconds
Started Jul 01 11:11:44 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 219636 kb
Host smart-5c2a9fd5-d38d-4773-b4b3-488595c1e3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817971811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.817971811
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.570322461
Short name T263
Test name
Test status
Simulation time 91478985 ps
CPU time 1.23 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 219076 kb
Host smart-326dfec3-5c26-4713-8cdd-177744df7bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570322461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.570322461
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1309469123
Short name T365
Test name
Test status
Simulation time 99486548 ps
CPU time 1.04 seconds
Started Jul 01 11:11:24 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 217444 kb
Host smart-bb7028bf-42c0-46f7-bff1-a54c4d99dc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309469123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1309469123
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2269772418
Short name T361
Test name
Test status
Simulation time 40114970 ps
CPU time 1.16 seconds
Started Jul 01 11:11:16 AM PDT 24
Finished Jul 01 11:11:22 AM PDT 24
Peak memory 219116 kb
Host smart-cef233e6-c5b6-4eda-99e1-c7a79ad21ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269772418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2269772418
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3069092161
Short name T188
Test name
Test status
Simulation time 58304659 ps
CPU time 0.97 seconds
Started Jul 01 11:11:59 AM PDT 24
Finished Jul 01 11:12:09 AM PDT 24
Peak memory 219000 kb
Host smart-e8572f76-a4e9-4c85-959b-b0b83bd4c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069092161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3069092161
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.381060759
Short name T672
Test name
Test status
Simulation time 84730661 ps
CPU time 1.48 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 218636 kb
Host smart-9a5916d9-9934-4ff9-a4ed-93dab9c8c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381060759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.381060759
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2039860189
Short name T333
Test name
Test status
Simulation time 82358367 ps
CPU time 1.16 seconds
Started Jul 01 11:11:35 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 218840 kb
Host smart-c4730d8e-f6d9-4d62-9233-112f045add81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039860189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2039860189
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3102408818
Short name T428
Test name
Test status
Simulation time 63734562 ps
CPU time 1.15 seconds
Started Jul 01 11:11:23 AM PDT 24
Finished Jul 01 11:11:27 AM PDT 24
Peak memory 217556 kb
Host smart-6987bee4-816d-4114-9d9c-0838345731be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102408818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3102408818
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1238647647
Short name T868
Test name
Test status
Simulation time 40473916 ps
CPU time 1.09 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:29 AM PDT 24
Peak memory 219000 kb
Host smart-057778c8-c805-4dd7-8f38-a13bb48e6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238647647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1238647647
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.330832892
Short name T895
Test name
Test status
Simulation time 13386213 ps
CPU time 0.9 seconds
Started Jul 01 11:09:29 AM PDT 24
Finished Jul 01 11:09:36 AM PDT 24
Peak memory 207128 kb
Host smart-a4fc6110-6d15-442e-a880-e5b7927ea6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330832892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.330832892
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2382471704
Short name T592
Test name
Test status
Simulation time 13280787 ps
CPU time 0.91 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 216876 kb
Host smart-ebd6c76c-2f5a-4fd6-9293-d2431bb9a7db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382471704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2382471704
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3726518766
Short name T716
Test name
Test status
Simulation time 90923609 ps
CPU time 1.13 seconds
Started Jul 01 11:09:49 AM PDT 24
Finished Jul 01 11:09:51 AM PDT 24
Peak memory 218692 kb
Host smart-dc02c35b-0266-48f4-ae7d-db29929433d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726518766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3726518766
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.3148468094
Short name T634
Test name
Test status
Simulation time 131729285 ps
CPU time 2.91 seconds
Started Jul 01 11:09:54 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 217888 kb
Host smart-40f9cfc0-784f-47da-a15e-d4b339c635d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148468094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3148468094
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1922577568
Short name T512
Test name
Test status
Simulation time 21131653 ps
CPU time 1.03 seconds
Started Jul 01 11:09:24 AM PDT 24
Finished Jul 01 11:09:26 AM PDT 24
Peak memory 215860 kb
Host smart-6b49787a-f493-499a-8651-6d8329bff312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922577568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1922577568
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1774313597
Short name T885
Test name
Test status
Simulation time 17440193 ps
CPU time 0.96 seconds
Started Jul 01 11:09:34 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 207364 kb
Host smart-4d7d3289-a672-44f2-9662-1d747d181c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774313597 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1774313597
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.902593170
Short name T500
Test name
Test status
Simulation time 19088725 ps
CPU time 1 seconds
Started Jul 01 11:09:23 AM PDT 24
Finished Jul 01 11:09:25 AM PDT 24
Peak memory 207364 kb
Host smart-eac158d1-1557-4516-8413-715bec9a92c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902593170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.902593170
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4155779085
Short name T862
Test name
Test status
Simulation time 738952748 ps
CPU time 2.26 seconds
Started Jul 01 11:09:30 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 215620 kb
Host smart-7a7a4aed-52aa-420a-b8ab-de1c60fb8f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155779085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4155779085
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.920126760
Short name T873
Test name
Test status
Simulation time 49186634757 ps
CPU time 324.54 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:15:01 AM PDT 24
Peak memory 218776 kb
Host smart-fe88dade-c834-4e2e-a8b9-aacf10302f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920126760 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.920126760
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3424564402
Short name T228
Test name
Test status
Simulation time 80922136 ps
CPU time 1.13 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 221368 kb
Host smart-6fe3f7d1-aa2d-496e-9ff7-c436a04c5512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424564402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3424564402
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1108999914
Short name T430
Test name
Test status
Simulation time 54619385 ps
CPU time 0.99 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 207064 kb
Host smart-450d10e5-417c-4a6b-9ec1-2676603dce2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108999914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1108999914
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3333894340
Short name T287
Test name
Test status
Simulation time 24250199 ps
CPU time 1.08 seconds
Started Jul 01 11:09:59 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 218816 kb
Host smart-6c13e4bf-bb59-4760-a2d4-d9a8a1623a27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333894340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3333894340
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2321082186
Short name T723
Test name
Test status
Simulation time 73461606 ps
CPU time 1.16 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 225912 kb
Host smart-7d874eec-5359-4586-873d-a61a25d57754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321082186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2321082186
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2581264608
Short name T647
Test name
Test status
Simulation time 287434706 ps
CPU time 3.93 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 217716 kb
Host smart-f5ea59bc-7c38-40ef-814f-df66e32a3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581264608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2581264608
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3876708663
Short name T55
Test name
Test status
Simulation time 39963201 ps
CPU time 0.97 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 224208 kb
Host smart-637cc0a2-d5a3-441e-a330-43153d1549cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876708663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3876708663
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2393535801
Short name T28
Test name
Test status
Simulation time 38941955 ps
CPU time 1 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 215640 kb
Host smart-b6183e60-cfa4-43af-ac85-04d53a797b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393535801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2393535801
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3869755300
Short name T52
Test name
Test status
Simulation time 844392625 ps
CPU time 3.29 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 215704 kb
Host smart-a2b042a4-0eaf-4a49-a7db-cd5f814aa8ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869755300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3869755300
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2800502506
Short name T231
Test name
Test status
Simulation time 324491434977 ps
CPU time 1092.77 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:28:32 AM PDT 24
Peak memory 222748 kb
Host smart-a83f5a30-1c0a-45d3-afa4-5462ccb6d676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800502506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2800502506
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4010761883
Short name T433
Test name
Test status
Simulation time 74147898 ps
CPU time 1.14 seconds
Started Jul 01 11:11:44 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 219180 kb
Host smart-ac587731-81cc-4134-9691-2635c3eb463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010761883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4010761883
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.163257577
Short name T48
Test name
Test status
Simulation time 216076297 ps
CPU time 2.67 seconds
Started Jul 01 11:11:45 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 220576 kb
Host smart-dc426712-ad51-482a-8cf6-f532eabdcb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163257577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.163257577
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2132850870
Short name T685
Test name
Test status
Simulation time 66671681 ps
CPU time 2.55 seconds
Started Jul 01 11:11:45 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 220616 kb
Host smart-7e4c358e-65a1-42ee-9f29-d08d90286076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132850870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2132850870
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3926773475
Short name T832
Test name
Test status
Simulation time 46678806 ps
CPU time 1.09 seconds
Started Jul 01 11:11:35 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 218620 kb
Host smart-df01cbde-d963-4828-9d7c-0cb0f94e64b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926773475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3926773475
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3943793755
Short name T389
Test name
Test status
Simulation time 56000680 ps
CPU time 1.25 seconds
Started Jul 01 11:11:28 AM PDT 24
Finished Jul 01 11:11:31 AM PDT 24
Peak memory 217568 kb
Host smart-fd55bc27-ac2d-4d94-90b9-9b6dc4b6cef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943793755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3943793755
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.129742059
Short name T787
Test name
Test status
Simulation time 70315632 ps
CPU time 1.19 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 219176 kb
Host smart-7a2b1842-7c54-4736-b0b9-dd1ca6778ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129742059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.129742059
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1867090700
Short name T402
Test name
Test status
Simulation time 55734133 ps
CPU time 1.21 seconds
Started Jul 01 11:11:27 AM PDT 24
Finished Jul 01 11:11:29 AM PDT 24
Peak memory 217644 kb
Host smart-5a1ad771-ed8a-4395-bc28-039122fed1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867090700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1867090700
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3537609918
Short name T404
Test name
Test status
Simulation time 41344818 ps
CPU time 1.49 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:00 AM PDT 24
Peak memory 218928 kb
Host smart-dd14bd74-dbe4-4d47-ac56-89ab619d7855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537609918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3537609918
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1230650954
Short name T659
Test name
Test status
Simulation time 320223948 ps
CPU time 2.68 seconds
Started Jul 01 11:11:47 AM PDT 24
Finished Jul 01 11:11:57 AM PDT 24
Peak memory 218912 kb
Host smart-927d5651-6532-4eab-910b-4784d37c3746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230650954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1230650954
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3477699061
Short name T494
Test name
Test status
Simulation time 75713467 ps
CPU time 1.5 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 218800 kb
Host smart-109b0d97-9df5-49b7-a011-c684b1bdd6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477699061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3477699061
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.158090364
Short name T577
Test name
Test status
Simulation time 36418310 ps
CPU time 1.21 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 219956 kb
Host smart-04446013-4871-44d3-84f0-67a76071bb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158090364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.158090364
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1480552551
Short name T557
Test name
Test status
Simulation time 17617493 ps
CPU time 0.95 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 207076 kb
Host smart-860fd9ad-38c5-44a2-8cf8-1ffec1e032b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480552551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1480552551
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3318929020
Short name T574
Test name
Test status
Simulation time 27514999 ps
CPU time 0.81 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 216296 kb
Host smart-741900d7-6a09-4c8a-8401-42449c9df582
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318929020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3318929020
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2872779782
Short name T208
Test name
Test status
Simulation time 118694482 ps
CPU time 1.19 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 217224 kb
Host smart-caa4caf2-4bb7-4ea0-9b9a-1b50c3bfd055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872779782 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2872779782
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3223301983
Short name T161
Test name
Test status
Simulation time 26488934 ps
CPU time 1.15 seconds
Started Jul 01 11:09:56 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 229892 kb
Host smart-88df39e4-82bf-4855-a2f8-94bc2448c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223301983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3223301983
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.1460418477
Short name T37
Test name
Test status
Simulation time 22064284 ps
CPU time 0.94 seconds
Started Jul 01 11:09:59 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 216220 kb
Host smart-3a96b375-7e6f-4d83-84b0-b6107e886713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460418477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1460418477
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1075830314
Short name T544
Test name
Test status
Simulation time 20527587 ps
CPU time 0.9 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 215608 kb
Host smart-6044c760-6dd2-4a65-9aeb-125abcdd919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075830314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1075830314
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3881638107
Short name T386
Test name
Test status
Simulation time 214742341 ps
CPU time 4.45 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 215612 kb
Host smart-5a5bb43e-fb11-4b18-9b4e-c480b158b98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881638107 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3881638107
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4031375008
Short name T434
Test name
Test status
Simulation time 404972530661 ps
CPU time 2448.73 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:50:56 AM PDT 24
Peak memory 229004 kb
Host smart-43dd110f-8630-4ae6-82d4-26c8a1cb0fa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031375008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4031375008
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.553352646
Short name T664
Test name
Test status
Simulation time 77359166 ps
CPU time 1.13 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 217580 kb
Host smart-5babcfa2-248e-4166-a758-5f1af07a9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553352646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.553352646
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.732248764
Short name T828
Test name
Test status
Simulation time 35283216 ps
CPU time 1.32 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 220276 kb
Host smart-43f5f35b-66b4-4f30-8f54-26622869c76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732248764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.732248764
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4263378766
Short name T312
Test name
Test status
Simulation time 37337758 ps
CPU time 1.26 seconds
Started Jul 01 11:11:18 AM PDT 24
Finished Jul 01 11:11:25 AM PDT 24
Peak memory 219168 kb
Host smart-3f8874ef-8339-4aec-b63c-0895d9f0da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263378766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4263378766
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2156309382
Short name T738
Test name
Test status
Simulation time 94133524 ps
CPU time 1.31 seconds
Started Jul 01 11:11:30 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 219108 kb
Host smart-670b9d16-dcab-4a69-a52c-e87377d07f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156309382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2156309382
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3485892711
Short name T822
Test name
Test status
Simulation time 38107583 ps
CPU time 1.36 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 217724 kb
Host smart-c340f256-dc31-41ff-b43e-9d6399f61fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485892711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3485892711
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3866677358
Short name T978
Test name
Test status
Simulation time 65371426 ps
CPU time 1 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 217704 kb
Host smart-6894bf2c-7e4d-48af-a4b6-a3bd808d3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866677358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3866677358
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3266376718
Short name T668
Test name
Test status
Simulation time 40479103 ps
CPU time 1.55 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 219208 kb
Host smart-0c83894c-a76c-4b07-9382-e1b8da87774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266376718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3266376718
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4071603735
Short name T581
Test name
Test status
Simulation time 31246037 ps
CPU time 1.16 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 219084 kb
Host smart-ac17a719-3967-404b-9903-c93b6cd51336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071603735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4071603735
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1654249516
Short name T491
Test name
Test status
Simulation time 86391844 ps
CPU time 1.35 seconds
Started Jul 01 11:11:30 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 219200 kb
Host smart-236b8a53-9409-4c63-b8f6-cef655b14557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654249516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1654249516
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1096515013
Short name T488
Test name
Test status
Simulation time 103166479 ps
CPU time 1.14 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 217600 kb
Host smart-a9e0b4b9-5f2f-41e8-99a6-eda877ce066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096515013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1096515013
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1814117893
Short name T108
Test name
Test status
Simulation time 27077182 ps
CPU time 1.27 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 219148 kb
Host smart-4881b739-7f95-4a6c-953b-682435284f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814117893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1814117893
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2473824562
Short name T565
Test name
Test status
Simulation time 39142557 ps
CPU time 0.82 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 206856 kb
Host smart-546c8e36-43e5-4d8d-8a40-a09f42527d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473824562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2473824562
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1680247235
Short name T424
Test name
Test status
Simulation time 21081583 ps
CPU time 0.86 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 215756 kb
Host smart-7444b302-75a1-405a-9da0-7ded3412cb18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680247235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1680247235
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.2383291418
Short name T622
Test name
Test status
Simulation time 32063593 ps
CPU time 1.07 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 224236 kb
Host smart-2cd72b99-7ea7-4fc2-be00-b1d5c7557086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383291418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2383291418
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1037156166
Short name T615
Test name
Test status
Simulation time 43200104 ps
CPU time 1.46 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 220008 kb
Host smart-8c9cfe6b-a834-4d3c-85ec-109d3e86c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037156166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1037156166
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1655399994
Short name T852
Test name
Test status
Simulation time 27969987 ps
CPU time 0.87 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 216108 kb
Host smart-b5065381-6ccf-477b-b533-1091a5c82883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655399994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1655399994
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1222022366
Short name T441
Test name
Test status
Simulation time 39505193 ps
CPU time 0.84 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 215724 kb
Host smart-ef574fc2-8030-4f79-8dd1-329dc0abaa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222022366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1222022366
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2298672130
Short name T579
Test name
Test status
Simulation time 165966482 ps
CPU time 1.43 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 217784 kb
Host smart-84b4ef32-18bf-4e99-a213-fdb630cc99ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298672130 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2298672130
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1426611986
Short name T236
Test name
Test status
Simulation time 63084157651 ps
CPU time 652.21 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:21:17 AM PDT 24
Peak memory 218912 kb
Host smart-772aacb5-4a42-43dd-be39-15ac1bdf16e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426611986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1426611986
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3297492742
Short name T369
Test name
Test status
Simulation time 42877413 ps
CPU time 1.16 seconds
Started Jul 01 11:11:51 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 218788 kb
Host smart-95e0ca84-2ab9-49a2-be5a-05b393d38faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297492742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3297492742
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3962717174
Short name T812
Test name
Test status
Simulation time 140705280 ps
CPU time 1.28 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:36 AM PDT 24
Peak memory 220360 kb
Host smart-333eb6d9-0d67-4b9f-9285-d95034ab0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962717174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3962717174
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2970857019
Short name T487
Test name
Test status
Simulation time 27237989 ps
CPU time 1.11 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 217616 kb
Host smart-85662e2e-e378-497e-8b3b-c93190e71a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970857019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2970857019
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.11569508
Short name T381
Test name
Test status
Simulation time 73682440 ps
CPU time 1.06 seconds
Started Jul 01 11:11:48 AM PDT 24
Finished Jul 01 11:11:57 AM PDT 24
Peak memory 217508 kb
Host smart-2ba65067-6591-40bb-8833-2718b635a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11569508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.11569508
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4113569762
Short name T641
Test name
Test status
Simulation time 135584770 ps
CPU time 2.69 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 220108 kb
Host smart-844f10b0-9cc0-4998-b7d8-3891b07b398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113569762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4113569762
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2183049379
Short name T25
Test name
Test status
Simulation time 104166572 ps
CPU time 2.43 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 220464 kb
Host smart-4e01879d-b2e3-4bb5-af63-6c85a32877e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183049379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2183049379
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3272794695
Short name T655
Test name
Test status
Simulation time 120209797 ps
CPU time 2.65 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:41 AM PDT 24
Peak memory 220600 kb
Host smart-2713b97e-f041-4dad-abf6-00ebb8dabe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272794695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3272794695
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.445809923
Short name T827
Test name
Test status
Simulation time 62854323 ps
CPU time 1.01 seconds
Started Jul 01 11:11:44 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 217696 kb
Host smart-ea1204d7-2545-4036-be3b-3eb45e044ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445809923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.445809923
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3530804009
Short name T593
Test name
Test status
Simulation time 51743490 ps
CPU time 0.95 seconds
Started Jul 01 11:11:46 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 217652 kb
Host smart-eaff07ba-1714-4188-acaa-baae4335f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530804009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3530804009
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2792579105
Short name T845
Test name
Test status
Simulation time 51050937 ps
CPU time 1.19 seconds
Started Jul 01 11:10:02 AM PDT 24
Finished Jul 01 11:10:04 AM PDT 24
Peak memory 220632 kb
Host smart-bec22f95-fdd7-4f5f-b8b0-ff5d725201cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792579105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2792579105
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.260944396
Short name T363
Test name
Test status
Simulation time 53348794 ps
CPU time 0.94 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 206972 kb
Host smart-cefe1c1d-8ad7-4bb7-9555-2d1fa6533633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260944396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.260944396
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1169724867
Short name T222
Test name
Test status
Simulation time 30394433 ps
CPU time 0.82 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 216572 kb
Host smart-6fbc1511-2908-4379-a952-8018c6c37243
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169724867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1169724867
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1051853405
Short name T507
Test name
Test status
Simulation time 39859656 ps
CPU time 1.33 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 217324 kb
Host smart-8468577c-1180-40e8-86db-d37f702111f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051853405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1051853405
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.4101025340
Short name T447
Test name
Test status
Simulation time 56706605 ps
CPU time 1.26 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 220132 kb
Host smart-8cbe7297-8d38-447c-ba15-55ec7487d095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101025340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4101025340
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.876533676
Short name T61
Test name
Test status
Simulation time 95162644 ps
CPU time 1.16 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 218808 kb
Host smart-eefb55cd-24e8-4486-951f-142db3e014ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876533676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.876533676
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.131465607
Short name T717
Test name
Test status
Simulation time 29928449 ps
CPU time 0.97 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 215704 kb
Host smart-3184480d-26eb-49f7-89ec-01eef4943673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131465607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.131465607
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3691256956
Short name T479
Test name
Test status
Simulation time 23643306 ps
CPU time 0.9 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 215508 kb
Host smart-6b708da5-1d2b-4631-9f91-10542c003507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691256956 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3691256956
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.427449162
Short name T662
Test name
Test status
Simulation time 49469322 ps
CPU time 1.51 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 217676 kb
Host smart-5ee91280-5569-4525-88ec-8f4f8ddb742a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427449162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.427449162
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2168400297
Short name T392
Test name
Test status
Simulation time 357553634054 ps
CPU time 1286.54 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:31:37 AM PDT 24
Peak memory 224788 kb
Host smart-23175c26-20ca-42f6-83f4-9c59916c0cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168400297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2168400297
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3948235197
Short name T327
Test name
Test status
Simulation time 85971829 ps
CPU time 1.29 seconds
Started Jul 01 11:11:48 AM PDT 24
Finished Jul 01 11:11:57 AM PDT 24
Peak memory 219276 kb
Host smart-63c9c18a-0f03-4e9a-9e15-7868b3d57a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948235197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3948235197
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3271523318
Short name T324
Test name
Test status
Simulation time 103068870 ps
CPU time 1.59 seconds
Started Jul 01 11:11:35 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 219220 kb
Host smart-3d6d280f-1360-437a-bf35-559201e6c99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271523318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3271523318
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.264921998
Short name T858
Test name
Test status
Simulation time 59820084 ps
CPU time 2.23 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:42 AM PDT 24
Peak memory 219684 kb
Host smart-ce1d1614-fc78-4f0f-8c39-aea4126713cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264921998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.264921998
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3308345132
Short name T399
Test name
Test status
Simulation time 90210459 ps
CPU time 1.27 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:38 AM PDT 24
Peak memory 220328 kb
Host smart-1d256534-c07a-4b9c-827b-d4a41fd6d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308345132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3308345132
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4175575522
Short name T857
Test name
Test status
Simulation time 68020608 ps
CPU time 1.35 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:38 AM PDT 24
Peak memory 217484 kb
Host smart-6d0ee180-faad-4abf-b6c0-e2b71878bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175575522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4175575522
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.380177986
Short name T358
Test name
Test status
Simulation time 43336969 ps
CPU time 1.51 seconds
Started Jul 01 11:11:46 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 218680 kb
Host smart-a434a3b4-2243-4bda-99e6-24ef2857b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380177986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.380177986
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3142089281
Short name T515
Test name
Test status
Simulation time 131261559 ps
CPU time 1.25 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 217544 kb
Host smart-08a43057-703d-4b4f-8717-dfa4bbdd9027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142089281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3142089281
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2946387588
Short name T687
Test name
Test status
Simulation time 124681589 ps
CPU time 1.01 seconds
Started Jul 01 11:11:47 AM PDT 24
Finished Jul 01 11:11:56 AM PDT 24
Peak memory 217664 kb
Host smart-54034e1a-18fa-4302-95f0-ecabee545798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946387588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2946387588
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2841568180
Short name T719
Test name
Test status
Simulation time 90506616 ps
CPU time 1.19 seconds
Started Jul 01 11:11:44 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 217604 kb
Host smart-a03fcdea-becd-4041-a08e-19b8b58366e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841568180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2841568180
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2231194340
Short name T373
Test name
Test status
Simulation time 156464682 ps
CPU time 1.01 seconds
Started Jul 01 11:11:42 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 217548 kb
Host smart-1a9ad1fc-7ae7-4372-bc62-64fb0b710d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231194340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2231194340
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.3998447861
Short name T718
Test name
Test status
Simulation time 41022336 ps
CPU time 0.85 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 215212 kb
Host smart-a2d61b52-80e5-4124-81f2-3f18b231de0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998447861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3998447861
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2432629757
Short name T168
Test name
Test status
Simulation time 63906488 ps
CPU time 0.86 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 215756 kb
Host smart-10030272-1f17-4167-91d5-a69434ca2189
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432629757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2432629757
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1292125952
Short name T550
Test name
Test status
Simulation time 85941498 ps
CPU time 1.15 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 217288 kb
Host smart-89d3fce1-83e3-45ee-afb7-15f12a495ce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292125952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1292125952
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1912314770
Short name T7
Test name
Test status
Simulation time 97619171 ps
CPU time 0.96 seconds
Started Jul 01 11:10:08 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 219024 kb
Host smart-fd2636b8-ce4b-4b31-945e-4659113ee4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912314770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1912314770
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4198027762
Short name T532
Test name
Test status
Simulation time 45612503 ps
CPU time 1.47 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 217548 kb
Host smart-48171fb5-53fc-46aa-b210-cd7aa8c5e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198027762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4198027762
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2730236595
Short name T894
Test name
Test status
Simulation time 27234071 ps
CPU time 0.96 seconds
Started Jul 01 11:10:12 AM PDT 24
Finished Jul 01 11:10:13 AM PDT 24
Peak memory 215864 kb
Host smart-2911d8dd-d72d-4e90-8573-afdd17021169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730236595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2730236595
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3873533923
Short name T527
Test name
Test status
Simulation time 16307327 ps
CPU time 0.98 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 215628 kb
Host smart-607efb67-8af8-425a-92f0-8ceb5ef16cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873533923 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3873533923
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4074596646
Short name T352
Test name
Test status
Simulation time 845874816 ps
CPU time 2.46 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 217528 kb
Host smart-7d2aeb3c-f2d9-4e4d-834e-4a2d2c180be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074596646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4074596646
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2691983489
Short name T232
Test name
Test status
Simulation time 31275438935 ps
CPU time 756.2 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:22:47 AM PDT 24
Peak memory 218412 kb
Host smart-5daa2cfb-c411-42ad-afdf-95a407cdee64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691983489 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2691983489
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.728647699
Short name T829
Test name
Test status
Simulation time 27003475 ps
CPU time 1.26 seconds
Started Jul 01 11:11:31 AM PDT 24
Finished Jul 01 11:11:34 AM PDT 24
Peak memory 218740 kb
Host smart-0a1f7904-cb85-4b29-88c5-b67f7c339af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728647699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.728647699
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3137544765
Short name T474
Test name
Test status
Simulation time 35217752 ps
CPU time 1.38 seconds
Started Jul 01 11:11:35 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 217672 kb
Host smart-e6e740f4-f48c-4607-8c54-80c329cc236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137544765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3137544765
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1019271244
Short name T669
Test name
Test status
Simulation time 64911385 ps
CPU time 1.15 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 217948 kb
Host smart-303f94c4-620f-4514-af9d-ec61734d8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019271244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1019271244
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3515162727
Short name T713
Test name
Test status
Simulation time 133609084 ps
CPU time 1.7 seconds
Started Jul 01 11:11:47 AM PDT 24
Finished Jul 01 11:11:56 AM PDT 24
Peak memory 220408 kb
Host smart-c0439794-1d36-423b-8415-d45084b84009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515162727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3515162727
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3841491143
Short name T745
Test name
Test status
Simulation time 156119114 ps
CPU time 2.03 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 215588 kb
Host smart-81935025-0c88-4633-869f-54eea18c61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841491143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3841491143
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1839367967
Short name T712
Test name
Test status
Simulation time 56379407 ps
CPU time 0.9 seconds
Started Jul 01 11:11:41 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 217484 kb
Host smart-ffab78b0-6377-471f-a0c1-a27423c38440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839367967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1839367967
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3873993947
Short name T938
Test name
Test status
Simulation time 54810950 ps
CPU time 1.38 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 218996 kb
Host smart-8e77039b-f8b7-44eb-a1d6-e6173f263e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873993947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3873993947
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1759396414
Short name T597
Test name
Test status
Simulation time 71708265 ps
CPU time 1.23 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 219296 kb
Host smart-51347b7d-5804-450f-9d19-e06e01404288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759396414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1759396414
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2044541405
Short name T419
Test name
Test status
Simulation time 57416508 ps
CPU time 1.16 seconds
Started Jul 01 11:11:45 AM PDT 24
Finished Jul 01 11:11:53 AM PDT 24
Peak memory 219260 kb
Host smart-af5a40f3-344d-4bf5-909b-52c8f2b5b981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044541405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2044541405
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2703238116
Short name T416
Test name
Test status
Simulation time 33854807 ps
CPU time 1.51 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 218980 kb
Host smart-7115886b-81f6-43ad-b9f0-8c453d9bd45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703238116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2703238116
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1405409616
Short name T691
Test name
Test status
Simulation time 187938616 ps
CPU time 1.39 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 220060 kb
Host smart-4038d7a7-4ef3-4e9f-b749-5317c4d4df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405409616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1405409616
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.17987897
Short name T73
Test name
Test status
Simulation time 72526945 ps
CPU time 0.79 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 215044 kb
Host smart-0d79c870-3653-4a70-b439-7a478a113ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.17987897
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3525100286
Short name T756
Test name
Test status
Simulation time 41847976 ps
CPU time 0.87 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 216576 kb
Host smart-7848d753-09b4-42ea-af67-909df4cc55a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525100286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3525100286
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3670006966
Short name T86
Test name
Test status
Simulation time 54441378 ps
CPU time 1.05 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 217060 kb
Host smart-f6b47384-a5eb-41e6-9d12-64521341fc3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670006966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3670006966
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2705879490
Short name T123
Test name
Test status
Simulation time 82547905 ps
CPU time 0.99 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 220828 kb
Host smart-8ad0b373-b095-4f3c-8ab0-0ac8b9da5fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705879490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2705879490
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2862165673
Short name T596
Test name
Test status
Simulation time 123764012 ps
CPU time 1.5 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 217772 kb
Host smart-7aaae1ad-6e11-4b7e-b502-ca755bc7a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862165673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2862165673
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3855357671
Short name T808
Test name
Test status
Simulation time 36726334 ps
CPU time 0.85 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 215584 kb
Host smart-b92120fa-f280-40f1-a96d-52c55ea226ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855357671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3855357671
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1605230181
Short name T443
Test name
Test status
Simulation time 133342573 ps
CPU time 0.93 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 215616 kb
Host smart-aac93e69-8878-4fdd-8bc6-8f050b5e18b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605230181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1605230181
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.917828817
Short name T590
Test name
Test status
Simulation time 149318518 ps
CPU time 3.39 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 217632 kb
Host smart-d27aa244-6c1c-46f6-86bc-1db33a3efa5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917828817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.917828817
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3923856490
Short name T385
Test name
Test status
Simulation time 61246540142 ps
CPU time 787.66 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:23:26 AM PDT 24
Peak memory 221324 kb
Host smart-2cd77cf6-ff4d-4786-93a5-de4c95f1af0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923856490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3923856490
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1118200745
Short name T606
Test name
Test status
Simulation time 94997831 ps
CPU time 1.27 seconds
Started Jul 01 11:11:40 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 220188 kb
Host smart-ca2496b9-2848-4159-9fa2-8b75b6d1a6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118200745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1118200745
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.85861917
Short name T619
Test name
Test status
Simulation time 214454421 ps
CPU time 3.15 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:41 AM PDT 24
Peak memory 217820 kb
Host smart-40f1c8c1-42b3-4e60-8e25-6e80f4cecf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85861917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.85861917
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1715863893
Short name T477
Test name
Test status
Simulation time 244558020 ps
CPU time 1.31 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:44 AM PDT 24
Peak memory 220224 kb
Host smart-d704e53e-2219-4bbb-be62-8640dc57de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715863893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1715863893
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.420963486
Short name T727
Test name
Test status
Simulation time 59234217 ps
CPU time 1.22 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 217892 kb
Host smart-c53d0f35-7620-4cc9-8631-f226bd788245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420963486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.420963486
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3407314225
Short name T1
Test name
Test status
Simulation time 52726616 ps
CPU time 1.72 seconds
Started Jul 01 11:12:02 AM PDT 24
Finished Jul 01 11:12:16 AM PDT 24
Peak memory 218928 kb
Host smart-e9533568-766e-4f1e-b132-89c0444f34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407314225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3407314225
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3527395234
Short name T310
Test name
Test status
Simulation time 24852111 ps
CPU time 1.21 seconds
Started Jul 01 11:12:06 AM PDT 24
Finished Jul 01 11:12:18 AM PDT 24
Peak memory 218968 kb
Host smart-7dc19b1f-db09-4fec-bb00-a2118448f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527395234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3527395234
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1195236702
Short name T329
Test name
Test status
Simulation time 41947976 ps
CPU time 1.06 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 218840 kb
Host smart-f19d1dba-0d66-42e1-898c-bd3aa0d93c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195236702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1195236702
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1007713705
Short name T401
Test name
Test status
Simulation time 43125813 ps
CPU time 1.23 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 220324 kb
Host smart-cc5672e8-5af5-4cb9-bbf8-a512850e39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007713705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1007713705
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1443498008
Short name T519
Test name
Test status
Simulation time 90094533 ps
CPU time 1.64 seconds
Started Jul 01 11:11:56 AM PDT 24
Finished Jul 01 11:12:08 AM PDT 24
Peak memory 219120 kb
Host smart-e1e8f637-690e-4b8a-bc09-b7de386b9607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443498008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1443498008
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1597959133
Short name T454
Test name
Test status
Simulation time 22704064 ps
CPU time 1.17 seconds
Started Jul 01 11:11:54 AM PDT 24
Finished Jul 01 11:12:05 AM PDT 24
Peak memory 218860 kb
Host smart-9fe3b37f-fc3c-4380-9ffe-2df40bf44a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597959133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1597959133
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4001398899
Short name T951
Test name
Test status
Simulation time 66665927 ps
CPU time 1.14 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 219032 kb
Host smart-1c198eba-a7b2-420e-b7dc-5572cd18a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001398899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4001398899
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.466978914
Short name T943
Test name
Test status
Simulation time 43583608 ps
CPU time 0.87 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:10:13 AM PDT 24
Peak memory 206844 kb
Host smart-21545c8e-6d48-42e4-803b-5023dda68821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466978914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.466978914
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1337874123
Short name T415
Test name
Test status
Simulation time 22935665 ps
CPU time 0.9 seconds
Started Jul 01 11:10:04 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 216332 kb
Host smart-bb8fce87-4030-429a-98c4-33aab18b2e4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337874123 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1337874123
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1057758707
Short name T224
Test name
Test status
Simulation time 85268015 ps
CPU time 1.18 seconds
Started Jul 01 11:10:27 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 226080 kb
Host smart-f0867333-4503-4cbd-a07c-5831a0f17016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057758707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1057758707
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.119031397
Short name T698
Test name
Test status
Simulation time 84789853 ps
CPU time 1.13 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 219232 kb
Host smart-0a0929e2-9f9b-4a60-b97c-d8bcc88898a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119031397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.119031397
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2750458067
Short name T709
Test name
Test status
Simulation time 28872073 ps
CPU time 1.08 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 215740 kb
Host smart-3e80d82f-01ed-4c13-8991-90e96d88576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750458067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2750458067
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1713260395
Short name T355
Test name
Test status
Simulation time 178618546 ps
CPU time 0.88 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 215428 kb
Host smart-3964c5ee-dc1d-42e4-b27e-65cfb261f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713260395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1713260395
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1993858090
Short name T71
Test name
Test status
Simulation time 284173553 ps
CPU time 2.39 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 219864 kb
Host smart-e2a89eae-2d1f-4895-abf4-cfde9e323bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993858090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1993858090
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2825684013
Short name T555
Test name
Test status
Simulation time 67524031235 ps
CPU time 1638.38 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:37:45 AM PDT 24
Peak memory 226732 kb
Host smart-20c1fe43-7b0f-4a21-9d98-02df57a1d271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825684013 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2825684013
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1532981570
Short name T682
Test name
Test status
Simulation time 65698002 ps
CPU time 1.97 seconds
Started Jul 01 11:11:53 AM PDT 24
Finished Jul 01 11:12:04 AM PDT 24
Peak memory 218896 kb
Host smart-c39d2726-5cd6-4fbc-85f2-083e1b1174f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532981570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1532981570
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4109961984
Short name T779
Test name
Test status
Simulation time 69254505 ps
CPU time 1.33 seconds
Started Jul 01 11:12:02 AM PDT 24
Finished Jul 01 11:12:15 AM PDT 24
Peak memory 219096 kb
Host smart-ae3d45f9-e8bf-4a80-a139-b2c23cd3ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109961984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4109961984
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2066708568
Short name T425
Test name
Test status
Simulation time 51138570 ps
CPU time 1.24 seconds
Started Jul 01 11:11:46 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 217700 kb
Host smart-b7439d49-a634-48d5-a62a-25b7cb70b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066708568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2066708568
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1193140459
Short name T440
Test name
Test status
Simulation time 114419506 ps
CPU time 1.35 seconds
Started Jul 01 11:11:40 AM PDT 24
Finished Jul 01 11:11:48 AM PDT 24
Peak memory 219252 kb
Host smart-4c94cb99-d2e2-49cb-b37e-19186a246673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193140459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1193140459
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.757073959
Short name T408
Test name
Test status
Simulation time 92987094 ps
CPU time 1.15 seconds
Started Jul 01 11:12:03 AM PDT 24
Finished Jul 01 11:12:15 AM PDT 24
Peak memory 220132 kb
Host smart-010ce39d-d382-43be-891d-b5bb95b7728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757073959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.757073959
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2206895522
Short name T623
Test name
Test status
Simulation time 33712942 ps
CPU time 1.28 seconds
Started Jul 01 11:11:42 AM PDT 24
Finished Jul 01 11:11:50 AM PDT 24
Peak memory 217520 kb
Host smart-7d5a5827-0800-4aa9-9411-a58ac8800c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206895522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2206895522
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.498229854
Short name T294
Test name
Test status
Simulation time 61547394 ps
CPU time 1.44 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 218956 kb
Host smart-f3b5c6a4-d0b8-4892-bbbb-67a4cd3e815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498229854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.498229854
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.280811790
Short name T315
Test name
Test status
Simulation time 127624843 ps
CPU time 2.69 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 220600 kb
Host smart-d6c682eb-0dbf-4d52-bde4-5bfb3bdec5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280811790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.280811790
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1109843249
Short name T972
Test name
Test status
Simulation time 28721159 ps
CPU time 1.22 seconds
Started Jul 01 11:11:49 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 217832 kb
Host smart-d933629a-acba-44eb-817b-21f263148225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109843249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1109843249
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1736251840
Short name T360
Test name
Test status
Simulation time 40897038 ps
CPU time 1.4 seconds
Started Jul 01 11:11:56 AM PDT 24
Finished Jul 01 11:12:08 AM PDT 24
Peak memory 218748 kb
Host smart-b1b192da-4801-4a21-8567-80ed3039e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736251840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1736251840
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.560825755
Short name T146
Test name
Test status
Simulation time 73670118 ps
CPU time 1.14 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 221204 kb
Host smart-ecedb5e6-dbc5-4f1e-b524-ce67fd896c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560825755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.560825755
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4065223054
Short name T616
Test name
Test status
Simulation time 56193657 ps
CPU time 0.88 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:09 AM PDT 24
Peak memory 215224 kb
Host smart-6d76a6a7-2bf5-49cc-bd8c-cb4822c63a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065223054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4065223054
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4267412890
Short name T229
Test name
Test status
Simulation time 46694046 ps
CPU time 0.88 seconds
Started Jul 01 11:10:08 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 215632 kb
Host smart-fe2f401b-6ae1-41aa-b29f-8bef2512f58c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267412890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4267412890
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1901271633
Short name T132
Test name
Test status
Simulation time 26243066 ps
CPU time 1.05 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 217200 kb
Host smart-5fd3ec10-c90d-4f0b-88aa-6fdf11c28853
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901271633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1901271633
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.731520613
Short name T847
Test name
Test status
Simulation time 34298127 ps
CPU time 1.03 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 217636 kb
Host smart-9dc5c03c-904f-401d-a805-e3e070617a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731520613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.731520613
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3659806850
Short name T97
Test name
Test status
Simulation time 22782977 ps
CPU time 1.04 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 216068 kb
Host smart-4a587252-4400-49df-9755-df3ab0190e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659806850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3659806850
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1034762098
Short name T356
Test name
Test status
Simulation time 26194659 ps
CPU time 0.91 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 215668 kb
Host smart-f2adf386-bb3c-45c0-a01f-dc1e5d617f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034762098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1034762098
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3120920021
Short name T254
Test name
Test status
Simulation time 31182411 ps
CPU time 1.24 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:10:08 AM PDT 24
Peak memory 207452 kb
Host smart-e0a63aa6-c77d-4240-ad07-b190a04a45cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120920021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3120920021
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3975556957
Short name T483
Test name
Test status
Simulation time 244814515785 ps
CPU time 1383.94 seconds
Started Jul 01 11:10:03 AM PDT 24
Finished Jul 01 11:33:09 AM PDT 24
Peak memory 224360 kb
Host smart-a17b8721-2876-49b9-9f21-3d298413b942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975556957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3975556957
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3515164007
Short name T780
Test name
Test status
Simulation time 83944354 ps
CPU time 1.05 seconds
Started Jul 01 11:11:40 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 217532 kb
Host smart-90ec5d9b-6ae1-4d13-9316-061bcad97c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515164007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3515164007
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1474523217
Short name T318
Test name
Test status
Simulation time 42456974 ps
CPU time 1.78 seconds
Started Jul 01 11:11:58 AM PDT 24
Finished Jul 01 11:12:09 AM PDT 24
Peak memory 218836 kb
Host smart-78d24c09-0c1e-4719-98d3-fdad3280b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474523217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1474523217
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1847075355
Short name T398
Test name
Test status
Simulation time 634557761 ps
CPU time 5.79 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:48 AM PDT 24
Peak memory 220768 kb
Host smart-8bcfd573-83b5-4186-a33c-c8cb03c5c675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847075355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1847075355
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2936042912
Short name T625
Test name
Test status
Simulation time 37966528 ps
CPU time 1.3 seconds
Started Jul 01 11:11:42 AM PDT 24
Finished Jul 01 11:11:49 AM PDT 24
Peak memory 218668 kb
Host smart-48987843-1636-4de4-8f78-014e5eb3b51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936042912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2936042912
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.721366225
Short name T901
Test name
Test status
Simulation time 91793494 ps
CPU time 1.35 seconds
Started Jul 01 11:12:04 AM PDT 24
Finished Jul 01 11:12:18 AM PDT 24
Peak memory 218936 kb
Host smart-4ceaa646-6259-46d3-926d-a79b099e9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721366225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.721366225
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2236959768
Short name T526
Test name
Test status
Simulation time 46864791 ps
CPU time 1.44 seconds
Started Jul 01 11:11:53 AM PDT 24
Finished Jul 01 11:12:04 AM PDT 24
Peak memory 218868 kb
Host smart-37a35e7b-fae0-4750-8e79-121a729572be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236959768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2236959768
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.172482278
Short name T245
Test name
Test status
Simulation time 77039599 ps
CPU time 2.73 seconds
Started Jul 01 11:12:02 AM PDT 24
Finished Jul 01 11:12:24 AM PDT 24
Peak memory 220168 kb
Host smart-938818d3-bb74-42d2-b634-361ca2106a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172482278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.172482278
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3620391816
Short name T453
Test name
Test status
Simulation time 58693586 ps
CPU time 1.04 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:42 AM PDT 24
Peak memory 217500 kb
Host smart-92b6df47-d32c-44c6-8a98-288540b80933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620391816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3620391816
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3343517625
Short name T426
Test name
Test status
Simulation time 189714284 ps
CPU time 1.96 seconds
Started Jul 01 11:11:37 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 219252 kb
Host smart-d6190b32-f8e8-403b-b635-5682eb66386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343517625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3343517625
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.899169089
Short name T706
Test name
Test status
Simulation time 129198203 ps
CPU time 1.65 seconds
Started Jul 01 11:11:43 AM PDT 24
Finished Jul 01 11:11:52 AM PDT 24
Peak memory 218952 kb
Host smart-305f601b-c942-46b1-a665-05f09272688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899169089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.899169089
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1004139820
Short name T582
Test name
Test status
Simulation time 25783165 ps
CPU time 1.2 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 219084 kb
Host smart-5f3560b6-5289-4474-a408-02c8c6a98023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004139820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1004139820
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.698881557
Short name T790
Test name
Test status
Simulation time 15376905 ps
CPU time 0.89 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 207012 kb
Host smart-51f2e5db-f602-4ae6-b264-5b12ffc7dd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698881557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.698881557
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.289283748
Short name T539
Test name
Test status
Simulation time 13134391 ps
CPU time 0.9 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 216696 kb
Host smart-6ba2efe6-7916-4086-b596-a1986a4ab3b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289283748 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.289283748
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2039855066
Short name T145
Test name
Test status
Simulation time 96525867 ps
CPU time 1.05 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 218908 kb
Host smart-aa9226e8-684d-4ad3-8a3a-1f71cc1de3d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039855066 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2039855066
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1190400664
Short name T628
Test name
Test status
Simulation time 19351323 ps
CPU time 1.2 seconds
Started Jul 01 11:10:08 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 229848 kb
Host smart-28f84748-43f7-4dba-9a91-7af1819884db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190400664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1190400664
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1551098364
Short name T888
Test name
Test status
Simulation time 57193364 ps
CPU time 1.03 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 219936 kb
Host smart-16b5b416-278b-484a-aadd-e894f87be9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551098364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1551098364
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2920871876
Short name T639
Test name
Test status
Simulation time 66431636 ps
CPU time 0.86 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 215824 kb
Host smart-d229deeb-c64b-4569-bf3b-8108b6558e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920871876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2920871876
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2098162708
Short name T801
Test name
Test status
Simulation time 15723284 ps
CPU time 0.96 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215564 kb
Host smart-a4ae8d3c-2c09-4d19-a2e7-b2b8b7349c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098162708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2098162708
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1618043630
Short name T747
Test name
Test status
Simulation time 628293948 ps
CPU time 3.82 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:14 AM PDT 24
Peak memory 217832 kb
Host smart-33901a50-bed2-41d8-9073-5e1b643536d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618043630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1618043630
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.172476816
Short name T478
Test name
Test status
Simulation time 146231750 ps
CPU time 1.45 seconds
Started Jul 01 11:11:33 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 219124 kb
Host smart-d25e4cb3-8d0c-4c93-9076-1620ea6e4867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172476816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.172476816
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1179679429
Short name T897
Test name
Test status
Simulation time 52667610 ps
CPU time 1.32 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:41 AM PDT 24
Peak memory 218984 kb
Host smart-d1cc4f95-93ba-4c00-b6cc-d91e9e6b76c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179679429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1179679429
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1586770362
Short name T451
Test name
Test status
Simulation time 65985616 ps
CPU time 1.01 seconds
Started Jul 01 11:11:38 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 217648 kb
Host smart-51117236-6c32-41d5-9ca6-979f41af16a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586770362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1586770362
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1701926232
Short name T380
Test name
Test status
Simulation time 80278200 ps
CPU time 1.61 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:39 AM PDT 24
Peak memory 219024 kb
Host smart-9345f9d8-7c6c-4829-ab52-60bfc7926ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701926232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1701926232
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.4240938402
Short name T782
Test name
Test status
Simulation time 52910039 ps
CPU time 1.62 seconds
Started Jul 01 11:11:30 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 219140 kb
Host smart-6616a275-3bef-46f1-9d21-9a50bba93f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240938402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.4240938402
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.374977120
Short name T417
Test name
Test status
Simulation time 57434300 ps
CPU time 1.35 seconds
Started Jul 01 11:11:39 AM PDT 24
Finished Jul 01 11:11:46 AM PDT 24
Peak memory 220344 kb
Host smart-4002a22d-ab6c-42e4-bed1-4ef335043d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374977120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.374977120
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1659896911
Short name T819
Test name
Test status
Simulation time 41139995 ps
CPU time 1.5 seconds
Started Jul 01 11:11:47 AM PDT 24
Finished Jul 01 11:11:56 AM PDT 24
Peak memory 218756 kb
Host smart-5cd8592c-f1bc-4613-80bf-2b12783d3b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659896911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1659896911
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2312536610
Short name T3
Test name
Test status
Simulation time 61787694 ps
CPU time 1.38 seconds
Started Jul 01 11:12:05 AM PDT 24
Finished Jul 01 11:12:18 AM PDT 24
Peak memory 219208 kb
Host smart-e799f843-8037-484e-99e5-bd6f4c828539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312536610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2312536610
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3582040758
Short name T445
Test name
Test status
Simulation time 43487050 ps
CPU time 1.3 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:41 AM PDT 24
Peak memory 220252 kb
Host smart-2823820c-af42-4f1a-bf31-7c3722a03dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582040758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3582040758
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1275824295
Short name T179
Test name
Test status
Simulation time 26448878 ps
CPU time 1.22 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:09 AM PDT 24
Peak memory 219984 kb
Host smart-2b6ba84c-9db1-48c4-89fc-4b0fa38fccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275824295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1275824295
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1188311560
Short name T347
Test name
Test status
Simulation time 28944819 ps
CPU time 0.95 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215472 kb
Host smart-1c7accc5-3fa3-41dd-8468-23f1360feb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188311560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1188311560
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3335244084
Short name T94
Test name
Test status
Simulation time 14281384 ps
CPU time 0.81 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 216596 kb
Host smart-cbe51ac7-bbf1-472d-a65f-f446398b073b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335244084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3335244084
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.913497210
Short name T633
Test name
Test status
Simulation time 98485995 ps
CPU time 1.36 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 217064 kb
Host smart-00f5accd-d03b-4b4a-a69e-082e1d7b4055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913497210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.913497210
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3432255587
Short name T826
Test name
Test status
Simulation time 19851418 ps
CPU time 1.05 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 219660 kb
Host smart-c4d5c6da-9cf3-4081-b867-c8c4f839691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432255587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3432255587
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.985814802
Short name T407
Test name
Test status
Simulation time 36745965 ps
CPU time 1.4 seconds
Started Jul 01 11:10:13 AM PDT 24
Finished Jul 01 11:10:14 AM PDT 24
Peak memory 217564 kb
Host smart-e0db7e46-dc2b-4cdf-a3ae-dafb5df45670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985814802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.985814802
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3170461833
Short name T646
Test name
Test status
Simulation time 28419553 ps
CPU time 1.01 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 215752 kb
Host smart-c6544882-2f37-4918-949f-4261a81eefa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170461833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3170461833
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.695992435
Short name T637
Test name
Test status
Simulation time 20589643 ps
CPU time 1.05 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 215648 kb
Host smart-600b0d95-45aa-419d-a118-47f1fee26e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695992435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.695992435
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2224573202
Short name T481
Test name
Test status
Simulation time 649793565 ps
CPU time 4.36 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 217552 kb
Host smart-000e681c-61b2-424b-a34c-0ffb01c1e0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224573202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2224573202
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1155512668
Short name T624
Test name
Test status
Simulation time 88136486649 ps
CPU time 2164.05 seconds
Started Jul 01 11:10:13 AM PDT 24
Finished Jul 01 11:46:17 AM PDT 24
Peak memory 231020 kb
Host smart-34789174-fbfd-4b4f-b24a-c1e62166e750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155512668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1155512668
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2444873068
Short name T912
Test name
Test status
Simulation time 52857999 ps
CPU time 1.67 seconds
Started Jul 01 11:11:59 AM PDT 24
Finished Jul 01 11:12:10 AM PDT 24
Peak memory 217732 kb
Host smart-d8510a68-8ffd-4a08-b156-e21042374154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444873068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2444873068
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3717667539
Short name T904
Test name
Test status
Simulation time 284812945 ps
CPU time 2.14 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 219580 kb
Host smart-bae5039a-d0b7-443c-bf48-0a66b6c9bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717667539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3717667539
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3832318266
Short name T772
Test name
Test status
Simulation time 58605126 ps
CPU time 1.13 seconds
Started Jul 01 11:11:36 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 217668 kb
Host smart-63914b24-8f08-406d-8c39-8a226c1ed8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832318266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3832318266
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3022111012
Short name T891
Test name
Test status
Simulation time 59855084 ps
CPU time 1.32 seconds
Started Jul 01 11:12:02 AM PDT 24
Finished Jul 01 11:12:15 AM PDT 24
Peak memory 217736 kb
Host smart-e3d0d2c0-d326-442e-84c4-4b301633007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022111012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3022111012
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2392574108
Short name T892
Test name
Test status
Simulation time 110775747 ps
CPU time 1.21 seconds
Started Jul 01 11:11:59 AM PDT 24
Finished Jul 01 11:12:11 AM PDT 24
Peak memory 217548 kb
Host smart-523ddcda-63ce-4be6-9323-0fd2f83c2ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392574108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2392574108
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2694985676
Short name T990
Test name
Test status
Simulation time 42184386 ps
CPU time 1.45 seconds
Started Jul 01 11:11:43 AM PDT 24
Finished Jul 01 11:11:51 AM PDT 24
Peak memory 218980 kb
Host smart-b9871db1-24b1-4b67-be5a-24721f159aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694985676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2694985676
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1639945352
Short name T393
Test name
Test status
Simulation time 74974103 ps
CPU time 1.38 seconds
Started Jul 01 11:11:46 AM PDT 24
Finished Jul 01 11:11:55 AM PDT 24
Peak memory 218784 kb
Host smart-0254bba7-43e5-4532-b6e6-8f371ac7e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639945352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1639945352
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.731906100
Short name T438
Test name
Test status
Simulation time 48097349 ps
CPU time 1.54 seconds
Started Jul 01 11:11:43 AM PDT 24
Finished Jul 01 11:11:51 AM PDT 24
Peak memory 218800 kb
Host smart-09bf6a61-f990-4ce5-8811-1bd7f1c101f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731906100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.731906100
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.906282278
Short name T470
Test name
Test status
Simulation time 33234502 ps
CPU time 1.16 seconds
Started Jul 01 11:12:01 AM PDT 24
Finished Jul 01 11:12:12 AM PDT 24
Peak memory 218960 kb
Host smart-fd0b66d3-b17c-43a4-93e4-7d325d969748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906282278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.906282278
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3690505585
Short name T480
Test name
Test status
Simulation time 231513306 ps
CPU time 1.64 seconds
Started Jul 01 11:11:50 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 219440 kb
Host smart-7e94143a-a98c-4616-8f3c-787c465639f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690505585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3690505585
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1055315134
Short name T67
Test name
Test status
Simulation time 42586272 ps
CPU time 1.13 seconds
Started Jul 01 11:09:55 AM PDT 24
Finished Jul 01 11:09:56 AM PDT 24
Peak memory 219468 kb
Host smart-5aff50e8-62fe-42e0-8033-1d068b13d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055315134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1055315134
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2160306954
Short name T794
Test name
Test status
Simulation time 19452829 ps
CPU time 0.96 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 207012 kb
Host smart-edbfc8aa-c745-4f7b-9d69-9d4f30014ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160306954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2160306954
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.352719323
Short name T521
Test name
Test status
Simulation time 19206249 ps
CPU time 0.86 seconds
Started Jul 01 11:09:40 AM PDT 24
Finished Jul 01 11:09:41 AM PDT 24
Peak memory 215756 kb
Host smart-9b4b8fc1-3f52-4123-a206-46fe97584994
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352719323 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.352719323
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3132560453
Short name T458
Test name
Test status
Simulation time 35206942 ps
CPU time 1.25 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 216788 kb
Host smart-810d8593-730d-4f71-aa74-66dfb6d9f499
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132560453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3132560453
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2590022529
Short name T16
Test name
Test status
Simulation time 29763482 ps
CPU time 1.41 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 226080 kb
Host smart-1e3c960a-e891-4653-809d-b975b100ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590022529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2590022529
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2602543833
Short name T886
Test name
Test status
Simulation time 42038268 ps
CPU time 1.66 seconds
Started Jul 01 11:09:50 AM PDT 24
Finished Jul 01 11:09:52 AM PDT 24
Peak memory 218800 kb
Host smart-fe7488fa-c1ce-44b4-9dd3-bc01fc60906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602543833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2602543833
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.440761777
Short name T58
Test name
Test status
Simulation time 22602358 ps
CPU time 1.12 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 224316 kb
Host smart-6e477fdd-0602-4258-a4fb-7ad3a32f588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440761777 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.440761777
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3668120376
Short name T63
Test name
Test status
Simulation time 249719605 ps
CPU time 4.12 seconds
Started Jul 01 11:09:38 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 235600 kb
Host smart-98e21634-4221-4697-988a-977572588e06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668120376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3668120376
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1526219460
Short name T702
Test name
Test status
Simulation time 15121151 ps
CPU time 0.97 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 215552 kb
Host smart-f69213fb-1b06-49de-9931-537d07de730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526219460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1526219460
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2700256747
Short name T831
Test name
Test status
Simulation time 449262945 ps
CPU time 2.65 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:39 AM PDT 24
Peak memory 217700 kb
Host smart-dc86eb09-5813-488d-b988-d87fa3dab774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700256747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2700256747
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2667112766
Short name T40
Test name
Test status
Simulation time 100907082226 ps
CPU time 1208.9 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:29:45 AM PDT 24
Peak memory 225952 kb
Host smart-acfb3557-155f-4de8-9bfa-06b47387edb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667112766 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2667112766
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1519718279
Short name T264
Test name
Test status
Simulation time 432725817 ps
CPU time 1.57 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:18 AM PDT 24
Peak memory 218780 kb
Host smart-9caa112b-3183-4753-aba3-519d87dcab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519718279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1519718279
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4175211167
Short name T944
Test name
Test status
Simulation time 28624213 ps
CPU time 0.87 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 207072 kb
Host smart-b51f8d9a-0f22-48f6-9aeb-6a3dde991630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175211167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4175211167
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2913223737
Short name T173
Test name
Test status
Simulation time 14237844 ps
CPU time 0.87 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 216772 kb
Host smart-d0995055-565c-4bdd-b6e8-ec37e0c6c8ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913223737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2913223737
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1710712099
Short name T351
Test name
Test status
Simulation time 93631436 ps
CPU time 1.12 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 217332 kb
Host smart-c6a378d8-aff0-4055-9649-160b4ac0c985
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710712099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1710712099
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.3178244718
Short name T725
Test name
Test status
Simulation time 76518348 ps
CPU time 1.36 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 218932 kb
Host smart-dfc235f4-867d-4e90-911c-564d85c8db1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178244718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3178244718
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3684336671
Short name T117
Test name
Test status
Simulation time 34013944 ps
CPU time 0.9 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 215972 kb
Host smart-6f6fa377-2e0b-4eef-a58c-47953db3c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684336671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3684336671
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2004618504
Short name T815
Test name
Test status
Simulation time 27680896 ps
CPU time 0.96 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 215492 kb
Host smart-108d503e-72d4-4813-b113-9fc3d10b910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004618504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2004618504
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2886551500
Short name T594
Test name
Test status
Simulation time 38385391 ps
CPU time 0.97 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 206844 kb
Host smart-e4db5f53-bc76-4f14-97ac-eeb89c815fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886551500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2886551500
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.46182279
Short name T457
Test name
Test status
Simulation time 355782627001 ps
CPU time 2242.36 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:47:47 AM PDT 24
Peak memory 227680 kb
Host smart-6ed79292-8dd8-4005-9cb0-d9ed06d35765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46182279 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.46182279
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2630529972
Short name T302
Test name
Test status
Simulation time 78920298 ps
CPU time 1.19 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:10 AM PDT 24
Peak memory 218744 kb
Host smart-122547db-53f6-4f8b-860f-cb58f5248e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630529972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2630529972
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.901307126
Short name T110
Test name
Test status
Simulation time 65225818 ps
CPU time 0.91 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 206952 kb
Host smart-5060bfe6-477f-40c4-a5f7-572754b4356e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901307126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.901307126
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1218600203
Short name T92
Test name
Test status
Simulation time 14035329 ps
CPU time 0.87 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 216844 kb
Host smart-9306eb73-58e9-447f-bd43-e9ca0de282c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218600203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1218600203
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2343620146
Short name T599
Test name
Test status
Simulation time 65366608 ps
CPU time 1.1 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 218828 kb
Host smart-d9f70f1d-e21d-417a-b7b1-6b0e76cd3e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343620146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2343620146
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2908724547
Short name T131
Test name
Test status
Simulation time 44928752 ps
CPU time 0.98 seconds
Started Jul 01 11:10:31 AM PDT 24
Finished Jul 01 11:10:33 AM PDT 24
Peak memory 220820 kb
Host smart-8bd220c8-ad93-41d5-b731-f3ff1651637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908724547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2908724547
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4020329176
Short name T611
Test name
Test status
Simulation time 56451702 ps
CPU time 1.26 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:16 AM PDT 24
Peak memory 217604 kb
Host smart-4c59d6cf-e5f5-4fa8-ac0b-9401cf92a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020329176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4020329176
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1549389448
Short name T435
Test name
Test status
Simulation time 22281790 ps
CPU time 1.05 seconds
Started Jul 01 11:10:13 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 215764 kb
Host smart-ad1aa052-94c8-44ce-ad92-8dcff93cafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549389448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1549389448
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2711176874
Short name T971
Test name
Test status
Simulation time 48790240 ps
CPU time 0.9 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 215608 kb
Host smart-96ccc89a-9a68-4d1d-b5c2-1ed22097c220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711176874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2711176874
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2634096050
Short name T626
Test name
Test status
Simulation time 400574022 ps
CPU time 4.08 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 220524 kb
Host smart-7ef41d43-1be9-4a78-b514-2017a2f1e877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634096050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2634096050
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2579370091
Short name T930
Test name
Test status
Simulation time 72647463732 ps
CPU time 448.49 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:17:56 AM PDT 24
Peak memory 218816 kb
Host smart-a14da192-a257-4981-ba29-9be4788563b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579370091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2579370091
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2178611004
Short name T835
Test name
Test status
Simulation time 30630323 ps
CPU time 1.12 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 220212 kb
Host smart-a236ec82-0689-4b96-97ae-4957abef1055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178611004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2178611004
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3656371582
Short name T522
Test name
Test status
Simulation time 24133830 ps
CPU time 0.85 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 215080 kb
Host smart-735fdddc-10fe-4d8a-868c-fbd089477219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656371582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3656371582
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1185799942
Short name T218
Test name
Test status
Simulation time 10712931 ps
CPU time 0.82 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:09 AM PDT 24
Peak memory 215760 kb
Host smart-dbb800c8-bf56-4ebb-abca-ef2aacab25bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185799942 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1185799942
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.965298942
Short name T155
Test name
Test status
Simulation time 74461927 ps
CPU time 1.25 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 217252 kb
Host smart-a24a447a-917e-4f9d-b6e8-efb4d1ce37fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965298942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.965298942
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3752187139
Short name T197
Test name
Test status
Simulation time 33323227 ps
CPU time 0.95 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 224100 kb
Host smart-07ed1b62-3fcb-4c3e-8626-04a209d60f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752187139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3752187139
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1829981129
Short name T889
Test name
Test status
Simulation time 47865093 ps
CPU time 1.14 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 217740 kb
Host smart-9c39596d-08d6-4aad-a25e-dcbe5a72b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829981129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1829981129
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3207453051
Short name T640
Test name
Test status
Simulation time 42352890 ps
CPU time 0.92 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 224352 kb
Host smart-a7b3b419-b89f-4fc3-a000-a288d82058fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207453051 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3207453051
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1898810089
Short name T517
Test name
Test status
Simulation time 15739038 ps
CPU time 0.96 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 215620 kb
Host smart-ce29b69c-439a-4b49-8977-0e6bbaa17e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898810089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1898810089
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1950536163
Short name T450
Test name
Test status
Simulation time 318378497 ps
CPU time 4.4 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 217492 kb
Host smart-2522bb52-cd54-4637-8866-a33f4f9134c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950536163 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1950536163
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1158437850
Short name T541
Test name
Test status
Simulation time 110063528250 ps
CPU time 1402.86 seconds
Started Jul 01 11:10:06 AM PDT 24
Finished Jul 01 11:33:30 AM PDT 24
Peak memory 226800 kb
Host smart-9363f0a7-43ca-4082-bcef-64a168d795b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158437850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1158437850
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2517010219
Short name T489
Test name
Test status
Simulation time 44710263 ps
CPU time 1.17 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 219084 kb
Host smart-bca53fd6-17f8-4395-a992-86144470855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517010219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2517010219
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1314049107
Short name T388
Test name
Test status
Simulation time 13532927 ps
CPU time 0.88 seconds
Started Jul 01 11:10:32 AM PDT 24
Finished Jul 01 11:10:33 AM PDT 24
Peak memory 206936 kb
Host smart-4bab79ff-1143-46b3-93da-6f0d6a08c13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314049107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1314049107
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.19374765
Short name T924
Test name
Test status
Simulation time 40533109 ps
CPU time 0.84 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 216308 kb
Host smart-f9e4a99d-04c8-4284-bcaf-d7b22017065e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19374765 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.19374765
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.112422525
Short name T143
Test name
Test status
Simulation time 31131414 ps
CPU time 1.15 seconds
Started Jul 01 11:10:35 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 220272 kb
Host smart-2df84f0e-8824-4293-b53a-76495d35794e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112422525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.112422525
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1957677086
Short name T200
Test name
Test status
Simulation time 32460512 ps
CPU time 0.86 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 219584 kb
Host smart-eb0955a4-2707-4f16-aa16-3db9308fe80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957677086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1957677086
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3162700531
Short name T908
Test name
Test status
Simulation time 42229206 ps
CPU time 1.49 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 218888 kb
Host smart-e2300565-e202-438d-9c29-0ba81e061f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162700531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3162700531
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3721378340
Short name T43
Test name
Test status
Simulation time 21313847 ps
CPU time 1.12 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 215700 kb
Host smart-49b0aae7-16f2-465a-af31-46dd20427307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721378340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3721378340
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3498545129
Short name T735
Test name
Test status
Simulation time 16836240 ps
CPU time 0.96 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215580 kb
Host smart-895873e7-cd64-42ba-ad29-0b395aa3b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498545129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3498545129
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1745605109
Short name T504
Test name
Test status
Simulation time 1401464011 ps
CPU time 3.66 seconds
Started Jul 01 11:10:07 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 217708 kb
Host smart-d929df20-4a0a-4d0c-b68d-c42216af13b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745605109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1745605109
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3492454711
Short name T395
Test name
Test status
Simulation time 135052067253 ps
CPU time 360.13 seconds
Started Jul 01 11:10:09 AM PDT 24
Finished Jul 01 11:16:11 AM PDT 24
Peak memory 219044 kb
Host smart-dcfadd45-84bf-45c0-a4a1-ca48d848cbaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492454711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3492454711
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2045538805
Short name T946
Test name
Test status
Simulation time 51954215 ps
CPU time 1.15 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 216028 kb
Host smart-731b96a8-e83a-4142-b617-c79fcaa17bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045538805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2045538805
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.212635238
Short name T573
Test name
Test status
Simulation time 46904578 ps
CPU time 0.84 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:39 AM PDT 24
Peak memory 207036 kb
Host smart-7e30dfc2-8beb-4ca9-ba50-6c3e542fa8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212635238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.212635238
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1155193793
Short name T193
Test name
Test status
Simulation time 36481072 ps
CPU time 0.82 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:40 AM PDT 24
Peak memory 216640 kb
Host smart-e56b8f9f-17a6-46a0-a037-267deb97557c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155193793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1155193793
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1465912777
Short name T133
Test name
Test status
Simulation time 157462424 ps
CPU time 1.27 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 219440 kb
Host smart-1a4baabf-7c16-4e5f-8e36-a236fbeea8c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465912777 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1465912777
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.905126961
Short name T939
Test name
Test status
Simulation time 21531618 ps
CPU time 1.01 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 218584 kb
Host smart-f4779131-9155-4881-bd2d-0f24b9f087ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905126961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.905126961
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.579779019
Short name T763
Test name
Test status
Simulation time 27536882 ps
CPU time 1.14 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 217312 kb
Host smart-0b45b343-9582-4ba6-a8f8-eedc37530340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579779019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.579779019
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3133399315
Short name T54
Test name
Test status
Simulation time 22984795 ps
CPU time 1.21 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 224244 kb
Host smart-6c31fdd5-8a7c-4048-bce1-2ed48ba59196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133399315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3133399315
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3431841123
Short name T65
Test name
Test status
Simulation time 99886340 ps
CPU time 0.9 seconds
Started Jul 01 11:10:30 AM PDT 24
Finished Jul 01 11:10:32 AM PDT 24
Peak memory 215596 kb
Host smart-929a087e-2dd4-47d6-94fc-5466dc82c20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431841123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3431841123
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3027192763
Short name T465
Test name
Test status
Simulation time 243484160 ps
CPU time 4.88 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215584 kb
Host smart-28654b58-3545-4acf-814e-1f200815f4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027192763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3027192763
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3906370486
Short name T950
Test name
Test status
Simulation time 170172048213 ps
CPU time 445.68 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:17:50 AM PDT 24
Peak memory 224072 kb
Host smart-7c9d1f4e-b362-4b43-a761-a99345433c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906370486 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3906370486
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2055159439
Short name T715
Test name
Test status
Simulation time 67776399 ps
CPU time 1.17 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 220860 kb
Host smart-1f46cbd5-bc26-4109-8cd1-d98c85b51a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055159439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2055159439
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1792110694
Short name T364
Test name
Test status
Simulation time 15939185 ps
CPU time 0.93 seconds
Started Jul 01 11:10:56 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 215188 kb
Host smart-798e606a-e3a9-42cd-8d85-f814c7738c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792110694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1792110694
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3381082084
Short name T213
Test name
Test status
Simulation time 20047383 ps
CPU time 0.84 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 216576 kb
Host smart-cc83f572-c786-4fc8-aaec-d650ef5f2c71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381082084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3381082084
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2902777221
Short name T127
Test name
Test status
Simulation time 80341723 ps
CPU time 1.01 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 217104 kb
Host smart-d1ed5e2d-55f2-4dc5-a5c2-faf660a6aa9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902777221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2902777221
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1887186748
Short name T968
Test name
Test status
Simulation time 18464540 ps
CPU time 1.03 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 218672 kb
Host smart-be474bbc-9163-46b3-83d3-8929389ff9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887186748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1887186748
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2179041483
Short name T824
Test name
Test status
Simulation time 103192490 ps
CPU time 2.11 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 219388 kb
Host smart-1d9d869b-55c7-4037-adbd-7ea00504779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179041483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2179041483
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3862574029
Short name T587
Test name
Test status
Simulation time 23129707 ps
CPU time 1.01 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:10:13 AM PDT 24
Peak memory 216088 kb
Host smart-0b4a37e2-e217-4347-8f66-6322128ce623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862574029 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3862574029
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.937284186
Short name T562
Test name
Test status
Simulation time 51127898 ps
CPU time 0.92 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215576 kb
Host smart-2e9078d0-d5ec-407a-a088-6b0f1685f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937284186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.937284186
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3476325801
Short name T605
Test name
Test status
Simulation time 67883387 ps
CPU time 0.97 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 206900 kb
Host smart-08b4055f-551f-4bb1-8417-6c30c0ba3e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476325801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3476325801
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2027687549
Short name T400
Test name
Test status
Simulation time 488801193615 ps
CPU time 2035.53 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:44:07 AM PDT 24
Peak memory 227256 kb
Host smart-049db0e2-0e14-464c-9d24-ad3926f88904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027687549 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2027687549
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3647282263
Short name T792
Test name
Test status
Simulation time 77055657 ps
CPU time 1.15 seconds
Started Jul 01 11:10:49 AM PDT 24
Finished Jul 01 11:10:52 AM PDT 24
Peak memory 219936 kb
Host smart-426f4c5f-481d-43ad-8353-4d5141b3685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647282263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3647282263
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3741752204
Short name T671
Test name
Test status
Simulation time 45499072 ps
CPU time 0.85 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:16 AM PDT 24
Peak memory 215240 kb
Host smart-091ade7b-9241-4996-94a2-018b9049fcf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741752204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3741752204
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1666871438
Short name T905
Test name
Test status
Simulation time 17959397 ps
CPU time 0.86 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 216544 kb
Host smart-21607b90-719e-4441-bf43-cd664a5d1778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666871438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1666871438
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1488299330
Short name T966
Test name
Test status
Simulation time 337888848 ps
CPU time 1.16 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 219076 kb
Host smart-a203e054-ec39-456c-8785-90e12a7f7fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488299330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1488299330
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3479115655
Short name T199
Test name
Test status
Simulation time 25515196 ps
CPU time 0.93 seconds
Started Jul 01 11:10:28 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 218584 kb
Host smart-8ee513eb-6e99-4864-a545-48bc9a80c9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479115655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3479115655
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2773348533
Short name T614
Test name
Test status
Simulation time 99382115 ps
CPU time 1.13 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 217320 kb
Host smart-89c265e8-dc7b-47a5-8533-86638e6078f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773348533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2773348533
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1828203516
Short name T98
Test name
Test status
Simulation time 36093855 ps
CPU time 0.85 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:12 AM PDT 24
Peak memory 215892 kb
Host smart-51a1a9e0-859b-4b32-a426-9ffac584f9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828203516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1828203516
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2042520225
Short name T811
Test name
Test status
Simulation time 39896348 ps
CPU time 0.87 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 207352 kb
Host smart-11cdf405-657b-46bd-81d5-18e3ec74e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042520225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2042520225
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4179705889
Short name T357
Test name
Test status
Simulation time 194983466 ps
CPU time 4.3 seconds
Started Jul 01 11:10:10 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 215620 kb
Host smart-f4eaf37b-1279-4d27-94f1-919b8208d00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179705889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4179705889
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3647410878
Short name T239
Test name
Test status
Simulation time 357881791452 ps
CPU time 2267.49 seconds
Started Jul 01 11:10:30 AM PDT 24
Finished Jul 01 11:48:19 AM PDT 24
Peak memory 226800 kb
Host smart-28f539e7-7f08-4607-b357-9b0df37ae2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647410878 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3647410878
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.447203138
Short name T954
Test name
Test status
Simulation time 92910864 ps
CPU time 1.15 seconds
Started Jul 01 11:10:30 AM PDT 24
Finished Jul 01 11:10:32 AM PDT 24
Peak memory 220284 kb
Host smart-eaead055-be88-4b9c-9cc5-598957176526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447203138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.447203138
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2122747915
Short name T844
Test name
Test status
Simulation time 16836155 ps
CPU time 0.9 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 215188 kb
Host smart-a2077270-24c9-44f8-91f6-758a5ba7d3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122747915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2122747915
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1899860794
Short name T411
Test name
Test status
Simulation time 18731043 ps
CPU time 0.94 seconds
Started Jul 01 11:10:32 AM PDT 24
Finished Jul 01 11:10:34 AM PDT 24
Peak memory 218636 kb
Host smart-74c67762-bafd-47f0-94e4-c57316f248e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899860794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1899860794
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1437539056
Short name T607
Test name
Test status
Simulation time 60762646 ps
CPU time 1.1 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 232308 kb
Host smart-39476a23-86ea-4946-a207-5ab6f78bd9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437539056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1437539056
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3179372356
Short name T846
Test name
Test status
Simulation time 84968969 ps
CPU time 1.12 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 217580 kb
Host smart-6f5f92ee-37c0-467e-a53b-a20c004e5a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179372356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3179372356
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1867899378
Short name T981
Test name
Test status
Simulation time 23650042 ps
CPU time 0.94 seconds
Started Jul 01 11:10:28 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 216128 kb
Host smart-89646aa4-55d6-4271-a474-4008a15a9b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867899378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1867899378
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1513482995
Short name T60
Test name
Test status
Simulation time 23271919 ps
CPU time 0.88 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 215652 kb
Host smart-40cd7ed9-1f35-419c-91b3-99f67117dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513482995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1513482995
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1870036167
Short name T554
Test name
Test status
Simulation time 234620176 ps
CPU time 3.65 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 218836 kb
Host smart-5d2ef988-6919-4101-ac1a-107e294c618b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870036167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1870036167
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3865957441
Short name T105
Test name
Test status
Simulation time 74793273542 ps
CPU time 356.29 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:16:51 AM PDT 24
Peak memory 218120 kb
Host smart-2aabf646-3452-4ae4-a87f-c77254a61413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865957441 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3865957441
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2902688233
Short name T553
Test name
Test status
Simulation time 73788555 ps
CPU time 1.17 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 220796 kb
Host smart-5928afc2-4450-44be-ac3c-0d4a8e6ef58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902688233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2902688233
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1525294721
Short name T759
Test name
Test status
Simulation time 27819820 ps
CPU time 0.99 seconds
Started Jul 01 11:10:27 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 215168 kb
Host smart-88ee110a-3ba7-4063-ad16-486378c8e3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525294721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1525294721
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2177143925
Short name T210
Test name
Test status
Simulation time 124162183 ps
CPU time 0.81 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:17 AM PDT 24
Peak memory 216604 kb
Host smart-ccf6eb38-fe9a-439d-b9ff-0225711beedd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177143925 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2177143925
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1626256198
Short name T366
Test name
Test status
Simulation time 174497296 ps
CPU time 1.02 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 217272 kb
Host smart-171d4fd3-8663-4eef-85eb-500db78e7fa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626256198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1626256198
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3666435995
Short name T149
Test name
Test status
Simulation time 36346182 ps
CPU time 1.39 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 226028 kb
Host smart-fcfe2457-421c-44b5-a586-13fef53cd4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666435995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3666435995
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.708335266
Short name T368
Test name
Test status
Simulation time 59452716 ps
CPU time 1.23 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:18 AM PDT 24
Peak memory 217536 kb
Host smart-9614309b-2ed3-45ba-8c54-e06716e599e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708335266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.708335266
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3599116381
Short name T466
Test name
Test status
Simulation time 21445731 ps
CPU time 1.06 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 216200 kb
Host smart-880e30c7-13b1-40b6-b66c-41c66d63c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599116381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3599116381
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1761932814
Short name T505
Test name
Test status
Simulation time 22164866 ps
CPU time 0.89 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 215596 kb
Host smart-d9fd92bf-8e86-48ed-a215-525e5dc91e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761932814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1761932814
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2849134170
Short name T613
Test name
Test status
Simulation time 468249523 ps
CPU time 4.73 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:10:16 AM PDT 24
Peak memory 215664 kb
Host smart-46a0e153-d140-4dc1-9829-0565c5980f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849134170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2849134170
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1471980216
Short name T316
Test name
Test status
Simulation time 163976769977 ps
CPU time 828.51 seconds
Started Jul 01 11:10:35 AM PDT 24
Finished Jul 01 11:24:24 AM PDT 24
Peak memory 223940 kb
Host smart-bffd53ce-eced-47c9-9245-9ac2e2ec16f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471980216 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1471980216
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.394772615
Short name T645
Test name
Test status
Simulation time 22717024 ps
CPU time 1.18 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 220172 kb
Host smart-74e525d2-e052-434f-b057-42ffcddffc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394772615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.394772615
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.775686418
Short name T575
Test name
Test status
Simulation time 25507760 ps
CPU time 0.84 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:15 AM PDT 24
Peak memory 206908 kb
Host smart-7a3744a3-284d-4d01-8bc2-5fcb4ef0c57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775686418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.775686418
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1204970100
Short name T183
Test name
Test status
Simulation time 46498928 ps
CPU time 0.83 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:39 AM PDT 24
Peak memory 216556 kb
Host smart-c4a0915c-0c28-404c-ade0-832782777234
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204970100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1204970100
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3937272479
Short name T205
Test name
Test status
Simulation time 33596186 ps
CPU time 0.93 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 216824 kb
Host smart-4dd1e635-97a7-470d-8626-d673f69ddc8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937272479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3937272479
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1363243893
Short name T799
Test name
Test status
Simulation time 18152950 ps
CPU time 1.07 seconds
Started Jul 01 11:10:14 AM PDT 24
Finished Jul 01 11:10:21 AM PDT 24
Peak memory 218848 kb
Host smart-b2b2d1f8-3950-4f6d-9927-3e473fd7f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363243893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1363243893
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1470819839
Short name T649
Test name
Test status
Simulation time 32364102 ps
CPU time 1.27 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 218804 kb
Host smart-ed8f311f-828a-4cc6-a063-443e1c6420e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470819839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1470819839
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3134732960
Short name T556
Test name
Test status
Simulation time 54485106 ps
CPU time 0.85 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215660 kb
Host smart-d99c61c3-f0ae-4995-add7-f97da9d2a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134732960 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3134732960
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3342332146
Short name T529
Test name
Test status
Simulation time 23840271 ps
CPU time 0.94 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 215600 kb
Host smart-9ca8b379-11ef-48fa-a97c-8514850a96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342332146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3342332146
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2318676963
Short name T561
Test name
Test status
Simulation time 532199811 ps
CPU time 3 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 217508 kb
Host smart-d1fe584e-6be6-4885-9f24-bf5e51f47fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318676963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2318676963
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4252968251
Short name T240
Test name
Test status
Simulation time 120843308842 ps
CPU time 1332.58 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:33:00 AM PDT 24
Peak memory 223560 kb
Host smart-b3ab4774-ea00-47c9-bf98-c915ad765db5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252968251 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4252968251
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.60385642
Short name T151
Test name
Test status
Simulation time 51048518 ps
CPU time 1.23 seconds
Started Jul 01 11:09:40 AM PDT 24
Finished Jul 01 11:09:42 AM PDT 24
Peak memory 216204 kb
Host smart-2d6451b8-03f5-4b70-919c-aed030e342d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60385642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.60385642
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1749844080
Short name T375
Test name
Test status
Simulation time 58247638 ps
CPU time 1.12 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:31 AM PDT 24
Peak memory 206976 kb
Host smart-5730192a-63bf-4385-bc48-bea7e4fe1102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749844080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1749844080
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.327947468
Short name T169
Test name
Test status
Simulation time 19447762 ps
CPU time 0.83 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:29 AM PDT 24
Peak memory 215700 kb
Host smart-2f7c75d7-c6b8-44e0-a081-54f2555e26c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327947468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.327947468
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2891052098
Short name T485
Test name
Test status
Simulation time 177035012 ps
CPU time 1.28 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:31 AM PDT 24
Peak memory 218860 kb
Host smart-0be2112a-3b20-4176-b856-8e841c0cc9e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891052098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2891052098
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.127043907
Short name T855
Test name
Test status
Simulation time 34094924 ps
CPU time 0.87 seconds
Started Jul 01 11:10:00 AM PDT 24
Finished Jul 01 11:10:02 AM PDT 24
Peak memory 218880 kb
Host smart-f5dfe884-86c3-4b98-81df-616d69869619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127043907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.127043907
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1143981427
Short name T777
Test name
Test status
Simulation time 70085801 ps
CPU time 1.33 seconds
Started Jul 01 11:09:23 AM PDT 24
Finished Jul 01 11:09:25 AM PDT 24
Peak memory 219308 kb
Host smart-8fc941f2-d1da-4a5d-bea7-1ad376706946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143981427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1143981427
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2233259918
Short name T467
Test name
Test status
Simulation time 22648946 ps
CPU time 1.13 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 215744 kb
Host smart-a8e86af0-d381-4e0f-97cc-69dc7ef18536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233259918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2233259918
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2318312941
Short name T741
Test name
Test status
Simulation time 26901173 ps
CPU time 0.93 seconds
Started Jul 01 11:10:11 AM PDT 24
Finished Jul 01 11:10:13 AM PDT 24
Peak memory 207444 kb
Host smart-f62d55bb-f9f3-4e58-8cd7-ec143e93ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318312941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2318312941
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1843394870
Short name T64
Test name
Test status
Simulation time 262110729 ps
CPU time 4.35 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:41 AM PDT 24
Peak memory 242400 kb
Host smart-cc557668-f5e0-4682-831a-858441292922
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843394870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1843394870
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3207439136
Short name T576
Test name
Test status
Simulation time 47007107 ps
CPU time 0.85 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 215624 kb
Host smart-cf2c2ffc-bf17-44ce-9d3a-c43751e740ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207439136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3207439136
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1824631241
Short name T796
Test name
Test status
Simulation time 1589398631 ps
CPU time 4.23 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 215612 kb
Host smart-5b8b59b3-bb49-4430-82f2-95355b2601d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824631241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1824631241
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3487509989
Short name T931
Test name
Test status
Simulation time 57152183449 ps
CPU time 649.12 seconds
Started Jul 01 11:09:23 AM PDT 24
Finished Jul 01 11:20:13 AM PDT 24
Peak memory 218024 kb
Host smart-913f884a-8d7c-490a-9954-9ff61362a168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487509989 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3487509989
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.986215018
Short name T134
Test name
Test status
Simulation time 24558518 ps
CPU time 1.24 seconds
Started Jul 01 11:10:35 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 220348 kb
Host smart-a0b6c2a3-e99e-43fe-b894-140d770ce259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986215018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.986215018
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3755566084
Short name T382
Test name
Test status
Simulation time 42885549 ps
CPU time 0.91 seconds
Started Jul 01 11:10:36 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 207076 kb
Host smart-091cdfdf-aebd-414c-a4d9-1ed2342b55aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755566084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3755566084
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2889716573
Short name T700
Test name
Test status
Simulation time 90977785 ps
CPU time 0.77 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:33 AM PDT 24
Peak memory 216560 kb
Host smart-e0249f18-ae48-4dde-83cc-96f4927ef82d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889716573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2889716573
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.704823986
Short name T128
Test name
Test status
Simulation time 76380311 ps
CPU time 1.26 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:18 AM PDT 24
Peak memory 217240 kb
Host smart-28a95f2c-a201-49b4-9a8c-45facf04f3da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704823986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.704823986
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3142481596
Short name T8
Test name
Test status
Simulation time 100424692 ps
CPU time 0.95 seconds
Started Jul 01 11:10:33 AM PDT 24
Finished Jul 01 11:10:35 AM PDT 24
Peak memory 218872 kb
Host smart-1cdccab0-64fc-49b0-abf2-2a328f59473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142481596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3142481596
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1682357909
Short name T563
Test name
Test status
Simulation time 56406956 ps
CPU time 1.34 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:49 AM PDT 24
Peak memory 219860 kb
Host smart-8bb7949e-261d-4338-b603-0903d95c3777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682357909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1682357909
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.166966533
Short name T118
Test name
Test status
Simulation time 28994582 ps
CPU time 1.17 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 217008 kb
Host smart-a0bd57a3-213c-46cc-af74-6a6c812b610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166966533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.166966533
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1241918096
Short name T518
Test name
Test status
Simulation time 51810065 ps
CPU time 0.93 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 215628 kb
Host smart-273a2637-1a9d-4aba-8fcd-591cf4c449be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241918096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1241918096
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2428176841
Short name T580
Test name
Test status
Simulation time 762776246 ps
CPU time 6.49 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215636 kb
Host smart-94bdb6c0-b52e-42ec-a35a-0bb5c6f2f535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428176841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2428176841
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3944152509
Short name T243
Test name
Test status
Simulation time 28111944217 ps
CPU time 592.91 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:20:15 AM PDT 24
Peak memory 218252 kb
Host smart-7c4dbfda-ac01-4bf3-a08c-643a3acf9aed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944152509 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3944152509
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.760548951
Short name T540
Test name
Test status
Simulation time 30170239 ps
CPU time 1.24 seconds
Started Jul 01 11:10:33 AM PDT 24
Finished Jul 01 11:10:35 AM PDT 24
Peak memory 220824 kb
Host smart-6044be87-0c6b-4ff6-9ac7-84af4bc7683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760548951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.760548951
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2506450568
Short name T749
Test name
Test status
Simulation time 94303330 ps
CPU time 0.8 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 206880 kb
Host smart-5ffb0d45-dd8f-486d-813a-65010f6f0de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506450568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2506450568
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.168496966
Short name T932
Test name
Test status
Simulation time 20528949 ps
CPU time 0.83 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:48 AM PDT 24
Peak memory 216548 kb
Host smart-e0b1f865-f755-46a8-b3c7-7a6de118387c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168496966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.168496966
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4176697727
Short name T732
Test name
Test status
Simulation time 31583949 ps
CPU time 1.14 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 220100 kb
Host smart-1be38341-9469-40cf-b2cd-0da2dcfa0d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176697727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4176697727
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2651839630
Short name T57
Test name
Test status
Simulation time 48715852 ps
CPU time 1.06 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 229604 kb
Host smart-d224ba90-b805-4d64-b2ac-8789be5f82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651839630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2651839630
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.448832182
Short name T632
Test name
Test status
Simulation time 157128183 ps
CPU time 0.97 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 217636 kb
Host smart-4ea285ce-cc2b-4281-a19a-f8cb78051327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448832182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.448832182
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4082172486
Short name T663
Test name
Test status
Simulation time 93182808 ps
CPU time 0.83 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215616 kb
Host smart-80e5e7bc-ae1f-454e-85d9-45d29f6dccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082172486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4082172486
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3045930363
Short name T993
Test name
Test status
Simulation time 37050382 ps
CPU time 0.85 seconds
Started Jul 01 11:10:43 AM PDT 24
Finished Jul 01 11:10:44 AM PDT 24
Peak memory 215404 kb
Host smart-d0afd0db-fbcd-464a-98d5-f17bb64346e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045930363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3045930363
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2418609444
Short name T459
Test name
Test status
Simulation time 220320527 ps
CPU time 4.75 seconds
Started Jul 01 11:10:33 AM PDT 24
Finished Jul 01 11:10:38 AM PDT 24
Peak memory 215580 kb
Host smart-14d7aa0e-14fc-4229-9ad2-3cc0023db4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418609444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2418609444
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4253388474
Short name T242
Test name
Test status
Simulation time 29893368013 ps
CPU time 686.47 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:21:51 AM PDT 24
Peak memory 224028 kb
Host smart-a9363c1e-848d-41d7-be00-a8ea56e7cca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253388474 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4253388474
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1244174449
Short name T195
Test name
Test status
Simulation time 62176006 ps
CPU time 1.07 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 220588 kb
Host smart-6fe975c6-3447-40ad-bdd6-9e59c4e5ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244174449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1244174449
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3820074440
Short name T559
Test name
Test status
Simulation time 47490867 ps
CPU time 0.83 seconds
Started Jul 01 11:10:28 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 206844 kb
Host smart-53f03fd2-ed40-4966-b561-5380262262db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820074440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3820074440
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1861534823
Short name T96
Test name
Test status
Simulation time 11754136 ps
CPU time 0.85 seconds
Started Jul 01 11:10:31 AM PDT 24
Finished Jul 01 11:10:33 AM PDT 24
Peak memory 216452 kb
Host smart-68a8a131-f3c3-492d-ad92-7c3ca1efc7bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861534823 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1861534823
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3958355370
Short name T778
Test name
Test status
Simulation time 66364576 ps
CPU time 1.03 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 217244 kb
Host smart-1c9cda34-f40d-473d-9612-573defec0122
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958355370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3958355370
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1415725341
Short name T219
Test name
Test status
Simulation time 19702736 ps
CPU time 1 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 218844 kb
Host smart-2e9d1c26-ebb8-45dd-a07e-08234c138093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415725341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1415725341
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.684878085
Short name T899
Test name
Test status
Simulation time 41042639 ps
CPU time 1.41 seconds
Started Jul 01 11:10:34 AM PDT 24
Finished Jul 01 11:10:36 AM PDT 24
Peak memory 219612 kb
Host smart-c8249472-fadf-4688-8301-a971d422be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684878085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.684878085
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.337032677
Short name T34
Test name
Test status
Simulation time 26148667 ps
CPU time 0.86 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 216112 kb
Host smart-710afbd0-8a63-4f6a-9f95-8660e7a701ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337032677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.337032677
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.928483220
Short name T989
Test name
Test status
Simulation time 81284585 ps
CPU time 0.85 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 215648 kb
Host smart-04b7afed-f913-4c27-8b48-25c30112d01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928483220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.928483220
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2998056156
Short name T866
Test name
Test status
Simulation time 1582663375 ps
CPU time 4.38 seconds
Started Jul 01 11:10:15 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 215556 kb
Host smart-a4eaded5-e0c4-4f08-991c-adf584a554bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998056156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2998056156
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3997431840
Short name T308
Test name
Test status
Simulation time 438991637308 ps
CPU time 1505.27 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:35:27 AM PDT 24
Peak memory 224512 kb
Host smart-5a149bd3-c71c-4a5f-9699-0a9d1c132114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997431840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3997431840
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2606768417
Short name T336
Test name
Test status
Simulation time 72450028 ps
CPU time 1.11 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:26 AM PDT 24
Peak memory 216000 kb
Host smart-6d290078-a0b8-4ce1-9dc9-1d7e82de95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606768417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2606768417
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3406530713
Short name T681
Test name
Test status
Simulation time 46873307 ps
CPU time 0.85 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 207020 kb
Host smart-eab73575-4d34-4dd6-888e-05d1e9bd7e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406530713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3406530713
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.68986405
Short name T956
Test name
Test status
Simulation time 41662622 ps
CPU time 0.86 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:20 AM PDT 24
Peak memory 216672 kb
Host smart-2c34c604-75fa-4b05-98c7-70e8cbf4cf69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68986405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.68986405
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2941861504
Short name T571
Test name
Test status
Simulation time 335196054 ps
CPU time 1.28 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 217204 kb
Host smart-e46475ff-23ce-472a-9c49-e37a15316894
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941861504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2941861504
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4099789845
Short name T9
Test name
Test status
Simulation time 98380949 ps
CPU time 0.96 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 220144 kb
Host smart-ffcf9ca7-6171-453d-bc95-148b87b35b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099789845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4099789845
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1851179631
Short name T883
Test name
Test status
Simulation time 95282165 ps
CPU time 1.24 seconds
Started Jul 01 11:10:39 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 220160 kb
Host smart-3070b924-ab31-48d1-b1fc-8e34c8c1adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851179631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1851179631
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1985456594
Short name T102
Test name
Test status
Simulation time 20315650 ps
CPU time 1.05 seconds
Started Jul 01 11:10:36 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 216072 kb
Host smart-72892496-9a73-4003-890c-a2f6b7864950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985456594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1985456594
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3974391525
Short name T600
Test name
Test status
Simulation time 30345873 ps
CPU time 0.94 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 215600 kb
Host smart-c9d934f6-efd0-4a5f-8a91-a8ef6dd83f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974391525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3974391525
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2968754557
Short name T783
Test name
Test status
Simulation time 306426398 ps
CPU time 1.67 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 217516 kb
Host smart-fe8b1a9b-accd-44f4-bc80-65da27c2a2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968754557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2968754557
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2211538140
Short name T482
Test name
Test status
Simulation time 183120722816 ps
CPU time 661.18 seconds
Started Jul 01 11:10:33 AM PDT 24
Finished Jul 01 11:21:35 AM PDT 24
Peak memory 222600 kb
Host smart-fa16b505-f35f-4b0a-b1e7-281cd80efedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211538140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2211538140
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.800720719
Short name T974
Test name
Test status
Simulation time 41817554 ps
CPU time 1.15 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:24 AM PDT 24
Peak memory 219052 kb
Host smart-3f7b9fb8-0969-4305-8746-ca8a4e666941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800720719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.800720719
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1910992604
Short name T658
Test name
Test status
Simulation time 22191716 ps
CPU time 0.93 seconds
Started Jul 01 11:10:28 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 215112 kb
Host smart-b7c1ba54-ea36-4b73-8422-f9938e332e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910992604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1910992604
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.54652579
Short name T170
Test name
Test status
Simulation time 13818366 ps
CPU time 0.9 seconds
Started Jul 01 11:10:34 AM PDT 24
Finished Jul 01 11:10:35 AM PDT 24
Peak memory 215804 kb
Host smart-3fb370cd-56ad-45f1-a6bd-d52c91cfe066
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54652579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.54652579
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3367080293
Short name T675
Test name
Test status
Simulation time 40562799 ps
CPU time 1.35 seconds
Started Jul 01 11:10:32 AM PDT 24
Finished Jul 01 11:10:34 AM PDT 24
Peak memory 217152 kb
Host smart-3b11b69e-4a18-4afe-9a6a-9e6e55ea72d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367080293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3367080293
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4197588602
Short name T166
Test name
Test status
Simulation time 220251496 ps
CPU time 1.16 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 225552 kb
Host smart-0678bb3c-059d-4535-9877-79e80929a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197588602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4197588602
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1608076838
Short name T677
Test name
Test status
Simulation time 88591597 ps
CPU time 1.5 seconds
Started Jul 01 11:10:39 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 217836 kb
Host smart-bb22c66f-bf21-4f4d-a336-39b7a4c231f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608076838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1608076838
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1816680669
Short name T344
Test name
Test status
Simulation time 24160260 ps
CPU time 0.92 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 215700 kb
Host smart-0807a610-1192-4fe3-82a5-a59a6a473ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816680669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1816680669
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3856013728
Short name T498
Test name
Test status
Simulation time 19421582 ps
CPU time 1.03 seconds
Started Jul 01 11:10:18 AM PDT 24
Finished Jul 01 11:10:22 AM PDT 24
Peak memory 215620 kb
Host smart-f6d0d73c-d67e-4dbf-8d78-3da4e4ea3390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856013728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3856013728
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2457217980
Short name T945
Test name
Test status
Simulation time 218815247 ps
CPU time 4.55 seconds
Started Jul 01 11:10:27 AM PDT 24
Finished Jul 01 11:10:34 AM PDT 24
Peak memory 217364 kb
Host smart-03af39dd-bbdf-47dd-9d16-343400d35fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457217980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2457217980
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.147832010
Short name T258
Test name
Test status
Simulation time 154488041 ps
CPU time 1.22 seconds
Started Jul 01 11:10:16 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 215952 kb
Host smart-bc43642f-aaad-47c3-960b-e9e54975c849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147832010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.147832010
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2071276296
Short name T589
Test name
Test status
Simulation time 32883924 ps
CPU time 1 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:39 AM PDT 24
Peak memory 207028 kb
Host smart-e2202df9-c38c-4038-9a74-dadfd2415528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071276296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2071276296
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3376420548
Short name T207
Test name
Test status
Simulation time 19821166 ps
CPU time 0.86 seconds
Started Jul 01 11:10:35 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 216200 kb
Host smart-40bacbb3-e08b-4c11-9083-0bd01dd8bc7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376420548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3376420548
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.328734162
Short name T47
Test name
Test status
Simulation time 230586589 ps
CPU time 1.09 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 217136 kb
Host smart-0639e33f-8c8e-409c-8e34-abe4ce219d74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328734162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.328734162
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2579449950
Short name T800
Test name
Test status
Simulation time 20704047 ps
CPU time 1.08 seconds
Started Jul 01 11:10:44 AM PDT 24
Finished Jul 01 11:10:46 AM PDT 24
Peak memory 218940 kb
Host smart-c2676c3e-a1d3-4124-a34f-29d57a4d7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579449950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2579449950
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1322114591
Short name T765
Test name
Test status
Simulation time 312423863 ps
CPU time 1.28 seconds
Started Jul 01 11:10:34 AM PDT 24
Finished Jul 01 11:10:36 AM PDT 24
Peak memory 220176 kb
Host smart-c3ad72d0-1b5c-4e6a-991a-52ada43a7bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322114591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1322114591
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3619343008
Short name T603
Test name
Test status
Simulation time 38287712 ps
CPU time 0.9 seconds
Started Jul 01 11:10:28 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 215736 kb
Host smart-a2e3a0a6-761b-4374-b3d0-00c11be03691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619343008 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3619343008
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.420761351
Short name T497
Test name
Test status
Simulation time 48789096 ps
CPU time 0.95 seconds
Started Jul 01 11:10:30 AM PDT 24
Finished Jul 01 11:10:32 AM PDT 24
Peak memory 215524 kb
Host smart-0fa0e37a-43f2-401b-a48e-4a2527aa61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420761351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.420761351
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1981782223
Short name T714
Test name
Test status
Simulation time 490335371 ps
CPU time 3.07 seconds
Started Jul 01 11:10:17 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 217628 kb
Host smart-992bc4cc-d4ed-4e70-9b06-89e48a361531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981782223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1981782223
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3158184970
Short name T41
Test name
Test status
Simulation time 27065912015 ps
CPU time 624.96 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:20:52 AM PDT 24
Peak memory 217828 kb
Host smart-2097737c-2874-457d-a964-a9980c1d663d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158184970 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3158184970
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2777898221
Short name T760
Test name
Test status
Simulation time 152429059 ps
CPU time 1.27 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 219748 kb
Host smart-064bb025-b8b4-4e03-812f-d8f13f578ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777898221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2777898221
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.897268864
Short name T935
Test name
Test status
Simulation time 19228553 ps
CPU time 0.98 seconds
Started Jul 01 11:10:21 AM PDT 24
Finished Jul 01 11:10:27 AM PDT 24
Peak memory 215476 kb
Host smart-6aef72ab-766e-4a31-bb73-3c95fe07445d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897268864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.897268864
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1996930628
Short name T429
Test name
Test status
Simulation time 22967792 ps
CPU time 0.86 seconds
Started Jul 01 11:10:26 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 215680 kb
Host smart-3506ccda-fe78-414f-af48-bf0cdbc432db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996930628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1996930628
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1158336125
Short name T11
Test name
Test status
Simulation time 56801279 ps
CPU time 1.15 seconds
Started Jul 01 11:10:26 AM PDT 24
Finished Jul 01 11:10:31 AM PDT 24
Peak memory 217184 kb
Host smart-79615aca-9d88-4837-9f2c-73784ee1bb07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158336125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1158336125
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2863754973
Short name T988
Test name
Test status
Simulation time 30391266 ps
CPU time 0.9 seconds
Started Jul 01 11:10:37 AM PDT 24
Finished Jul 01 11:10:38 AM PDT 24
Peak memory 218864 kb
Host smart-f7f79f35-c2fe-45bc-b246-a6b57e02090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863754973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2863754973
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.586858546
Short name T764
Test name
Test status
Simulation time 59752482 ps
CPU time 1.22 seconds
Started Jul 01 11:10:24 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 218660 kb
Host smart-2e93de6d-2647-44d3-94f4-336b8ab88b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586858546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.586858546
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.741249529
Short name T928
Test name
Test status
Simulation time 42102339 ps
CPU time 0.84 seconds
Started Jul 01 11:10:19 AM PDT 24
Finished Jul 01 11:10:23 AM PDT 24
Peak memory 215444 kb
Host smart-d2a4fdff-1bcd-412e-a6ad-e848abf8ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741249529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.741249529
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3222925305
Short name T349
Test name
Test status
Simulation time 194388141 ps
CPU time 1.53 seconds
Started Jul 01 11:10:23 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 215532 kb
Host smart-c2a7d979-669e-4a11-928e-7d6250dcbf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222925305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3222925305
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.856096588
Short name T244
Test name
Test status
Simulation time 121819818190 ps
CPU time 1442.69 seconds
Started Jul 01 11:10:37 AM PDT 24
Finished Jul 01 11:34:40 AM PDT 24
Peak memory 224008 kb
Host smart-9cff495a-a8c8-4f5e-8b75-2c5a5be5c72f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856096588 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.856096588
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3273647582
Short name T79
Test name
Test status
Simulation time 38301739 ps
CPU time 1.12 seconds
Started Jul 01 11:10:31 AM PDT 24
Finished Jul 01 11:10:33 AM PDT 24
Peak memory 220468 kb
Host smart-e6e947a5-e2cf-47f9-91d2-cb28535851fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273647582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3273647582
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1316475276
Short name T503
Test name
Test status
Simulation time 22413596 ps
CPU time 0.92 seconds
Started Jul 01 11:10:49 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 215200 kb
Host smart-0a8ed2fa-37ef-414b-b09b-c4e0870654aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316475276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1316475276
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2931749999
Short name T211
Test name
Test status
Simulation time 19807958 ps
CPU time 0.84 seconds
Started Jul 01 11:10:53 AM PDT 24
Finished Jul 01 11:10:55 AM PDT 24
Peak memory 216680 kb
Host smart-e332a426-0ab0-4924-8e6c-937ebc02101b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931749999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2931749999
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.233542026
Short name T530
Test name
Test status
Simulation time 23051140 ps
CPU time 1.05 seconds
Started Jul 01 11:10:20 AM PDT 24
Finished Jul 01 11:10:25 AM PDT 24
Peak memory 218984 kb
Host smart-f316c01f-cd4d-454f-9a40-2efef609de23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233542026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.233542026
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.161143134
Short name T644
Test name
Test status
Simulation time 25069125 ps
CPU time 0.88 seconds
Started Jul 01 11:10:22 AM PDT 24
Finished Jul 01 11:10:28 AM PDT 24
Peak memory 218628 kb
Host smart-1a5d2cf5-7aab-4b92-8e2f-9652679d1ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161143134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.161143134
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2119450641
Short name T842
Test name
Test status
Simulation time 72799747 ps
CPU time 1.32 seconds
Started Jul 01 11:10:25 AM PDT 24
Finished Jul 01 11:10:30 AM PDT 24
Peak memory 219092 kb
Host smart-90cc5905-40ff-44df-a371-a088ea0d1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119450641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2119450641
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1031946375
Short name T53
Test name
Test status
Simulation time 23159808 ps
CPU time 1.07 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 215732 kb
Host smart-9f0adf3f-1949-4cee-9eeb-a951138d80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031946375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1031946375
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2419980172
Short name T601
Test name
Test status
Simulation time 47644633 ps
CPU time 0.91 seconds
Started Jul 01 11:10:40 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 215812 kb
Host smart-736b9183-61c6-4ea4-97e4-8416a4729500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419980172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2419980172
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.662611322
Short name T642
Test name
Test status
Simulation time 354854180 ps
CPU time 4.71 seconds
Started Jul 01 11:10:33 AM PDT 24
Finished Jul 01 11:10:38 AM PDT 24
Peak memory 217656 kb
Host smart-e7770b9b-5413-4351-a840-6d68a81f3938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662611322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.662611322
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1045760252
Short name T237
Test name
Test status
Simulation time 38430620903 ps
CPU time 859.18 seconds
Started Jul 01 11:10:39 AM PDT 24
Finished Jul 01 11:24:59 AM PDT 24
Peak memory 218520 kb
Host smart-9c4e9cad-8e73-49d8-b23c-f457da279120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045760252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1045760252
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2916982127
Short name T578
Test name
Test status
Simulation time 37555277 ps
CPU time 1.29 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 216024 kb
Host smart-73ab177a-9d64-4f89-9237-386c06077597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916982127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2916982127
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3374054510
Short name T345
Test name
Test status
Simulation time 22415996 ps
CPU time 0.83 seconds
Started Jul 01 11:10:44 AM PDT 24
Finished Jul 01 11:10:46 AM PDT 24
Peak memory 207092 kb
Host smart-c7f8e850-652e-4252-8f93-9b53cbb1b938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374054510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3374054510
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.248847785
Short name T911
Test name
Test status
Simulation time 32614908 ps
CPU time 0.89 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 216688 kb
Host smart-af350ae4-5a9b-4d96-8122-3bf411bef448
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248847785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.248847785
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2440294744
Short name T359
Test name
Test status
Simulation time 96765382 ps
CPU time 1.07 seconds
Started Jul 01 11:10:39 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 219016 kb
Host smart-3a7276f2-9920-41d8-a602-6045944734e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440294744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2440294744
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2846661797
Short name T409
Test name
Test status
Simulation time 48525784 ps
CPU time 0.95 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:48 AM PDT 24
Peak memory 220028 kb
Host smart-be7b19e6-05db-430e-b619-d8f0847bf459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846661797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2846661797
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3543313464
Short name T535
Test name
Test status
Simulation time 68379791 ps
CPU time 1.09 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:39 AM PDT 24
Peak memory 217560 kb
Host smart-0b2d383d-6f85-496f-9e4a-f2d369c1f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543313464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3543313464
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3703257528
Short name T56
Test name
Test status
Simulation time 34479084 ps
CPU time 0.98 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 224360 kb
Host smart-837b7a55-20c2-4e27-b3f0-775994fdce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703257528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3703257528
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1810674227
Short name T937
Test name
Test status
Simulation time 37010082 ps
CPU time 0.92 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 215508 kb
Host smart-d42e3132-452f-49ae-b692-cf35b8803269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810674227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1810674227
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2823713221
Short name T253
Test name
Test status
Simulation time 444842471 ps
CPU time 4.31 seconds
Started Jul 01 11:10:53 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 215632 kb
Host smart-a0a34d76-b224-49d1-9caf-446a16dc57b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823713221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2823713221
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2477379995
Short name T241
Test name
Test status
Simulation time 77805389846 ps
CPU time 759.63 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:23:28 AM PDT 24
Peak memory 220040 kb
Host smart-c62146e4-fb27-4a4c-85e0-a434986d7bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477379995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2477379995
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.409142033
Short name T795
Test name
Test status
Simulation time 28836366 ps
CPU time 1.29 seconds
Started Jul 01 11:10:39 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 218968 kb
Host smart-ff382f2e-29d0-4abf-bdca-eb7e1492c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409142033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.409142033
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3951773913
Short name T501
Test name
Test status
Simulation time 16169355 ps
CPU time 0.94 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 207076 kb
Host smart-cb79e200-6713-42c1-b05d-a7e40da69b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951773913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3951773913
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2289275082
Short name T534
Test name
Test status
Simulation time 16409562 ps
CPU time 0.87 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 216640 kb
Host smart-2db3874e-6566-4555-8cfd-5df65144fd75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289275082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2289275082
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1287399851
Short name T569
Test name
Test status
Simulation time 65066711 ps
CPU time 1.16 seconds
Started Jul 01 11:10:49 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 217180 kb
Host smart-1a4ac64f-a9df-43da-ba79-ee0bc93ecfc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287399851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1287399851
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1947597816
Short name T818
Test name
Test status
Simulation time 33716448 ps
CPU time 1.35 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 225956 kb
Host smart-f3f8579d-24d1-4be8-92ce-5bacfab789b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947597816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1947597816
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2141894095
Short name T853
Test name
Test status
Simulation time 63708872 ps
CPU time 1.29 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 215632 kb
Host smart-2ce249af-bfa5-4585-b927-e8a7e2f3de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141894095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2141894095
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1010733773
Short name T969
Test name
Test status
Simulation time 31038669 ps
CPU time 0.98 seconds
Started Jul 01 11:10:35 AM PDT 24
Finished Jul 01 11:10:37 AM PDT 24
Peak memory 224148 kb
Host smart-bc4e493d-c45c-429f-99d1-4d153f341567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010733773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1010733773
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1172057744
Short name T610
Test name
Test status
Simulation time 18420570 ps
CPU time 1.05 seconds
Started Jul 01 11:10:40 AM PDT 24
Finished Jul 01 11:10:41 AM PDT 24
Peak memory 215620 kb
Host smart-9c03860d-57fa-4102-9f1e-936f296d3f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172057744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1172057744
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2945082515
Short name T708
Test name
Test status
Simulation time 294866244 ps
CPU time 2.05 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 217492 kb
Host smart-edfe8c01-1a3b-43cb-ac3a-e21d03afffd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945082515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2945082515
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3203424055
Short name T916
Test name
Test status
Simulation time 62948749326 ps
CPU time 400.27 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:17:33 AM PDT 24
Peak memory 218208 kb
Host smart-7b44a873-c789-44d7-b43d-6567f94936d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203424055 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3203424055
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.207578271
Short name T422
Test name
Test status
Simulation time 190057090 ps
CPU time 1.12 seconds
Started Jul 01 11:09:23 AM PDT 24
Finished Jul 01 11:09:25 AM PDT 24
Peak memory 221604 kb
Host smart-27c6d854-6a53-4d18-a678-30afebdea9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207578271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.207578271
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3758178888
Short name T421
Test name
Test status
Simulation time 40732977 ps
CPU time 0.82 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 214976 kb
Host smart-2fca5ce2-6f4a-4f36-ac4e-c367f711c45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758178888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3758178888
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1425778332
Short name T81
Test name
Test status
Simulation time 30448800 ps
CPU time 0.84 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 216456 kb
Host smart-df5b86ee-d3f5-4c32-898e-d6e168a42bfb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425778332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1425778332
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1331214640
Short name T859
Test name
Test status
Simulation time 133762702 ps
CPU time 1.04 seconds
Started Jul 01 11:09:29 AM PDT 24
Finished Jul 01 11:09:36 AM PDT 24
Peak memory 218568 kb
Host smart-c964f156-51a9-4cc1-bfe8-525c5733d9ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331214640 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1331214640
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2386270590
Short name T551
Test name
Test status
Simulation time 19542516 ps
CPU time 1.17 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:33 AM PDT 24
Peak memory 224220 kb
Host smart-c8694ab7-f046-41a8-adf9-af5de88a105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386270590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2386270590
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3755925082
Short name T751
Test name
Test status
Simulation time 63162038 ps
CPU time 1.24 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 219324 kb
Host smart-c055be3c-ac34-4a8a-89c8-e0b35b9b76cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755925082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3755925082
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.3157748906
Short name T704
Test name
Test status
Simulation time 25035157 ps
CPU time 0.94 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:35 AM PDT 24
Peak memory 207392 kb
Host smart-7c62cdaf-8d6b-475d-9191-b5d35ebffa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157748906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3157748906
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3798300254
Short name T923
Test name
Test status
Simulation time 42789158 ps
CPU time 0.93 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 215616 kb
Host smart-1122573a-cf6c-4c74-85ba-a87cc606979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798300254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3798300254
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2007875459
Short name T711
Test name
Test status
Simulation time 539083533 ps
CPU time 3.05 seconds
Started Jul 01 11:09:29 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 217736 kb
Host smart-50b2472c-69aa-47ef-bb1a-8754ddc22c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007875459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2007875459
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.422303952
Short name T879
Test name
Test status
Simulation time 71923688786 ps
CPU time 863.35 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:23:57 AM PDT 24
Peak memory 221300 kb
Host smart-85f2fdd9-e58d-4bfc-b08e-dca0e3cd109e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422303952 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.422303952
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.4107043442
Short name T880
Test name
Test status
Simulation time 22864956 ps
CPU time 1.2 seconds
Started Jul 01 11:10:44 AM PDT 24
Finished Jul 01 11:10:46 AM PDT 24
Peak memory 221304 kb
Host smart-b2c198df-8936-43b4-8d55-09ba477c870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107043442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.4107043442
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1971361664
Short name T112
Test name
Test status
Simulation time 35867077 ps
CPU time 1.13 seconds
Started Jul 01 11:10:30 AM PDT 24
Finished Jul 01 11:10:32 AM PDT 24
Peak memory 220968 kb
Host smart-1d41e463-33b4-453b-999e-9438d5200f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971361664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1971361664
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.603422726
Short name T805
Test name
Test status
Simulation time 59512309 ps
CPU time 1.23 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 218808 kb
Host smart-8808b49d-8427-4a66-9c9c-3768ad02eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603422726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.603422726
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1383053959
Short name T225
Test name
Test status
Simulation time 30118920 ps
CPU time 1.19 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 219456 kb
Host smart-5fd4f4a1-302d-4e5a-b799-e766980953ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383053959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1383053959
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.726358485
Short name T520
Test name
Test status
Simulation time 119957341 ps
CPU time 0.97 seconds
Started Jul 01 11:10:41 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 220096 kb
Host smart-f08a3b8c-27c0-428f-91c6-93b5a54919bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726358485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.726358485
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2426908120
Short name T384
Test name
Test status
Simulation time 80861593 ps
CPU time 1.04 seconds
Started Jul 01 11:10:43 AM PDT 24
Finished Jul 01 11:10:45 AM PDT 24
Peak memory 217604 kb
Host smart-0b91a9a6-92e4-4bb7-9b99-6af3bf415c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426908120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2426908120
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3814191236
Short name T921
Test name
Test status
Simulation time 52258792 ps
CPU time 1.1 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 220436 kb
Host smart-65312c71-9c64-4e0c-ad3f-4b94bfa12401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814191236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3814191236
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3719265784
Short name T126
Test name
Test status
Simulation time 36849361 ps
CPU time 1.11 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 220716 kb
Host smart-47d0748e-ba14-4760-8b69-ff9dd481e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719265784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3719265784
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.233478372
Short name T313
Test name
Test status
Simulation time 45898424 ps
CPU time 1.74 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 218908 kb
Host smart-8738eba3-cbf9-4a4f-a2a3-b0d60170e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233478372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.233478372
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2430406019
Short name T729
Test name
Test status
Simulation time 62932715 ps
CPU time 1.14 seconds
Started Jul 01 11:10:41 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 220140 kb
Host smart-d786a0f8-025f-4c0b-b8a3-4272506f1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430406019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2430406019
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.87776781
Short name T137
Test name
Test status
Simulation time 44667185 ps
CPU time 1.02 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 220020 kb
Host smart-ed6e9e82-272b-4e20-9890-e276e50f0a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87776781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.87776781
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3315829354
Short name T823
Test name
Test status
Simulation time 42943387 ps
CPU time 1.39 seconds
Started Jul 01 11:10:40 AM PDT 24
Finished Jul 01 11:10:42 AM PDT 24
Peak memory 218856 kb
Host smart-f678d9de-58c7-4ba6-994f-2bce1aadc840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315829354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3315829354
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3708611388
Short name T171
Test name
Test status
Simulation time 47671145 ps
CPU time 1.23 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:52 AM PDT 24
Peak memory 220452 kb
Host smart-d905c64f-e810-49fc-94ce-b7548d109f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708611388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3708611388
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_genbits.2568590095
Short name T962
Test name
Test status
Simulation time 37936061 ps
CPU time 1.47 seconds
Started Jul 01 11:10:42 AM PDT 24
Finished Jul 01 11:10:44 AM PDT 24
Peak memory 220056 kb
Host smart-95627d0d-5ae1-4df1-aa62-ff57c91e105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568590095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2568590095
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.236146164
Short name T906
Test name
Test status
Simulation time 88556260 ps
CPU time 1.27 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 220296 kb
Host smart-f9048a25-9bfa-4536-933d-38c4923c79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236146164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.236146164
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3051411067
Short name T744
Test name
Test status
Simulation time 30737061 ps
CPU time 0.92 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 218692 kb
Host smart-14207f81-d02a-4d85-8a05-fabf7f8c3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051411067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3051411067
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2743984475
Short name T508
Test name
Test status
Simulation time 72521916 ps
CPU time 1.27 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:49 AM PDT 24
Peak memory 217740 kb
Host smart-a8ea5861-9052-45f2-896f-a201801a0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743984475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2743984475
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.39762343
Short name T390
Test name
Test status
Simulation time 28172369 ps
CPU time 0.84 seconds
Started Jul 01 11:10:49 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 218760 kb
Host smart-7dff0895-16ca-4123-9048-22ba6c592d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39762343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.39762343
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1307868023
Short name T455
Test name
Test status
Simulation time 45533820 ps
CPU time 1.52 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 217816 kb
Host smart-99415b90-fbd7-4d31-b9e6-e2f0ef8fd2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307868023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1307868023
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1896101623
Short name T838
Test name
Test status
Simulation time 102960854 ps
CPU time 1.18 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:48 AM PDT 24
Peak memory 219980 kb
Host smart-e7d4275b-864c-47a3-862c-0ef62b396457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896101623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1896101623
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2045961657
Short name T152
Test name
Test status
Simulation time 53899440 ps
CPU time 1.01 seconds
Started Jul 01 11:10:42 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 229952 kb
Host smart-49d5f864-e802-4aeb-84e4-803a79058bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045961657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2045961657
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1639426824
Short name T560
Test name
Test status
Simulation time 59752530 ps
CPU time 1.46 seconds
Started Jul 01 11:10:41 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 217764 kb
Host smart-45834a5b-130f-45d7-8599-45f125e6c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639426824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1639426824
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.362973457
Short name T934
Test name
Test status
Simulation time 89328867 ps
CPU time 1.15 seconds
Started Jul 01 11:10:56 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 216032 kb
Host smart-cc4ffd5d-cf90-4a71-aa5c-248a9b653e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362973457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.362973457
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.915103727
Short name T181
Test name
Test status
Simulation time 23561989 ps
CPU time 0.94 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 218912 kb
Host smart-1113370d-2817-4e22-b26c-5a0ae03a8389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915103727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.915103727
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.522024925
Short name T653
Test name
Test status
Simulation time 102563019 ps
CPU time 1.22 seconds
Started Jul 01 11:10:38 AM PDT 24
Finished Jul 01 11:10:40 AM PDT 24
Peak memory 215628 kb
Host smart-c78b77f8-dda7-40d8-8aa5-599546f37bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522024925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.522024925
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2566627097
Short name T383
Test name
Test status
Simulation time 97621769 ps
CPU time 1.24 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 215932 kb
Host smart-c6b2624e-a0f6-4e44-9e8c-4bc92f8dd0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566627097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2566627097
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3198899126
Short name T160
Test name
Test status
Simulation time 34873065 ps
CPU time 1.02 seconds
Started Jul 01 11:10:44 AM PDT 24
Finished Jul 01 11:10:45 AM PDT 24
Peak memory 219824 kb
Host smart-7dfecd2c-8831-4f19-a4f5-303b2dc168a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198899126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3198899126
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3957766485
Short name T585
Test name
Test status
Simulation time 116545737 ps
CPU time 1.3 seconds
Started Jul 01 11:10:43 AM PDT 24
Finished Jul 01 11:10:45 AM PDT 24
Peak memory 217720 kb
Host smart-c9b1d044-4dad-45e9-b755-37b2b87657f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957766485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3957766485
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.767480097
Short name T259
Test name
Test status
Simulation time 59853723 ps
CPU time 1.22 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 220096 kb
Host smart-73220e6a-2e40-44ad-8194-44ed3594b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767480097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.767480097
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.105448625
Short name T493
Test name
Test status
Simulation time 34813224 ps
CPU time 1.01 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 207112 kb
Host smart-3f000e3d-0f9b-4fbb-b677-9ccfc70a7171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105448625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.105448625
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1567398266
Short name T810
Test name
Test status
Simulation time 32601943 ps
CPU time 0.83 seconds
Started Jul 01 11:09:40 AM PDT 24
Finished Jul 01 11:09:42 AM PDT 24
Peak memory 216300 kb
Host smart-3765b9c5-39db-41b5-958d-316dfd55b026
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567398266 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1567398266
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1533840329
Short name T403
Test name
Test status
Simulation time 34242397 ps
CPU time 0.99 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:53 AM PDT 24
Peak memory 218660 kb
Host smart-bf7ccd0b-6c8e-415f-a0a2-11670e673228
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533840329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1533840329
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3306044211
Short name T223
Test name
Test status
Simulation time 33579296 ps
CPU time 1.42 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:35 AM PDT 24
Peak memory 225864 kb
Host smart-3efc7b28-8eaa-40fa-8c59-0fa914f345b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306044211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3306044211
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2604220425
Short name T564
Test name
Test status
Simulation time 106591247 ps
CPU time 1.17 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 218880 kb
Host smart-7b10aa0b-4c98-4bca-a2af-5944d43f85d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604220425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2604220425
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1703357556
Short name T74
Test name
Test status
Simulation time 22305745 ps
CPU time 1.11 seconds
Started Jul 01 11:09:43 AM PDT 24
Finished Jul 01 11:09:44 AM PDT 24
Peak memory 215856 kb
Host smart-44519764-27a4-4444-8791-a93f0193c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703357556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1703357556
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.66720982
Short name T752
Test name
Test status
Simulation time 18833014 ps
CPU time 0.95 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 207412 kb
Host smart-065c68bd-4fda-4ce7-bcd6-93213ca62e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66720982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.66720982
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2061463265
Short name T793
Test name
Test status
Simulation time 59837057 ps
CPU time 0.92 seconds
Started Jul 01 11:09:29 AM PDT 24
Finished Jul 01 11:09:41 AM PDT 24
Peak memory 215608 kb
Host smart-e209ca62-c008-4aa0-8d2f-e8074d425768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061463265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2061463265
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1987282062
Short name T731
Test name
Test status
Simulation time 714544564 ps
CPU time 5.24 seconds
Started Jul 01 11:09:40 AM PDT 24
Finished Jul 01 11:09:45 AM PDT 24
Peak memory 215680 kb
Host smart-523f79e5-4584-4008-8b0b-cd65e9f1b4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987282062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1987282062
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4243047540
Short name T367
Test name
Test status
Simulation time 90031249118 ps
CPU time 2339.54 seconds
Started Jul 01 11:09:51 AM PDT 24
Finished Jul 01 11:48:51 AM PDT 24
Peak memory 240288 kb
Host smart-41743dfb-24e4-407f-b085-3d207ba54f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243047540 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4243047540
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2542749780
Short name T863
Test name
Test status
Simulation time 29302142 ps
CPU time 1.15 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 219896 kb
Host smart-d9759f6f-2b69-4e19-93a5-5d685316934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542749780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2542749780
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1757247823
Short name T148
Test name
Test status
Simulation time 19328349 ps
CPU time 1.19 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 224240 kb
Host smart-82581d12-9f18-4115-9379-60204246a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757247823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1757247823
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2264522177
Short name T789
Test name
Test status
Simulation time 41938430 ps
CPU time 1.6 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:49 AM PDT 24
Peak memory 218836 kb
Host smart-f7bdd989-c464-4772-822f-36eb41bf0640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264522177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2264522177
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2400406849
Short name T167
Test name
Test status
Simulation time 32998782 ps
CPU time 0.95 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 224044 kb
Host smart-4fa8f755-57f0-41f8-8978-fdf57a5bc28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400406849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2400406849
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.661767893
Short name T684
Test name
Test status
Simulation time 115826061 ps
CPU time 1.04 seconds
Started Jul 01 11:10:41 AM PDT 24
Finished Jul 01 11:10:42 AM PDT 24
Peak memory 217564 kb
Host smart-c55d9b85-3291-4fcc-9bfb-ba524309beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661767893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.661767893
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.957634132
Short name T875
Test name
Test status
Simulation time 22434843 ps
CPU time 1.18 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 219504 kb
Host smart-a7150b1e-2287-4029-9f05-81a41de9709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957634132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.957634132
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2885788295
Short name T189
Test name
Test status
Simulation time 20310258 ps
CPU time 1.02 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 218804 kb
Host smart-189883b3-337e-4403-ad37-ba4d13516f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885788295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2885788295
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3475509874
Short name T878
Test name
Test status
Simulation time 114889144 ps
CPU time 1.26 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:48 AM PDT 24
Peak memory 217620 kb
Host smart-7ba4f3ff-3801-4873-8fbb-87697c6e5d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475509874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3475509874
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.874334789
Short name T980
Test name
Test status
Simulation time 40098883 ps
CPU time 1.11 seconds
Started Jul 01 11:10:56 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 220700 kb
Host smart-6b238fe0-6be1-4c73-a3b0-e7da904fb042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874334789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.874334789
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.750581267
Short name T172
Test name
Test status
Simulation time 19684200 ps
CPU time 1.08 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 218792 kb
Host smart-74d24ef8-75cb-417e-b396-c4e0cf37b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750581267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.750581267
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.735712716
Short name T342
Test name
Test status
Simulation time 70300658 ps
CPU time 1.19 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 220120 kb
Host smart-6562db00-4498-4d68-b4ef-9d8e3defd803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735712716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.735712716
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1975057196
Short name T523
Test name
Test status
Simulation time 25319724 ps
CPU time 1.1 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 220072 kb
Host smart-7124342c-6faa-4d93-986a-e7e619a8ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975057196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1975057196
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1379250120
Short name T620
Test name
Test status
Simulation time 24293472 ps
CPU time 0.94 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:56 AM PDT 24
Peak memory 218812 kb
Host smart-69c33a1e-c309-446a-9f3a-81ae06951612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379250120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1379250120
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3168907585
Short name T314
Test name
Test status
Simulation time 34163445 ps
CPU time 1.28 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 220212 kb
Host smart-c7b633cb-3502-4c75-b5fc-2860cbda5d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168907585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3168907585
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.911366466
Short name T511
Test name
Test status
Simulation time 78448492 ps
CPU time 1.16 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 220424 kb
Host smart-8fb8f336-abcf-4a72-8d56-da6af9e9677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911366466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.911366466
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1910443903
Short name T476
Test name
Test status
Simulation time 53909569 ps
CPU time 1.18 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 219820 kb
Host smart-abdd4866-3c6c-4780-b5c9-9d55233b91d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910443903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1910443903
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.18123617
Short name T423
Test name
Test status
Simulation time 98784710 ps
CPU time 1.14 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 219820 kb
Host smart-fc240660-7c8c-40e2-9425-fc639f9bf6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18123617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.18123617
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1993056635
Short name T903
Test name
Test status
Simulation time 49576659 ps
CPU time 1.19 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:18 AM PDT 24
Peak memory 219476 kb
Host smart-93c1e344-a2f4-486c-b32b-54dd02277c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993056635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1993056635
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.4042422326
Short name T948
Test name
Test status
Simulation time 24655671 ps
CPU time 0.92 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 219172 kb
Host smart-b39a39e8-6299-42e7-8063-b05e2f0ebedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042422326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4042422326
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2738261564
Short name T42
Test name
Test status
Simulation time 112641102 ps
CPU time 1.26 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 217640 kb
Host smart-3a7c42cf-6930-4250-9606-56aad0a674d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738261564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2738261564
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1003734628
Short name T337
Test name
Test status
Simulation time 44195067 ps
CPU time 1.13 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 220072 kb
Host smart-d5d97155-18ae-40b3-9445-89f6044c1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003734628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1003734628
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.141205986
Short name T830
Test name
Test status
Simulation time 30698702 ps
CPU time 1.2 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 220084 kb
Host smart-35678936-c1d6-49c3-bfb7-d5d693377249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141205986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.141205986
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.496736556
Short name T414
Test name
Test status
Simulation time 111308899 ps
CPU time 1.37 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 220256 kb
Host smart-2a846eda-e488-4d27-806b-a885f2c54c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496736556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.496736556
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.847498973
Short name T572
Test name
Test status
Simulation time 27823458 ps
CPU time 1.22 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 218928 kb
Host smart-1acab70f-bb40-4b51-9d1f-26f1563e0a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847498973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.847498973
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3931742146
Short name T113
Test name
Test status
Simulation time 31183040 ps
CPU time 1.23 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 220820 kb
Host smart-f4ba3cb0-3854-478f-baa1-d7dd934bbdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931742146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3931742146
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1069661642
Short name T798
Test name
Test status
Simulation time 42184750 ps
CPU time 1.68 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 218768 kb
Host smart-ef52582d-0e67-438d-a9cd-9f8dfa1a429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069661642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1069661642
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2287441308
Short name T926
Test name
Test status
Simulation time 40263269 ps
CPU time 1.22 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 221140 kb
Host smart-c671c6ab-6df2-4c97-98b4-eda6cae798ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287441308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2287441308
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1030560200
Short name T769
Test name
Test status
Simulation time 74694264 ps
CPU time 1.04 seconds
Started Jul 01 11:10:53 AM PDT 24
Finished Jul 01 11:10:55 AM PDT 24
Peak memory 219864 kb
Host smart-cf2a79c2-1a29-40b7-b803-18dc4b0a8112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030560200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1030560200
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4192946704
Short name T733
Test name
Test status
Simulation time 34701538 ps
CPU time 1.34 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 219076 kb
Host smart-feda787c-6cd9-48e5-9826-4bcfbf141a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192946704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4192946704
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1613924160
Short name T773
Test name
Test status
Simulation time 33509981 ps
CPU time 1.24 seconds
Started Jul 01 11:10:05 AM PDT 24
Finished Jul 01 11:10:07 AM PDT 24
Peak memory 216032 kb
Host smart-b9c38c1d-d6aa-4295-a54e-2fcfd7ae365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613924160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1613924160
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1410613720
Short name T618
Test name
Test status
Simulation time 36865978 ps
CPU time 1 seconds
Started Jul 01 11:09:36 AM PDT 24
Finished Jul 01 11:09:40 AM PDT 24
Peak memory 215224 kb
Host smart-0ead44f4-91cf-49fc-a00a-39a0bd1cbf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410613720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1410613720
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1750032503
Short name T609
Test name
Test status
Simulation time 16420233 ps
CPU time 0.92 seconds
Started Jul 01 11:09:56 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 216572 kb
Host smart-5cb5a519-b1ff-4c0d-9112-51f91fee03da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750032503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1750032503
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3559051049
Short name T898
Test name
Test status
Simulation time 35272142 ps
CPU time 1.53 seconds
Started Jul 01 11:09:26 AM PDT 24
Finished Jul 01 11:09:32 AM PDT 24
Peak memory 217220 kb
Host smart-38723dd2-6c74-4335-a4e1-2f8d7c8ef3a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559051049 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3559051049
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3521489900
Short name T821
Test name
Test status
Simulation time 27688007 ps
CPU time 0.97 seconds
Started Jul 01 11:09:30 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 219804 kb
Host smart-a25a3f2b-66c1-4b1a-b9fd-6525335ed214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521489900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3521489900
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.596328355
Short name T985
Test name
Test status
Simulation time 41517808 ps
CPU time 1.22 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 219032 kb
Host smart-b769cb22-866f-4f4e-9131-b29fd6cd1127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596328355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.596328355
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2007274928
Short name T39
Test name
Test status
Simulation time 20817213 ps
CPU time 1.1 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 216264 kb
Host smart-330c7383-f2eb-4c04-8f93-3e63fb2fb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007274928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2007274928
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1729379632
Short name T31
Test name
Test status
Simulation time 28500652 ps
CPU time 0.98 seconds
Started Jul 01 11:09:58 AM PDT 24
Finished Jul 01 11:10:00 AM PDT 24
Peak memory 207516 kb
Host smart-caa16c23-6e07-4b11-acf4-74d31375e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729379632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1729379632
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3896497022
Short name T877
Test name
Test status
Simulation time 194913157 ps
CPU time 0.91 seconds
Started Jul 01 11:09:56 AM PDT 24
Finished Jul 01 11:09:57 AM PDT 24
Peak memory 215660 kb
Host smart-47ac0a9f-459c-4e28-88d2-c5ae8091c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896497022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3896497022
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2908807005
Short name T536
Test name
Test status
Simulation time 370189610 ps
CPU time 3.94 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:09:52 AM PDT 24
Peak memory 215560 kb
Host smart-ec7462fa-76dd-4039-b193-9769e1fad984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908807005 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2908807005
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3638780273
Short name T887
Test name
Test status
Simulation time 276338701303 ps
CPU time 1438.34 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:33:32 AM PDT 24
Peak memory 225932 kb
Host smart-b8176112-99d9-46c2-aef7-ccb1e8d7aba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638780273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3638780273
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.73052229
Short name T226
Test name
Test status
Simulation time 61763751 ps
CPU time 1.11 seconds
Started Jul 01 11:10:45 AM PDT 24
Finished Jul 01 11:10:47 AM PDT 24
Peak memory 221920 kb
Host smart-41238d32-de0f-4d04-988c-1dd6bf7c714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73052229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.73052229
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.470505337
Short name T212
Test name
Test status
Simulation time 20960514 ps
CPU time 1.1 seconds
Started Jul 01 11:10:48 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 219932 kb
Host smart-8c92c345-06d0-4f39-8a2a-10a4b1361a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470505337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.470505337
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3067460304
Short name T693
Test name
Test status
Simulation time 80091609 ps
CPU time 1.57 seconds
Started Jul 01 11:10:47 AM PDT 24
Finished Jul 01 11:10:50 AM PDT 24
Peak memory 218892 kb
Host smart-d7a408eb-160e-4192-b203-d7cc9c287e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067460304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3067460304
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.282568754
Short name T775
Test name
Test status
Simulation time 23769539 ps
CPU time 1.16 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 218804 kb
Host smart-16f82e2f-39ea-4abf-ac9a-3061446a2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282568754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.282568754
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1070233153
Short name T177
Test name
Test status
Simulation time 46067302 ps
CPU time 1.25 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 226096 kb
Host smart-d6c408fa-37d7-4f85-9cba-2a85b7008496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070233153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1070233153
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.507481362
Short name T322
Test name
Test status
Simulation time 168450753 ps
CPU time 1.33 seconds
Started Jul 01 11:10:51 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 219216 kb
Host smart-146632a7-4974-456c-9c16-86de29232c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507481362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.507481362
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.741791155
Short name T753
Test name
Test status
Simulation time 38106557 ps
CPU time 1.18 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:56 AM PDT 24
Peak memory 218896 kb
Host smart-e9ccc0d5-72e6-43e1-9935-8b31f8ad095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741791155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.741791155
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2227305918
Short name T638
Test name
Test status
Simulation time 26835120 ps
CPU time 1.19 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220016 kb
Host smart-a3d2506a-095a-4f35-a78e-f81454b7063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227305918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2227305918
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3747674238
Short name T456
Test name
Test status
Simulation time 160771810 ps
CPU time 1.01 seconds
Started Jul 01 11:11:13 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 217804 kb
Host smart-44268eb5-9bfa-4f41-98d8-ae955699636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747674238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3747674238
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1214874543
Short name T952
Test name
Test status
Simulation time 22123774 ps
CPU time 1.16 seconds
Started Jul 01 11:11:03 AM PDT 24
Finished Jul 01 11:11:07 AM PDT 24
Peak memory 218860 kb
Host smart-cf109060-1b03-4f59-a63b-a237b0895f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214874543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1214874543
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3582548838
Short name T220
Test name
Test status
Simulation time 27488730 ps
CPU time 1.24 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 221136 kb
Host smart-1f95e6bd-2184-42b1-885e-38df267e5597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582548838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3582548838
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.830125476
Short name T531
Test name
Test status
Simulation time 33100007 ps
CPU time 1.3 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 218748 kb
Host smart-0710929c-ba50-4695-9b08-5f201fede8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830125476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.830125476
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.610691851
Short name T848
Test name
Test status
Simulation time 37797603 ps
CPU time 1.08 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 219296 kb
Host smart-2dafc41d-b4b5-4839-9a8f-b6cc83ba86ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610691851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.610691851
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3913246852
Short name T17
Test name
Test status
Simulation time 37851963 ps
CPU time 1.01 seconds
Started Jul 01 11:10:56 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 224072 kb
Host smart-83430ec4-8978-4965-8332-753878151965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913246852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3913246852
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.898406246
Short name T317
Test name
Test status
Simulation time 49765184 ps
CPU time 1.83 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:49 AM PDT 24
Peak memory 219012 kb
Host smart-3d41ae63-b9f1-47e8-b2e4-f1c44b07e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898406246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.898406246
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3933021437
Short name T334
Test name
Test status
Simulation time 24701257 ps
CPU time 1.2 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:56 AM PDT 24
Peak memory 218252 kb
Host smart-f87d0ffb-2f40-4a9f-8c26-89c0a15d31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933021437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3933021437
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3085180885
Short name T191
Test name
Test status
Simulation time 23153658 ps
CPU time 0.91 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 218784 kb
Host smart-3696e2ef-fb32-488e-9da5-0e1d158a7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085180885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3085180885
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1665543764
Short name T631
Test name
Test status
Simulation time 107329359 ps
CPU time 1.27 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 219172 kb
Host smart-71b5338e-ac01-4874-8c69-f54cab535fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665543764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1665543764
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1640716898
Short name T88
Test name
Test status
Simulation time 45395766 ps
CPU time 1.19 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 218860 kb
Host smart-df5810b7-1115-42f7-aa87-7012d455ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640716898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1640716898
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.284668971
Short name T215
Test name
Test status
Simulation time 30854257 ps
CPU time 1.02 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 219792 kb
Host smart-eb61b6df-e341-4a3f-a28d-bf0324a08572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284668971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.284668971
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1178572056
Short name T45
Test name
Test status
Simulation time 57061209 ps
CPU time 1.57 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 218932 kb
Host smart-7063130d-8257-4c1b-8238-ec338d988717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178572056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1178572056
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3265809591
Short name T621
Test name
Test status
Simulation time 21509101 ps
CPU time 1.16 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 219984 kb
Host smart-310329f6-eebe-4e28-b943-97116d8a1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265809591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3265809591
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2175796927
Short name T761
Test name
Test status
Simulation time 41450282 ps
CPU time 0.99 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 220104 kb
Host smart-02ca5935-f65a-4a0c-9be8-1c6291181b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175796927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2175796927
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3377211596
Short name T651
Test name
Test status
Simulation time 462387180 ps
CPU time 3.15 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 219896 kb
Host smart-63d079cf-a604-4a3e-b0c6-6bcbfbdfed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377211596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3377211596
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3884304667
Short name T567
Test name
Test status
Simulation time 29198833 ps
CPU time 1.21 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 220148 kb
Host smart-666b73bc-d095-48a2-9fae-9dce25db1792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884304667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3884304667
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4103334617
Short name T139
Test name
Test status
Simulation time 35206311 ps
CPU time 1.05 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 221008 kb
Host smart-fec8422d-7bd1-424b-9d3e-f7b058dad351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103334617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4103334617
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4143011947
Short name T293
Test name
Test status
Simulation time 40959310 ps
CPU time 1.16 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 219004 kb
Host smart-7aa40f3f-36ab-4f3f-86e0-02766c194bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143011947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4143011947
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1966710649
Short name T135
Test name
Test status
Simulation time 78237311 ps
CPU time 1.15 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 218924 kb
Host smart-473774f3-5a4f-463e-82cf-62fc74882b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966710649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1966710649
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2105816360
Short name T961
Test name
Test status
Simulation time 27240504 ps
CPU time 0.87 seconds
Started Jul 01 11:10:46 AM PDT 24
Finished Jul 01 11:10:49 AM PDT 24
Peak memory 218520 kb
Host smart-7064a2f1-b4a2-491e-ac5d-a807da465f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105816360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2105816360
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3233922426
Short name T93
Test name
Test status
Simulation time 146315670 ps
CPU time 3.2 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 220556 kb
Host smart-209bd955-39e7-423c-a62d-6c5dc09f8cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233922426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3233922426
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3667913556
Short name T584
Test name
Test status
Simulation time 53031932 ps
CPU time 1.1 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 220132 kb
Host smart-09f79f11-0519-4ba3-ad66-85ac51355417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667913556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3667913556
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3645073379
Short name T583
Test name
Test status
Simulation time 21029944 ps
CPU time 0.96 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 215216 kb
Host smart-adbdabe1-65fc-4d89-baa9-8ce36bfb3ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645073379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3645073379
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.923472429
Short name T707
Test name
Test status
Simulation time 12416267 ps
CPU time 0.89 seconds
Started Jul 01 11:09:30 AM PDT 24
Finished Jul 01 11:09:42 AM PDT 24
Peak memory 215940 kb
Host smart-470c3aef-f2d4-4f34-b51a-37472f7a620c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923472429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.923472429
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1993137027
Short name T163
Test name
Test status
Simulation time 48016088 ps
CPU time 1.13 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 217348 kb
Host smart-b7d39f7c-3027-41ee-8be0-ea4d70f4666b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993137027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1993137027
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3585985709
Short name T153
Test name
Test status
Simulation time 32534773 ps
CPU time 1.07 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 230084 kb
Host smart-86ea4c87-59bf-4fc1-9c43-795093fa9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585985709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3585985709
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3812966828
Short name T568
Test name
Test status
Simulation time 125180834 ps
CPU time 1.31 seconds
Started Jul 01 11:09:47 AM PDT 24
Finished Jul 01 11:09:49 AM PDT 24
Peak memory 219328 kb
Host smart-ca7fc938-5867-4bc2-bdfd-6959ab35c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812966828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3812966828
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3048073460
Short name T99
Test name
Test status
Simulation time 23848511 ps
CPU time 0.91 seconds
Started Jul 01 11:09:28 AM PDT 24
Finished Jul 01 11:09:35 AM PDT 24
Peak memory 216076 kb
Host smart-e88f52f6-be40-4198-8bb0-3bfb0bed6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048073460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3048073460
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3989081501
Short name T30
Test name
Test status
Simulation time 23238640 ps
CPU time 0.89 seconds
Started Jul 01 11:09:32 AM PDT 24
Finished Jul 01 11:09:38 AM PDT 24
Peak memory 207380 kb
Host smart-63b3c4f0-07bd-4dd3-b161-a307cab2e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989081501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3989081501
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.709220025
Short name T420
Test name
Test status
Simulation time 18391037 ps
CPU time 0.92 seconds
Started Jul 01 11:09:52 AM PDT 24
Finished Jul 01 11:09:54 AM PDT 24
Peak memory 215488 kb
Host smart-ede8e032-3f3b-4882-bbe7-d272872bbd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709220025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.709220025
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1094335611
Short name T525
Test name
Test status
Simulation time 53618460 ps
CPU time 1.6 seconds
Started Jul 01 11:09:27 AM PDT 24
Finished Jul 01 11:09:35 AM PDT 24
Peak memory 215560 kb
Host smart-bce73da8-9c1b-4599-a766-33e01cc46b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094335611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1094335611
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.172623354
Short name T238
Test name
Test status
Simulation time 126924158733 ps
CPU time 238.31 seconds
Started Jul 01 11:09:41 AM PDT 24
Finished Jul 01 11:13:40 AM PDT 24
Peak memory 224032 kb
Host smart-1a8b7a9b-c00b-404e-982e-bc99e97686b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172623354 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.172623354
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1988876288
Short name T107
Test name
Test status
Simulation time 30658755 ps
CPU time 1.31 seconds
Started Jul 01 11:10:53 AM PDT 24
Finished Jul 01 11:10:55 AM PDT 24
Peak memory 216004 kb
Host smart-a53de87c-fa17-4773-a9c0-535f75bb59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988876288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1988876288
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.936922521
Short name T142
Test name
Test status
Simulation time 25887244 ps
CPU time 1 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 220008 kb
Host smart-dfcad504-0da2-4226-9fa3-827f4301e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936922521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.936922521
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_alert.1115630916
Short name T164
Test name
Test status
Simulation time 54967528 ps
CPU time 1.22 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 218744 kb
Host smart-95f8fe91-77c5-4b05-b3e9-ae739c064b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115630916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1115630916
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1839424643
Short name T251
Test name
Test status
Simulation time 19440326 ps
CPU time 1.03 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:58 AM PDT 24
Peak memory 215688 kb
Host smart-a4d629c7-7c0f-4380-b526-f6049ddf2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839424643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1839424643
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2776518936
Short name T697
Test name
Test status
Simulation time 55217284 ps
CPU time 1.34 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 218828 kb
Host smart-be27e787-eab6-4223-893d-764e6fa9424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776518936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2776518936
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3541788163
Short name T350
Test name
Test status
Simulation time 20608784 ps
CPU time 1.02 seconds
Started Jul 01 11:11:04 AM PDT 24
Finished Jul 01 11:11:08 AM PDT 24
Peak memory 218488 kb
Host smart-2553d086-bb22-425c-8192-991f79c44b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541788163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3541788163
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3446640513
Short name T257
Test name
Test status
Simulation time 73143986 ps
CPU time 1.12 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 217628 kb
Host smart-a284304c-f61d-42bc-b482-ea1288ddf2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446640513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3446640513
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2164631492
Short name T130
Test name
Test status
Simulation time 24996444 ps
CPU time 1.2 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 220024 kb
Host smart-7c08a43f-51b8-4636-8120-0e27d33e2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164631492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2164631492
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2711132650
Short name T174
Test name
Test status
Simulation time 20900129 ps
CPU time 1.04 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 218764 kb
Host smart-8859c01c-ae92-4194-a36d-b3b29e506daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711132650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2711132650
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.767657572
Short name T636
Test name
Test status
Simulation time 63274583 ps
CPU time 2.52 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:18 AM PDT 24
Peak memory 220692 kb
Host smart-48566733-d9de-472e-930d-f044af06d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767657572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.767657572
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3240844121
Short name T740
Test name
Test status
Simulation time 29035972 ps
CPU time 1.27 seconds
Started Jul 01 11:11:06 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 219512 kb
Host smart-c1a8b3a8-d4ae-4b5c-9a79-ce39a1246668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240844121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3240844121
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3563412875
Short name T766
Test name
Test status
Simulation time 20596912 ps
CPU time 1.04 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 218748 kb
Host smart-2dac8257-6cbf-4263-9c95-e8f88e2ce3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563412875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3563412875
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3848647886
Short name T667
Test name
Test status
Simulation time 67331827 ps
CPU time 1.23 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 217532 kb
Host smart-2ca6a00d-19be-4afc-9f60-80000979c2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848647886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3848647886
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1236696482
Short name T788
Test name
Test status
Simulation time 25873008 ps
CPU time 1.15 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 218948 kb
Host smart-c0bc84e2-f299-44ed-b3f0-bea5cb6e06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236696482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1236696482
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1433855686
Short name T936
Test name
Test status
Simulation time 36448095 ps
CPU time 0.83 seconds
Started Jul 01 11:11:01 AM PDT 24
Finished Jul 01 11:11:03 AM PDT 24
Peak memory 218260 kb
Host smart-31665054-a76a-4eea-b5f7-d660b95d6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433855686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1433855686
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1811410816
Short name T762
Test name
Test status
Simulation time 109485866 ps
CPU time 1.36 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 219156 kb
Host smart-d2dd5ee9-8b24-4820-873a-952a050ad116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811410816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1811410816
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2761910564
Short name T743
Test name
Test status
Simulation time 37674822 ps
CPU time 1.1 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:20 AM PDT 24
Peak memory 220132 kb
Host smart-d076810c-9519-48f8-a796-c57ca01db3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761910564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2761910564
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.971769907
Short name T884
Test name
Test status
Simulation time 30921195 ps
CPU time 0.91 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 218624 kb
Host smart-2dec6ef0-6a01-4064-8f64-86c3e4e1e81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971769907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.971769907
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.770393171
Short name T250
Test name
Test status
Simulation time 226994359 ps
CPU time 3.16 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:11 AM PDT 24
Peak memory 220640 kb
Host smart-b1de8740-7ddf-40da-bf5c-45aac6b5c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770393171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.770393171
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.787746873
Short name T196
Test name
Test status
Simulation time 67165251 ps
CPU time 1.17 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 221088 kb
Host smart-f6424f1b-7d32-4367-af79-df7ba6258c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787746873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.787746873
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1194460249
Short name T185
Test name
Test status
Simulation time 18094380 ps
CPU time 1.07 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 218720 kb
Host smart-eef35f1a-4f32-4020-a068-87bf3e583040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194460249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1194460249
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4087361377
Short name T958
Test name
Test status
Simulation time 32960849 ps
CPU time 1.38 seconds
Started Jul 01 11:10:52 AM PDT 24
Finished Jul 01 11:10:54 AM PDT 24
Peak memory 218916 kb
Host smart-62ee55bd-edd0-4fa5-8046-7b7ad6b6d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087361377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4087361377
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3999513924
Short name T286
Test name
Test status
Simulation time 32065867 ps
CPU time 1.38 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 215948 kb
Host smart-69c3b4bf-536f-4eaf-8b1b-537f8bf17e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999513924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3999513924
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.443592076
Short name T837
Test name
Test status
Simulation time 102687090 ps
CPU time 0.92 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 219892 kb
Host smart-6ff92082-409a-4fba-a2d9-9969b0806d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443592076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.443592076
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3775785144
Short name T548
Test name
Test status
Simulation time 55187913 ps
CPU time 0.96 seconds
Started Jul 01 11:10:55 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 217708 kb
Host smart-afc1e5cb-487f-4deb-9ab2-b14019e203bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775785144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3775785144
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1849523992
Short name T192
Test name
Test status
Simulation time 37065386 ps
CPU time 0.89 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 218668 kb
Host smart-d9546000-23e6-4147-a446-be5339689e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849523992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1849523992
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.958344271
Short name T767
Test name
Test status
Simulation time 112736810 ps
CPU time 1.3 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:03 AM PDT 24
Peak memory 217976 kb
Host smart-c94ec93b-a270-4399-89d9-58b5ee3553ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958344271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.958344271
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1460373505
Short name T51
Test name
Test status
Simulation time 39292010 ps
CPU time 1.11 seconds
Started Jul 01 11:09:31 AM PDT 24
Finished Jul 01 11:09:37 AM PDT 24
Peak memory 219052 kb
Host smart-eb58855d-44ab-40ad-b660-d42f11d471ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460373505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1460373505
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3922224026
Short name T660
Test name
Test status
Simulation time 68722994 ps
CPU time 1.01 seconds
Started Jul 01 11:09:57 AM PDT 24
Finished Jul 01 11:09:59 AM PDT 24
Peak memory 215460 kb
Host smart-35e563cb-bf0c-423f-bec2-04610f95b254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922224026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3922224026
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_err.2490864491
Short name T180
Test name
Test status
Simulation time 21210533 ps
CPU time 1.11 seconds
Started Jul 01 11:09:46 AM PDT 24
Finished Jul 01 11:09:48 AM PDT 24
Peak memory 218688 kb
Host smart-cde39a5d-3c5b-44bb-b86f-62ccb1ba96cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490864491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2490864491
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1293536646
Short name T909
Test name
Test status
Simulation time 77483267 ps
CPU time 1.05 seconds
Started Jul 01 11:09:45 AM PDT 24
Finished Jul 01 11:09:46 AM PDT 24
Peak memory 217600 kb
Host smart-62be09de-393d-4727-8c95-34a339400191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293536646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1293536646
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1428976457
Short name T670
Test name
Test status
Simulation time 47667733 ps
CPU time 0.98 seconds
Started Jul 01 11:09:54 AM PDT 24
Finished Jul 01 11:09:55 AM PDT 24
Peak memory 224276 kb
Host smart-00d8ce01-8528-4347-be7d-27465ddae181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428976457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1428976457
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2944149529
Short name T331
Test name
Test status
Simulation time 39431116 ps
CPU time 0.88 seconds
Started Jul 01 11:09:56 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 207420 kb
Host smart-a1c91d8d-bc8c-40d5-8bf1-034efb02446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944149529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2944149529
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2817955529
Short name T394
Test name
Test status
Simulation time 109522795 ps
CPU time 0.9 seconds
Started Jul 01 11:09:48 AM PDT 24
Finished Jul 01 11:09:50 AM PDT 24
Peak memory 215572 kb
Host smart-18374b0b-6af6-4339-be81-49d3a184d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817955529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2817955529
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1636957335
Short name T876
Test name
Test status
Simulation time 919632596 ps
CPU time 4.98 seconds
Started Jul 01 11:09:42 AM PDT 24
Finished Jul 01 11:09:47 AM PDT 24
Peak memory 217324 kb
Host smart-969caa5b-c12f-431f-a8d3-70cdd8601ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636957335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1636957335
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.777212015
Short name T864
Test name
Test status
Simulation time 27712101164 ps
CPU time 715.79 seconds
Started Jul 01 11:09:50 AM PDT 24
Finished Jul 01 11:21:47 AM PDT 24
Peak memory 217904 kb
Host smart-3851a50d-ef62-47ce-839d-266e73daa51d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777212015 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.777212015
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.397647092
Short name T724
Test name
Test status
Simulation time 24744791 ps
CPU time 1.21 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 220152 kb
Host smart-d84238ed-b619-4071-8d4c-6ecf462bbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397647092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.397647092
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2068361299
Short name T984
Test name
Test status
Simulation time 227703421 ps
CPU time 1.09 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 226080 kb
Host smart-6ce95014-4ac0-4b51-b5d5-b3eab4cf95c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068361299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2068361299
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3145052378
Short name T776
Test name
Test status
Simulation time 75070159 ps
CPU time 1.04 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 217596 kb
Host smart-9f2446fe-34c3-45c3-b835-fa33265d80a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145052378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3145052378
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3294524548
Short name T468
Test name
Test status
Simulation time 23223812 ps
CPU time 1.15 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 220132 kb
Host smart-cde39705-e53e-4b29-afe8-af4ee64df785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294524548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3294524548
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3965748120
Short name T124
Test name
Test status
Simulation time 27108094 ps
CPU time 1.32 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 230080 kb
Host smart-afd81e6a-328a-4f36-ad76-dfb1dd2b7384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965748120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3965748120
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.969720626
Short name T983
Test name
Test status
Simulation time 48124905 ps
CPU time 1.23 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 219292 kb
Host smart-10ff4f8f-b68a-4829-a523-1de2b456587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969720626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.969720626
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1899864285
Short name T490
Test name
Test status
Simulation time 29785803 ps
CPU time 1.32 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 218836 kb
Host smart-47240e72-2c2b-4902-acfc-62e9caa472eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899864285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1899864285
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2261178253
Short name T412
Test name
Test status
Simulation time 18894105 ps
CPU time 1.06 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:53 AM PDT 24
Peak memory 218408 kb
Host smart-aaed9b4e-27c9-4232-87a0-be86b5362bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261178253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2261178253
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.201989093
Short name T13
Test name
Test status
Simulation time 66117634 ps
CPU time 1.13 seconds
Started Jul 01 11:11:34 AM PDT 24
Finished Jul 01 11:11:37 AM PDT 24
Peak memory 220256 kb
Host smart-23b31990-3864-4c5d-a495-11706dca61e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201989093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.201989093
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2974585653
Short name T992
Test name
Test status
Simulation time 71467800 ps
CPU time 1.11 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 219828 kb
Host smart-7df84e08-2a02-4988-8863-5ff383d2bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974585653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2974585653
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2668410684
Short name T59
Test name
Test status
Simulation time 52263121 ps
CPU time 1.3 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 226008 kb
Host smart-d30b1a87-ee74-465e-b97b-60846f37e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668410684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2668410684
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1246300075
Short name T896
Test name
Test status
Simulation time 70387681 ps
CPU time 1.31 seconds
Started Jul 01 11:10:57 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 219248 kb
Host smart-2d51144b-2306-4a1c-9872-ec8d12e22c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246300075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1246300075
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2266536211
Short name T602
Test name
Test status
Simulation time 51364750 ps
CPU time 1.22 seconds
Started Jul 01 11:10:58 AM PDT 24
Finished Jul 01 11:11:01 AM PDT 24
Peak memory 216024 kb
Host smart-0fa49903-98a6-446b-93c1-cb2976fcf567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266536211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2266536211
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1099632094
Short name T881
Test name
Test status
Simulation time 25311374 ps
CPU time 0.94 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 218720 kb
Host smart-d3b86cab-c119-4a3c-8d2a-6133603970ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099632094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1099632094
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2558563876
Short name T374
Test name
Test status
Simulation time 24832299 ps
CPU time 1.27 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:06 AM PDT 24
Peak memory 217844 kb
Host smart-87cbe6f9-282a-479a-85f9-b900586ed310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558563876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2558563876
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2594646984
Short name T76
Test name
Test status
Simulation time 267991543 ps
CPU time 1.48 seconds
Started Jul 01 11:10:59 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 220156 kb
Host smart-1360969b-815c-499d-8b9a-1006e7cbaaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594646984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2594646984
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.604722326
Short name T246
Test name
Test status
Simulation time 44636636 ps
CPU time 1.17 seconds
Started Jul 01 11:11:10 AM PDT 24
Finished Jul 01 11:11:17 AM PDT 24
Peak memory 220088 kb
Host smart-199e7493-08e6-49a1-a638-6bb419bf1fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604722326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.604722326
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3473421518
Short name T95
Test name
Test status
Simulation time 48439845 ps
CPU time 1.16 seconds
Started Jul 01 11:11:08 AM PDT 24
Finished Jul 01 11:11:15 AM PDT 24
Peak memory 218916 kb
Host smart-8f2cd60b-e29c-4d6e-bb32-e9a2dd18e530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473421518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3473421518
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3203835920
Short name T66
Test name
Test status
Simulation time 56787199 ps
CPU time 1.14 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 219452 kb
Host smart-5b11cb79-1540-4357-bdcd-21f3969a1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203835920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3203835920
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.57578349
Short name T652
Test name
Test status
Simulation time 18755665 ps
CPU time 1.07 seconds
Started Jul 01 11:10:56 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 219120 kb
Host smart-308e94b3-27fa-453e-a89a-64a91f69bf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57578349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.57578349
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3027826541
Short name T376
Test name
Test status
Simulation time 38922341 ps
CPU time 1.56 seconds
Started Jul 01 11:11:07 AM PDT 24
Finished Jul 01 11:11:13 AM PDT 24
Peak memory 218884 kb
Host smart-70578df3-1483-4db5-aefc-a386436cb112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027826541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3027826541
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.4208840398
Short name T967
Test name
Test status
Simulation time 37685388 ps
CPU time 1.09 seconds
Started Jul 01 11:11:14 AM PDT 24
Finished Jul 01 11:11:21 AM PDT 24
Peak memory 219852 kb
Host smart-2163a978-5da5-449d-a7a4-432b8928855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208840398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.4208840398
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2155972802
Short name T216
Test name
Test status
Simulation time 41849751 ps
CPU time 1.13 seconds
Started Jul 01 11:10:54 AM PDT 24
Finished Jul 01 11:10:56 AM PDT 24
Peak memory 220336 kb
Host smart-5bef47be-83a0-4047-82d3-135744dbdc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155972802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2155972802
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2072390617
Short name T397
Test name
Test status
Simulation time 24284843 ps
CPU time 1.08 seconds
Started Jul 01 11:11:02 AM PDT 24
Finished Jul 01 11:11:05 AM PDT 24
Peak memory 217764 kb
Host smart-45017729-4174-4a2f-bbbf-a78a935bd5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072390617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2072390617
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3278798545
Short name T262
Test name
Test status
Simulation time 28559094 ps
CPU time 1.26 seconds
Started Jul 01 11:11:12 AM PDT 24
Finished Jul 01 11:11:24 AM PDT 24
Peak memory 219964 kb
Host smart-c7b7b3a0-7242-468f-8c86-e26ad4db8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278798545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3278798545
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3413146982
Short name T201
Test name
Test status
Simulation time 44015639 ps
CPU time 0.91 seconds
Started Jul 01 11:10:50 AM PDT 24
Finished Jul 01 11:10:52 AM PDT 24
Peak memory 219284 kb
Host smart-59ceab66-51d2-4a8d-a51f-d0d503c2a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413146982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3413146982
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1251508147
Short name T987
Test name
Test status
Simulation time 53270678 ps
CPU time 1.49 seconds
Started Jul 01 11:11:09 AM PDT 24
Finished Jul 01 11:11:16 AM PDT 24
Peak memory 219080 kb
Host smart-7699a76e-9127-4d37-8061-cf11c71cd911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251508147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1251508147
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3818173605
Short name T692
Test name
Test status
Simulation time 70972872 ps
CPU time 1.16 seconds
Started Jul 01 11:11:00 AM PDT 24
Finished Jul 01 11:11:02 AM PDT 24
Peak memory 221008 kb
Host smart-025cf383-6454-4e0e-81d7-2dcfb75aae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818173605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3818173605
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2461082288
Short name T184
Test name
Test status
Simulation time 44704128 ps
CPU time 0.91 seconds
Started Jul 01 11:11:05 AM PDT 24
Finished Jul 01 11:11:10 AM PDT 24
Peak memory 224096 kb
Host smart-49c33c39-f1b7-40b6-8b13-ab0cb4804807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461082288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2461082288
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.104033044
Short name T804
Test name
Test status
Simulation time 85038028 ps
CPU time 1.52 seconds
Started Jul 01 11:11:11 AM PDT 24
Finished Jul 01 11:11:19 AM PDT 24
Peak memory 219172 kb
Host smart-4343b465-f6ea-4b89-a86a-a3d1998371e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104033044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.104033044
Directory /workspace/99.edn_genbits/latest
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