Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

6756

1

T4

14

T5

8

T6

11

all_values[1]

6756

1

T4

14

T5

8

T6

11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6981

1

T4

22

T5

9

T6

11

auto[1]

6531

1

T4

6

T5

7

T6

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5284

1

T4

11

T5

8

T6

4

auto[1]

8228

1

T4

17

T5

8

T6

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7992

1

T4

19

T5

9

T6

10

auto[1]

5520

1

T4

9

T5

7

T6

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1411

1

T4

4

T5

1

T6

2

all_values[0]

auto[0]

auto[0]

auto[1]

674

1

T4

5

T6

2

T41

9

all_values[0]

auto[0]

auto[1]

auto[0]

1199

1

T5

2

T41

7

T42

43

all_values[0]

auto[0]

auto[1]

auto[1]

685

1

T4

2

T6

1

T41

6

all_values[0]

auto[1]

auto[0]

auto[1]

1486

1

T4

2

T5

4

T6

6

all_values[0]

auto[1]

auto[1]

auto[1]

1301

1

T4

1

T5

1

T41

11

all_values[1]

auto[0]

auto[0]

auto[0]

1327

1

T4

5

T5

2

T6

1

all_values[1]

auto[0]

auto[0]

auto[1]

642

1

T4

1

T41

11

T42

22

all_values[1]

auto[0]

auto[1]

auto[0]

1347

1

T4

2

T5

3

T6

1

all_values[1]

auto[0]

auto[1]

auto[1]

707

1

T5

1

T6

3

T41

5

all_values[1]

auto[1]

auto[0]

auto[1]

1441

1

T4

5

T5

2

T41

20

all_values[1]

auto[1]

auto[1]

auto[1]

1292

1

T4

1

T6

6

T41

7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal