Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.83 98.25 93.91 97.02 93.60 96.37 99.77 91.89


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1021 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3554185176 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:08 PM PDT 24 25617437 ps
T1022 /workspace/coverage/cover_reg_top/37.edn_intr_test.398265830 Jul 01 04:35:14 PM PDT 24 Jul 01 04:35:24 PM PDT 24 19612965 ps
T277 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1897293515 Jul 01 04:34:50 PM PDT 24 Jul 01 04:35:00 PM PDT 24 31786638 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1112759342 Jul 01 04:34:51 PM PDT 24 Jul 01 04:35:03 PM PDT 24 443607807 ps
T261 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1561262747 Jul 01 04:34:42 PM PDT 24 Jul 01 04:34:53 PM PDT 24 27622047 ps
T286 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2314958133 Jul 01 04:34:48 PM PDT 24 Jul 01 04:35:00 PM PDT 24 798216927 ps
T1024 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.985092514 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:11 PM PDT 24 190538564 ps
T278 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2035120478 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:57 PM PDT 24 106112445 ps
T279 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3150990342 Jul 01 04:35:06 PM PDT 24 Jul 01 04:35:15 PM PDT 24 17122884 ps
T280 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2587558864 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:13 PM PDT 24 58318792 ps
T1025 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1065693227 Jul 01 04:35:07 PM PDT 24 Jul 01 04:35:16 PM PDT 24 71598298 ps
T1026 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4223573389 Jul 01 04:34:51 PM PDT 24 Jul 01 04:35:03 PM PDT 24 332449133 ps
T1027 /workspace/coverage/cover_reg_top/36.edn_intr_test.2479304342 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:18 PM PDT 24 48467666 ps
T294 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2886943287 Jul 01 04:35:06 PM PDT 24 Jul 01 04:35:17 PM PDT 24 193457251 ps
T1028 /workspace/coverage/cover_reg_top/29.edn_intr_test.4292977853 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:18 PM PDT 24 12451221 ps
T1029 /workspace/coverage/cover_reg_top/49.edn_intr_test.3754774466 Jul 01 04:35:14 PM PDT 24 Jul 01 04:35:24 PM PDT 24 24417322 ps
T1030 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1216922565 Jul 01 04:34:50 PM PDT 24 Jul 01 04:35:02 PM PDT 24 114898413 ps
T1031 /workspace/coverage/cover_reg_top/16.edn_intr_test.479103116 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:12 PM PDT 24 22783906 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_csr_rw.481961396 Jul 01 04:34:46 PM PDT 24 Jul 01 04:34:57 PM PDT 24 21140911 ps
T281 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2734699774 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:18 PM PDT 24 26150233 ps
T1033 /workspace/coverage/cover_reg_top/47.edn_intr_test.158432050 Jul 01 04:35:25 PM PDT 24 Jul 01 04:35:35 PM PDT 24 21735762 ps
T1034 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3947296418 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:09 PM PDT 24 31699386 ps
T1035 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2591623843 Jul 01 04:34:54 PM PDT 24 Jul 01 04:35:02 PM PDT 24 22442941 ps
T1036 /workspace/coverage/cover_reg_top/11.edn_intr_test.3536116213 Jul 01 04:34:58 PM PDT 24 Jul 01 04:35:06 PM PDT 24 14585830 ps
T1037 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1243743802 Jul 01 04:34:58 PM PDT 24 Jul 01 04:35:06 PM PDT 24 114310064 ps
T1038 /workspace/coverage/cover_reg_top/21.edn_intr_test.386985960 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:18 PM PDT 24 42953319 ps
T1039 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2335387497 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:11 PM PDT 24 27171018 ps
T1040 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1141734946 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:56 PM PDT 24 39822412 ps
T262 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1449557130 Jul 01 04:34:49 PM PDT 24 Jul 01 04:35:00 PM PDT 24 32684464 ps
T1041 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.574160239 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:06 PM PDT 24 121755309 ps
T1042 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2990144589 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:12 PM PDT 24 209168968 ps
T268 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1929992001 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:58 PM PDT 24 58715605 ps
T1043 /workspace/coverage/cover_reg_top/46.edn_intr_test.4159325120 Jul 01 04:35:13 PM PDT 24 Jul 01 04:35:23 PM PDT 24 15485029 ps
T1044 /workspace/coverage/cover_reg_top/13.edn_intr_test.136332723 Jul 01 04:35:04 PM PDT 24 Jul 01 04:35:14 PM PDT 24 13928458 ps
T1045 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2510625968 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:07 PM PDT 24 49076238 ps
T1046 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2220629467 Jul 01 04:35:01 PM PDT 24 Jul 01 04:35:10 PM PDT 24 14606891 ps
T263 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1995513961 Jul 01 04:34:46 PM PDT 24 Jul 01 04:34:57 PM PDT 24 44649923 ps
T1047 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3402046853 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:12 PM PDT 24 41687014 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2392003942 Jul 01 04:34:49 PM PDT 24 Jul 01 04:35:00 PM PDT 24 22309728 ps
T295 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2550539533 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:53 PM PDT 24 276899010 ps
T1049 /workspace/coverage/cover_reg_top/7.edn_tl_errors.570719067 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:07 PM PDT 24 85521520 ps
T1050 /workspace/coverage/cover_reg_top/34.edn_intr_test.197503534 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:17 PM PDT 24 14551639 ps
T1051 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2200900153 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:10 PM PDT 24 311348436 ps
T1052 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3635223732 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:10 PM PDT 24 137690679 ps
T1053 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1376922446 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:07 PM PDT 24 372155367 ps
T1054 /workspace/coverage/cover_reg_top/5.edn_intr_test.3752926462 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:05 PM PDT 24 48098401 ps
T1055 /workspace/coverage/cover_reg_top/19.edn_intr_test.508600709 Jul 01 04:35:10 PM PDT 24 Jul 01 04:35:20 PM PDT 24 23834002 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3179588650 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:09 PM PDT 24 81897044 ps
T1057 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2694655804 Jul 01 04:34:46 PM PDT 24 Jul 01 04:34:59 PM PDT 24 1405163506 ps
T1058 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2489192178 Jul 01 04:34:55 PM PDT 24 Jul 01 04:35:03 PM PDT 24 41692310 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3104387022 Jul 01 04:34:48 PM PDT 24 Jul 01 04:35:00 PM PDT 24 165647278 ps
T1060 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.21624140 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:04 PM PDT 24 19220757 ps
T1061 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.660914548 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:06 PM PDT 24 174118753 ps
T1062 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1665295236 Jul 01 04:34:48 PM PDT 24 Jul 01 04:35:02 PM PDT 24 155086156 ps
T1063 /workspace/coverage/cover_reg_top/4.edn_intr_test.3855722653 Jul 01 04:34:47 PM PDT 24 Jul 01 04:34:58 PM PDT 24 26052668 ps
T1064 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1953947742 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:13 PM PDT 24 26199126 ps
T1065 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1415013497 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:05 PM PDT 24 20884057 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_intr_test.3922948403 Jul 01 04:34:46 PM PDT 24 Jul 01 04:34:58 PM PDT 24 14976590 ps
T1067 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2791842795 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:13 PM PDT 24 76751131 ps
T1068 /workspace/coverage/cover_reg_top/27.edn_intr_test.3859576116 Jul 01 04:35:07 PM PDT 24 Jul 01 04:35:16 PM PDT 24 70731213 ps
T1069 /workspace/coverage/cover_reg_top/24.edn_intr_test.2884574623 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:17 PM PDT 24 40991183 ps
T1070 /workspace/coverage/cover_reg_top/39.edn_intr_test.2770008324 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:17 PM PDT 24 159697867 ps
T1071 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3515797977 Jul 01 04:34:55 PM PDT 24 Jul 01 04:35:04 PM PDT 24 35309845 ps
T1072 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2076251967 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:11 PM PDT 24 614053021 ps
T1073 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.333754020 Jul 01 04:34:49 PM PDT 24 Jul 01 04:34:59 PM PDT 24 66323041 ps
T1074 /workspace/coverage/cover_reg_top/28.edn_intr_test.570193604 Jul 01 04:35:10 PM PDT 24 Jul 01 04:35:19 PM PDT 24 17186284 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4091865041 Jul 01 04:35:05 PM PDT 24 Jul 01 04:35:16 PM PDT 24 53463676 ps
T1076 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3803484680 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:09 PM PDT 24 131263436 ps
T1077 /workspace/coverage/cover_reg_top/38.edn_intr_test.2186769116 Jul 01 04:35:11 PM PDT 24 Jul 01 04:35:21 PM PDT 24 28041375 ps
T1078 /workspace/coverage/cover_reg_top/43.edn_intr_test.2096093854 Jul 01 04:35:10 PM PDT 24 Jul 01 04:35:19 PM PDT 24 13305710 ps
T1079 /workspace/coverage/cover_reg_top/26.edn_intr_test.3795663005 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:17 PM PDT 24 17471938 ps
T1080 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2358429548 Jul 01 04:34:49 PM PDT 24 Jul 01 04:34:59 PM PDT 24 18583255 ps
T264 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3959668850 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:05 PM PDT 24 13752265 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1535111842 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:11 PM PDT 24 78181894 ps
T1082 /workspace/coverage/cover_reg_top/10.edn_intr_test.1703165375 Jul 01 04:34:58 PM PDT 24 Jul 01 04:35:06 PM PDT 24 22641612 ps
T1083 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1215453864 Jul 01 04:34:54 PM PDT 24 Jul 01 04:35:02 PM PDT 24 85207855 ps
T1084 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1342393403 Jul 01 04:34:49 PM PDT 24 Jul 01 04:35:01 PM PDT 24 113061621 ps
T1085 /workspace/coverage/cover_reg_top/8.edn_intr_test.3210023965 Jul 01 04:34:58 PM PDT 24 Jul 01 04:35:06 PM PDT 24 44179317 ps
T1086 /workspace/coverage/cover_reg_top/8.edn_tl_errors.39161723 Jul 01 04:34:55 PM PDT 24 Jul 01 04:35:06 PM PDT 24 320954197 ps
T265 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1434015636 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:06 PM PDT 24 11262129 ps
T296 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1592586261 Jul 01 04:34:48 PM PDT 24 Jul 01 04:34:59 PM PDT 24 92227713 ps
T1087 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1174741513 Jul 01 04:34:56 PM PDT 24 Jul 01 04:35:04 PM PDT 24 15350844 ps
T1088 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3509985918 Jul 01 04:34:50 PM PDT 24 Jul 01 04:35:00 PM PDT 24 72420716 ps
T1089 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1483627976 Jul 01 04:34:44 PM PDT 24 Jul 01 04:34:56 PM PDT 24 32297176 ps
T1090 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.915293963 Jul 01 04:34:52 PM PDT 24 Jul 01 04:35:02 PM PDT 24 138544843 ps
T1091 /workspace/coverage/cover_reg_top/30.edn_intr_test.50026025 Jul 01 04:35:07 PM PDT 24 Jul 01 04:35:16 PM PDT 24 36646462 ps
T1092 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4148351432 Jul 01 04:34:47 PM PDT 24 Jul 01 04:34:58 PM PDT 24 192908683 ps
T1093 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.314264727 Jul 01 04:34:48 PM PDT 24 Jul 01 04:34:59 PM PDT 24 97887527 ps
T1094 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3204610978 Jul 01 04:34:46 PM PDT 24 Jul 01 04:34:57 PM PDT 24 13944225 ps
T1095 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3351672449 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:09 PM PDT 24 68246923 ps
T1096 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2306963153 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:12 PM PDT 24 75110070 ps
T1097 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1014138218 Jul 01 04:35:01 PM PDT 24 Jul 01 04:35:12 PM PDT 24 99935223 ps
T1098 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.849089179 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:06 PM PDT 24 72406507 ps
T1099 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.821664082 Jul 01 04:35:05 PM PDT 24 Jul 01 04:35:15 PM PDT 24 40478315 ps
T266 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.788300698 Jul 01 04:34:42 PM PDT 24 Jul 01 04:34:54 PM PDT 24 43117700 ps
T1100 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.246391705 Jul 01 04:34:49 PM PDT 24 Jul 01 04:35:01 PM PDT 24 31478205 ps
T1101 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3128147264 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:10 PM PDT 24 80090681 ps
T1102 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3054380 Jul 01 04:34:40 PM PDT 24 Jul 01 04:34:50 PM PDT 24 17640980 ps
T1103 /workspace/coverage/cover_reg_top/9.edn_intr_test.2544258301 Jul 01 04:35:00 PM PDT 24 Jul 01 04:35:09 PM PDT 24 28773601 ps
T267 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2309915828 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:05 PM PDT 24 13094600 ps
T270 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3644368500 Jul 01 04:34:39 PM PDT 24 Jul 01 04:34:48 PM PDT 24 11603876 ps
T1104 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3956925639 Jul 01 04:35:03 PM PDT 24 Jul 01 04:35:13 PM PDT 24 70312272 ps
T1105 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.711325435 Jul 01 04:34:58 PM PDT 24 Jul 01 04:35:07 PM PDT 24 40672206 ps
T1106 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3076825705 Jul 01 04:34:55 PM PDT 24 Jul 01 04:35:04 PM PDT 24 124226295 ps
T1107 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2077083437 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:21 PM PDT 24 250501992 ps
T1108 /workspace/coverage/cover_reg_top/25.edn_intr_test.2087367756 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:18 PM PDT 24 15151468 ps
T1109 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2526372735 Jul 01 04:34:57 PM PDT 24 Jul 01 04:35:05 PM PDT 24 53044977 ps
T1110 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2026222810 Jul 01 04:34:48 PM PDT 24 Jul 01 04:35:05 PM PDT 24 1058122461 ps
T1111 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2027310174 Jul 01 04:34:50 PM PDT 24 Jul 01 04:35:01 PM PDT 24 298301976 ps
T1112 /workspace/coverage/cover_reg_top/14.edn_intr_test.3588604879 Jul 01 04:35:05 PM PDT 24 Jul 01 04:35:14 PM PDT 24 45203207 ps
T1113 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3647421464 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:20 PM PDT 24 107784080 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3762830249 Jul 01 04:35:02 PM PDT 24 Jul 01 04:35:11 PM PDT 24 101400244 ps
T1115 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4264158446 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:52 PM PDT 24 139006419 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_intr_test.3964284533 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:19 PM PDT 24 12401224 ps
T1117 /workspace/coverage/cover_reg_top/33.edn_intr_test.4059590563 Jul 01 04:35:11 PM PDT 24 Jul 01 04:35:21 PM PDT 24 27824832 ps
T1118 /workspace/coverage/cover_reg_top/22.edn_intr_test.1083052062 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:18 PM PDT 24 29102310 ps
T1119 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2135418316 Jul 01 04:35:10 PM PDT 24 Jul 01 04:35:19 PM PDT 24 49279930 ps
T1120 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1071167638 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:18 PM PDT 24 79119060 ps
T1121 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2948464969 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:58 PM PDT 24 117024645 ps
T1122 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3366164532 Jul 01 04:34:47 PM PDT 24 Jul 01 04:34:59 PM PDT 24 160563533 ps
T1123 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2650817334 Jul 01 04:35:09 PM PDT 24 Jul 01 04:35:19 PM PDT 24 46650129 ps
T1124 /workspace/coverage/cover_reg_top/12.edn_intr_test.2915665530 Jul 01 04:34:59 PM PDT 24 Jul 01 04:35:07 PM PDT 24 30438487 ps
T269 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1677191406 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:52 PM PDT 24 17473563 ps
T1125 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1278950169 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:56 PM PDT 24 353733800 ps
T271 /workspace/coverage/cover_reg_top/13.edn_csr_rw.202471419 Jul 01 04:35:05 PM PDT 24 Jul 01 04:35:15 PM PDT 24 18087536 ps
T1126 /workspace/coverage/cover_reg_top/45.edn_intr_test.120008559 Jul 01 04:35:14 PM PDT 24 Jul 01 04:35:24 PM PDT 24 14346704 ps
T1127 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2696964227 Jul 01 04:35:06 PM PDT 24 Jul 01 04:35:17 PM PDT 24 109437098 ps
T1128 /workspace/coverage/cover_reg_top/40.edn_intr_test.1447874140 Jul 01 04:35:08 PM PDT 24 Jul 01 04:35:18 PM PDT 24 15479044 ps
T1129 /workspace/coverage/cover_reg_top/9.edn_tl_errors.76011346 Jul 01 04:35:04 PM PDT 24 Jul 01 04:35:15 PM PDT 24 47601500 ps
T1130 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1612748257 Jul 01 04:34:48 PM PDT 24 Jul 01 04:34:59 PM PDT 24 47506882 ps

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1601079680
Short name T4
Test name
Test status
Simulation time 80582021158 ps
CPU time 1455.26 seconds
Started Jul 01 05:36:19 PM PDT 24
Finished Jul 01 06:00:35 PM PDT 24
Peak memory 222736 kb
Host smart-04dda0d7-df27-4230-bfd5-e46423df299a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601079680 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1601079680
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.edn_genbits.910337991
Short name T13
Test name
Test status
Simulation time 112389058 ps
CPU time 1.41 seconds
Started Jul 01 05:39:17 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 220260 kb
Host smart-130e3c82-84a8-4d79-856a-a59ba6536b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910337991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.910337991
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1157779766
Short name T23
Test name
Test status
Simulation time 45183851 ps
CPU time 1.32 seconds
Started Jul 01 05:39:16 PM PDT 24
Finished Jul 01 05:39:18 PM PDT 24
Peak memory 219240 kb
Host smart-d0da9bfd-8e51-4130-accc-14418e15e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157779766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1157779766
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3835849704
Short name T18
Test name
Test status
Simulation time 560038734 ps
CPU time 8.53 seconds
Started Jul 01 05:35:40 PM PDT 24
Finished Jul 01 05:35:49 PM PDT 24
Peak memory 236808 kb
Host smart-99ebc17f-0518-4310-9126-a4b9086d9913
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835849704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3835849704
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2192339936
Short name T21
Test name
Test status
Simulation time 33292831 ps
CPU time 1.16 seconds
Started Jul 01 05:36:38 PM PDT 24
Finished Jul 01 05:36:40 PM PDT 24
Peak memory 218700 kb
Host smart-36005e00-2c6e-4d66-9c9d-ed8ed1f06d95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192339936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2192339936
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/113.edn_alert.3349981202
Short name T107
Test name
Test status
Simulation time 28919956 ps
CPU time 1.3 seconds
Started Jul 01 05:39:01 PM PDT 24
Finished Jul 01 05:39:05 PM PDT 24
Peak memory 220300 kb
Host smart-33e458c6-8ecd-4f3d-ab40-6761fe3f234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349981202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3349981202
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2712651532
Short name T62
Test name
Test status
Simulation time 495320628 ps
CPU time 7.25 seconds
Started Jul 01 05:35:33 PM PDT 24
Finished Jul 01 05:35:41 PM PDT 24
Peak memory 236692 kb
Host smart-70d37cec-f2b4-4f0a-ba83-143162ede9ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712651532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2712651532
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1059581142
Short name T42
Test name
Test status
Simulation time 56788639363 ps
CPU time 1465.37 seconds
Started Jul 01 05:34:58 PM PDT 24
Finished Jul 01 05:59:24 PM PDT 24
Peak memory 225236 kb
Host smart-9539bc10-864d-41f3-b874-e2c87b867321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059581142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1059581142
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.edn_alert.1138880850
Short name T129
Test name
Test status
Simulation time 24103429 ps
CPU time 1.17 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 220212 kb
Host smart-cc519bc4-b854-46f8-b5b5-5aea363daae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138880850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1138880850
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/171.edn_alert.2503734453
Short name T53
Test name
Test status
Simulation time 49645015 ps
CPU time 1.26 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 220224 kb
Host smart-e5c742f4-aadb-4de7-8b87-7ef4377f2a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503734453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2503734453
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.2213014669
Short name T28
Test name
Test status
Simulation time 27629714 ps
CPU time 0.93 seconds
Started Jul 01 05:35:11 PM PDT 24
Finished Jul 01 05:35:12 PM PDT 24
Peak memory 207508 kb
Host smart-27e71484-41cd-4073-a1e1-6cc653b99879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213014669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2213014669
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2834690762
Short name T67
Test name
Test status
Simulation time 29887543 ps
CPU time 1.19 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 219592 kb
Host smart-a1f19c28-3e33-41e2-91ce-d7faef55bf65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834690762 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2834690762
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1923528153
Short name T284
Test name
Test status
Simulation time 84768741 ps
CPU time 2.45 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 207184 kb
Host smart-864616f2-4df8-4635-9bc0-26755b9f2280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923528153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1923528153
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/48.edn_disable.1863739415
Short name T77
Test name
Test status
Simulation time 10848755 ps
CPU time 0.91 seconds
Started Jul 01 05:38:15 PM PDT 24
Finished Jul 01 05:38:17 PM PDT 24
Peak memory 216596 kb
Host smart-c8d44052-3891-4726-8b06-10f7ed6e04f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863739415 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1863739415
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/1.edn_genbits.2279296114
Short name T51
Test name
Test status
Simulation time 218437729 ps
CPU time 2.74 seconds
Started Jul 01 05:35:10 PM PDT 24
Finished Jul 01 05:35:13 PM PDT 24
Peak memory 218956 kb
Host smart-ad6e2462-dd84-4f90-a157-213044e2816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279296114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2279296114
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3291747493
Short name T579
Test name
Test status
Simulation time 96392198 ps
CPU time 1.22 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 216040 kb
Host smart-3eb92da0-de9b-4138-aa3c-a31012eac72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291747493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3291747493
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1443313901
Short name T141
Test name
Test status
Simulation time 34688184 ps
CPU time 1.25 seconds
Started Jul 01 05:35:38 PM PDT 24
Finished Jul 01 05:35:40 PM PDT 24
Peak memory 217280 kb
Host smart-e47cc36a-ef45-4f83-923a-8e7dcc33720f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443313901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1443313901
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/190.edn_alert.264027683
Short name T144
Test name
Test status
Simulation time 27642591 ps
CPU time 1.22 seconds
Started Jul 01 05:39:34 PM PDT 24
Finished Jul 01 05:39:38 PM PDT 24
Peak memory 219068 kb
Host smart-65e4c1ae-709c-45b8-8675-9857dffb8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264027683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.264027683
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.2508187750
Short name T196
Test name
Test status
Simulation time 41846297 ps
CPU time 0.87 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 216600 kb
Host smart-3d69870a-b051-4461-a612-948e0ffc52d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508187750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2508187750
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/99.edn_err.251699353
Short name T190
Test name
Test status
Simulation time 18733890 ps
CPU time 1.08 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 218884 kb
Host smart-e7a46bd7-b4d7-44f0-9c21-11aca30bc58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251699353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.251699353
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1995513961
Short name T263
Test name
Test status
Simulation time 44649923 ps
CPU time 1.04 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 206836 kb
Host smart-9ec7ea49-aab8-4ab0-904f-f6927bedcbd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995513961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1995513961
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/56.edn_alert.427675075
Short name T17
Test name
Test status
Simulation time 65738973 ps
CPU time 1.1 seconds
Started Jul 01 05:38:28 PM PDT 24
Finished Jul 01 05:38:31 PM PDT 24
Peak memory 219064 kb
Host smart-dca972fa-402e-4307-9a5a-5151dec407d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427675075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.427675075
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/86.edn_alert.1046904820
Short name T151
Test name
Test status
Simulation time 25230167 ps
CPU time 1.25 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 218944 kb
Host smart-c1922a63-c54d-4143-b405-8eb623cb766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046904820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1046904820
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/49.edn_genbits.1831638527
Short name T82
Test name
Test status
Simulation time 212482544 ps
CPU time 1.42 seconds
Started Jul 01 05:38:20 PM PDT 24
Finished Jul 01 05:38:23 PM PDT 24
Peak memory 220520 kb
Host smart-83b9477c-4e9b-4457-bfc8-b481d099d45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831638527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1831638527
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4125943802
Short name T251
Test name
Test status
Simulation time 34470656 ps
CPU time 1.31 seconds
Started Jul 01 05:37:07 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 216048 kb
Host smart-e7cc3838-a61a-4d27-b712-23a6cb819280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125943802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4125943802
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/38.edn_intr.1021207437
Short name T32
Test name
Test status
Simulation time 21808451 ps
CPU time 1.08 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:52 PM PDT 24
Peak memory 216240 kb
Host smart-c869d7ad-2e1b-48e5-825b-980075c23b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021207437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1021207437
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.63823392
Short name T202
Test name
Test status
Simulation time 94399581255 ps
CPU time 2010.43 seconds
Started Jul 01 05:37:15 PM PDT 24
Finished Jul 01 06:10:48 PM PDT 24
Peak memory 227232 kb
Host smart-37d7a9b8-5fa7-4a66-8fba-ac103fd0c9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63823392 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.63823392
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.2866197663
Short name T92
Test name
Test status
Simulation time 76157828 ps
CPU time 1.07 seconds
Started Jul 01 05:36:28 PM PDT 24
Finished Jul 01 05:36:31 PM PDT 24
Peak memory 220908 kb
Host smart-992d975e-e32e-4fd8-a6b0-1b3ab837f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866197663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2866197663
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.1563960435
Short name T187
Test name
Test status
Simulation time 30139410 ps
CPU time 1.28 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 216040 kb
Host smart-854f2470-3fc8-4740-af6f-2e7d6c97bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563960435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1563960435
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/196.edn_alert.1536429240
Short name T183
Test name
Test status
Simulation time 46609908 ps
CPU time 1.2 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 222144 kb
Host smart-a0f7864d-0858-474b-9cd2-843d6512ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536429240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1536429240
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert.3139264621
Short name T125
Test name
Test status
Simulation time 37444482 ps
CPU time 1.2 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:38:14 PM PDT 24
Peak memory 220156 kb
Host smart-4aa10eb4-d1e5-4b2d-b53e-cd07f4ddf1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139264621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3139264621
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.3341379208
Short name T844
Test name
Test status
Simulation time 42656162 ps
CPU time 1.18 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 219928 kb
Host smart-17b5aef8-c86a-4a04-8e82-7e576cc227c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341379208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3341379208
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2630552212
Short name T60
Test name
Test status
Simulation time 34804162 ps
CPU time 1 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 224216 kb
Host smart-90afde24-9587-4aba-9b57-8975e575457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630552212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2630552212
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/199.edn_genbits.959510471
Short name T52
Test name
Test status
Simulation time 119616037 ps
CPU time 1.7 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 219184 kb
Host smart-a8fd959b-d473-447e-a65b-67ac01b162d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959510471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.959510471
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2062597405
Short name T155
Test name
Test status
Simulation time 24383565 ps
CPU time 1.3 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 219688 kb
Host smart-601375c0-f137-42d4-b3d3-eadcf1e0e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062597405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2062597405
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.145612727
Short name T186
Test name
Test status
Simulation time 17795742 ps
CPU time 0.87 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 216600 kb
Host smart-ce9c28bd-8170-46ca-bd8f-3edcb13ab6b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145612727 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.145612727
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/14.edn_intr.780222035
Short name T98
Test name
Test status
Simulation time 27104185 ps
CPU time 0.83 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:28 PM PDT 24
Peak memory 215876 kb
Host smart-165ee3ac-11ff-4009-bb92-422bb99fb904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780222035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.780222035
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.2434039
Short name T200
Test name
Test status
Simulation time 11933786 ps
CPU time 0.89 seconds
Started Jul 01 05:35:17 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 216764 kb
Host smart-91ca64f7-f207-4adc-90ab-95ff88c1890c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2434039
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.2363425402
Short name T882
Test name
Test status
Simulation time 14823060 ps
CPU time 0.9 seconds
Started Jul 01 05:36:12 PM PDT 24
Finished Jul 01 05:36:14 PM PDT 24
Peak memory 216712 kb
Host smart-c042906c-fb15-4fe8-9751-81e50f2366bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363425402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2363425402
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/119.edn_alert.562213077
Short name T526
Test name
Test status
Simulation time 49330819 ps
CPU time 1.2 seconds
Started Jul 01 05:39:03 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 220024 kb
Host smart-7aee6cbf-fb79-4177-9aca-ed0dbbb80b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562213077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.562213077
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.773898983
Short name T123
Test name
Test status
Simulation time 38892786 ps
CPU time 1.25 seconds
Started Jul 01 05:36:20 PM PDT 24
Finished Jul 01 05:36:22 PM PDT 24
Peak memory 217164 kb
Host smart-1a7c8a78-2dcc-49f8-9e2d-9891af7d4725
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773898983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.773898983
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable.3399437769
Short name T205
Test name
Test status
Simulation time 17903708 ps
CPU time 0.81 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 216656 kb
Host smart-a13949ce-4a5f-40b6-8191-e17acc9d1b0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399437769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3399437769
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4205963303
Short name T420
Test name
Test status
Simulation time 226887849 ps
CPU time 1.04 seconds
Started Jul 01 05:36:31 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 220172 kb
Host smart-8b922f61-04be-48bd-ac74-347b407ffbb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205963303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4205963303
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.318198202
Short name T215
Test name
Test status
Simulation time 13620176 ps
CPU time 0.91 seconds
Started Jul 01 05:36:39 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 216804 kb
Host smart-5310e2a5-e1c7-4caf-9a17-3705f7a86551
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318198202 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.318198202
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.3079710689
Short name T81
Test name
Test status
Simulation time 19103706 ps
CPU time 0.87 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:47 PM PDT 24
Peak memory 216544 kb
Host smart-bacb0b2c-2c2a-4afd-9d13-9010a71abff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079710689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3079710689
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.992861686
Short name T609
Test name
Test status
Simulation time 60208948 ps
CPU time 1.13 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:48 PM PDT 24
Peak memory 217404 kb
Host smart-234637b5-3004-45ad-8778-6800e9dc387b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992861686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.992861686
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.983842942
Short name T203
Test name
Test status
Simulation time 11440934 ps
CPU time 0.85 seconds
Started Jul 01 05:35:29 PM PDT 24
Finished Jul 01 05:35:31 PM PDT 24
Peak memory 216576 kb
Host smart-830ae13b-7673-4714-8cda-a3cd694126ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983842942 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.983842942
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.171487187
Short name T957
Test name
Test status
Simulation time 29065941 ps
CPU time 0.89 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:01 PM PDT 24
Peak memory 215576 kb
Host smart-c7c88dc8-2e9e-4a70-9474-f45d542a3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171487187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.171487187
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1071887126
Short name T142
Test name
Test status
Simulation time 17271734 ps
CPU time 0.99 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:07 PM PDT 24
Peak memory 217340 kb
Host smart-7e964601-7797-4d5f-b090-44bdeaf97c09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071887126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1071887126
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_disable.860229200
Short name T197
Test name
Test status
Simulation time 37968996 ps
CPU time 0.85 seconds
Started Jul 01 05:38:07 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 216664 kb
Host smart-4dcdd71c-3b23-45bb-a17d-261228487aad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860229200 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.860229200
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.1320368811
Short name T194
Test name
Test status
Simulation time 21653763 ps
CPU time 1.21 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 229868 kb
Host smart-87ef53c3-d681-4f08-9c45-cba659b9f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320368811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1320368811
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/282.edn_genbits.1034637709
Short name T299
Test name
Test status
Simulation time 82781824 ps
CPU time 1.31 seconds
Started Jul 01 05:39:54 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 219012 kb
Host smart-52070ab0-6410-4cb0-aa70-970aec09bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034637709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1034637709
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3830565478
Short name T673
Test name
Test status
Simulation time 81871707 ps
CPU time 1.16 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:39 PM PDT 24
Peak memory 220048 kb
Host smart-b40b8f61-bd6e-45c2-8d22-10c48ba4705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830565478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3830565478
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2953680837
Short name T358
Test name
Test status
Simulation time 16890351 ps
CPU time 1 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:36 PM PDT 24
Peak memory 207088 kb
Host smart-4ba0460b-3f9a-4aa1-ac6f-d9f3205c9ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953680837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2953680837
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2788040524
Short name T41
Test name
Test status
Simulation time 22751745712 ps
CPU time 516.48 seconds
Started Jul 01 05:36:40 PM PDT 24
Finished Jul 01 05:45:18 PM PDT 24
Peak memory 224120 kb
Host smart-082e7dc7-b927-4c15-a6c3-db663357af4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788040524 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2788040524
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_genbits.3883238031
Short name T11
Test name
Test status
Simulation time 87094553 ps
CPU time 1.25 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 219808 kb
Host smart-b419d499-7321-4c2d-a315-afdaa453aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883238031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3883238031
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2244401172
Short name T871
Test name
Test status
Simulation time 109540572485 ps
CPU time 1374.65 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:59:06 PM PDT 24
Peak memory 226564 kb
Host smart-3df69799-24b4-4fc3-8930-5590ec2d51f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244401172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2244401172
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_intr.3968707169
Short name T99
Test name
Test status
Simulation time 35201824 ps
CPU time 0.93 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:01 PM PDT 24
Peak memory 216152 kb
Host smart-3b2be148-0724-4cd0-b7a9-32fe5e46cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968707169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3968707169
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1897293515
Short name T277
Test name
Test status
Simulation time 31786638 ps
CPU time 0.98 seconds
Started Jul 01 04:34:50 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206900 kb
Host smart-935ecb45-5088-4176-a812-356518715c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897293515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1897293515
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/125.edn_genbits.1562683608
Short name T317
Test name
Test status
Simulation time 48981751 ps
CPU time 1.33 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 218996 kb
Host smart-fcda2983-04bd-4e5e-9684-88588df69fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562683608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1562683608
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.2285889778
Short name T313
Test name
Test status
Simulation time 59566928 ps
CPU time 1.1 seconds
Started Jul 01 05:36:21 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 219172 kb
Host smart-5151e129-9373-4678-8984-26c35d70987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285889778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2285889778
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1103762049
Short name T237
Test name
Test status
Simulation time 337593323644 ps
CPU time 1217.84 seconds
Started Jul 01 05:36:22 PM PDT 24
Finished Jul 01 05:56:42 PM PDT 24
Peak memory 221960 kb
Host smart-108ec28b-44e6-47e9-b5b3-c2364482df58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103762049 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1103762049
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.edn_genbits.3744740982
Short name T300
Test name
Test status
Simulation time 53525579 ps
CPU time 1.2 seconds
Started Jul 01 05:39:11 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 218968 kb
Host smart-7acdae36-8ab0-44b7-be2a-fd19d6fba5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744740982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3744740982
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/160.edn_genbits.2948084890
Short name T791
Test name
Test status
Simulation time 50796540 ps
CPU time 1.73 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 217688 kb
Host smart-1d176d19-0dec-457b-aff4-156f9dd47c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948084890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2948084890
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.6340061
Short name T303
Test name
Test status
Simulation time 75535767 ps
CPU time 2.55 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:38 PM PDT 24
Peak memory 220452 kb
Host smart-3b735904-f5b0-417f-84f2-24029cee807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6340061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.6340061
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2855198441
Short name T316
Test name
Test status
Simulation time 45419978 ps
CPU time 1.55 seconds
Started Jul 01 05:39:28 PM PDT 24
Finished Jul 01 05:39:32 PM PDT 24
Peak memory 218768 kb
Host smart-57afd235-3ec9-48a3-961b-dab685e12af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855198441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2855198441
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3223784358
Short name T309
Test name
Test status
Simulation time 86011217 ps
CPU time 1.26 seconds
Started Jul 01 05:39:41 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 220500 kb
Host smart-307c35a2-e346-4344-9f5d-465498458b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223784358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3223784358
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3641856173
Short name T35
Test name
Test status
Simulation time 22824996 ps
CPU time 0.96 seconds
Started Jul 01 05:37:15 PM PDT 24
Finished Jul 01 05:37:18 PM PDT 24
Peak memory 216048 kb
Host smart-03e961d8-4fd1-4f32-9ed7-06f1ac584593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641856173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3641856173
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/87.edn_err.3798551046
Short name T9
Test name
Test status
Simulation time 33122199 ps
CPU time 0.92 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 219896 kb
Host smart-c272437e-5bd0-43cb-b0d2-290852001acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798551046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3798551046
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.970320528
Short name T1011
Test name
Test status
Simulation time 678616290 ps
CPU time 5.16 seconds
Started Jul 01 04:34:42 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 206972 kb
Host smart-91e2c6aa-b1ae-4e78-9b09-6fc9b11772e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970320528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.970320528
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.788300698
Short name T266
Test name
Test status
Simulation time 43117700 ps
CPU time 0.85 seconds
Started Jul 01 04:34:42 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 206908 kb
Host smart-62687f71-ee06-4e1c-a000-82f7fdff20c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788300698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.788300698
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3054380
Short name T1102
Test name
Test status
Simulation time 17640980 ps
CPU time 1.24 seconds
Started Jul 01 04:34:40 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 215176 kb
Host smart-db4f866f-b3c9-4d75-a15a-6efbf910b576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054380 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3054380
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3204610978
Short name T1094
Test name
Test status
Simulation time 13944225 ps
CPU time 0.89 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 206892 kb
Host smart-4b8d2ad2-b0a5-4493-897d-d6ecb719cc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204610978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3204610978
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2241274215
Short name T1015
Test name
Test status
Simulation time 24764113 ps
CPU time 0.88 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206740 kb
Host smart-e61feb4b-703f-4864-95e6-653d7afcf0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241274215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2241274215
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4264158446
Short name T1115
Test name
Test status
Simulation time 139006419 ps
CPU time 1.44 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 206868 kb
Host smart-995759f7-7afd-466f-89e1-fc85c4a5902a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264158446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4264158446
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1665295236
Short name T1062
Test name
Test status
Simulation time 155086156 ps
CPU time 4.76 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 215168 kb
Host smart-2d84fb0a-4262-44a5-a235-2962db376f43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665295236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1665295236
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4148351432
Short name T1092
Test name
Test status
Simulation time 192908683 ps
CPU time 1.68 seconds
Started Jul 01 04:34:47 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 207308 kb
Host smart-c8b34588-0d7e-4a5b-8678-5a4813f09ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148351432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4148351432
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.131025286
Short name T258
Test name
Test status
Simulation time 41105471 ps
CPU time 1.73 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 207108 kb
Host smart-8016f01d-78a5-4f59-a10c-2dd3b5993310
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131025286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.131025286
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1278950169
Short name T1125
Test name
Test status
Simulation time 353733800 ps
CPU time 5.13 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 206920 kb
Host smart-f7bc9c5c-0c4d-489b-a1c0-a22dc0de68c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278950169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1278950169
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.857403118
Short name T1000
Test name
Test status
Simulation time 36077471 ps
CPU time 0.94 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 206780 kb
Host smart-da676ced-6db9-4d1b-a5e0-d6e1e06df8cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857403118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.857403118
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1483627976
Short name T1089
Test name
Test status
Simulation time 32297176 ps
CPU time 1.23 seconds
Started Jul 01 04:34:44 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 215188 kb
Host smart-087d4861-d261-465d-b61b-35d823315a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483627976 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1483627976
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3644368500
Short name T270
Test name
Test status
Simulation time 11603876 ps
CPU time 0.92 seconds
Started Jul 01 04:34:39 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 207068 kb
Host smart-7abbca22-fbfb-49fc-a95a-9358c667357c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644368500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3644368500
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3350237829
Short name T1016
Test name
Test status
Simulation time 14451421 ps
CPU time 0.88 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 206724 kb
Host smart-0d9ec8dd-11c1-4301-adbd-a89eda5ad9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350237829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3350237829
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2694655804
Short name T1057
Test name
Test status
Simulation time 1405163506 ps
CPU time 2.81 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 215140 kb
Host smart-764b21fe-1ba2-40ee-a398-f6b58fa11aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694655804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2694655804
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2550539533
Short name T295
Test name
Test status
Simulation time 276899010 ps
CPU time 1.64 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 207036 kb
Host smart-544ad0ff-9f33-482f-a35b-149f2d3f05ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550539533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2550539533
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3630407719
Short name T1014
Test name
Test status
Simulation time 99398478 ps
CPU time 1.33 seconds
Started Jul 01 04:34:55 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 218048 kb
Host smart-0df4e899-860b-429b-b6cd-6a3a88c24104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630407719 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3630407719
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3959668850
Short name T264
Test name
Test status
Simulation time 13752265 ps
CPU time 0.92 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 206932 kb
Host smart-692d7ff0-06b0-4193-b0ce-bebfeb88e33b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959668850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3959668850
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1703165375
Short name T1082
Test name
Test status
Simulation time 22641612 ps
CPU time 0.87 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206888 kb
Host smart-dcabdb29-0a4f-45f6-9b82-2586659a0071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703165375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1703165375
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2355754312
Short name T275
Test name
Test status
Simulation time 24286115 ps
CPU time 1.25 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206928 kb
Host smart-7065eb40-2211-4935-935a-af0ea96c7728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355754312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2355754312
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3128147264
Short name T1101
Test name
Test status
Simulation time 80090681 ps
CPU time 2.86 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:10 PM PDT 24
Peak memory 215192 kb
Host smart-171e3606-1da8-419a-b309-35739b477b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128147264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3128147264
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.711325435
Short name T1105
Test name
Test status
Simulation time 40672206 ps
CPU time 1.13 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 217484 kb
Host smart-6539f048-7444-47c0-8fcf-853ec3722f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711325435 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.711325435
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1174741513
Short name T1087
Test name
Test status
Simulation time 15350844 ps
CPU time 0.88 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 206704 kb
Host smart-9f6deb6c-3cb9-46c8-b45b-9a4f36e3f3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174741513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1174741513
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3536116213
Short name T1036
Test name
Test status
Simulation time 14585830 ps
CPU time 0.9 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206788 kb
Host smart-f082130b-0ceb-4fd3-a90d-00f5631b5256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536116213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3536116213
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3076825705
Short name T1106
Test name
Test status
Simulation time 124226295 ps
CPU time 1.1 seconds
Started Jul 01 04:34:55 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 206892 kb
Host smart-92d280ad-6be8-4ccb-9913-d4ed1adad59c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076825705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3076825705
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3351672449
Short name T1095
Test name
Test status
Simulation time 68246923 ps
CPU time 2.41 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:09 PM PDT 24
Peak memory 215192 kb
Host smart-ca79a130-cf06-4d63-8df0-661447e74f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351672449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3351672449
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.574160239
Short name T1041
Test name
Test status
Simulation time 121755309 ps
CPU time 2.24 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 207080 kb
Host smart-63d95c24-40fd-40df-a772-654063c82f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574160239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.574160239
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1215453864
Short name T1083
Test name
Test status
Simulation time 85207855 ps
CPU time 1.1 seconds
Started Jul 01 04:34:54 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 215100 kb
Host smart-87094cad-6979-4f2d-a15f-7a30e56214c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215453864 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1215453864
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2489192178
Short name T1058
Test name
Test status
Simulation time 41692310 ps
CPU time 0.83 seconds
Started Jul 01 04:34:55 PM PDT 24
Finished Jul 01 04:35:03 PM PDT 24
Peak memory 206756 kb
Host smart-e7abb092-9e6b-4f3a-b01c-e6296236a13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489192178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2489192178
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2915665530
Short name T1124
Test name
Test status
Simulation time 30438487 ps
CPU time 0.81 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 206564 kb
Host smart-d4716679-fa4c-4f2b-b4f2-6596981472df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915665530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2915665530
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3947296418
Short name T1034
Test name
Test status
Simulation time 31699386 ps
CPU time 1.14 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:09 PM PDT 24
Peak memory 207000 kb
Host smart-c7633824-4b21-48b7-ab6c-55412c8778cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947296418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3947296418
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4091865041
Short name T1075
Test name
Test status
Simulation time 53463676 ps
CPU time 2.27 seconds
Started Jul 01 04:35:05 PM PDT 24
Finished Jul 01 04:35:16 PM PDT 24
Peak memory 215072 kb
Host smart-fd6cbe1a-7110-414d-b364-34803146834a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091865041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4091865041
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.966468691
Short name T285
Test name
Test status
Simulation time 124979551 ps
CPU time 2.99 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206812 kb
Host smart-3d759d9c-d578-4fe1-8922-5e2d2678b379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966468691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.966468691
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1953947742
Short name T1064
Test name
Test status
Simulation time 26199126 ps
CPU time 1.21 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 215072 kb
Host smart-81fc27a1-06e6-4404-9555-862960db3edf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953947742 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1953947742
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.202471419
Short name T271
Test name
Test status
Simulation time 18087536 ps
CPU time 1 seconds
Started Jul 01 04:35:05 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 206900 kb
Host smart-43cbd8bc-8b45-481b-a729-8e37e052d982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202471419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.202471419
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.136332723
Short name T1044
Test name
Test status
Simulation time 13928458 ps
CPU time 0.92 seconds
Started Jul 01 04:35:04 PM PDT 24
Finished Jul 01 04:35:14 PM PDT 24
Peak memory 206772 kb
Host smart-eaa1f31d-9cde-4c62-a181-4f0ed92f23f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136332723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.136332723
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3402046853
Short name T1047
Test name
Test status
Simulation time 41687014 ps
CPU time 1.03 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 206960 kb
Host smart-27f1119d-635f-476c-acd3-653c991e589c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402046853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3402046853
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1124238882
Short name T1009
Test name
Test status
Simulation time 283737360 ps
CPU time 2.77 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:10 PM PDT 24
Peak memory 215252 kb
Host smart-c2f4486e-8396-4d2d-972e-19760d1853db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124238882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1124238882
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2076251967
Short name T1072
Test name
Test status
Simulation time 614053021 ps
CPU time 1.73 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 206992 kb
Host smart-b0aba99e-60b6-420b-9c76-a0e93b4254a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076251967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2076251967
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.985092514
Short name T1024
Test name
Test status
Simulation time 190538564 ps
CPU time 1.36 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 215364 kb
Host smart-a68c2762-8116-4ca1-90c4-ac44602dfcc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985092514 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.985092514
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2510625968
Short name T1045
Test name
Test status
Simulation time 49076238 ps
CPU time 0.9 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 206928 kb
Host smart-0a83ec8e-e8e5-4207-8d2f-f4734222aa9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510625968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2510625968
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3588604879
Short name T1112
Test name
Test status
Simulation time 45203207 ps
CPU time 0.81 seconds
Started Jul 01 04:35:05 PM PDT 24
Finished Jul 01 04:35:14 PM PDT 24
Peak memory 206672 kb
Host smart-e9f032e3-1505-4537-903d-31e777c08cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588604879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3588604879
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2306963153
Short name T1096
Test name
Test status
Simulation time 75110070 ps
CPU time 1.15 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 206976 kb
Host smart-118d54ac-5c62-4616-9b1e-9bb30f2e2506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306963153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2306963153
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3762830249
Short name T1114
Test name
Test status
Simulation time 101400244 ps
CPU time 1.99 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 215440 kb
Host smart-5990a397-a1a5-4b16-bc1c-d75fe0b78416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762830249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3762830249
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2200900153
Short name T1051
Test name
Test status
Simulation time 311348436 ps
CPU time 2.11 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:10 PM PDT 24
Peak memory 206936 kb
Host smart-09739ef8-1b56-4ba0-9007-258476b90c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200900153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2200900153
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1376922446
Short name T1053
Test name
Test status
Simulation time 372155367 ps
CPU time 1.56 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 215188 kb
Host smart-fb3a3a88-791b-4c3f-be38-f3e0763be483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376922446 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1376922446
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2220629467
Short name T1046
Test name
Test status
Simulation time 14606891 ps
CPU time 0.92 seconds
Started Jul 01 04:35:01 PM PDT 24
Finished Jul 01 04:35:10 PM PDT 24
Peak memory 206940 kb
Host smart-ba2948a4-6463-4097-b84a-ded0ad8e9adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220629467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2220629467
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1258458495
Short name T1004
Test name
Test status
Simulation time 13143086 ps
CPU time 0.88 seconds
Started Jul 01 04:35:06 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 206848 kb
Host smart-2bbf87ea-059e-473e-ae2b-cbeb64af43dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258458495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1258458495
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.821664082
Short name T1099
Test name
Test status
Simulation time 40478315 ps
CPU time 1.14 seconds
Started Jul 01 04:35:05 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 206828 kb
Host smart-2f248b17-3d33-4e57-82bf-6735b875a333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821664082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.821664082
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2990144589
Short name T1042
Test name
Test status
Simulation time 209168968 ps
CPU time 2.19 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 215192 kb
Host smart-75d40cf1-35d9-4af6-aeea-786692d19ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990144589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2990144589
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2886943287
Short name T294
Test name
Test status
Simulation time 193457251 ps
CPU time 2.5 seconds
Started Jul 01 04:35:06 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 206904 kb
Host smart-c43a5657-8002-4f0e-adf2-76badf753195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886943287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2886943287
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3554185176
Short name T1021
Test name
Test status
Simulation time 25617437 ps
CPU time 1.65 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:08 PM PDT 24
Peak memory 215280 kb
Host smart-a47e6081-b273-4a73-94ed-b8b80a966c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554185176 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3554185176
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3966898105
Short name T276
Test name
Test status
Simulation time 104535341 ps
CPU time 0.88 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206752 kb
Host smart-ccf924fe-7ec8-4d3f-82f2-45306aef8785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966898105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3966898105
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.479103116
Short name T1031
Test name
Test status
Simulation time 22783906 ps
CPU time 1.06 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 207064 kb
Host smart-83765768-a53e-422d-95d0-ffed6b5a087a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479103116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.479103116
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2335387497
Short name T1039
Test name
Test status
Simulation time 27171018 ps
CPU time 1.24 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 206920 kb
Host smart-5d9d8835-6592-44b9-b053-02cd65301dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335387497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2335387497
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2791842795
Short name T1067
Test name
Test status
Simulation time 76751131 ps
CPU time 2.63 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 213516 kb
Host smart-201e1ea2-1dfa-489f-a31c-5102d745b456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791842795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2791842795
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1535111842
Short name T1081
Test name
Test status
Simulation time 78181894 ps
CPU time 1.46 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 207016 kb
Host smart-005b870b-d171-4ec9-987c-e82f37cf9359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535111842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1535111842
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3884270908
Short name T1010
Test name
Test status
Simulation time 32172603 ps
CPU time 1.18 seconds
Started Jul 01 04:35:02 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 215124 kb
Host smart-40acfa94-3225-4d8b-8ea1-bae8b9956568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884270908 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3884270908
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3150990342
Short name T279
Test name
Test status
Simulation time 17122884 ps
CPU time 0.93 seconds
Started Jul 01 04:35:06 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 206908 kb
Host smart-484cbc6e-abb8-4f43-86dc-4d56895e7ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150990342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3150990342
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2240063117
Short name T1008
Test name
Test status
Simulation time 16779815 ps
CPU time 0.82 seconds
Started Jul 01 04:35:04 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 206716 kb
Host smart-d948f25b-9dd0-4c37-a82c-e3e99b89bbea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240063117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2240063117
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2587558864
Short name T280
Test name
Test status
Simulation time 58318792 ps
CPU time 1.11 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 206988 kb
Host smart-a29b4825-24e8-4c8c-9895-b2640696a948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587558864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2587558864
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1014138218
Short name T1097
Test name
Test status
Simulation time 99935223 ps
CPU time 2.42 seconds
Started Jul 01 04:35:01 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 215196 kb
Host smart-c88c5525-d947-4924-9f31-99c5a96c9a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014138218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1014138218
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2696964227
Short name T1127
Test name
Test status
Simulation time 109437098 ps
CPU time 2.45 seconds
Started Jul 01 04:35:06 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 215144 kb
Host smart-6a8ad15e-45c2-408b-9814-367ef3d43d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696964227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2696964227
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1065693227
Short name T1025
Test name
Test status
Simulation time 71598298 ps
CPU time 1.1 seconds
Started Jul 01 04:35:07 PM PDT 24
Finished Jul 01 04:35:16 PM PDT 24
Peak memory 206992 kb
Host smart-d08a20c8-0267-4ac6-858f-13929c28f901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065693227 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1065693227
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2338703733
Short name T274
Test name
Test status
Simulation time 67415136 ps
CPU time 0.87 seconds
Started Jul 01 04:35:11 PM PDT 24
Finished Jul 01 04:35:21 PM PDT 24
Peak memory 206896 kb
Host smart-260faf15-783b-4b76-ac97-0e25a7e9da53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338703733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2338703733
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3964284533
Short name T1116
Test name
Test status
Simulation time 12401224 ps
CPU time 0.91 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:19 PM PDT 24
Peak memory 206964 kb
Host smart-3e9d6c83-4999-4166-bb8c-36d995dd93de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964284533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3964284533
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2650817334
Short name T1123
Test name
Test status
Simulation time 46650129 ps
CPU time 1.15 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:19 PM PDT 24
Peak memory 206916 kb
Host smart-235028fb-fae2-40f3-92ed-4def14005060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650817334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2650817334
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3956925639
Short name T1104
Test name
Test status
Simulation time 70312272 ps
CPU time 2.63 seconds
Started Jul 01 04:35:03 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 213524 kb
Host smart-02328bd5-724d-44ec-b80e-5ab10442c7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956925639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3956925639
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1071167638
Short name T1120
Test name
Test status
Simulation time 79119060 ps
CPU time 1.51 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 207116 kb
Host smart-a7e57586-dc1d-456d-beb4-56c03607cf7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071167638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1071167638
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1254345111
Short name T1005
Test name
Test status
Simulation time 20089823 ps
CPU time 1.12 seconds
Started Jul 01 04:35:11 PM PDT 24
Finished Jul 01 04:35:26 PM PDT 24
Peak memory 216632 kb
Host smart-f48f9591-09f7-4218-b7ef-83e03a66adb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254345111 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1254345111
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2135418316
Short name T1119
Test name
Test status
Simulation time 49279930 ps
CPU time 0.86 seconds
Started Jul 01 04:35:10 PM PDT 24
Finished Jul 01 04:35:19 PM PDT 24
Peak memory 206776 kb
Host smart-f04626a0-a0d5-4335-9529-2937f30bdafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135418316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2135418316
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.508600709
Short name T1055
Test name
Test status
Simulation time 23834002 ps
CPU time 0.84 seconds
Started Jul 01 04:35:10 PM PDT 24
Finished Jul 01 04:35:20 PM PDT 24
Peak memory 206836 kb
Host smart-94620a52-882e-4fb6-858f-81c96fcaf5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508600709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.508600709
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2734699774
Short name T281
Test name
Test status
Simulation time 26150233 ps
CPU time 1 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206924 kb
Host smart-8d2602cf-b5af-497f-92ef-2a6f63dddfac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734699774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2734699774
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2077083437
Short name T1107
Test name
Test status
Simulation time 250501992 ps
CPU time 4.46 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:21 PM PDT 24
Peak memory 219480 kb
Host smart-4d01141b-9742-49a6-8a20-d32a12a4b835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077083437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2077083437
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3647421464
Short name T1113
Test name
Test status
Simulation time 107784080 ps
CPU time 2.75 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:20 PM PDT 24
Peak memory 206888 kb
Host smart-dbdb2c39-e063-4df1-ae9a-22ad07e5cd6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647421464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3647421464
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1141734946
Short name T1040
Test name
Test status
Simulation time 39822412 ps
CPU time 1.62 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 206884 kb
Host smart-c8dd8865-f4d5-498f-850d-ea790e971e9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141734946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1141734946
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1929992001
Short name T268
Test name
Test status
Simulation time 58715605 ps
CPU time 3.23 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 206956 kb
Host smart-26e744cf-1dea-4423-9316-34afe5ea27e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929992001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1929992001
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1561262747
Short name T261
Test name
Test status
Simulation time 27622047 ps
CPU time 0.91 seconds
Started Jul 01 04:34:42 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 206828 kb
Host smart-e6b302a7-2aeb-4929-adb5-bf78f2a43669
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561262747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1561262747
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.915293963
Short name T1090
Test name
Test status
Simulation time 138544843 ps
CPU time 1.59 seconds
Started Jul 01 04:34:52 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 215096 kb
Host smart-72b38b32-9867-4fac-b3ad-df676873a1fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915293963 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.915293963
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3433978997
Short name T272
Test name
Test status
Simulation time 23369916 ps
CPU time 0.9 seconds
Started Jul 01 04:34:52 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 206836 kb
Host smart-897d6f53-6a89-439b-9802-1eae56246967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433978997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3433978997
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3922948403
Short name T1066
Test name
Test status
Simulation time 14976590 ps
CPU time 0.93 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 206776 kb
Host smart-5f1a691d-38fc-4f3b-928b-b5bcf17861da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922948403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3922948403
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2035120478
Short name T278
Test name
Test status
Simulation time 106112445 ps
CPU time 1.12 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 206780 kb
Host smart-e76f3b69-fd66-45fb-ae83-4e2ab6395063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035120478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2035120478
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.316530485
Short name T1006
Test name
Test status
Simulation time 53949619 ps
CPU time 1.77 seconds
Started Jul 01 04:34:51 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 215088 kb
Host smart-2ffe9915-f19d-4654-9c32-6f7968f8adb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316530485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.316530485
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1592586261
Short name T296
Test name
Test status
Simulation time 92227713 ps
CPU time 1.66 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 207092 kb
Host smart-3f034f36-35bf-4f44-b7bb-6b22baf90f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592586261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1592586261
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.813056677
Short name T997
Test name
Test status
Simulation time 18577714 ps
CPU time 0.81 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206692 kb
Host smart-d51c95ef-c807-46b3-a96f-9a2fb328fd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813056677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.813056677
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.386985960
Short name T1038
Test name
Test status
Simulation time 42953319 ps
CPU time 0.82 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206864 kb
Host smart-5800f127-603d-43aa-95ea-417fae6d7154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386985960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.386985960
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1083052062
Short name T1118
Test name
Test status
Simulation time 29102310 ps
CPU time 0.78 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206692 kb
Host smart-bd854a3b-3ff0-4abf-ad6a-26404906183c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083052062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1083052062
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1557435679
Short name T1013
Test name
Test status
Simulation time 36262258 ps
CPU time 0.81 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206696 kb
Host smart-35393ab3-9999-4146-b609-ab3bb5de064e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557435679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1557435679
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2884574623
Short name T1069
Test name
Test status
Simulation time 40991183 ps
CPU time 0.86 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 206824 kb
Host smart-41f4a2f1-9971-4020-908f-55e6bd0050eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884574623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2884574623
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2087367756
Short name T1108
Test name
Test status
Simulation time 15151468 ps
CPU time 0.91 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206744 kb
Host smart-9789aead-43a2-407a-b9b0-df77e13f7914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087367756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2087367756
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3795663005
Short name T1079
Test name
Test status
Simulation time 17471938 ps
CPU time 0.94 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 206868 kb
Host smart-30f75215-56c1-4a2c-8eff-f0d39409fa16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795663005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3795663005
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3859576116
Short name T1068
Test name
Test status
Simulation time 70731213 ps
CPU time 0.8 seconds
Started Jul 01 04:35:07 PM PDT 24
Finished Jul 01 04:35:16 PM PDT 24
Peak memory 206688 kb
Host smart-7e197040-01f7-4aee-acb0-9bb288aebf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859576116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3859576116
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.570193604
Short name T1074
Test name
Test status
Simulation time 17186284 ps
CPU time 0.83 seconds
Started Jul 01 04:35:10 PM PDT 24
Finished Jul 01 04:35:19 PM PDT 24
Peak memory 206888 kb
Host smart-a30e92ca-3bc9-41ef-8312-0d56e26dc277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570193604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.570193604
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4292977853
Short name T1028
Test name
Test status
Simulation time 12451221 ps
CPU time 0.86 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206728 kb
Host smart-4e461012-c81d-4376-b8aa-5accde5bbca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292977853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4292977853
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2392003942
Short name T1048
Test name
Test status
Simulation time 22309728 ps
CPU time 1.1 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206836 kb
Host smart-4e594ed0-5c68-41f9-80bd-1ef0eaf63c65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392003942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2392003942
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1216922565
Short name T1030
Test name
Test status
Simulation time 114898413 ps
CPU time 3.1 seconds
Started Jul 01 04:34:50 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 206864 kb
Host smart-19ca2eb4-fa93-4339-9cb5-6cf11e05d899
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216922565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1216922565
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1677191406
Short name T269
Test name
Test status
Simulation time 17473563 ps
CPU time 0.95 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 206916 kb
Host smart-d5f77013-c96b-45b0-a187-2b06f531366c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677191406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1677191406
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1342393403
Short name T1084
Test name
Test status
Simulation time 113061621 ps
CPU time 1.82 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:01 PM PDT 24
Peak memory 215096 kb
Host smart-bfee4184-a2a7-4db2-8b48-0fdbdcb4374d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342393403 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1342393403
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.481961396
Short name T1032
Test name
Test status
Simulation time 21140911 ps
CPU time 0.82 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 206924 kb
Host smart-5917a42d-26a3-43d9-88e0-3fb38203f208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481961396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.481961396
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2357435444
Short name T1002
Test name
Test status
Simulation time 12430676 ps
CPU time 0.9 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 206944 kb
Host smart-bef4b5af-d299-450e-8fda-4ee9e16ed577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357435444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2357435444
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3509985918
Short name T1088
Test name
Test status
Simulation time 72420716 ps
CPU time 1.35 seconds
Started Jul 01 04:34:50 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206844 kb
Host smart-449f0ebb-bce0-4789-bc1b-7e224fa6b41e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509985918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3509985918
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1112759342
Short name T1023
Test name
Test status
Simulation time 443607807 ps
CPU time 2.76 seconds
Started Jul 01 04:34:51 PM PDT 24
Finished Jul 01 04:35:03 PM PDT 24
Peak memory 215148 kb
Host smart-3d97b2d2-e3be-4974-8a7d-a58b958829f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112759342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1112759342
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3366164532
Short name T1122
Test name
Test status
Simulation time 160563533 ps
CPU time 2.39 seconds
Started Jul 01 04:34:47 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 215140 kb
Host smart-91bc9772-75cd-45e4-b0b8-1addccf8f3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366164532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3366164532
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.50026025
Short name T1091
Test name
Test status
Simulation time 36646462 ps
CPU time 0.85 seconds
Started Jul 01 04:35:07 PM PDT 24
Finished Jul 01 04:35:16 PM PDT 24
Peak memory 206756 kb
Host smart-d6355138-3158-47d8-ae6d-582fef860f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50026025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.50026025
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1163874234
Short name T1019
Test name
Test status
Simulation time 18348883 ps
CPU time 0.83 seconds
Started Jul 01 04:35:07 PM PDT 24
Finished Jul 01 04:35:16 PM PDT 24
Peak memory 206784 kb
Host smart-0fb34f10-e6a3-442f-93fd-c0dbf4d56527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163874234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1163874234
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1359078340
Short name T998
Test name
Test status
Simulation time 84866347 ps
CPU time 0.84 seconds
Started Jul 01 04:35:19 PM PDT 24
Finished Jul 01 04:35:29 PM PDT 24
Peak memory 206592 kb
Host smart-39b8786f-667f-44b6-b437-1f2448a37306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359078340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1359078340
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4059590563
Short name T1117
Test name
Test status
Simulation time 27824832 ps
CPU time 0.93 seconds
Started Jul 01 04:35:11 PM PDT 24
Finished Jul 01 04:35:21 PM PDT 24
Peak memory 206876 kb
Host smart-554e9a2c-d4d4-4862-85f3-ddef5d0e4a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059590563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4059590563
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.197503534
Short name T1050
Test name
Test status
Simulation time 14551639 ps
CPU time 0.9 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 206784 kb
Host smart-2d09231e-9f7e-4052-a54a-88a5aacd2653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197503534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.197503534
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1058647160
Short name T1003
Test name
Test status
Simulation time 120258832 ps
CPU time 0.84 seconds
Started Jul 01 04:35:06 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 206864 kb
Host smart-de8249e9-b6ca-4ad8-9905-3c17660c4155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058647160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1058647160
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2479304342
Short name T1027
Test name
Test status
Simulation time 48467666 ps
CPU time 0.95 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206860 kb
Host smart-1dd6a354-1bd5-46b0-80e7-ff43c1ae607d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479304342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2479304342
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.398265830
Short name T1022
Test name
Test status
Simulation time 19612965 ps
CPU time 0.84 seconds
Started Jul 01 04:35:14 PM PDT 24
Finished Jul 01 04:35:24 PM PDT 24
Peak memory 206768 kb
Host smart-e0cd98c0-8b63-41d6-ac35-ed4196f4005d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398265830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.398265830
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2186769116
Short name T1077
Test name
Test status
Simulation time 28041375 ps
CPU time 0.9 seconds
Started Jul 01 04:35:11 PM PDT 24
Finished Jul 01 04:35:21 PM PDT 24
Peak memory 206880 kb
Host smart-ec62f45a-f0a3-4622-90b9-149255295c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186769116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2186769116
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2770008324
Short name T1070
Test name
Test status
Simulation time 159697867 ps
CPU time 0.86 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:17 PM PDT 24
Peak memory 206568 kb
Host smart-b22e9596-6765-47ac-9cb6-93f0b2fdb4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770008324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2770008324
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.314264727
Short name T1093
Test name
Test status
Simulation time 97887527 ps
CPU time 1.05 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 207000 kb
Host smart-3119e500-e9c5-4006-bf3b-561d895791fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314264727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.314264727
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2026222810
Short name T1110
Test name
Test status
Simulation time 1058122461 ps
CPU time 7.19 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 207028 kb
Host smart-1c6c7e4a-3652-47ce-ab27-ec068d535ff5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026222810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2026222810
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3602680326
Short name T260
Test name
Test status
Simulation time 41464536 ps
CPU time 0.83 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 206740 kb
Host smart-27c8aadc-7747-4808-a675-7ea3453a00cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602680326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3602680326
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1612748257
Short name T1130
Test name
Test status
Simulation time 47506882 ps
CPU time 1.31 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 215184 kb
Host smart-bcb6536d-6e19-4334-9c2f-f2dfb32afd1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612748257 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1612748257
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1449557130
Short name T262
Test name
Test status
Simulation time 32684464 ps
CPU time 0.83 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206832 kb
Host smart-957d0426-bc1f-427b-b712-2e6dc7f36ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449557130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1449557130
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3855722653
Short name T1063
Test name
Test status
Simulation time 26052668 ps
CPU time 0.85 seconds
Started Jul 01 04:34:47 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 206776 kb
Host smart-48b28b2a-bd42-46d9-8c41-569cf2173596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855722653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3855722653
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3529976197
Short name T273
Test name
Test status
Simulation time 14847376 ps
CPU time 0.97 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206856 kb
Host smart-4ecbab3d-2627-4b8c-879e-15e94cc0a7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529976197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3529976197
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2948464969
Short name T1121
Test name
Test status
Simulation time 117024645 ps
CPU time 4.1 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 215184 kb
Host smart-1701de5a-62d3-4f7f-80b6-d0017b9cbd3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948464969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2948464969
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3104387022
Short name T1059
Test name
Test status
Simulation time 165647278 ps
CPU time 3.36 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 215028 kb
Host smart-f822c7c3-56f5-42fe-973b-42878e659d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104387022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3104387022
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1447874140
Short name T1128
Test name
Test status
Simulation time 15479044 ps
CPU time 0.94 seconds
Started Jul 01 04:35:08 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206724 kb
Host smart-86fd77d9-94b7-4225-b0a5-1a42ca9a893b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447874140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1447874140
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2364062415
Short name T996
Test name
Test status
Simulation time 24122332 ps
CPU time 0.91 seconds
Started Jul 01 04:35:09 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 206960 kb
Host smart-b7ad2c33-0a89-481b-bbbd-b61150802477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364062415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2364062415
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3099120929
Short name T1007
Test name
Test status
Simulation time 20968568 ps
CPU time 0.81 seconds
Started Jul 01 04:35:19 PM PDT 24
Finished Jul 01 04:35:29 PM PDT 24
Peak memory 206556 kb
Host smart-b85778a5-6445-4f87-bd57-6b2936b83e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099120929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3099120929
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2096093854
Short name T1078
Test name
Test status
Simulation time 13305710 ps
CPU time 0.95 seconds
Started Jul 01 04:35:10 PM PDT 24
Finished Jul 01 04:35:19 PM PDT 24
Peak memory 206832 kb
Host smart-c3e45339-280b-4113-add5-474908dd154f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096093854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2096093854
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1301950302
Short name T1020
Test name
Test status
Simulation time 24084205 ps
CPU time 0.83 seconds
Started Jul 01 04:35:12 PM PDT 24
Finished Jul 01 04:35:23 PM PDT 24
Peak memory 206860 kb
Host smart-04135522-e9fc-4388-a61d-d32934200789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301950302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1301950302
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.120008559
Short name T1126
Test name
Test status
Simulation time 14346704 ps
CPU time 0.9 seconds
Started Jul 01 04:35:14 PM PDT 24
Finished Jul 01 04:35:24 PM PDT 24
Peak memory 206876 kb
Host smart-c1c71d73-1d6c-4c15-b986-74bece3de59a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120008559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.120008559
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4159325120
Short name T1043
Test name
Test status
Simulation time 15485029 ps
CPU time 0.93 seconds
Started Jul 01 04:35:13 PM PDT 24
Finished Jul 01 04:35:23 PM PDT 24
Peak memory 206888 kb
Host smart-90e2e381-c48b-435b-a15f-8b794a7acc49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159325120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4159325120
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.158432050
Short name T1033
Test name
Test status
Simulation time 21735762 ps
CPU time 0.84 seconds
Started Jul 01 04:35:25 PM PDT 24
Finished Jul 01 04:35:35 PM PDT 24
Peak memory 206868 kb
Host smart-2cc8d4be-5b5a-4e54-92b6-9bae12b36a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158432050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.158432050
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.529922706
Short name T1001
Test name
Test status
Simulation time 60619932 ps
CPU time 0.9 seconds
Started Jul 01 04:35:14 PM PDT 24
Finished Jul 01 04:35:24 PM PDT 24
Peak memory 207076 kb
Host smart-822052fd-4197-4d50-b02f-241a88e7a44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529922706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.529922706
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3754774466
Short name T1029
Test name
Test status
Simulation time 24417322 ps
CPU time 0.86 seconds
Started Jul 01 04:35:14 PM PDT 24
Finished Jul 01 04:35:24 PM PDT 24
Peak memory 206900 kb
Host smart-3036c497-79ab-4c4e-a0a4-439b9f03fb31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754774466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3754774466
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.333754020
Short name T1073
Test name
Test status
Simulation time 66323041 ps
CPU time 1.39 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 215124 kb
Host smart-32072527-31b0-4939-9e4f-0820479ebc29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333754020 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.333754020
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2591623843
Short name T1035
Test name
Test status
Simulation time 22442941 ps
CPU time 0.94 seconds
Started Jul 01 04:34:54 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 206884 kb
Host smart-0ea7cd3c-86d9-4bf0-b3b6-fa0834fea639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591623843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2591623843
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3752926462
Short name T1054
Test name
Test status
Simulation time 48098401 ps
CPU time 0.82 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 206812 kb
Host smart-d5814762-551b-4963-9574-c1fef8cfef8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752926462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3752926462
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1243743802
Short name T1037
Test name
Test status
Simulation time 114310064 ps
CPU time 1.32 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206928 kb
Host smart-ac01e610-bcf8-4ff8-afa6-0b5a716c3bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243743802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1243743802
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3861748532
Short name T1017
Test name
Test status
Simulation time 50130489 ps
CPU time 2.21 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:01 PM PDT 24
Peak memory 215272 kb
Host smart-0a07a2f6-9008-4b6c-8600-59a6cd5c16e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861748532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3861748532
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2027310174
Short name T1111
Test name
Test status
Simulation time 298301976 ps
CPU time 2.3 seconds
Started Jul 01 04:34:50 PM PDT 24
Finished Jul 01 04:35:01 PM PDT 24
Peak memory 215124 kb
Host smart-6a3b2a55-d778-4034-9d55-b847797c204f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027310174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2027310174
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.246391705
Short name T1100
Test name
Test status
Simulation time 31478205 ps
CPU time 1.76 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:01 PM PDT 24
Peak memory 215188 kb
Host smart-63ac0572-4e65-4825-9c8e-f58bd622fd35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246391705 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.246391705
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2309915828
Short name T267
Test name
Test status
Simulation time 13094600 ps
CPU time 0.87 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 206920 kb
Host smart-05f3c4e7-46fd-46a4-bc73-f313d72e1ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309915828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2309915828
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1516995720
Short name T1012
Test name
Test status
Simulation time 13161354 ps
CPU time 0.93 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206696 kb
Host smart-9d3d3ab0-aae6-4f98-b5ee-76d7a2683e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516995720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1516995720
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2358429548
Short name T1080
Test name
Test status
Simulation time 18583255 ps
CPU time 1.24 seconds
Started Jul 01 04:34:49 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 207060 kb
Host smart-69ac1649-c10b-4e70-94a2-99866d6aab49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358429548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2358429548
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4223573389
Short name T1026
Test name
Test status
Simulation time 332449133 ps
CPU time 3.09 seconds
Started Jul 01 04:34:51 PM PDT 24
Finished Jul 01 04:35:03 PM PDT 24
Peak memory 219216 kb
Host smart-d42c2d0b-cb4b-46ba-9bfa-438ce237ef50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223573389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4223573389
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.660914548
Short name T1061
Test name
Test status
Simulation time 174118753 ps
CPU time 2.28 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206856 kb
Host smart-6ec60f44-d5bc-44e4-9420-fbbd945591da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660914548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.660914548
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2815247141
Short name T999
Test name
Test status
Simulation time 92610657 ps
CPU time 1.18 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 215200 kb
Host smart-c07acd1d-9255-4da3-9277-86371c2b725f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815247141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2815247141
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1840109891
Short name T259
Test name
Test status
Simulation time 149874590 ps
CPU time 0.93 seconds
Started Jul 01 04:34:53 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 206920 kb
Host smart-6631f24a-0fda-4387-8f78-0c9e6ae78fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840109891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1840109891
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4153635207
Short name T1018
Test name
Test status
Simulation time 17382534 ps
CPU time 0.92 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 207076 kb
Host smart-a90832ab-d9cc-4c74-8aa5-799252921856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153635207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4153635207
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.849089179
Short name T1098
Test name
Test status
Simulation time 72406507 ps
CPU time 1.08 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 206960 kb
Host smart-020a95b8-05cc-4386-b664-9f4605fb25ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849089179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.849089179
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.570719067
Short name T1049
Test name
Test status
Simulation time 85521520 ps
CPU time 3.21 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 214964 kb
Host smart-77cc3a20-d39e-430f-b062-42891d27b021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570719067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.570719067
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2314958133
Short name T286
Test name
Test status
Simulation time 798216927 ps
CPU time 2.57 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 206828 kb
Host smart-a79051b5-4adc-49aa-ad93-ec865c0ea30c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314958133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2314958133
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3179588650
Short name T1056
Test name
Test status
Simulation time 81897044 ps
CPU time 1.19 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:09 PM PDT 24
Peak memory 215244 kb
Host smart-d79dcb94-ffe6-40fa-810c-8ae5b308e158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179588650 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3179588650
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1434015636
Short name T265
Test name
Test status
Simulation time 11262129 ps
CPU time 0.92 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 207148 kb
Host smart-a2f61ac3-964e-4144-8500-a24869f49dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434015636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1434015636
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3210023965
Short name T1085
Test name
Test status
Simulation time 44179317 ps
CPU time 0.95 seconds
Started Jul 01 04:34:58 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 207076 kb
Host smart-b028bcc8-3622-4b97-8017-4a6deb5f9ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210023965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3210023965
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.21624140
Short name T1060
Test name
Test status
Simulation time 19220757 ps
CPU time 1.24 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 206916 kb
Host smart-569f8720-310c-4085-b4d8-bf7154315383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outs
tanding.21624140
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.39161723
Short name T1086
Test name
Test status
Simulation time 320954197 ps
CPU time 3.68 seconds
Started Jul 01 04:34:55 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 215196 kb
Host smart-30f0d3ec-f72a-48fe-beda-5e24680cea28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.39161723
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3635223732
Short name T1052
Test name
Test status
Simulation time 137690679 ps
CPU time 1.54 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:10 PM PDT 24
Peak memory 206976 kb
Host smart-a3d6d98f-f419-4f37-b2a5-2d1d04edfe69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635223732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3635223732
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1415013497
Short name T1065
Test name
Test status
Simulation time 20884057 ps
CPU time 1.21 seconds
Started Jul 01 04:34:56 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 217008 kb
Host smart-79c7c440-f8c5-4922-89b0-e61aec7d58f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415013497 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1415013497
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2526372735
Short name T1109
Test name
Test status
Simulation time 53044977 ps
CPU time 0.87 seconds
Started Jul 01 04:34:57 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 206864 kb
Host smart-1ef443db-dee3-4a98-85b7-4b67f84a247c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526372735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2526372735
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2544258301
Short name T1103
Test name
Test status
Simulation time 28773601 ps
CPU time 0.9 seconds
Started Jul 01 04:35:00 PM PDT 24
Finished Jul 01 04:35:09 PM PDT 24
Peak memory 206776 kb
Host smart-ca311adf-1de9-4a18-9d78-041e132013d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544258301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2544258301
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3515797977
Short name T1071
Test name
Test status
Simulation time 35309845 ps
CPU time 1.11 seconds
Started Jul 01 04:34:55 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 206888 kb
Host smart-5ad96039-6637-4efe-988c-63699e56d3fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515797977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3515797977
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.76011346
Short name T1129
Test name
Test status
Simulation time 47601500 ps
CPU time 1.77 seconds
Started Jul 01 04:35:04 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 215204 kb
Host smart-78fc4a4d-6307-4fba-9fd3-aa70099cd511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76011346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.76011346
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3803484680
Short name T1076
Test name
Test status
Simulation time 131263436 ps
CPU time 2.13 seconds
Started Jul 01 04:34:59 PM PDT 24
Finished Jul 01 04:35:09 PM PDT 24
Peak memory 215136 kb
Host smart-e5832330-2b0f-4061-ac6a-020c45c4c946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803484680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3803484680
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4272566907
Short name T759
Test name
Test status
Simulation time 60294505 ps
CPU time 1.1 seconds
Started Jul 01 05:35:02 PM PDT 24
Finished Jul 01 05:35:05 PM PDT 24
Peak memory 219104 kb
Host smart-d33afe14-e92d-4004-a6cc-59cb1ea6d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272566907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4272566907
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.551020960
Short name T432
Test name
Test status
Simulation time 25969422 ps
CPU time 0.86 seconds
Started Jul 01 05:35:11 PM PDT 24
Finished Jul 01 05:35:12 PM PDT 24
Peak memory 215292 kb
Host smart-a2a97b27-3c8a-4ff6-8364-f205bdb33084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551020960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.551020960
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2628899971
Short name T966
Test name
Test status
Simulation time 11404835 ps
CPU time 0.87 seconds
Started Jul 01 05:35:03 PM PDT 24
Finished Jul 01 05:35:05 PM PDT 24
Peak memory 216368 kb
Host smart-1e5f8317-9bba-4512-b90f-d0410deb7f34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628899971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2628899971
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1787235745
Short name T801
Test name
Test status
Simulation time 26635583 ps
CPU time 1.07 seconds
Started Jul 01 05:35:04 PM PDT 24
Finished Jul 01 05:35:06 PM PDT 24
Peak memory 218680 kb
Host smart-6c74fd41-f0a2-447f-8cae-08771bbc63b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787235745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1787235745
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2393559821
Short name T100
Test name
Test status
Simulation time 25807816 ps
CPU time 1.01 seconds
Started Jul 01 05:35:02 PM PDT 24
Finished Jul 01 05:35:05 PM PDT 24
Peak memory 220232 kb
Host smart-121aec92-786b-4bb0-b062-a9b618c202d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393559821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2393559821
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4018322573
Short name T790
Test name
Test status
Simulation time 43925073 ps
CPU time 1.55 seconds
Started Jul 01 05:35:00 PM PDT 24
Finished Jul 01 05:35:03 PM PDT 24
Peak memory 218832 kb
Host smart-2f9f8894-4775-4a2a-b923-1f015276acd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018322573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4018322573
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3085654080
Short name T38
Test name
Test status
Simulation time 80884951 ps
CPU time 0.84 seconds
Started Jul 01 05:34:59 PM PDT 24
Finished Jul 01 05:35:01 PM PDT 24
Peak memory 215772 kb
Host smart-e63cbfc9-fba6-4b96-b5a8-2544f7153faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085654080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3085654080
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3797907684
Short name T732
Test name
Test status
Simulation time 42627454 ps
CPU time 0.86 seconds
Started Jul 01 05:34:57 PM PDT 24
Finished Jul 01 05:34:59 PM PDT 24
Peak memory 207520 kb
Host smart-4eb323c6-c228-4f03-9042-eb998aef0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797907684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3797907684
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3653772756
Short name T19
Test name
Test status
Simulation time 1951949106 ps
CPU time 4.17 seconds
Started Jul 01 05:35:08 PM PDT 24
Finished Jul 01 05:35:13 PM PDT 24
Peak memory 242464 kb
Host smart-33902b79-5882-42e4-aba4-6e2e42364bbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653772756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3653772756
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1389839669
Short name T543
Test name
Test status
Simulation time 28577299 ps
CPU time 0.9 seconds
Started Jul 01 05:35:00 PM PDT 24
Finished Jul 01 05:35:02 PM PDT 24
Peak memory 215552 kb
Host smart-70ff721f-c484-4ba2-a5c0-a07f00c6d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389839669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1389839669
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4107113535
Short name T626
Test name
Test status
Simulation time 106359019 ps
CPU time 1.75 seconds
Started Jul 01 05:34:58 PM PDT 24
Finished Jul 01 05:35:00 PM PDT 24
Peak memory 215856 kb
Host smart-1883f919-04f4-4daf-bf7b-a389dc71adef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107113535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4107113535
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1478492342
Short name T130
Test name
Test status
Simulation time 39149082 ps
CPU time 1.16 seconds
Started Jul 01 05:35:11 PM PDT 24
Finished Jul 01 05:35:13 PM PDT 24
Peak memory 220792 kb
Host smart-0c315949-2c8f-4f25-b738-81ef0f6d1b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478492342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1478492342
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3558267492
Short name T954
Test name
Test status
Simulation time 57507555 ps
CPU time 0.83 seconds
Started Jul 01 05:35:17 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 215204 kb
Host smart-21103266-ea05-489d-81e7-d7c3a031888a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558267492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3558267492
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.446778513
Short name T723
Test name
Test status
Simulation time 20327929 ps
CPU time 1.04 seconds
Started Jul 01 05:35:17 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 218832 kb
Host smart-9453f931-8368-4007-8823-9d750020e91b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446778513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.446778513
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3825374223
Short name T210
Test name
Test status
Simulation time 75271055 ps
CPU time 1.07 seconds
Started Jul 01 05:35:17 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 220136 kb
Host smart-fdc396b4-00fe-43d4-9f9e-e7eede296630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825374223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3825374223
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.2477501913
Short name T238
Test name
Test status
Simulation time 29274150 ps
CPU time 0.94 seconds
Started Jul 01 05:35:09 PM PDT 24
Finished Jul 01 05:35:11 PM PDT 24
Peak memory 215736 kb
Host smart-e4bbe105-33b4-4221-a40e-c28d2de83ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477501913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2477501913
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3670260588
Short name T63
Test name
Test status
Simulation time 455020618 ps
CPU time 6.6 seconds
Started Jul 01 05:35:16 PM PDT 24
Finished Jul 01 05:35:23 PM PDT 24
Peak memory 238060 kb
Host smart-488b116a-b2fa-4633-b479-b5bbac358649
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670260588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3670260588
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.827093672
Short name T970
Test name
Test status
Simulation time 17744416 ps
CPU time 1.01 seconds
Started Jul 01 05:35:10 PM PDT 24
Finished Jul 01 05:35:12 PM PDT 24
Peak memory 215636 kb
Host smart-b5f15819-7604-4823-b58b-369a080cee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827093672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.827093672
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.748244383
Short name T412
Test name
Test status
Simulation time 133622836 ps
CPU time 1.86 seconds
Started Jul 01 05:35:09 PM PDT 24
Finished Jul 01 05:35:12 PM PDT 24
Peak memory 218668 kb
Host smart-17027799-7b7f-47d1-99d3-17668e13e907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748244383 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.748244383
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.582398475
Short name T720
Test name
Test status
Simulation time 105192832993 ps
CPU time 2523.94 seconds
Started Jul 01 05:35:10 PM PDT 24
Finished Jul 01 06:17:16 PM PDT 24
Peak memory 233608 kb
Host smart-f4789ccb-e75c-41fd-997b-667957702f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582398475 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.582398475
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2248321131
Short name T717
Test name
Test status
Simulation time 73015736 ps
CPU time 1.17 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:12 PM PDT 24
Peak memory 219624 kb
Host smart-d1bd9794-88f9-4030-9eb6-18c766b9d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248321131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2248321131
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.729806547
Short name T784
Test name
Test status
Simulation time 86574833 ps
CPU time 1.04 seconds
Started Jul 01 05:36:15 PM PDT 24
Finished Jul 01 05:36:18 PM PDT 24
Peak memory 207248 kb
Host smart-84044905-b964-4116-9db8-a81c503ce2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729806547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.729806547
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2157621705
Short name T868
Test name
Test status
Simulation time 73806385 ps
CPU time 1.3 seconds
Started Jul 01 05:36:18 PM PDT 24
Finished Jul 01 05:36:20 PM PDT 24
Peak memory 217260 kb
Host smart-14677c23-7925-47db-b594-f4c9753b6e79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157621705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2157621705
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.344079219
Short name T120
Test name
Test status
Simulation time 27413314 ps
CPU time 1.18 seconds
Started Jul 01 05:36:12 PM PDT 24
Finished Jul 01 05:36:15 PM PDT 24
Peak memory 217756 kb
Host smart-880721e4-d5ab-4ffe-b7a7-0c7371d91681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344079219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.344079219
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1477771789
Short name T340
Test name
Test status
Simulation time 61657801 ps
CPU time 1.48 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:13 PM PDT 24
Peak memory 220516 kb
Host smart-39724780-e18c-461c-874c-92afaa9bf25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477771789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1477771789
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.494446805
Short name T741
Test name
Test status
Simulation time 27635570 ps
CPU time 0.85 seconds
Started Jul 01 05:36:11 PM PDT 24
Finished Jul 01 05:36:14 PM PDT 24
Peak memory 215932 kb
Host smart-7622eb8a-e106-42d1-a39f-96fe7832995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494446805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.494446805
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2021962994
Short name T914
Test name
Test status
Simulation time 46965871 ps
CPU time 0.9 seconds
Started Jul 01 05:36:08 PM PDT 24
Finished Jul 01 05:36:10 PM PDT 24
Peak memory 215696 kb
Host smart-3a36594d-fba4-4d70-8175-a3f03c933ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021962994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2021962994
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3667358139
Short name T694
Test name
Test status
Simulation time 54020692 ps
CPU time 1.58 seconds
Started Jul 01 05:36:08 PM PDT 24
Finished Jul 01 05:36:11 PM PDT 24
Peak memory 215588 kb
Host smart-e94fd50e-a0b4-4c59-a6b0-51a7a6df47b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667358139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3667358139
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.3623227034
Short name T862
Test name
Test status
Simulation time 111244303 ps
CPU time 1.09 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:58 PM PDT 24
Peak memory 216024 kb
Host smart-626f03e4-1470-44f5-8ae2-aa5c8a7d5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623227034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3623227034
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3686707384
Short name T622
Test name
Test status
Simulation time 32913080 ps
CPU time 1.35 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 217996 kb
Host smart-d54d0878-9e89-4c5e-af2a-8c6a5d19cb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686707384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3686707384
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2613078260
Short name T941
Test name
Test status
Simulation time 40387353 ps
CPU time 1.16 seconds
Started Jul 01 05:38:54 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 219640 kb
Host smart-5be9a087-a6b6-4059-aa12-2c488d1d99eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613078260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2613078260
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.585347716
Short name T584
Test name
Test status
Simulation time 43722955 ps
CPU time 1.39 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 219116 kb
Host smart-cea832bb-6515-492b-9456-65ae66eefd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585347716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.585347716
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.540511843
Short name T911
Test name
Test status
Simulation time 75071882 ps
CPU time 1.13 seconds
Started Jul 01 05:38:52 PM PDT 24
Finished Jul 01 05:38:55 PM PDT 24
Peak memory 219620 kb
Host smart-b9084dd1-4433-496b-af00-6c1ecbe508ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540511843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.540511843
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2254209004
Short name T647
Test name
Test status
Simulation time 36241523 ps
CPU time 1.46 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 218828 kb
Host smart-2ef8c43d-a1db-439d-b01e-2961aab716a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254209004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2254209004
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3667439657
Short name T702
Test name
Test status
Simulation time 23058767 ps
CPU time 1.12 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 218924 kb
Host smart-9453adc9-e3ed-4536-8902-e3267d5931b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667439657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3667439657
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.4290159875
Short name T915
Test name
Test status
Simulation time 224212824 ps
CPU time 1.62 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 219100 kb
Host smart-28c3297d-352b-4f14-ad02-58e516b3257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290159875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4290159875
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3882512712
Short name T395
Test name
Test status
Simulation time 94086513 ps
CPU time 1.18 seconds
Started Jul 01 05:38:56 PM PDT 24
Finished Jul 01 05:38:59 PM PDT 24
Peak memory 219060 kb
Host smart-aa6764de-0be6-4426-b73b-9c94129cd4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882512712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3882512712
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.346505110
Short name T104
Test name
Test status
Simulation time 39138555 ps
CPU time 1.06 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:58 PM PDT 24
Peak memory 217712 kb
Host smart-1ff4c9d5-e731-44c4-8802-9c40f779d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346505110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.346505110
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1070854348
Short name T919
Test name
Test status
Simulation time 57084982 ps
CPU time 1.23 seconds
Started Jul 01 05:39:03 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 216000 kb
Host smart-ee262f08-59de-4da4-9320-ba0077677269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070854348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1070854348
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3644174717
Short name T411
Test name
Test status
Simulation time 263597784 ps
CPU time 1.57 seconds
Started Jul 01 05:38:56 PM PDT 24
Finished Jul 01 05:38:59 PM PDT 24
Peak memory 219600 kb
Host smart-85f6d7e5-5dd8-40ce-bcdd-1ad3dbbdd000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644174717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3644174717
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1158121625
Short name T590
Test name
Test status
Simulation time 56068249 ps
CPU time 1.19 seconds
Started Jul 01 05:39:02 PM PDT 24
Finished Jul 01 05:39:05 PM PDT 24
Peak memory 219080 kb
Host smart-6ef325f0-277d-40dd-a9bf-9b66ca692a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158121625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1158121625
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3970212742
Short name T83
Test name
Test status
Simulation time 30223894 ps
CPU time 1.34 seconds
Started Jul 01 05:39:03 PM PDT 24
Finished Jul 01 05:39:07 PM PDT 24
Peak memory 218964 kb
Host smart-baab6ead-8cb1-4296-bb60-36dbef145d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970212742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3970212742
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.132471481
Short name T733
Test name
Test status
Simulation time 25236333 ps
CPU time 1.24 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 219704 kb
Host smart-334edca5-c052-44b6-b15d-9eee35c49bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132471481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.132471481
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1409533252
Short name T87
Test name
Test status
Simulation time 256897932 ps
CPU time 2.08 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 220396 kb
Host smart-ce7588e3-6b8c-4e45-9ec1-d09eda06dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409533252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1409533252
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2578804767
Short name T982
Test name
Test status
Simulation time 45835071 ps
CPU time 1.19 seconds
Started Jul 01 05:38:58 PM PDT 24
Finished Jul 01 05:39:00 PM PDT 24
Peak memory 219220 kb
Host smart-a371ff10-8769-4c56-9cd9-b8de1d443463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578804767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2578804767
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3066398862
Short name T778
Test name
Test status
Simulation time 79257115 ps
CPU time 1.46 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 219532 kb
Host smart-2dff7dec-ed07-475a-aa47-bc8b26bef414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066398862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3066398862
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4030922477
Short name T608
Test name
Test status
Simulation time 22943946 ps
CPU time 1.17 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 220160 kb
Host smart-16a735d5-c638-4c87-9bac-97b10b076c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030922477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4030922477
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1717205151
Short name T589
Test name
Test status
Simulation time 54954166 ps
CPU time 1.25 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 217784 kb
Host smart-a3cb0d24-72d0-489e-ba8c-3d88d8510254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717205151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1717205151
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1100586295
Short name T44
Test name
Test status
Simulation time 267035839 ps
CPU time 1.43 seconds
Started Jul 01 05:36:16 PM PDT 24
Finished Jul 01 05:36:19 PM PDT 24
Peak memory 221020 kb
Host smart-a476b04a-4a95-4f20-8a0b-a7d4e0c0152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100586295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1100586295
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2292413478
Short name T926
Test name
Test status
Simulation time 16277621 ps
CPU time 0.93 seconds
Started Jul 01 05:36:16 PM PDT 24
Finished Jul 01 05:36:19 PM PDT 24
Peak memory 207052 kb
Host smart-e0a8d622-9fc0-4953-83c5-6b98e40dc846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292413478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2292413478
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1406404572
Short name T219
Test name
Test status
Simulation time 18299244 ps
CPU time 0.86 seconds
Started Jul 01 05:36:15 PM PDT 24
Finished Jul 01 05:36:18 PM PDT 24
Peak memory 216640 kb
Host smart-e422e676-0fc6-48c5-9e65-5b8f78ab8ffd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406404572 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1406404572
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4096023623
Short name T500
Test name
Test status
Simulation time 33606075 ps
CPU time 1.06 seconds
Started Jul 01 05:36:16 PM PDT 24
Finished Jul 01 05:36:19 PM PDT 24
Peak memory 217256 kb
Host smart-95637ed1-b3dc-40b4-b896-5637ebd4acf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096023623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4096023623
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3766634702
Short name T566
Test name
Test status
Simulation time 38485225 ps
CPU time 0.85 seconds
Started Jul 01 05:36:17 PM PDT 24
Finished Jul 01 05:36:19 PM PDT 24
Peak memory 218532 kb
Host smart-77f7b70f-d075-4827-b476-be9251e489f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766634702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3766634702
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.527962799
Short name T913
Test name
Test status
Simulation time 228220626 ps
CPU time 1.3 seconds
Started Jul 01 05:36:17 PM PDT 24
Finished Jul 01 05:36:20 PM PDT 24
Peak memory 220132 kb
Host smart-b9350eed-7ccc-4a73-b933-0ee842c31208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527962799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.527962799
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3308804979
Short name T371
Test name
Test status
Simulation time 31874575 ps
CPU time 0.88 seconds
Started Jul 01 05:36:17 PM PDT 24
Finished Jul 01 05:36:19 PM PDT 24
Peak memory 215708 kb
Host smart-be1c8f58-2ffc-45e9-9620-2ba16e30441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308804979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3308804979
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3555296868
Short name T793
Test name
Test status
Simulation time 54006351 ps
CPU time 0.92 seconds
Started Jul 01 05:36:15 PM PDT 24
Finished Jul 01 05:36:18 PM PDT 24
Peak memory 215664 kb
Host smart-0761d722-26d8-433a-a7c4-682647a9b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555296868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3555296868
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1370744912
Short name T674
Test name
Test status
Simulation time 423157288 ps
CPU time 7.99 seconds
Started Jul 01 05:36:14 PM PDT 24
Finished Jul 01 05:36:23 PM PDT 24
Peak memory 215732 kb
Host smart-bbaafb95-5a2e-49f9-8b5c-6fdaae419d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370744912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1370744912
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.183675603
Short name T193
Test name
Test status
Simulation time 45152970 ps
CPU time 1.22 seconds
Started Jul 01 05:39:02 PM PDT 24
Finished Jul 01 05:39:05 PM PDT 24
Peak memory 220128 kb
Host smart-82e21940-9b8f-4584-bf97-b4ddad4eb195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183675603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.183675603
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3501591268
Short name T671
Test name
Test status
Simulation time 74142523 ps
CPU time 1.28 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 219216 kb
Host smart-35c58de8-8046-416e-b982-6bcef4ba9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501591268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3501591268
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.342515819
Short name T625
Test name
Test status
Simulation time 28979809 ps
CPU time 1.26 seconds
Started Jul 01 05:39:02 PM PDT 24
Finished Jul 01 05:39:05 PM PDT 24
Peak memory 220164 kb
Host smart-9ecdd0f9-65cc-4aa9-a600-e9d5c6a7e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342515819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.342515819
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2680230842
Short name T325
Test name
Test status
Simulation time 35470350 ps
CPU time 1.37 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 220412 kb
Host smart-b0bfbb67-3aad-42ed-ad20-e94c91ee167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680230842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2680230842
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1881247663
Short name T336
Test name
Test status
Simulation time 94881718 ps
CPU time 1.27 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 215876 kb
Host smart-fc71bc17-9555-420c-b6d3-12d47327e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881247663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1881247663
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.116824944
Short name T93
Test name
Test status
Simulation time 54053258 ps
CPU time 1.12 seconds
Started Jul 01 05:39:01 PM PDT 24
Finished Jul 01 05:39:04 PM PDT 24
Peak memory 217584 kb
Host smart-85974b07-734d-4bc5-99e6-d7267af5cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116824944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.116824944
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1580910847
Short name T942
Test name
Test status
Simulation time 85398941 ps
CPU time 1.15 seconds
Started Jul 01 05:38:59 PM PDT 24
Finished Jul 01 05:39:01 PM PDT 24
Peak memory 215704 kb
Host smart-a926c1aa-7998-4793-a837-4c7b19dd4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580910847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1580910847
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1192011305
Short name T874
Test name
Test status
Simulation time 29380571 ps
CPU time 1.28 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 220036 kb
Host smart-89d5f42a-e925-4d8f-b970-cc4468d8a3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192011305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1192011305
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3274485527
Short name T646
Test name
Test status
Simulation time 115049933 ps
CPU time 2.43 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:04 PM PDT 24
Peak memory 220544 kb
Host smart-dd3e4aea-cb76-4ea6-9aa7-3399e557e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274485527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3274485527
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.4279595730
Short name T920
Test name
Test status
Simulation time 28221687 ps
CPU time 1.24 seconds
Started Jul 01 05:39:03 PM PDT 24
Finished Jul 01 05:39:07 PM PDT 24
Peak memory 220036 kb
Host smart-2d44e35a-546a-4099-a398-b6f60e2c7217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279595730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.4279595730
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1924135203
Short name T684
Test name
Test status
Simulation time 32188005 ps
CPU time 1.36 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 218676 kb
Host smart-6b65d7ac-fc83-43b6-9dcf-a2861244ffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924135203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1924135203
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2280500212
Short name T983
Test name
Test status
Simulation time 101098815 ps
CPU time 1.35 seconds
Started Jul 01 05:39:04 PM PDT 24
Finished Jul 01 05:39:09 PM PDT 24
Peak memory 216096 kb
Host smart-533a91ae-3b76-4255-9008-f39a6eac140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280500212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2280500212
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3286531137
Short name T477
Test name
Test status
Simulation time 199876108 ps
CPU time 3.58 seconds
Started Jul 01 05:39:01 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 218872 kb
Host smart-e74b7f84-d26d-4e06-9626-8ca5694d9a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286531137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3286531137
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1246335300
Short name T964
Test name
Test status
Simulation time 245458883 ps
CPU time 1.24 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 219036 kb
Host smart-0347c784-8e36-42de-a54b-728d95f05a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246335300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1246335300
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.29917243
Short name T486
Test name
Test status
Simulation time 41734229 ps
CPU time 1.66 seconds
Started Jul 01 05:39:05 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 218856 kb
Host smart-1590dd5f-bc31-4761-939d-84d693c9bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29917243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.29917243
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.894998550
Short name T757
Test name
Test status
Simulation time 65512399 ps
CPU time 1.32 seconds
Started Jul 01 05:39:02 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 219068 kb
Host smart-29864fc3-fb53-47f5-bcaa-5648eff15ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894998550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.894998550
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2917872109
Short name T55
Test name
Test status
Simulation time 44616760 ps
CPU time 1.42 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:02 PM PDT 24
Peak memory 217648 kb
Host smart-baebf768-6565-4596-a301-927247030f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917872109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2917872109
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3131146571
Short name T614
Test name
Test status
Simulation time 51078721 ps
CPU time 1.22 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 218936 kb
Host smart-33b857f9-034a-4312-a26d-8fc4a72f2cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131146571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3131146571
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2745848653
Short name T833
Test name
Test status
Simulation time 24260389 ps
CPU time 1.27 seconds
Started Jul 01 05:36:21 PM PDT 24
Finished Jul 01 05:36:23 PM PDT 24
Peak memory 218892 kb
Host smart-0e70f95b-659f-43d8-808c-01003f5a75c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745848653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2745848653
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2183320844
Short name T506
Test name
Test status
Simulation time 16483607 ps
CPU time 0.97 seconds
Started Jul 01 05:36:22 PM PDT 24
Finished Jul 01 05:36:25 PM PDT 24
Peak memory 215436 kb
Host smart-93620597-9c33-453b-88f8-b13e0263ff23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183320844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2183320844
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2943354029
Short name T664
Test name
Test status
Simulation time 12759977 ps
CPU time 0.98 seconds
Started Jul 01 05:36:23 PM PDT 24
Finished Jul 01 05:36:25 PM PDT 24
Peak memory 215960 kb
Host smart-90110b6d-49ca-4786-9f49-e058aa54f962
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943354029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2943354029
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.194054415
Short name T641
Test name
Test status
Simulation time 24199999 ps
CPU time 0.9 seconds
Started Jul 01 05:36:22 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 218800 kb
Host smart-0a88aedb-7e3d-4761-afd0-3e703353658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194054415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.194054415
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1860759641
Short name T551
Test name
Test status
Simulation time 57539009 ps
CPU time 1.94 seconds
Started Jul 01 05:36:24 PM PDT 24
Finished Jul 01 05:36:27 PM PDT 24
Peak memory 218752 kb
Host smart-66363ab6-3945-4419-bfd2-f040505739d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860759641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1860759641
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.104388403
Short name T102
Test name
Test status
Simulation time 33162273 ps
CPU time 0.94 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:29 PM PDT 24
Peak memory 216220 kb
Host smart-018f2eb8-c37b-4c8e-90e3-f0c737d489ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104388403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.104388403
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3153982904
Short name T349
Test name
Test status
Simulation time 25575768 ps
CPU time 0.92 seconds
Started Jul 01 05:36:16 PM PDT 24
Finished Jul 01 05:36:18 PM PDT 24
Peak memory 215572 kb
Host smart-a71452ec-4818-4f40-8885-51795c3c1bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153982904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3153982904
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2418341268
Short name T380
Test name
Test status
Simulation time 59348868 ps
CPU time 1.64 seconds
Started Jul 01 05:36:22 PM PDT 24
Finished Jul 01 05:36:25 PM PDT 24
Peak memory 215588 kb
Host smart-2ceb43e8-0395-41c2-bec1-9c52b264fb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418341268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2418341268
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2076676689
Short name T234
Test name
Test status
Simulation time 141541388345 ps
CPU time 1715.38 seconds
Started Jul 01 05:36:21 PM PDT 24
Finished Jul 01 06:04:58 PM PDT 24
Peak memory 225092 kb
Host smart-3d7c8caf-b01a-4b7f-88ad-9a65f4db883f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076676689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2076676689
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2649628588
Short name T934
Test name
Test status
Simulation time 74082625 ps
CPU time 1.19 seconds
Started Jul 01 05:39:05 PM PDT 24
Finished Jul 01 05:39:08 PM PDT 24
Peak memory 220176 kb
Host smart-5e7a68c5-6253-42de-9f43-df2ee3bd7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649628588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2649628588
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1741458129
Short name T502
Test name
Test status
Simulation time 48046961 ps
CPU time 1.51 seconds
Started Jul 01 05:39:01 PM PDT 24
Finished Jul 01 05:39:04 PM PDT 24
Peak memory 218784 kb
Host smart-16122682-2b53-457b-ae65-a889b37fdfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741458129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1741458129
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.2778236804
Short name T331
Test name
Test status
Simulation time 74390781 ps
CPU time 1.1 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 219924 kb
Host smart-504b656c-6fc6-4318-9be4-2422783f39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778236804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2778236804
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.371996156
Short name T620
Test name
Test status
Simulation time 67176260 ps
CPU time 1.26 seconds
Started Jul 01 05:39:00 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 215664 kb
Host smart-4970083e-e078-490e-a126-3973ac3bbb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371996156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.371996156
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2382151899
Short name T157
Test name
Test status
Simulation time 28652620 ps
CPU time 1.18 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 221416 kb
Host smart-961245f9-3dae-49f4-b246-43dad0920f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382151899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2382151899
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3943543564
Short name T627
Test name
Test status
Simulation time 87265377 ps
CPU time 1.24 seconds
Started Jul 01 05:39:16 PM PDT 24
Finished Jul 01 05:39:19 PM PDT 24
Peak memory 220308 kb
Host smart-1a442481-c2a6-4cf2-8d55-04de2b83a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943543564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3943543564
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2366335546
Short name T171
Test name
Test status
Simulation time 26044747 ps
CPU time 1.22 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 220212 kb
Host smart-7da611bb-f5cd-4096-a80b-83438073e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366335546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2366335546
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2118772490
Short name T795
Test name
Test status
Simulation time 65392832 ps
CPU time 1.62 seconds
Started Jul 01 05:39:08 PM PDT 24
Finished Jul 01 05:39:12 PM PDT 24
Peak memory 219232 kb
Host smart-395e5fc9-39a5-44f8-9222-8dbd00d8af52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118772490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2118772490
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.216857800
Short name T508
Test name
Test status
Simulation time 89576455 ps
CPU time 1.28 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 219932 kb
Host smart-9887846e-422e-40ca-955a-a653041c98f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216857800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.216857800
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2335735384
Short name T580
Test name
Test status
Simulation time 203128101 ps
CPU time 1.5 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 218912 kb
Host smart-dbec74ce-d8b4-4064-978b-d62f2c4bdcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335735384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2335735384
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3404246403
Short name T973
Test name
Test status
Simulation time 26437625 ps
CPU time 1.24 seconds
Started Jul 01 05:39:11 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 220672 kb
Host smart-71c92762-3f0e-463d-9ba9-5c185c02f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404246403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3404246403
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.428643584
Short name T781
Test name
Test status
Simulation time 252870553 ps
CPU time 1.39 seconds
Started Jul 01 05:39:17 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 220020 kb
Host smart-812a71dd-d7c1-46ce-a425-7fda43f038e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428643584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.428643584
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2770527491
Short name T320
Test name
Test status
Simulation time 92265030 ps
CPU time 1.32 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 217752 kb
Host smart-1a887d5e-d11c-45b0-8c26-16f80ec0bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770527491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2770527491
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4049146763
Short name T706
Test name
Test status
Simulation time 76486359 ps
CPU time 1.19 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 219072 kb
Host smart-077fd492-aac9-485f-8548-461fe6603ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049146763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4049146763
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1041151219
Short name T493
Test name
Test status
Simulation time 99662730 ps
CPU time 1.31 seconds
Started Jul 01 05:39:08 PM PDT 24
Finished Jul 01 05:39:12 PM PDT 24
Peak memory 219444 kb
Host smart-1ec5d3d1-e54b-4861-b72c-345f49205e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041151219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1041151219
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.47003912
Short name T282
Test name
Test status
Simulation time 89341033 ps
CPU time 1.22 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 220792 kb
Host smart-496cc024-71a6-4d08-b42d-eb352c6a7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47003912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.47003912
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.60570214
Short name T955
Test name
Test status
Simulation time 71572167 ps
CPU time 2.63 seconds
Started Jul 01 05:39:05 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 215700 kb
Host smart-9c380cfa-7bd5-4dd4-b123-b2bdede36bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60570214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.60570214
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2821444391
Short name T389
Test name
Test status
Simulation time 223859567 ps
CPU time 2.73 seconds
Started Jul 01 05:39:16 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 220048 kb
Host smart-76735a57-5c68-4bc4-9958-aeb1a46d09ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821444391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2821444391
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3014634466
Short name T488
Test name
Test status
Simulation time 36706490 ps
CPU time 1.04 seconds
Started Jul 01 05:36:22 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 218768 kb
Host smart-42fac496-6c28-44af-80b4-047bf9b7a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014634466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3014634466
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3632467335
Short name T408
Test name
Test status
Simulation time 51475510 ps
CPU time 0.97 seconds
Started Jul 01 05:36:25 PM PDT 24
Finished Jul 01 05:36:27 PM PDT 24
Peak memory 207224 kb
Host smart-5c132294-4e69-4eb8-9e75-b4c4e7289fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632467335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3632467335
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2891446913
Short name T90
Test name
Test status
Simulation time 12752033 ps
CPU time 0.91 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:29 PM PDT 24
Peak memory 216868 kb
Host smart-051d0f44-ae31-44b6-a107-f8f1220b49df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891446913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2891446913
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.255930950
Short name T499
Test name
Test status
Simulation time 21876123 ps
CPU time 1.07 seconds
Started Jul 01 05:36:28 PM PDT 24
Finished Jul 01 05:36:31 PM PDT 24
Peak memory 217188 kb
Host smart-56692e30-e6b0-4504-98ad-b3fbada32fc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255930950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.255930950
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3773044227
Short name T885
Test name
Test status
Simulation time 22666320 ps
CPU time 0.99 seconds
Started Jul 01 05:36:23 PM PDT 24
Finished Jul 01 05:36:25 PM PDT 24
Peak memory 218676 kb
Host smart-2c607fe9-8844-4b47-96f6-663d1d2ee971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773044227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3773044227
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.2682965816
Short name T697
Test name
Test status
Simulation time 35636236 ps
CPU time 0.87 seconds
Started Jul 01 05:36:21 PM PDT 24
Finished Jul 01 05:36:23 PM PDT 24
Peak memory 215588 kb
Host smart-f930c49e-da81-4b2e-a65c-3aece0d13e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682965816 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2682965816
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1899578591
Short name T850
Test name
Test status
Simulation time 50329083 ps
CPU time 1 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:29 PM PDT 24
Peak memory 215760 kb
Host smart-1b5c420f-fc8e-42ee-b853-d9180b7b3004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899578591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1899578591
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.151035052
Short name T922
Test name
Test status
Simulation time 262956889 ps
CPU time 1.42 seconds
Started Jul 01 05:36:21 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 217756 kb
Host smart-4eed6f5e-7018-4651-be82-0832c78ea60f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151035052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.151035052
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.4072665651
Short name T797
Test name
Test status
Simulation time 118680473 ps
CPU time 1.17 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:09 PM PDT 24
Peak memory 219912 kb
Host smart-8c8c70f5-2038-4991-bf7b-dbc2c248b8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072665651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.4072665651
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2334516470
Short name T855
Test name
Test status
Simulation time 80095133 ps
CPU time 1.1 seconds
Started Jul 01 05:39:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 217516 kb
Host smart-77d35025-5f07-48be-ad14-be3048683aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334516470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2334516470
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3365319008
Short name T739
Test name
Test status
Simulation time 119498288 ps
CPU time 1.13 seconds
Started Jul 01 05:39:15 PM PDT 24
Finished Jul 01 05:39:17 PM PDT 24
Peak memory 218944 kb
Host smart-4dac9252-ae1c-4cf5-81ba-f48a693c3fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365319008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3365319008
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.350816390
Short name T893
Test name
Test status
Simulation time 118299376 ps
CPU time 1.43 seconds
Started Jul 01 05:39:16 PM PDT 24
Finished Jul 01 05:39:19 PM PDT 24
Peak memory 220388 kb
Host smart-ee638d72-c69c-4742-9e4e-d25677f1996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350816390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.350816390
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1981249158
Short name T222
Test name
Test status
Simulation time 35649589 ps
CPU time 1.1 seconds
Started Jul 01 05:39:10 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 220784 kb
Host smart-14898153-ddd1-49bc-93ae-f94a0892c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981249158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1981249158
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.915575546
Short name T322
Test name
Test status
Simulation time 78638003 ps
CPU time 2.79 seconds
Started Jul 01 05:39:08 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 220400 kb
Host smart-d8069d87-7b9c-417a-bac7-0841f0c8dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915575546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.915575546
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1901713346
Short name T131
Test name
Test status
Simulation time 98177771 ps
CPU time 1.22 seconds
Started Jul 01 05:39:08 PM PDT 24
Finished Jul 01 05:39:12 PM PDT 24
Peak memory 220264 kb
Host smart-0492cfd0-0907-444e-a298-f95880f68ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901713346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1901713346
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2516790723
Short name T443
Test name
Test status
Simulation time 59599486 ps
CPU time 1.79 seconds
Started Jul 01 05:39:08 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 219036 kb
Host smart-88f5d229-9e91-479c-8751-28d17a2e8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516790723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2516790723
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2883949761
Short name T601
Test name
Test status
Simulation time 339264754 ps
CPU time 1.36 seconds
Started Jul 01 05:39:16 PM PDT 24
Finished Jul 01 05:39:19 PM PDT 24
Peak memory 219684 kb
Host smart-92462763-70f1-41d7-8629-e35667aa49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883949761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2883949761
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3369389877
Short name T564
Test name
Test status
Simulation time 42559817 ps
CPU time 1.61 seconds
Started Jul 01 05:39:09 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 220292 kb
Host smart-d382d25d-59ac-4991-b719-72ff8a6e3c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369389877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3369389877
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3465852417
Short name T809
Test name
Test status
Simulation time 29146869 ps
CPU time 1.28 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 219820 kb
Host smart-e2a62085-038b-49cc-8982-7a0e4f6bac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465852417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3465852417
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3053520174
Short name T631
Test name
Test status
Simulation time 53573439 ps
CPU time 1.2 seconds
Started Jul 01 05:39:06 PM PDT 24
Finished Jul 01 05:39:10 PM PDT 24
Peak memory 217540 kb
Host smart-6c169e9f-740c-4458-ab94-64f02f7dc1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053520174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3053520174
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3545695616
Short name T961
Test name
Test status
Simulation time 44636288 ps
CPU time 1.17 seconds
Started Jul 01 05:39:13 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 218860 kb
Host smart-e945bebe-8d34-4b0f-a7ed-52e91f536486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545695616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3545695616
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1778449221
Short name T574
Test name
Test status
Simulation time 36718736 ps
CPU time 1.12 seconds
Started Jul 01 05:39:10 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 217844 kb
Host smart-7fe22620-797d-46c5-812c-ace7f5ae29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778449221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1778449221
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1468446881
Short name T438
Test name
Test status
Simulation time 27698501 ps
CPU time 1.28 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:14 PM PDT 24
Peak memory 220976 kb
Host smart-d6d31379-85b7-4177-a3c3-c7ce7f0326b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468446881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1468446881
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.209914155
Short name T534
Test name
Test status
Simulation time 25657844 ps
CPU time 1.39 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:14 PM PDT 24
Peak memory 217768 kb
Host smart-3eba30d2-2ee1-4748-8b57-632fac9fb5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209914155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.209914155
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.823740657
Short name T96
Test name
Test status
Simulation time 30788059 ps
CPU time 1.31 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:14 PM PDT 24
Peak memory 216100 kb
Host smart-00995853-92e0-4c04-9d24-6ff628940582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823740657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.823740657
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3936957397
Short name T482
Test name
Test status
Simulation time 78118352 ps
CPU time 2.82 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 217904 kb
Host smart-1049c3b3-d951-4452-8af4-d3cc52503a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936957397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3936957397
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.4127609921
Short name T106
Test name
Test status
Simulation time 29352485 ps
CPU time 1.28 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 220128 kb
Host smart-8edb24fc-f73f-4f57-8f91-2866f35bed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127609921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.4127609921
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4188526007
Short name T946
Test name
Test status
Simulation time 150456007 ps
CPU time 0.84 seconds
Started Jul 01 05:36:29 PM PDT 24
Finished Jul 01 05:36:31 PM PDT 24
Peak memory 206880 kb
Host smart-2b2d8c99-80ef-41e3-b755-5f2d01b05569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188526007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4188526007
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.415471601
Short name T760
Test name
Test status
Simulation time 36034073 ps
CPU time 0.84 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:28 PM PDT 24
Peak memory 215808 kb
Host smart-93d1becc-39b7-4878-94d6-fa5ae6de9ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415471601 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.415471601
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3363427815
Short name T616
Test name
Test status
Simulation time 280451546 ps
CPU time 1.18 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:30 PM PDT 24
Peak memory 217236 kb
Host smart-8a5ca694-d969-48b8-bee3-046ac31a97e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363427815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3363427815
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1513334795
Short name T115
Test name
Test status
Simulation time 29541678 ps
CPU time 1.06 seconds
Started Jul 01 05:36:28 PM PDT 24
Finished Jul 01 05:36:30 PM PDT 24
Peak memory 220072 kb
Host smart-cc4cb2f7-622d-4b83-884d-52c150bc9105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513334795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1513334795
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1737436552
Short name T597
Test name
Test status
Simulation time 85116334 ps
CPU time 1.21 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:30 PM PDT 24
Peak memory 217604 kb
Host smart-371624a5-e15e-4e42-8ea0-fdc861ff4c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737436552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1737436552
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.375883866
Short name T785
Test name
Test status
Simulation time 50228560 ps
CPU time 0.89 seconds
Started Jul 01 05:36:28 PM PDT 24
Finished Jul 01 05:36:31 PM PDT 24
Peak memory 215652 kb
Host smart-71014709-9673-4b07-a578-e0fdd1e6f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375883866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.375883866
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.411906798
Short name T861
Test name
Test status
Simulation time 147221869 ps
CPU time 3.19 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:32 PM PDT 24
Peak memory 217700 kb
Host smart-a2f04af5-5964-462c-9112-a3d2a5041efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411906798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.411906798
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3808314142
Short name T749
Test name
Test status
Simulation time 26953720963 ps
CPU time 445.33 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:43:53 PM PDT 24
Peak memory 223772 kb
Host smart-10b62c5c-ddf4-42fe-bd09-feca52ca171c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808314142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3808314142
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2471456503
Short name T859
Test name
Test status
Simulation time 27436334 ps
CPU time 1.17 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:15 PM PDT 24
Peak memory 220264 kb
Host smart-1c67ad99-2b53-449e-a575-067bff1cd555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471456503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2471456503
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.926026841
Short name T451
Test name
Test status
Simulation time 36545449 ps
CPU time 1.15 seconds
Started Jul 01 05:39:10 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 220104 kb
Host smart-4749fe63-bf94-44f0-b882-0fd1bee44a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926026841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.926026841
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2899651446
Short name T139
Test name
Test status
Simulation time 36007332 ps
CPU time 1.12 seconds
Started Jul 01 05:39:14 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 218804 kb
Host smart-7529ed8d-7c54-4ecf-9b4d-ffd79ad3bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899651446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2899651446
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1945705905
Short name T386
Test name
Test status
Simulation time 63256696 ps
CPU time 1.09 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 218708 kb
Host smart-62fc34c5-7902-4d37-af22-ed0db34980e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945705905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1945705905
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1973267128
Short name T357
Test name
Test status
Simulation time 30015635 ps
CPU time 1.34 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:15 PM PDT 24
Peak memory 220008 kb
Host smart-19da33b1-35ce-4136-8fb2-111259dbbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973267128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1973267128
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3814016636
Short name T413
Test name
Test status
Simulation time 37781037 ps
CPU time 1.44 seconds
Started Jul 01 05:39:14 PM PDT 24
Finished Jul 01 05:39:17 PM PDT 24
Peak memory 217688 kb
Host smart-863a5f65-fd09-46a1-be1b-64afcaf553ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814016636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3814016636
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.4266796214
Short name T221
Test name
Test status
Simulation time 68570793 ps
CPU time 1.14 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 219512 kb
Host smart-277b939b-b853-4a4c-bf24-593d8ec9b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266796214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.4266796214
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.816505302
Short name T326
Test name
Test status
Simulation time 35575099 ps
CPU time 1.42 seconds
Started Jul 01 05:39:13 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 220112 kb
Host smart-ea0bee90-2ee5-4638-bb03-e99006199ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816505302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.816505302
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2545699830
Short name T330
Test name
Test status
Simulation time 84420259 ps
CPU time 1.1 seconds
Started Jul 01 05:39:11 PM PDT 24
Finished Jul 01 05:39:13 PM PDT 24
Peak memory 221060 kb
Host smart-2742bcf5-cb3f-4f9a-a8b7-2a1f3289c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545699830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2545699830
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.842982834
Short name T837
Test name
Test status
Simulation time 32545381 ps
CPU time 1.26 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:15 PM PDT 24
Peak memory 218880 kb
Host smart-2190db71-99e3-43bb-a6f6-8b5b1397198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842982834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.842982834
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.360466019
Short name T136
Test name
Test status
Simulation time 65022168 ps
CPU time 1.08 seconds
Started Jul 01 05:39:12 PM PDT 24
Finished Jul 01 05:39:14 PM PDT 24
Peak memory 220156 kb
Host smart-f57db61e-6987-4e6f-900a-da9a165da29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360466019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.360466019
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.3332084855
Short name T152
Test name
Test status
Simulation time 62693675 ps
CPU time 1.11 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 219116 kb
Host smart-a67ab2e6-0f3a-4139-a832-0ea7060ba443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332084855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3332084855
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2054064330
Short name T672
Test name
Test status
Simulation time 78243243 ps
CPU time 1.28 seconds
Started Jul 01 05:39:14 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 219360 kb
Host smart-344e2dd4-da98-472f-8ee0-db126c57c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054064330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2054064330
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3798292782
Short name T979
Test name
Test status
Simulation time 41364290 ps
CPU time 1.4 seconds
Started Jul 01 05:39:18 PM PDT 24
Finished Jul 01 05:39:21 PM PDT 24
Peak memory 220852 kb
Host smart-5453f1bc-6c9b-4e3d-8166-c12427bddce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798292782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3798292782
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1644114542
Short name T661
Test name
Test status
Simulation time 4553046095 ps
CPU time 87.75 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:40:49 PM PDT 24
Peak memory 218944 kb
Host smart-4832e491-a662-4962-bccb-819be8a10ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644114542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1644114542
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3066691734
Short name T918
Test name
Test status
Simulation time 85279742 ps
CPU time 1.18 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 218936 kb
Host smart-4e65e64c-78a3-4935-8045-c4e58b1ea873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066691734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3066691734
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.992012279
Short name T414
Test name
Test status
Simulation time 100586401 ps
CPU time 1.59 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 219264 kb
Host smart-52148135-76f5-44e8-978a-99d6ae28508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992012279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.992012279
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3973127287
Short name T786
Test name
Test status
Simulation time 47221542 ps
CPU time 1.28 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 219860 kb
Host smart-44875351-2daf-46f1-b386-d41f0432b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973127287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3973127287
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2186833876
Short name T823
Test name
Test status
Simulation time 61020405 ps
CPU time 1.3 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:27 PM PDT 24
Peak memory 217540 kb
Host smart-e90eea82-7a3c-4e48-b89d-6cb8c4675db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186833876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2186833876
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.4221358919
Short name T162
Test name
Test status
Simulation time 62542745 ps
CPU time 1.02 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:36 PM PDT 24
Peak memory 220088 kb
Host smart-19a1222e-7d49-40e0-abd7-3c1de9a04848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221358919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4221358919
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2547512616
Short name T457
Test name
Test status
Simulation time 100641926 ps
CPU time 0.89 seconds
Started Jul 01 05:36:31 PM PDT 24
Finished Jul 01 05:36:33 PM PDT 24
Peak memory 215256 kb
Host smart-0e11aff4-8ef9-4a8f-a06e-ad28270246fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547512616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2547512616
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.2530264364
Short name T359
Test name
Test status
Simulation time 27214734 ps
CPU time 1.08 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 220872 kb
Host smart-d6f0153b-b1d5-4cc1-9722-759f57b8be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530264364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2530264364
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1559045756
Short name T540
Test name
Test status
Simulation time 53059370 ps
CPU time 1.52 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:29 PM PDT 24
Peak memory 218932 kb
Host smart-2ea85dd7-b6d0-49c4-a2eb-249420c67a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559045756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1559045756
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.250293505
Short name T974
Test name
Test status
Simulation time 36563337 ps
CPU time 0.83 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:29 PM PDT 24
Peak memory 215684 kb
Host smart-825da636-5ab2-4a6d-a98b-0d982a84892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250293505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.250293505
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.503549535
Short name T712
Test name
Test status
Simulation time 40953610 ps
CPU time 0.93 seconds
Started Jul 01 05:36:27 PM PDT 24
Finished Jul 01 05:36:30 PM PDT 24
Peak memory 215700 kb
Host smart-68974bfc-9107-46eb-82a4-e319a510247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503549535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.503549535
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3105005954
Short name T568
Test name
Test status
Simulation time 783218973 ps
CPU time 4.65 seconds
Started Jul 01 05:36:26 PM PDT 24
Finished Jul 01 05:36:32 PM PDT 24
Peak memory 215840 kb
Host smart-23201aab-25c8-485d-972f-a94632bd4bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105005954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3105005954
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1215638193
Short name T232
Test name
Test status
Simulation time 82602856577 ps
CPU time 1630.91 seconds
Started Jul 01 05:36:28 PM PDT 24
Finished Jul 01 06:03:40 PM PDT 24
Peak memory 225212 kb
Host smart-c5ad60eb-a8bd-4fd3-a578-03874d06e027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215638193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1215638193
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3468428727
Short name T965
Test name
Test status
Simulation time 190296681 ps
CPU time 1.11 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 220192 kb
Host smart-df09aa9e-9643-45bd-a7e4-a2a5ab5999b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468428727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3468428727
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.253475016
Short name T470
Test name
Test status
Simulation time 49005170 ps
CPU time 1.07 seconds
Started Jul 01 05:39:17 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 217772 kb
Host smart-4c13e2f1-f98f-4459-b52d-ce076d2f3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253475016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.253475016
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1843292906
Short name T805
Test name
Test status
Simulation time 81042615 ps
CPU time 1.35 seconds
Started Jul 01 05:39:18 PM PDT 24
Finished Jul 01 05:39:21 PM PDT 24
Peak memory 218960 kb
Host smart-3d094712-916b-46d3-86ce-e32cf47424f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843292906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1843292906
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1598186966
Short name T466
Test name
Test status
Simulation time 103770107 ps
CPU time 1.27 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 217748 kb
Host smart-2302908b-7bff-4de2-866b-fa745d445d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598186966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1598186966
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2193754749
Short name T444
Test name
Test status
Simulation time 28677152 ps
CPU time 1.26 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 221124 kb
Host smart-463d243c-ca5d-4eb4-a255-11e2302b617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193754749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2193754749
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.519860877
Short name T379
Test name
Test status
Simulation time 29033292 ps
CPU time 1.15 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 217524 kb
Host smart-eb6014a4-2fca-49fc-841d-c2658cb6ad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519860877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.519860877
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1857330407
Short name T177
Test name
Test status
Simulation time 45573191 ps
CPU time 1.15 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 218940 kb
Host smart-5189ad3e-c1ee-4669-bc88-32a11f1abfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857330407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1857330407
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3823045790
Short name T936
Test name
Test status
Simulation time 36414535 ps
CPU time 1.27 seconds
Started Jul 01 05:39:22 PM PDT 24
Finished Jul 01 05:39:25 PM PDT 24
Peak memory 218928 kb
Host smart-d51221ce-8741-42e8-bc83-3a845ad3c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823045790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3823045790
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4182132455
Short name T550
Test name
Test status
Simulation time 43083163 ps
CPU time 1.19 seconds
Started Jul 01 05:39:22 PM PDT 24
Finished Jul 01 05:39:25 PM PDT 24
Peak memory 218908 kb
Host smart-93058e3b-fb24-41f1-b04e-5adcc9483a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182132455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4182132455
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2108028820
Short name T363
Test name
Test status
Simulation time 79780312 ps
CPU time 1 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:21 PM PDT 24
Peak memory 217644 kb
Host smart-5a3ab6ea-8399-4f55-890b-52ec070532ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108028820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2108028820
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3110323318
Short name T810
Test name
Test status
Simulation time 47071309 ps
CPU time 1.3 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 219032 kb
Host smart-20560cde-8a87-45d3-ae25-b621bb2d374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110323318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3110323318
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.939842774
Short name T708
Test name
Test status
Simulation time 75150208 ps
CPU time 2.83 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 219808 kb
Host smart-1190824c-dc57-46c3-b6af-07b6654c2f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939842774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.939842774
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.91877097
Short name T969
Test name
Test status
Simulation time 132316229 ps
CPU time 1.23 seconds
Started Jul 01 05:39:17 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 216024 kb
Host smart-b617114e-9f4d-413f-8639-f188ded7811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91877097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.91877097
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.843430784
Short name T753
Test name
Test status
Simulation time 52317405 ps
CPU time 1.18 seconds
Started Jul 01 05:39:18 PM PDT 24
Finished Jul 01 05:39:21 PM PDT 24
Peak memory 219872 kb
Host smart-354989e2-ebf4-4a3a-a899-3c97b131d7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843430784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.843430784
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2108933390
Short name T503
Test name
Test status
Simulation time 245343601 ps
CPU time 1.41 seconds
Started Jul 01 05:39:19 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 221000 kb
Host smart-54bccfff-dd34-485e-9cc3-50698cec9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108933390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2108933390
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.488198548
Short name T662
Test name
Test status
Simulation time 74642475 ps
CPU time 1.19 seconds
Started Jul 01 05:39:21 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 219244 kb
Host smart-3c8eb7aa-abba-4b4d-9b47-60cc6b7ae011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488198548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.488198548
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1567562487
Short name T283
Test name
Test status
Simulation time 155642485 ps
CPU time 1.28 seconds
Started Jul 01 05:39:21 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 220632 kb
Host smart-37f81a3d-746b-45c6-89fa-d6cb4b14f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567562487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1567562487
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1296909521
Short name T648
Test name
Test status
Simulation time 62475459 ps
CPU time 1.21 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 217612 kb
Host smart-9966627b-1ae7-4f4b-b8d2-6664b40aa146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296909521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1296909521
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.65454160
Short name T419
Test name
Test status
Simulation time 33047951 ps
CPU time 1.36 seconds
Started Jul 01 05:39:20 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 216048 kb
Host smart-8578b979-332e-4bc8-99f3-e4dd6cada5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65454160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.65454160
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2613448989
Short name T984
Test name
Test status
Simulation time 52303000 ps
CPU time 1.16 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 217752 kb
Host smart-b39bd322-8093-43d4-907b-3a42baf58969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613448989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2613448989
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1552304934
Short name T743
Test name
Test status
Simulation time 92541825 ps
CPU time 1.23 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 218908 kb
Host smart-610333b2-f9b6-4fc7-bafc-d75728750835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552304934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1552304934
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.557952110
Short name T135
Test name
Test status
Simulation time 32105066 ps
CPU time 1.06 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 217160 kb
Host smart-4339870b-ab0e-47f8-aae8-4fc7e8848937
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557952110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.557952110
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.666013448
Short name T14
Test name
Test status
Simulation time 67924802 ps
CPU time 1.16 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 225852 kb
Host smart-569912a1-0f1f-43dd-93b8-23a3e74677d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666013448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.666013448
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3746053882
Short name T880
Test name
Test status
Simulation time 79256766 ps
CPU time 1.59 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 219128 kb
Host smart-c79f5684-a3d4-4181-a6d3-7321e7dadc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746053882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3746053882
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2939150615
Short name T112
Test name
Test status
Simulation time 83580992 ps
CPU time 0.9 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 215844 kb
Host smart-9f891f41-2a00-4f96-8215-3e19707175f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939150615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2939150615
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.968865639
Short name T73
Test name
Test status
Simulation time 18115819 ps
CPU time 0.98 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 215692 kb
Host smart-e0878fd3-495b-4391-9f50-3594d08923e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968865639 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.968865639
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3239116890
Short name T815
Test name
Test status
Simulation time 253046823 ps
CPU time 5.15 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:38 PM PDT 24
Peak memory 218996 kb
Host smart-3615a215-750f-4111-9459-1b3294cc5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239116890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3239116890
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3255772403
Short name T562
Test name
Test status
Simulation time 93687577575 ps
CPU time 1026.49 seconds
Started Jul 01 05:36:33 PM PDT 24
Finished Jul 01 05:53:41 PM PDT 24
Peak memory 221564 kb
Host smart-588f4c90-6c6c-48b0-8f9f-d99037e1a5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255772403 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3255772403
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.360965048
Short name T774
Test name
Test status
Simulation time 80308645 ps
CPU time 1.16 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:26 PM PDT 24
Peak memory 216040 kb
Host smart-c5123769-33ee-42dc-8041-52a236cceae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360965048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.360965048
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.553560134
Short name T939
Test name
Test status
Simulation time 48328607 ps
CPU time 1.23 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 219100 kb
Host smart-2f663886-eff8-4c98-8c80-85321aa88d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553560134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.553560134
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3678930776
Short name T333
Test name
Test status
Simulation time 52103539 ps
CPU time 1.13 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 220920 kb
Host smart-8a002e31-9a5b-43cb-8b5c-d808d3c69fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678930776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3678930776
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4087155166
Short name T840
Test name
Test status
Simulation time 97992540 ps
CPU time 1.26 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 218964 kb
Host smart-27cd192f-d90f-44f0-b5d3-b669e79396fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087155166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4087155166
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1297248019
Short name T878
Test name
Test status
Simulation time 174741985 ps
CPU time 1.41 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 216016 kb
Host smart-0ac0591b-5148-4349-be84-ca55c13fa7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297248019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1297248019
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3037879438
Short name T992
Test name
Test status
Simulation time 149089177 ps
CPU time 1.98 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 219052 kb
Host smart-84fa989c-ae31-40a2-9f77-30bf29abece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037879438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3037879438
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.244705995
Short name T645
Test name
Test status
Simulation time 42481136 ps
CPU time 1.2 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 219596 kb
Host smart-6147aa14-a89d-4984-b97a-4abb8339e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244705995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.244705995
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2632627310
Short name T306
Test name
Test status
Simulation time 130926350 ps
CPU time 2.62 seconds
Started Jul 01 05:39:23 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 217864 kb
Host smart-d947c004-ac6c-4643-b2b9-ffd79fdf6ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632627310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2632627310
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3914276496
Short name T650
Test name
Test status
Simulation time 474399588 ps
CPU time 1.35 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 216156 kb
Host smart-a134e910-cbb0-430c-ad8a-d54bc65facb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914276496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3914276496
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1293243920
Short name T456
Test name
Test status
Simulation time 139158430 ps
CPU time 2.42 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 220348 kb
Host smart-9c530408-3e29-412e-a2b9-36a65899d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293243920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1293243920
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.695870898
Short name T514
Test name
Test status
Simulation time 41052915 ps
CPU time 1 seconds
Started Jul 01 05:39:30 PM PDT 24
Finished Jul 01 05:39:33 PM PDT 24
Peak memory 217768 kb
Host smart-004246f7-bd48-42a7-aafe-f42f0369892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695870898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.695870898
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1787578142
Short name T1
Test name
Test status
Simulation time 38484568 ps
CPU time 1.39 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 220292 kb
Host smart-ec182383-3af9-4166-8e40-fae61d2e64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787578142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1787578142
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.520059787
Short name T761
Test name
Test status
Simulation time 77520119 ps
CPU time 1.06 seconds
Started Jul 01 05:39:23 PM PDT 24
Finished Jul 01 05:39:26 PM PDT 24
Peak memory 219672 kb
Host smart-825773ea-81a9-403f-b06b-38e4ee3c8af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520059787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.520059787
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3828150458
Short name T763
Test name
Test status
Simulation time 211793984 ps
CPU time 1.23 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:27 PM PDT 24
Peak memory 215984 kb
Host smart-ca0ff5bb-d1f1-49d9-a483-0a943c1bd8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828150458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3828150458
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3832056086
Short name T572
Test name
Test status
Simulation time 72230928 ps
CPU time 1.7 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 219068 kb
Host smart-9cc4d474-bcc8-4f95-9fce-cf9b545205a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832056086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3832056086
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1763758294
Short name T735
Test name
Test status
Simulation time 71694085 ps
CPU time 1.23 seconds
Started Jul 01 05:39:23 PM PDT 24
Finished Jul 01 05:39:26 PM PDT 24
Peak memory 218924 kb
Host smart-90b10ecd-d7a1-412b-b0d8-5a8d19ef1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763758294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1763758294
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4081506875
Short name T388
Test name
Test status
Simulation time 109614231 ps
CPU time 1.29 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:27 PM PDT 24
Peak memory 219460 kb
Host smart-0a9d766e-d169-4e85-a8d4-07480ecb5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081506875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4081506875
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.1682914236
Short name T360
Test name
Test status
Simulation time 75373579 ps
CPU time 0.79 seconds
Started Jul 01 05:36:39 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 207112 kb
Host smart-482ef48b-d474-4076-9af9-9114eeb28322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682914236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1682914236
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.676235448
Short name T985
Test name
Test status
Simulation time 21901886 ps
CPU time 1 seconds
Started Jul 01 05:36:38 PM PDT 24
Finished Jul 01 05:36:40 PM PDT 24
Peak memory 218712 kb
Host smart-e53022b1-9f54-4209-8b5a-35d3aac4e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676235448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.676235448
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2674359971
Short name T944
Test name
Test status
Simulation time 51419845 ps
CPU time 1.59 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 220368 kb
Host smart-b9aa6e27-06be-46f9-988b-ca34f5c68aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674359971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2674359971
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1778732829
Short name T730
Test name
Test status
Simulation time 40791990 ps
CPU time 0.89 seconds
Started Jul 01 05:36:35 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 215684 kb
Host smart-a7c39765-e323-4d78-9e96-e97a4e283e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778732829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1778732829
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3125508255
Short name T483
Test name
Test status
Simulation time 25741951 ps
CPU time 0.97 seconds
Started Jul 01 05:36:32 PM PDT 24
Finished Jul 01 05:36:34 PM PDT 24
Peak memory 215672 kb
Host smart-bfe05854-e95b-479a-9b6c-47c9b78b56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125508255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3125508255
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1296768042
Short name T962
Test name
Test status
Simulation time 739347575 ps
CPU time 4.11 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 05:36:40 PM PDT 24
Peak memory 218880 kb
Host smart-0e4e800b-7c79-4908-abc9-e465b67005b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296768042 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1296768042
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.90227994
Short name T225
Test name
Test status
Simulation time 253899020912 ps
CPU time 1763.03 seconds
Started Jul 01 05:36:34 PM PDT 24
Finished Jul 01 06:05:58 PM PDT 24
Peak memory 228116 kb
Host smart-e9f3d5fa-9433-420d-8365-dde821b2015a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90227994 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.90227994
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2703571456
Short name T188
Test name
Test status
Simulation time 29527450 ps
CPU time 1.25 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 220296 kb
Host smart-6d4a721d-016b-43b7-a36b-aa9d1a42f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703571456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2703571456
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4156525
Short name T699
Test name
Test status
Simulation time 66496494 ps
CPU time 2.39 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 220092 kb
Host smart-b57acb75-1819-4a74-a809-d2edcd00b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4156525
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3492213425
Short name T845
Test name
Test status
Simulation time 30544040 ps
CPU time 0.99 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 217792 kb
Host smart-8b64f5b5-8e9e-499f-b2ad-b39777e7fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492213425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3492213425
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1156984660
Short name T835
Test name
Test status
Simulation time 26435498 ps
CPU time 1.33 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 219000 kb
Host smart-5a47556b-3039-488e-9587-efe5951318a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156984660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1156984660
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.955264162
Short name T808
Test name
Test status
Simulation time 131478491 ps
CPU time 1.35 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 217708 kb
Host smart-fad14f17-ede3-4481-a3c1-19e48123904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955264162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.955264162
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2277191532
Short name T178
Test name
Test status
Simulation time 43518285 ps
CPU time 1.14 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 220172 kb
Host smart-13eff44e-eb60-49c0-9ad3-ba371ab1ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277191532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2277191532
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.31158580
Short name T48
Test name
Test status
Simulation time 89454581 ps
CPU time 1.31 seconds
Started Jul 01 05:39:24 PM PDT 24
Finished Jul 01 05:39:27 PM PDT 24
Peak memory 217648 kb
Host smart-60890d92-6265-49e4-a878-ddd717d551d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31158580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.31158580
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3269948870
Short name T257
Test name
Test status
Simulation time 107291060 ps
CPU time 1.32 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 216052 kb
Host smart-65155070-c1d9-4731-b3b7-e2578cf6d98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269948870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3269948870
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2226803429
Short name T725
Test name
Test status
Simulation time 121860186 ps
CPU time 1.55 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 219096 kb
Host smart-84103276-47e4-4e14-8b28-96d9560f0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226803429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2226803429
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3353073788
Short name T223
Test name
Test status
Simulation time 79406384 ps
CPU time 1.2 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 219160 kb
Host smart-142c7fa2-87c4-4b3f-b0d2-94ce0a25111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353073788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3353073788
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.4132386750
Short name T304
Test name
Test status
Simulation time 69314863 ps
CPU time 1.46 seconds
Started Jul 01 05:39:27 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 217712 kb
Host smart-6c3c4e88-1975-4360-bd00-eb68d1640d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132386750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4132386750
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.469943778
Short name T680
Test name
Test status
Simulation time 33127428 ps
CPU time 1.17 seconds
Started Jul 01 05:39:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 218900 kb
Host smart-8380c35e-79e4-4494-b354-ea026c72a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469943778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.469943778
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1964490927
Short name T734
Test name
Test status
Simulation time 30594165 ps
CPU time 1.26 seconds
Started Jul 01 05:39:25 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 217996 kb
Host smart-bbcdeb33-1a90-4419-b665-c5e97a23534e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964490927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1964490927
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1934286780
Short name T255
Test name
Test status
Simulation time 94111257 ps
CPU time 1.24 seconds
Started Jul 01 05:39:34 PM PDT 24
Finished Jul 01 05:39:39 PM PDT 24
Peak memory 218892 kb
Host smart-44d61b01-b514-485e-ab88-05c69e232c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934286780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1934286780
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1711942344
Short name T588
Test name
Test status
Simulation time 66216745 ps
CPU time 1.25 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 218940 kb
Host smart-db808ffd-0d20-4fa5-a8b3-1e50fa98d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711942344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1711942344
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.4219040180
Short name T145
Test name
Test status
Simulation time 29937012 ps
CPU time 1.35 seconds
Started Jul 01 05:39:29 PM PDT 24
Finished Jul 01 05:39:33 PM PDT 24
Peak memory 220700 kb
Host smart-cc534fd9-3954-45ad-9b30-4a058cf4adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219040180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.4219040180
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3315848204
Short name T12
Test name
Test status
Simulation time 43192332 ps
CPU time 1.55 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 219260 kb
Host smart-48a45221-1b9b-4cbc-9cd4-793778f1d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315848204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3315848204
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3845161724
Short name T567
Test name
Test status
Simulation time 79056474 ps
CPU time 1.16 seconds
Started Jul 01 05:39:29 PM PDT 24
Finished Jul 01 05:39:32 PM PDT 24
Peak memory 219204 kb
Host smart-d966c650-1d1a-4a3c-9a4a-2b456717ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845161724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3845161724
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.713461867
Short name T779
Test name
Test status
Simulation time 82954096 ps
CPU time 1.09 seconds
Started Jul 01 05:39:30 PM PDT 24
Finished Jul 01 05:39:33 PM PDT 24
Peak memory 217740 kb
Host smart-c3c5a390-a18b-4dc2-861f-11e81dcca218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713461867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.713461867
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2967471923
Short name T253
Test name
Test status
Simulation time 378726175 ps
CPU time 1.36 seconds
Started Jul 01 05:36:41 PM PDT 24
Finished Jul 01 05:36:44 PM PDT 24
Peak memory 216156 kb
Host smart-63899eb6-2011-4996-9c44-22b661a583fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967471923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2967471923
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.171992607
Short name T952
Test name
Test status
Simulation time 14976761 ps
CPU time 1 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:47 PM PDT 24
Peak memory 207324 kb
Host smart-f4897475-0e29-44e3-8cb6-d4cb334a7f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171992607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.171992607
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.2388415313
Short name T172
Test name
Test status
Simulation time 22840707 ps
CPU time 1.04 seconds
Started Jul 01 05:36:39 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 224320 kb
Host smart-85088f22-a29e-444b-9f71-08bff0cda479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388415313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2388415313
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1747778953
Short name T667
Test name
Test status
Simulation time 62865900 ps
CPU time 1.01 seconds
Started Jul 01 05:36:39 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 217480 kb
Host smart-5265143e-102f-4ef4-8eb1-383d01351864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747778953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1747778953
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1926210290
Short name T40
Test name
Test status
Simulation time 24651948 ps
CPU time 0.97 seconds
Started Jul 01 05:36:38 PM PDT 24
Finished Jul 01 05:36:40 PM PDT 24
Peak memory 216244 kb
Host smart-c4ef405a-1805-4adb-9a26-1531df6632c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926210290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1926210290
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2470108307
Short name T764
Test name
Test status
Simulation time 43757575 ps
CPU time 0.91 seconds
Started Jul 01 05:36:40 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 215680 kb
Host smart-c87d6db4-cf8e-4a89-b170-bfcad6866a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470108307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2470108307
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2318924943
Short name T842
Test name
Test status
Simulation time 287185960 ps
CPU time 3.28 seconds
Started Jul 01 05:36:39 PM PDT 24
Finished Jul 01 05:36:44 PM PDT 24
Peak memory 217844 kb
Host smart-fdc88c7a-6d47-4154-b488-a408fbc3a367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318924943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2318924943
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.2607766852
Short name T896
Test name
Test status
Simulation time 67180877 ps
CPU time 1.18 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 219188 kb
Host smart-300f356b-89de-4552-908c-bf6197d1b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607766852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2607766852
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.130537663
Short name T346
Test name
Test status
Simulation time 20623240 ps
CPU time 1.08 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:37 PM PDT 24
Peak memory 220328 kb
Host smart-77fd70dc-719d-404c-98fa-7f3462a5b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130537663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.130537663
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2650471136
Short name T288
Test name
Test status
Simulation time 28382220 ps
CPU time 1.28 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:37 PM PDT 24
Peak memory 220344 kb
Host smart-26b256fc-9daa-4c5a-9173-5dc79f85ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650471136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2650471136
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/182.edn_alert.2161547481
Short name T994
Test name
Test status
Simulation time 116239269 ps
CPU time 1.12 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:37 PM PDT 24
Peak memory 220136 kb
Host smart-e87f691e-84e6-40ff-a73f-7e0c246d8158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161547481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2161547481
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2588351494
Short name T45
Test name
Test status
Simulation time 68224420 ps
CPU time 1.67 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:37 PM PDT 24
Peak memory 219044 kb
Host smart-1a6e24ee-2a97-4bce-a5b0-bda5442e6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588351494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2588351494
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1861864860
Short name T517
Test name
Test status
Simulation time 25031918 ps
CPU time 1.16 seconds
Started Jul 01 05:39:34 PM PDT 24
Finished Jul 01 05:39:38 PM PDT 24
Peak memory 220252 kb
Host smart-1879c802-0fe7-43ec-abb6-8f9f9d45c40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861864860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1861864860
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.473797626
Short name T86
Test name
Test status
Simulation time 44538222 ps
CPU time 1.53 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 218780 kb
Host smart-0ad1be69-04da-4a50-91ca-6ce7719aeb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473797626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.473797626
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.4291662911
Short name T817
Test name
Test status
Simulation time 30384601 ps
CPU time 1.18 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:34 PM PDT 24
Peak memory 218652 kb
Host smart-a1367da3-916f-4e10-b8a1-ca16adb5a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291662911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.4291662911
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3195479554
Short name T836
Test name
Test status
Simulation time 35766602 ps
CPU time 1.26 seconds
Started Jul 01 05:39:34 PM PDT 24
Finished Jul 01 05:39:38 PM PDT 24
Peak memory 217544 kb
Host smart-548fc8e3-9ea4-46c2-ab39-b9e14c92a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195479554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3195479554
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3624625617
Short name T628
Test name
Test status
Simulation time 36315339 ps
CPU time 1.1 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 219952 kb
Host smart-4e52887b-41ed-428b-99f7-ccb3c1a62eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624625617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3624625617
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.2677189371
Short name T925
Test name
Test status
Simulation time 31971094 ps
CPU time 1.33 seconds
Started Jul 01 05:39:30 PM PDT 24
Finished Jul 01 05:39:34 PM PDT 24
Peak memory 216092 kb
Host smart-a6105d00-ac10-453a-ad3b-88219f135eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677189371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2677189371
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3557404610
Short name T382
Test name
Test status
Simulation time 45721499 ps
CPU time 1.6 seconds
Started Jul 01 05:39:30 PM PDT 24
Finished Jul 01 05:39:34 PM PDT 24
Peak memory 218908 kb
Host smart-3050d6ec-d618-49c0-878d-806456693b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557404610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3557404610
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3850221725
Short name T577
Test name
Test status
Simulation time 60680910 ps
CPU time 1.19 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 220136 kb
Host smart-120efeab-58de-4cdb-b415-24fc034d0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850221725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3850221725
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3604976535
Short name T49
Test name
Test status
Simulation time 59266647 ps
CPU time 1.3 seconds
Started Jul 01 05:39:30 PM PDT 24
Finished Jul 01 05:39:34 PM PDT 24
Peak memory 215700 kb
Host smart-e94e4b3e-9e49-4d2b-8503-f7f94936a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604976535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3604976535
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1144222469
Short name T244
Test name
Test status
Simulation time 66511267 ps
CPU time 1.22 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 218892 kb
Host smart-063717b4-d471-4c67-9bd9-fb8ae1218b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144222469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1144222469
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3745137425
Short name T312
Test name
Test status
Simulation time 47619895 ps
CPU time 1.42 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 219076 kb
Host smart-6aa5b4a3-a66b-4a0c-95e4-ba7ea824481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745137425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3745137425
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.4142401445
Short name T460
Test name
Test status
Simulation time 41734703 ps
CPU time 1.08 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 221204 kb
Host smart-4181fdb3-5658-4967-95ab-8f575f09cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142401445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.4142401445
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2909405720
Short name T978
Test name
Test status
Simulation time 55134447 ps
CPU time 1.66 seconds
Started Jul 01 05:39:34 PM PDT 24
Finished Jul 01 05:39:39 PM PDT 24
Peak memory 218012 kb
Host smart-3db9139c-8842-4173-812d-f5ddac4b7a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909405720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2909405720
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.82957522
Short name T239
Test name
Test status
Simulation time 30165396 ps
CPU time 1.29 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:48 PM PDT 24
Peak memory 219176 kb
Host smart-f319c5f3-29b6-4518-a245-0ee63a68d1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82957522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.82957522
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.30530565
Short name T378
Test name
Test status
Simulation time 38108370 ps
CPU time 0.83 seconds
Started Jul 01 05:36:44 PM PDT 24
Finished Jul 01 05:36:45 PM PDT 24
Peak memory 206920 kb
Host smart-76228d06-225c-4179-806a-fe1d884b9911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.30530565
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2929242
Short name T207
Test name
Test status
Simulation time 52791251 ps
CPU time 0.88 seconds
Started Jul 01 05:36:46 PM PDT 24
Finished Jul 01 05:36:48 PM PDT 24
Peak memory 216620 kb
Host smart-7dcae8fc-5692-4613-a8c6-db4d97b3f116
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2929242
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2235024308
Short name T689
Test name
Test status
Simulation time 89507731 ps
CPU time 1.06 seconds
Started Jul 01 05:36:43 PM PDT 24
Finished Jul 01 05:36:44 PM PDT 24
Peak memory 219956 kb
Host smart-b85581ee-07e6-4b36-8516-ccca5dfbf1a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235024308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2235024308
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.790540435
Short name T58
Test name
Test status
Simulation time 32920684 ps
CPU time 1.2 seconds
Started Jul 01 05:36:44 PM PDT 24
Finished Jul 01 05:36:45 PM PDT 24
Peak memory 229988 kb
Host smart-0b601f43-19a5-4ea8-b9b3-5f36ba305361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790540435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.790540435
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.157306809
Short name T991
Test name
Test status
Simulation time 77899900 ps
CPU time 1.07 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:48 PM PDT 24
Peak memory 217700 kb
Host smart-c1ffd8cb-2f5c-4e1c-93a5-0f53f5253efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157306809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.157306809
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.468312537
Short name T33
Test name
Test status
Simulation time 27220150 ps
CPU time 0.9 seconds
Started Jul 01 05:36:44 PM PDT 24
Finished Jul 01 05:36:45 PM PDT 24
Peak memory 216076 kb
Host smart-8e20f218-4f93-4ecf-a8fd-784a5ab8e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468312537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.468312537
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3076553909
Short name T548
Test name
Test status
Simulation time 55965440 ps
CPU time 0.97 seconds
Started Jul 01 05:36:44 PM PDT 24
Finished Jul 01 05:36:47 PM PDT 24
Peak memory 215684 kb
Host smart-6d6b6a9a-ed13-4881-bd39-6ad973f3e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076553909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3076553909
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.216824560
Short name T619
Test name
Test status
Simulation time 51121477 ps
CPU time 1.26 seconds
Started Jul 01 05:36:45 PM PDT 24
Finished Jul 01 05:36:48 PM PDT 24
Peak memory 217656 kb
Host smart-1d1fcbc8-fb0e-4a14-8106-4a9b8d071e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216824560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.216824560
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2352762225
Short name T831
Test name
Test status
Simulation time 337238460111 ps
CPU time 1304.3 seconds
Started Jul 01 05:36:47 PM PDT 24
Finished Jul 01 05:58:32 PM PDT 24
Peak memory 224396 kb
Host smart-ac46d932-e575-4831-8eb7-a4ef855db7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352762225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2352762225
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.546960284
Short name T50
Test name
Test status
Simulation time 33306436 ps
CPU time 1.28 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 217672 kb
Host smart-ed60333d-d548-4e35-8939-0a63c0f74388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546960284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.546960284
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.4001905000
Short name T76
Test name
Test status
Simulation time 39518118 ps
CPU time 1.17 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 221164 kb
Host smart-7f3bce6d-794a-49c6-b904-47a3992c650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001905000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.4001905000
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3952756277
Short name T354
Test name
Test status
Simulation time 92467190 ps
CPU time 1 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 217684 kb
Host smart-789b14d1-6534-4466-9b4f-e11705ce8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952756277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3952756277
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2356133186
Short name T683
Test name
Test status
Simulation time 23697666 ps
CPU time 1.17 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:38 PM PDT 24
Peak memory 220172 kb
Host smart-588e6b35-9b6e-4929-9655-0d9a2eda754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356133186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2356133186
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3712916689
Short name T660
Test name
Test status
Simulation time 100861296 ps
CPU time 1.25 seconds
Started Jul 01 05:39:33 PM PDT 24
Finished Jul 01 05:39:37 PM PDT 24
Peak memory 219236 kb
Host smart-9b7782e0-a43e-4c91-a685-7750ce3aee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712916689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3712916689
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3184922289
Short name T56
Test name
Test status
Simulation time 109777507 ps
CPU time 1.23 seconds
Started Jul 01 05:39:32 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 220196 kb
Host smart-60b4fc28-586e-4c06-8419-76e5acaa1697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184922289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3184922289
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.923334150
Short name T450
Test name
Test status
Simulation time 103617654 ps
CPU time 1.02 seconds
Started Jul 01 05:39:31 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 215660 kb
Host smart-ad829de5-eaa5-4996-89ab-d44ec9ce8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923334150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.923334150
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2464678782
Short name T324
Test name
Test status
Simulation time 44296783 ps
CPU time 1.76 seconds
Started Jul 01 05:39:41 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 218912 kb
Host smart-f456181f-b479-4aa8-82e6-a65f0e65f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464678782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2464678782
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3183475045
Short name T85
Test name
Test status
Simulation time 107112307 ps
CPU time 1.19 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 219212 kb
Host smart-d88bae3f-e755-4f0d-be02-4455b9592213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183475045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3183475045
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1115436671
Short name T884
Test name
Test status
Simulation time 147442277 ps
CPU time 1.3 seconds
Started Jul 01 05:39:38 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 220520 kb
Host smart-17c165a1-095f-4a61-b12c-20bc864d8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115436671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1115436671
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.422549265
Short name T520
Test name
Test status
Simulation time 38346070 ps
CPU time 0.99 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 217660 kb
Host smart-81d0b6da-0f0b-4074-9371-669567aacc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422549265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.422549265
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3600985047
Short name T150
Test name
Test status
Simulation time 33376634 ps
CPU time 1.36 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:39 PM PDT 24
Peak memory 216100 kb
Host smart-2cf910c9-fc7d-4e8e-aa36-d2428713e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600985047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3600985047
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1629637054
Short name T829
Test name
Test status
Simulation time 40662883 ps
CPU time 1.29 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 218724 kb
Host smart-c003be7f-cee8-4f9d-b786-6aa6212c911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629637054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1629637054
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1293730839
Short name T958
Test name
Test status
Simulation time 116440140 ps
CPU time 1.19 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 220092 kb
Host smart-5ce8b2f3-3f6a-4671-a2c1-fa9cefa44a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293730839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1293730839
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.4166698930
Short name T387
Test name
Test status
Simulation time 40197694 ps
CPU time 1.64 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 218900 kb
Host smart-3099af2d-27aa-4b69-801c-ad7225dabdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166698930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4166698930
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1292804949
Short name T935
Test name
Test status
Simulation time 147510839 ps
CPU time 1.27 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 220184 kb
Host smart-f1c7c153-e7c6-4f7d-b77d-81be759fcc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292804949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1292804949
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.3160309580
Short name T553
Test name
Test status
Simulation time 23343172 ps
CPU time 1.16 seconds
Started Jul 01 05:35:32 PM PDT 24
Finished Jul 01 05:35:34 PM PDT 24
Peak memory 219072 kb
Host smart-dc48264c-2d07-423f-941b-131be4c619f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160309580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3160309580
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1821702663
Short name T593
Test name
Test status
Simulation time 40096358 ps
CPU time 1.01 seconds
Started Jul 01 05:35:28 PM PDT 24
Finished Jul 01 05:35:30 PM PDT 24
Peak memory 207108 kb
Host smart-3c40cf2a-77d8-4c05-9d96-6e56f4042cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821702663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1821702663
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3553640857
Short name T401
Test name
Test status
Simulation time 85735158 ps
CPU time 1.08 seconds
Started Jul 01 05:35:30 PM PDT 24
Finished Jul 01 05:35:32 PM PDT 24
Peak memory 219004 kb
Host smart-c0f63d43-f582-4c07-9ff8-60b89d92e96b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553640857 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3553640857
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.146240785
Short name T8
Test name
Test status
Simulation time 19165920 ps
CPU time 1.18 seconds
Started Jul 01 05:35:29 PM PDT 24
Finished Jul 01 05:35:32 PM PDT 24
Peak memory 224224 kb
Host smart-de71cab8-48bf-4ef4-a414-6cdf1c50e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146240785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.146240785
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.506346289
Short name T559
Test name
Test status
Simulation time 48757094 ps
CPU time 2.01 seconds
Started Jul 01 05:35:22 PM PDT 24
Finished Jul 01 05:35:25 PM PDT 24
Peak memory 218840 kb
Host smart-62fb1d00-ef01-4c75-b432-0fa220b953f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506346289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.506346289
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4073081225
Short name T505
Test name
Test status
Simulation time 29184932 ps
CPU time 0.89 seconds
Started Jul 01 05:35:30 PM PDT 24
Finished Jul 01 05:35:32 PM PDT 24
Peak memory 215932 kb
Host smart-5fce2909-f5b9-4075-8987-fade57f4126c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073081225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4073081225
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3300059436
Short name T976
Test name
Test status
Simulation time 16869859 ps
CPU time 0.94 seconds
Started Jul 01 05:35:30 PM PDT 24
Finished Jul 01 05:35:31 PM PDT 24
Peak memory 207364 kb
Host smart-5c70cf87-1303-4c08-a64e-dc7ba0819f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300059436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3300059436
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.247928825
Short name T428
Test name
Test status
Simulation time 46739444 ps
CPU time 0.95 seconds
Started Jul 01 05:35:22 PM PDT 24
Finished Jul 01 05:35:23 PM PDT 24
Peak memory 215740 kb
Host smart-21eb31ee-a8ff-46e9-b493-e75775738193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247928825 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.247928825
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1463959697
Short name T243
Test name
Test status
Simulation time 83532272 ps
CPU time 2.02 seconds
Started Jul 01 05:35:21 PM PDT 24
Finished Jul 01 05:35:23 PM PDT 24
Peak memory 220536 kb
Host smart-b6c9bd6f-2667-4e3e-8cf1-fa23232b355b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463959697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1463959697
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2950253479
Short name T229
Test name
Test status
Simulation time 185708901788 ps
CPU time 1834.48 seconds
Started Jul 01 05:35:29 PM PDT 24
Finished Jul 01 06:06:04 PM PDT 24
Peak memory 226492 kb
Host smart-fd61c964-1735-4e17-b7cc-66fc305ddce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950253479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2950253479
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.910060159
Short name T329
Test name
Test status
Simulation time 84523968 ps
CPU time 1.09 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:55 PM PDT 24
Peak memory 220116 kb
Host smart-fb20b074-ea4b-4a3e-8ce6-c30e564105b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910060159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.910060159
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.199214246
Short name T245
Test name
Test status
Simulation time 34252711 ps
CPU time 1 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:54 PM PDT 24
Peak memory 207116 kb
Host smart-c9f85573-109a-424b-b84e-2bf658f745fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199214246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.199214246
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2369871981
Short name T891
Test name
Test status
Simulation time 16758402 ps
CPU time 0.81 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 216264 kb
Host smart-7415f72f-e005-47d0-8d7b-118861d92dc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369871981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2369871981
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3016511824
Short name T121
Test name
Test status
Simulation time 100655946 ps
CPU time 1 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:52 PM PDT 24
Peak memory 217116 kb
Host smart-90f92cc5-dbd8-4261-a6f7-45663499031f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016511824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3016511824
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1337449143
Short name T839
Test name
Test status
Simulation time 45701601 ps
CPU time 1 seconds
Started Jul 01 05:36:49 PM PDT 24
Finished Jul 01 05:36:51 PM PDT 24
Peak memory 229892 kb
Host smart-04c914b4-4ebf-42bc-b47f-e2856f7dd36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337449143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1337449143
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.3481211814
Short name T569
Test name
Test status
Simulation time 23616225 ps
CPU time 0.95 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 215936 kb
Host smart-d0eaaaf5-7886-48e4-ac44-6a889b8a86c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481211814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3481211814
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.56180761
Short name T344
Test name
Test status
Simulation time 15470235 ps
CPU time 0.98 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:54 PM PDT 24
Peak memory 215644 kb
Host smart-99f7d07c-956b-45eb-be7f-ae07497fbf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56180761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.56180761
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1569439113
Short name T917
Test name
Test status
Simulation time 3316741726 ps
CPU time 4.83 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:56 PM PDT 24
Peak memory 218068 kb
Host smart-fc1e4f0f-4050-42fe-943c-8036bf594245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569439113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1569439113
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2652728512
Short name T821
Test name
Test status
Simulation time 150606058133 ps
CPU time 1245.69 seconds
Started Jul 01 05:36:52 PM PDT 24
Finished Jul 01 05:57:40 PM PDT 24
Peak memory 223180 kb
Host smart-f2c1821a-6bc6-45fa-8104-72321911a92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652728512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2652728512
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1030221007
Short name T617
Test name
Test status
Simulation time 72198249 ps
CPU time 2.46 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:43 PM PDT 24
Peak memory 219208 kb
Host smart-5eca3d19-2dd7-436e-b891-784cf79e337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030221007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1030221007
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2760240408
Short name T581
Test name
Test status
Simulation time 103653402 ps
CPU time 1.04 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 217616 kb
Host smart-c1a1a415-33d7-45ea-9ce8-16e8ca0be128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760240408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2760240408
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3336981609
Short name T365
Test name
Test status
Simulation time 43771237 ps
CPU time 1.13 seconds
Started Jul 01 05:39:36 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 220272 kb
Host smart-7b3b8bd5-fc74-4b70-b2ff-19802d25c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336981609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3336981609
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.281322914
Short name T498
Test name
Test status
Simulation time 41240576 ps
CPU time 1.26 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 219016 kb
Host smart-89a0bacd-1eb0-4764-9ebd-ef066c57e33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281322914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.281322914
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.742412994
Short name T728
Test name
Test status
Simulation time 75896820 ps
CPU time 2.62 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:43 PM PDT 24
Peak memory 219976 kb
Host smart-ba54bed1-c64e-4f62-a3b6-39b921df2282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742412994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.742412994
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1827988990
Short name T480
Test name
Test status
Simulation time 44887189 ps
CPU time 1.54 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 220408 kb
Host smart-452e48ba-1cef-47d1-bb0f-3915ad2d4770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827988990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1827988990
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1384658360
Short name T975
Test name
Test status
Simulation time 52074308 ps
CPU time 1.46 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 217680 kb
Host smart-052e9572-4e2c-4047-b224-226a3311e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384658360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1384658360
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3757627557
Short name T802
Test name
Test status
Simulation time 23741204 ps
CPU time 1.09 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 217608 kb
Host smart-ce6e01d8-01df-49de-981f-efa80a9c29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757627557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3757627557
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1653839421
Short name T675
Test name
Test status
Simulation time 71973495 ps
CPU time 1.1 seconds
Started Jul 01 05:39:38 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 219980 kb
Host smart-a435160e-a7e7-42f9-873d-927cf390b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653839421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1653839421
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3846695019
Short name T495
Test name
Test status
Simulation time 204070310 ps
CPU time 1.24 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 217824 kb
Host smart-040262cd-f620-442a-8d0c-8a5ce6830c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846695019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3846695019
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4159923592
Short name T536
Test name
Test status
Simulation time 216023473 ps
CPU time 1.42 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 05:36:54 PM PDT 24
Peak memory 219332 kb
Host smart-7d6ded05-aae0-43c3-ba39-7b849b6a0723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159923592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4159923592
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3591572696
Short name T721
Test name
Test status
Simulation time 19885603 ps
CPU time 1.02 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:01 PM PDT 24
Peak memory 207100 kb
Host smart-5b4ba668-ede1-4696-9179-a4e20f077af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591572696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3591572696
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4210640274
Short name T496
Test name
Test status
Simulation time 10373275 ps
CPU time 0.85 seconds
Started Jul 01 05:36:57 PM PDT 24
Finished Jul 01 05:36:59 PM PDT 24
Peak memory 215728 kb
Host smart-8aa14088-108a-4060-8582-7cf582d7cf78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210640274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4210640274
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2138469897
Short name T595
Test name
Test status
Simulation time 29659341 ps
CPU time 1.17 seconds
Started Jul 01 05:36:59 PM PDT 24
Finished Jul 01 05:37:02 PM PDT 24
Peak memory 218524 kb
Host smart-5cec158b-7feb-4f66-bbf6-7007db0e0baf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138469897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2138469897
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.983790274
Short name T114
Test name
Test status
Simulation time 34619429 ps
CPU time 1.05 seconds
Started Jul 01 05:36:57 PM PDT 24
Finished Jul 01 05:36:59 PM PDT 24
Peak memory 230004 kb
Host smart-d9cddfc6-4a16-4b77-b85a-6345c4f482e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983790274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.983790274
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.821462378
Short name T527
Test name
Test status
Simulation time 73740531 ps
CPU time 1.05 seconds
Started Jul 01 05:36:49 PM PDT 24
Finished Jul 01 05:36:51 PM PDT 24
Peak memory 217720 kb
Host smart-8781a6a3-15b8-4d8c-a41d-7177f9aefff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821462378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.821462378
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4221216936
Short name T818
Test name
Test status
Simulation time 26101101 ps
CPU time 0.93 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 216224 kb
Host smart-73902a30-32e2-433b-9429-bd4ff1336fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221216936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4221216936
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4274727631
Short name T497
Test name
Test status
Simulation time 19452682 ps
CPU time 1.02 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 215640 kb
Host smart-8ed05118-9fe9-42cd-9ff9-5b68403cd3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274727631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4274727631
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1953217886
Short name T530
Test name
Test status
Simulation time 931314855 ps
CPU time 3.06 seconds
Started Jul 01 05:36:50 PM PDT 24
Finished Jul 01 05:36:55 PM PDT 24
Peak memory 217644 kb
Host smart-1db62492-6916-4347-8446-2acbf4b86ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953217886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1953217886
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3736177869
Short name T403
Test name
Test status
Simulation time 111751635926 ps
CPU time 2935.54 seconds
Started Jul 01 05:36:51 PM PDT 24
Finished Jul 01 06:25:49 PM PDT 24
Peak memory 234672 kb
Host smart-37ade8a9-6419-4b94-b5a9-9bd6227c7a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736177869 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3736177869
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3278385873
Short name T755
Test name
Test status
Simulation time 248095424 ps
CPU time 1.72 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 219284 kb
Host smart-97530ab7-eeb5-4db1-867d-5e6f647154fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278385873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3278385873
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1166318153
Short name T665
Test name
Test status
Simulation time 47844471 ps
CPU time 1.78 seconds
Started Jul 01 05:39:35 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 219120 kb
Host smart-4acf1aee-8900-4509-9250-3874c238b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166318153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1166318153
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.421061740
Short name T960
Test name
Test status
Simulation time 128379891 ps
CPU time 1.31 seconds
Started Jul 01 05:39:37 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 217576 kb
Host smart-824780bd-b25b-4e94-a516-3b7635c3499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421061740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.421061740
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3251631466
Short name T950
Test name
Test status
Simulation time 53897802 ps
CPU time 1.61 seconds
Started Jul 01 05:39:41 PM PDT 24
Finished Jul 01 05:39:44 PM PDT 24
Peak memory 219340 kb
Host smart-c6533470-eb47-40e2-8722-453d168c2dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251631466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3251631466
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.256919275
Short name T394
Test name
Test status
Simulation time 27129636 ps
CPU time 1.24 seconds
Started Jul 01 05:39:38 PM PDT 24
Finished Jul 01 05:39:42 PM PDT 24
Peak memory 217592 kb
Host smart-01e5bb81-65b7-4778-9e49-a3e7f1b82b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256919275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.256919275
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3147896846
Short name T890
Test name
Test status
Simulation time 64121327 ps
CPU time 1.56 seconds
Started Jul 01 05:39:38 PM PDT 24
Finished Jul 01 05:39:43 PM PDT 24
Peak memory 215656 kb
Host smart-4a06e04e-6ceb-4c60-ad9e-0da0ff2bb892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147896846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3147896846
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.588461039
Short name T64
Test name
Test status
Simulation time 37401474 ps
CPU time 1.27 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 220260 kb
Host smart-02f0dace-ce9c-4725-8597-952e270ac0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588461039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.588461039
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.645733003
Short name T327
Test name
Test status
Simulation time 139965754 ps
CPU time 1.11 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 217704 kb
Host smart-9615c5e4-a6cc-4893-af87-a967c840a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645733003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.645733003
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3025818664
Short name T827
Test name
Test status
Simulation time 26382848 ps
CPU time 1.22 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:47 PM PDT 24
Peak memory 217692 kb
Host smart-b5870832-3efa-434e-bd8d-5937b4c1b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025818664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3025818664
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4060080148
Short name T585
Test name
Test status
Simulation time 124668603 ps
CPU time 1.13 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 215728 kb
Host smart-578aa9b6-9e9d-4ad4-a42f-0e1e17ff851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060080148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4060080148
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2294826787
Short name T825
Test name
Test status
Simulation time 116107803 ps
CPU time 1.17 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:01 PM PDT 24
Peak memory 219140 kb
Host smart-7b113c3f-48bc-4318-8cfa-90eb404fa70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294826787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2294826787
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1119657963
Short name T899
Test name
Test status
Simulation time 79934155 ps
CPU time 1.14 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:01 PM PDT 24
Peak memory 207208 kb
Host smart-e58f24a4-9a30-432c-a58f-0d19f3d61d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119657963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1119657963
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.420382093
Short name T544
Test name
Test status
Simulation time 12277763 ps
CPU time 0.9 seconds
Started Jul 01 05:36:59 PM PDT 24
Finished Jul 01 05:37:02 PM PDT 24
Peak memory 216824 kb
Host smart-38e37386-e7d4-4628-aa46-8147f114b0d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420382093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.420382093
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3648895598
Short name T807
Test name
Test status
Simulation time 45845525 ps
CPU time 1.39 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 217320 kb
Host smart-3756de24-e11a-4bbb-96d8-8f13c45de911
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648895598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3648895598
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.1959712600
Short name T339
Test name
Test status
Simulation time 83009864 ps
CPU time 1.14 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 217696 kb
Host smart-38fcaaff-d6e0-4958-9602-ad55561a9126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959712600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1959712600
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2507942448
Short name T663
Test name
Test status
Simulation time 20429437 ps
CPU time 1.08 seconds
Started Jul 01 05:36:59 PM PDT 24
Finished Jul 01 05:37:02 PM PDT 24
Peak memory 215892 kb
Host smart-a5db47e7-8b43-4a63-b616-3f8e4fe21426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507942448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2507942448
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3410612338
Short name T385
Test name
Test status
Simulation time 26967168 ps
CPU time 0.94 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 215664 kb
Host smart-e138e5c3-d6d4-4d13-8ace-de13d6c44931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410612338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3410612338
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.393779860
Short name T693
Test name
Test status
Simulation time 452476205 ps
CPU time 2.91 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:02 PM PDT 24
Peak memory 217508 kb
Host smart-d844d756-60d7-4f11-844d-331d15d98577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393779860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.393779860
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3914259175
Short name T951
Test name
Test status
Simulation time 287001503290 ps
CPU time 1652.32 seconds
Started Jul 01 05:36:59 PM PDT 24
Finished Jul 01 06:04:33 PM PDT 24
Peak memory 225852 kb
Host smart-9cbc5e67-e368-4faf-af21-14cd205d4aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914259175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3914259175
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3932516226
Short name T690
Test name
Test status
Simulation time 37849057 ps
CPU time 1.65 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 217852 kb
Host smart-ee5b8113-393e-44be-9dd8-ba6bb5cae54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932516226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3932516226
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3312441786
Short name T654
Test name
Test status
Simulation time 141689060 ps
CPU time 3.05 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 220712 kb
Host smart-bda7c1d0-cd31-415f-981d-a0d494d7fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312441786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3312441786
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.837145007
Short name T84
Test name
Test status
Simulation time 47993299 ps
CPU time 1.65 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 217648 kb
Host smart-bdd56199-c0ce-49d4-8075-e60df4fed084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837145007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.837145007
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1145969124
Short name T901
Test name
Test status
Simulation time 80794384 ps
CPU time 1.38 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 219336 kb
Host smart-ebc09fb7-4016-4a01-bbe4-d8cbd46ffa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145969124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1145969124
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4024121131
Short name T700
Test name
Test status
Simulation time 176636312 ps
CPU time 3.04 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 219256 kb
Host smart-11540d1c-cb81-48dd-8411-fbb6dd8a7d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024121131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4024121131
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2783224067
Short name T302
Test name
Test status
Simulation time 84217127 ps
CPU time 1.29 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:47 PM PDT 24
Peak memory 219960 kb
Host smart-eabdd4e1-18d7-4741-97e1-82095bb235ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783224067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2783224067
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.575290534
Short name T635
Test name
Test status
Simulation time 54513567 ps
CPU time 1.18 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 217528 kb
Host smart-3b9032f9-7e57-4657-9d27-86d6a7154ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575290534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.575290534
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3517715674
Short name T798
Test name
Test status
Simulation time 34893859 ps
CPU time 1.2 seconds
Started Jul 01 05:39:45 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 215564 kb
Host smart-ea168c4e-0501-4b2b-bca4-27e1304ee441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517715674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3517715674
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1273025419
Short name T881
Test name
Test status
Simulation time 110126618 ps
CPU time 1.25 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 217752 kb
Host smart-04475261-0a5e-40fa-98b9-67b23f9ceb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273025419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1273025419
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2059851334
Short name T591
Test name
Test status
Simulation time 70407849 ps
CPU time 1.12 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 220180 kb
Host smart-16d67bef-4737-48da-881b-9491992f2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059851334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2059851334
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2563710419
Short name T487
Test name
Test status
Simulation time 39525016 ps
CPU time 0.87 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:07 PM PDT 24
Peak memory 215052 kb
Host smart-45650bfd-bb73-46eb-9268-37441d633c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563710419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2563710419
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2697086635
Short name T168
Test name
Test status
Simulation time 102393344 ps
CPU time 0.85 seconds
Started Jul 01 05:37:09 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 216580 kb
Host smart-98301041-8cc4-4069-9226-a4ddb64a777a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697086635 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2697086635
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3487273421
Short name T678
Test name
Test status
Simulation time 60294468 ps
CPU time 1.16 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 216064 kb
Host smart-e05c22a0-5218-4723-bae3-c93a05ba6717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487273421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3487273421
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.329588875
Short name T611
Test name
Test status
Simulation time 45617714 ps
CPU time 1.26 seconds
Started Jul 01 05:37:04 PM PDT 24
Finished Jul 01 05:37:06 PM PDT 24
Peak memory 225768 kb
Host smart-a82e04a1-a436-4f34-9be4-afb3e54c31da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329588875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.329588875
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.447020379
Short name T376
Test name
Test status
Simulation time 41649931 ps
CPU time 1.06 seconds
Started Jul 01 05:36:57 PM PDT 24
Finished Jul 01 05:36:59 PM PDT 24
Peak memory 215628 kb
Host smart-36433eb9-3176-46e0-992e-9ea0075d48db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447020379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.447020379
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3627103169
Short name T696
Test name
Test status
Simulation time 28350242 ps
CPU time 0.97 seconds
Started Jul 01 05:37:04 PM PDT 24
Finished Jul 01 05:37:06 PM PDT 24
Peak memory 215868 kb
Host smart-ea3450c3-6031-4442-8f14-c11e525a343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627103169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3627103169
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4122458567
Short name T491
Test name
Test status
Simulation time 26588326 ps
CPU time 0.92 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 215712 kb
Host smart-8ef86058-5e81-4b81-bb8e-ae762c258a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122458567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4122458567
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3041156014
Short name T467
Test name
Test status
Simulation time 2954540653 ps
CPU time 5.65 seconds
Started Jul 01 05:36:58 PM PDT 24
Finished Jul 01 05:37:05 PM PDT 24
Peak memory 215732 kb
Host smart-058d2e5a-06db-4803-8e51-1789b35dae43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041156014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3041156014
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2556194229
Short name T838
Test name
Test status
Simulation time 5705220569 ps
CPU time 121.07 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 220724 kb
Host smart-7da0d827-903d-4539-b10b-890c7525f5f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556194229 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2556194229
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3352969459
Short name T927
Test name
Test status
Simulation time 43217734 ps
CPU time 1.35 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 217776 kb
Host smart-2d37c9bc-7d5a-45e0-9e38-d3cdb81ca204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352969459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3352969459
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1268643935
Short name T615
Test name
Test status
Simulation time 23691206 ps
CPU time 1.2 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 217668 kb
Host smart-56b7f48e-55d7-47b9-ab44-0a64ad2f6ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268643935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1268643935
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4066948686
Short name T873
Test name
Test status
Simulation time 39762194 ps
CPU time 1.58 seconds
Started Jul 01 05:39:46 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 217940 kb
Host smart-360f7dda-040c-43f1-bdff-3a49b49f2410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066948686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4066948686
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.920295456
Short name T565
Test name
Test status
Simulation time 67536320 ps
CPU time 1.57 seconds
Started Jul 01 05:39:45 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 218624 kb
Host smart-d4f705b4-f1c8-4795-9332-71ff6ad20cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920295456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.920295456
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3078018703
Short name T433
Test name
Test status
Simulation time 38506885 ps
CPU time 1.4 seconds
Started Jul 01 05:39:42 PM PDT 24
Finished Jul 01 05:39:45 PM PDT 24
Peak memory 217740 kb
Host smart-150ca89e-a1f8-4e6c-b681-b88dfb39af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078018703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3078018703
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3114765321
Short name T547
Test name
Test status
Simulation time 79325171 ps
CPU time 2.93 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 220628 kb
Host smart-46392434-ae87-4bdd-88f3-8a6c5c42c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114765321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3114765321
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3886997127
Short name T337
Test name
Test status
Simulation time 64522077 ps
CPU time 1.12 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 220240 kb
Host smart-ea53d03e-f716-40d1-b393-cc2376759b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886997127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3886997127
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2013355018
Short name T509
Test name
Test status
Simulation time 45422628 ps
CPU time 1.11 seconds
Started Jul 01 05:39:41 PM PDT 24
Finished Jul 01 05:39:44 PM PDT 24
Peak memory 219908 kb
Host smart-0f248b79-3fe6-4370-96d5-a3397c89a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013355018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2013355018
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3096169328
Short name T415
Test name
Test status
Simulation time 46715860 ps
CPU time 1.56 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:47 PM PDT 24
Peak memory 220080 kb
Host smart-6213350c-1715-47c3-b9f1-86ceaa078748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096169328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3096169328
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3787259911
Short name T538
Test name
Test status
Simulation time 37882894 ps
CPU time 1.27 seconds
Started Jul 01 05:39:43 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 217744 kb
Host smart-19edef22-b2ff-4bdc-8b74-b22776a9975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787259911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3787259911
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.4667834
Short name T719
Test name
Test status
Simulation time 45019302 ps
CPU time 0.86 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:07 PM PDT 24
Peak memory 215296 kb
Host smart-b7e60c95-a3cd-4c14-98b3-0006f7233f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4667834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4667834
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3326754631
Short name T980
Test name
Test status
Simulation time 12943658 ps
CPU time 0.87 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 216232 kb
Host smart-9232fc02-8990-4cc1-9596-fda905720617
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326754631 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3326754631
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.3911874357
Short name T824
Test name
Test status
Simulation time 85759894 ps
CPU time 0.96 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 218892 kb
Host smart-23bbf061-8403-4f15-8876-cd08bce90c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911874357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3911874357
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.699861485
Short name T877
Test name
Test status
Simulation time 50966407 ps
CPU time 1.61 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 219044 kb
Host smart-cf51ade2-0340-455e-94dc-10fff836db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699861485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.699861485
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.45727219
Short name T37
Test name
Test status
Simulation time 92028660 ps
CPU time 0.89 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:07 PM PDT 24
Peak memory 215564 kb
Host smart-b9ea2f14-bf5e-4f5e-8a4b-d937c40629d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45727219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.45727219
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.230500496
Short name T350
Test name
Test status
Simulation time 14823227 ps
CPU time 0.92 seconds
Started Jul 01 05:37:03 PM PDT 24
Finished Jul 01 05:37:05 PM PDT 24
Peak memory 215696 kb
Host smart-3658c998-77ef-4789-a37f-9739efa24c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230500496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.230500496
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1775898265
Short name T621
Test name
Test status
Simulation time 153249371 ps
CPU time 2.26 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 219972 kb
Host smart-a4b31545-7cc6-4d85-b754-6423d4cbbae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775898265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1775898265
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1690436331
Short name T606
Test name
Test status
Simulation time 33133058702 ps
CPU time 562.08 seconds
Started Jul 01 05:37:09 PM PDT 24
Finished Jul 01 05:46:32 PM PDT 24
Peak memory 217220 kb
Host smart-e51e518a-b1cc-4863-8dcc-1c00f5e2c85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690436331 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1690436331
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2990138080
Short name T956
Test name
Test status
Simulation time 151021965 ps
CPU time 1.22 seconds
Started Jul 01 05:39:44 PM PDT 24
Finished Jul 01 05:39:48 PM PDT 24
Peak memory 218800 kb
Host smart-b5835e4f-8297-4e2c-8dc8-2f09110b6427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990138080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2990138080
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3569295452
Short name T249
Test name
Test status
Simulation time 98578441 ps
CPU time 1.62 seconds
Started Jul 01 05:39:46 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 219300 kb
Host smart-25e50f09-3635-4ab3-937e-6cdc41f8e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569295452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3569295452
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1351941041
Short name T932
Test name
Test status
Simulation time 77264084 ps
CPU time 1.65 seconds
Started Jul 01 05:39:46 PM PDT 24
Finished Jul 01 05:39:49 PM PDT 24
Peak memory 220260 kb
Host smart-32c65d24-7f6a-49ef-b296-6b601f7f987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351941041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1351941041
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2691729545
Short name T293
Test name
Test status
Simulation time 42850145 ps
CPU time 1.75 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 218832 kb
Host smart-02962c54-7a76-4774-80b8-907083f22f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691729545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2691729545
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.465748018
Short name T630
Test name
Test status
Simulation time 103769994 ps
CPU time 1.7 seconds
Started Jul 01 05:39:53 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 218932 kb
Host smart-161d95a9-941b-497a-bbb9-887dfd0fb92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465748018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.465748018
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2782663586
Short name T903
Test name
Test status
Simulation time 32996768 ps
CPU time 1.28 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 219304 kb
Host smart-014d6347-ebb2-4439-ab6c-327b5e261f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782663586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2782663586
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1408076888
Short name T605
Test name
Test status
Simulation time 37799944 ps
CPU time 1.71 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 219264 kb
Host smart-9d0d8756-781a-4b4c-a27c-9ce6853446c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408076888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1408076888
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2527168875
Short name T870
Test name
Test status
Simulation time 71474087 ps
CPU time 1.27 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 220336 kb
Host smart-f783d28f-8ee2-46c2-be3a-1f34297f79c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527168875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2527168875
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1857816502
Short name T352
Test name
Test status
Simulation time 242871976 ps
CPU time 3.57 seconds
Started Jul 01 05:39:49 PM PDT 24
Finished Jul 01 05:39:53 PM PDT 24
Peak memory 220584 kb
Host smart-7d1e54b8-2751-4465-8deb-1e7921a8e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857816502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1857816502
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3476338199
Short name T636
Test name
Test status
Simulation time 82387116 ps
CPU time 1.22 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 219076 kb
Host smart-bd2fe41d-92a3-4207-8af6-4317b35c9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476338199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3476338199
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.113581865
Short name T471
Test name
Test status
Simulation time 91766556 ps
CPU time 1.17 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 219856 kb
Host smart-28407144-0545-4641-a89d-3f66424670be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113581865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.113581865
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2559005590
Short name T953
Test name
Test status
Simulation time 30641846 ps
CPU time 0.78 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 206700 kb
Host smart-795ec2e9-0bce-4819-9228-99190af2a2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559005590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2559005590
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.124814242
Short name T576
Test name
Test status
Simulation time 39137011 ps
CPU time 0.85 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 215740 kb
Host smart-807f3d20-5084-43e8-85ce-7c014db8a5f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124814242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.124814242
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.598399688
Short name T806
Test name
Test status
Simulation time 460489382 ps
CPU time 1.11 seconds
Started Jul 01 05:37:07 PM PDT 24
Finished Jul 01 05:37:10 PM PDT 24
Peak memory 217800 kb
Host smart-bc60faa8-d1a0-45f3-9281-71d89ba0e5ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598399688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.598399688
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.565647047
Short name T165
Test name
Test status
Simulation time 21305209 ps
CPU time 0.91 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 218780 kb
Host smart-e40a7dc2-ff56-4513-83f0-f4aa6b9588ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565647047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.565647047
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1705875990
Short name T652
Test name
Test status
Simulation time 37556652 ps
CPU time 1.05 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 218796 kb
Host smart-360c62ec-911c-4a9e-969f-d93ec224f813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705875990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1705875990
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.310737346
Short name T657
Test name
Test status
Simulation time 47580138 ps
CPU time 0.84 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 215580 kb
Host smart-1d2fa251-369d-4c36-8943-3a8a5dcd900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310737346 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.310737346
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1945513059
Short name T554
Test name
Test status
Simulation time 57998602 ps
CPU time 0.89 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 215696 kb
Host smart-0c841e56-77cd-4b6d-9b6f-d4b621071c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945513059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1945513059
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1153704713
Short name T250
Test name
Test status
Simulation time 104437145 ps
CPU time 2.51 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 217668 kb
Host smart-ab2174d1-ceb8-4780-8d24-ebf5a68a42ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153704713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1153704713
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2922583896
Short name T990
Test name
Test status
Simulation time 425621894926 ps
CPU time 1312.1 seconds
Started Jul 01 05:37:04 PM PDT 24
Finished Jul 01 05:58:57 PM PDT 24
Peak memory 225084 kb
Host smart-c9ec13a5-47a0-445b-a901-7426152d9162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922583896 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2922583896
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3827455389
Short name T959
Test name
Test status
Simulation time 58645938 ps
CPU time 1.47 seconds
Started Jul 01 05:39:55 PM PDT 24
Finished Jul 01 05:39:59 PM PDT 24
Peak memory 219140 kb
Host smart-14042bb3-c6d9-41b8-a0ad-111693f70d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827455389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3827455389
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4284042744
Short name T875
Test name
Test status
Simulation time 24774291 ps
CPU time 1.16 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 217724 kb
Host smart-38f2f8ed-91c0-415e-9ce3-7608de485d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284042744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4284042744
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.580400358
Short name T632
Test name
Test status
Simulation time 63175814 ps
CPU time 1.27 seconds
Started Jul 01 05:39:53 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 219148 kb
Host smart-e22bb1b3-0950-4fff-b676-bed3af74f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580400358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.580400358
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3798173718
Short name T321
Test name
Test status
Simulation time 213386994 ps
CPU time 1.2 seconds
Started Jul 01 05:39:55 PM PDT 24
Finished Jul 01 05:39:59 PM PDT 24
Peak memory 220508 kb
Host smart-f8a90ba9-4006-4f89-8245-f8f87047c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798173718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3798173718
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3890568794
Short name T532
Test name
Test status
Simulation time 77951315 ps
CPU time 2.15 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 218096 kb
Host smart-d0d542db-df57-43af-9c28-853701957026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890568794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3890568794
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2538207033
Short name T796
Test name
Test status
Simulation time 55185488 ps
CPU time 1.46 seconds
Started Jul 01 05:39:54 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 219112 kb
Host smart-0c9ff349-5ab7-4004-b4a5-0623dacedff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538207033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2538207033
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2530226271
Short name T832
Test name
Test status
Simulation time 38024204 ps
CPU time 1.35 seconds
Started Jul 01 05:39:49 PM PDT 24
Finished Jul 01 05:39:52 PM PDT 24
Peak memory 220236 kb
Host smart-f74781ba-223e-44b9-aa0c-3c03dd93b55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530226271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2530226271
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1128088662
Short name T70
Test name
Test status
Simulation time 44602944 ps
CPU time 1.54 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 218916 kb
Host smart-ddd948ac-a6f8-4129-aba5-28e793ef6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128088662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1128088662
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2394578008
Short name T27
Test name
Test status
Simulation time 62659957 ps
CPU time 1.12 seconds
Started Jul 01 05:39:49 PM PDT 24
Finished Jul 01 05:39:52 PM PDT 24
Peak memory 219040 kb
Host smart-e8ea220f-dc6d-47df-9565-b7dcad7c3447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394578008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2394578008
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.722312622
Short name T311
Test name
Test status
Simulation time 148065804 ps
CPU time 2.15 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:55 PM PDT 24
Peak memory 220572 kb
Host smart-bf874298-aa29-4a4f-a25b-fb4d53d683d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722312622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.722312622
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.593623681
Short name T2
Test name
Test status
Simulation time 28144322 ps
CPU time 1.23 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 219860 kb
Host smart-57328f27-b505-435f-81e1-aadfc2a2c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593623681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.593623681
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3497972299
Short name T894
Test name
Test status
Simulation time 15092539 ps
CPU time 0.85 seconds
Started Jul 01 05:37:12 PM PDT 24
Finished Jul 01 05:37:14 PM PDT 24
Peak memory 207192 kb
Host smart-4100aa59-f0ca-4d8a-98c7-fc758903a7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497972299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3497972299
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4292403554
Short name T897
Test name
Test status
Simulation time 52886443 ps
CPU time 1.13 seconds
Started Jul 01 05:37:15 PM PDT 24
Finished Jul 01 05:37:18 PM PDT 24
Peak memory 217396 kb
Host smart-0a475bc6-d357-4062-bdd8-483219b81995
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292403554 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4292403554
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2173658786
Short name T174
Test name
Test status
Simulation time 28397713 ps
CPU time 0.88 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 218600 kb
Host smart-78a0febd-bf67-4f1b-b209-6ba8081f4cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173658786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2173658786
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.383518001
Short name T599
Test name
Test status
Simulation time 767047873 ps
CPU time 6.65 seconds
Started Jul 01 05:37:05 PM PDT 24
Finished Jul 01 05:37:14 PM PDT 24
Peak memory 220700 kb
Host smart-b17c783b-7399-401a-b951-ecc1d23dbee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383518001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.383518001
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2684333078
Short name T481
Test name
Test status
Simulation time 47163722 ps
CPU time 0.89 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 215572 kb
Host smart-7bac4481-2981-4a79-9a78-1ba0b16b590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684333078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2684333078
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.171111339
Short name T938
Test name
Test status
Simulation time 29321768 ps
CPU time 0.99 seconds
Started Jul 01 05:37:06 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 215644 kb
Host smart-c17d9afe-0917-4cfc-8aff-1c8990c44c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171111339 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.171111339
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4041215855
Short name T834
Test name
Test status
Simulation time 202883152 ps
CPU time 1.11 seconds
Started Jul 01 05:37:08 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 217552 kb
Host smart-d44aea9d-9b31-464d-b14f-0b10d35193cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041215855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4041215855
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1554430195
Short name T865
Test name
Test status
Simulation time 25203516604 ps
CPU time 651.2 seconds
Started Jul 01 05:37:07 PM PDT 24
Finished Jul 01 05:48:01 PM PDT 24
Peak memory 224160 kb
Host smart-ec50bd3d-fe36-4992-9022-b67205777ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554430195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1554430195
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.56660845
Short name T308
Test name
Test status
Simulation time 38140967 ps
CPU time 1.43 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:53 PM PDT 24
Peak memory 219008 kb
Host smart-4e9e78bf-27ad-434e-b8eb-d0c26cea3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56660845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.56660845
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3835438661
Short name T575
Test name
Test status
Simulation time 192729485 ps
CPU time 2.19 seconds
Started Jul 01 05:39:55 PM PDT 24
Finished Jul 01 05:40:00 PM PDT 24
Peak memory 220372 kb
Host smart-952c7464-9b82-413f-b438-d77ee90b4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835438661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3835438661
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3218525170
Short name T828
Test name
Test status
Simulation time 51297966 ps
CPU time 1.26 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:53 PM PDT 24
Peak memory 219708 kb
Host smart-e6a5b165-ff2e-429c-bee4-289e0388ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218525170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3218525170
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1558791221
Short name T988
Test name
Test status
Simulation time 41708540 ps
CPU time 1.3 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 220184 kb
Host smart-8608f890-c5c6-47ec-b43c-acbd028eaab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558791221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1558791221
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.943075856
Short name T465
Test name
Test status
Simulation time 53953684 ps
CPU time 1.4 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:55 PM PDT 24
Peak memory 218736 kb
Host smart-39eb0c05-5343-4498-928f-9cc9efcbbfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943075856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.943075856
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2219796865
Short name T422
Test name
Test status
Simulation time 69013639 ps
CPU time 1.49 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:53 PM PDT 24
Peak memory 218032 kb
Host smart-d7ba9af8-c3e1-4606-8625-f08eb7c068c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219796865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2219796865
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.558071843
Short name T724
Test name
Test status
Simulation time 233969318 ps
CPU time 1.57 seconds
Started Jul 01 05:39:53 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 219288 kb
Host smart-23cac06d-0ddf-4542-892e-42c49612a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558071843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.558071843
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3747734909
Short name T658
Test name
Test status
Simulation time 51789121 ps
CPU time 1.23 seconds
Started Jul 01 05:39:53 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 217648 kb
Host smart-85f9086b-c408-4770-bfaa-2e053d934b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747734909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3747734909
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2362357232
Short name T701
Test name
Test status
Simulation time 33294266 ps
CPU time 1.28 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 215628 kb
Host smart-90c31f01-024c-48ca-b7f7-9b419e5e0616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362357232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2362357232
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.168469673
Short name T895
Test name
Test status
Simulation time 45546954 ps
CPU time 1.44 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:55 PM PDT 24
Peak memory 217592 kb
Host smart-91be4009-3af0-4a44-9fd2-76a3c445eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168469673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.168469673
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1954938693
Short name T634
Test name
Test status
Simulation time 42717970 ps
CPU time 1.1 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 221024 kb
Host smart-0849e3f6-c886-4fec-99c9-6913ac9c1c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954938693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1954938693
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.434777355
Short name T637
Test name
Test status
Simulation time 27876212 ps
CPU time 0.79 seconds
Started Jul 01 05:37:14 PM PDT 24
Finished Jul 01 05:37:18 PM PDT 24
Peak memory 206448 kb
Host smart-efb11bb3-731c-4e88-a4d0-f5fe39791454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434777355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.434777355
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.670522461
Short name T204
Test name
Test status
Simulation time 12130642 ps
CPU time 0.88 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 216836 kb
Host smart-85b41738-5db7-463b-aa23-85de05fde8a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670522461 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.670522461
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4230327461
Short name T117
Test name
Test status
Simulation time 47140311 ps
CPU time 1.06 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:37:13 PM PDT 24
Peak memory 217404 kb
Host smart-80252a45-6a95-4953-bd6d-3997a0a0935e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230327461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4230327461
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.61076820
Short name T111
Test name
Test status
Simulation time 90991642 ps
CPU time 0.9 seconds
Started Jul 01 05:37:10 PM PDT 24
Finished Jul 01 05:37:13 PM PDT 24
Peak memory 219880 kb
Host smart-9a4e5ef2-c88b-4420-8cb3-62271133fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61076820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.61076820
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1751480590
Short name T598
Test name
Test status
Simulation time 109536172 ps
CPU time 1.28 seconds
Started Jul 01 05:37:16 PM PDT 24
Finished Jul 01 05:37:19 PM PDT 24
Peak memory 220264 kb
Host smart-cc2ec38d-938b-4fc3-a87c-1d8fb2bce29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751480590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1751480590
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3000169315
Short name T240
Test name
Test status
Simulation time 42488894 ps
CPU time 0.9 seconds
Started Jul 01 05:37:14 PM PDT 24
Finished Jul 01 05:37:18 PM PDT 24
Peak memory 215684 kb
Host smart-5a5cbe87-e513-4676-a348-b151b5243e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000169315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3000169315
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.92259223
Short name T769
Test name
Test status
Simulation time 27422193 ps
CPU time 0.91 seconds
Started Jul 01 05:37:10 PM PDT 24
Finished Jul 01 05:37:13 PM PDT 24
Peak memory 215584 kb
Host smart-cd61051f-f2e8-4031-8cdf-fbdfff984e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92259223 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.92259223
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3688570198
Short name T923
Test name
Test status
Simulation time 470004186 ps
CPU time 1.69 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:37:14 PM PDT 24
Peak memory 217528 kb
Host smart-beeb7055-9296-40ac-bf34-80eeb5132509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688570198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3688570198
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.2539357149
Short name T780
Test name
Test status
Simulation time 87621733 ps
CPU time 1.36 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 218844 kb
Host smart-f96a6f92-1a86-4108-becd-95974c621646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539357149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2539357149
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3265164399
Short name T727
Test name
Test status
Simulation time 61390080 ps
CPU time 2.38 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 220464 kb
Host smart-2918e356-3c65-4eee-a6fa-bd6800a0eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265164399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3265164399
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.489368088
Short name T348
Test name
Test status
Simulation time 63529059 ps
CPU time 1.48 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 219360 kb
Host smart-b373dd31-e0ad-4d44-9c2a-db1732390f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489368088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.489368088
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1357809683
Short name T556
Test name
Test status
Simulation time 44063657 ps
CPU time 1.67 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 218940 kb
Host smart-126569c3-61f9-4ada-bf5b-df6d53989dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357809683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1357809683
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1979597269
Short name T88
Test name
Test status
Simulation time 41894703 ps
CPU time 1.25 seconds
Started Jul 01 05:39:54 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 219000 kb
Host smart-9109ca2f-cb49-4e90-8452-3c33c83e38e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979597269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1979597269
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2372075631
Short name T341
Test name
Test status
Simulation time 140674316 ps
CPU time 3.16 seconds
Started Jul 01 05:39:51 PM PDT 24
Finished Jul 01 05:39:57 PM PDT 24
Peak memory 220304 kb
Host smart-9e7c02e1-6e32-4ed8-a297-66fc1e3f35f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372075631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2372075631
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4258699273
Short name T345
Test name
Test status
Simulation time 51862894 ps
CPU time 1.64 seconds
Started Jul 01 05:39:49 PM PDT 24
Finished Jul 01 05:39:52 PM PDT 24
Peak memory 218776 kb
Host smart-4ad83969-7023-4569-ba84-f34ee94f2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258699273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4258699273
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.702233778
Short name T47
Test name
Test status
Simulation time 42236194 ps
CPU time 1.22 seconds
Started Jul 01 05:39:52 PM PDT 24
Finished Jul 01 05:39:56 PM PDT 24
Peak memory 217532 kb
Host smart-e3c94961-5484-4272-ba0c-3c4591d13078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702233778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.702233778
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1105151035
Short name T10
Test name
Test status
Simulation time 31697746 ps
CPU time 1.31 seconds
Started Jul 01 05:39:53 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 220296 kb
Host smart-5023033e-8903-4f7c-b264-ee7eebd052be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105151035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1105151035
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2305655393
Short name T351
Test name
Test status
Simulation time 247313156 ps
CPU time 1.22 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:53 PM PDT 24
Peak memory 217648 kb
Host smart-318336b0-f35e-4ac2-91e9-38457995a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305655393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2305655393
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2947414681
Short name T179
Test name
Test status
Simulation time 36356173 ps
CPU time 1.01 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 219908 kb
Host smart-9957e22a-8640-4cb5-ab5b-d90a1de6817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947414681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2947414681
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4117295059
Short name T377
Test name
Test status
Simulation time 16515498 ps
CPU time 0.91 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:37:13 PM PDT 24
Peak memory 207016 kb
Host smart-0cd73a68-be7c-42c6-b897-b059ebbc31f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117295059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4117295059
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1530224044
Short name T176
Test name
Test status
Simulation time 29685510 ps
CPU time 0.84 seconds
Started Jul 01 05:37:14 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 216708 kb
Host smart-4c16d70f-6b7d-47ee-b75c-23d841568754
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530224044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1530224044
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.418732901
Short name T686
Test name
Test status
Simulation time 96139123 ps
CPU time 1.1 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:37:13 PM PDT 24
Peak memory 219880 kb
Host smart-630fb049-158b-493f-8102-bfa375f0d440
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418732901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.418732901
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3318850980
Short name T715
Test name
Test status
Simulation time 53448200 ps
CPU time 1.03 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:37:14 PM PDT 24
Peak memory 219988 kb
Host smart-62631903-d0ba-4ebc-a233-e902c8d1eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318850980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3318850980
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2528562218
Short name T820
Test name
Test status
Simulation time 113214974 ps
CPU time 1.17 seconds
Started Jul 01 05:37:12 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 217608 kb
Host smart-e7a8de74-d70d-4c5d-a2f5-ed13965aed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528562218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2528562218
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.738735596
Short name T101
Test name
Test status
Simulation time 22993750 ps
CPU time 0.97 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 216036 kb
Host smart-ce6a851a-dcb1-402b-89af-58479203d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738735596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.738735596
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3628873843
Short name T515
Test name
Test status
Simulation time 95716798 ps
CPU time 0.87 seconds
Started Jul 01 05:37:12 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 215448 kb
Host smart-e98264d6-f990-49fd-821b-dd5506b074aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628873843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3628873843
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1698838275
Short name T6
Test name
Test status
Simulation time 118693762 ps
CPU time 1.23 seconds
Started Jul 01 05:37:15 PM PDT 24
Finished Jul 01 05:37:19 PM PDT 24
Peak memory 206964 kb
Host smart-df6ab02a-07a5-40c7-abc3-12a5f580d711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698838275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1698838275
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.148698429
Short name T437
Test name
Test status
Simulation time 187667510571 ps
CPU time 878.25 seconds
Started Jul 01 05:37:12 PM PDT 24
Finished Jul 01 05:51:52 PM PDT 24
Peak memory 224068 kb
Host smart-8d9a860b-f3f9-4c8d-95cc-463de0752a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148698429 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.148698429
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1277123181
Short name T374
Test name
Test status
Simulation time 26382922 ps
CPU time 1.25 seconds
Started Jul 01 05:39:54 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 218968 kb
Host smart-0a9f96fa-c976-43ca-a26d-68881b602e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277123181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1277123181
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1646295583
Short name T816
Test name
Test status
Simulation time 48215996 ps
CPU time 1.29 seconds
Started Jul 01 05:39:50 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 217784 kb
Host smart-83c3bcc6-d57f-4a7a-82f1-742cc6c3489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646295583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1646295583
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1446560341
Short name T704
Test name
Test status
Simulation time 129912752 ps
CPU time 1.44 seconds
Started Jul 01 05:39:54 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 219420 kb
Host smart-899d944b-3a1d-4a7c-bea8-d0cb87285652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446560341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1446560341
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1639274036
Short name T292
Test name
Test status
Simulation time 52795115 ps
CPU time 1.63 seconds
Started Jul 01 05:39:57 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 218616 kb
Host smart-7c1e4931-5688-4cfb-bd61-be7c6706346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639274036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1639274036
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3641837269
Short name T642
Test name
Test status
Simulation time 62975325 ps
CPU time 1.17 seconds
Started Jul 01 05:39:58 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 217536 kb
Host smart-ef0c15e8-e584-4a00-aec8-f387936bc688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641837269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3641837269
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3653416738
Short name T523
Test name
Test status
Simulation time 43436638 ps
CPU time 1.76 seconds
Started Jul 01 05:39:59 PM PDT 24
Finished Jul 01 05:40:04 PM PDT 24
Peak memory 219156 kb
Host smart-f7240730-8222-4585-bf7b-207de63357ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653416738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3653416738
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.856904320
Short name T552
Test name
Test status
Simulation time 217813708 ps
CPU time 1.16 seconds
Started Jul 01 05:39:57 PM PDT 24
Finished Jul 01 05:40:01 PM PDT 24
Peak memory 217668 kb
Host smart-b2cfbc7a-922a-4048-80ff-bb3ea124109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856904320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.856904320
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3859497205
Short name T426
Test name
Test status
Simulation time 56354831 ps
CPU time 1.36 seconds
Started Jul 01 05:39:56 PM PDT 24
Finished Jul 01 05:40:00 PM PDT 24
Peak memory 218812 kb
Host smart-2b43d15e-6a98-4553-8645-4d562069e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859497205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3859497205
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.561073507
Short name T323
Test name
Test status
Simulation time 42582992 ps
CPU time 1.13 seconds
Started Jul 01 05:39:59 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 217752 kb
Host smart-d37718f7-3c1b-4841-b8c9-2de90c817adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561073507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.561073507
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.636418176
Short name T703
Test name
Test status
Simulation time 40073706 ps
CPU time 1.11 seconds
Started Jul 01 05:37:19 PM PDT 24
Finished Jul 01 05:37:21 PM PDT 24
Peak memory 219112 kb
Host smart-6110fb98-f54a-4d99-99db-2b91c83881b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636418176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.636418176
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.355127564
Short name T886
Test name
Test status
Simulation time 29038588 ps
CPU time 0.84 seconds
Started Jul 01 05:37:18 PM PDT 24
Finished Jul 01 05:37:20 PM PDT 24
Peak memory 207064 kb
Host smart-9b84528c-9020-4613-9bf6-1a3c1819d547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355127564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.355127564
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4055223123
Short name T224
Test name
Test status
Simulation time 12990117 ps
CPU time 0.9 seconds
Started Jul 01 05:37:20 PM PDT 24
Finished Jul 01 05:37:21 PM PDT 24
Peak memory 215908 kb
Host smart-9526bf5d-8f3f-4538-a77e-45dee63bd6b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055223123 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4055223123
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1630707794
Short name T423
Test name
Test status
Simulation time 31920191 ps
CPU time 1.05 seconds
Started Jul 01 05:37:20 PM PDT 24
Finished Jul 01 05:37:22 PM PDT 24
Peak memory 219980 kb
Host smart-6960487c-f8b1-4107-a26e-673b68887d09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630707794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1630707794
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.329085667
Short name T459
Test name
Test status
Simulation time 46936393 ps
CPU time 0.97 seconds
Started Jul 01 05:37:20 PM PDT 24
Finished Jul 01 05:37:22 PM PDT 24
Peak memory 218912 kb
Host smart-7c6d5996-7aab-4803-b244-62f6d841350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329085667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.329085667
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.848482824
Short name T770
Test name
Test status
Simulation time 31214680 ps
CPU time 1.37 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 220032 kb
Host smart-31bbec04-98fc-4cbf-bd25-7689c909cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848482824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.848482824
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.623839709
Short name T916
Test name
Test status
Simulation time 27488894 ps
CPU time 0.93 seconds
Started Jul 01 05:37:13 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 215644 kb
Host smart-fb819055-abda-4ab4-90f2-ce50c8d89dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623839709 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.623839709
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1950652605
Short name T246
Test name
Test status
Simulation time 205928429 ps
CPU time 1.68 seconds
Started Jul 01 05:37:16 PM PDT 24
Finished Jul 01 05:37:19 PM PDT 24
Peak memory 217720 kb
Host smart-5a46bba7-7fe1-4bf3-9e46-41b176d94e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950652605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1950652605
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1847955986
Short name T857
Test name
Test status
Simulation time 451125655346 ps
CPU time 999.78 seconds
Started Jul 01 05:37:11 PM PDT 24
Finished Jul 01 05:53:52 PM PDT 24
Peak memory 220836 kb
Host smart-36be7460-b3a6-4e8e-86e4-a8b41190d8ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847955986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1847955986
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1314049164
Short name T864
Test name
Test status
Simulation time 40503546 ps
CPU time 1.46 seconds
Started Jul 01 05:40:07 PM PDT 24
Finished Jul 01 05:40:12 PM PDT 24
Peak memory 218844 kb
Host smart-3d164959-f22f-4aa4-b8ea-00773d60fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314049164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1314049164
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.295307051
Short name T528
Test name
Test status
Simulation time 66028601 ps
CPU time 1.04 seconds
Started Jul 01 05:39:59 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 217632 kb
Host smart-6810a809-39a2-4577-99c1-0a993dce9bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295307051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.295307051
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2677985148
Short name T691
Test name
Test status
Simulation time 99474179 ps
CPU time 1.22 seconds
Started Jul 01 05:39:57 PM PDT 24
Finished Jul 01 05:40:01 PM PDT 24
Peak memory 219212 kb
Host smart-bd1043c6-90da-4606-a2b4-930b39e0e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677985148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2677985148
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.544124746
Short name T604
Test name
Test status
Simulation time 33439780 ps
CPU time 1.31 seconds
Started Jul 01 05:39:58 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 220192 kb
Host smart-82e45eba-fe82-485a-8ae2-df3df170d9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544124746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.544124746
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1588280615
Short name T301
Test name
Test status
Simulation time 51165010 ps
CPU time 1.26 seconds
Started Jul 01 05:39:59 PM PDT 24
Finished Jul 01 05:40:03 PM PDT 24
Peak memory 218700 kb
Host smart-60411cfb-30f0-4840-ab3a-664cced3f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588280615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1588280615
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4199652229
Short name T314
Test name
Test status
Simulation time 60936484 ps
CPU time 1.14 seconds
Started Jul 01 05:40:06 PM PDT 24
Finished Jul 01 05:40:11 PM PDT 24
Peak memory 219348 kb
Host smart-a3120086-d188-4786-a5ad-fc65a80a23af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199652229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4199652229
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3515782816
Short name T398
Test name
Test status
Simulation time 49025530 ps
CPU time 1.24 seconds
Started Jul 01 05:39:58 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 217704 kb
Host smart-adea46e9-d60c-4fa5-b6f3-1732ef630d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515782816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3515782816
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.154269287
Short name T928
Test name
Test status
Simulation time 32911071 ps
CPU time 1.4 seconds
Started Jul 01 05:39:59 PM PDT 24
Finished Jul 01 05:40:02 PM PDT 24
Peak memory 218948 kb
Host smart-f17b8cae-ed19-4eb9-a396-bf102358daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154269287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.154269287
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1080089362
Short name T879
Test name
Test status
Simulation time 64439312 ps
CPU time 1.5 seconds
Started Jul 01 05:39:57 PM PDT 24
Finished Jul 01 05:40:01 PM PDT 24
Peak memory 219092 kb
Host smart-72cb6fd0-c776-4449-8546-6ed69e5cd7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080089362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1080089362
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.273139372
Short name T866
Test name
Test status
Simulation time 31115839 ps
CPU time 1.27 seconds
Started Jul 01 05:40:02 PM PDT 24
Finished Jul 01 05:40:05 PM PDT 24
Peak memory 217588 kb
Host smart-f8ee8ddf-543e-43f3-a30f-365f1332bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273139372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.273139372
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1680555908
Short name T519
Test name
Test status
Simulation time 50705555 ps
CPU time 1.14 seconds
Started Jul 01 05:35:36 PM PDT 24
Finished Jul 01 05:35:38 PM PDT 24
Peak memory 218860 kb
Host smart-67de0e5e-9287-48ca-aa86-b22f36764628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680555908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1680555908
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1245586597
Short name T822
Test name
Test status
Simulation time 52275287 ps
CPU time 0.93 seconds
Started Jul 01 05:35:36 PM PDT 24
Finished Jul 01 05:35:38 PM PDT 24
Peak memory 215236 kb
Host smart-7182de04-5539-4872-8430-a576ecb87cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245586597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1245586597
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.204745317
Short name T819
Test name
Test status
Simulation time 15303909 ps
CPU time 0.82 seconds
Started Jul 01 05:35:34 PM PDT 24
Finished Jul 01 05:35:36 PM PDT 24
Peak memory 216612 kb
Host smart-e75f93d2-6e4c-4af3-83b6-f508315183f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204745317 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.204745317
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1822468785
Short name T445
Test name
Test status
Simulation time 36884893 ps
CPU time 1.23 seconds
Started Jul 01 05:35:33 PM PDT 24
Finished Jul 01 05:35:35 PM PDT 24
Peak memory 217272 kb
Host smart-fd3996ae-d979-4c31-b3c9-b0a388ae8943
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822468785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1822468785
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1269317207
Short name T147
Test name
Test status
Simulation time 84241189 ps
CPU time 1.05 seconds
Started Jul 01 05:35:34 PM PDT 24
Finished Jul 01 05:35:36 PM PDT 24
Peak memory 229952 kb
Host smart-cedb389d-d6e6-4ebf-844e-1a798e0169a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269317207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1269317207
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3303293908
Short name T863
Test name
Test status
Simulation time 34226177 ps
CPU time 1.24 seconds
Started Jul 01 05:35:30 PM PDT 24
Finished Jul 01 05:35:32 PM PDT 24
Peak memory 220336 kb
Host smart-d5f9d855-cdcb-42f2-b0bf-bfea00264f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303293908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3303293908
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.493739984
Short name T765
Test name
Test status
Simulation time 20399358 ps
CPU time 1.07 seconds
Started Jul 01 05:35:33 PM PDT 24
Finished Jul 01 05:35:35 PM PDT 24
Peak memory 216240 kb
Host smart-942734b4-92c2-4c6f-aa2f-568ab61398be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493739984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.493739984
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3586665332
Short name T742
Test name
Test status
Simulation time 18669897 ps
CPU time 1 seconds
Started Jul 01 05:35:29 PM PDT 24
Finished Jul 01 05:35:30 PM PDT 24
Peak memory 207516 kb
Host smart-565d837b-f5ce-4734-ac7a-156a9be29f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586665332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3586665332
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.568043483
Short name T20
Test name
Test status
Simulation time 487915402 ps
CPU time 6.97 seconds
Started Jul 01 05:35:34 PM PDT 24
Finished Jul 01 05:35:42 PM PDT 24
Peak memory 236612 kb
Host smart-59dfb550-18fe-421d-9384-9ec3fc27d2be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568043483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.568043483
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.319082430
Short name T512
Test name
Test status
Simulation time 14918319 ps
CPU time 0.93 seconds
Started Jul 01 05:35:28 PM PDT 24
Finished Jul 01 05:35:29 PM PDT 24
Peak memory 215644 kb
Host smart-f91dadf0-9cdc-4c41-8548-58f6692fa300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319082430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.319082430
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3012756443
Short name T545
Test name
Test status
Simulation time 343800485 ps
CPU time 1.91 seconds
Started Jul 01 05:35:32 PM PDT 24
Finished Jul 01 05:35:34 PM PDT 24
Peak memory 215668 kb
Host smart-a6aa27a3-f1a5-4aa5-b916-b61a5131c408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012756443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3012756443
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2207604983
Short name T226
Test name
Test status
Simulation time 96636762790 ps
CPU time 2453.47 seconds
Started Jul 01 05:35:30 PM PDT 24
Finished Jul 01 06:16:25 PM PDT 24
Peak memory 231888 kb
Host smart-3d49c75b-5d04-429c-99e3-baeb1471f49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207604983 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2207604983
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2614171863
Short name T710
Test name
Test status
Simulation time 102093132 ps
CPU time 1.28 seconds
Started Jul 01 05:37:19 PM PDT 24
Finished Jul 01 05:37:22 PM PDT 24
Peak memory 216044 kb
Host smart-dabaeae3-aecc-4ce9-b9f0-6c7fcdf52df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614171863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2614171863
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2958702070
Short name T603
Test name
Test status
Simulation time 21151170 ps
CPU time 0.92 seconds
Started Jul 01 05:37:21 PM PDT 24
Finished Jul 01 05:37:23 PM PDT 24
Peak memory 215236 kb
Host smart-84206a57-a6cb-4e4d-a702-f2b5334ece75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958702070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2958702070
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4243399303
Short name T656
Test name
Test status
Simulation time 35543459 ps
CPU time 0.81 seconds
Started Jul 01 05:37:21 PM PDT 24
Finished Jul 01 05:37:23 PM PDT 24
Peak memory 216740 kb
Host smart-0f4c3a1e-460d-4fe5-b383-8e17c72e5f2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243399303 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4243399303
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2535640440
Short name T24
Test name
Test status
Simulation time 77302028 ps
CPU time 1.41 seconds
Started Jul 01 05:37:20 PM PDT 24
Finished Jul 01 05:37:23 PM PDT 24
Peak memory 217228 kb
Host smart-8d1ac064-4741-4d31-a07e-1fa5dfc05874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535640440 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2535640440
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4181744094
Short name T729
Test name
Test status
Simulation time 48998475 ps
CPU time 0.88 seconds
Started Jul 01 05:37:22 PM PDT 24
Finished Jul 01 05:37:24 PM PDT 24
Peak memory 218624 kb
Host smart-6fe9a8d5-14d2-4dbd-b71a-48ecbb74eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181744094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4181744094
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.97674180
Short name T986
Test name
Test status
Simulation time 47735515 ps
CPU time 1.53 seconds
Started Jul 01 05:37:18 PM PDT 24
Finished Jul 01 05:37:21 PM PDT 24
Peak memory 218916 kb
Host smart-336575b7-55f8-42e2-be41-85de3f355494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97674180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.97674180
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2555544320
Short name T924
Test name
Test status
Simulation time 22825346 ps
CPU time 1.11 seconds
Started Jul 01 05:37:21 PM PDT 24
Finished Jul 01 05:37:23 PM PDT 24
Peak memory 215932 kb
Host smart-9c2a779f-5d05-47b3-b970-e79797897c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555544320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2555544320
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3855714004
Short name T343
Test name
Test status
Simulation time 46047948 ps
CPU time 0.9 seconds
Started Jul 01 05:37:20 PM PDT 24
Finished Jul 01 05:37:22 PM PDT 24
Peak memory 215652 kb
Host smart-05ae2c33-9b68-4ce2-b451-cd0d28177879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855714004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3855714004
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.904487943
Short name T524
Test name
Test status
Simulation time 243473193 ps
CPU time 4.8 seconds
Started Jul 01 05:37:19 PM PDT 24
Finished Jul 01 05:37:25 PM PDT 24
Peak memory 217548 kb
Host smart-3530f60b-b50e-438d-b0fc-a2598d046899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904487943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.904487943
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3631725358
Short name T638
Test name
Test status
Simulation time 2730334923 ps
CPU time 70.47 seconds
Started Jul 01 05:37:18 PM PDT 24
Finished Jul 01 05:38:29 PM PDT 24
Peak memory 221132 kb
Host smart-93578eb1-f847-4646-b41d-d4d98d51fb01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631725358 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3631725358
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3132889170
Short name T429
Test name
Test status
Simulation time 45425714 ps
CPU time 1.14 seconds
Started Jul 01 05:37:28 PM PDT 24
Finished Jul 01 05:37:31 PM PDT 24
Peak memory 221060 kb
Host smart-b245b8f4-caf1-481c-ac63-5d15b0b53260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132889170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3132889170
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1799604963
Short name T518
Test name
Test status
Simulation time 180410461 ps
CPU time 0.92 seconds
Started Jul 01 05:37:26 PM PDT 24
Finished Jul 01 05:37:27 PM PDT 24
Peak memory 215248 kb
Host smart-bf37f344-c153-4795-85e7-09aafeba9caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799604963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1799604963
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.396208467
Short name T25
Test name
Test status
Simulation time 16692530 ps
CPU time 0.87 seconds
Started Jul 01 05:37:29 PM PDT 24
Finished Jul 01 05:37:31 PM PDT 24
Peak memory 215892 kb
Host smart-d70d6ab8-df74-478b-a561-4a5154605618
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396208467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.396208467
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4061569203
Short name T578
Test name
Test status
Simulation time 32589108 ps
CPU time 1.21 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:29 PM PDT 24
Peak memory 217288 kb
Host smart-86b6d9d1-030d-45fa-b989-03a1041a382d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061569203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4061569203
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2950644324
Short name T119
Test name
Test status
Simulation time 58171553 ps
CPU time 1.13 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:30 PM PDT 24
Peak memory 230064 kb
Host smart-905345eb-1ddb-4ed1-9a26-c758ddb31655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950644324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2950644324
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2379366817
Short name T931
Test name
Test status
Simulation time 99439866 ps
CPU time 1.4 seconds
Started Jul 01 05:37:22 PM PDT 24
Finished Jul 01 05:37:25 PM PDT 24
Peak memory 220196 kb
Host smart-be0ed45e-f18e-475c-8186-6d8f1a1af7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379366817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2379366817
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.470652781
Short name T39
Test name
Test status
Simulation time 24816895 ps
CPU time 1.02 seconds
Started Jul 01 05:37:26 PM PDT 24
Finished Jul 01 05:37:27 PM PDT 24
Peak memory 216232 kb
Host smart-428f248b-ae57-4f28-849f-ffaf7fb55d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470652781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.470652781
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2361950616
Short name T670
Test name
Test status
Simulation time 15951961 ps
CPU time 1.02 seconds
Started Jul 01 05:37:24 PM PDT 24
Finished Jul 01 05:37:25 PM PDT 24
Peak memory 215628 kb
Host smart-2c3c5fd9-d90d-4452-8cee-9e6da0487235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361950616 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2361950616
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3315789863
Short name T949
Test name
Test status
Simulation time 354743371 ps
CPU time 7 seconds
Started Jul 01 05:37:29 PM PDT 24
Finished Jul 01 05:37:37 PM PDT 24
Peak memory 217856 kb
Host smart-b346b5c5-a3d0-4f97-9b35-ca1e86e7ff9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315789863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3315789863
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.947050443
Short name T546
Test name
Test status
Simulation time 177456390372 ps
CPU time 1146.46 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:56:35 PM PDT 24
Peak memory 224112 kb
Host smart-7392194c-3573-411d-b63c-14d68a7b57f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947050443 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.947050443
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.333866284
Short name T287
Test name
Test status
Simulation time 22739362 ps
CPU time 1.14 seconds
Started Jul 01 05:37:29 PM PDT 24
Finished Jul 01 05:37:31 PM PDT 24
Peak memory 218800 kb
Host smart-5489cdad-cba7-4e64-a922-c7f5555e2dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333866284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.333866284
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3493403740
Short name T782
Test name
Test status
Simulation time 20559220 ps
CPU time 0.9 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:29 PM PDT 24
Peak memory 207060 kb
Host smart-f6051976-fbcf-499d-9c1d-e6bbd3785028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493403740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3493403740
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.224360700
Short name T516
Test name
Test status
Simulation time 14085370 ps
CPU time 0.97 seconds
Started Jul 01 05:37:30 PM PDT 24
Finished Jul 01 05:37:32 PM PDT 24
Peak memory 216536 kb
Host smart-7a31f7a9-2d84-497e-a394-dba3c57952bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224360700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.224360700
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3158714791
Short name T214
Test name
Test status
Simulation time 47107365 ps
CPU time 1.12 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:30 PM PDT 24
Peak memory 217256 kb
Host smart-bfd83b0f-0d42-4a9f-8797-b9531c373152
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158714791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3158714791
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3655879710
Short name T182
Test name
Test status
Simulation time 18672167 ps
CPU time 1.15 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:30 PM PDT 24
Peak memory 224348 kb
Host smart-79c180a9-96dd-4c47-8713-d6dd8cf40039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655879710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3655879710
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3429223571
Short name T492
Test name
Test status
Simulation time 55386635 ps
CPU time 1.29 seconds
Started Jul 01 05:37:25 PM PDT 24
Finished Jul 01 05:37:28 PM PDT 24
Peak memory 220272 kb
Host smart-5f6d834e-8009-48d0-bbf6-a544689c8d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429223571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3429223571
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.650740534
Short name T705
Test name
Test status
Simulation time 22587923 ps
CPU time 1.19 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:29 PM PDT 24
Peak memory 215732 kb
Host smart-be0cfa1e-6b5e-43e4-9824-49f88b53df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650740534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.650740534
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1770793585
Short name T402
Test name
Test status
Simulation time 16301674 ps
CPU time 0.99 seconds
Started Jul 01 05:37:26 PM PDT 24
Finished Jul 01 05:37:28 PM PDT 24
Peak memory 215660 kb
Host smart-80c966ba-79ff-47ba-a898-0f25b83fb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770793585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1770793585
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.490948014
Short name T744
Test name
Test status
Simulation time 288249933 ps
CPU time 3.54 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:32 PM PDT 24
Peak memory 217424 kb
Host smart-3c436e9f-7e41-4fcc-bed2-7e1b96411de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490948014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.490948014
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1452655428
Short name T478
Test name
Test status
Simulation time 173603926450 ps
CPU time 1077.11 seconds
Started Jul 01 05:37:28 PM PDT 24
Finished Jul 01 05:55:27 PM PDT 24
Peak memory 224884 kb
Host smart-3e4cb79f-40ad-42d3-b8d6-1bea4409d18b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452655428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1452655428
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2569184390
Short name T555
Test name
Test status
Simulation time 25375247 ps
CPU time 1.19 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:35 PM PDT 24
Peak memory 219072 kb
Host smart-f5c4037e-15c4-4cc2-860b-ca82df6d091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569184390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2569184390
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2007994363
Short name T440
Test name
Test status
Simulation time 153459992 ps
CPU time 0.89 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 215240 kb
Host smart-318df6f6-f145-488e-8663-99c74e44feee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007994363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2007994363
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2940105911
Short name T681
Test name
Test status
Simulation time 23056286 ps
CPU time 0.86 seconds
Started Jul 01 05:37:31 PM PDT 24
Finished Jul 01 05:37:33 PM PDT 24
Peak memory 216664 kb
Host smart-de931c42-69fe-4efe-911f-111411eef62e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940105911 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2940105911
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1374764515
Short name T410
Test name
Test status
Simulation time 38464037 ps
CPU time 1.3 seconds
Started Jul 01 05:37:31 PM PDT 24
Finished Jul 01 05:37:33 PM PDT 24
Peak memory 219684 kb
Host smart-e651d4c6-6563-4854-bf9c-20a8ad8ec533
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374764515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1374764515
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2371744275
Short name T841
Test name
Test status
Simulation time 20856128 ps
CPU time 1.08 seconds
Started Jul 01 05:37:31 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 220304 kb
Host smart-6c99eb5e-4b65-4f84-b49b-fc0aa6cb3080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371744275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2371744275
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.408048214
Short name T643
Test name
Test status
Simulation time 32124623 ps
CPU time 1.3 seconds
Started Jul 01 05:37:29 PM PDT 24
Finished Jul 01 05:37:32 PM PDT 24
Peak memory 218764 kb
Host smart-d9aabcf5-0291-433b-9e87-14bb6fb3ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408048214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.408048214
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2968648987
Short name T513
Test name
Test status
Simulation time 69248662 ps
CPU time 1 seconds
Started Jul 01 05:37:33 PM PDT 24
Finished Jul 01 05:37:35 PM PDT 24
Peak memory 215772 kb
Host smart-c5b03329-eef3-4d6d-b099-52c365fd83f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968648987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2968648987
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.951343957
Short name T685
Test name
Test status
Simulation time 51582911 ps
CPU time 0.93 seconds
Started Jul 01 05:37:26 PM PDT 24
Finished Jul 01 05:37:29 PM PDT 24
Peak memory 215656 kb
Host smart-fa047537-d073-46d6-b812-4e7f5b1760ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951343957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.951343957
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.871146926
Short name T726
Test name
Test status
Simulation time 492947117 ps
CPU time 3.02 seconds
Started Jul 01 05:37:27 PM PDT 24
Finished Jul 01 05:37:31 PM PDT 24
Peak memory 217788 kb
Host smart-59b60677-d643-4556-895f-14e593c62c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871146926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.871146926
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1039589815
Short name T236
Test name
Test status
Simulation time 277123160986 ps
CPU time 482.29 seconds
Started Jul 01 05:37:26 PM PDT 24
Finished Jul 01 05:45:29 PM PDT 24
Peak memory 232408 kb
Host smart-e87b5052-02ee-40b9-9055-1cb5ef5cb835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039589815 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1039589815
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1991677488
Short name T490
Test name
Test status
Simulation time 305879832 ps
CPU time 1.35 seconds
Started Jul 01 05:37:34 PM PDT 24
Finished Jul 01 05:37:37 PM PDT 24
Peak memory 218696 kb
Host smart-cc6c307c-4af9-46db-99fa-e9fb2db89fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991677488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1991677488
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.209954750
Short name T110
Test name
Test status
Simulation time 10843873 ps
CPU time 0.8 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 207124 kb
Host smart-b7ece802-abb2-4278-83c3-2e51c2a19a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209954750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.209954750
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3798000428
Short name T908
Test name
Test status
Simulation time 35637823 ps
CPU time 0.83 seconds
Started Jul 01 05:37:34 PM PDT 24
Finished Jul 01 05:37:37 PM PDT 24
Peak memory 216656 kb
Host smart-f3d38780-c69f-41f1-a468-9260d5c222c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798000428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3798000428
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.913407259
Short name T148
Test name
Test status
Simulation time 87628722 ps
CPU time 1.22 seconds
Started Jul 01 05:37:34 PM PDT 24
Finished Jul 01 05:37:37 PM PDT 24
Peak memory 217328 kb
Host smart-d60a76d4-8600-454f-9aa7-7465acc448be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913407259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.913407259
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1049134417
Short name T211
Test name
Test status
Simulation time 18784304 ps
CPU time 1.06 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 218888 kb
Host smart-ca4285d8-0f13-4fa7-9bab-1bc4461669d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049134417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1049134417
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.423554992
Short name T522
Test name
Test status
Simulation time 130096132 ps
CPU time 0.96 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:35 PM PDT 24
Peak memory 217708 kb
Host smart-e64951f9-4bb3-44b5-8855-362253f6341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423554992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.423554992
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3507010532
Short name T902
Test name
Test status
Simulation time 25249203 ps
CPU time 0.93 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 215988 kb
Host smart-671428f6-dbdd-41af-ab90-0e597d10cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507010532 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3507010532
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2537583089
Short name T602
Test name
Test status
Simulation time 19434321 ps
CPU time 1.03 seconds
Started Jul 01 05:37:32 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 215756 kb
Host smart-8028eb25-54ad-4aaf-9d95-75308a704b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537583089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2537583089
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3692576523
Short name T319
Test name
Test status
Simulation time 142314953 ps
CPU time 2.07 seconds
Started Jul 01 05:37:31 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 217496 kb
Host smart-ee44af61-a6c2-4cdc-a469-29fea085080d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692576523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3692576523
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2608625440
Short name T228
Test name
Test status
Simulation time 91065115512 ps
CPU time 2200.42 seconds
Started Jul 01 05:37:34 PM PDT 24
Finished Jul 01 06:14:17 PM PDT 24
Peak memory 230992 kb
Host smart-800c00fc-38a3-47b0-bfce-be719648aefb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608625440 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2608625440
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.321760989
Short name T921
Test name
Test status
Simulation time 50348077 ps
CPU time 1.22 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:37:41 PM PDT 24
Peak memory 218736 kb
Host smart-2f3c46ed-9032-42e6-9e7f-e6fb58a627a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321760989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.321760989
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.721757384
Short name T687
Test name
Test status
Simulation time 14073771 ps
CPU time 0.93 seconds
Started Jul 01 05:37:37 PM PDT 24
Finished Jul 01 05:37:38 PM PDT 24
Peak memory 207132 kb
Host smart-d066f24d-639c-4dc5-8409-337015fe6ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721757384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.721757384
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1763927131
Short name T858
Test name
Test status
Simulation time 13047082 ps
CPU time 0.9 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:40 PM PDT 24
Peak memory 216568 kb
Host smart-41d7a79d-a608-437b-bc47-adac683c65ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763927131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1763927131
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.4227562603
Short name T383
Test name
Test status
Simulation time 63904170 ps
CPU time 1.28 seconds
Started Jul 01 05:37:46 PM PDT 24
Finished Jul 01 05:37:48 PM PDT 24
Peak memory 217376 kb
Host smart-efb3fd2f-ab02-4b7a-958b-80085838c73e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227562603 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.4227562603
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3373426556
Short name T600
Test name
Test status
Simulation time 23281663 ps
CPU time 0.97 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:37:42 PM PDT 24
Peak memory 219124 kb
Host smart-2d6e6e50-e791-4e8c-a79f-87accb53ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373426556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3373426556
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3949748842
Short name T995
Test name
Test status
Simulation time 121623640 ps
CPU time 2.46 seconds
Started Jul 01 05:37:36 PM PDT 24
Finished Jul 01 05:37:39 PM PDT 24
Peak memory 219364 kb
Host smart-909bd7c1-c0f3-4a1a-a4ef-ac1cd2428a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949748842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3949748842
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3266370349
Short name T95
Test name
Test status
Simulation time 28585645 ps
CPU time 0.92 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:40 PM PDT 24
Peak memory 216084 kb
Host smart-3c64919c-5e70-4d3d-b2f3-143071fef486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266370349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3266370349
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2299314042
Short name T342
Test name
Test status
Simulation time 17175874 ps
CPU time 0.98 seconds
Started Jul 01 05:37:37 PM PDT 24
Finished Jul 01 05:37:39 PM PDT 24
Peak memory 215572 kb
Host smart-ccac4c26-0803-4f38-9710-e67e0b409b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299314042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2299314042
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.438149766
Short name T912
Test name
Test status
Simulation time 69868577 ps
CPU time 1.87 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:41 PM PDT 24
Peak memory 215660 kb
Host smart-5f49e831-b80e-4a83-ba06-7eea3554ad0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438149766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.438149766
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.333145581
Short name T409
Test name
Test status
Simulation time 5636365196 ps
CPU time 30.63 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:38:11 PM PDT 24
Peak memory 221164 kb
Host smart-0b46e0ba-40a7-4e8f-830c-6665275fee27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333145581 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.333145581
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2241468155
Short name T943
Test name
Test status
Simulation time 78277691 ps
CPU time 1.19 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:37:42 PM PDT 24
Peak memory 220064 kb
Host smart-8a46c746-cbfc-4a7a-8213-6e8db5fe67ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241468155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2241468155
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3020108355
Short name T439
Test name
Test status
Simulation time 13792128 ps
CPU time 0.9 seconds
Started Jul 01 05:37:44 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 207044 kb
Host smart-34406934-4a3d-435f-8f93-04d1c82b058a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020108355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3020108355
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2543991482
Short name T754
Test name
Test status
Simulation time 22505634 ps
CPU time 0.85 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:37:45 PM PDT 24
Peak memory 216564 kb
Host smart-f1e8d883-40a8-4f91-a7b3-6417566c9df5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543991482 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2543991482
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.370314716
Short name T134
Test name
Test status
Simulation time 62663387 ps
CPU time 1.23 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 217132 kb
Host smart-477dd272-274a-4811-834d-ae10f2a31a23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370314716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.370314716
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2472933145
Short name T898
Test name
Test status
Simulation time 33133436 ps
CPU time 1.08 seconds
Started Jul 01 05:37:40 PM PDT 24
Finished Jul 01 05:37:43 PM PDT 24
Peak memory 220188 kb
Host smart-5f3c4ef4-668f-4a19-8bc8-1832f5d570c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472933145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2472933145
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1720634458
Short name T639
Test name
Test status
Simulation time 30245318 ps
CPU time 1.4 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:37:41 PM PDT 24
Peak memory 217752 kb
Host smart-4413475c-9e89-47d5-ab49-49b9d7eee4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720634458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1720634458
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.948337568
Short name T396
Test name
Test status
Simulation time 47319495 ps
CPU time 0.85 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:40 PM PDT 24
Peak memory 215544 kb
Host smart-65a0cab5-efaa-448c-aff6-43aee69b3076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948337568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.948337568
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.517696467
Short name T435
Test name
Test status
Simulation time 20910585 ps
CPU time 0.96 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:39 PM PDT 24
Peak memory 215640 kb
Host smart-323c4ad8-5efd-443d-85b1-5f40d83004cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517696467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.517696467
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1618999380
Short name T856
Test name
Test status
Simulation time 276592721 ps
CPU time 4.87 seconds
Started Jul 01 05:37:38 PM PDT 24
Finished Jul 01 05:37:44 PM PDT 24
Peak memory 220576 kb
Host smart-14433a3e-8bd6-4cd4-86f7-76476387ba06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618999380 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1618999380
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2206010338
Short name T571
Test name
Test status
Simulation time 52904747171 ps
CPU time 884.11 seconds
Started Jul 01 05:37:39 PM PDT 24
Finished Jul 01 05:52:25 PM PDT 24
Peak memory 219304 kb
Host smart-450f3609-f1df-43e3-b515-15ac52d037f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206010338 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2206010338
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.367768814
Short name T682
Test name
Test status
Simulation time 64667303 ps
CPU time 1.05 seconds
Started Jul 01 05:37:55 PM PDT 24
Finished Jul 01 05:37:58 PM PDT 24
Peak memory 218956 kb
Host smart-a2948ab1-52f3-42e1-8044-72a4095a8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367768814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.367768814
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3182300787
Short name T549
Test name
Test status
Simulation time 29186403 ps
CPU time 0.94 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 215528 kb
Host smart-3598bc6d-2ed9-478f-9288-5ed6f28c696b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182300787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3182300787
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1607454827
Short name T206
Test name
Test status
Simulation time 13574692 ps
CPU time 0.93 seconds
Started Jul 01 05:37:44 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 216756 kb
Host smart-6c68cf82-dc69-4c54-a6f2-21e2b8fce8b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607454827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1607454827
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3732493915
Short name T198
Test name
Test status
Simulation time 44514003 ps
CPU time 0.98 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 219888 kb
Host smart-bd00a5dc-9b47-4349-b7d9-ef5a9f02e146
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732493915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3732493915
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.63628708
Short name T192
Test name
Test status
Simulation time 18878166 ps
CPU time 1.11 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:37:45 PM PDT 24
Peak memory 224356 kb
Host smart-17d55c08-5f4d-462e-8b0b-6ad80ea62def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63628708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.63628708
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2731169669
Short name T561
Test name
Test status
Simulation time 156269786 ps
CPU time 2.23 seconds
Started Jul 01 05:37:46 PM PDT 24
Finished Jul 01 05:37:50 PM PDT 24
Peak memory 218904 kb
Host smart-caf6617a-61f0-4caf-991a-ca78b4619976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731169669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2731169669
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.808759353
Short name T74
Test name
Test status
Simulation time 28491998 ps
CPU time 0.97 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:55 PM PDT 24
Peak memory 215692 kb
Host smart-87593067-78f7-4e9f-90b1-17addafef471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808759353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.808759353
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2194575185
Short name T361
Test name
Test status
Simulation time 44377243 ps
CPU time 0.93 seconds
Started Jul 01 05:37:46 PM PDT 24
Finished Jul 01 05:37:48 PM PDT 24
Peak memory 215700 kb
Host smart-256c3339-dbad-4323-9bc6-531675604219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194575185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2194575185
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.330337396
Short name T347
Test name
Test status
Simulation time 56379906 ps
CPU time 1.7 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 207496 kb
Host smart-5ee64fd9-a7f5-4ec1-b47c-a92b31abc3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330337396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.330337396
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2192479578
Short name T72
Test name
Test status
Simulation time 72780476549 ps
CPU time 463.04 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:45:37 PM PDT 24
Peak memory 218764 kb
Host smart-7dba2df0-0510-4985-8789-322926449670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192479578 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2192479578
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.889611146
Short name T220
Test name
Test status
Simulation time 294689800 ps
CPU time 1.25 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 218968 kb
Host smart-15366854-68c2-4c39-8028-3c6834ebf66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889611146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.889611146
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1585114056
Short name T446
Test name
Test status
Simulation time 31652110 ps
CPU time 0.91 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:52 PM PDT 24
Peak memory 207088 kb
Host smart-8966edc1-d877-4ad3-b386-3b646a8876ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585114056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1585114056
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.976755472
Short name T655
Test name
Test status
Simulation time 12948041 ps
CPU time 0.88 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:37:44 PM PDT 24
Peak memory 215996 kb
Host smart-1e8e32fb-d606-4eaf-a295-edc06591ac5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976755472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.976755472
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3978345886
Short name T209
Test name
Test status
Simulation time 44199714 ps
CPU time 1.39 seconds
Started Jul 01 05:37:44 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 217340 kb
Host smart-f7edb443-9111-450f-82fc-99d47a8cd36f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978345886 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3978345886
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4166217848
Short name T799
Test name
Test status
Simulation time 32188130 ps
CPU time 0.96 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 219216 kb
Host smart-ff213f5f-963c-431b-9eb5-02d12f51aa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166217848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4166217848
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3954845445
Short name T668
Test name
Test status
Simulation time 95304331 ps
CPU time 1.33 seconds
Started Jul 01 05:37:44 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 219088 kb
Host smart-e1c3c752-16f4-4258-a2be-74d0661fbd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954845445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3954845445
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.3487033594
Short name T876
Test name
Test status
Simulation time 19309140 ps
CPU time 1.06 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:37:45 PM PDT 24
Peak memory 215656 kb
Host smart-5880afd4-696c-45b8-af9c-ea68ef0e34e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487033594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3487033594
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1408217565
Short name T989
Test name
Test status
Simulation time 105804241 ps
CPU time 2.51 seconds
Started Jul 01 05:37:46 PM PDT 24
Finished Jul 01 05:37:50 PM PDT 24
Peak memory 215748 kb
Host smart-c72744c4-da37-4999-9f8c-f20b47de2eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408217565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1408217565
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3322436995
Short name T233
Test name
Test status
Simulation time 55310578267 ps
CPU time 1206.82 seconds
Started Jul 01 05:37:43 PM PDT 24
Finished Jul 01 05:57:51 PM PDT 24
Peak memory 224080 kb
Host smart-596874b7-c421-4f75-87b9-7414004fb425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322436995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3322436995
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4271286951
Short name T618
Test name
Test status
Simulation time 71668134 ps
CPU time 1.11 seconds
Started Jul 01 05:37:56 PM PDT 24
Finished Jul 01 05:37:59 PM PDT 24
Peak memory 219544 kb
Host smart-5fde5cb4-994c-4a27-9a68-4b63e080051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271286951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4271286951
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1110962067
Short name T772
Test name
Test status
Simulation time 24558453 ps
CPU time 0.89 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 207132 kb
Host smart-073e03fd-0604-4670-bfb7-72bec6d07e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110962067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1110962067
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1817683870
Short name T407
Test name
Test status
Simulation time 14642483 ps
CPU time 0.99 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 216920 kb
Host smart-9586f784-6adf-4118-8688-cefc498bd493
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817683870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1817683870
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1298144339
Short name T442
Test name
Test status
Simulation time 29556806 ps
CPU time 1.11 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 217212 kb
Host smart-de7376bb-e7e6-4a88-87b2-dcc5a5e5aac0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298144339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1298144339
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3421005521
Short name T208
Test name
Test status
Simulation time 79671148 ps
CPU time 1.02 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 221252 kb
Host smart-b6a100f6-137d-4d50-b688-f3cc5e1633ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421005521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3421005521
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.927915141
Short name T291
Test name
Test status
Simulation time 60598482 ps
CPU time 1.27 seconds
Started Jul 01 05:37:46 PM PDT 24
Finished Jul 01 05:37:48 PM PDT 24
Peak memory 217588 kb
Host smart-2bc3662f-e764-4d0d-b91c-241aab9abad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927915141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.927915141
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.225101961
Short name T97
Test name
Test status
Simulation time 27947386 ps
CPU time 0.97 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:37:54 PM PDT 24
Peak memory 216208 kb
Host smart-65477b77-8d5e-4954-ae28-0864bf7fd9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225101961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.225101961
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4207501292
Short name T421
Test name
Test status
Simulation time 41475733 ps
CPU time 0.9 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:37:55 PM PDT 24
Peak memory 207496 kb
Host smart-249aa3f0-d94a-40f4-ac76-1f60529f5b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207501292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4207501292
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1718316282
Short name T241
Test name
Test status
Simulation time 760032638 ps
CPU time 4.25 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:38:00 PM PDT 24
Peak memory 215776 kb
Host smart-7193f7bb-0c68-4b84-aaf2-1ff68342f0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718316282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1718316282
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.620301305
Short name T676
Test name
Test status
Simulation time 44344095671 ps
CPU time 1162.6 seconds
Started Jul 01 05:37:44 PM PDT 24
Finished Jul 01 05:57:08 PM PDT 24
Peak memory 224116 kb
Host smart-eb90810c-c583-4fd6-b396-9a0dffb00883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620301305 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.620301305
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1693806355
Short name T987
Test name
Test status
Simulation time 69925006 ps
CPU time 1.22 seconds
Started Jul 01 05:35:43 PM PDT 24
Finished Jul 01 05:35:45 PM PDT 24
Peak memory 220828 kb
Host smart-94128935-1330-45ef-a492-6866ee4bb79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693806355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1693806355
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4036980756
Short name T892
Test name
Test status
Simulation time 19928493 ps
CPU time 0.99 seconds
Started Jul 01 05:35:39 PM PDT 24
Finished Jul 01 05:35:41 PM PDT 24
Peak memory 207168 kb
Host smart-119508e1-7016-4265-97a2-9cfff9909bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036980756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4036980756
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1524384208
Short name T883
Test name
Test status
Simulation time 59709606 ps
CPU time 0.82 seconds
Started Jul 01 05:35:39 PM PDT 24
Finished Jul 01 05:35:41 PM PDT 24
Peak memory 216608 kb
Host smart-164857ee-121a-4e9c-8498-d0bef67685c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524384208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1524384208
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.3347820601
Short name T653
Test name
Test status
Simulation time 28453728 ps
CPU time 0.83 seconds
Started Jul 01 05:35:42 PM PDT 24
Finished Jul 01 05:35:43 PM PDT 24
Peak memory 218616 kb
Host smart-0f8959aa-0974-4d71-9e4e-d3129695666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347820601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3347820601
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2999620360
Short name T909
Test name
Test status
Simulation time 116708904 ps
CPU time 1.49 seconds
Started Jul 01 05:35:33 PM PDT 24
Finished Jul 01 05:35:35 PM PDT 24
Peak memory 219404 kb
Host smart-bbcd4706-952e-4a67-ba59-fa46978034ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999620360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2999620360
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2224756120
Short name T826
Test name
Test status
Simulation time 40631936 ps
CPU time 0.92 seconds
Started Jul 01 05:35:41 PM PDT 24
Finished Jul 01 05:35:43 PM PDT 24
Peak memory 215688 kb
Host smart-cd6fbeb8-a04d-466a-b715-a988a12e32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224756120 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2224756120
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3114396718
Short name T30
Test name
Test status
Simulation time 17687881 ps
CPU time 0.98 seconds
Started Jul 01 05:35:33 PM PDT 24
Finished Jul 01 05:35:34 PM PDT 24
Peak memory 207420 kb
Host smart-e2b5d968-f4c8-4036-833a-e7f368ee2e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114396718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3114396718
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3414100470
Short name T748
Test name
Test status
Simulation time 193818161 ps
CPU time 0.94 seconds
Started Jul 01 05:35:34 PM PDT 24
Finished Jul 01 05:35:36 PM PDT 24
Peak memory 215704 kb
Host smart-f72273d0-7ac4-48fa-b8bb-320d7e14310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414100470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3414100470
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2231634851
Short name T65
Test name
Test status
Simulation time 285025169 ps
CPU time 1.59 seconds
Started Jul 01 05:35:34 PM PDT 24
Finished Jul 01 05:35:36 PM PDT 24
Peak memory 217624 kb
Host smart-42892878-ad7c-4af8-8b26-dfdbe706b51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231634851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2231634851
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.627914580
Short name T854
Test name
Test status
Simulation time 108081582261 ps
CPU time 518.81 seconds
Started Jul 01 05:35:40 PM PDT 24
Finished Jul 01 05:44:19 PM PDT 24
Peak memory 219916 kb
Host smart-b8fa706b-6555-49e8-b8e2-a816d1a2bbbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627914580 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.627914580
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3605654989
Short name T907
Test name
Test status
Simulation time 53762150 ps
CPU time 1.19 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 219492 kb
Host smart-285c5963-8aea-48c2-bde9-1a329f7a5393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605654989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3605654989
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1360244353
Short name T418
Test name
Test status
Simulation time 30110759 ps
CPU time 0.94 seconds
Started Jul 01 05:38:01 PM PDT 24
Finished Jul 01 05:38:04 PM PDT 24
Peak memory 207088 kb
Host smart-e12d8157-3f74-4ada-9b42-93d73099c30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360244353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1360244353
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.849229031
Short name T731
Test name
Test status
Simulation time 17814519 ps
CPU time 0.86 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 215720 kb
Host smart-c6e1cc97-ae62-417e-a696-365e634bca93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849229031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.849229031
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.1046874664
Short name T132
Test name
Test status
Simulation time 26039901 ps
CPU time 1.29 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 230164 kb
Host smart-8cfc820d-80fd-4e57-95ee-ef8fd349cff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046874664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1046874664
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.578707037
Short name T80
Test name
Test status
Simulation time 84998081 ps
CPU time 2.11 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 220556 kb
Host smart-ed08f916-5aac-43c2-97ae-8954c52ea76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578707037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.578707037
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2738628382
Short name T448
Test name
Test status
Simulation time 21320495 ps
CPU time 1.07 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 215996 kb
Host smart-adcd6c7c-3188-492a-a4c2-e66eb62d8450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738628382 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2738628382
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.4077640265
Short name T69
Test name
Test status
Simulation time 94183753 ps
CPU time 0.9 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 215652 kb
Host smart-1b5a8d3c-1f33-46c3-8b1d-2dea66d6cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077640265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.4077640265
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4055931991
Short name T756
Test name
Test status
Simulation time 448326817 ps
CPU time 4.66 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:38:00 PM PDT 24
Peak memory 217760 kb
Host smart-b7981247-2a36-4b39-be8c-50f0f81522a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055931991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4055931991
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.983348249
Short name T416
Test name
Test status
Simulation time 126433948953 ps
CPU time 1616.56 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 06:04:50 PM PDT 24
Peak memory 227504 kb
Host smart-e312164e-d3a3-49e4-a803-bf1f57ad4db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983348249 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.983348249
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3684778749
Short name T688
Test name
Test status
Simulation time 61978141 ps
CPU time 1.2 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 221708 kb
Host smart-f9276734-8884-41a6-89b0-edfe4e7911f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684778749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3684778749
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2561211837
Short name T794
Test name
Test status
Simulation time 54190945 ps
CPU time 0.91 seconds
Started Jul 01 05:37:54 PM PDT 24
Finished Jul 01 05:37:58 PM PDT 24
Peak memory 207068 kb
Host smart-91c6726d-c10e-491f-934f-efd0dcee83d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561211837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2561211837
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2031344953
Short name T867
Test name
Test status
Simulation time 14221375 ps
CPU time 0.98 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 216836 kb
Host smart-7da81773-33c8-459c-a8e6-c4bac45a7db5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031344953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2031344953
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3976163880
Short name T738
Test name
Test status
Simulation time 38124435 ps
CPU time 1.2 seconds
Started Jul 01 05:37:50 PM PDT 24
Finished Jul 01 05:37:52 PM PDT 24
Peak memory 218620 kb
Host smart-78bc1431-9034-4ef7-9ff3-1ef313a3d6eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976163880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3976163880
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2017253163
Short name T425
Test name
Test status
Simulation time 30638968 ps
CPU time 1.02 seconds
Started Jul 01 05:37:55 PM PDT 24
Finished Jul 01 05:37:58 PM PDT 24
Peak memory 220000 kb
Host smart-b035d479-9d78-4c7b-8d79-a5bbfecb0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017253163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2017253163
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3134247624
Short name T381
Test name
Test status
Simulation time 43996284 ps
CPU time 1.19 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 218812 kb
Host smart-a2520f02-1613-4c44-b7f7-e0b716e38b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134247624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3134247624
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2424935675
Short name T945
Test name
Test status
Simulation time 21136945 ps
CPU time 1.09 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 216344 kb
Host smart-36661090-5d5e-4842-a752-329a78bd62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424935675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2424935675
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3505489794
Short name T248
Test name
Test status
Simulation time 21618974 ps
CPU time 0.93 seconds
Started Jul 01 05:37:54 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 215644 kb
Host smart-622b48f2-e745-49c8-aaf6-ade7f5e8d90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505489794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3505489794
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.56231645
Short name T629
Test name
Test status
Simulation time 331888437 ps
CPU time 3.96 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:38:00 PM PDT 24
Peak memory 220036 kb
Host smart-3af58f20-993b-41ad-8565-87eae9993639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56231645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.56231645
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2020407072
Short name T612
Test name
Test status
Simulation time 24167299898 ps
CPU time 294.7 seconds
Started Jul 01 05:37:56 PM PDT 24
Finished Jul 01 05:42:52 PM PDT 24
Peak memory 223968 kb
Host smart-9a967044-72bd-43aa-b4ad-6c980f72f6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020407072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2020407072
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3953282267
Short name T3
Test name
Test status
Simulation time 28987256 ps
CPU time 1.35 seconds
Started Jul 01 05:37:56 PM PDT 24
Finished Jul 01 05:37:59 PM PDT 24
Peak memory 221004 kb
Host smart-b2f539a9-a476-44cd-a522-6c2b0f69812c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953282267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3953282267
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.504792410
Short name T889
Test name
Test status
Simulation time 137823934 ps
CPU time 0.98 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:02 PM PDT 24
Peak memory 207036 kb
Host smart-96540d4d-31a2-41fc-9853-8c8f588e1522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504792410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.504792410
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.920315844
Short name T752
Test name
Test status
Simulation time 25992376 ps
CPU time 0.87 seconds
Started Jul 01 05:37:54 PM PDT 24
Finished Jul 01 05:37:58 PM PDT 24
Peak memory 216308 kb
Host smart-e5ecdf13-7f3f-4179-8e63-12c3cb361b57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920315844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.920315844
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2393995686
Short name T133
Test name
Test status
Simulation time 45509902 ps
CPU time 1.39 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:02 PM PDT 24
Peak memory 216008 kb
Host smart-652fa16e-11e1-423d-b503-3e306fb55fd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393995686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2393995686
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.746415858
Short name T929
Test name
Test status
Simulation time 33351884 ps
CPU time 1.47 seconds
Started Jul 01 05:37:51 PM PDT 24
Finished Jul 01 05:37:54 PM PDT 24
Peak memory 225848 kb
Host smart-06ea0f12-63ef-4b09-a0b4-4bd69931091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746415858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.746415858
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.349425223
Short name T851
Test name
Test status
Simulation time 94420365 ps
CPU time 2.51 seconds
Started Jul 01 05:37:53 PM PDT 24
Finished Jul 01 05:37:59 PM PDT 24
Peak memory 218920 kb
Host smart-d3d2a9c7-cc67-46dc-8b27-29024cfc9b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349425223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.349425223
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4174159045
Short name T36
Test name
Test status
Simulation time 22142025 ps
CPU time 1.09 seconds
Started Jul 01 05:37:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 215832 kb
Host smart-d05f6f7c-443c-4b18-84c6-6cc9ea7e7fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174159045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4174159045
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3741373549
Short name T364
Test name
Test status
Simulation time 50182018 ps
CPU time 0.92 seconds
Started Jul 01 05:37:54 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 215640 kb
Host smart-ad59b9af-1e36-4387-b398-b229b05186e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741373549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3741373549
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1665505249
Short name T5
Test name
Test status
Simulation time 259633212 ps
CPU time 3.3 seconds
Started Jul 01 05:38:02 PM PDT 24
Finished Jul 01 05:38:06 PM PDT 24
Peak memory 217660 kb
Host smart-31c4b4a2-789f-4d54-a53a-5d55e0fda794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665505249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1665505249
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.561800425
Short name T227
Test name
Test status
Simulation time 95055765169 ps
CPU time 376.66 seconds
Started Jul 01 05:37:55 PM PDT 24
Finished Jul 01 05:44:14 PM PDT 24
Peak memory 219272 kb
Host smart-a4454a13-59b4-4d7f-8c95-fe62ad342952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561800425 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.561800425
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1564778034
Short name T138
Test name
Test status
Simulation time 23258097 ps
CPU time 1.13 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:06 PM PDT 24
Peak memory 218800 kb
Host smart-4f9544ab-f5eb-42ab-89a5-41b6f8a50588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564778034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1564778034
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.922841333
Short name T108
Test name
Test status
Simulation time 91723839 ps
CPU time 0.82 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:02 PM PDT 24
Peak memory 215336 kb
Host smart-4427bb6e-3ff7-45cc-9315-256e23f8f3f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922841333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.922841333
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.99174045
Short name T91
Test name
Test status
Simulation time 20133798 ps
CPU time 0.86 seconds
Started Jul 01 05:38:00 PM PDT 24
Finished Jul 01 05:38:03 PM PDT 24
Peak memory 216560 kb
Host smart-e0e5e47b-e00b-45a4-95b8-cd034b4d8433
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99174045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.99174045
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2865725012
Short name T993
Test name
Test status
Simulation time 37001109 ps
CPU time 1.02 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:02 PM PDT 24
Peak memory 217096 kb
Host smart-6adb62d6-3376-4f97-ae27-769c7b8ce70b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865725012 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2865725012
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2432036883
Short name T146
Test name
Test status
Simulation time 52463668 ps
CPU time 1.11 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:01 PM PDT 24
Peak memory 230076 kb
Host smart-16dcce3f-820f-4c54-a73b-6ac7825e4c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432036883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2432036883
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1355327575
Short name T305
Test name
Test status
Simulation time 193867998 ps
CPU time 1.39 seconds
Started Jul 01 05:38:01 PM PDT 24
Finished Jul 01 05:38:04 PM PDT 24
Peak memory 219056 kb
Host smart-9af3ea2e-9d42-48eb-be20-4d8fa32ae79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355327575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1355327575
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3581502412
Short name T542
Test name
Test status
Simulation time 24180266 ps
CPU time 1.23 seconds
Started Jul 01 05:38:01 PM PDT 24
Finished Jul 01 05:38:04 PM PDT 24
Peak memory 224420 kb
Host smart-f3478c5e-4a2d-4c55-96e9-50acd9c4d7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581502412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3581502412
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2850231718
Short name T247
Test name
Test status
Simulation time 58616891 ps
CPU time 0.89 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:38:02 PM PDT 24
Peak memory 215700 kb
Host smart-0d7824b1-0d2c-4612-baa7-95952a73ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850231718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2850231718
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3656827534
Short name T529
Test name
Test status
Simulation time 313270844 ps
CPU time 3.96 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:08 PM PDT 24
Peak memory 217636 kb
Host smart-797f6bd5-9ba6-4686-a782-bb4429fc425d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656827534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3656827534
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2256724617
Short name T71
Test name
Test status
Simulation time 277226563064 ps
CPU time 664.99 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:49:06 PM PDT 24
Peak memory 220408 kb
Host smart-5c840424-2945-49b2-a442-46ba477c82e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256724617 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2256724617
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4032148543
Short name T163
Test name
Test status
Simulation time 38933017 ps
CPU time 1.15 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 220008 kb
Host smart-1c310914-c938-4dfe-a7c4-27d71cb82330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032148543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4032148543
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2682282258
Short name T541
Test name
Test status
Simulation time 83508929 ps
CPU time 0.93 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 215516 kb
Host smart-85ea5009-2162-40f8-913a-734be382cc1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682282258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2682282258
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2507197800
Short name T447
Test name
Test status
Simulation time 32981523 ps
CPU time 0.81 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 215764 kb
Host smart-116b218b-544c-4231-8995-89474959e580
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507197800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2507197800
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1695361971
Short name T122
Test name
Test status
Simulation time 26323378 ps
CPU time 1.1 seconds
Started Jul 01 05:38:07 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 217384 kb
Host smart-ea28f725-06d7-4e67-a221-f87ec5db051e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695361971 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1695361971
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.64229429
Short name T596
Test name
Test status
Simulation time 21170144 ps
CPU time 0.95 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 218576 kb
Host smart-dab10fc7-3ec6-4de8-9e84-30dceed6f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64229429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.64229429
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3841215275
Short name T318
Test name
Test status
Simulation time 43317832 ps
CPU time 1.44 seconds
Started Jul 01 05:38:04 PM PDT 24
Finished Jul 01 05:38:06 PM PDT 24
Peak memory 219020 kb
Host smart-11deb1e1-6dd1-4b09-9717-bbda321d1c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841215275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3841215275
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_smoke.1157275541
Short name T362
Test name
Test status
Simulation time 19179176 ps
CPU time 0.99 seconds
Started Jul 01 05:37:58 PM PDT 24
Finished Jul 01 05:38:00 PM PDT 24
Peak memory 215740 kb
Host smart-d9ee5cef-d17f-442e-aabc-c46416465f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157275541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1157275541
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3578263074
Short name T947
Test name
Test status
Simulation time 425796560 ps
CPU time 2.18 seconds
Started Jul 01 05:38:05 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 215732 kb
Host smart-11bf1555-d794-4818-87f0-634e246cbef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578263074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3578263074
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2554311764
Short name T783
Test name
Test status
Simulation time 108046434340 ps
CPU time 733.78 seconds
Started Jul 01 05:37:59 PM PDT 24
Finished Jul 01 05:50:15 PM PDT 24
Peak memory 224080 kb
Host smart-2e03a29b-245f-4dfa-a347-a39837754c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554311764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2554311764
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3077655038
Short name T391
Test name
Test status
Simulation time 28268941 ps
CPU time 1.3 seconds
Started Jul 01 05:38:08 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 216040 kb
Host smart-2efa2fc1-1dc1-4574-ba35-14f1032125f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077655038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3077655038
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.4029305232
Short name T906
Test name
Test status
Simulation time 11042492 ps
CPU time 0.88 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 207112 kb
Host smart-2b3e03d6-f8d2-49f9-a97f-d1e668668f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029305232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4029305232
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1199486841
Short name T369
Test name
Test status
Simulation time 48093861 ps
CPU time 0.8 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 215812 kb
Host smart-fa3ad76f-9f35-479c-94b4-c1a2b23e1370
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199486841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1199486841
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3859211729
Short name T814
Test name
Test status
Simulation time 97530200 ps
CPU time 1.1 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:08 PM PDT 24
Peak memory 218904 kb
Host smart-ff8903f0-b299-485e-87e3-e5815074782c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859211729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3859211729
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2732416272
Short name T160
Test name
Test status
Simulation time 24195866 ps
CPU time 0.9 seconds
Started Jul 01 05:38:03 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 218852 kb
Host smart-1eec1c8e-9f51-4f0f-91ef-b547b33ff155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732416272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2732416272
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1192777630
Short name T501
Test name
Test status
Simulation time 52598964 ps
CPU time 1.16 seconds
Started Jul 01 05:38:04 PM PDT 24
Finished Jul 01 05:38:07 PM PDT 24
Peak memory 219184 kb
Host smart-c7b627c0-6478-4f7a-9c13-475431149372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192777630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1192777630
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4086307272
Short name T34
Test name
Test status
Simulation time 24138259 ps
CPU time 1.06 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 216156 kb
Host smart-29c14c1f-f343-4fdf-9b21-de34600927b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086307272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4086307272
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3808742218
Short name T747
Test name
Test status
Simulation time 15800912 ps
CPU time 0.94 seconds
Started Jul 01 05:38:04 PM PDT 24
Finished Jul 01 05:38:06 PM PDT 24
Peak memory 215644 kb
Host smart-b714420d-117f-440c-89f3-6d9d8814a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808742218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3808742218
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3018911915
Short name T843
Test name
Test status
Simulation time 81333844 ps
CPU time 1.24 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 207520 kb
Host smart-c4a54f11-782c-4d52-8984-1ee43e460d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018911915 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3018911915
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2301230880
Short name T404
Test name
Test status
Simulation time 261116458380 ps
CPU time 1735.75 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 06:07:15 PM PDT 24
Peak memory 227972 kb
Host smart-dc82bb5b-cc1b-4883-b5d2-8464f0c0818f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301230880 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2301230880
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3127449645
Short name T124
Test name
Test status
Simulation time 25144034 ps
CPU time 1.23 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:38:14 PM PDT 24
Peak memory 219080 kb
Host smart-8543c251-c93c-488a-ae2d-f0c6fd8cdfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127449645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3127449645
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4193654439
Short name T373
Test name
Test status
Simulation time 41689633 ps
CPU time 1.12 seconds
Started Jul 01 05:38:08 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 207184 kb
Host smart-c1407ddf-b0fb-4b99-9882-249411442265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193654439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4193654439
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.488906671
Short name T737
Test name
Test status
Simulation time 14106013 ps
CPU time 0.91 seconds
Started Jul 01 05:38:07 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 218668 kb
Host smart-0011d169-54db-4b8d-8d9b-f0a0611bf3d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488906671 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.488906671
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.3706354406
Short name T375
Test name
Test status
Simulation time 38815671 ps
CPU time 1.24 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 220180 kb
Host smart-bdf2435b-95d8-4a69-97d9-7f6f8b4445e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706354406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3706354406
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.740371593
Short name T558
Test name
Test status
Simulation time 25845626 ps
CPU time 0.97 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 215736 kb
Host smart-8b622087-fb8a-4aa1-b7e7-f19e7540e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740371593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.740371593
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3496279206
Short name T510
Test name
Test status
Simulation time 91745903 ps
CPU time 0.92 seconds
Started Jul 01 05:38:06 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 215740 kb
Host smart-32b4b275-e994-4a48-a622-de90c61afc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496279206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3496279206
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.50300409
Short name T242
Test name
Test status
Simulation time 110409922 ps
CPU time 2.54 seconds
Started Jul 01 05:38:05 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 217696 kb
Host smart-1df434cd-d955-40ac-8eca-09f23dcd592e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50300409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.50300409
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.279963240
Short name T231
Test name
Test status
Simulation time 56784405862 ps
CPU time 639.21 seconds
Started Jul 01 05:38:05 PM PDT 24
Finished Jul 01 05:48:46 PM PDT 24
Peak memory 218120 kb
Host smart-bc42e85e-47c1-4c10-8345-494ae2c566c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279963240 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.279963240
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.411162996
Short name T298
Test name
Test status
Simulation time 24880197 ps
CPU time 1.19 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 220156 kb
Host smart-81462471-a914-41ed-8a49-9144a7528f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411162996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.411162996
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2126198185
Short name T464
Test name
Test status
Simulation time 27708515 ps
CPU time 0.95 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 215240 kb
Host smart-f542f46c-0937-4bb8-aeba-a148c9674eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126198185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2126198185
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4061333501
Short name T489
Test name
Test status
Simulation time 38088723 ps
CPU time 0.83 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:38:14 PM PDT 24
Peak memory 216676 kb
Host smart-546904a7-9dbc-4bd1-92d9-33a19eb14a3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061333501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4061333501
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2537849925
Short name T624
Test name
Test status
Simulation time 67075814 ps
CPU time 1.07 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:38:13 PM PDT 24
Peak memory 220208 kb
Host smart-bacff6a1-9101-4fc2-958d-46da74800e4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537849925 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2537849925
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1922497378
Short name T904
Test name
Test status
Simulation time 25771461 ps
CPU time 0.99 seconds
Started Jul 01 05:38:13 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 224056 kb
Host smart-ad7ee9f2-7ba4-4035-8a49-23e5aabc0208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922497378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1922497378
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1922650159
Short name T26
Test name
Test status
Simulation time 109506879 ps
CPU time 1.41 seconds
Started Jul 01 05:38:14 PM PDT 24
Finished Jul 01 05:38:17 PM PDT 24
Peak memory 217788 kb
Host smart-75aa6f2c-5e4e-49c4-9612-9b43ee8e4cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922650159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1922650159
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.326442963
Short name T57
Test name
Test status
Simulation time 20612007 ps
CPU time 1.22 seconds
Started Jul 01 05:38:13 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 224416 kb
Host smart-35aa1447-5e2c-46d8-a8e6-f89f3c3d3fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326442963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.326442963
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.420466045
Short name T750
Test name
Test status
Simulation time 25746116 ps
CPU time 0.94 seconds
Started Jul 01 05:38:10 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 215684 kb
Host smart-e0dabf55-ad52-449b-9a89-5981ec30a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420466045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.420466045
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.466166722
Short name T659
Test name
Test status
Simulation time 851537867 ps
CPU time 3.16 seconds
Started Jul 01 05:38:20 PM PDT 24
Finished Jul 01 05:38:25 PM PDT 24
Peak memory 217500 kb
Host smart-4c1be187-147d-48e1-bf9a-6b48bc7a3706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466166722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.466166722
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1343936838
Short name T235
Test name
Test status
Simulation time 53742394909 ps
CPU time 1223.59 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:58:35 PM PDT 24
Peak memory 224044 kb
Host smart-28bd0a9d-4df3-425e-a1c7-fac9a0af333f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343936838 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1343936838
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.200061600
Short name T533
Test name
Test status
Simulation time 22669280 ps
CPU time 0.9 seconds
Started Jul 01 05:38:13 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 215516 kb
Host smart-d03bfa23-6d96-42d8-b1c4-d68b980fd78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200061600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.200061600
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3514076240
Short name T143
Test name
Test status
Simulation time 74090788 ps
CPU time 1.26 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 219792 kb
Host smart-dfd93ff7-5638-4468-88f6-4f32babf6061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514076240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3514076240
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1069416353
Short name T173
Test name
Test status
Simulation time 19287125 ps
CPU time 1.12 seconds
Started Jul 01 05:38:10 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 224300 kb
Host smart-e6d39dae-a713-44fc-b11c-2098264185fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069416353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1069416353
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2654961277
Short name T476
Test name
Test status
Simulation time 90427153 ps
CPU time 1.15 seconds
Started Jul 01 05:38:09 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 217688 kb
Host smart-64a69e42-9069-4970-8278-577161717e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654961277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2654961277
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3457990222
Short name T666
Test name
Test status
Simulation time 23765168 ps
CPU time 0.95 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:38:14 PM PDT 24
Peak memory 216108 kb
Host smart-ea0035ea-dc01-4aec-ac49-799fa8f2ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457990222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3457990222
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1094043662
Short name T384
Test name
Test status
Simulation time 16793689 ps
CPU time 1.04 seconds
Started Jul 01 05:38:14 PM PDT 24
Finished Jul 01 05:38:17 PM PDT 24
Peak memory 215644 kb
Host smart-9fb56898-422b-49cb-9211-a034b3a101c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094043662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1094043662
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.947329873
Short name T539
Test name
Test status
Simulation time 16871115 ps
CPU time 0.97 seconds
Started Jul 01 05:38:13 PM PDT 24
Finished Jul 01 05:38:16 PM PDT 24
Peak memory 206884 kb
Host smart-25745e42-a52f-447b-a813-4f8d6fa10ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947329873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.947329873
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.779159016
Short name T424
Test name
Test status
Simulation time 31379389819 ps
CPU time 718.96 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:50:12 PM PDT 24
Peak memory 218260 kb
Host smart-9f34a7d9-e0a1-4f9c-8485-563433b96bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779159016 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.779159016
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2742788983
Short name T830
Test name
Test status
Simulation time 64533096 ps
CPU time 1.18 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 221488 kb
Host smart-1e3014fa-717b-4262-9d83-d9291e1ac7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742788983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2742788983
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3780051845
Short name T846
Test name
Test status
Simulation time 36433270 ps
CPU time 0.96 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:19 PM PDT 24
Peak memory 207000 kb
Host smart-9110e639-e5bb-40a7-9d41-c185e3ba5ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780051845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3780051845
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2235128965
Short name T888
Test name
Test status
Simulation time 19706094 ps
CPU time 0.85 seconds
Started Jul 01 05:38:21 PM PDT 24
Finished Jul 01 05:38:23 PM PDT 24
Peak memory 216588 kb
Host smart-e20c07d4-b8c8-412d-97cd-c1605d056625
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235128965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2235128965
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2614310514
Short name T613
Test name
Test status
Simulation time 38414474 ps
CPU time 1.32 seconds
Started Jul 01 05:38:20 PM PDT 24
Finished Jul 01 05:38:23 PM PDT 24
Peak memory 217188 kb
Host smart-b3a353eb-2ebc-4193-b740-ced5b9660b8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614310514 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2614310514
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3305378006
Short name T930
Test name
Test status
Simulation time 27782040 ps
CPU time 1.18 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:19 PM PDT 24
Peak memory 221056 kb
Host smart-e1b284ec-ab12-495b-96df-c3b4ad1d2af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305378006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3305378006
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.567432305
Short name T714
Test name
Test status
Simulation time 89950446 ps
CPU time 0.86 seconds
Started Jul 01 05:38:16 PM PDT 24
Finished Jul 01 05:38:18 PM PDT 24
Peak memory 215512 kb
Host smart-9c07684a-270d-4fd6-98ac-ac7acce09dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567432305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.567432305
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3747816449
Short name T356
Test name
Test status
Simulation time 129544062 ps
CPU time 0.95 seconds
Started Jul 01 05:38:11 PM PDT 24
Finished Jul 01 05:38:14 PM PDT 24
Peak memory 215828 kb
Host smart-6bf0ddee-6804-44b2-8a84-43aeb84ee0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747816449 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3747816449
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3369405131
Short name T762
Test name
Test status
Simulation time 237488234 ps
CPU time 5.11 seconds
Started Jul 01 05:38:14 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 217696 kb
Host smart-deee5caa-0e23-4284-b880-3b632182f067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369405131 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3369405131
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.998173019
Short name T849
Test name
Test status
Simulation time 172844808368 ps
CPU time 1208.16 seconds
Started Jul 01 05:38:12 PM PDT 24
Finished Jul 01 05:58:22 PM PDT 24
Peak memory 224088 kb
Host smart-64db912f-b7c3-49a9-9566-bfdf8d588c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998173019 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.998173019
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3310318785
Short name T436
Test name
Test status
Simulation time 180744935 ps
CPU time 1.11 seconds
Started Jul 01 05:35:46 PM PDT 24
Finished Jul 01 05:35:48 PM PDT 24
Peak memory 219296 kb
Host smart-8de0e2b0-73b4-49af-8ed7-13f29a473d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310318785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3310318785
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.137917720
Short name T399
Test name
Test status
Simulation time 58380512 ps
CPU time 0.94 seconds
Started Jul 01 05:35:47 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 215416 kb
Host smart-6f631b05-b5df-4220-bb21-3dbed46a6c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137917720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.137917720
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1635654215
Short name T213
Test name
Test status
Simulation time 25681248 ps
CPU time 0.81 seconds
Started Jul 01 05:35:48 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 216752 kb
Host smart-dbe35819-1182-48f0-8983-b663e7795c83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635654215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1635654215
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1935853468
Short name T406
Test name
Test status
Simulation time 124063000 ps
CPU time 1.27 seconds
Started Jul 01 05:35:46 PM PDT 24
Finished Jul 01 05:35:48 PM PDT 24
Peak memory 217092 kb
Host smart-ae21bf2f-c95b-41c2-a127-2b00326f81d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935853468 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1935853468
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2187239856
Short name T167
Test name
Test status
Simulation time 35944631 ps
CPU time 0.89 seconds
Started Jul 01 05:35:46 PM PDT 24
Finished Jul 01 05:35:48 PM PDT 24
Peak memory 218736 kb
Host smart-73c82933-ebdd-484e-99fb-0be58353ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187239856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2187239856
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1044864538
Short name T977
Test name
Test status
Simulation time 56810926 ps
CPU time 1.21 seconds
Started Jul 01 05:35:47 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 218928 kb
Host smart-890df686-612c-4921-9589-90fb60e1a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044864538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1044864538
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.938034704
Short name T16
Test name
Test status
Simulation time 54240703 ps
CPU time 1.44 seconds
Started Jul 01 05:35:44 PM PDT 24
Finished Jul 01 05:35:47 PM PDT 24
Peak memory 225508 kb
Host smart-50723161-2555-4cc7-95aa-3be575702d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938034704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.938034704
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.601483385
Short name T328
Test name
Test status
Simulation time 64697225 ps
CPU time 0.91 seconds
Started Jul 01 05:35:48 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 207360 kb
Host smart-794ddcfa-6daa-478a-8000-53c2cd759c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601483385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.601483385
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.848083903
Short name T698
Test name
Test status
Simulation time 35658079 ps
CPU time 0.92 seconds
Started Jul 01 05:35:39 PM PDT 24
Finished Jul 01 05:35:41 PM PDT 24
Peak memory 215592 kb
Host smart-835c2499-10a7-407f-bbfc-576402d8d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848083903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.848083903
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.254333473
Short name T758
Test name
Test status
Simulation time 1567687933 ps
CPU time 4.23 seconds
Started Jul 01 05:35:46 PM PDT 24
Finished Jul 01 05:35:52 PM PDT 24
Peak memory 220368 kb
Host smart-7d683bbf-b444-43c5-bd6d-d3ad7edd56bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254333473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.254333473
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1012151496
Short name T968
Test name
Test status
Simulation time 36063272934 ps
CPU time 785.09 seconds
Started Jul 01 05:35:47 PM PDT 24
Finished Jul 01 05:48:53 PM PDT 24
Peak memory 224052 kb
Host smart-2091acc8-8bd2-481a-a443-4712b741e9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012151496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1012151496
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2545373981
Short name T972
Test name
Test status
Simulation time 93470800 ps
CPU time 1.16 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 221156 kb
Host smart-779f10e5-7ecb-4e94-9b94-93fd7108b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545373981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2545373981
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3906415422
Short name T166
Test name
Test status
Simulation time 27486155 ps
CPU time 0.84 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 218660 kb
Host smart-e3e9a64d-3c59-4100-80c6-33fdf4031e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906415422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3906415422
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3956723020
Short name T560
Test name
Test status
Simulation time 94499058 ps
CPU time 1.17 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 217708 kb
Host smart-c46eacdc-1243-4450-8a88-11107352885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956723020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3956723020
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1258597656
Short name T644
Test name
Test status
Simulation time 72897246 ps
CPU time 1.1 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 220116 kb
Host smart-35e2e245-cadf-44d7-b882-e4d4fd0fe44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258597656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1258597656
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3730203655
Short name T848
Test name
Test status
Simulation time 32010629 ps
CPU time 1.16 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 218784 kb
Host smart-f62310df-df84-4242-a63a-8dec7d23302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730203655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3730203655
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4019680829
Short name T43
Test name
Test status
Simulation time 55320037 ps
CPU time 1.28 seconds
Started Jul 01 05:38:15 PM PDT 24
Finished Jul 01 05:38:18 PM PDT 24
Peak memory 218844 kb
Host smart-65a2c6bd-8585-4d5c-864f-8cfe3dc110dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019680829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4019680829
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.4092286222
Short name T573
Test name
Test status
Simulation time 50998478 ps
CPU time 1.17 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 219412 kb
Host smart-c0ebfd9f-9dfe-453c-bae1-e59ca20ec2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092286222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.4092286222
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3651908539
Short name T195
Test name
Test status
Simulation time 19186044 ps
CPU time 1.18 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 229940 kb
Host smart-df0e24b3-43b2-4210-a128-5154f9a4bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651908539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3651908539
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.822239833
Short name T462
Test name
Test status
Simulation time 89335522 ps
CPU time 1.19 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 217736 kb
Host smart-156c3547-f9e4-443e-a5c4-a83db2b69521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822239833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.822239833
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3532702471
Short name T594
Test name
Test status
Simulation time 85476847 ps
CPU time 1.1 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:19 PM PDT 24
Peak memory 220308 kb
Host smart-41f41bc5-7502-4450-8852-91426051725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532702471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3532702471
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.713896722
Short name T127
Test name
Test status
Simulation time 87737920 ps
CPU time 1.04 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 229716 kb
Host smart-66798a2a-78f2-4ecf-a229-0fdd6c02606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713896722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.713896722
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1211187222
Short name T461
Test name
Test status
Simulation time 44548798 ps
CPU time 1.22 seconds
Started Jul 01 05:38:15 PM PDT 24
Finished Jul 01 05:38:17 PM PDT 24
Peak memory 217664 kb
Host smart-7c06f5bc-9a5e-493e-9eb5-e89fee6057c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211187222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1211187222
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1199365101
Short name T773
Test name
Test status
Simulation time 73855610 ps
CPU time 1.11 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 218968 kb
Host smart-e8687331-8e3b-415f-8f43-5005db065c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199365101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1199365101
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.4019788849
Short name T113
Test name
Test status
Simulation time 23815193 ps
CPU time 1.18 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:22 PM PDT 24
Peak memory 220136 kb
Host smart-2805c4f3-b65b-43f9-80b8-b057b5f0697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019788849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.4019788849
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2865658848
Short name T535
Test name
Test status
Simulation time 48529662 ps
CPU time 1.46 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 219280 kb
Host smart-e74e391b-33db-48d1-b497-c43018c1b193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865658848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2865658848
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2331571059
Short name T587
Test name
Test status
Simulation time 23300416 ps
CPU time 1.17 seconds
Started Jul 01 05:38:17 PM PDT 24
Finished Jul 01 05:38:20 PM PDT 24
Peak memory 219172 kb
Host smart-6a697462-7396-4dd4-8ab0-4952e0740a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331571059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2331571059
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1701318497
Short name T900
Test name
Test status
Simulation time 31804713 ps
CPU time 0.84 seconds
Started Jul 01 05:38:18 PM PDT 24
Finished Jul 01 05:38:21 PM PDT 24
Peak memory 218584 kb
Host smart-22eff8b2-273e-4c45-ae66-e08629bcfe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701318497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1701318497
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.997801412
Short name T370
Test name
Test status
Simulation time 168459980 ps
CPU time 1.6 seconds
Started Jul 01 05:38:19 PM PDT 24
Finished Jul 01 05:38:23 PM PDT 24
Peak memory 219240 kb
Host smart-e3748126-dfe0-4a70-b048-d0dc7810ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997801412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.997801412
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2432406461
Short name T161
Test name
Test status
Simulation time 76119970 ps
CPU time 1.09 seconds
Started Jul 01 05:38:24 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 220040 kb
Host smart-b4dfcbfb-0dcb-4f47-b031-b0f078ae1410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432406461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2432406461
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2081928864
Short name T368
Test name
Test status
Simulation time 83092998 ps
CPU time 1.12 seconds
Started Jul 01 05:38:22 PM PDT 24
Finished Jul 01 05:38:24 PM PDT 24
Peak memory 220024 kb
Host smart-b18cd660-8913-4daa-ac3f-9a2a5f823e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081928864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2081928864
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2413950266
Short name T390
Test name
Test status
Simulation time 83405578 ps
CPU time 1.09 seconds
Started Jul 01 05:38:30 PM PDT 24
Finished Jul 01 05:38:33 PM PDT 24
Peak memory 219976 kb
Host smart-a5659332-e9c3-4585-97f9-0a43c7721dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413950266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2413950266
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3487625108
Short name T126
Test name
Test status
Simulation time 58682871 ps
CPU time 1.03 seconds
Started Jul 01 05:38:28 PM PDT 24
Finished Jul 01 05:38:31 PM PDT 24
Peak memory 220772 kb
Host smart-d304fbc4-ce48-4afb-8f78-599a2bd39d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487625108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3487625108
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3772715285
Short name T583
Test name
Test status
Simulation time 82837068 ps
CPU time 1.51 seconds
Started Jul 01 05:38:23 PM PDT 24
Finished Jul 01 05:38:25 PM PDT 24
Peak memory 218952 kb
Host smart-0a1a3432-d898-47b3-95b8-b96ceccfc020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772715285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3772715285
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1207420306
Short name T256
Test name
Test status
Simulation time 153054233 ps
CPU time 1.28 seconds
Started Jul 01 05:38:25 PM PDT 24
Finished Jul 01 05:38:27 PM PDT 24
Peak memory 216100 kb
Host smart-1a3081a9-9102-498c-b654-1c525e30fffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207420306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1207420306
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1885038480
Short name T940
Test name
Test status
Simulation time 23771877 ps
CPU time 1.33 seconds
Started Jul 01 05:38:25 PM PDT 24
Finished Jul 01 05:38:27 PM PDT 24
Peak memory 224492 kb
Host smart-a1c7b1ba-bdb4-4dc9-99de-133867507bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885038480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1885038480
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3064758712
Short name T454
Test name
Test status
Simulation time 42833205 ps
CPU time 1.12 seconds
Started Jul 01 05:38:28 PM PDT 24
Finished Jul 01 05:38:31 PM PDT 24
Peak memory 218704 kb
Host smart-8012e7ac-c198-43a0-af47-6ae54a57fb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064758712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3064758712
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3216533352
Short name T449
Test name
Test status
Simulation time 23487599 ps
CPU time 1.18 seconds
Started Jul 01 05:38:26 PM PDT 24
Finished Jul 01 05:38:28 PM PDT 24
Peak memory 220888 kb
Host smart-a06535b9-d01d-4408-aee4-42d444aca005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216533352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3216533352
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.864824427
Short name T15
Test name
Test status
Simulation time 26098082 ps
CPU time 1.06 seconds
Started Jul 01 05:38:24 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 224396 kb
Host smart-67ac0206-a472-414b-b8b8-4f12a979cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864824427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.864824427
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4015230061
Short name T315
Test name
Test status
Simulation time 41397030 ps
CPU time 1.26 seconds
Started Jul 01 05:38:24 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 217708 kb
Host smart-e3521189-6604-4142-b31f-c0d538498b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015230061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4015230061
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2333004360
Short name T184
Test name
Test status
Simulation time 36148081 ps
CPU time 1.24 seconds
Started Jul 01 05:35:55 PM PDT 24
Finished Jul 01 05:35:57 PM PDT 24
Peak memory 219152 kb
Host smart-a246fcc2-d33d-4f12-aaa4-4441f6fc702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333004360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2333004360
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1879196631
Short name T430
Test name
Test status
Simulation time 27674937 ps
CPU time 0.94 seconds
Started Jul 01 05:35:49 PM PDT 24
Finished Jul 01 05:35:51 PM PDT 24
Peak memory 207076 kb
Host smart-9f935064-021b-4fcd-83e5-eeb562ca247b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879196631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1879196631
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1189215918
Short name T218
Test name
Test status
Simulation time 38050767 ps
CPU time 0.84 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:54 PM PDT 24
Peak memory 215752 kb
Host smart-01fef6f8-097b-4bb3-8673-b2306a2a7571
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189215918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1189215918
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2630146235
Short name T695
Test name
Test status
Simulation time 121408189 ps
CPU time 1 seconds
Started Jul 01 05:35:53 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 217280 kb
Host smart-7ff7bd47-0a0e-414d-bd19-b123a4bbba35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630146235 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2630146235
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.58848091
Short name T494
Test name
Test status
Simulation time 68094942 ps
CPU time 1.03 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:35:54 PM PDT 24
Peak memory 224400 kb
Host smart-556f161b-2cc8-4ba2-a3be-c46da6a18a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58848091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.58848091
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2354637376
Short name T355
Test name
Test status
Simulation time 46094365 ps
CPU time 1.37 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:35:54 PM PDT 24
Peak memory 218828 kb
Host smart-fd213e98-6f0e-43fa-a32a-83cd6e6dd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354637376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2354637376
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3124801476
Short name T89
Test name
Test status
Simulation time 21097636 ps
CPU time 1.06 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 215948 kb
Host smart-54a480bb-2eb2-4d29-a7dd-1168e225696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124801476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3124801476
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.225136543
Short name T776
Test name
Test status
Simulation time 55795032 ps
CPU time 0.92 seconds
Started Jul 01 05:35:45 PM PDT 24
Finished Jul 01 05:35:47 PM PDT 24
Peak memory 207456 kb
Host smart-ef485c4d-bbf1-4d2c-92f1-4b3f164e8b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225136543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.225136543
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.46527740
Short name T452
Test name
Test status
Simulation time 62101403 ps
CPU time 0.88 seconds
Started Jul 01 05:35:48 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 207520 kb
Host smart-ceee9f6e-815d-4f1e-897b-1a46cab02f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46527740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.46527740
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3533668510
Short name T971
Test name
Test status
Simulation time 566776288 ps
CPU time 2.96 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:57 PM PDT 24
Peak memory 217756 kb
Host smart-3eec7462-27ba-4928-96f4-580ff9062dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533668510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3533668510
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1666346455
Short name T531
Test name
Test status
Simulation time 28120460489 ps
CPU time 168.37 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 223684 kb
Host smart-a94962cc-2b22-485f-9951-ce7ed75186b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666346455 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1666346455
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3865675010
Short name T948
Test name
Test status
Simulation time 66236741 ps
CPU time 1.14 seconds
Started Jul 01 05:38:23 PM PDT 24
Finished Jul 01 05:38:25 PM PDT 24
Peak memory 218832 kb
Host smart-75fa6656-a71a-43be-b646-feee4f379d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865675010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3865675010
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.326058399
Short name T61
Test name
Test status
Simulation time 60587042 ps
CPU time 1.09 seconds
Started Jul 01 05:38:25 PM PDT 24
Finished Jul 01 05:38:27 PM PDT 24
Peak memory 232576 kb
Host smart-5690ae8b-9be1-48b3-be5d-4fd5c658091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326058399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.326058399
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1124340383
Short name T22
Test name
Test status
Simulation time 27775116 ps
CPU time 1.15 seconds
Started Jul 01 05:38:24 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 218016 kb
Host smart-bf3e78e7-e681-4346-9ff0-8dcdb4a19593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124340383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1124340383
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2229912226
Short name T46
Test name
Test status
Simulation time 47492817 ps
CPU time 1.26 seconds
Started Jul 01 05:38:30 PM PDT 24
Finished Jul 01 05:38:33 PM PDT 24
Peak memory 219784 kb
Host smart-b416f5c2-5f58-4305-a763-bc809a334263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229912226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2229912226
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.4052806762
Short name T59
Test name
Test status
Simulation time 61827540 ps
CPU time 0.99 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 224128 kb
Host smart-6025b148-6886-4e98-b095-4b285d02ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052806762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.4052806762
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.301671004
Short name T905
Test name
Test status
Simulation time 39014089 ps
CPU time 1.53 seconds
Started Jul 01 05:38:24 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 217896 kb
Host smart-baa295f4-01a6-47e1-b8cf-a19f6a93885f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301671004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.301671004
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.307831543
Short name T68
Test name
Test status
Simulation time 73490622 ps
CPU time 1.14 seconds
Started Jul 01 05:38:31 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 220176 kb
Host smart-8c7e3d15-9c92-440a-876b-87c56089e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307831543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.307831543
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.28448359
Short name T736
Test name
Test status
Simulation time 28345636 ps
CPU time 1.01 seconds
Started Jul 01 05:38:31 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 220208 kb
Host smart-fb92f3a1-4391-4a60-9462-8e8edbb98d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28448359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.28448359
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2354895143
Short name T338
Test name
Test status
Simulation time 69813682 ps
CPU time 1.38 seconds
Started Jul 01 05:38:31 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 219496 kb
Host smart-92caea2c-f1c3-405e-a112-5e76b8fac8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354895143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2354895143
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3451955326
Short name T455
Test name
Test status
Simulation time 26719682 ps
CPU time 1.24 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 219004 kb
Host smart-d31f460b-b18f-4d34-b38a-eb32578abf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451955326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3451955326
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1284989163
Short name T372
Test name
Test status
Simulation time 38779189 ps
CPU time 1.02 seconds
Started Jul 01 05:38:28 PM PDT 24
Finished Jul 01 05:38:31 PM PDT 24
Peak memory 224336 kb
Host smart-5224bad6-e61f-406d-9a74-e7059a691dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284989163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1284989163
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.148545790
Short name T967
Test name
Test status
Simulation time 43478800 ps
CPU time 1.06 seconds
Started Jul 01 05:38:34 PM PDT 24
Finished Jul 01 05:38:36 PM PDT 24
Peak memory 217756 kb
Host smart-da0c671d-44f3-400f-bdfe-399ab687fdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148545790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.148545790
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3928425301
Short name T254
Test name
Test status
Simulation time 203655351 ps
CPU time 1.21 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 220784 kb
Host smart-0399608f-ad57-421d-9daa-849e1d9631d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928425301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3928425301
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1449095321
Short name T474
Test name
Test status
Simulation time 18760075 ps
CPU time 1.14 seconds
Started Jul 01 05:38:27 PM PDT 24
Finished Jul 01 05:38:29 PM PDT 24
Peak memory 224308 kb
Host smart-71149680-fcea-45bd-90a4-0f8320c12994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449095321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1449095321
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1856121672
Short name T711
Test name
Test status
Simulation time 78887537 ps
CPU time 1.26 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 218996 kb
Host smart-f1029953-928a-439c-adb8-cd1cb1212445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856121672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1856121672
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1513752057
Short name T853
Test name
Test status
Simulation time 75000422 ps
CPU time 1.17 seconds
Started Jul 01 05:38:30 PM PDT 24
Finished Jul 01 05:38:33 PM PDT 24
Peak memory 219912 kb
Host smart-cec59451-c1ad-431f-a4aa-08063294c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513752057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1513752057
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1018801643
Short name T180
Test name
Test status
Simulation time 23382876 ps
CPU time 1.13 seconds
Started Jul 01 05:38:27 PM PDT 24
Finished Jul 01 05:38:29 PM PDT 24
Peak memory 224372 kb
Host smart-9be18c37-2b7e-43da-ac2d-0ea4a0f1c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018801643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1018801643
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1240028079
Short name T307
Test name
Test status
Simulation time 48138928 ps
CPU time 1.26 seconds
Started Jul 01 05:38:27 PM PDT 24
Finished Jul 01 05:38:29 PM PDT 24
Peak memory 219096 kb
Host smart-284b6a7c-f0d4-460c-9716-0e01b8fa6d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240028079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1240028079
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1368909851
Short name T586
Test name
Test status
Simulation time 179379464 ps
CPU time 1.27 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 218900 kb
Host smart-df50531b-5a9a-4bc5-a417-7cce184d1849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368909851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1368909851
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3224419644
Short name T164
Test name
Test status
Simulation time 18110133 ps
CPU time 1.19 seconds
Started Jul 01 05:38:31 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 224316 kb
Host smart-4cc78633-dfcf-4a00-b7c2-c06c043b5a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224419644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3224419644
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1355579463
Short name T869
Test name
Test status
Simulation time 170134252 ps
CPU time 1.67 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:33 PM PDT 24
Peak memory 220272 kb
Host smart-8614adde-3a6b-447b-b5d2-fc2cabc5ff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355579463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1355579463
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3312829456
Short name T154
Test name
Test status
Simulation time 34701416 ps
CPU time 0.96 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 218808 kb
Host smart-77f09505-afd2-434f-a1fb-2a5bbaca169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312829456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3312829456
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3955035827
Short name T775
Test name
Test status
Simulation time 47241687 ps
CPU time 1.81 seconds
Started Jul 01 05:38:29 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 218932 kb
Host smart-52e4fee4-32ca-485c-89f2-829118c03c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955035827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3955035827
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1485435140
Short name T640
Test name
Test status
Simulation time 74328478 ps
CPU time 1.12 seconds
Started Jul 01 05:38:39 PM PDT 24
Finished Jul 01 05:38:43 PM PDT 24
Peak memory 219036 kb
Host smart-d7920589-c17a-4683-ab9b-176be65425e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485435140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1485435140
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1458390625
Short name T217
Test name
Test status
Simulation time 33233247 ps
CPU time 1.03 seconds
Started Jul 01 05:38:39 PM PDT 24
Finished Jul 01 05:38:43 PM PDT 24
Peak memory 224112 kb
Host smart-915c3285-e2cc-4bc2-9799-e775b0f4503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458390625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1458390625
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.119457503
Short name T31
Test name
Test status
Simulation time 50838039 ps
CPU time 1.27 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 219112 kb
Host smart-4e278738-1bfd-4c5e-a3d8-1d451a3d1192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119457503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.119457503
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.473364557
Short name T860
Test name
Test status
Simulation time 26162609 ps
CPU time 1.28 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:39 PM PDT 24
Peak memory 219072 kb
Host smart-742d20db-6c9e-4806-af32-8dd5e93b0e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473364557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.473364557
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2085904555
Short name T771
Test name
Test status
Simulation time 36581238 ps
CPU time 1.06 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 229808 kb
Host smart-ae872714-89c0-45cb-ab5d-3b7cbe64eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085904555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2085904555
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1516067972
Short name T463
Test name
Test status
Simulation time 35435854 ps
CPU time 1.56 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 220588 kb
Host smart-3f7534b1-36f3-4984-a3ea-31df8d147ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516067972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1516067972
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1300796089
Short name T789
Test name
Test status
Simulation time 36491215 ps
CPU time 1.22 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 221264 kb
Host smart-ee0e2757-12be-43bd-be63-e8de846382bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300796089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1300796089
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1495233095
Short name T109
Test name
Test status
Simulation time 70849161 ps
CPU time 0.8 seconds
Started Jul 01 05:35:58 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 207208 kb
Host smart-24262ea9-0d7e-44d3-9cf1-dd502909ced9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495233095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1495233095
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2845709120
Short name T169
Test name
Test status
Simulation time 92871240 ps
CPU time 0.84 seconds
Started Jul 01 05:35:57 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 216656 kb
Host smart-804ae4e6-db4c-41b1-bcb2-49f1c01c98f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845709120 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2845709120
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1364005007
Short name T149
Test name
Test status
Simulation time 47127477 ps
CPU time 1.57 seconds
Started Jul 01 05:35:57 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 217424 kb
Host smart-4e532f25-2a4f-44ba-9656-558779ad8f39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364005007 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1364005007
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1061139435
Short name T453
Test name
Test status
Simulation time 27406106 ps
CPU time 0.83 seconds
Started Jul 01 05:35:56 PM PDT 24
Finished Jul 01 05:35:57 PM PDT 24
Peak memory 218628 kb
Host smart-bb58e8ba-8397-4c8f-b204-b4d671006656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061139435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1061139435
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2078732334
Short name T507
Test name
Test status
Simulation time 96089220 ps
CPU time 1.22 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 219256 kb
Host smart-2bf2c636-6348-4ed5-92d0-467f9b3be46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078732334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2078732334
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1845109442
Short name T94
Test name
Test status
Simulation time 21886484 ps
CPU time 1.11 seconds
Started Jul 01 05:35:52 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 216228 kb
Host smart-122d2aa1-8274-48bc-9621-2e9938dbc714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845109442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1845109442
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.540660084
Short name T679
Test name
Test status
Simulation time 18205585 ps
CPU time 0.99 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:35:54 PM PDT 24
Peak memory 207460 kb
Host smart-e6c4631a-a18e-4442-ae89-d4dfe1a0fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540660084 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.540660084
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4194560254
Short name T366
Test name
Test status
Simulation time 45902700 ps
CPU time 0.88 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:35:53 PM PDT 24
Peak memory 215652 kb
Host smart-b4321777-6b53-4724-9e49-14df24278bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194560254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4194560254
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4288100213
Short name T468
Test name
Test status
Simulation time 52151910 ps
CPU time 1.55 seconds
Started Jul 01 05:35:53 PM PDT 24
Finished Jul 01 05:35:56 PM PDT 24
Peak memory 215636 kb
Host smart-03c29575-c707-47c2-a34a-5d6be4828e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288100213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4288100213
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2987586242
Short name T230
Test name
Test status
Simulation time 19771283420 ps
CPU time 448.77 seconds
Started Jul 01 05:35:51 PM PDT 24
Finished Jul 01 05:43:22 PM PDT 24
Peak memory 218744 kb
Host smart-2017fec4-9a3a-45bc-a89e-2a39f9e9ae1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987586242 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2987586242
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.736559107
Short name T722
Test name
Test status
Simulation time 41662470 ps
CPU time 1.09 seconds
Started Jul 01 05:38:38 PM PDT 24
Finished Jul 01 05:38:42 PM PDT 24
Peak memory 218676 kb
Host smart-67d690e3-86f4-4179-96d8-987b0f4f2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736559107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.736559107
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2488876725
Short name T158
Test name
Test status
Simulation time 19409670 ps
CPU time 1.22 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 224444 kb
Host smart-e8aa72c9-8485-4bc7-9c18-1dbe10c6118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488876725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2488876725
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3832008636
Short name T766
Test name
Test status
Simulation time 54135564 ps
CPU time 1.45 seconds
Started Jul 01 05:38:35 PM PDT 24
Finished Jul 01 05:38:37 PM PDT 24
Peak memory 219296 kb
Host smart-f47fc8c0-7703-42ce-8630-da14227d3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832008636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3832008636
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2359751105
Short name T252
Test name
Test status
Simulation time 49018491 ps
CPU time 1.19 seconds
Started Jul 01 05:38:41 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 219904 kb
Host smart-ffb71fcb-8dd4-45f3-b8d7-80cbf2d77fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359751105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2359751105
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3139389648
Short name T7
Test name
Test status
Simulation time 65556991 ps
CPU time 1.18 seconds
Started Jul 01 05:38:38 PM PDT 24
Finished Jul 01 05:38:42 PM PDT 24
Peak memory 220012 kb
Host smart-4e405896-4732-4a88-8b54-a1fbec507b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139389648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3139389648
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3792739800
Short name T473
Test name
Test status
Simulation time 134162917 ps
CPU time 1.42 seconds
Started Jul 01 05:38:38 PM PDT 24
Finished Jul 01 05:38:42 PM PDT 24
Peak memory 219236 kb
Host smart-36ec7d93-3f81-4f5b-bf75-d60df5a5883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792739800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3792739800
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.4218253349
Short name T521
Test name
Test status
Simulation time 52888831 ps
CPU time 1.22 seconds
Started Jul 01 05:38:41 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 220080 kb
Host smart-ab438783-d513-4e47-aafb-619ecb690229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218253349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.4218253349
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3142012247
Short name T479
Test name
Test status
Simulation time 65175750 ps
CPU time 1.06 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 220264 kb
Host smart-cac8d464-9ef5-4583-ac68-3b8af5d81b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142012247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3142012247
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.791413435
Short name T582
Test name
Test status
Simulation time 28202855 ps
CPU time 1.15 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 217748 kb
Host smart-dfed5446-1730-4512-85e8-4bac5dd1d464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791413435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.791413435
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2968197552
Short name T170
Test name
Test status
Simulation time 66601979 ps
CPU time 1.07 seconds
Started Jul 01 05:38:39 PM PDT 24
Finished Jul 01 05:38:44 PM PDT 24
Peak memory 221644 kb
Host smart-7901513d-a0d1-46fe-b77d-9313052d2740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968197552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2968197552
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2437198686
Short name T937
Test name
Test status
Simulation time 36609421 ps
CPU time 0.89 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 218676 kb
Host smart-f5cbc321-491a-4500-9047-72c41c32d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437198686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2437198686
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4041636843
Short name T66
Test name
Test status
Simulation time 192660084 ps
CPU time 1.42 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:42 PM PDT 24
Peak memory 219388 kb
Host smart-3c7f98fb-6aee-4b1c-9ca1-a3174307cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041636843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4041636843
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.804262724
Short name T472
Test name
Test status
Simulation time 79630959 ps
CPU time 1.04 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:39 PM PDT 24
Peak memory 221124 kb
Host smart-c1a7f58e-94d4-4249-ba78-effb5a49c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804262724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.804262724
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2759676364
Short name T159
Test name
Test status
Simulation time 21016229 ps
CPU time 1.05 seconds
Started Jul 01 05:38:35 PM PDT 24
Finished Jul 01 05:38:38 PM PDT 24
Peak memory 224248 kb
Host smart-064ff000-ed29-4dec-b630-1864661266f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759676364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2759676364
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3325122606
Short name T811
Test name
Test status
Simulation time 45737328 ps
CPU time 1.61 seconds
Started Jul 01 05:38:35 PM PDT 24
Finished Jul 01 05:38:38 PM PDT 24
Peak memory 220220 kb
Host smart-b3862275-4a7f-467d-853d-fb8d01a4a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325122606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3325122606
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3423743841
Short name T434
Test name
Test status
Simulation time 27314987 ps
CPU time 0.85 seconds
Started Jul 01 05:38:41 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 218364 kb
Host smart-80a0e1aa-ec3b-4a7a-8972-8fbf115f2d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423743841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3423743841
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2606113883
Short name T484
Test name
Test status
Simulation time 40727635 ps
CPU time 1.17 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 217712 kb
Host smart-b79a4984-a4a0-46ae-acb7-bfb0bad792cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606113883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2606113883
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1424368569
Short name T297
Test name
Test status
Simulation time 49764474 ps
CPU time 1.2 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 221568 kb
Host smart-beace19d-7821-4683-b450-fbbb2ec413fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424368569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1424368569
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.987130981
Short name T610
Test name
Test status
Simulation time 17890292 ps
CPU time 1.15 seconds
Started Jul 01 05:38:35 PM PDT 24
Finished Jul 01 05:38:39 PM PDT 24
Peak memory 224376 kb
Host smart-0f63281f-4d2f-443d-8722-07d0dec551f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987130981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.987130981
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1546813893
Short name T746
Test name
Test status
Simulation time 92894347 ps
CPU time 1.42 seconds
Started Jul 01 05:38:39 PM PDT 24
Finished Jul 01 05:38:44 PM PDT 24
Peak memory 219360 kb
Host smart-a546a080-00cd-4669-8469-836a03462867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546813893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1546813893
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.182484643
Short name T290
Test name
Test status
Simulation time 105408316 ps
CPU time 1.23 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:39 PM PDT 24
Peak memory 218784 kb
Host smart-c5d18924-7d4f-49eb-bb5a-3ab89ea31cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182484643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.182484643
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3984181793
Short name T887
Test name
Test status
Simulation time 25761779 ps
CPU time 1.05 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:41 PM PDT 24
Peak memory 220112 kb
Host smart-2606e77d-4df2-4349-b4f3-f29af446b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984181793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3984181793
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3179248175
Short name T768
Test name
Test status
Simulation time 109178724 ps
CPU time 2.53 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:42 PM PDT 24
Peak memory 220308 kb
Host smart-e8e300d0-381a-4374-a244-2066026bbd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179248175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3179248175
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3134770960
Short name T475
Test name
Test status
Simulation time 29809953 ps
CPU time 1.27 seconds
Started Jul 01 05:38:36 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 220332 kb
Host smart-0f3dc50b-f951-45be-afc2-959fd5d63ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134770960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3134770960
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2758399987
Short name T153
Test name
Test status
Simulation time 43375910 ps
CPU time 1.43 seconds
Started Jul 01 05:38:41 PM PDT 24
Finished Jul 01 05:38:46 PM PDT 24
Peak memory 226324 kb
Host smart-f10569d3-1959-4f20-8025-cbe28ddace9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758399987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2758399987
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2233335123
Short name T751
Test name
Test status
Simulation time 244820814 ps
CPU time 2.9 seconds
Started Jul 01 05:38:37 PM PDT 24
Finished Jul 01 05:38:43 PM PDT 24
Peak memory 220508 kb
Host smart-5a751de5-38a6-4dc9-8bce-6075405ab6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233335123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2233335123
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.701320745
Short name T392
Test name
Test status
Simulation time 28300214 ps
CPU time 1.32 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:48 PM PDT 24
Peak memory 220136 kb
Host smart-9a36ae83-b939-4404-b7f7-4396a5b8e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701320745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.701320745
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1264521173
Short name T767
Test name
Test status
Simulation time 52059379 ps
CPU time 1.08 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:46 PM PDT 24
Peak memory 220996 kb
Host smart-9e563abb-ad13-465d-aca0-e7e4d2306423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264521173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1264521173
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3341609976
Short name T504
Test name
Test status
Simulation time 48576874 ps
CPU time 1.48 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 217568 kb
Host smart-f1c6e68f-6678-4275-86a4-0bbcef7ae0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341609976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3341609976
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.144353918
Short name T332
Test name
Test status
Simulation time 88097281 ps
CPU time 1.15 seconds
Started Jul 01 05:36:04 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 219048 kb
Host smart-a3a6b905-c3f3-4832-bb43-fcb8fe7a3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144353918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.144353918
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.922452509
Short name T713
Test name
Test status
Simulation time 20943349 ps
CPU time 0.89 seconds
Started Jul 01 05:36:03 PM PDT 24
Finished Jul 01 05:36:04 PM PDT 24
Peak memory 207084 kb
Host smart-0127caff-2cc8-40ec-87cd-4aae7b08a996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922452509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.922452509
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4170576867
Short name T175
Test name
Test status
Simulation time 10635729 ps
CPU time 0.86 seconds
Started Jul 01 05:36:04 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 216716 kb
Host smart-683e3450-50bf-4188-9581-ca8a7b9627cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170576867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4170576867
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.32218785
Short name T804
Test name
Test status
Simulation time 37588772 ps
CPU time 1.3 seconds
Started Jul 01 05:36:04 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 217392 kb
Host smart-2115a3d2-f938-4a62-ab7b-fa68a236bf76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disa
ble_auto_req_mode.32218785
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.385060949
Short name T199
Test name
Test status
Simulation time 57997699 ps
CPU time 0.97 seconds
Started Jul 01 05:36:05 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 219056 kb
Host smart-78143418-2ef3-4295-a6d3-c42d9383587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385060949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.385060949
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.600715152
Short name T417
Test name
Test status
Simulation time 58312123 ps
CPU time 1.45 seconds
Started Jul 01 05:35:56 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 219012 kb
Host smart-72e2e695-d937-4cd1-a91d-b35ebb423826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600715152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.600715152
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2817290876
Short name T800
Test name
Test status
Simulation time 31296757 ps
CPU time 0.91 seconds
Started Jul 01 05:36:03 PM PDT 24
Finished Jul 01 05:36:04 PM PDT 24
Peak memory 215820 kb
Host smart-979b6768-89b7-4228-8b06-f0936f9e370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817290876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2817290876
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3739795979
Short name T872
Test name
Test status
Simulation time 27839980 ps
CPU time 0.89 seconds
Started Jul 01 05:35:57 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 207356 kb
Host smart-899b5897-0826-4eec-b5be-6d22aadd5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739795979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3739795979
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1385072713
Short name T537
Test name
Test status
Simulation time 51497186 ps
CPU time 0.94 seconds
Started Jul 01 05:35:57 PM PDT 24
Finished Jul 01 05:35:59 PM PDT 24
Peak memory 215592 kb
Host smart-64297296-5e64-4d3e-8229-7942b2ab54f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385072713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1385072713
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.663857713
Short name T812
Test name
Test status
Simulation time 607616461 ps
CPU time 2.83 seconds
Started Jul 01 05:35:57 PM PDT 24
Finished Jul 01 05:36:00 PM PDT 24
Peak memory 215720 kb
Host smart-fb939df2-c8d6-4e67-893c-c9b7425b77b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663857713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.663857713
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2527068884
Short name T201
Test name
Test status
Simulation time 38936014229 ps
CPU time 980.47 seconds
Started Jul 01 05:36:05 PM PDT 24
Finished Jul 01 05:52:26 PM PDT 24
Peak memory 220124 kb
Host smart-85e3150f-06cf-405f-90c8-fafb1227cc9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527068884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2527068884
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2775354922
Short name T709
Test name
Test status
Simulation time 34190609 ps
CPU time 1.25 seconds
Started Jul 01 05:38:40 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 219764 kb
Host smart-418a296a-3e5b-4887-8d0e-dba5651a5af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775354922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2775354922
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1482878833
Short name T137
Test name
Test status
Simulation time 26130924 ps
CPU time 1.2 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:46 PM PDT 24
Peak memory 218884 kb
Host smart-145867a2-173c-48fe-a4c2-22ad8b24bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482878833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1482878833
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1192032725
Short name T557
Test name
Test status
Simulation time 59416590 ps
CPU time 1.26 seconds
Started Jul 01 05:38:40 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 215684 kb
Host smart-313bad6a-e16e-4116-8f29-125e1cf28e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192032725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1192032725
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2351305440
Short name T189
Test name
Test status
Simulation time 70549782 ps
CPU time 1.2 seconds
Started Jul 01 05:38:41 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 216096 kb
Host smart-b57dbc2d-88a6-4a4a-a96a-090273ce036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351305440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2351305440
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1006048643
Short name T847
Test name
Test status
Simulation time 26557854 ps
CPU time 0.9 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219792 kb
Host smart-e0c2bfa8-8f8b-4f91-b041-921fb6264516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006048643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1006048643
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1584819448
Short name T745
Test name
Test status
Simulation time 23774100 ps
CPU time 1.17 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219092 kb
Host smart-0723731c-92de-4a1b-975a-19e3aa2b1e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584819448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1584819448
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.248730653
Short name T79
Test name
Test status
Simulation time 43328324 ps
CPU time 1.18 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:48 PM PDT 24
Peak memory 220060 kb
Host smart-955da467-2b58-4761-997b-b1139045c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248730653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.248730653
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2417691477
Short name T75
Test name
Test status
Simulation time 25113321 ps
CPU time 0.96 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:48 PM PDT 24
Peak memory 218624 kb
Host smart-fe43793e-4b75-4886-9319-7a49c00c916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417691477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2417691477
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2130533745
Short name T427
Test name
Test status
Simulation time 49130696 ps
CPU time 1.54 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:48 PM PDT 24
Peak memory 220276 kb
Host smart-5d9749be-f02d-42f3-b935-ec0ed6ea13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130533745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2130533745
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.259265175
Short name T78
Test name
Test status
Simulation time 26395773 ps
CPU time 1.25 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 218712 kb
Host smart-7b9f5841-af8c-4ff9-ba86-6f62361bf30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259265175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.259265175
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2089058268
Short name T677
Test name
Test status
Simulation time 48392911 ps
CPU time 0.98 seconds
Started Jul 01 05:38:40 PM PDT 24
Finished Jul 01 05:38:44 PM PDT 24
Peak memory 220004 kb
Host smart-b0aafe7b-d07f-4aec-86ba-6d24761eca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089058268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2089058268
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3060173818
Short name T431
Test name
Test status
Simulation time 30327220 ps
CPU time 1.46 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 218780 kb
Host smart-b67bc143-ae10-4fc8-b426-f90b23d12d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060173818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3060173818
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3684837165
Short name T803
Test name
Test status
Simulation time 51776550 ps
CPU time 1.18 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:46 PM PDT 24
Peak memory 219912 kb
Host smart-8b31fc22-3135-417f-baf1-753ec9a1661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684837165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3684837165
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4046600004
Short name T777
Test name
Test status
Simulation time 33234088 ps
CPU time 1.13 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219124 kb
Host smart-50696164-d851-48d2-9ac4-c523ab80441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046600004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4046600004
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2048244335
Short name T393
Test name
Test status
Simulation time 55297539 ps
CPU time 1.03 seconds
Started Jul 01 05:38:43 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219028 kb
Host smart-65c1616e-c74d-42e1-b159-4119c0da8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048244335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2048244335
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2634573101
Short name T441
Test name
Test status
Simulation time 31699803 ps
CPU time 1.3 seconds
Started Jul 01 05:38:39 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 219828 kb
Host smart-fd7c53c0-eca1-4124-938c-26fc499fd3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634573101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2634573101
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3305032325
Short name T103
Test name
Test status
Simulation time 33275987 ps
CPU time 0.85 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219608 kb
Host smart-b388dc34-c2b1-4ebb-a17c-d59a0fd6f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305032325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3305032325
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3908466631
Short name T910
Test name
Test status
Simulation time 100528597 ps
CPU time 2.23 seconds
Started Jul 01 05:38:44 PM PDT 24
Finished Jul 01 05:38:49 PM PDT 24
Peak memory 220488 kb
Host smart-8f31681f-524e-40b6-85c0-8defcd8b034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908466631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3908466631
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.498803557
Short name T963
Test name
Test status
Simulation time 21778949 ps
CPU time 0.93 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 218720 kb
Host smart-ccd649ca-e96c-4b9a-8e22-e0ff8e8ea710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498803557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.498803557
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1497926859
Short name T592
Test name
Test status
Simulation time 249919203 ps
CPU time 1.42 seconds
Started Jul 01 05:38:42 PM PDT 24
Finished Jul 01 05:38:47 PM PDT 24
Peak memory 219356 kb
Host smart-d8c3d6dd-e455-476a-b96b-c2d46de90a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497926859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1497926859
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3854705262
Short name T649
Test name
Test status
Simulation time 46247884 ps
CPU time 1.1 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:51 PM PDT 24
Peak memory 219084 kb
Host smart-669d1f0e-f7df-4841-b714-786491418ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854705262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3854705262
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_genbits.982723737
Short name T469
Test name
Test status
Simulation time 30150873 ps
CPU time 1.18 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:52 PM PDT 24
Peak memory 218784 kb
Host smart-17b19722-78e8-42b4-9b57-dd4173e143f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982723737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.982723737
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2123602973
Short name T669
Test name
Test status
Simulation time 46627783 ps
CPU time 1.18 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 218896 kb
Host smart-8238146a-bcd6-4efb-8ac7-3b060623974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123602973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2123602973
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3572105684
Short name T651
Test name
Test status
Simulation time 32821861 ps
CPU time 1.12 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:52 PM PDT 24
Peak memory 220232 kb
Host smart-c742813a-b396-4574-90d2-3ff9e86ace94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572105684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3572105684
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3263781593
Short name T458
Test name
Test status
Simulation time 30335193 ps
CPU time 1.28 seconds
Started Jul 01 05:38:51 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 220236 kb
Host smart-d1321a3b-c710-4a0b-ac10-9a7c73078ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263781593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3263781593
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.600007755
Short name T716
Test name
Test status
Simulation time 51388639 ps
CPU time 1.24 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 220196 kb
Host smart-fcaed271-8ff2-4853-8735-321341b36b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600007755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.600007755
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1964206131
Short name T140
Test name
Test status
Simulation time 29277730 ps
CPU time 1.09 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 230168 kb
Host smart-6a15f487-1f81-497d-bb19-1ff6fac72fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964206131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1964206131
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3780767142
Short name T633
Test name
Test status
Simulation time 75297586 ps
CPU time 1.2 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 215780 kb
Host smart-4cd0dc60-95ac-4681-8cd1-ba5f7481e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780767142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3780767142
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.162010227
Short name T933
Test name
Test status
Simulation time 62559134 ps
CPU time 1.12 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:13 PM PDT 24
Peak memory 220064 kb
Host smart-3de68c60-49e2-44e4-9cab-71694fa71cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162010227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.162010227
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.447741713
Short name T707
Test name
Test status
Simulation time 26434378 ps
CPU time 0.86 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:12 PM PDT 24
Peak memory 207168 kb
Host smart-db105f73-1294-420d-a3fc-8773a8a3f814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447741713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.447741713
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2838616804
Short name T54
Test name
Test status
Simulation time 17170761 ps
CPU time 0.8 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:12 PM PDT 24
Peak memory 215760 kb
Host smart-39f8758e-1793-4ca1-92e8-b2d6d6d0ebe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838616804 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2838616804
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1265920597
Short name T116
Test name
Test status
Simulation time 41688077 ps
CPU time 1.38 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:13 PM PDT 24
Peak memory 217300 kb
Host smart-735f8ed7-9f08-4c31-9633-097e02f0f963
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265920597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1265920597
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.144607453
Short name T212
Test name
Test status
Simulation time 19275858 ps
CPU time 1.24 seconds
Started Jul 01 05:36:09 PM PDT 24
Finished Jul 01 05:36:11 PM PDT 24
Peak memory 224324 kb
Host smart-382e609b-e18a-4ea1-987e-41c7629b009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144607453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.144607453
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2269296116
Short name T607
Test name
Test status
Simulation time 136838655 ps
CPU time 2.79 seconds
Started Jul 01 05:36:10 PM PDT 24
Finished Jul 01 05:36:14 PM PDT 24
Peak memory 220008 kb
Host smart-6acb57af-a6b5-406b-a454-3d2f4398bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269296116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2269296116
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2949569238
Short name T525
Test name
Test status
Simulation time 39740329 ps
CPU time 1.02 seconds
Started Jul 01 05:36:09 PM PDT 24
Finished Jul 01 05:36:11 PM PDT 24
Peak memory 224360 kb
Host smart-3d07c7f9-4f27-484a-af81-107aa7fea301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949569238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2949569238
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2836977370
Short name T29
Test name
Test status
Simulation time 16966043 ps
CPU time 0.97 seconds
Started Jul 01 05:36:04 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 207460 kb
Host smart-b478cfc4-849f-4576-a119-27a79f8119b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836977370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2836977370
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.613618835
Short name T563
Test name
Test status
Simulation time 27216957 ps
CPU time 1.01 seconds
Started Jul 01 05:36:03 PM PDT 24
Finished Jul 01 05:36:05 PM PDT 24
Peak memory 215700 kb
Host smart-27483b43-941f-4dcc-adf4-b01cd7e59794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613618835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.613618835
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1658243459
Short name T792
Test name
Test status
Simulation time 506957832 ps
CPU time 7.1 seconds
Started Jul 01 05:36:11 PM PDT 24
Finished Jul 01 05:36:20 PM PDT 24
Peak memory 215668 kb
Host smart-e4526830-b90f-4804-b9a4-b7d88c6afb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658243459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1658243459
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2482383104
Short name T692
Test name
Test status
Simulation time 149261616430 ps
CPU time 1928.39 seconds
Started Jul 01 05:36:11 PM PDT 24
Finished Jul 01 06:08:21 PM PDT 24
Peak memory 228972 kb
Host smart-865f4f52-d1b8-454d-ad1c-42f60bb06586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482383104 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2482383104
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1470074900
Short name T623
Test name
Test status
Simulation time 93623478 ps
CPU time 1.18 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:52 PM PDT 24
Peak memory 219828 kb
Host smart-72ef5694-ddc2-46a3-bf1b-19928f522f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470074900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1470074900
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2773772813
Short name T181
Test name
Test status
Simulation time 21277688 ps
CPU time 1.07 seconds
Started Jul 01 05:38:47 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 218876 kb
Host smart-ca98049c-951b-4808-99c6-cba56e5e3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773772813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2773772813
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2608934427
Short name T485
Test name
Test status
Simulation time 66650357 ps
CPU time 1.21 seconds
Started Jul 01 05:38:51 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 215704 kb
Host smart-3eac7959-afb1-4115-b76a-c84e4f71f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608934427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2608934427
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1041675738
Short name T334
Test name
Test status
Simulation time 130322459 ps
CPU time 1.19 seconds
Started Jul 01 05:38:47 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 220796 kb
Host smart-b0b6a9c8-a72d-4920-a765-392c3f805952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041675738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1041675738
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_genbits.3090520548
Short name T397
Test name
Test status
Simulation time 60268569 ps
CPU time 1.08 seconds
Started Jul 01 05:38:47 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 217792 kb
Host smart-0e9dc3e2-10cd-44b0-bf13-adff58fdbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090520548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3090520548
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.586997369
Short name T156
Test name
Test status
Simulation time 94640828 ps
CPU time 1.16 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 220560 kb
Host smart-00ac8516-4210-4245-af68-9b8542f9f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586997369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.586997369
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1225820284
Short name T128
Test name
Test status
Simulation time 48799325 ps
CPU time 1.13 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 229812 kb
Host smart-23b5f336-733b-4a98-af51-a89e0dc1e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225820284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1225820284
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1475794601
Short name T400
Test name
Test status
Simulation time 40299056 ps
CPU time 1.4 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:51 PM PDT 24
Peak memory 217624 kb
Host smart-367122aa-49e7-46ff-ab86-089aa9a01d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475794601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1475794601
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1604570620
Short name T718
Test name
Test status
Simulation time 35997931 ps
CPU time 1.01 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:52 PM PDT 24
Peak memory 219228 kb
Host smart-464ddb25-c033-40dc-ab31-7084aa407aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604570620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1604570620
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1340652137
Short name T353
Test name
Test status
Simulation time 45552556 ps
CPU time 1.12 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:51 PM PDT 24
Peak memory 221080 kb
Host smart-36c6654f-16ff-473b-9515-86598dad3257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340652137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1340652137
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3632579048
Short name T289
Test name
Test status
Simulation time 37775069 ps
CPU time 1.4 seconds
Started Jul 01 05:38:48 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 220544 kb
Host smart-d67bd809-a935-4d98-9354-6b7748fb5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632579048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3632579048
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1976333188
Short name T740
Test name
Test status
Simulation time 74924882 ps
CPU time 1.04 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 221060 kb
Host smart-94660993-306e-4532-a2b3-ed52811468b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976333188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1976333188
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1377743163
Short name T216
Test name
Test status
Simulation time 43508776 ps
CPU time 1.12 seconds
Started Jul 01 05:38:58 PM PDT 24
Finished Jul 01 05:39:00 PM PDT 24
Peak memory 219980 kb
Host smart-37ce886f-7257-4119-b24f-952e39cfc66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377743163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1377743163
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3698135672
Short name T813
Test name
Test status
Simulation time 46595343 ps
CPU time 1.78 seconds
Started Jul 01 05:38:49 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 219064 kb
Host smart-245eaa2f-9ab5-4807-b812-67ef5e18c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698135672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3698135672
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.328417092
Short name T852
Test name
Test status
Simulation time 112809888 ps
CPU time 1.18 seconds
Started Jul 01 05:38:50 PM PDT 24
Finished Jul 01 05:38:53 PM PDT 24
Peak memory 219012 kb
Host smart-9295d589-6658-48f7-9f19-409e995202d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328417092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.328417092
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1990292824
Short name T511
Test name
Test status
Simulation time 27837842 ps
CPU time 1.04 seconds
Started Jul 01 05:38:54 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 218824 kb
Host smart-eb5740c9-221f-4213-8371-decc92d0a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990292824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1990292824
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.833106116
Short name T788
Test name
Test status
Simulation time 51492049 ps
CPU time 1.28 seconds
Started Jul 01 05:38:51 PM PDT 24
Finished Jul 01 05:38:54 PM PDT 24
Peak memory 217796 kb
Host smart-cd7663b9-07e0-4240-ab10-4154da998a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833106116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.833106116
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.472719078
Short name T335
Test name
Test status
Simulation time 202209417 ps
CPU time 1.21 seconds
Started Jul 01 05:38:54 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 220056 kb
Host smart-94c2ea54-3d14-4598-82c6-786afeae9ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472719078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.472719078
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3468130353
Short name T185
Test name
Test status
Simulation time 35289780 ps
CPU time 0.92 seconds
Started Jul 01 05:38:54 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 218664 kb
Host smart-76757294-1b45-44fe-b4d5-a1cdf239524e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468130353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3468130353
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1925006340
Short name T367
Test name
Test status
Simulation time 73367675 ps
CPU time 1.07 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:58 PM PDT 24
Peak memory 217612 kb
Host smart-85a1ddd1-bc7a-49eb-818f-267845298b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925006340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1925006340
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2904885541
Short name T118
Test name
Test status
Simulation time 23907893 ps
CPU time 1.22 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:58 PM PDT 24
Peak memory 220164 kb
Host smart-28371053-d6e5-40ff-ae2b-96ad23316beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904885541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2904885541
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4023811932
Short name T570
Test name
Test status
Simulation time 29298121 ps
CPU time 1.12 seconds
Started Jul 01 05:38:55 PM PDT 24
Finished Jul 01 05:38:58 PM PDT 24
Peak memory 224324 kb
Host smart-5cc96eba-3ae3-40f4-a7e8-756663dc18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023811932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4023811932
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3453472548
Short name T310
Test name
Test status
Simulation time 62693841 ps
CPU time 1.15 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 220340 kb
Host smart-873517f0-4fb4-4170-b18d-d1d5ae7d0345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453472548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3453472548
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2654800069
Short name T981
Test name
Test status
Simulation time 29990013 ps
CPU time 1.22 seconds
Started Jul 01 05:38:53 PM PDT 24
Finished Jul 01 05:38:56 PM PDT 24
Peak memory 220200 kb
Host smart-9a7fb759-9003-4b6d-93d4-fb9022688df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654800069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2654800069
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3897944510
Short name T191
Test name
Test status
Simulation time 19736381 ps
CPU time 1.05 seconds
Started Jul 01 05:38:52 PM PDT 24
Finished Jul 01 05:38:54 PM PDT 24
Peak memory 218964 kb
Host smart-e8cb0629-33c1-4753-ab83-d47f71eef9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897944510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3897944510
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.912688474
Short name T787
Test name
Test status
Simulation time 54049719 ps
CPU time 1.04 seconds
Started Jul 01 05:38:52 PM PDT 24
Finished Jul 01 05:38:55 PM PDT 24
Peak memory 217576 kb
Host smart-bc09265c-32d0-4ce6-90de-3171d1d7fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912688474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.912688474
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3448749675
Short name T405
Test name
Test status
Simulation time 31959554 ps
CPU time 1.48 seconds
Started Jul 01 05:38:59 PM PDT 24
Finished Jul 01 05:39:01 PM PDT 24
Peak memory 220304 kb
Host smart-e4c889c9-0da3-4914-a542-719213e05414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448749675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3448749675
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_genbits.1769370050
Short name T105
Test name
Test status
Simulation time 64334129 ps
CPU time 1.64 seconds
Started Jul 01 05:38:54 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 219064 kb
Host smart-aff3d925-9918-4f06-b62a-77d5cfebf59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769370050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1769370050
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%