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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.67 98.25 93.73 97.02 92.44 96.37 99.77 92.08


Total test records in report: 1129
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T1016 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3310688774 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:44 AM PDT 24 237843281 ps
T1017 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1294065653 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 28650095 ps
T1018 /workspace/coverage/cover_reg_top/16.edn_intr_test.1171727805 Jul 02 09:46:41 AM PDT 24 Jul 02 09:46:44 AM PDT 24 18822393 ps
T1019 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4017414644 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 25326219 ps
T1020 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3811816627 Jul 02 09:46:31 AM PDT 24 Jul 02 09:46:33 AM PDT 24 70217341 ps
T1021 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1193947825 Jul 02 09:46:45 AM PDT 24 Jul 02 09:46:48 AM PDT 24 19849390 ps
T262 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3441469391 Jul 02 09:46:49 AM PDT 24 Jul 02 09:46:50 AM PDT 24 15123698 ps
T1022 /workspace/coverage/cover_reg_top/43.edn_intr_test.60732973 Jul 02 09:46:38 AM PDT 24 Jul 02 09:46:40 AM PDT 24 29809325 ps
T1023 /workspace/coverage/cover_reg_top/9.edn_csr_rw.263596765 Jul 02 09:46:32 AM PDT 24 Jul 02 09:46:34 AM PDT 24 14671508 ps
T1024 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1588583019 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 343889397 ps
T1025 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.754003054 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:42 AM PDT 24 54446392 ps
T263 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1970767038 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 31102024 ps
T1026 /workspace/coverage/cover_reg_top/41.edn_intr_test.1465732292 Jul 02 09:46:45 AM PDT 24 Jul 02 09:46:48 AM PDT 24 23772613 ps
T1027 /workspace/coverage/cover_reg_top/11.edn_intr_test.2120247515 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 13818385 ps
T1028 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4292134910 Jul 02 09:46:32 AM PDT 24 Jul 02 09:46:38 AM PDT 24 309236197 ps
T299 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3648407566 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:31 AM PDT 24 96691867 ps
T1029 /workspace/coverage/cover_reg_top/46.edn_intr_test.2479923997 Jul 02 09:46:44 AM PDT 24 Jul 02 09:46:47 AM PDT 24 14127274 ps
T1030 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3485589139 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:32 AM PDT 24 58211471 ps
T1031 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3701824093 Jul 02 09:46:54 AM PDT 24 Jul 02 09:46:57 AM PDT 24 67086867 ps
T1032 /workspace/coverage/cover_reg_top/44.edn_intr_test.765843213 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:43 AM PDT 24 76283142 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.372237185 Jul 02 09:46:31 AM PDT 24 Jul 02 09:46:34 AM PDT 24 44834691 ps
T1034 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2757608992 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:32 AM PDT 24 283535516 ps
T1035 /workspace/coverage/cover_reg_top/19.edn_intr_test.2919469921 Jul 02 09:46:52 AM PDT 24 Jul 02 09:46:55 AM PDT 24 13631459 ps
T294 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.342158458 Jul 02 09:46:36 AM PDT 24 Jul 02 09:46:39 AM PDT 24 226078635 ps
T1036 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2354968148 Jul 02 09:46:37 AM PDT 24 Jul 02 09:46:39 AM PDT 24 102446283 ps
T1037 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2047168773 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 33197486 ps
T1038 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1102914005 Jul 02 09:46:25 AM PDT 24 Jul 02 09:46:28 AM PDT 24 22769055 ps
T264 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2885186103 Jul 02 09:46:45 AM PDT 24 Jul 02 09:46:48 AM PDT 24 17660174 ps
T1039 /workspace/coverage/cover_reg_top/13.edn_intr_test.3248330068 Jul 02 09:46:46 AM PDT 24 Jul 02 09:46:49 AM PDT 24 14963845 ps
T1040 /workspace/coverage/cover_reg_top/14.edn_csr_rw.4019586980 Jul 02 09:46:57 AM PDT 24 Jul 02 09:46:58 AM PDT 24 14910988 ps
T1041 /workspace/coverage/cover_reg_top/33.edn_intr_test.3417888485 Jul 02 09:46:38 AM PDT 24 Jul 02 09:46:40 AM PDT 24 36051397 ps
T1042 /workspace/coverage/cover_reg_top/7.edn_intr_test.1310938734 Jul 02 09:46:30 AM PDT 24 Jul 02 09:46:32 AM PDT 24 31975269 ps
T1043 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2267996621 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:28 AM PDT 24 48199130 ps
T1044 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1501414278 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:28 AM PDT 24 34818517 ps
T295 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3617282854 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:26 AM PDT 24 74618718 ps
T1045 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1352069917 Jul 02 09:46:41 AM PDT 24 Jul 02 09:46:44 AM PDT 24 58432361 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3484882416 Jul 02 09:46:42 AM PDT 24 Jul 02 09:46:45 AM PDT 24 35752491 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1355755889 Jul 02 09:46:29 AM PDT 24 Jul 02 09:46:32 AM PDT 24 86211704 ps
T1048 /workspace/coverage/cover_reg_top/18.edn_intr_test.1495083211 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:42 AM PDT 24 15358892 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_intr_test.3807546221 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 25121015 ps
T265 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3080464632 Jul 02 09:46:22 AM PDT 24 Jul 02 09:46:24 AM PDT 24 27827687 ps
T1050 /workspace/coverage/cover_reg_top/9.edn_intr_test.4230632320 Jul 02 09:46:31 AM PDT 24 Jul 02 09:46:33 AM PDT 24 23094968 ps
T1051 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1591064592 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:48 AM PDT 24 295714453 ps
T266 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2190709838 Jul 02 09:46:22 AM PDT 24 Jul 02 09:46:24 AM PDT 24 16305038 ps
T1052 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1116711664 Jul 02 09:46:33 AM PDT 24 Jul 02 09:46:35 AM PDT 24 99632962 ps
T1053 /workspace/coverage/cover_reg_top/1.edn_intr_test.3325050165 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 19533554 ps
T1054 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3774750516 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 86333998 ps
T1055 /workspace/coverage/cover_reg_top/14.edn_tl_errors.129486186 Jul 02 09:46:38 AM PDT 24 Jul 02 09:46:44 AM PDT 24 428048671 ps
T1056 /workspace/coverage/cover_reg_top/6.edn_intr_test.346637808 Jul 02 09:46:26 AM PDT 24 Jul 02 09:46:29 AM PDT 24 21635734 ps
T1057 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3598944723 Jul 02 09:46:37 AM PDT 24 Jul 02 09:46:39 AM PDT 24 139423852 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4172886318 Jul 02 09:46:26 AM PDT 24 Jul 02 09:46:29 AM PDT 24 36412249 ps
T1059 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3664059391 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:37 AM PDT 24 223786724 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2096876832 Jul 02 09:46:29 AM PDT 24 Jul 02 09:46:34 AM PDT 24 439044742 ps
T1061 /workspace/coverage/cover_reg_top/28.edn_intr_test.3921105672 Jul 02 09:46:58 AM PDT 24 Jul 02 09:47:01 AM PDT 24 41599372 ps
T1062 /workspace/coverage/cover_reg_top/38.edn_intr_test.3655726164 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:41 AM PDT 24 43260835 ps
T297 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3971899218 Jul 02 09:46:37 AM PDT 24 Jul 02 09:46:40 AM PDT 24 373905500 ps
T1063 /workspace/coverage/cover_reg_top/8.edn_csr_rw.309463533 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:36 AM PDT 24 54337574 ps
T267 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4249376423 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:28 AM PDT 24 41729179 ps
T1064 /workspace/coverage/cover_reg_top/21.edn_intr_test.3845031553 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:36 AM PDT 24 12703362 ps
T1065 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1761909429 Jul 02 09:46:29 AM PDT 24 Jul 02 09:46:32 AM PDT 24 78222092 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_intr_test.1649799663 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:26 AM PDT 24 28956241 ps
T1067 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2976584353 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:42 AM PDT 24 50455005 ps
T1068 /workspace/coverage/cover_reg_top/48.edn_intr_test.1371932780 Jul 02 09:46:47 AM PDT 24 Jul 02 09:46:49 AM PDT 24 20527332 ps
T1069 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2631093830 Jul 02 09:46:26 AM PDT 24 Jul 02 09:46:28 AM PDT 24 14357367 ps
T1070 /workspace/coverage/cover_reg_top/36.edn_intr_test.2574413050 Jul 02 09:46:45 AM PDT 24 Jul 02 09:46:48 AM PDT 24 43992731 ps
T269 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2764204090 Jul 02 09:46:25 AM PDT 24 Jul 02 09:46:31 AM PDT 24 515717733 ps
T1071 /workspace/coverage/cover_reg_top/26.edn_intr_test.3185703407 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:36 AM PDT 24 103120932 ps
T1072 /workspace/coverage/cover_reg_top/8.edn_intr_test.2400607521 Jul 02 09:46:30 AM PDT 24 Jul 02 09:46:32 AM PDT 24 33521703 ps
T1073 /workspace/coverage/cover_reg_top/31.edn_intr_test.4043460910 Jul 02 09:46:44 AM PDT 24 Jul 02 09:46:47 AM PDT 24 37739688 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.445553648 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 75046441 ps
T1075 /workspace/coverage/cover_reg_top/24.edn_intr_test.393523161 Jul 02 09:46:37 AM PDT 24 Jul 02 09:46:39 AM PDT 24 12857949 ps
T1076 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3844577066 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:38 AM PDT 24 98697954 ps
T271 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.429386936 Jul 02 09:46:31 AM PDT 24 Jul 02 09:46:33 AM PDT 24 25581971 ps
T1077 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4208415939 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:26 AM PDT 24 83702906 ps
T1078 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1802693269 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:43 AM PDT 24 13317880 ps
T1079 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.663030000 Jul 02 09:46:25 AM PDT 24 Jul 02 09:46:28 AM PDT 24 67790378 ps
T1080 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1547196767 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:48 AM PDT 24 506243091 ps
T1081 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.956924257 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:32 AM PDT 24 222807985 ps
T1082 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4218322325 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:41 AM PDT 24 17019309 ps
T1083 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2196529430 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:30 AM PDT 24 46227431 ps
T1084 /workspace/coverage/cover_reg_top/29.edn_intr_test.250086856 Jul 02 09:46:38 AM PDT 24 Jul 02 09:46:40 AM PDT 24 59114415 ps
T1085 /workspace/coverage/cover_reg_top/37.edn_intr_test.1726797631 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:46 AM PDT 24 22265264 ps
T1086 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2916503481 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:32 AM PDT 24 88863692 ps
T1087 /workspace/coverage/cover_reg_top/30.edn_intr_test.2998063832 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:47 AM PDT 24 28494547 ps
T272 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.384534209 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:30 AM PDT 24 31410833 ps
T1088 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2762960302 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:48 AM PDT 24 122137660 ps
T1089 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.563706498 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:31 AM PDT 24 67436610 ps
T1090 /workspace/coverage/cover_reg_top/22.edn_intr_test.4035257477 Jul 02 09:46:54 AM PDT 24 Jul 02 09:46:56 AM PDT 24 14798253 ps
T1091 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.551445058 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 136292322 ps
T1092 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2256944045 Jul 02 09:46:41 AM PDT 24 Jul 02 09:46:44 AM PDT 24 97316706 ps
T300 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.592120044 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:23 AM PDT 24 87827631 ps
T1093 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1581584669 Jul 02 09:46:34 AM PDT 24 Jul 02 09:46:36 AM PDT 24 120522870 ps
T1094 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3600155668 Jul 02 09:46:22 AM PDT 24 Jul 02 09:46:30 AM PDT 24 36211402 ps
T270 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3631818529 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:28 AM PDT 24 254308147 ps
T1095 /workspace/coverage/cover_reg_top/3.edn_intr_test.646036158 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:26 AM PDT 24 18222633 ps
T1096 /workspace/coverage/cover_reg_top/40.edn_intr_test.1025104908 Jul 02 09:46:57 AM PDT 24 Jul 02 09:46:59 AM PDT 24 43467703 ps
T1097 /workspace/coverage/cover_reg_top/23.edn_intr_test.1580712408 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:46 AM PDT 24 17744264 ps
T1098 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3879181993 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:42 AM PDT 24 92467253 ps
T1099 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1594976914 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:36 AM PDT 24 18232995 ps
T1100 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3458038202 Jul 02 09:46:37 AM PDT 24 Jul 02 09:46:39 AM PDT 24 41931473 ps
T1101 /workspace/coverage/cover_reg_top/12.edn_intr_test.1848962306 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:31 AM PDT 24 42792684 ps
T1102 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4213667549 Jul 02 09:46:27 AM PDT 24 Jul 02 09:46:32 AM PDT 24 62610091 ps
T1103 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2866780632 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:32 AM PDT 24 189232402 ps
T1104 /workspace/coverage/cover_reg_top/15.edn_intr_test.3246522643 Jul 02 09:46:36 AM PDT 24 Jul 02 09:46:43 AM PDT 24 48735877 ps
T1105 /workspace/coverage/cover_reg_top/49.edn_intr_test.3678184596 Jul 02 09:46:45 AM PDT 24 Jul 02 09:46:48 AM PDT 24 14913748 ps
T1106 /workspace/coverage/cover_reg_top/27.edn_intr_test.3349993668 Jul 02 09:46:52 AM PDT 24 Jul 02 09:46:54 AM PDT 24 15153474 ps
T1107 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.756041984 Jul 02 09:46:26 AM PDT 24 Jul 02 09:46:29 AM PDT 24 28290210 ps
T1108 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2810674609 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:28 AM PDT 24 116527004 ps
T1109 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3320596806 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:45 AM PDT 24 231809917 ps
T1110 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2771356873 Jul 02 09:46:33 AM PDT 24 Jul 02 09:46:35 AM PDT 24 26004854 ps
T1111 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1397851117 Jul 02 09:46:28 AM PDT 24 Jul 02 09:46:35 AM PDT 24 353303248 ps
T1112 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.366423132 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 188713973 ps
T1113 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1253497446 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:43 AM PDT 24 116839504 ps
T1114 /workspace/coverage/cover_reg_top/10.edn_intr_test.2688417218 Jul 02 09:46:35 AM PDT 24 Jul 02 09:46:36 AM PDT 24 21528685 ps
T1115 /workspace/coverage/cover_reg_top/47.edn_intr_test.1741271977 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:47 AM PDT 24 20169918 ps
T1116 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2878530818 Jul 02 09:46:26 AM PDT 24 Jul 02 09:46:29 AM PDT 24 54330486 ps
T1117 /workspace/coverage/cover_reg_top/0.edn_intr_test.3593449662 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:26 AM PDT 24 21520448 ps
T1118 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1559267264 Jul 02 09:46:30 AM PDT 24 Jul 02 09:46:34 AM PDT 24 305349797 ps
T1119 /workspace/coverage/cover_reg_top/32.edn_intr_test.1455747773 Jul 02 09:46:55 AM PDT 24 Jul 02 09:46:57 AM PDT 24 39156353 ps
T1120 /workspace/coverage/cover_reg_top/34.edn_intr_test.1350781143 Jul 02 09:46:41 AM PDT 24 Jul 02 09:46:44 AM PDT 24 43753955 ps
T1121 /workspace/coverage/cover_reg_top/19.edn_tl_errors.329021108 Jul 02 09:46:40 AM PDT 24 Jul 02 09:46:43 AM PDT 24 210124325 ps
T1122 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2109485369 Jul 02 09:46:44 AM PDT 24 Jul 02 09:46:48 AM PDT 24 418437559 ps
T1123 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.939971534 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:26 AM PDT 24 32804273 ps
T1124 /workspace/coverage/cover_reg_top/20.edn_intr_test.1105262979 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:46 AM PDT 24 21631165 ps
T1125 /workspace/coverage/cover_reg_top/14.edn_intr_test.2902930465 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:42 AM PDT 24 12946503 ps
T1126 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1131373254 Jul 02 09:46:39 AM PDT 24 Jul 02 09:46:42 AM PDT 24 34143542 ps
T1127 /workspace/coverage/cover_reg_top/45.edn_intr_test.3697271509 Jul 02 09:46:52 AM PDT 24 Jul 02 09:46:55 AM PDT 24 17016630 ps
T1128 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1860364752 Jul 02 09:46:52 AM PDT 24 Jul 02 09:46:54 AM PDT 24 31005528 ps
T1129 /workspace/coverage/cover_reg_top/17.edn_intr_test.896103806 Jul 02 09:46:43 AM PDT 24 Jul 02 09:46:46 AM PDT 24 13326154 ps

Test location /workspace/coverage/default/74.edn_genbits.895020234
Short name T9
Test name
Test status
Simulation time 28800252 ps
CPU time 1.21 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 218812 kb
Host smart-161aa683-39b5-4329-981d-839d694993cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895020234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.895020234
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1615108741
Short name T5
Test name
Test status
Simulation time 301950217108 ps
CPU time 1339.57 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 10:17:59 AM PDT 24
Peak memory 224196 kb
Host smart-5e0b57fc-8551-4ce2-bcf6-e2ed88708ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615108741 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1615108741
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.edn_alert.3383466463
Short name T28
Test name
Test status
Simulation time 94678084 ps
CPU time 1.16 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:39 AM PDT 24
Peak memory 219984 kb
Host smart-64db0f99-4f58-46f9-8f46-ee266de3d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383466463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3383466463
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3736569173
Short name T17
Test name
Test status
Simulation time 540473893 ps
CPU time 8.22 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 236376 kb
Host smart-b8932625-ff9c-4ff0-a3fa-44ecdd8b48a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736569173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3736569173
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/16.edn_err.152960008
Short name T33
Test name
Test status
Simulation time 42224752 ps
CPU time 0.85 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 218812 kb
Host smart-85f2f478-5221-404b-be86-0c32b2c85fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152960008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.152960008
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/298.edn_genbits.3631967008
Short name T81
Test name
Test status
Simulation time 64875243 ps
CPU time 1.51 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219012 kb
Host smart-1bbe8453-77f8-4025-9231-c81f386e86ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631967008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3631967008
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.980204353
Short name T20
Test name
Test status
Simulation time 64329815 ps
CPU time 1.15 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 215928 kb
Host smart-eaa575ca-d911-498a-8942-4183a365beea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980204353 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.980204353
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_disable.2704198440
Short name T176
Test name
Test status
Simulation time 27950228 ps
CPU time 0.84 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 216760 kb
Host smart-e19a8a99-5e27-4dbe-b136-a2515d7edf91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704198440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2704198440
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/183.edn_alert.3994891523
Short name T78
Test name
Test status
Simulation time 88002681 ps
CPU time 1.23 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 219980 kb
Host smart-4740cfcb-ad93-497a-8737-9364d2fd4e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994891523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3994891523
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.2499943397
Short name T29
Test name
Test status
Simulation time 18376804 ps
CPU time 1.02 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 207460 kb
Host smart-7b9dc230-c82e-4b76-abcf-e1bad6c830fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499943397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2499943397
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/102.edn_alert.4246270353
Short name T119
Test name
Test status
Simulation time 31171114 ps
CPU time 1.38 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 219884 kb
Host smart-aa8381f9-45bb-4935-98e3-075de2ea46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246270353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.4246270353
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3061027602
Short name T143
Test name
Test status
Simulation time 112864308 ps
CPU time 1.22 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 217436 kb
Host smart-c06dd119-395d-457b-830c-060c3fb6d6ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061027602 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3061027602
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2153008293
Short name T228
Test name
Test status
Simulation time 36767372028 ps
CPU time 335.81 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 10:01:09 AM PDT 24
Peak memory 224064 kb
Host smart-9b830c60-46eb-46eb-913d-afa61dd395fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153008293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2153008293
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3971899218
Short name T297
Test name
Test status
Simulation time 373905500 ps
CPU time 2.53 seconds
Started Jul 02 09:46:37 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 207020 kb
Host smart-b6d324cd-a19c-4b21-a384-fd9613a5bcef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971899218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3971899218
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/90.edn_alert.3711837815
Short name T159
Test name
Test status
Simulation time 37415619 ps
CPU time 1.13 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 220636 kb
Host smart-721b34ec-9b9f-41ca-b327-6104949ae4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711837815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3711837815
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.3590818809
Short name T198
Test name
Test status
Simulation time 30467959 ps
CPU time 0.83 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 215768 kb
Host smart-6c93305f-8cbf-461b-a059-4b1f2deaeff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590818809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3590818809
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.404525259
Short name T197
Test name
Test status
Simulation time 46439807 ps
CPU time 0.87 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 216592 kb
Host smart-78368de7-0b5d-4fb8-af41-c1c26b42c85f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404525259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.404525259
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/15.edn_alert.2978251728
Short name T193
Test name
Test status
Simulation time 46361214 ps
CPU time 1.17 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 219384 kb
Host smart-a222c926-9aaf-4531-98e9-259b5ddf7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978251728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2978251728
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2294099336
Short name T117
Test name
Test status
Simulation time 38652281 ps
CPU time 1.36 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 217240 kb
Host smart-74df8080-e48c-4b7b-898c-0297e1b49183
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294099336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2294099336
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable.1775148905
Short name T170
Test name
Test status
Simulation time 11168286 ps
CPU time 0.88 seconds
Started Jul 02 09:56:29 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 216528 kb
Host smart-8586e82d-5049-4f84-a974-e6708c773c54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775148905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1775148905
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1726019481
Short name T259
Test name
Test status
Simulation time 181940712 ps
CPU time 0.97 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 206916 kb
Host smart-4c1f2b68-a1fe-4a67-ad8e-742d8a36fd29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726019481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1726019481
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/default/144.edn_alert.3770705341
Short name T153
Test name
Test status
Simulation time 39506327 ps
CPU time 1.19 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220452 kb
Host smart-44f5e6e5-25c9-41bc-ac7f-1fb7ccbd9496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770705341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3770705341
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/181.edn_alert.3357624374
Short name T105
Test name
Test status
Simulation time 50760582 ps
CPU time 1.27 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220028 kb
Host smart-7b8b0849-c271-43be-bdd9-549dbf62e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357624374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3357624374
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/203.edn_genbits.1648792466
Short name T309
Test name
Test status
Simulation time 97866212 ps
CPU time 3.33 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 220000 kb
Host smart-385a74a0-56ae-4f3a-930f-771f02c07de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648792466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1648792466
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1506336749
Short name T221
Test name
Test status
Simulation time 75940101 ps
CPU time 1.2 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220832 kb
Host smart-a90fbe19-d8fe-4a95-882b-0fd791eb1fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506336749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1506336749
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1814239327
Short name T305
Test name
Test status
Simulation time 41149395 ps
CPU time 1.1 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 218820 kb
Host smart-5fd758d7-4288-43ff-b213-6924e2b44543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814239327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1814239327
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.2356986479
Short name T44
Test name
Test status
Simulation time 145104480 ps
CPU time 1.15 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:58 AM PDT 24
Peak memory 220012 kb
Host smart-7f6d9e1f-996e-4f96-9ef6-992da77e1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356986479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2356986479
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/18.edn_err.2741404190
Short name T191
Test name
Test status
Simulation time 20511510 ps
CPU time 1.16 seconds
Started Jul 02 09:55:34 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 224220 kb
Host smart-00032faa-4a26-4175-bad8-c3f5c8d56edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741404190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2741404190
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/186.edn_alert.471585767
Short name T188
Test name
Test status
Simulation time 27177029 ps
CPU time 1.23 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 220160 kb
Host smart-6cf74063-a8ee-4d85-aae7-2b13f668407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471585767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.471585767
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert.3017618453
Short name T901
Test name
Test status
Simulation time 76543349 ps
CPU time 1.21 seconds
Started Jul 02 09:56:32 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 220000 kb
Host smart-16d2d31e-092b-45d6-b5d9-04c862362553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017618453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3017618453
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/26.edn_intr.2613507483
Short name T90
Test name
Test status
Simulation time 21481287 ps
CPU time 1.08 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:53 AM PDT 24
Peak memory 216328 kb
Host smart-024e27d0-968e-4eb3-8cf0-06fafdc020a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613507483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2613507483
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/75.edn_err.1983433617
Short name T7
Test name
Test status
Simulation time 51023493 ps
CPU time 0.99 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:53 AM PDT 24
Peak memory 220232 kb
Host smart-3d6979c0-c75c-40e1-a4bf-6eaa101a0672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983433617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1983433617
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.694444461
Short name T887
Test name
Test status
Simulation time 17155644 ps
CPU time 0.84 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 216676 kb
Host smart-70065fa5-d1ba-41bd-a121-98dc01d038fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694444461 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.694444461
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/113.edn_alert.1180922893
Short name T981
Test name
Test status
Simulation time 283826495 ps
CPU time 1.35 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 218604 kb
Host smart-ee5717c2-f752-4b7c-a1cf-ac6163749eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180922893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1180922893
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.2842849904
Short name T140
Test name
Test status
Simulation time 45269465 ps
CPU time 1.23 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220184 kb
Host smart-0cd4c9ac-d0e5-458f-927b-c5fc63a9d1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842849904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2842849904
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/20.edn_intr.3611021898
Short name T93
Test name
Test status
Simulation time 21671922 ps
CPU time 1.03 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:30 AM PDT 24
Peak memory 216132 kb
Host smart-bc87c937-c3a4-4869-ae91-aac7ee23345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611021898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3611021898
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.612727180
Short name T856
Test name
Test status
Simulation time 48993971 ps
CPU time 1.45 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 217384 kb
Host smart-6a3a4b23-889c-496f-8f2e-3d0ec731dcfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612727180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.612727180
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_alert.2651528295
Short name T130
Test name
Test status
Simulation time 25130446 ps
CPU time 1.18 seconds
Started Jul 02 09:56:26 AM PDT 24
Finished Jul 02 09:56:34 AM PDT 24
Peak memory 219808 kb
Host smart-705ab19e-2a91-45bb-b9f2-c93bbedc7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651528295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2651528295
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.518719068
Short name T226
Test name
Test status
Simulation time 19658461 ps
CPU time 0.87 seconds
Started Jul 02 09:55:32 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 215740 kb
Host smart-1f18bf55-dc58-4e08-9035-d7ac02f66f0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518719068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.518719068
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/117.edn_alert.3669225168
Short name T390
Test name
Test status
Simulation time 31960131 ps
CPU time 1.11 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:38 AM PDT 24
Peak memory 219932 kb
Host smart-030c4fe8-81e9-481c-9b8b-466fe7f7e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669225168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3669225168
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable.1830401892
Short name T214
Test name
Test status
Simulation time 44787475 ps
CPU time 0.88 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 216892 kb
Host smart-97e62ae0-aac6-4752-89ce-07cf8644fa7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830401892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1830401892
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1596316492
Short name T51
Test name
Test status
Simulation time 31102978 ps
CPU time 0.98 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 229584 kb
Host smart-1ae96e10-4e97-414f-9094-3ff209cd9077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596316492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1596316492
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4031824076
Short name T151
Test name
Test status
Simulation time 88777693 ps
CPU time 1.08 seconds
Started Jul 02 09:55:59 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 217276 kb
Host smart-e0e63a6e-ee62-4155-92fb-6899cac27673
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031824076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4031824076
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3843189002
Short name T202
Test name
Test status
Simulation time 98959339 ps
CPU time 1.08 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 09:56:15 AM PDT 24
Peak memory 217156 kb
Host smart-363339e8-5f0f-4fce-9fb1-42fc9dd00b37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843189002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3843189002
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2896820654
Short name T180
Test name
Test status
Simulation time 20564115 ps
CPU time 1.15 seconds
Started Jul 02 09:56:29 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 218728 kb
Host smart-098e88e2-3d5f-44fa-926b-11ddff75a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896820654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2896820654
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/40.edn_disable.3805660198
Short name T187
Test name
Test status
Simulation time 31841529 ps
CPU time 0.86 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 216552 kb
Host smart-e1443647-e2da-45d4-82ad-a644a64aa939
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805660198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3805660198
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/175.edn_genbits.3754255331
Short name T329
Test name
Test status
Simulation time 214274347 ps
CPU time 1.75 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 219060 kb
Host smart-7af3fd95-3e21-4899-a4f8-26120b9ddf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754255331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3754255331
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_genbits.3476714237
Short name T325
Test name
Test status
Simulation time 121160909 ps
CPU time 2.77 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 219132 kb
Host smart-654cab88-0c55-4897-a06c-845a53f13559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476714237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3476714237
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2091487823
Short name T71
Test name
Test status
Simulation time 20090218 ps
CPU time 1.01 seconds
Started Jul 02 09:55:32 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 207036 kb
Host smart-d8db193c-94a8-410e-9582-a86b7a9aa04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091487823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2091487823
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/120.edn_genbits.894648479
Short name T316
Test name
Test status
Simulation time 52956504 ps
CPU time 1.25 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 219032 kb
Host smart-ee959d68-00ed-49e7-9633-0e57d222f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894648479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.894648479
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_genbits.3175857617
Short name T673
Test name
Test status
Simulation time 140914051 ps
CPU time 1.55 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 220400 kb
Host smart-e4ebc826-569f-4d5a-89e0-edd4d658437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175857617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3175857617
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_genbits.3446787483
Short name T45
Test name
Test status
Simulation time 349036227 ps
CPU time 1.33 seconds
Started Jul 02 09:56:12 AM PDT 24
Finished Jul 02 09:56:13 AM PDT 24
Peak memory 217816 kb
Host smart-36f0c0e1-feba-4cf4-b9b0-cffda85c8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446787483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3446787483
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3080464632
Short name T265
Test name
Test status
Simulation time 27827687 ps
CPU time 1 seconds
Started Jul 02 09:46:22 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 206956 kb
Host smart-33efb94a-6a84-4205-9a51-c995212713f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080464632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3080464632
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.592120044
Short name T300
Test name
Test status
Simulation time 87827631 ps
CPU time 2.46 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:23 AM PDT 24
Peak memory 206964 kb
Host smart-bd5293ec-d3e8-4681-8e27-846ae5b0f39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592120044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.592120044
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.211576786
Short name T947
Test name
Test status
Simulation time 97422519 ps
CPU time 1.4 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 219396 kb
Host smart-65b79e54-a0c8-4c87-be0a-8509bc2e0b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211576786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.211576786
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_smoke.3873752043
Short name T280
Test name
Test status
Simulation time 36232700 ps
CPU time 0.89 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 215640 kb
Host smart-5b306d96-4baf-422a-a97f-ce4cefe3e35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873752043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3873752043
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/100.edn_genbits.1630594592
Short name T818
Test name
Test status
Simulation time 46788110 ps
CPU time 1.28 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218640 kb
Host smart-635a8d9d-10b9-462f-98bf-25ce1b7ff382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630594592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1630594592
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.208951722
Short name T106
Test name
Test status
Simulation time 70175980 ps
CPU time 1.07 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 218984 kb
Host smart-886f5ad4-507e-4357-aac5-195c74191ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208951722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.208951722
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.591876545
Short name T336
Test name
Test status
Simulation time 42048702 ps
CPU time 1.43 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218932 kb
Host smart-8830f029-e5ec-47d3-99b0-a4a9370acb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591876545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.591876545
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1486238022
Short name T331
Test name
Test status
Simulation time 380997258 ps
CPU time 1.51 seconds
Started Jul 02 09:56:27 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 220612 kb
Host smart-0204b816-d23a-4ec4-b9b7-838c5ea5ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486238022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1486238022
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1650962818
Short name T335
Test name
Test status
Simulation time 97155788 ps
CPU time 1.49 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 219224 kb
Host smart-a69d13a5-a4ca-41e2-a1e2-07a743a7668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650962818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1650962818
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.842765295
Short name T320
Test name
Test status
Simulation time 56753707 ps
CPU time 1.88 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 218884 kb
Host smart-db4d2065-10b0-4453-966c-3872829e9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842765295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.842765295
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.4257499480
Short name T313
Test name
Test status
Simulation time 69016937 ps
CPU time 1.5 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 218988 kb
Host smart-db45543c-f0cd-40b7-9b52-4f15a57c0457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257499480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4257499480
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/160.edn_alert.4276782466
Short name T907
Test name
Test status
Simulation time 91756024 ps
CPU time 1.24 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 216036 kb
Host smart-807ea3c8-4d06-4ebd-b64b-8bdacb24ce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276782466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4276782466
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.1219699613
Short name T152
Test name
Test status
Simulation time 51290902 ps
CPU time 1.29 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219528 kb
Host smart-182b3106-7c47-48a1-aed4-ed997c270102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219699613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1219699613
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2162125548
Short name T864
Test name
Test status
Simulation time 31386612 ps
CPU time 1.25 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 217684 kb
Host smart-24bb4f0e-4478-4e03-8688-e21d7ddee0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162125548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2162125548
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/200.edn_genbits.3040061637
Short name T333
Test name
Test status
Simulation time 45224270 ps
CPU time 1.13 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 217756 kb
Host smart-526328da-798e-49dc-bd2a-51a4d5b09b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040061637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3040061637
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1792173520
Short name T37
Test name
Test status
Simulation time 57169149 ps
CPU time 0.83 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 215824 kb
Host smart-7c4338f2-c714-457e-b682-388567549258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792173520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1792173520
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/2.edn_intr.3133225844
Short name T111
Test name
Test status
Simulation time 36041609 ps
CPU time 0.86 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 216000 kb
Host smart-5db94c4c-6da3-4eca-84c7-af573ab6c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133225844 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3133225844
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/177.edn_genbits.1363250307
Short name T537
Test name
Test status
Simulation time 52192890 ps
CPU time 1.91 seconds
Started Jul 02 09:57:00 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 220700 kb
Host smart-9973b0e3-bba6-4429-984b-4e86ea1002ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363250307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1363250307
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3774750516
Short name T1054
Test name
Test status
Simulation time 86333998 ps
CPU time 1.18 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 207032 kb
Host smart-775a6991-f8ec-47ed-bdf9-420a63e6d4be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774750516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3774750516
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3631818529
Short name T270
Test name
Test status
Simulation time 254308147 ps
CPU time 6.63 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 206960 kb
Host smart-7685c342-3f4c-4e16-b7af-f0379001a5dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631818529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3631818529
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3500164315
Short name T1013
Test name
Test status
Simulation time 21729168 ps
CPU time 1.45 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 215296 kb
Host smart-1e4a5337-5937-4a75-8ba8-97167875c3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500164315 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3500164315
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3416515775
Short name T258
Test name
Test status
Simulation time 42887272 ps
CPU time 0.91 seconds
Started Jul 02 09:46:18 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 206976 kb
Host smart-08e96ba5-4468-4aca-b440-4fa4339dbcfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416515775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3416515775
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3593449662
Short name T1117
Test name
Test status
Simulation time 21520448 ps
CPU time 0.81 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206864 kb
Host smart-031e17a8-7052-45e9-a7cf-c99e695d879a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593449662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3593449662
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.939971534
Short name T1123
Test name
Test status
Simulation time 32804273 ps
CPU time 1.37 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206920 kb
Host smart-5ae37d36-1ab6-44e7-bd6e-7caa323d4ab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939971534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.939971534
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1588583019
Short name T1024
Test name
Test status
Simulation time 343889397 ps
CPU time 1.8 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 215180 kb
Host smart-3f0394fa-bfb3-4931-985e-5a2f4a11acad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588583019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1588583019
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1294065653
Short name T1017
Test name
Test status
Simulation time 28650095 ps
CPU time 1.24 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 206952 kb
Host smart-4eed68eb-208a-4e3d-b4f3-d7502b17cc19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294065653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1294065653
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2757608992
Short name T1034
Test name
Test status
Simulation time 283535516 ps
CPU time 3.19 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 207120 kb
Host smart-d2f60bae-07b7-4e96-9f48-b42948b35673
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757608992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2757608992
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2196529430
Short name T1083
Test name
Test status
Simulation time 46227431 ps
CPU time 0.88 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 207120 kb
Host smart-fc424738-feaa-4713-828c-53f6a6a943fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196529430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2196529430
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.176274577
Short name T1000
Test name
Test status
Simulation time 52256907 ps
CPU time 0.91 seconds
Started Jul 02 09:46:32 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 207000 kb
Host smart-62f255dd-aafa-47c7-b957-19ca9955d83b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176274577 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.176274577
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3325050165
Short name T1053
Test name
Test status
Simulation time 19533554 ps
CPU time 0.85 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 206688 kb
Host smart-58be6b8c-9671-4137-988c-41e724f647cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325050165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3325050165
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4017414644
Short name T1019
Test name
Test status
Simulation time 25326219 ps
CPU time 0.94 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206932 kb
Host smart-335c0866-ea48-4887-926c-84935bac02aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017414644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4017414644
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3466424849
Short name T1003
Test name
Test status
Simulation time 102713564 ps
CPU time 2.17 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 215224 kb
Host smart-d6580162-f8fa-49d8-85c5-ef464645320e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466424849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3466424849
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.551445058
Short name T1091
Test name
Test status
Simulation time 136292322 ps
CPU time 1.54 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 215168 kb
Host smart-cb0940f0-4a79-4607-b9a1-fc84533ed17d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551445058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.551445058
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1761909429
Short name T1065
Test name
Test status
Simulation time 78222092 ps
CPU time 1.1 seconds
Started Jul 02 09:46:29 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 215204 kb
Host smart-87a22935-e330-4a27-88fb-4fd0d13f4f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761909429 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1761909429
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3154361685
Short name T260
Test name
Test status
Simulation time 54174704 ps
CPU time 0.87 seconds
Started Jul 02 09:46:36 AM PDT 24
Finished Jul 02 09:46:38 AM PDT 24
Peak memory 206724 kb
Host smart-679c952a-d59b-4afc-bee1-6fb2c3fe911f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154361685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3154361685
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2688417218
Short name T1114
Test name
Test status
Simulation time 21528685 ps
CPU time 0.85 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 206900 kb
Host smart-a8be41c6-6bdd-4d1e-8612-8252ce6e6f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688417218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2688417218
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2354968148
Short name T1036
Test name
Test status
Simulation time 102446283 ps
CPU time 1.03 seconds
Started Jul 02 09:46:37 AM PDT 24
Finished Jul 02 09:46:39 AM PDT 24
Peak memory 207036 kb
Host smart-f88c53a3-4527-4dc5-8494-cc0baf8ec212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354968148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2354968148
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2916503481
Short name T1086
Test name
Test status
Simulation time 88863692 ps
CPU time 1.91 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 215284 kb
Host smart-28608382-81c2-42cf-891a-043e5184a803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916503481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2916503481
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3474201999
Short name T287
Test name
Test status
Simulation time 79890777 ps
CPU time 2.29 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 207056 kb
Host smart-ab8d5b0c-d35e-4f51-9344-2786e699ec73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474201999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3474201999
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2898338828
Short name T1006
Test name
Test status
Simulation time 470265901 ps
CPU time 1.54 seconds
Started Jul 02 09:46:30 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 215144 kb
Host smart-d8aa0d63-feb7-4d8c-a413-595c07577dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898338828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2898338828
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3811816627
Short name T1020
Test name
Test status
Simulation time 70217341 ps
CPU time 0.85 seconds
Started Jul 02 09:46:31 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 206960 kb
Host smart-70d9bb9f-60d5-4444-83c7-e0637c7a550c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811816627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3811816627
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2120247515
Short name T1027
Test name
Test status
Simulation time 13818385 ps
CPU time 0.92 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206864 kb
Host smart-35b1eebd-e523-4891-8e56-f1743f63f588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120247515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2120247515
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.445553648
Short name T1074
Test name
Test status
Simulation time 75046441 ps
CPU time 1.17 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 207168 kb
Host smart-d2831476-2b48-4bd8-8810-3672457651b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445553648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.445553648
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3879181993
Short name T1098
Test name
Test status
Simulation time 92467253 ps
CPU time 2.08 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 215224 kb
Host smart-4386930e-a552-40be-95f2-393e3bbeb579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879181993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3879181993
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3664059391
Short name T1059
Test name
Test status
Simulation time 223786724 ps
CPU time 1.63 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:37 AM PDT 24
Peak memory 215236 kb
Host smart-08465ccf-1ba1-4fb6-acaf-f60b76251f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664059391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3664059391
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1193947825
Short name T1021
Test name
Test status
Simulation time 19849390 ps
CPU time 1.15 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 216328 kb
Host smart-09506191-4b51-4a80-98e1-8e5211275ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193947825 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1193947825
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1802693269
Short name T1078
Test name
Test status
Simulation time 13317880 ps
CPU time 0.9 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 206956 kb
Host smart-ef669bf3-dd3d-48a6-b321-57fa1ea8fbb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802693269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1802693269
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1848962306
Short name T1101
Test name
Test status
Simulation time 42792684 ps
CPU time 0.84 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206916 kb
Host smart-13889558-7794-4643-95bd-8ec74c12ba44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848962306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1848962306
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.754003054
Short name T1025
Test name
Test status
Simulation time 54446392 ps
CPU time 1.13 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 206924 kb
Host smart-0a0a09dd-8be6-4c0c-acdd-02538a0d7ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754003054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.754003054
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4292134910
Short name T1028
Test name
Test status
Simulation time 309236197 ps
CPU time 4.84 seconds
Started Jul 02 09:46:32 AM PDT 24
Finished Jul 02 09:46:38 AM PDT 24
Peak memory 215156 kb
Host smart-d86e1efa-07fc-434a-b577-1d9883fdad02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292134910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4292134910
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2116462249
Short name T298
Test name
Test status
Simulation time 107971581 ps
CPU time 2.77 seconds
Started Jul 02 09:46:29 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 207024 kb
Host smart-688dd803-c017-4a64-abdb-fb74cfd20d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116462249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2116462249
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2320891064
Short name T1015
Test name
Test status
Simulation time 31103431 ps
CPU time 1.51 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 218072 kb
Host smart-c7d9a67a-c921-4e1b-8b29-e13a920d453d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320891064 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2320891064
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.580166094
Short name T261
Test name
Test status
Simulation time 16086399 ps
CPU time 0.91 seconds
Started Jul 02 09:46:33 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 206956 kb
Host smart-71ca7182-d274-4692-b4aa-6a8c2e82661c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580166094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.580166094
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3248330068
Short name T1039
Test name
Test status
Simulation time 14963845 ps
CPU time 0.91 seconds
Started Jul 02 09:46:46 AM PDT 24
Finished Jul 02 09:46:49 AM PDT 24
Peak memory 206912 kb
Host smart-04c93d5b-b0f2-4dcd-8701-887bd128dab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248330068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3248330068
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1769518007
Short name T276
Test name
Test status
Simulation time 26806248 ps
CPU time 1.19 seconds
Started Jul 02 09:46:54 AM PDT 24
Finished Jul 02 09:46:57 AM PDT 24
Peak memory 206900 kb
Host smart-ae6c22fb-f295-4c0e-a697-449383516ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769518007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1769518007
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3587012262
Short name T1001
Test name
Test status
Simulation time 78540854 ps
CPU time 2.98 seconds
Started Jul 02 09:46:33 AM PDT 24
Finished Jul 02 09:46:37 AM PDT 24
Peak memory 215160 kb
Host smart-2c1f5bcc-0808-43f8-bc49-627634ed35fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587012262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3587012262
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3458038202
Short name T1100
Test name
Test status
Simulation time 41931473 ps
CPU time 1.39 seconds
Started Jul 02 09:46:37 AM PDT 24
Finished Jul 02 09:46:39 AM PDT 24
Peak memory 206984 kb
Host smart-a0058890-2dd3-405f-9a44-20d6c9a850dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458038202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3458038202
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4019586980
Short name T1040
Test name
Test status
Simulation time 14910988 ps
CPU time 0.94 seconds
Started Jul 02 09:46:57 AM PDT 24
Finished Jul 02 09:46:58 AM PDT 24
Peak memory 206900 kb
Host smart-04339430-a212-4efa-92f2-f7e4e54a57e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019586980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4019586980
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2902930465
Short name T1125
Test name
Test status
Simulation time 12946503 ps
CPU time 0.88 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 206884 kb
Host smart-5bf37c63-2574-4a85-8296-9c94a0881720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902930465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2902930465
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1000348130
Short name T279
Test name
Test status
Simulation time 296732129 ps
CPU time 1.42 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206972 kb
Host smart-d7262372-1627-4fc0-932c-a7b155fae6d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000348130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1000348130
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.129486186
Short name T1055
Test name
Test status
Simulation time 428048671 ps
CPU time 4.24 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 215500 kb
Host smart-89bc1b4e-03be-4c61-bedb-0dfbdd147ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129486186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.129486186
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2109485369
Short name T1122
Test name
Test status
Simulation time 418437559 ps
CPU time 1.53 seconds
Started Jul 02 09:46:44 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 215128 kb
Host smart-cccf725d-2393-4510-a2ac-ac5e4049cf99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109485369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2109485369
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2762960302
Short name T1088
Test name
Test status
Simulation time 122137660 ps
CPU time 2.05 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 215088 kb
Host smart-9b01cb43-4e52-4a7f-8d93-08e471087bf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762960302 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2762960302
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4218322325
Short name T1082
Test name
Test status
Simulation time 17019309 ps
CPU time 0.91 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:41 AM PDT 24
Peak memory 206932 kb
Host smart-a5cf5d9f-6ee8-4a17-9f0e-b8ebd3996848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218322325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4218322325
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3246522643
Short name T1104
Test name
Test status
Simulation time 48735877 ps
CPU time 0.83 seconds
Started Jul 02 09:46:36 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 206692 kb
Host smart-4dbc2c1f-5931-48c5-92d9-0e246c77d21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246522643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3246522643
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1591064592
Short name T1051
Test name
Test status
Simulation time 295714453 ps
CPU time 1.48 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206828 kb
Host smart-466f6118-056b-4f42-ade7-ccefdfe302a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591064592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1591064592
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3167937700
Short name T1011
Test name
Test status
Simulation time 41761029 ps
CPU time 1.68 seconds
Started Jul 02 09:46:42 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 215356 kb
Host smart-59e101c0-6679-44f3-8168-574f8a38d9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167937700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3167937700
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1547196767
Short name T1080
Test name
Test status
Simulation time 506243091 ps
CPU time 2.65 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 215100 kb
Host smart-d45c758e-5950-49f9-a882-e4186a82c52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547196767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1547196767
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1131373254
Short name T1126
Test name
Test status
Simulation time 34143542 ps
CPU time 1.56 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 218876 kb
Host smart-2723d06a-30d7-4020-a26c-ee7869fc252f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131373254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1131373254
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.961040833
Short name T998
Test name
Test status
Simulation time 22352060 ps
CPU time 0.91 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 206968 kb
Host smart-f94e6e9b-e220-4f2f-b0a6-924d6f43ad76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961040833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.961040833
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1171727805
Short name T1018
Test name
Test status
Simulation time 18822393 ps
CPU time 0.87 seconds
Started Jul 02 09:46:41 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 206872 kb
Host smart-e2dccc0e-ce0c-4ed5-be5f-1fdc662b2988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171727805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1171727805
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2127716342
Short name T273
Test name
Test status
Simulation time 94201970 ps
CPU time 1.29 seconds
Started Jul 02 09:46:52 AM PDT 24
Finished Jul 02 09:46:55 AM PDT 24
Peak memory 206940 kb
Host smart-11e0b9f8-a2d1-4ea7-bbc1-4a66f5bb6a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127716342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2127716342
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3310688774
Short name T1016
Test name
Test status
Simulation time 237843281 ps
CPU time 2.47 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 215260 kb
Host smart-f7fb53c1-12ef-4346-bf24-3c3d0dc25b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310688774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3310688774
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2256944045
Short name T1092
Test name
Test status
Simulation time 97316706 ps
CPU time 1.64 seconds
Started Jul 02 09:46:41 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 215140 kb
Host smart-322cec31-ca28-46f3-8b3e-00dd52e3f0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256944045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2256944045
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1352069917
Short name T1045
Test name
Test status
Simulation time 58432361 ps
CPU time 1.45 seconds
Started Jul 02 09:46:41 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 215292 kb
Host smart-8faf3461-a82d-49e4-b6e9-8f1b86816ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352069917 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1352069917
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2885186103
Short name T264
Test name
Test status
Simulation time 17660174 ps
CPU time 0.86 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206880 kb
Host smart-f6f5eda9-5249-4506-8531-2f1963406c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885186103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2885186103
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.896103806
Short name T1129
Test name
Test status
Simulation time 13326154 ps
CPU time 0.86 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 206848 kb
Host smart-8c054a1c-09f5-4792-b1cc-34e03e3ec1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896103806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.896103806
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3784674750
Short name T274
Test name
Test status
Simulation time 83419480 ps
CPU time 1.18 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206928 kb
Host smart-6e4e74eb-8dda-4bfc-8e19-6022f31f9fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784674750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3784674750
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3320596806
Short name T1109
Test name
Test status
Simulation time 231809917 ps
CPU time 3.34 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:45 AM PDT 24
Peak memory 215196 kb
Host smart-fdc999b9-d110-4866-afd4-f3361285a927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320596806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3320596806
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.342158458
Short name T294
Test name
Test status
Simulation time 226078635 ps
CPU time 1.53 seconds
Started Jul 02 09:46:36 AM PDT 24
Finished Jul 02 09:46:39 AM PDT 24
Peak memory 215120 kb
Host smart-4a241344-ebbc-4497-8330-1f985702f48c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342158458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.342158458
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1860364752
Short name T1128
Test name
Test status
Simulation time 31005528 ps
CPU time 1.4 seconds
Started Jul 02 09:46:52 AM PDT 24
Finished Jul 02 09:46:54 AM PDT 24
Peak memory 215212 kb
Host smart-2831bb03-7d4d-4508-9971-3146bd5f7679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860364752 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1860364752
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1912053246
Short name T275
Test name
Test status
Simulation time 35612464 ps
CPU time 0.81 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206904 kb
Host smart-d72dd572-dc1d-4f95-94f9-f9cf0a1c4562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912053246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1912053246
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1495083211
Short name T1048
Test name
Test status
Simulation time 15358892 ps
CPU time 0.9 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 206892 kb
Host smart-ae2877cc-60b0-4d72-ae48-7282254a3958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495083211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1495083211
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3701824093
Short name T1031
Test name
Test status
Simulation time 67086867 ps
CPU time 1.44 seconds
Started Jul 02 09:46:54 AM PDT 24
Finished Jul 02 09:46:57 AM PDT 24
Peak memory 206908 kb
Host smart-93cdf241-d779-40c0-a180-997377bd91c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701824093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3701824093
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2168747590
Short name T1002
Test name
Test status
Simulation time 25097898 ps
CPU time 1.83 seconds
Started Jul 02 09:46:44 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 215300 kb
Host smart-16f2583c-38f6-4bd1-9057-f00f254f5340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168747590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2168747590
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3844577066
Short name T1076
Test name
Test status
Simulation time 98697954 ps
CPU time 2.69 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:38 AM PDT 24
Peak memory 206956 kb
Host smart-1269cfa1-e98d-4a41-8ca8-bccb9055e70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844577066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3844577066
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.372237185
Short name T1033
Test name
Test status
Simulation time 44834691 ps
CPU time 1.54 seconds
Started Jul 02 09:46:31 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 215140 kb
Host smart-84d63e97-4f3f-43f7-bab4-0aabe1d25fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372237185 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.372237185
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3441469391
Short name T262
Test name
Test status
Simulation time 15123698 ps
CPU time 0.98 seconds
Started Jul 02 09:46:49 AM PDT 24
Finished Jul 02 09:46:50 AM PDT 24
Peak memory 206924 kb
Host smart-d3fc80ce-aedd-4bea-9d68-787284efd65f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441469391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3441469391
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2919469921
Short name T1035
Test name
Test status
Simulation time 13631459 ps
CPU time 0.88 seconds
Started Jul 02 09:46:52 AM PDT 24
Finished Jul 02 09:46:55 AM PDT 24
Peak memory 206892 kb
Host smart-6c99bfde-e83a-4d45-9e72-3598044dfd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919469921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2919469921
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3484882416
Short name T1046
Test name
Test status
Simulation time 35752491 ps
CPU time 1.07 seconds
Started Jul 02 09:46:42 AM PDT 24
Finished Jul 02 09:46:45 AM PDT 24
Peak memory 207032 kb
Host smart-8491da1b-659d-461f-8ad7-a1b959aff5a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484882416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3484882416
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.329021108
Short name T1121
Test name
Test status
Simulation time 210124325 ps
CPU time 2.21 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 215276 kb
Host smart-d88b5740-247d-48bd-b80f-f7d1e8339e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329021108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.329021108
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4160270622
Short name T288
Test name
Test status
Simulation time 63695515 ps
CPU time 1.91 seconds
Started Jul 02 09:46:58 AM PDT 24
Finished Jul 02 09:47:01 AM PDT 24
Peak memory 207060 kb
Host smart-f39b9820-3986-4889-ab7e-e8c91c3b8e74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160270622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4160270622
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4249376423
Short name T267
Test name
Test status
Simulation time 41729179 ps
CPU time 1.58 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 206916 kb
Host smart-df236a57-28a9-42f3-b90d-5365fe5944b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249376423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4249376423
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1397851117
Short name T1111
Test name
Test status
Simulation time 353303248 ps
CPU time 5.28 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 207040 kb
Host smart-c7c64d2f-24de-4ce1-966e-280552af2849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397851117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1397851117
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1843496253
Short name T1009
Test name
Test status
Simulation time 14186009 ps
CPU time 0.93 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206964 kb
Host smart-97393e45-19f6-47aa-964c-5a67bcee451b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843496253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1843496253
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.756041984
Short name T1107
Test name
Test status
Simulation time 28290210 ps
CPU time 1.75 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 215148 kb
Host smart-eb828052-efd9-405d-8cb2-585df7e0427e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756041984 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.756041984
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2190709838
Short name T266
Test name
Test status
Simulation time 16305038 ps
CPU time 0.8 seconds
Started Jul 02 09:46:22 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 206748 kb
Host smart-1a25a0c2-ba30-4eda-a659-91234eeeb121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190709838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2190709838
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1649799663
Short name T1066
Test name
Test status
Simulation time 28956241 ps
CPU time 0.9 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206832 kb
Host smart-35c95689-a748-45e5-b5d5-7d70e10d5543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649799663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1649799663
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2267996621
Short name T1043
Test name
Test status
Simulation time 48199130 ps
CPU time 1.23 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 207096 kb
Host smart-d5f73827-deb3-4dcd-b47d-f5259d1a820a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267996621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2267996621
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.790144214
Short name T1008
Test name
Test status
Simulation time 65094066 ps
CPU time 2.54 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 215264 kb
Host smart-aafe06da-2991-42f3-a8a6-4d77b889ceee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790144214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.790144214
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3270662335
Short name T289
Test name
Test status
Simulation time 106526934 ps
CPU time 2.64 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 207040 kb
Host smart-65d331d8-4b5c-402d-b004-9f56f9e049a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270662335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3270662335
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1105262979
Short name T1124
Test name
Test status
Simulation time 21631165 ps
CPU time 0.87 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 206892 kb
Host smart-a5fecf96-75d6-49b0-a816-577c9a2f148e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105262979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1105262979
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3845031553
Short name T1064
Test name
Test status
Simulation time 12703362 ps
CPU time 0.84 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 206868 kb
Host smart-be08984f-2a5b-4567-8a85-da1792b0a56f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845031553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3845031553
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4035257477
Short name T1090
Test name
Test status
Simulation time 14798253 ps
CPU time 0.9 seconds
Started Jul 02 09:46:54 AM PDT 24
Finished Jul 02 09:46:56 AM PDT 24
Peak memory 206848 kb
Host smart-4345d9f2-a872-403b-834e-6b7c5a58db68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035257477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4035257477
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1580712408
Short name T1097
Test name
Test status
Simulation time 17744264 ps
CPU time 0.93 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 206896 kb
Host smart-45ae87bc-9c3c-49f4-b4af-6c0977d8d0d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580712408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1580712408
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.393523161
Short name T1075
Test name
Test status
Simulation time 12857949 ps
CPU time 0.8 seconds
Started Jul 02 09:46:37 AM PDT 24
Finished Jul 02 09:46:39 AM PDT 24
Peak memory 206692 kb
Host smart-3a063e7b-e028-4d92-ae9a-a62b62c28519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393523161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.393523161
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3447541062
Short name T1012
Test name
Test status
Simulation time 12563819 ps
CPU time 0.86 seconds
Started Jul 02 09:46:44 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206876 kb
Host smart-6479d91e-0ae5-4d06-8016-fe9dde706860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447541062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3447541062
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3185703407
Short name T1071
Test name
Test status
Simulation time 103120932 ps
CPU time 0.8 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 206716 kb
Host smart-565bb9a9-2bae-491f-813c-44d575623896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185703407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3185703407
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3349993668
Short name T1106
Test name
Test status
Simulation time 15153474 ps
CPU time 0.91 seconds
Started Jul 02 09:46:52 AM PDT 24
Finished Jul 02 09:46:54 AM PDT 24
Peak memory 206852 kb
Host smart-8aa4280e-e732-45aa-b7d1-6e7441d7d04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349993668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3349993668
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3921105672
Short name T1061
Test name
Test status
Simulation time 41599372 ps
CPU time 0.84 seconds
Started Jul 02 09:46:58 AM PDT 24
Finished Jul 02 09:47:01 AM PDT 24
Peak memory 207040 kb
Host smart-3210e9bc-d667-4b77-aabf-27b26ae802a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921105672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3921105672
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.250086856
Short name T1084
Test name
Test status
Simulation time 59114415 ps
CPU time 0.8 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206720 kb
Host smart-2eaace77-82df-458e-b1f8-c81731fcbdda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250086856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.250086856
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.429386936
Short name T271
Test name
Test status
Simulation time 25581971 ps
CPU time 1.2 seconds
Started Jul 02 09:46:31 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 207028 kb
Host smart-d301bc85-e4d0-4711-8d37-93b3f4c9cbe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429386936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.429386936
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2422888076
Short name T268
Test name
Test status
Simulation time 454124352 ps
CPU time 5.75 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 207028 kb
Host smart-dd783669-475f-44af-a4ad-3daa9c5edc22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422888076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2422888076
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.384534209
Short name T272
Test name
Test status
Simulation time 31410833 ps
CPU time 0.96 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 206968 kb
Host smart-728f2fe2-8535-4acd-902f-9840c800686f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384534209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.384534209
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1102914005
Short name T1038
Test name
Test status
Simulation time 22769055 ps
CPU time 1.38 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 215296 kb
Host smart-beeb5d5c-b3c8-4884-a166-3c1948a2179d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102914005 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1102914005
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4172886318
Short name T1058
Test name
Test status
Simulation time 36412249 ps
CPU time 0.86 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 206728 kb
Host smart-02adaa42-592e-4a0d-982b-7fcc1adcbf1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172886318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4172886318
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.646036158
Short name T1095
Test name
Test status
Simulation time 18222633 ps
CPU time 0.83 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206820 kb
Host smart-4da443c5-6425-498b-8cad-9c10b95e8ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646036158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.646036158
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3600155668
Short name T1094
Test name
Test status
Simulation time 36211402 ps
CPU time 1.08 seconds
Started Jul 02 09:46:22 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 206992 kb
Host smart-fc96fb43-04ca-41f3-832a-628224be9c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600155668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3600155668
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3485589139
Short name T1030
Test name
Test status
Simulation time 58211471 ps
CPU time 2.34 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 215240 kb
Host smart-77071a81-c39d-4037-95e9-9650bf1ff662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485589139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3485589139
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3617282854
Short name T295
Test name
Test status
Simulation time 74618718 ps
CPU time 2.13 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 207024 kb
Host smart-e7226bab-58c3-458d-9f58-1e2b630b2aea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617282854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3617282854
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2998063832
Short name T1087
Test name
Test status
Simulation time 28494547 ps
CPU time 0.91 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:47 AM PDT 24
Peak memory 206868 kb
Host smart-987e6ed5-b228-4337-a13e-48e7cdddb316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998063832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2998063832
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4043460910
Short name T1073
Test name
Test status
Simulation time 37739688 ps
CPU time 0.85 seconds
Started Jul 02 09:46:44 AM PDT 24
Finished Jul 02 09:46:47 AM PDT 24
Peak memory 206912 kb
Host smart-f7572391-18a2-4e4a-b247-81b63829563f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043460910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4043460910
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1455747773
Short name T1119
Test name
Test status
Simulation time 39156353 ps
CPU time 0.81 seconds
Started Jul 02 09:46:55 AM PDT 24
Finished Jul 02 09:46:57 AM PDT 24
Peak memory 206916 kb
Host smart-61da4302-8cd7-4c88-a431-d54731bb62d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455747773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1455747773
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3417888485
Short name T1041
Test name
Test status
Simulation time 36051397 ps
CPU time 0.87 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206908 kb
Host smart-b6385d6f-b43c-4144-a690-81cec289c43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417888485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3417888485
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1350781143
Short name T1120
Test name
Test status
Simulation time 43753955 ps
CPU time 0.85 seconds
Started Jul 02 09:46:41 AM PDT 24
Finished Jul 02 09:46:44 AM PDT 24
Peak memory 206864 kb
Host smart-9d3d8de2-3e38-4e6e-98ce-aecbeb7c407d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350781143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1350781143
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2560062618
Short name T1004
Test name
Test status
Simulation time 49936149 ps
CPU time 0.9 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206916 kb
Host smart-0431f8a7-c7f8-450e-985e-f57057f4df1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560062618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2560062618
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2574413050
Short name T1070
Test name
Test status
Simulation time 43992731 ps
CPU time 0.86 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206772 kb
Host smart-9d794cbb-8f45-4ae9-aa9e-c6155cb35333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574413050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2574413050
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1726797631
Short name T1085
Test name
Test status
Simulation time 22265264 ps
CPU time 0.9 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 206864 kb
Host smart-7a6bdd75-dc1a-4d48-b290-e2fd8cb4d76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726797631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1726797631
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3655726164
Short name T1062
Test name
Test status
Simulation time 43260835 ps
CPU time 0.79 seconds
Started Jul 02 09:46:39 AM PDT 24
Finished Jul 02 09:46:41 AM PDT 24
Peak memory 206656 kb
Host smart-fc123468-f559-4d50-a4d9-1ca9c1aba53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655726164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3655726164
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.600048562
Short name T1014
Test name
Test status
Simulation time 29505807 ps
CPU time 0.93 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206824 kb
Host smart-ec06276d-59eb-4e4a-a27b-a566273312d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600048562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.600048562
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.563706498
Short name T1089
Test name
Test status
Simulation time 67436610 ps
CPU time 1.61 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206964 kb
Host smart-4575b525-7c6c-4c6a-981e-a2fc0dc69075
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563706498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.563706498
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2764204090
Short name T269
Test name
Test status
Simulation time 515717733 ps
CPU time 3.61 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 207072 kb
Host smart-b7d509ed-abdb-4007-a4a6-e6227ec355f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764204090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2764204090
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.445247071
Short name T1007
Test name
Test status
Simulation time 25193363 ps
CPU time 0.9 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 206968 kb
Host smart-8adfe430-8ead-4d67-89c4-8c9820ebc6d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445247071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.445247071
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4208415939
Short name T1077
Test name
Test status
Simulation time 83702906 ps
CPU time 1.6 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 215200 kb
Host smart-6c9fc327-e8ca-46a1-8da8-4966975153b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208415939 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4208415939
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3645437274
Short name T278
Test name
Test status
Simulation time 20427408 ps
CPU time 0.84 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 206880 kb
Host smart-76746167-8297-4112-90a8-38024c1cab95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645437274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3645437274
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1557001597
Short name T1010
Test name
Test status
Simulation time 42888400 ps
CPU time 0.86 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 206912 kb
Host smart-2c5b1453-84e3-43db-9acd-c58049a03863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557001597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1557001597
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.663030000
Short name T1079
Test name
Test status
Simulation time 67790378 ps
CPU time 1.08 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 206972 kb
Host smart-c179228e-01f2-4f65-8cb1-cbcd32167183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663030000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.663030000
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2810674609
Short name T1108
Test name
Test status
Simulation time 116527004 ps
CPU time 2.55 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 215316 kb
Host smart-f796c749-47cd-456a-9bc9-0d6ac4c6e4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810674609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2810674609
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3376027030
Short name T296
Test name
Test status
Simulation time 54618029 ps
CPU time 1.65 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 206808 kb
Host smart-d6de18f2-991a-4294-bedd-899de605c3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376027030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3376027030
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1025104908
Short name T1096
Test name
Test status
Simulation time 43467703 ps
CPU time 0.84 seconds
Started Jul 02 09:46:57 AM PDT 24
Finished Jul 02 09:46:59 AM PDT 24
Peak memory 206908 kb
Host smart-b19cb294-0e75-4f85-b9df-b27b672f73c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025104908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1025104908
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1465732292
Short name T1026
Test name
Test status
Simulation time 23772613 ps
CPU time 0.91 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 206912 kb
Host smart-c16c9b38-6e32-444c-a3c7-860f7f5d5cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465732292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1465732292
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3968754964
Short name T1005
Test name
Test status
Simulation time 68768809 ps
CPU time 0.89 seconds
Started Jul 02 09:46:42 AM PDT 24
Finished Jul 02 09:46:45 AM PDT 24
Peak memory 206868 kb
Host smart-10a5faa6-6cc1-4d31-839d-7a5fa1a0af87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968754964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3968754964
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.60732973
Short name T1022
Test name
Test status
Simulation time 29809325 ps
CPU time 0.88 seconds
Started Jul 02 09:46:38 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 206920 kb
Host smart-43573c94-0743-4793-9fc4-6bf4a2455969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60732973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.60732973
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.765843213
Short name T1032
Test name
Test status
Simulation time 76283142 ps
CPU time 0.84 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 206864 kb
Host smart-0e0e889b-5eca-4b1d-a60a-a47f3446b12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765843213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.765843213
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3697271509
Short name T1127
Test name
Test status
Simulation time 17016630 ps
CPU time 0.85 seconds
Started Jul 02 09:46:52 AM PDT 24
Finished Jul 02 09:46:55 AM PDT 24
Peak memory 206916 kb
Host smart-2996ed36-f3c1-4646-b378-188f6fb6f261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697271509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3697271509
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2479923997
Short name T1029
Test name
Test status
Simulation time 14127274 ps
CPU time 0.88 seconds
Started Jul 02 09:46:44 AM PDT 24
Finished Jul 02 09:46:47 AM PDT 24
Peak memory 206976 kb
Host smart-0bc821e6-9587-4910-a9b2-edf65e1676f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479923997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2479923997
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1741271977
Short name T1115
Test name
Test status
Simulation time 20169918 ps
CPU time 0.83 seconds
Started Jul 02 09:46:43 AM PDT 24
Finished Jul 02 09:46:47 AM PDT 24
Peak memory 206956 kb
Host smart-622907e5-a635-4f6c-ada6-949dea7ec8f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741271977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1741271977
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1371932780
Short name T1068
Test name
Test status
Simulation time 20527332 ps
CPU time 0.9 seconds
Started Jul 02 09:46:47 AM PDT 24
Finished Jul 02 09:46:49 AM PDT 24
Peak memory 206896 kb
Host smart-94819b52-d97b-4568-9a61-9858a4fe7a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371932780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1371932780
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3678184596
Short name T1105
Test name
Test status
Simulation time 14913748 ps
CPU time 0.93 seconds
Started Jul 02 09:46:45 AM PDT 24
Finished Jul 02 09:46:48 AM PDT 24
Peak memory 207056 kb
Host smart-6e3fedec-3769-4d3b-83a4-3782e068510c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678184596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3678184596
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2976584353
Short name T1067
Test name
Test status
Simulation time 50455005 ps
CPU time 1.15 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:42 AM PDT 24
Peak memory 215284 kb
Host smart-2e6d073c-775f-4612-aa1e-265a55d4415d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976584353 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2976584353
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2631093830
Short name T1069
Test name
Test status
Simulation time 14357367 ps
CPU time 0.94 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 206976 kb
Host smart-2c2293a9-a34a-44a9-bba0-07810375acfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631093830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2631093830
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3807546221
Short name T1049
Test name
Test status
Simulation time 25121015 ps
CPU time 0.92 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206896 kb
Host smart-e1b13c98-f1d4-440c-976c-d8a0e04b5a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807546221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3807546221
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1927127414
Short name T277
Test name
Test status
Simulation time 59601355 ps
CPU time 1.37 seconds
Started Jul 02 09:46:31 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 207008 kb
Host smart-bebf81d7-3461-4ea1-993d-3d92da9273fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927127414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1927127414
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4213667549
Short name T1102
Test name
Test status
Simulation time 62610091 ps
CPU time 2.49 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 215380 kb
Host smart-41a4777d-e630-466c-bff7-b32983c17243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213667549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4213667549
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.366423132
Short name T1112
Test name
Test status
Simulation time 188713973 ps
CPU time 1.58 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 206992 kb
Host smart-a81376de-b6f8-404c-8874-d197d4155ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366423132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.366423132
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.14644257
Short name T997
Test name
Test status
Simulation time 31878325 ps
CPU time 1.6 seconds
Started Jul 02 09:46:32 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 219568 kb
Host smart-3059c32a-9147-4955-a8a5-d5cc03efe48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644257 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.14644257
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2878530818
Short name T1116
Test name
Test status
Simulation time 54330486 ps
CPU time 0.8 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 206548 kb
Host smart-55086733-390d-4003-96a6-3ea4298defaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878530818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2878530818
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.346637808
Short name T1056
Test name
Test status
Simulation time 21635734 ps
CPU time 0.84 seconds
Started Jul 02 09:46:26 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 206900 kb
Host smart-53de7a95-9145-4323-8e2d-7b686a526197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346637808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.346637808
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2047168773
Short name T1037
Test name
Test status
Simulation time 33197486 ps
CPU time 1.12 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 207032 kb
Host smart-e936f286-3a98-4905-959c-4b17681a210a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047168773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2047168773
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1498732870
Short name T999
Test name
Test status
Simulation time 144955226 ps
CPU time 2.74 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:45 AM PDT 24
Peak memory 215212 kb
Host smart-b91518f9-d515-4f83-8d1e-2dc5c925b3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498732870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1498732870
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3648407566
Short name T299
Test name
Test status
Simulation time 96691867 ps
CPU time 1.56 seconds
Started Jul 02 09:46:27 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 207104 kb
Host smart-123100f3-7baa-46ee-8d7f-ed55e897c69f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648407566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3648407566
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2771356873
Short name T1110
Test name
Test status
Simulation time 26004854 ps
CPU time 1.07 seconds
Started Jul 02 09:46:33 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 215212 kb
Host smart-692b0fcb-970e-4141-a9f2-aa7537ad5f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771356873 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2771356873
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1970767038
Short name T263
Test name
Test status
Simulation time 31102024 ps
CPU time 0.81 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:31 AM PDT 24
Peak memory 206728 kb
Host smart-5bc13b80-de14-49fa-8e1c-b5938d1db6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970767038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1970767038
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1310938734
Short name T1042
Test name
Test status
Simulation time 31975269 ps
CPU time 0.83 seconds
Started Jul 02 09:46:30 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 206688 kb
Host smart-2fd98ccf-3c7e-4bfd-9dc0-744666cc3b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310938734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1310938734
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1253497446
Short name T1113
Test name
Test status
Simulation time 116839504 ps
CPU time 1.03 seconds
Started Jul 02 09:46:40 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 207116 kb
Host smart-e56bd457-f0fa-404c-ae43-d4cdedc54a28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253497446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1253497446
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1501414278
Short name T1044
Test name
Test status
Simulation time 34818517 ps
CPU time 2.29 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 215224 kb
Host smart-3b8a627b-6c88-45bd-a060-3456f46e59c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501414278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1501414278
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2866780632
Short name T1103
Test name
Test status
Simulation time 189232402 ps
CPU time 1.67 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 207112 kb
Host smart-80491d2b-d1d7-4a47-83a0-2af2a6a382cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866780632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2866780632
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3598944723
Short name T1057
Test name
Test status
Simulation time 139423852 ps
CPU time 1.21 seconds
Started Jul 02 09:46:37 AM PDT 24
Finished Jul 02 09:46:39 AM PDT 24
Peak memory 215164 kb
Host smart-133ba45d-da16-49bd-926f-9cb21fe36e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598944723 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3598944723
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.309463533
Short name T1063
Test name
Test status
Simulation time 54337574 ps
CPU time 0.93 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 206980 kb
Host smart-bdc2788e-7741-431b-8206-77f12db0c7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309463533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.309463533
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2400607521
Short name T1072
Test name
Test status
Simulation time 33521703 ps
CPU time 0.79 seconds
Started Jul 02 09:46:30 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 206724 kb
Host smart-8066118b-4f1f-4251-a75f-e3b6d2a5c2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400607521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2400607521
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1594976914
Short name T1099
Test name
Test status
Simulation time 18232995 ps
CPU time 1.03 seconds
Started Jul 02 09:46:35 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 206960 kb
Host smart-1959177b-4067-4281-98d9-1ca082626ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594976914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1594976914
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1355755889
Short name T1047
Test name
Test status
Simulation time 86211704 ps
CPU time 1.55 seconds
Started Jul 02 09:46:29 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 215180 kb
Host smart-053baeb8-4b58-41c5-82b8-f40a19ed5f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355755889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1355755889
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.956924257
Short name T1081
Test name
Test status
Simulation time 222807985 ps
CPU time 1.59 seconds
Started Jul 02 09:46:28 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 207004 kb
Host smart-2490555f-b9dc-447c-979e-c6b8134b375e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956924257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.956924257
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1581584669
Short name T1093
Test name
Test status
Simulation time 120522870 ps
CPU time 1.34 seconds
Started Jul 02 09:46:34 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 215280 kb
Host smart-c9b9b306-b15f-4728-85b5-20c2db6946ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581584669 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1581584669
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.263596765
Short name T1023
Test name
Test status
Simulation time 14671508 ps
CPU time 0.9 seconds
Started Jul 02 09:46:32 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 206988 kb
Host smart-5a2a1f83-a531-4cf7-923e-0c44deeff9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263596765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.263596765
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4230632320
Short name T1050
Test name
Test status
Simulation time 23094968 ps
CPU time 1 seconds
Started Jul 02 09:46:31 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 206864 kb
Host smart-2f4e752d-95a6-4276-8188-6e72cd0384a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230632320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4230632320
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1116711664
Short name T1052
Test name
Test status
Simulation time 99632962 ps
CPU time 1.37 seconds
Started Jul 02 09:46:33 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 207120 kb
Host smart-c5777867-8051-43d8-8e94-012e3ba5b475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116711664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1116711664
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2096876832
Short name T1060
Test name
Test status
Simulation time 439044742 ps
CPU time 3.95 seconds
Started Jul 02 09:46:29 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 215220 kb
Host smart-0ee4cd95-01dd-477d-8fce-4b75cfddbbb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096876832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2096876832
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1559267264
Short name T1118
Test name
Test status
Simulation time 305349797 ps
CPU time 2.29 seconds
Started Jul 02 09:46:30 AM PDT 24
Finished Jul 02 09:46:34 AM PDT 24
Peak memory 206992 kb
Host smart-394b232e-0062-4583-a39e-3d09322e139e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559267264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1559267264
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.7373620
Short name T614
Test name
Test status
Simulation time 27559253 ps
CPU time 1.18 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 220000 kb
Host smart-cc98dddc-7a30-4e56-a4f2-bef634eba127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7373620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.7373620
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.887587492
Short name T660
Test name
Test status
Simulation time 24986082 ps
CPU time 0.89 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 215504 kb
Host smart-9a244daf-698b-46f4-afc5-5f4bf55fb644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887587492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.887587492
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.354306078
Short name T911
Test name
Test status
Simulation time 24245045 ps
CPU time 0.97 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 224112 kb
Host smart-21738aad-7c80-4664-b2e7-f91147c07790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354306078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.354306078
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1337782258
Short name T646
Test name
Test status
Simulation time 20623609 ps
CPU time 1.02 seconds
Started Jul 02 09:55:32 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 215884 kb
Host smart-76431242-7ba9-4f22-9344-40aa96d10cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337782258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1337782258
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2931266252
Short name T30
Test name
Test status
Simulation time 14865972 ps
CPU time 0.98 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:21 AM PDT 24
Peak memory 207388 kb
Host smart-b3e4874d-4c92-4f85-940a-89d5d8f14f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931266252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2931266252
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2104859232
Short name T19
Test name
Test status
Simulation time 968542177 ps
CPU time 7.92 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 237968 kb
Host smart-b37cd8b0-16de-4300-9d71-3deac727217e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104859232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2104859232
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_stress_all.67814147
Short name T994
Test name
Test status
Simulation time 441231384 ps
CPU time 6.97 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 217804 kb
Host smart-11555aae-f597-4caa-9d93-099444b4bc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67814147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.67814147
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.105460316
Short name T230
Test name
Test status
Simulation time 7062867268 ps
CPU time 184.7 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 222492 kb
Host smart-98cc2b10-6586-4f46-a4a2-e452fa0d41aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105460316 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.105460316
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2575812196
Short name T83
Test name
Test status
Simulation time 46527981 ps
CPU time 1.13 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 219896 kb
Host smart-48db4c44-f721-48fb-9fe4-b23080e20c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575812196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2575812196
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1307685920
Short name T959
Test name
Test status
Simulation time 61129847 ps
CPU time 0.93 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 215480 kb
Host smart-6025dc74-459b-47fd-a142-9b9fc0ea027e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307685920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1307685920
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.459983078
Short name T204
Test name
Test status
Simulation time 65342194 ps
CPU time 0.84 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 216716 kb
Host smart-6b7ce4ac-b223-464d-9180-f04aa6d3f9b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459983078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.459983078
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2294026620
Short name T206
Test name
Test status
Simulation time 43884252 ps
CPU time 1.33 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 217328 kb
Host smart-e1eb9c16-0b93-40bf-890c-58425d051166
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294026620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2294026620
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1079623460
Short name T984
Test name
Test status
Simulation time 94474710 ps
CPU time 0.99 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 220920 kb
Host smart-6c4b13d7-924c-494f-a49f-c721100e0acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079623460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1079623460
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.509441781
Short name T495
Test name
Test status
Simulation time 32874141 ps
CPU time 1.28 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:30 AM PDT 24
Peak memory 219052 kb
Host smart-e2105d06-dc8c-44bd-b661-5294b5f57d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509441781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.509441781
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3755109355
Short name T365
Test name
Test status
Simulation time 29132024 ps
CPU time 0.99 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 215728 kb
Host smart-4513d572-dea5-48ae-8c14-b4e034017c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755109355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3755109355
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3146461244
Short name T658
Test name
Test status
Simulation time 34325782 ps
CPU time 0.89 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 207452 kb
Host smart-214ac477-bcd3-4c91-b4d3-4e840848c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146461244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3146461244
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2791660435
Short name T57
Test name
Test status
Simulation time 441460458 ps
CPU time 6.64 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 236360 kb
Host smart-f5c59d32-0483-47e1-874d-235db8aef0c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791660435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2791660435
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2458477027
Short name T422
Test name
Test status
Simulation time 25700093 ps
CPU time 0.92 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 215568 kb
Host smart-61c18932-6999-4b16-9586-73f87ccd8319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458477027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2458477027
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3867802697
Short name T393
Test name
Test status
Simulation time 472855216 ps
CPU time 5.61 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 215580 kb
Host smart-096e5131-98a3-4de2-a634-962b9109a61a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867802697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3867802697
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2561141618
Short name T724
Test name
Test status
Simulation time 52882070223 ps
CPU time 1317.89 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 10:17:36 AM PDT 24
Peak memory 224064 kb
Host smart-15a18ab8-fa85-4374-959c-8aa8c4dd6707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561141618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2561141618
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2527369026
Short name T529
Test name
Test status
Simulation time 47415891 ps
CPU time 1.18 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 221628 kb
Host smart-9b937bff-795c-4d40-81ac-746ba9232dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527369026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2527369026
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.909072253
Short name T656
Test name
Test status
Simulation time 25056349 ps
CPU time 0.85 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 215168 kb
Host smart-59583a3e-7bff-490e-a0f5-e0d400362396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909072253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.909072253
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3102978146
Short name T747
Test name
Test status
Simulation time 56554916 ps
CPU time 0.9 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 216268 kb
Host smart-c2658d3d-2fe9-4896-b74d-0d4483c79145
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102978146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3102978146
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2318219792
Short name T285
Test name
Test status
Simulation time 35864385 ps
CPU time 0.92 seconds
Started Jul 02 09:55:32 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 218588 kb
Host smart-b23098e9-47fb-4821-b60b-78a24514ca85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318219792 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2318219792
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1506655854
Short name T813
Test name
Test status
Simulation time 35607165 ps
CPU time 0.88 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 218776 kb
Host smart-810f042c-2cff-4a97-9bf2-ddba73b58d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506655854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1506655854
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.2621538878
Short name T545
Test name
Test status
Simulation time 46480761 ps
CPU time 0.99 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 224148 kb
Host smart-750760eb-54e3-430c-bb56-b0828b4deb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621538878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2621538878
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.352230263
Short name T377
Test name
Test status
Simulation time 51319166 ps
CPU time 0.87 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:30 AM PDT 24
Peak memory 215580 kb
Host smart-79cf2cd4-fff4-4ba0-8644-e1d16e3624f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352230263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.352230263
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.762363873
Short name T518
Test name
Test status
Simulation time 1911782613 ps
CPU time 5.11 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 220896 kb
Host smart-ac4088ec-188b-4e6b-b257-eaafb7640bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762363873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.762363873
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1047922826
Short name T38
Test name
Test status
Simulation time 77165177344 ps
CPU time 661.85 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 10:06:39 AM PDT 24
Peak memory 220476 kb
Host smart-9385fb4b-48d4-47c8-9b65-c6267ac8ada8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047922826 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1047922826
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2010206019
Short name T808
Test name
Test status
Simulation time 27281854 ps
CPU time 1.23 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 220152 kb
Host smart-5592c8f3-17c7-4eac-b4b4-0a3c1d5613be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010206019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2010206019
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3700124157
Short name T473
Test name
Test status
Simulation time 306197882 ps
CPU time 1.29 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 217780 kb
Host smart-7e1b19f9-e42c-4103-b32d-6e3a8cdf0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700124157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3700124157
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1352358179
Short name T372
Test name
Test status
Simulation time 64014200 ps
CPU time 1.18 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 217684 kb
Host smart-5ed4c32d-14aa-4233-bc0e-be17cde5a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352358179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1352358179
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3300955753
Short name T769
Test name
Test status
Simulation time 80841408 ps
CPU time 1.42 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 219260 kb
Host smart-65390f51-8121-4402-aad5-4f23a4e55f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300955753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3300955753
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.365510915
Short name T387
Test name
Test status
Simulation time 93333368 ps
CPU time 1.22 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 219076 kb
Host smart-338cdaf4-193c-45c3-ade8-f5fd5c0f045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365510915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.365510915
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2424476064
Short name T449
Test name
Test status
Simulation time 52789474 ps
CPU time 1.01 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 217756 kb
Host smart-853cd3fd-9c91-4733-81dd-6629d4b6974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424476064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2424476064
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2618607008
Short name T179
Test name
Test status
Simulation time 90600296 ps
CPU time 1.07 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 218920 kb
Host smart-2e21203a-dccc-4e73-aae5-5f2667dab300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618607008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2618607008
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.563104112
Short name T590
Test name
Test status
Simulation time 82277848 ps
CPU time 1.01 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 217616 kb
Host smart-79252d4a-da43-4f3f-87b3-1682797c0284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563104112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.563104112
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.4077647308
Short name T800
Test name
Test status
Simulation time 29737265 ps
CPU time 1.22 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220180 kb
Host smart-49c8f5c2-ba75-4cd1-90f3-6050641dcbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077647308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.4077647308
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.3797749835
Short name T681
Test name
Test status
Simulation time 32172337 ps
CPU time 1.37 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:53 AM PDT 24
Peak memory 220476 kb
Host smart-bcff3a31-6c63-4959-adda-28e4ba3af221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797749835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3797749835
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.2161284367
Short name T146
Test name
Test status
Simulation time 73563137 ps
CPU time 1.13 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 219100 kb
Host smart-b667ac92-d420-45b7-90b9-f59960fe82f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161284367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2161284367
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3214996116
Short name T870
Test name
Test status
Simulation time 30388361 ps
CPU time 1.28 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 220316 kb
Host smart-777b675e-cab8-4afd-9567-138c28700fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214996116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3214996116
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1186440826
Short name T918
Test name
Test status
Simulation time 295517856 ps
CPU time 1.28 seconds
Started Jul 02 09:56:33 AM PDT 24
Finished Jul 02 09:56:38 AM PDT 24
Peak memory 221052 kb
Host smart-b86bd1a5-7b4c-4c4a-90da-c781c6b77091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186440826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1186440826
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1562678506
Short name T596
Test name
Test status
Simulation time 187966728 ps
CPU time 2.97 seconds
Started Jul 02 09:56:44 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 219132 kb
Host smart-3f042205-eff4-4d2d-b02e-49c78304053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562678506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1562678506
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.754542667
Short name T859
Test name
Test status
Simulation time 30219276 ps
CPU time 1.17 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 219600 kb
Host smart-76a72aab-e54e-4959-a16e-b5f7e59e1494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754542667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.754542667
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.366877431
Short name T880
Test name
Test status
Simulation time 49918995 ps
CPU time 0.88 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 207020 kb
Host smart-50d75d8f-d6fa-4772-a1d7-3afe33fd1a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366877431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.366877431
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3070673564
Short name T568
Test name
Test status
Simulation time 20707060 ps
CPU time 1.02 seconds
Started Jul 02 09:55:34 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 217348 kb
Host smart-3be33895-92fc-462c-a0f5-5f880ce221d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070673564 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3070673564
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.79994376
Short name T174
Test name
Test status
Simulation time 24853573 ps
CPU time 0.99 seconds
Started Jul 02 09:55:43 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 224236 kb
Host smart-fcbdaf9b-019c-49f1-9ac1-d1bcbe50546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79994376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.79994376
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.659801610
Short name T832
Test name
Test status
Simulation time 102905165 ps
CPU time 1.53 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 219136 kb
Host smart-496031e3-530f-4614-bb15-ce1b9f20ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659801610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.659801610
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.781654280
Short name T764
Test name
Test status
Simulation time 24646236 ps
CPU time 1.14 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 215912 kb
Host smart-e515d430-e6b5-49f3-9349-20d8d5e8867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781654280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.781654280
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2628920382
Short name T379
Test name
Test status
Simulation time 46932026 ps
CPU time 0.92 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 215592 kb
Host smart-92fb7bdb-e551-46a7-8913-9265b737567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628920382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2628920382
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4057125806
Short name T59
Test name
Test status
Simulation time 186119527 ps
CPU time 4.04 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:29 AM PDT 24
Peak memory 218808 kb
Host smart-30ba6e78-aa5f-4734-9fe3-5047be24c08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057125806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4057125806
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.2697874260
Short name T970
Test name
Test status
Simulation time 64004942 ps
CPU time 1.11 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 220132 kb
Host smart-7cad98c5-72db-44f4-8f10-232f318965c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697874260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2697874260
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.852725902
Short name T562
Test name
Test status
Simulation time 46044575 ps
CPU time 1.14 seconds
Started Jul 02 09:56:44 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 218704 kb
Host smart-4b751ceb-9fae-48b1-a891-06dc860d471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852725902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.852725902
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.439021649
Short name T890
Test name
Test status
Simulation time 51193405 ps
CPU time 1.28 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 219072 kb
Host smart-782d6513-72aa-49c7-b2c3-57958d4fbf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439021649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.439021649
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.479646400
Short name T842
Test name
Test status
Simulation time 67561572 ps
CPU time 1.34 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 218656 kb
Host smart-d12b343b-7df1-4059-941f-b721c2269841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479646400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.479646400
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2207319817
Short name T898
Test name
Test status
Simulation time 24932695 ps
CPU time 1.22 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:58 AM PDT 24
Peak memory 218972 kb
Host smart-ee52a40b-890f-4c8d-a8b2-643d2956be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207319817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2207319817
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3400271191
Short name T472
Test name
Test status
Simulation time 102071291 ps
CPU time 1.58 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 219304 kb
Host smart-59cfbcff-49af-4300-bcda-80fa1520636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400271191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3400271191
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3454051278
Short name T829
Test name
Test status
Simulation time 46972325 ps
CPU time 1.2 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 219048 kb
Host smart-341906bf-a58b-4785-8f87-6d8d30ebe09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454051278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3454051278
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.193238776
Short name T532
Test name
Test status
Simulation time 73591253 ps
CPU time 1.13 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 218932 kb
Host smart-746eb9cd-cb82-445e-aa93-1a3eab99fafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193238776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.193238776
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3980577359
Short name T12
Test name
Test status
Simulation time 41181023 ps
CPU time 1.48 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 220356 kb
Host smart-8b12841f-74d8-4680-8aa0-6a9239c08338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980577359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3980577359
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3727480345
Short name T985
Test name
Test status
Simulation time 24663937 ps
CPU time 1.24 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 220068 kb
Host smart-6f9ac2ae-9697-482a-94ee-609acc5f190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727480345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3727480345
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.4146069614
Short name T857
Test name
Test status
Simulation time 231219474 ps
CPU time 1.59 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 219372 kb
Host smart-f29543d6-4b4c-48f7-9198-4899ba4d5f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146069614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4146069614
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1847565617
Short name T502
Test name
Test status
Simulation time 43581574 ps
CPU time 1.21 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 220156 kb
Host smart-571b8f8c-dc2f-4639-a528-aa4e3554a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847565617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1847565617
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3128687398
Short name T385
Test name
Test status
Simulation time 60166462 ps
CPU time 1.56 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 219108 kb
Host smart-bf152ee0-d892-4720-9b2e-cda75fa67f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128687398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3128687398
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1785982656
Short name T822
Test name
Test status
Simulation time 402609964 ps
CPU time 3.78 seconds
Started Jul 02 09:56:32 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219984 kb
Host smart-660eb949-ca54-43f7-a7cf-8b37fe7fa561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785982656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1785982656
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1714533009
Short name T609
Test name
Test status
Simulation time 75324891 ps
CPU time 1.17 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 217736 kb
Host smart-75d89782-5f6b-4dcf-9e57-20941e14dc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714533009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1714533009
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2805281942
Short name T308
Test name
Test status
Simulation time 41663529 ps
CPU time 1.14 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 220204 kb
Host smart-7bdd192b-075c-484f-bf94-48df460a21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805281942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2805281942
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.4042198812
Short name T301
Test name
Test status
Simulation time 91771865 ps
CPU time 1.23 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 218896 kb
Host smart-da93a608-3eff-44d8-b7f8-760f2e4efe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042198812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4042198812
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2315177844
Short name T417
Test name
Test status
Simulation time 15251048 ps
CPU time 0.89 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 207064 kb
Host smart-8f28703f-5f5f-477d-851b-0176c8c783a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315177844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2315177844
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2840540279
Short name T661
Test name
Test status
Simulation time 13271701 ps
CPU time 0.92 seconds
Started Jul 02 09:55:33 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 216384 kb
Host smart-f6cabb70-7b21-466c-ae35-664889345015
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840540279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2840540279
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3812265341
Short name T123
Test name
Test status
Simulation time 126514830 ps
CPU time 1.65 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 217172 kb
Host smart-34f3e93c-7853-4a13-a668-d8f4c126c436
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812265341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3812265341
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2376567755
Short name T142
Test name
Test status
Simulation time 26511579 ps
CPU time 1.33 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 229872 kb
Host smart-02a186e4-7f11-4cbd-bfe4-cd863ddedb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376567755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2376567755
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2564030596
Short name T505
Test name
Test status
Simulation time 27536074 ps
CPU time 1.36 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 218976 kb
Host smart-4d26650d-2c56-4fca-8c8d-b0dedef2314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564030596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2564030596
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3166868260
Short name T14
Test name
Test status
Simulation time 28192005 ps
CPU time 1.02 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 224344 kb
Host smart-090f1b13-69b7-4875-b0f1-70590ca5311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166868260 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3166868260
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1844684533
Short name T541
Test name
Test status
Simulation time 42733943 ps
CPU time 0.92 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 215460 kb
Host smart-812f1acc-a8c1-4180-ab16-ba55609e63b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844684533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1844684533
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.537000977
Short name T4
Test name
Test status
Simulation time 265253822 ps
CPU time 1.91 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 215612 kb
Host smart-474a127c-4faa-4097-9f1e-d2f1fbd384a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537000977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.537000977
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1546047517
Short name T854
Test name
Test status
Simulation time 293238643831 ps
CPU time 1750.94 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 10:24:56 AM PDT 24
Peak memory 225924 kb
Host smart-ec3e355c-1c9f-4e66-a736-d08918293ce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546047517 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1546047517
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1642955804
Short name T535
Test name
Test status
Simulation time 24229389 ps
CPU time 1.25 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219112 kb
Host smart-99eb6f4b-9a14-489d-90a5-80460a3b3ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642955804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1642955804
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.568094189
Short name T257
Test name
Test status
Simulation time 27834037 ps
CPU time 1.29 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 219860 kb
Host smart-add87a06-4554-4cb2-946b-5915406037f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568094189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.568094189
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2171463735
Short name T831
Test name
Test status
Simulation time 82845773 ps
CPU time 1.15 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 219196 kb
Host smart-ff07afe7-51b5-4bcb-a57c-78eaa6a41739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171463735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2171463735
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.362712614
Short name T672
Test name
Test status
Simulation time 28983107 ps
CPU time 1.25 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218964 kb
Host smart-6833ba80-8012-4670-a945-acb95b38b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362712614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.362712614
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.859150387
Short name T47
Test name
Test status
Simulation time 66909486 ps
CPU time 1.36 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 215616 kb
Host smart-cd352577-67fb-493f-95f3-9625931afc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859150387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.859150387
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2775597234
Short name T826
Test name
Test status
Simulation time 24127056 ps
CPU time 1.27 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:58 AM PDT 24
Peak memory 221024 kb
Host smart-44b09a60-c823-4f01-8d2f-073c8bcc9783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775597234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2775597234
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1722254422
Short name T707
Test name
Test status
Simulation time 24063026 ps
CPU time 1.21 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 217920 kb
Host smart-12a1d822-fc9a-46a4-96b0-40f6d4d52a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722254422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1722254422
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.647038797
Short name T745
Test name
Test status
Simulation time 91475983 ps
CPU time 1.22 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 219748 kb
Host smart-7849a218-b1b8-4ef7-8a35-f6d388f0ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647038797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.647038797
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1577686698
Short name T900
Test name
Test status
Simulation time 37599443 ps
CPU time 1.04 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:53 AM PDT 24
Peak memory 217768 kb
Host smart-53d5feb9-6fdb-4551-9263-4d644bac365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577686698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1577686698
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2146544309
Short name T173
Test name
Test status
Simulation time 24764995 ps
CPU time 1.16 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 218960 kb
Host smart-217e7de0-ab8c-49b8-9b3f-d07720281780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146544309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2146544309
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.137011679
Short name T466
Test name
Test status
Simulation time 86845276 ps
CPU time 1.15 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 217704 kb
Host smart-501b3dd4-c3dd-4240-882c-6ebb2337167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137011679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.137011679
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.4266896492
Short name T572
Test name
Test status
Simulation time 51746909 ps
CPU time 1.36 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 220196 kb
Host smart-85c246e1-3821-449d-9992-06f8c5728081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266896492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.4266896492
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.2654308031
Short name T531
Test name
Test status
Simulation time 26438047 ps
CPU time 1.25 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 220312 kb
Host smart-eaccb387-f2be-4794-b4d6-e97f97426ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654308031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2654308031
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.273183201
Short name T620
Test name
Test status
Simulation time 73355814 ps
CPU time 1.37 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219560 kb
Host smart-ddbc8e7d-193c-4b74-adc5-b1cf916aff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273183201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.273183201
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2971917815
Short name T671
Test name
Test status
Simulation time 65788285 ps
CPU time 1.18 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 216124 kb
Host smart-49fbc3b3-faee-44f0-8f17-155dcad6adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971917815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2971917815
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2752506815
Short name T638
Test name
Test status
Simulation time 64202885 ps
CPU time 1.36 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 219440 kb
Host smart-ace70555-604f-4e73-a356-43b1110ef178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752506815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2752506815
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2704839594
Short name T256
Test name
Test status
Simulation time 117431243 ps
CPU time 1.32 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 216020 kb
Host smart-b5311c75-0c95-40eb-9965-702c8a27f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704839594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2704839594
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3389184345
Short name T904
Test name
Test status
Simulation time 72994999 ps
CPU time 1.23 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219464 kb
Host smart-31c10109-d05a-4820-87fa-bdf37663b147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389184345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3389184345
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.495279652
Short name T253
Test name
Test status
Simulation time 124408879 ps
CPU time 1.29 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 216008 kb
Host smart-927a5360-44cf-46dc-89a3-fb5a3234b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495279652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.495279652
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1258671741
Short name T697
Test name
Test status
Simulation time 12811743 ps
CPU time 0.91 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 207736 kb
Host smart-86856960-32d6-4386-bb2f-30c21cf42958
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258671741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1258671741
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4101591850
Short name T286
Test name
Test status
Simulation time 39744383 ps
CPU time 0.96 seconds
Started Jul 02 09:55:36 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 218852 kb
Host smart-a2fce204-7569-4d45-ac33-c39c975a374a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101591850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4101591850
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.470465797
Short name T184
Test name
Test status
Simulation time 23767437 ps
CPU time 1.05 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:32 AM PDT 24
Peak memory 224308 kb
Host smart-83ba60b7-8d10-46ab-869f-fe7a83e7fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470465797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.470465797
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.654663785
Short name T242
Test name
Test status
Simulation time 44037026 ps
CPU time 1.34 seconds
Started Jul 02 09:55:38 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 218828 kb
Host smart-1ae39af2-e509-492a-957e-f6132065c7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654663785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.654663785
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4001001240
Short name T963
Test name
Test status
Simulation time 21155851 ps
CPU time 1.17 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 224464 kb
Host smart-45b02b53-0fc4-4eef-8964-88e51e349510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001001240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4001001240
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.74509751
Short name T762
Test name
Test status
Simulation time 38677401 ps
CPU time 0.88 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 215644 kb
Host smart-e98981f6-6636-4d90-995e-04d0fa1a8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74509751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.74509751
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1395878147
Short name T798
Test name
Test status
Simulation time 336963922 ps
CPU time 6.24 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 219688 kb
Host smart-3277ce8e-a598-49a7-910f-66ba9c95266d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395878147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1395878147
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3776007442
Short name T475
Test name
Test status
Simulation time 298456293101 ps
CPU time 1923.93 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 10:27:44 AM PDT 24
Peak memory 229748 kb
Host smart-386b1dbc-e415-4657-80df-774dd00baa55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776007442 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3776007442
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.271857354
Short name T642
Test name
Test status
Simulation time 74367967 ps
CPU time 1.09 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 219084 kb
Host smart-e287f909-a802-49cb-9ed7-fa23b7f836c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271857354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.271857354
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1675367596
Short name T882
Test name
Test status
Simulation time 53370111 ps
CPU time 1.17 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 219340 kb
Host smart-9dcba886-6c00-435e-9cc4-b7bdd7011dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675367596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1675367596
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.976408736
Short name T514
Test name
Test status
Simulation time 52160218 ps
CPU time 1.22 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 220288 kb
Host smart-43b3df91-b401-4ae2-b6b7-e981f0fea21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976408736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.976408736
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2870615287
Short name T368
Test name
Test status
Simulation time 153750531 ps
CPU time 1.13 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 217684 kb
Host smart-64c63b79-caf5-49aa-88ab-e7ac91aa5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870615287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2870615287
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.659765799
Short name T736
Test name
Test status
Simulation time 25225560 ps
CPU time 1.21 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 220320 kb
Host smart-c5c39690-0d5f-4d7f-8312-aa0b74343968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659765799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.659765799
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.356986317
Short name T752
Test name
Test status
Simulation time 46132776 ps
CPU time 1.99 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 218880 kb
Host smart-f1c97697-380b-4aab-8eb3-cae90241137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356986317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.356986317
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1569019033
Short name T916
Test name
Test status
Simulation time 50647731 ps
CPU time 1.32 seconds
Started Jul 02 09:56:46 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 216016 kb
Host smart-d0396160-ebb1-4c8f-8894-81bc4153a594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569019033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1569019033
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3069402263
Short name T739
Test name
Test status
Simulation time 39150580 ps
CPU time 1.48 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 220204 kb
Host smart-1c8e65c8-ff73-4864-9482-b0c6e5891244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069402263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3069402263
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.387496321
Short name T708
Test name
Test status
Simulation time 58689633 ps
CPU time 1.15 seconds
Started Jul 02 09:57:01 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 219584 kb
Host smart-6f3a24f3-eef8-4e9f-883c-a8705b284216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387496321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.387496321
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.463743317
Short name T330
Test name
Test status
Simulation time 86096172 ps
CPU time 1.28 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 218020 kb
Host smart-f89a64ae-07ee-472d-b45a-ac0c41d65657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463743317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.463743317
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3468703671
Short name T544
Test name
Test status
Simulation time 24615860 ps
CPU time 1.23 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220068 kb
Host smart-f91fcd86-14f1-40a5-9b56-e624f7a8c52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468703671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3468703671
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2116059422
Short name T406
Test name
Test status
Simulation time 871802987 ps
CPU time 7.7 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 220448 kb
Host smart-05390dd2-4887-4880-9b99-6cc8fd3596c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116059422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2116059422
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.548225273
Short name T750
Test name
Test status
Simulation time 121010932 ps
CPU time 1.17 seconds
Started Jul 02 09:56:29 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 219432 kb
Host smart-06bd04ff-a7fb-44ca-9648-6b678501233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548225273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.548225273
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3894808365
Short name T600
Test name
Test status
Simulation time 51151247 ps
CPU time 1.21 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 217584 kb
Host smart-c2f9626b-599b-40f4-8844-ab27778ebf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894808365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3894808365
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3727665790
Short name T731
Test name
Test status
Simulation time 83244677 ps
CPU time 1.45 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 219188 kb
Host smart-6f0be4cc-5063-4f1a-8d63-c5878b5467b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727665790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3727665790
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.65958494
Short name T31
Test name
Test status
Simulation time 49242643 ps
CPU time 1.12 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 219468 kb
Host smart-eb97847e-4723-4337-ad39-f4e51e9a8f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65958494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.65958494
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2025408296
Short name T241
Test name
Test status
Simulation time 39069727 ps
CPU time 1.63 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 218792 kb
Host smart-f3f01d19-689d-43af-8cfd-c7ceb266e5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025408296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2025408296
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.4111237901
Short name T757
Test name
Test status
Simulation time 78836248 ps
CPU time 1.07 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 220468 kb
Host smart-fc43cf49-57c3-4ef1-9c5b-4b96b443bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111237901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.4111237901
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.248703298
Short name T939
Test name
Test status
Simulation time 35560243 ps
CPU time 1.36 seconds
Started Jul 02 09:56:59 AM PDT 24
Finished Jul 02 09:57:04 AM PDT 24
Peak memory 218952 kb
Host smart-131b7b75-9b6d-42f1-b606-a0c17c379c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248703298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.248703298
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2194244825
Short name T699
Test name
Test status
Simulation time 410927689 ps
CPU time 1.33 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 220860 kb
Host smart-b21ded1b-1acb-4375-a89b-7e313b0a9b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194244825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2194244825
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1118470276
Short name T872
Test name
Test status
Simulation time 14996597 ps
CPU time 0.89 seconds
Started Jul 02 09:55:38 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 215224 kb
Host smart-bcdc8c1c-a963-4e60-9217-167d8bb1bc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118470276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1118470276
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2142907599
Short name T199
Test name
Test status
Simulation time 19236639 ps
CPU time 0.83 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 216580 kb
Host smart-8b08f4f4-7950-4fe7-b3ea-159ce944caf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142907599 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2142907599
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3695778254
Short name T581
Test name
Test status
Simulation time 117857182 ps
CPU time 1.25 seconds
Started Jul 02 09:55:43 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 217328 kb
Host smart-c044bb63-e439-4203-b4f9-c0bb377f0c75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695778254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3695778254
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.102825685
Short name T217
Test name
Test status
Simulation time 58148528 ps
CPU time 1.01 seconds
Started Jul 02 09:55:33 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 218800 kb
Host smart-5893f0e7-9d8f-4420-8a30-665f8e8d1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102825685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.102825685
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.821874785
Short name T909
Test name
Test status
Simulation time 43387605 ps
CPU time 0.97 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 224188 kb
Host smart-6077ac8e-cdea-4ffb-96bc-bae2a6bd7bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821874785 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.821874785
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3406708762
Short name T460
Test name
Test status
Simulation time 15215606 ps
CPU time 0.94 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 215684 kb
Host smart-5361ab6e-d143-4c4d-9021-8bfd355b7a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406708762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3406708762
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.607067847
Short name T450
Test name
Test status
Simulation time 121156302 ps
CPU time 1.58 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 218708 kb
Host smart-065b9a5e-0adb-45c5-940d-0e137de9a666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607067847 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.607067847
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3200343085
Short name T917
Test name
Test status
Simulation time 1019102041121 ps
CPU time 1319.16 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 10:17:39 AM PDT 24
Peak memory 224024 kb
Host smart-a1bc57e3-4848-4f65-8b3e-fabf645ddddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200343085 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3200343085
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1574410730
Short name T79
Test name
Test status
Simulation time 22906000 ps
CPU time 1.16 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:58 AM PDT 24
Peak memory 220052 kb
Host smart-bcda27a1-1fca-496a-b4eb-be1c4d95af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574410730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1574410730
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1003041289
Short name T652
Test name
Test status
Simulation time 75180207 ps
CPU time 1.45 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 219152 kb
Host smart-4fdeb0b2-d08c-4843-a1f9-9cce3b7bab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003041289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1003041289
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.576406763
Short name T56
Test name
Test status
Simulation time 65260343 ps
CPU time 1.06 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 219232 kb
Host smart-266b997d-da44-4588-9ef5-4bf293cb6558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576406763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.576406763
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1235575333
Short name T511
Test name
Test status
Simulation time 51899993 ps
CPU time 1.31 seconds
Started Jul 02 09:56:46 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 217736 kb
Host smart-b3df1838-7ead-4efc-93dd-61104bb16ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235575333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1235575333
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3686291081
Short name T851
Test name
Test status
Simulation time 71014033 ps
CPU time 1.1 seconds
Started Jul 02 09:56:33 AM PDT 24
Finished Jul 02 09:56:38 AM PDT 24
Peak memory 221580 kb
Host smart-d1e5c410-210f-4f6d-9d7b-0281b40d749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686291081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3686291081
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.116728637
Short name T459
Test name
Test status
Simulation time 91700719 ps
CPU time 1.65 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:58 AM PDT 24
Peak memory 220748 kb
Host smart-801a1f06-269f-4de1-a7d2-9c833e2d1f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116728637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.116728637
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1069646827
Short name T455
Test name
Test status
Simulation time 80700610 ps
CPU time 1.16 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 219044 kb
Host smart-5e2376c9-f08d-4f88-9ec9-1cac6540940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069646827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1069646827
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3249640968
Short name T749
Test name
Test status
Simulation time 81238445 ps
CPU time 1.8 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 219128 kb
Host smart-bd8242b2-3fb9-469f-b55c-558dd064861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249640968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3249640968
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.4279346222
Short name T972
Test name
Test status
Simulation time 49692439 ps
CPU time 1.68 seconds
Started Jul 02 09:56:46 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218844 kb
Host smart-cf0de856-87c4-4bd1-aff0-d0d715a7671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279346222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4279346222
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2067795909
Short name T101
Test name
Test status
Simulation time 28885337 ps
CPU time 1.36 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 215948 kb
Host smart-326ec0bd-4531-4847-a86e-df61cfb63e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067795909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2067795909
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2059214
Short name T860
Test name
Test status
Simulation time 77033185 ps
CPU time 1.6 seconds
Started Jul 02 09:56:33 AM PDT 24
Finished Jul 02 09:56:39 AM PDT 24
Peak memory 219148 kb
Host smart-ea9eed82-bc1c-45e1-8f00-5cef4c726b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2059214
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2171435798
Short name T905
Test name
Test status
Simulation time 123898551 ps
CPU time 1.31 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 220544 kb
Host smart-28ec78ba-c5f1-4a82-bba0-c6fdc5c14076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171435798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2171435798
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1765006421
Short name T344
Test name
Test status
Simulation time 282312563 ps
CPU time 3.81 seconds
Started Jul 02 09:56:44 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 220624 kb
Host smart-832dd928-b1e0-48c9-b91d-3a478775f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765006421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1765006421
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1143584372
Short name T778
Test name
Test status
Simulation time 46705492 ps
CPU time 1.19 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219008 kb
Host smart-bb8f8a92-802b-47cc-ab4e-1d3a68db5b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143584372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1143584372
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2755564789
Short name T773
Test name
Test status
Simulation time 38854883 ps
CPU time 1.52 seconds
Started Jul 02 09:57:05 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 218952 kb
Host smart-c08a4b27-a6f6-4ad4-8dce-c4aa42ab586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755564789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2755564789
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.383824464
Short name T648
Test name
Test status
Simulation time 96800596 ps
CPU time 1.26 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 221696 kb
Host smart-3a0eaa7e-8fcd-4016-8ec5-d851f94e2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383824464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.383824464
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2998335306
Short name T338
Test name
Test status
Simulation time 93010607 ps
CPU time 1.21 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 220004 kb
Host smart-8a58fcee-e4c2-4d98-93db-ec3c838af301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998335306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2998335306
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1953781342
Short name T404
Test name
Test status
Simulation time 42261919 ps
CPU time 1.11 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218868 kb
Host smart-be705af6-549d-445a-9618-e7510ba0398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953781342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1953781342
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.4227185071
Short name T734
Test name
Test status
Simulation time 146362592 ps
CPU time 3.23 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 220596 kb
Host smart-51253ae3-09a7-4130-bfef-f8564dc5ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227185071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4227185071
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.821842512
Short name T63
Test name
Test status
Simulation time 12789446 ps
CPU time 0.85 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 206896 kb
Host smart-e4209080-8957-4fed-ae74-b964e2bae5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821842512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.821842512
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2640747947
Short name T809
Test name
Test status
Simulation time 37830853 ps
CPU time 0.87 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 215700 kb
Host smart-b5a14b1a-8bba-4687-8d9d-af79b907dc56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640747947 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2640747947
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3185324809
Short name T465
Test name
Test status
Simulation time 111465048 ps
CPU time 1.03 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 218636 kb
Host smart-55fbaa65-3718-462e-8d03-90baa4c420e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185324809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3185324809
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4283608386
Short name T121
Test name
Test status
Simulation time 24817011 ps
CPU time 1.2 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 220076 kb
Host smart-4a077be9-87e0-4b17-92ea-b5e3ad8ccde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283608386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4283608386
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1991948650
Short name T549
Test name
Test status
Simulation time 71132187 ps
CPU time 1.34 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 218760 kb
Host smart-b00efc35-3183-4ddb-afd0-c11e32325a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991948650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1991948650
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1411890094
Short name T577
Test name
Test status
Simulation time 22858816 ps
CPU time 1.23 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 224328 kb
Host smart-afe432e5-944a-40b4-bc96-780a33459a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411890094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1411890094
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1995633162
Short name T639
Test name
Test status
Simulation time 21263141 ps
CPU time 1.04 seconds
Started Jul 02 09:55:44 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 215704 kb
Host smart-02d235af-0933-4270-937b-997ba6d88db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995633162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1995633162
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4267721973
Short name T988
Test name
Test status
Simulation time 367724904 ps
CPU time 4.35 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 215576 kb
Host smart-9f852091-5ecb-4388-8ee3-6145640194f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267721973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4267721973
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3569998328
Short name T405
Test name
Test status
Simulation time 23443775413 ps
CPU time 132.29 seconds
Started Jul 02 09:55:37 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 218172 kb
Host smart-cb1ae3b4-db01-4b42-b5ba-8c2dc8430d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569998328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3569998328
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3847746969
Short name T370
Test name
Test status
Simulation time 26418494 ps
CPU time 1.23 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 219936 kb
Host smart-b80d4676-15f8-470c-8d62-d8d9bc110aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847746969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3847746969
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.630125129
Short name T781
Test name
Test status
Simulation time 147348928 ps
CPU time 3.28 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 220604 kb
Host smart-cf702b7d-d2a1-4cd6-978b-f9b3906e0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630125129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.630125129
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1929540392
Short name T431
Test name
Test status
Simulation time 71491178 ps
CPU time 1.1 seconds
Started Jul 02 09:56:28 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219516 kb
Host smart-ac1efacf-1741-4057-9585-062e20437229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929540392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1929540392
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2340266650
Short name T345
Test name
Test status
Simulation time 135238490 ps
CPU time 2.43 seconds
Started Jul 02 09:57:00 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 220492 kb
Host smart-ff641277-b28b-434f-9ee8-76ae22c12e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340266650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2340266650
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1912011088
Short name T691
Test name
Test status
Simulation time 26378999 ps
CPU time 1.27 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219076 kb
Host smart-c4298675-b634-40c8-a528-25b991fa85ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912011088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1912011088
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1111690603
Short name T26
Test name
Test status
Simulation time 290537609 ps
CPU time 1.64 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 219008 kb
Host smart-0139ffb2-0a23-452d-a245-17c5b945e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111690603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1111690603
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1399654771
Short name T438
Test name
Test status
Simulation time 56729791 ps
CPU time 1.11 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 220396 kb
Host smart-c59e2b52-8da1-4edb-9c89-5d95771bca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399654771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1399654771
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.235176821
Short name T982
Test name
Test status
Simulation time 31796931 ps
CPU time 1.21 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 217580 kb
Host smart-a917fc75-3110-423b-8c2b-635b59924162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235176821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.235176821
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2607524505
Short name T682
Test name
Test status
Simulation time 81019107 ps
CPU time 1.1 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 219988 kb
Host smart-afacfa43-76e2-419d-856d-e79dc946549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607524505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2607524505
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2949694677
Short name T339
Test name
Test status
Simulation time 163465778 ps
CPU time 1.38 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 219308 kb
Host smart-e27e75a6-50ea-4ef5-95d4-2162e3599851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949694677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2949694677
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2653803195
Short name T255
Test name
Test status
Simulation time 30155916 ps
CPU time 1.4 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 216028 kb
Host smart-67c3a467-3bab-4aa0-98a0-19262443db1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653803195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2653803195
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1317894020
Short name T496
Test name
Test status
Simulation time 50646983 ps
CPU time 1.18 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 215672 kb
Host smart-f256c49c-a292-4b85-82d8-ffee6e2c0396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317894020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1317894020
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2962437610
Short name T513
Test name
Test status
Simulation time 24961141 ps
CPU time 1.21 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 220176 kb
Host smart-fb1d0bc2-d10e-47ad-93d7-d24780d09609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962437610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2962437610
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.410358706
Short name T557
Test name
Test status
Simulation time 118450547 ps
CPU time 1.31 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 217832 kb
Host smart-371d3f91-6dd0-4ced-9387-dedbb88e7e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410358706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.410358706
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.665195905
Short name T630
Test name
Test status
Simulation time 39969696 ps
CPU time 1.2 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 215996 kb
Host smart-f733d588-d174-4a8c-92d6-3a8854d89cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665195905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.665195905
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.348063126
Short name T619
Test name
Test status
Simulation time 52942238 ps
CPU time 1.23 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 219088 kb
Host smart-d3d4133c-b66b-4fd2-9543-ad7453e3be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348063126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.348063126
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2995108553
Short name T494
Test name
Test status
Simulation time 70477258 ps
CPU time 1.23 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 215996 kb
Host smart-e9e88c07-a07f-4d5f-a0f8-fc5b4c5c0587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995108553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2995108553
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2319630913
Short name T622
Test name
Test status
Simulation time 70301435 ps
CPU time 1.14 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 217476 kb
Host smart-3df7719e-9258-42c8-bc3d-891a5d236133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319630913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2319630913
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2535150932
Short name T825
Test name
Test status
Simulation time 48650605 ps
CPU time 1.21 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219912 kb
Host smart-0d4542d4-15fd-4fe3-9e0a-295801cdcde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535150932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2535150932
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2152611958
Short name T815
Test name
Test status
Simulation time 299147718 ps
CPU time 2.05 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:04 AM PDT 24
Peak memory 219052 kb
Host smart-a0bdc54f-6fd3-4e48-a7f2-d4fe78ae4b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152611958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2152611958
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3755224680
Short name T428
Test name
Test status
Simulation time 106260180 ps
CPU time 1.23 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 215984 kb
Host smart-2fa92d0a-7cb8-4473-8c14-59383b359f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755224680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3755224680
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1253656726
Short name T68
Test name
Test status
Simulation time 31528687 ps
CPU time 1.14 seconds
Started Jul 02 09:55:37 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 207036 kb
Host smart-d54f7b70-ebbc-4d4f-9932-8fa82b84ce8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253656726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1253656726
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1716180059
Short name T58
Test name
Test status
Simulation time 38116442 ps
CPU time 0.84 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 216600 kb
Host smart-10133025-2082-4068-a8f2-4ee59a858c3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716180059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1716180059
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2681931121
Short name T145
Test name
Test status
Simulation time 38072415 ps
CPU time 1.28 seconds
Started Jul 02 09:55:33 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 217160 kb
Host smart-c5186e3c-9a03-4455-abf8-0c654b038d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681931121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2681931121
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.364424420
Short name T863
Test name
Test status
Simulation time 88998096 ps
CPU time 3.14 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 219212 kb
Host smart-076760c1-0e6d-4034-abf2-91b8c1fe93bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364424420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.364424420
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2886458138
Short name T62
Test name
Test status
Simulation time 103234639 ps
CPU time 0.84 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 215648 kb
Host smart-6b95c595-3581-4455-9de7-a369c702dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886458138 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2886458138
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2920695119
Short name T684
Test name
Test status
Simulation time 18405894 ps
CPU time 0.98 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 215648 kb
Host smart-3546d078-3e41-4e5b-84c2-fd4006a2c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920695119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2920695119
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1048793162
Short name T727
Test name
Test status
Simulation time 416212036 ps
CPU time 4.42 seconds
Started Jul 02 09:55:41 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 217484 kb
Host smart-c64ae76a-f54f-4e20-a5fb-9fa072ccf2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048793162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1048793162
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.1028616140
Short name T400
Test name
Test status
Simulation time 48889208 ps
CPU time 1.48 seconds
Started Jul 02 09:56:46 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 218656 kb
Host smart-14be13ea-f40c-4d1e-a74a-91d9bedcab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028616140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1028616140
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3383789076
Short name T989
Test name
Test status
Simulation time 111755441 ps
CPU time 1.15 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 218876 kb
Host smart-a5cbd3d7-8393-40f1-b3bc-c9485e63f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383789076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3383789076
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.694837851
Short name T931
Test name
Test status
Simulation time 236472593 ps
CPU time 3.25 seconds
Started Jul 02 09:57:01 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 218976 kb
Host smart-b123957f-e7d3-4858-8030-ee101c7ac9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694837851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.694837851
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.133958028
Short name T80
Test name
Test status
Simulation time 144940810 ps
CPU time 1.11 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 219176 kb
Host smart-6a4df60f-e94c-43bd-9cae-810f755fe0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133958028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.133958028
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3686005484
Short name T350
Test name
Test status
Simulation time 67562993 ps
CPU time 1.18 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219192 kb
Host smart-fda12b1c-6ffc-4551-9ec8-09d3113d5402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686005484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3686005484
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1946665857
Short name T303
Test name
Test status
Simulation time 26068432 ps
CPU time 1.23 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 220592 kb
Host smart-fe093c68-9c93-4e16-9b11-1625d0ff7398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946665857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1946665857
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.534447351
Short name T360
Test name
Test status
Simulation time 44387240 ps
CPU time 1.53 seconds
Started Jul 02 09:56:46 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 220352 kb
Host smart-463cf3f6-5e21-488b-8510-f47ab21e27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534447351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.534447351
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3278247458
Short name T131
Test name
Test status
Simulation time 31244520 ps
CPU time 1.39 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 220312 kb
Host smart-2db97b56-b096-4267-a1ca-47382a82534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278247458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3278247458
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3270013501
Short name T468
Test name
Test status
Simulation time 41199719 ps
CPU time 1.29 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 218824 kb
Host smart-975c320c-ce70-4358-bd54-a8fc16b073f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270013501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3270013501
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.236162475
Short name T42
Test name
Test status
Simulation time 60078138 ps
CPU time 1.39 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218904 kb
Host smart-a83bd199-c8a7-4b87-961c-b526dce1ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236162475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.236162475
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3654230687
Short name T598
Test name
Test status
Simulation time 25162148 ps
CPU time 1.21 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 220088 kb
Host smart-d43270f4-82fd-426e-b5ee-12b8a03cbd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654230687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3654230687
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.474893670
Short name T480
Test name
Test status
Simulation time 183740749 ps
CPU time 1.85 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 219476 kb
Host smart-fc6facf3-597e-4103-a981-e0a3a4cb4289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474893670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.474893670
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1002162734
Short name T137
Test name
Test status
Simulation time 51455353 ps
CPU time 1.18 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:53 AM PDT 24
Peak memory 220708 kb
Host smart-8497456d-d9fa-4bd7-933d-3e0ea7e24dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002162734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1002162734
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1521338309
Short name T328
Test name
Test status
Simulation time 50757061 ps
CPU time 1.43 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 217552 kb
Host smart-20702814-c589-498d-8615-f4a9014e4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521338309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1521338309
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3734725899
Short name T88
Test name
Test status
Simulation time 23252395 ps
CPU time 1.15 seconds
Started Jul 02 09:56:44 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 220140 kb
Host smart-230a8198-c6c0-4d7b-ad8c-271ee992c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734725899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3734725899
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.52731114
Short name T373
Test name
Test status
Simulation time 78130784 ps
CPU time 1.49 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 217580 kb
Host smart-6185baeb-b5f9-4f01-8bb0-2bc45aa4d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52731114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.52731114
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2509577453
Short name T244
Test name
Test status
Simulation time 24148162 ps
CPU time 1.16 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 218896 kb
Host smart-5f0a5380-0a1e-41f2-a738-5113f12086d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509577453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2509577453
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.611776897
Short name T343
Test name
Test status
Simulation time 55548827 ps
CPU time 2.06 seconds
Started Jul 02 09:56:59 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 220568 kb
Host smart-a5a202e7-d2ad-4b4f-a279-33e1a572df52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611776897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.611776897
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.2033966976
Short name T421
Test name
Test status
Simulation time 16694073 ps
CPU time 0.94 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 215240 kb
Host smart-f2cee7a0-55dd-464f-9367-44785de5fc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033966976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2033966976
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.857122048
Short name T69
Test name
Test status
Simulation time 140326496 ps
CPU time 1.28 seconds
Started Jul 02 09:55:38 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 217284 kb
Host smart-3f6a5baf-41dd-4be7-8774-65bb3c88d1ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857122048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.857122048
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.150581254
Short name T168
Test name
Test status
Simulation time 20146191 ps
CPU time 1.16 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 224288 kb
Host smart-a0534278-d583-4c8d-a258-66289db56be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150581254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.150581254
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3412694680
Short name T538
Test name
Test status
Simulation time 53519010 ps
CPU time 1.4 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 217620 kb
Host smart-d8a623ff-b0ff-4ddb-8661-3207a88ca8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412694680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3412694680
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4121842767
Short name T774
Test name
Test status
Simulation time 22622608 ps
CPU time 1.05 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 215752 kb
Host smart-68a9965f-c580-47e7-a596-e4030299d81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121842767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4121842767
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4163659750
Short name T685
Test name
Test status
Simulation time 51613896 ps
CPU time 0.87 seconds
Started Jul 02 09:55:43 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 215648 kb
Host smart-92e9226f-ca4e-4990-a7ff-4927767c26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163659750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4163659750
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2994571886
Short name T397
Test name
Test status
Simulation time 196304692 ps
CPU time 1.5 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 217540 kb
Host smart-af00d7ee-72cf-4590-bdc3-e2c986ec8bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994571886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2994571886
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.475491880
Short name T653
Test name
Test status
Simulation time 227387640176 ps
CPU time 1485.46 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 10:20:23 AM PDT 24
Peak memory 226704 kb
Host smart-6cd6b86a-a11e-41b2-97ed-a87a42e11058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475491880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.475491880
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1989615318
Short name T737
Test name
Test status
Simulation time 87243299 ps
CPU time 1.16 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 219664 kb
Host smart-180828e1-836e-419d-8517-5d883e96f569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989615318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1989615318
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1050047489
Short name T503
Test name
Test status
Simulation time 43645169 ps
CPU time 1.17 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 218924 kb
Host smart-38d0f68f-5442-414d-9c3e-4ac7f7f01d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050047489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1050047489
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3026175757
Short name T879
Test name
Test status
Simulation time 31477394 ps
CPU time 1.35 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 220076 kb
Host smart-097e9e02-4e50-4d12-be54-7d42519e298c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026175757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3026175757
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2561261442
Short name T923
Test name
Test status
Simulation time 112383265 ps
CPU time 1.5 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 215668 kb
Host smart-6f39cc0c-a640-4d48-8bfa-200f144e4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561261442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2561261442
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3664929616
Short name T457
Test name
Test status
Simulation time 59611377 ps
CPU time 1.17 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 220072 kb
Host smart-e96e1490-6c4d-464c-947c-cbf865cb4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664929616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3664929616
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3662111462
Short name T732
Test name
Test status
Simulation time 50847346 ps
CPU time 1.65 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 220436 kb
Host smart-e420048b-fc42-47ae-94c5-1bbacbfc45df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662111462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3662111462
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.71189768
Short name T127
Test name
Test status
Simulation time 50839290 ps
CPU time 1.18 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 220016 kb
Host smart-0860b9e8-a97e-4bce-94bd-df3da410927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71189768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.71189768
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.330546844
Short name T971
Test name
Test status
Simulation time 72494862 ps
CPU time 2.51 seconds
Started Jul 02 09:56:50 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 220772 kb
Host smart-548085a7-78ae-4084-b9ac-5a2225c2ae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330546844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.330546844
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1978662399
Short name T786
Test name
Test status
Simulation time 36683132 ps
CPU time 1.08 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 218944 kb
Host smart-20a32756-a99e-4fab-bf2c-ecc2e5dc5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978662399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1978662399
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2362821231
Short name T463
Test name
Test status
Simulation time 75918528 ps
CPU time 1.11 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 217556 kb
Host smart-1a8fdced-0c23-44d9-a724-28a38d9bd0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362821231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2362821231
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1332908887
Short name T574
Test name
Test status
Simulation time 66443570 ps
CPU time 1.14 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 219816 kb
Host smart-66790eb7-8603-4929-908e-7b7c3204f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332908887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1332908887
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.846606070
Short name T86
Test name
Test status
Simulation time 74141030 ps
CPU time 1.16 seconds
Started Jul 02 09:56:49 AM PDT 24
Finished Jul 02 09:56:54 AM PDT 24
Peak memory 220576 kb
Host smart-eb078590-e61b-4b5d-a70c-bf22ddb83f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846606070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.846606070
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.4199323317
Short name T973
Test name
Test status
Simulation time 23704011 ps
CPU time 1.21 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 218876 kb
Host smart-9be172d5-3b86-4c19-9bf4-d07b0ece6146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199323317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.4199323317
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.3334578185
Short name T820
Test name
Test status
Simulation time 28191545 ps
CPU time 1.25 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 220836 kb
Host smart-ca426eea-8e63-40fd-b8a0-85e66a79a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334578185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3334578185
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3450982115
Short name T664
Test name
Test status
Simulation time 100509192 ps
CPU time 1.33 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 218948 kb
Host smart-e0bab5ce-2bc1-4ca7-930f-bd2a28ef15d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450982115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3450982115
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2577122087
Short name T789
Test name
Test status
Simulation time 66377619 ps
CPU time 1.14 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 221220 kb
Host smart-c51d1c08-f5e6-4976-86ab-5d3934021a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577122087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2577122087
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3352802211
Short name T759
Test name
Test status
Simulation time 62981824 ps
CPU time 1.48 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 219004 kb
Host smart-29c06605-7717-4873-aceb-7c4feab6c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352802211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3352802211
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3572045797
Short name T290
Test name
Test status
Simulation time 32731280 ps
CPU time 1.34 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 220216 kb
Host smart-8b455957-9c66-43a6-9a41-2db59ea177b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572045797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3572045797
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3003132323
Short name T812
Test name
Test status
Simulation time 158118138 ps
CPU time 0.92 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 207044 kb
Host smart-23452540-bcc0-4ef3-b31e-e487bd798d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003132323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3003132323
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2663904574
Short name T848
Test name
Test status
Simulation time 12623760 ps
CPU time 0.93 seconds
Started Jul 02 09:55:43 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 216448 kb
Host smart-d790f108-feef-4990-8bfc-b27cb2988984
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663904574 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2663904574
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3311020121
Short name T751
Test name
Test status
Simulation time 59128337 ps
CPU time 1.23 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 217432 kb
Host smart-228b28a3-614f-4dac-9ec9-ba62e9f8fac9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311020121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3311020121
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.56492666
Short name T22
Test name
Test status
Simulation time 83933975 ps
CPU time 2.13 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 220592 kb
Host smart-e21bf850-2032-476a-a0b3-5cf18b957b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56492666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.56492666
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3800364082
Short name T608
Test name
Test status
Simulation time 37830574 ps
CPU time 1 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 224304 kb
Host smart-3eb86fd9-0280-4901-a785-2f56147299bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800364082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3800364082
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2604631457
Short name T852
Test name
Test status
Simulation time 18257531 ps
CPU time 1 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 215668 kb
Host smart-0a6ae6ad-f863-4895-82ca-f77eac59e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604631457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2604631457
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1672562750
Short name T676
Test name
Test status
Simulation time 263877375 ps
CPU time 3.03 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 217412 kb
Host smart-57adbd2d-17dc-46de-80f0-2cc541c55ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672562750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1672562750
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2282678122
Short name T669
Test name
Test status
Simulation time 74527443977 ps
CPU time 519.41 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 10:04:30 AM PDT 24
Peak memory 219212 kb
Host smart-72328c92-fe4c-4872-b993-5e6ad390d2ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282678122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2282678122
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1679073410
Short name T617
Test name
Test status
Simulation time 74346839 ps
CPU time 1.15 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219812 kb
Host smart-ecba12c8-e624-4ca2-ae10-231e254b9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679073410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1679073410
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1378117541
Short name T741
Test name
Test status
Simulation time 82613445 ps
CPU time 3.15 seconds
Started Jul 02 09:56:57 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 220632 kb
Host smart-96180a95-ec05-473e-ae8c-48dcd928f69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378117541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1378117541
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3965560357
Short name T430
Test name
Test status
Simulation time 105655884 ps
CPU time 1.16 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 217636 kb
Host smart-33f1b7d5-bda0-4cbd-a587-07f0c23e7611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965560357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3965560357
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1595516999
Short name T481
Test name
Test status
Simulation time 323385119 ps
CPU time 1.23 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 218968 kb
Host smart-c2179b91-4468-4637-a321-a14f0e15ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595516999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1595516999
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3770048646
Short name T469
Test name
Test status
Simulation time 64345363 ps
CPU time 1.28 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 217512 kb
Host smart-8072e2dd-bb8a-4d78-9006-e73f6b42620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770048646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3770048646
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3008887853
Short name T936
Test name
Test status
Simulation time 53610840 ps
CPU time 1.67 seconds
Started Jul 02 09:57:08 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 218868 kb
Host smart-64cbb4b2-a650-4a77-ab0b-de9d99aa115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008887853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3008887853
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3721370536
Short name T486
Test name
Test status
Simulation time 24229779 ps
CPU time 1.17 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 218732 kb
Host smart-2990d0e3-2f6c-4e0d-a31c-6b6a3746d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721370536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3721370536
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3971222807
Short name T588
Test name
Test status
Simulation time 66217399 ps
CPU time 1.18 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 219040 kb
Host smart-9ff9b3ca-2eaa-4bd8-a09f-6987649c89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971222807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3971222807
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.938237146
Short name T926
Test name
Test status
Simulation time 193853362 ps
CPU time 1.14 seconds
Started Jul 02 09:57:08 AM PDT 24
Finished Jul 02 09:57:11 AM PDT 24
Peak memory 220072 kb
Host smart-1608d6ff-58a7-4a58-8cd2-6dee2da261a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938237146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.938237146
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1576829826
Short name T281
Test name
Test status
Simulation time 89339085 ps
CPU time 1.1 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 217604 kb
Host smart-256b05ce-a90c-443e-a50a-2824025dd319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576829826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1576829826
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.265566123
Short name T401
Test name
Test status
Simulation time 55967627 ps
CPU time 1.11 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217564 kb
Host smart-402f8b47-9c9e-480c-bda7-833726bbb56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265566123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.265566123
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3237745944
Short name T254
Test name
Test status
Simulation time 42769229 ps
CPU time 1.2 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219680 kb
Host smart-3aa7627d-ef72-46b5-a46a-8963d3925ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237745944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3237745944
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4207496576
Short name T435
Test name
Test status
Simulation time 77064297 ps
CPU time 2.71 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 219400 kb
Host smart-14ea3bf9-1a0b-42db-be03-22f99ed11980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207496576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4207496576
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1285540884
Short name T416
Test name
Test status
Simulation time 30221853 ps
CPU time 1.1 seconds
Started Jul 02 09:57:01 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 220092 kb
Host smart-0084c810-059b-4adb-9739-23fb9968b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285540884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1285540884
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.399578439
Short name T784
Test name
Test status
Simulation time 45923548 ps
CPU time 1.12 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 217476 kb
Host smart-de1f3cde-9db4-4550-87c9-8c1b7eecf0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399578439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.399578439
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.440697754
Short name T950
Test name
Test status
Simulation time 114731624 ps
CPU time 1.24 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 216044 kb
Host smart-f721d943-087d-49fd-a885-d98c4c1a677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440697754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.440697754
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.762083967
Short name T742
Test name
Test status
Simulation time 143570823 ps
CPU time 2.42 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 220548 kb
Host smart-880ea3b0-1994-421c-aa20-e0ebd048940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762083967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.762083967
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.350098770
Short name T689
Test name
Test status
Simulation time 28087667 ps
CPU time 1.1 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 221220 kb
Host smart-eff25845-aec6-4457-86ca-44a3a59e474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350098770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.350098770
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2045814364
Short name T940
Test name
Test status
Simulation time 66889818 ps
CPU time 0.89 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 207004 kb
Host smart-5d69d8c2-1dcb-4d72-92e0-18a6645f26d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045814364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2045814364
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1087315564
Short name T116
Test name
Test status
Simulation time 24882834 ps
CPU time 1.1 seconds
Started Jul 02 09:55:42 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 217180 kb
Host smart-7b9d288d-f589-4af9-8de7-04b7188d0cee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087315564 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1087315564
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.3941762476
Short name T571
Test name
Test status
Simulation time 39336309 ps
CPU time 1.19 seconds
Started Jul 02 09:55:33 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 217504 kb
Host smart-81e6d060-3925-49e6-b375-e34ac9d16ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941762476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3941762476
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1177521536
Short name T597
Test name
Test status
Simulation time 26677000 ps
CPU time 0.99 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 215840 kb
Host smart-9492cf3c-42ef-4326-9d5a-298719501c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177521536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1177521536
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.616105529
Short name T833
Test name
Test status
Simulation time 18260576 ps
CPU time 1.01 seconds
Started Jul 02 09:55:54 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 215652 kb
Host smart-ed35efa6-3264-4fb8-9b9c-b198d2e03bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616105529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.616105529
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3401173984
Short name T540
Test name
Test status
Simulation time 84599329 ps
CPU time 1.03 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 215572 kb
Host smart-da1068da-10d1-4355-a871-3116e3091901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401173984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3401173984
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.272597943
Short name T631
Test name
Test status
Simulation time 247669596088 ps
CPU time 1556.88 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 10:21:29 AM PDT 24
Peak memory 225428 kb
Host smart-d2a10b7c-f716-4144-be76-24fc04f12e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272597943 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.272597943
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4044317153
Short name T304
Test name
Test status
Simulation time 69473895 ps
CPU time 1.11 seconds
Started Jul 02 09:57:00 AM PDT 24
Finished Jul 02 09:57:04 AM PDT 24
Peak memory 219468 kb
Host smart-fb881042-be78-4671-bc7a-269617810f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044317153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4044317153
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.537090065
Short name T659
Test name
Test status
Simulation time 144261406 ps
CPU time 1.22 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 220324 kb
Host smart-514bb101-c4eb-4cd4-aa9d-0a087cfabfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537090065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.537090065
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3462564544
Short name T554
Test name
Test status
Simulation time 50657867 ps
CPU time 1.13 seconds
Started Jul 02 09:57:01 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 218900 kb
Host smart-a4528974-c8c7-439a-ba07-91eb96041a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462564544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3462564544
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.484433611
Short name T723
Test name
Test status
Simulation time 30458121 ps
CPU time 1.39 seconds
Started Jul 02 09:57:04 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 220272 kb
Host smart-f3a63556-47e4-4c34-ac9a-5c4df2ab9e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484433611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.484433611
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1469070200
Short name T667
Test name
Test status
Simulation time 26714189 ps
CPU time 1.27 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 219632 kb
Host smart-d529dd44-4a72-4acc-abd3-1c82c365db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469070200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1469070200
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1206244003
Short name T883
Test name
Test status
Simulation time 36757626 ps
CPU time 1.63 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 219020 kb
Host smart-d2a6919f-96ce-426f-99df-04b5be8031bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206244003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1206244003
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3376401825
Short name T2
Test name
Test status
Simulation time 70789662 ps
CPU time 1.08 seconds
Started Jul 02 09:56:54 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 218808 kb
Host smart-276c1f4d-c3e1-42a7-b057-06e463288b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376401825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3376401825
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2573350364
Short name T446
Test name
Test status
Simulation time 46298358 ps
CPU time 1.35 seconds
Started Jul 02 09:57:00 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 219116 kb
Host smart-64df957f-bde2-40fb-b857-c61859e5d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573350364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2573350364
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2729204900
Short name T603
Test name
Test status
Simulation time 32682053 ps
CPU time 1.02 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217668 kb
Host smart-67215a85-4905-4bb0-a0ef-ec67a63354dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729204900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2729204900
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3775769483
Short name T801
Test name
Test status
Simulation time 29532818 ps
CPU time 1.21 seconds
Started Jul 02 09:56:59 AM PDT 24
Finished Jul 02 09:57:04 AM PDT 24
Peak memory 219796 kb
Host smart-6eac3bda-8956-4ca8-a540-682188484435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775769483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3775769483
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.277306229
Short name T402
Test name
Test status
Simulation time 33064722 ps
CPU time 1.43 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 217452 kb
Host smart-00592d8d-c6fe-428e-85f1-35968592c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277306229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.277306229
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1797725568
Short name T582
Test name
Test status
Simulation time 69241871 ps
CPU time 1.17 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 220032 kb
Host smart-a675a9fd-4593-47ba-83b8-dd9c03444f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797725568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1797725568
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1681672296
Short name T949
Test name
Test status
Simulation time 161601215 ps
CPU time 2.29 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219772 kb
Host smart-19110dc6-9473-40d4-9e4e-d98d46a434ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681672296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1681672296
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3784520640
Short name T3
Test name
Test status
Simulation time 26413682 ps
CPU time 1.28 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:11 AM PDT 24
Peak memory 220828 kb
Host smart-6fcfeac9-bbfe-4770-804e-641240244158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784520640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3784520640
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1846570828
Short name T378
Test name
Test status
Simulation time 371916960 ps
CPU time 4.16 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 220332 kb
Host smart-6a5a0e77-ebd9-46bf-b3a9-63323e42e2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846570828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1846570828
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1839603814
Short name T427
Test name
Test status
Simulation time 22609417 ps
CPU time 1.14 seconds
Started Jul 02 09:57:05 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 220016 kb
Host smart-0a7e6587-c4d7-4d28-ae2e-e2a20a358f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839603814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1839603814
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2931243495
Short name T440
Test name
Test status
Simulation time 98650601 ps
CPU time 1.4 seconds
Started Jul 02 09:57:05 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 219300 kb
Host smart-163a0f9c-f5c8-4c26-a3f9-e48925c7a7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931243495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2931243495
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1696334474
Short name T386
Test name
Test status
Simulation time 28534301 ps
CPU time 1.27 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 220088 kb
Host smart-2913e55e-d362-48e2-a7e8-c65eae85dbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696334474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1696334474
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1985756586
Short name T420
Test name
Test status
Simulation time 103589356 ps
CPU time 1.28 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 218728 kb
Host smart-22805c66-8c37-475a-9c2e-8cbc0c7554b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985756586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1985756586
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.91629310
Short name T896
Test name
Test status
Simulation time 46348117 ps
CPU time 1.19 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 220208 kb
Host smart-b8b14f27-eb9c-4353-a7dd-26b11eba9cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91629310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.91629310
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.951308671
Short name T945
Test name
Test status
Simulation time 37009176 ps
CPU time 0.9 seconds
Started Jul 02 09:55:05 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 215076 kb
Host smart-d63a8c0c-b2bb-45b1-9449-b60f8348426b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951308671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.951308671
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2072786436
Short name T171
Test name
Test status
Simulation time 75734876 ps
CPU time 0.82 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 216612 kb
Host smart-3da7b583-6b7f-4719-ba36-0bd7221f2ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072786436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2072786436
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.67421264
Short name T508
Test name
Test status
Simulation time 105253963 ps
CPU time 1.2 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 219852 kb
Host smart-f14057a0-f9e6-4f37-a371-a5171639b456
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67421264 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disa
ble_auto_req_mode.67421264
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3586582990
Short name T967
Test name
Test status
Simulation time 27036756 ps
CPU time 0.94 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 218768 kb
Host smart-6373cb80-3296-4b70-af2f-34fc998fe01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586582990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3586582990
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.826750555
Short name T686
Test name
Test status
Simulation time 102741491 ps
CPU time 2.82 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:32 AM PDT 24
Peak memory 218932 kb
Host smart-adbda5da-12d6-4532-bb6b-d249459b82d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826750555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.826750555
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2936607729
Short name T874
Test name
Test status
Simulation time 15747365 ps
CPU time 0.97 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:32 AM PDT 24
Peak memory 207468 kb
Host smart-29c7e769-3702-476d-b524-092cce3274d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936607729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2936607729
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2412237919
Short name T18
Test name
Test status
Simulation time 525579795 ps
CPU time 4.22 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 236192 kb
Host smart-05110d1d-4706-4126-aa4a-b906be25a875
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412237919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2412237919
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4272788619
Short name T512
Test name
Test status
Simulation time 22032214 ps
CPU time 1.04 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 215584 kb
Host smart-2a069354-c451-4583-a404-fed0585b359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272788619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4272788619
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.387798588
Short name T845
Test name
Test status
Simulation time 271957839 ps
CPU time 4.87 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 217472 kb
Host smart-1aa275d4-90af-4586-ba23-f32467dd54ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387798588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.387798588
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1539375113
Short name T644
Test name
Test status
Simulation time 57091779106 ps
CPU time 1277.45 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 10:16:42 AM PDT 24
Peak memory 222292 kb
Host smart-c6acbcf7-fe3a-4797-a3da-e319ac851399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539375113 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1539375113
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.270394038
Short name T632
Test name
Test status
Simulation time 29312155 ps
CPU time 1.47 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 220248 kb
Host smart-4aadfb90-f804-443c-a505-0c89487ec6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270394038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.270394038
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3750039881
Short name T710
Test name
Test status
Simulation time 138020560 ps
CPU time 0.85 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 206668 kb
Host smart-0e7b2bf2-1d58-47c7-aaf0-137c5eaa8933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750039881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3750039881
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2229290642
Short name T695
Test name
Test status
Simulation time 23762013 ps
CPU time 0.89 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 216308 kb
Host smart-ecf5371b-126b-47ff-a156-5e31a6012349
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229290642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2229290642
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.204507021
Short name T147
Test name
Test status
Simulation time 151225537 ps
CPU time 0.95 seconds
Started Jul 02 09:55:36 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 220824 kb
Host smart-02ea5f30-4a9c-40cc-aaa1-05924ff8473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204507021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.204507021
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2196157884
Short name T340
Test name
Test status
Simulation time 47379071 ps
CPU time 1.75 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 220368 kb
Host smart-915588dc-b38e-4e23-b152-525bfc799d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196157884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2196157884
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.2406936125
Short name T807
Test name
Test status
Simulation time 29834071 ps
CPU time 0.94 seconds
Started Jul 02 09:55:41 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 215604 kb
Host smart-818df070-2e00-4e0f-a178-38d36ef91f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406936125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2406936125
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2238934074
Short name T722
Test name
Test status
Simulation time 316238650 ps
CPU time 3.72 seconds
Started Jul 02 09:55:44 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 217664 kb
Host smart-a2757ef1-cc3d-40de-a371-286e5612f7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238934074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2238934074
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3409082755
Short name T237
Test name
Test status
Simulation time 276896279111 ps
CPU time 1577.99 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 10:22:10 AM PDT 24
Peak memory 224240 kb
Host smart-ac5ed472-e007-43e6-92c0-dbf7c4f8aece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409082755 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3409082755
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.edn_genbits.41254042
Short name T367
Test name
Test status
Simulation time 53487979 ps
CPU time 1.25 seconds
Started Jul 02 09:57:08 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 218652 kb
Host smart-a93b981b-8052-4753-b277-1bf62de8b3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41254042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.41254042
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1157696474
Short name T314
Test name
Test status
Simulation time 82247250 ps
CPU time 1.2 seconds
Started Jul 02 09:57:05 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 219384 kb
Host smart-e2c9bbe3-452a-4e5f-9be6-daebbd5de6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157696474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1157696474
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3426097411
Short name T761
Test name
Test status
Simulation time 77971022 ps
CPU time 2.85 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 218800 kb
Host smart-1ae7746f-b4e0-4aed-84a2-237e994698ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426097411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3426097411
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.960676489
Short name T359
Test name
Test status
Simulation time 33556238 ps
CPU time 1.4 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 218700 kb
Host smart-17b5afce-a50b-4fbd-b6a0-4f955280ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960676489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.960676489
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3275932837
Short name T341
Test name
Test status
Simulation time 116075027 ps
CPU time 1.31 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219276 kb
Host smart-47943360-bd0c-44f3-b8af-29238817b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275932837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3275932837
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3955467560
Short name T827
Test name
Test status
Simulation time 73336187 ps
CPU time 1.23 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 219212 kb
Host smart-67c2d40a-b771-44d0-ad4b-fa279586244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955467560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3955467560
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1095418719
Short name T806
Test name
Test status
Simulation time 42733585 ps
CPU time 1.78 seconds
Started Jul 02 09:57:00 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 218964 kb
Host smart-c63b90a3-22df-4f6b-9153-105e75f441cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095418719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1095418719
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.410685373
Short name T40
Test name
Test status
Simulation time 57123918 ps
CPU time 2.01 seconds
Started Jul 02 09:57:08 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 220472 kb
Host smart-8b76d2f1-af4f-43a7-b288-7f1fd8b6c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410685373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.410685373
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.325772755
Short name T628
Test name
Test status
Simulation time 25454262 ps
CPU time 1.29 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 220216 kb
Host smart-007026f7-2d7b-4846-a68f-990404b764c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325772755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.325772755
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.329047775
Short name T744
Test name
Test status
Simulation time 17908381 ps
CPU time 0.82 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 207128 kb
Host smart-14870788-6e41-4cd1-881f-5faa162d7ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329047775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.329047775
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3770225119
Short name T968
Test name
Test status
Simulation time 27206913 ps
CPU time 0.83 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 216284 kb
Host smart-3c968702-dddc-4baa-8f53-13fadbf1ed9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770225119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3770225119
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.975201271
Short name T292
Test name
Test status
Simulation time 66012364 ps
CPU time 1.23 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 218664 kb
Host smart-adce9082-16ce-41de-9b5b-f225cdc9771b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975201271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.975201271
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2888325709
Short name T132
Test name
Test status
Simulation time 32978849 ps
CPU time 1.04 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 229896 kb
Host smart-4b47e225-2365-4a78-b57a-774b3e340d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888325709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2888325709
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1984275637
Short name T474
Test name
Test status
Simulation time 243412721 ps
CPU time 1.24 seconds
Started Jul 02 09:55:33 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 217664 kb
Host smart-c42eb34a-baf6-469d-8dff-c8db8bc47ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984275637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1984275637
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1144218968
Short name T109
Test name
Test status
Simulation time 22471211 ps
CPU time 1.06 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 216160 kb
Host smart-ae863f91-7312-44f1-a87b-0c2b4d91c0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144218968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1144218968
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2164148468
Short name T442
Test name
Test status
Simulation time 208538703 ps
CPU time 1 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 215620 kb
Host smart-ff56f931-8ae3-4b06-ab18-04c5d085e35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164148468 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2164148468
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2208155342
Short name T746
Test name
Test status
Simulation time 3448590141 ps
CPU time 5.55 seconds
Started Jul 02 09:55:32 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 217632 kb
Host smart-640e6b82-0cf6-483c-98af-a58e71bd7ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208155342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2208155342
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3864095698
Short name T730
Test name
Test status
Simulation time 22727776479 ps
CPU time 513.71 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 10:04:18 AM PDT 24
Peak memory 218720 kb
Host smart-e95ceb1d-8cf7-4ad3-869e-9233c224cfa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864095698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3864095698
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2351912348
Short name T436
Test name
Test status
Simulation time 88734200 ps
CPU time 2.71 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:32 AM PDT 24
Peak memory 220252 kb
Host smart-dbc4797e-71e7-41f8-a6b9-0f19003718da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351912348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2351912348
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4166772037
Short name T461
Test name
Test status
Simulation time 64944716 ps
CPU time 1.56 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 220352 kb
Host smart-3dc66b04-c66e-4b94-8b18-f48fd6bd2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166772037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4166772037
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1680541566
Short name T323
Test name
Test status
Simulation time 51504269 ps
CPU time 1.54 seconds
Started Jul 02 09:57:08 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 219140 kb
Host smart-7087567b-dcfe-4861-95f8-aca4026ec1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680541566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1680541566
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1375934998
Short name T43
Test name
Test status
Simulation time 69082333 ps
CPU time 1.15 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 220284 kb
Host smart-5e9bff00-47c9-4b53-bb29-1ab4a345bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375934998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1375934998
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1076469081
Short name T315
Test name
Test status
Simulation time 41375371 ps
CPU time 1.1 seconds
Started Jul 02 09:57:11 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 220100 kb
Host smart-20d451a3-de17-4186-868f-7e47040ad716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076469081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1076469081
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3131674204
Short name T910
Test name
Test status
Simulation time 114614890 ps
CPU time 1.37 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 219256 kb
Host smart-1c09cc89-07fd-4fb8-a164-95856c4b0d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131674204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3131674204
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2859356426
Short name T895
Test name
Test status
Simulation time 127038429 ps
CPU time 1.19 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 217832 kb
Host smart-15c97a10-56a9-420e-b756-27e1c2e4efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859356426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2859356426
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.509419150
Short name T771
Test name
Test status
Simulation time 82185513 ps
CPU time 1.25 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 219028 kb
Host smart-56cbfb49-3f15-4ae7-9b29-86f0c386e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509419150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.509419150
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1857368710
Short name T776
Test name
Test status
Simulation time 115275550 ps
CPU time 1.01 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 217616 kb
Host smart-df80546f-1cd6-468d-be1c-b53bbb3fdf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857368710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1857368710
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4293957629
Short name T889
Test name
Test status
Simulation time 64079543 ps
CPU time 1.65 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219060 kb
Host smart-1bf1492e-9a2c-43e2-a114-e79ef772eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293957629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4293957629
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3698423325
Short name T561
Test name
Test status
Simulation time 80825661 ps
CPU time 1.25 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 218916 kb
Host smart-d84653db-221a-4c8d-a7df-c3095c0f50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698423325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3698423325
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.839027089
Short name T610
Test name
Test status
Simulation time 15874986 ps
CPU time 0.91 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 215252 kb
Host smart-3e64f3e2-7bea-4628-a4f7-32400b4d2fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839027089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.839027089
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1888053305
Short name T607
Test name
Test status
Simulation time 13248040 ps
CPU time 0.89 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 216444 kb
Host smart-ce62841a-9d91-40b8-ad8a-f5bb845b25a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888053305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1888053305
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3618366483
Short name T578
Test name
Test status
Simulation time 40288692 ps
CPU time 1.28 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 217196 kb
Host smart-72a23068-c93b-405d-83dc-c05c043af52b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618366483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3618366483
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2593927906
Short name T120
Test name
Test status
Simulation time 38283404 ps
CPU time 0.93 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 219812 kb
Host smart-5035b2c7-3a48-45c7-a7d9-1e485dadd43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593927906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2593927906
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3321488390
Short name T321
Test name
Test status
Simulation time 45010539 ps
CPU time 1.4 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 218780 kb
Host smart-3942c649-cbee-4e95-859e-d0f60970547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321488390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3321488390
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3890049991
Short name T77
Test name
Test status
Simulation time 34724011 ps
CPU time 0.89 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 215772 kb
Host smart-e74acdc4-c868-4ce5-a531-6976a38fc594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890049991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3890049991
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.934565775
Short name T563
Test name
Test status
Simulation time 46767719 ps
CPU time 0.89 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 207388 kb
Host smart-6038ef09-fad6-4e26-8f0e-0f66b6eba662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934565775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.934565775
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2279014441
Short name T662
Test name
Test status
Simulation time 400741798 ps
CPU time 4.38 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 215708 kb
Host smart-f6637819-73f3-4d49-9219-bc271ce465e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279014441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2279014441
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1934079983
Short name T318
Test name
Test status
Simulation time 16188514214 ps
CPU time 374.76 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 10:01:55 AM PDT 24
Peak memory 218924 kb
Host smart-c899ead5-4c52-43ff-a23d-0afd1989399b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934079983 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1934079983
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.275336382
Short name T352
Test name
Test status
Simulation time 75148044 ps
CPU time 1.15 seconds
Started Jul 02 09:56:56 AM PDT 24
Finished Jul 02 09:57:02 AM PDT 24
Peak memory 219176 kb
Host smart-9c05322d-386d-4f47-99a1-f756b5091e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275336382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.275336382
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1330157980
Short name T369
Test name
Test status
Simulation time 118677944 ps
CPU time 1.27 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217640 kb
Host smart-b13f129d-a807-4092-941b-68e9166eb47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330157980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1330157980
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2609536393
Short name T246
Test name
Test status
Simulation time 30666099 ps
CPU time 1.38 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 217808 kb
Host smart-207d784d-1f84-4a95-b0bc-945630ca6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609536393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2609536393
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.893100879
Short name T913
Test name
Test status
Simulation time 234421170 ps
CPU time 3.29 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 219748 kb
Host smart-8848b2e4-328b-4bfb-b3d0-b6deed94eaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893100879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.893100879
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2470661455
Short name T245
Test name
Test status
Simulation time 35049022 ps
CPU time 1.32 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 215620 kb
Host smart-db6031f1-89b8-4c74-b4e2-1090ddfdbbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470661455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2470661455
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3680507516
Short name T690
Test name
Test status
Simulation time 328973077 ps
CPU time 4.1 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 218972 kb
Host smart-cec36b9c-1168-4f4a-8803-3b4b043c6562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680507516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3680507516
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2462957380
Short name T326
Test name
Test status
Simulation time 89307400 ps
CPU time 1.26 seconds
Started Jul 02 09:57:23 AM PDT 24
Finished Jul 02 09:57:31 AM PDT 24
Peak memory 217916 kb
Host smart-2d250ee6-b8c3-4684-ae8d-f5fae43b102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462957380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2462957380
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2512274979
Short name T447
Test name
Test status
Simulation time 81227313 ps
CPU time 1.53 seconds
Started Jul 02 09:57:03 AM PDT 24
Finished Jul 02 09:57:07 AM PDT 24
Peak memory 219116 kb
Host smart-64dc55f7-11a1-4daf-95cb-89dcb31477a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512274979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2512274979
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.907137330
Short name T564
Test name
Test status
Simulation time 57992393 ps
CPU time 1.38 seconds
Started Jul 02 09:57:18 AM PDT 24
Finished Jul 02 09:57:24 AM PDT 24
Peak memory 219060 kb
Host smart-2db70435-dcc6-4f36-a4ec-6b8a26a467a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907137330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.907137330
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.811362456
Short name T384
Test name
Test status
Simulation time 91997117 ps
CPU time 3.27 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 218864 kb
Host smart-86d1f04a-00c6-4ff7-86c6-608b4873d752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811362456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.811362456
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3525862400
Short name T441
Test name
Test status
Simulation time 68325351 ps
CPU time 1.16 seconds
Started Jul 02 09:55:41 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 219108 kb
Host smart-5ac4c00d-ab75-4ad0-ac30-6da71e39a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525862400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3525862400
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3064765345
Short name T587
Test name
Test status
Simulation time 21916801 ps
CPU time 0.99 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 207064 kb
Host smart-e639207a-2165-4d1a-9655-0a10356b3a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064765345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3064765345
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2957475056
Short name T122
Test name
Test status
Simulation time 39672362 ps
CPU time 1.25 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 217216 kb
Host smart-256ae2f2-4ee9-4a4d-8390-d62556484246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957475056 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2957475056
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1418553293
Short name T54
Test name
Test status
Simulation time 114233194 ps
CPU time 1.17 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 225880 kb
Host smart-883f092a-4ce7-43f3-a818-75002a219fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418553293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1418553293
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.368352552
Short name T626
Test name
Test status
Simulation time 34621915 ps
CPU time 1.36 seconds
Started Jul 02 09:55:38 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 220028 kb
Host smart-36cd1f9b-2358-4a52-b011-c7c752367116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368352552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.368352552
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2872568408
Short name T953
Test name
Test status
Simulation time 28521336 ps
CPU time 1.03 seconds
Started Jul 02 09:55:36 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 224352 kb
Host smart-471a74d2-ef8a-49c9-b235-8715d4182dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872568408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2872568408
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.331225791
Short name T584
Test name
Test status
Simulation time 17799407 ps
CPU time 0.96 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 215648 kb
Host smart-2a98d089-72d4-4782-8a6f-2e35e953703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331225791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.331225791
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2394690905
Short name T250
Test name
Test status
Simulation time 383542732 ps
CPU time 4.07 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:53 AM PDT 24
Peak memory 215708 kb
Host smart-68cc5ec1-3231-4138-808b-97add133b553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394690905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2394690905
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3443858672
Short name T668
Test name
Test status
Simulation time 151676236060 ps
CPU time 881.41 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 10:10:34 AM PDT 24
Peak memory 224088 kb
Host smart-7f4bb249-9c54-493f-a9aa-44d5cc972e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443858672 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3443858672
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.918572736
Short name T951
Test name
Test status
Simulation time 239021260 ps
CPU time 1.17 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 217576 kb
Host smart-a28fc630-0cf7-47b3-abd7-95235afb09e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918572736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.918572736
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3362892309
Short name T491
Test name
Test status
Simulation time 81106360 ps
CPU time 1.09 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 217796 kb
Host smart-00b3e0f0-c8b6-45df-b0dd-6a6bfe35020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362892309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3362892309
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.558844090
Short name T383
Test name
Test status
Simulation time 66946000 ps
CPU time 1.4 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 217748 kb
Host smart-162425ab-0c2f-4f1e-aa43-715454737bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558844090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.558844090
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3584939025
Short name T770
Test name
Test status
Simulation time 45707752 ps
CPU time 1.85 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 219032 kb
Host smart-917553e2-ad45-4348-8487-511f56c4af75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584939025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3584939025
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4175611628
Short name T819
Test name
Test status
Simulation time 285082570 ps
CPU time 3.77 seconds
Started Jul 02 09:57:19 AM PDT 24
Finished Jul 02 09:57:27 AM PDT 24
Peak memory 220352 kb
Host smart-393390aa-8b7e-48b6-a7e4-3af6b84d4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175611628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4175611628
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.846000218
Short name T381
Test name
Test status
Simulation time 152194124 ps
CPU time 1.36 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 219208 kb
Host smart-a938048e-8081-46e4-a30b-ce7314a52094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846000218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.846000218
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1811325676
Short name T625
Test name
Test status
Simulation time 49930244 ps
CPU time 1.52 seconds
Started Jul 02 09:57:31 AM PDT 24
Finished Jul 02 09:57:34 AM PDT 24
Peak memory 219156 kb
Host smart-34f2c265-e63d-4016-9b3f-70fa9f2d36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811325676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1811325676
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3006364756
Short name T196
Test name
Test status
Simulation time 23272060 ps
CPU time 1.2 seconds
Started Jul 02 09:57:23 AM PDT 24
Finished Jul 02 09:57:27 AM PDT 24
Peak memory 218896 kb
Host smart-9d55312a-fe97-48b4-8522-907069717f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006364756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3006364756
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.159715461
Short name T46
Test name
Test status
Simulation time 53030622 ps
CPU time 1.65 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 218764 kb
Host smart-1e07e9cc-a388-49f6-8815-33682ede629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159715461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.159715461
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1203435177
Short name T546
Test name
Test status
Simulation time 38251720 ps
CPU time 1.61 seconds
Started Jul 02 09:57:22 AM PDT 24
Finished Jul 02 09:57:27 AM PDT 24
Peak memory 220452 kb
Host smart-ecaf4c61-ccd0-4443-bf74-33a1a6faa827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203435177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1203435177
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3517967732
Short name T126
Test name
Test status
Simulation time 50902805 ps
CPU time 1.23 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 219056 kb
Host smart-22efc5fc-f53d-48a2-9953-f2cfae5eca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517967732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3517967732
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.725556620
Short name T70
Test name
Test status
Simulation time 52229841 ps
CPU time 0.78 seconds
Started Jul 02 09:55:59 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 206684 kb
Host smart-4f04495a-50e5-4652-8f0e-27b76988309d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725556620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.725556620
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1809363794
Short name T613
Test name
Test status
Simulation time 12831465 ps
CPU time 0.92 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 216508 kb
Host smart-7b9ae31e-fa9f-42fc-ae4e-713ef2ad0d89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809363794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1809363794
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1957998057
Short name T567
Test name
Test status
Simulation time 84364590 ps
CPU time 1.12 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 09:56:05 AM PDT 24
Peak memory 217272 kb
Host smart-7ca53a5d-5084-48f7-afb7-8eb32e78bc32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957998057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1957998057
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.378580554
Short name T595
Test name
Test status
Simulation time 34263738 ps
CPU time 0.91 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 219120 kb
Host smart-6dfbc22d-3600-4c85-9527-2a20ff0344f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378580554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.378580554
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3206695758
Short name T499
Test name
Test status
Simulation time 93380843 ps
CPU time 1.27 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 219096 kb
Host smart-7ad94cc8-ccb1-4b6d-a5fc-58557ba86f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206695758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3206695758
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3209965204
Short name T782
Test name
Test status
Simulation time 22502743 ps
CPU time 1.19 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 224444 kb
Host smart-2e3f58f1-78d8-42d9-8814-26a06546e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209965204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3209965204
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1365626038
Short name T921
Test name
Test status
Simulation time 16280475 ps
CPU time 0.97 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 215644 kb
Host smart-48740776-0a3c-481e-b383-dbdc25cdae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365626038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1365626038
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3690320080
Short name T252
Test name
Test status
Simulation time 409626613 ps
CPU time 3.19 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 218824 kb
Host smart-2ef1043e-a0f0-49e0-b69a-6323bdebbbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690320080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3690320080
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2686495028
Short name T236
Test name
Test status
Simulation time 249927886817 ps
CPU time 1498.88 seconds
Started Jul 02 09:55:47 AM PDT 24
Finished Jul 02 10:20:47 AM PDT 24
Peak memory 224268 kb
Host smart-5129a2e0-5bdd-42b1-883a-1c94c676e9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686495028 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2686495028
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2163562324
Short name T391
Test name
Test status
Simulation time 129741253 ps
CPU time 1.17 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 217804 kb
Host smart-3a65e4bf-4b42-4485-97f1-a9817650caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163562324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2163562324
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.825928346
Short name T621
Test name
Test status
Simulation time 38365186 ps
CPU time 1.32 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:15 AM PDT 24
Peak memory 217644 kb
Host smart-3e1bc585-d7f5-4169-b2cc-9ab3c0f13035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825928346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.825928346
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2448443736
Short name T55
Test name
Test status
Simulation time 136958692 ps
CPU time 1.23 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 219164 kb
Host smart-211b780f-07cb-4ed8-b424-7a207a5c9730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448443736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2448443736
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1065743970
Short name T364
Test name
Test status
Simulation time 55670553 ps
CPU time 1.2 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 217684 kb
Host smart-c61115d7-e82e-4940-a801-dc5d473ef99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065743970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1065743970
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2455045894
Short name T439
Test name
Test status
Simulation time 33988254 ps
CPU time 1.4 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 218828 kb
Host smart-b83598f7-dcea-47fc-9994-ae9d14358333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455045894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2455045894
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3933185336
Short name T530
Test name
Test status
Simulation time 26561085 ps
CPU time 1.18 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 220124 kb
Host smart-6b9310e9-50ca-460a-9c6d-7a878eebae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933185336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3933185336
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1122368188
Short name T453
Test name
Test status
Simulation time 93019090 ps
CPU time 1.55 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 219720 kb
Host smart-ee6037d8-6227-4f04-ab9b-c0a1e8c817e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122368188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1122368188
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1524868231
Short name T347
Test name
Test status
Simulation time 126111396 ps
CPU time 1.03 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217784 kb
Host smart-0db638ab-6f6b-4f6f-99f9-d8bb18f57c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524868231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1524868231
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3600498012
Short name T836
Test name
Test status
Simulation time 90072382 ps
CPU time 1.2 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 215664 kb
Host smart-efbc03f1-010a-4fad-b910-61b2bb99e8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600498012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3600498012
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3149035706
Short name T996
Test name
Test status
Simulation time 59069163 ps
CPU time 2.37 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 219828 kb
Host smart-ef21a31c-ee46-418a-af02-5cec15d60078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149035706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3149035706
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.381187674
Short name T282
Test name
Test status
Simulation time 151047240 ps
CPU time 1.24 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 218912 kb
Host smart-e8c553f5-abcc-4b75-bd41-cdabf3c8b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381187674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.381187674
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3577876641
Short name T965
Test name
Test status
Simulation time 65145478 ps
CPU time 0.81 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 206860 kb
Host smart-5cd4d0c6-317f-407b-a616-b7cf8a345fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577876641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3577876641
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1014745541
Short name T209
Test name
Test status
Simulation time 43980384 ps
CPU time 0.87 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:55:57 AM PDT 24
Peak memory 216600 kb
Host smart-20785b94-cc55-416b-a54d-69e67054163b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014745541 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1014745541
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4266769862
Short name T591
Test name
Test status
Simulation time 81351952 ps
CPU time 1.08 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 217212 kb
Host smart-f5e48a6b-12b5-4131-9efb-1582c247beaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266769862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4266769862
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1000475641
Short name T6
Test name
Test status
Simulation time 25710470 ps
CPU time 1.14 seconds
Started Jul 02 09:55:40 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 220196 kb
Host smart-b0c6b5df-9912-45fb-802e-3a6b077c4635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000475641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1000475641
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1671010767
Short name T82
Test name
Test status
Simulation time 40796453 ps
CPU time 1.23 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 217840 kb
Host smart-97b9474e-0f48-4154-9c8d-ee7d8304a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671010767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1671010767
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2099441529
Short name T888
Test name
Test status
Simulation time 25636237 ps
CPU time 0.95 seconds
Started Jul 02 09:55:47 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 216108 kb
Host smart-6486b696-4865-43f7-9515-0d4fc2ff83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099441529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2099441529
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1310232929
Short name T618
Test name
Test status
Simulation time 23591299 ps
CPU time 0.97 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 215660 kb
Host smart-e002520d-8fe7-41d2-a347-6ffba578002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310232929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1310232929
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2148276312
Short name T418
Test name
Test status
Simulation time 249703818 ps
CPU time 4.85 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:56:02 AM PDT 24
Peak memory 215568 kb
Host smart-4fc8c010-5af0-4cdd-8226-7a6ae1ac74eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148276312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2148276312
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2205094991
Short name T423
Test name
Test status
Simulation time 36890572738 ps
CPU time 461.18 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 10:03:26 AM PDT 24
Peak memory 218360 kb
Host smart-dbe8f4ad-0657-48ca-a594-83f7141a35d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205094991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2205094991
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.830071363
Short name T824
Test name
Test status
Simulation time 317453777 ps
CPU time 1.27 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 217672 kb
Host smart-b6cfaa20-de57-4118-a089-10b399f77259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830071363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.830071363
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1648414418
Short name T956
Test name
Test status
Simulation time 50255653 ps
CPU time 1.63 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 217528 kb
Host smart-e9712883-6d0d-4d2a-b2cd-aae216546ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648414418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1648414418
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3617571249
Short name T633
Test name
Test status
Simulation time 114111055 ps
CPU time 1.17 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 217504 kb
Host smart-43e6a42d-8a09-4c33-9ecb-ddc1335238b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617571249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3617571249
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1646793535
Short name T64
Test name
Test status
Simulation time 70151539 ps
CPU time 1.1 seconds
Started Jul 02 09:57:11 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 217480 kb
Host smart-4c41d770-8325-4055-a421-9387e932251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646793535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1646793535
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2736494675
Short name T551
Test name
Test status
Simulation time 66356112 ps
CPU time 1.4 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 218992 kb
Host smart-53168741-4db9-4df3-9ad7-d90efd20ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736494675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2736494675
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3447407918
Short name T517
Test name
Test status
Simulation time 76546912 ps
CPU time 2.61 seconds
Started Jul 02 09:57:23 AM PDT 24
Finished Jul 02 09:57:28 AM PDT 24
Peak memory 220204 kb
Host smart-a4e592f2-7e51-4999-b68d-fcd41c86f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447407918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3447407918
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3417381963
Short name T509
Test name
Test status
Simulation time 30671701 ps
CPU time 1.29 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 220372 kb
Host smart-039db29a-fac5-4352-aa60-9cbae845ef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417381963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3417381963
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3102715345
Short name T654
Test name
Test status
Simulation time 45434535 ps
CPU time 1.82 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 218992 kb
Host smart-dd777295-0b1a-4e4c-b7d7-631e66749c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102715345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3102715345
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1027217045
Short name T975
Test name
Test status
Simulation time 50120433 ps
CPU time 1.18 seconds
Started Jul 02 09:57:27 AM PDT 24
Finished Jul 02 09:57:29 AM PDT 24
Peak memory 217500 kb
Host smart-27354e44-a219-4b1c-a3ef-160a33596965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027217045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1027217045
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3861007014
Short name T445
Test name
Test status
Simulation time 58138490 ps
CPU time 1.23 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 217528 kb
Host smart-0117dd2e-8e8a-474a-b275-20095bb74bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861007014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3861007014
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3244520920
Short name T604
Test name
Test status
Simulation time 24834294 ps
CPU time 1.26 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 221220 kb
Host smart-bc8253f1-4abc-4312-8839-9ef4fba8c2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244520920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3244520920
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.843329335
Short name T67
Test name
Test status
Simulation time 38727019 ps
CPU time 0.86 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 207068 kb
Host smart-9f9b8263-dbfd-45b5-85e6-cfe9b3f7c9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843329335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.843329335
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2020506880
Short name T434
Test name
Test status
Simulation time 11504629 ps
CPU time 0.87 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 216564 kb
Host smart-59649fcb-435f-4696-a0bd-65aacbc16069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020506880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2020506880
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2412900220
Short name T986
Test name
Test status
Simulation time 61709387 ps
CPU time 1.01 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:53 AM PDT 24
Peak memory 218744 kb
Host smart-4a83dd92-66d6-497b-99e3-6d2155cea37e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412900220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2412900220
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1296222625
Short name T881
Test name
Test status
Simulation time 43031189 ps
CPU time 0.94 seconds
Started Jul 02 09:55:44 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 218888 kb
Host smart-716bdeee-ad03-44c1-bb9a-bb1898d0c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296222625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1296222625
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3125136208
Short name T929
Test name
Test status
Simulation time 27843755 ps
CPU time 1.19 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 220368 kb
Host smart-e1443e50-eda6-44ea-b7aa-2335ac965288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125136208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3125136208
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.2242109899
Short name T792
Test name
Test status
Simulation time 20159861 ps
CPU time 0.9 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 215696 kb
Host smart-0753565d-cb3c-42a9-a9d0-897aa2f6f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242109899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2242109899
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3726629305
Short name T98
Test name
Test status
Simulation time 323772944 ps
CPU time 4.74 seconds
Started Jul 02 09:55:40 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 217588 kb
Host smart-4ac0d9a7-44f8-4f50-be49-2f984f3e7bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726629305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3726629305
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2205450831
Short name T521
Test name
Test status
Simulation time 130630768885 ps
CPU time 1710.4 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 10:24:35 AM PDT 24
Peak memory 228084 kb
Host smart-fdfd82fc-1169-4e6f-883d-ff2381d8bf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205450831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2205450831
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3008741891
Short name T548
Test name
Test status
Simulation time 28776558 ps
CPU time 1.28 seconds
Started Jul 02 09:57:11 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 217640 kb
Host smart-6d5928b3-8078-47a3-9a5e-b709a318bfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008741891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3008741891
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2353679440
Short name T448
Test name
Test status
Simulation time 36751244 ps
CPU time 1.67 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:24 AM PDT 24
Peak memory 217900 kb
Host smart-76059a28-eba4-44ec-936d-f825df45e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353679440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2353679440
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1362482844
Short name T760
Test name
Test status
Simulation time 257477603 ps
CPU time 3.93 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 220544 kb
Host smart-237fdad3-b6ef-4b50-9e2e-34de1e82a65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362482844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1362482844
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2749877501
Short name T897
Test name
Test status
Simulation time 39816840 ps
CPU time 1.39 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 218808 kb
Host smart-15522246-0fea-422b-a56d-e7efced6a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749877501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2749877501
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1150063142
Short name T721
Test name
Test status
Simulation time 36048822 ps
CPU time 1.38 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 220384 kb
Host smart-3e3e5f4c-303c-46dc-b37d-3255a33ca977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150063142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1150063142
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1220417739
Short name T885
Test name
Test status
Simulation time 112197341 ps
CPU time 1.05 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 217668 kb
Host smart-a923810f-035c-4175-b148-1bf75332341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220417739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1220417739
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1522961587
Short name T376
Test name
Test status
Simulation time 36113637 ps
CPU time 1.27 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 219012 kb
Host smart-09a79fa7-b6a8-4599-8b9f-d4fb4cd2357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522961587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1522961587
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4037496952
Short name T356
Test name
Test status
Simulation time 79443485 ps
CPU time 1.42 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 217512 kb
Host smart-ae523b7f-f24a-43f2-9a5b-6efeecd5f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037496952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4037496952
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2631051084
Short name T830
Test name
Test status
Simulation time 44770276 ps
CPU time 1.24 seconds
Started Jul 02 09:57:05 AM PDT 24
Finished Jul 02 09:57:08 AM PDT 24
Peak memory 220120 kb
Host smart-a908e997-db20-400c-bd87-8ab4f2672f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631051084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2631051084
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1649498878
Short name T915
Test name
Test status
Simulation time 84218092 ps
CPU time 1.07 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 215656 kb
Host smart-df0695f1-49a2-4b59-bcbf-0a3fd635a488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649498878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1649498878
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4215775420
Short name T665
Test name
Test status
Simulation time 56973176 ps
CPU time 1.26 seconds
Started Jul 02 09:55:42 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 219968 kb
Host smart-d9b0cadc-19ba-463d-bfe3-3e4bb847d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215775420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4215775420
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1442706750
Short name T524
Test name
Test status
Simulation time 27674955 ps
CPU time 0.92 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 215432 kb
Host smart-5ada1b80-b9e0-4110-8196-1b3eb6a19c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442706750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1442706750
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.623503430
Short name T158
Test name
Test status
Simulation time 43069395 ps
CPU time 0.91 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 09:55:51 AM PDT 24
Peak memory 215748 kb
Host smart-b8a73d70-0f11-4cc0-abdb-2deb64faf65e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623503430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.623503430
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1411731386
Short name T955
Test name
Test status
Simulation time 24832489 ps
CPU time 1.1 seconds
Started Jul 02 09:55:46 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 217356 kb
Host smart-b97b183c-e87b-4ee2-82d4-8dbe69cd7b80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411731386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1411731386
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.887984507
Short name T76
Test name
Test status
Simulation time 19953922 ps
CPU time 1.06 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 218772 kb
Host smart-7815f0e1-9638-49b0-8aa9-6ab2bea15324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887984507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.887984507
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2614325426
Short name T974
Test name
Test status
Simulation time 54325437 ps
CPU time 2.06 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 219116 kb
Host smart-e48d13d7-f09c-41d4-8609-a3032cb22910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614325426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2614325426
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2901074018
Short name T871
Test name
Test status
Simulation time 22826164 ps
CPU time 1.09 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 215756 kb
Host smart-66d90d9a-38cb-4297-b580-5e27721869af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901074018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2901074018
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.987223969
Short name T520
Test name
Test status
Simulation time 45542853 ps
CPU time 0.9 seconds
Started Jul 02 09:55:59 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 215648 kb
Host smart-6e7230df-7ba6-41f1-8eba-ddacbcb086b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987223969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.987223969
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1033912238
Short name T709
Test name
Test status
Simulation time 111013217 ps
CPU time 2.58 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 218840 kb
Host smart-a9730abf-ecbb-4f58-9ab1-eefeaec00ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033912238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1033912238
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3262687716
Short name T539
Test name
Test status
Simulation time 140291800968 ps
CPU time 2007.96 seconds
Started Jul 02 09:56:00 AM PDT 24
Finished Jul 02 10:29:29 AM PDT 24
Peak memory 230416 kb
Host smart-96e29776-33c5-4571-a6a5-f9e3d79f4306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262687716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3262687716
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2295705889
Short name T374
Test name
Test status
Simulation time 29703938 ps
CPU time 1.43 seconds
Started Jul 02 09:57:22 AM PDT 24
Finished Jul 02 09:57:27 AM PDT 24
Peak memory 218704 kb
Host smart-9dcc0a45-27dd-4bee-bb99-88b40c78320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295705889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2295705889
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3519134576
Short name T337
Test name
Test status
Simulation time 68033642 ps
CPU time 1.61 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:19 AM PDT 24
Peak memory 220632 kb
Host smart-23d1b99a-b50b-4d0d-8f3b-eb1516d6d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519134576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3519134576
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.316221877
Short name T371
Test name
Test status
Simulation time 163184337 ps
CPU time 0.99 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217652 kb
Host smart-49cee0da-30cc-45f0-9efb-8ad790d524f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316221877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.316221877
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2091409616
Short name T627
Test name
Test status
Simulation time 59453278 ps
CPU time 1.21 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 217480 kb
Host smart-b90f3a25-bef8-4d5a-9988-f15146c727e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091409616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2091409616
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2349098835
Short name T743
Test name
Test status
Simulation time 25801425 ps
CPU time 1.11 seconds
Started Jul 02 09:57:32 AM PDT 24
Finished Jul 02 09:57:34 AM PDT 24
Peak memory 217564 kb
Host smart-63848bf7-3917-43a7-a002-0d07abff1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349098835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2349098835
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1396753319
Short name T995
Test name
Test status
Simulation time 89417731 ps
CPU time 1.06 seconds
Started Jul 02 09:57:06 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 217712 kb
Host smart-9a3859f5-9288-4322-be9f-d7a8e9619447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396753319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1396753319
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.274810502
Short name T726
Test name
Test status
Simulation time 46762141 ps
CPU time 1.25 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 217648 kb
Host smart-1596e2fb-db4b-449d-a898-5887fb49103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274810502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.274810502
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2986039151
Short name T606
Test name
Test status
Simulation time 62965097 ps
CPU time 0.99 seconds
Started Jul 02 09:57:21 AM PDT 24
Finished Jul 02 09:57:25 AM PDT 24
Peak memory 217564 kb
Host smart-221844b6-f902-43ec-9da6-f2def9c6675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986039151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2986039151
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.301563735
Short name T755
Test name
Test status
Simulation time 38781566 ps
CPU time 1.16 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 217716 kb
Host smart-a871ba80-72ac-47e0-a2bb-7ea6eb0b563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301563735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.301563735
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3392029557
Short name T467
Test name
Test status
Simulation time 71972251 ps
CPU time 1.2 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 217992 kb
Host smart-d2d4f835-add5-4aac-8a3d-bc6455a78e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392029557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3392029557
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2168930371
Short name T961
Test name
Test status
Simulation time 88776186 ps
CPU time 1.26 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 220188 kb
Host smart-2c66af44-40c8-46df-ae83-ccd9af295518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168930371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2168930371
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.28270557
Short name T718
Test name
Test status
Simulation time 51154142 ps
CPU time 1.01 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 215296 kb
Host smart-8ca9d440-1229-408a-9721-fe862d679bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.28270557
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1722988244
Short name T178
Test name
Test status
Simulation time 54081131 ps
CPU time 0.87 seconds
Started Jul 02 09:55:58 AM PDT 24
Finished Jul 02 09:56:00 AM PDT 24
Peak memory 216672 kb
Host smart-2ec919f6-3895-4276-95b5-acfb30a61934
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722988244 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1722988244
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.632462832
Short name T795
Test name
Test status
Simulation time 20979935 ps
CPU time 1.15 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 220128 kb
Host smart-b6f718dd-a665-43cb-afea-f2676f9df7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632462832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.632462832
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1054205438
Short name T354
Test name
Test status
Simulation time 26722967 ps
CPU time 1.29 seconds
Started Jul 02 09:55:45 AM PDT 24
Finished Jul 02 09:55:49 AM PDT 24
Peak memory 218936 kb
Host smart-02c1687e-e98d-444f-8fd2-1f2ca3ab231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054205438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1054205438
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2457452646
Short name T92
Test name
Test status
Simulation time 27186749 ps
CPU time 0.93 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 216116 kb
Host smart-2b48269f-9365-4e15-96c3-8d92e10f07ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457452646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2457452646
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1243145514
Short name T952
Test name
Test status
Simulation time 22318336 ps
CPU time 0.93 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 215652 kb
Host smart-9abedd0e-13e2-4e6e-9f4a-059307d6a0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243145514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1243145514
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2048651123
Short name T680
Test name
Test status
Simulation time 146438907 ps
CPU time 3.21 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 215644 kb
Host smart-09ddc7b8-ec9e-46c5-b4b0-d1844c3e0b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048651123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2048651123
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2352924223
Short name T239
Test name
Test status
Simulation time 72191134635 ps
CPU time 1589.13 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 10:22:26 AM PDT 24
Peak memory 224224 kb
Host smart-bda18013-3f34-411e-b947-06e93ebd4ac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352924223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2352924223
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1568195180
Short name T868
Test name
Test status
Simulation time 34111517 ps
CPU time 1.28 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 218852 kb
Host smart-477a5f72-ce3d-46cc-b888-c4ebf6b2df3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568195180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1568195180
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2250764895
Short name T775
Test name
Test status
Simulation time 71883485 ps
CPU time 0.94 seconds
Started Jul 02 09:57:15 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 217604 kb
Host smart-9d0198c4-e326-4b5f-bf93-00780adb6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250764895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2250764895
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.824188725
Short name T803
Test name
Test status
Simulation time 37253243 ps
CPU time 1.36 seconds
Started Jul 02 09:57:10 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 218672 kb
Host smart-4758f2fe-6145-4804-a3c5-304cca14bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824188725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.824188725
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2447151186
Short name T528
Test name
Test status
Simulation time 48202916 ps
CPU time 1.35 seconds
Started Jul 02 09:57:33 AM PDT 24
Finished Jul 02 09:57:36 AM PDT 24
Peak memory 218964 kb
Host smart-5d337331-92e0-4ca1-a55e-ac51fffd41c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447151186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2447151186
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1124414546
Short name T805
Test name
Test status
Simulation time 137044941 ps
CPU time 1.28 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 220184 kb
Host smart-1dc7bb23-246e-4d0f-9679-cf35a578a473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124414546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1124414546
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.380353407
Short name T847
Test name
Test status
Simulation time 96146682 ps
CPU time 1.27 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 217672 kb
Host smart-4637356f-40af-4539-aa11-b02e60c84867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380353407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.380353407
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.386778922
Short name T334
Test name
Test status
Simulation time 42881925 ps
CPU time 1.79 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:11 AM PDT 24
Peak memory 218888 kb
Host smart-6f72347a-249c-42c7-b44e-457782588e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386778922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.386778922
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1777086528
Short name T433
Test name
Test status
Simulation time 43742640 ps
CPU time 1.15 seconds
Started Jul 02 09:57:11 AM PDT 24
Finished Jul 02 09:57:14 AM PDT 24
Peak memory 217644 kb
Host smart-9407efd0-f453-4522-a445-9bb9af24000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777086528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1777086528
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3970153559
Short name T388
Test name
Test status
Simulation time 40957333 ps
CPU time 1.39 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:57:59 AM PDT 24
Peak memory 219108 kb
Host smart-548c4d47-d162-4265-8796-9f1912bc413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970153559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3970153559
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1238090294
Short name T322
Test name
Test status
Simulation time 50771342 ps
CPU time 1.55 seconds
Started Jul 02 09:57:14 AM PDT 24
Finished Jul 02 09:57:20 AM PDT 24
Peak memory 220344 kb
Host smart-626b0b3c-6987-4717-9983-575a2950aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238090294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1238090294
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1264350337
Short name T946
Test name
Test status
Simulation time 46190206 ps
CPU time 1.16 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 219524 kb
Host smart-89264e26-9a0b-4ead-ae30-6cc609a25a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264350337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1264350337
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2368675318
Short name T533
Test name
Test status
Simulation time 30833380 ps
CPU time 0.96 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 215476 kb
Host smart-e970e6ba-7fdc-41c7-83fc-1e68258bac8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368675318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2368675318
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3575016161
Short name T186
Test name
Test status
Simulation time 37914654 ps
CPU time 0.83 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 216588 kb
Host smart-25b90b8c-85d6-414a-9e32-1e64d2f65495
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575016161 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3575016161
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3084468290
Short name T150
Test name
Test status
Simulation time 185880566 ps
CPU time 1.17 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 217352 kb
Host smart-3416e311-dded-4e8b-9e16-6f0d1bf51b03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084468290 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3084468290
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3113705272
Short name T194
Test name
Test status
Simulation time 21438666 ps
CPU time 1.02 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 219760 kb
Host smart-77bfb227-7cd1-4d00-b8ed-b644c9ea6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113705272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3113705272
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1538156309
Short name T332
Test name
Test status
Simulation time 183487711 ps
CPU time 2.39 seconds
Started Jul 02 09:55:59 AM PDT 24
Finished Jul 02 09:56:02 AM PDT 24
Peak memory 220132 kb
Host smart-8f0a5ec0-3695-405d-bbbf-5321b3fc1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538156309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1538156309
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.930950939
Short name T677
Test name
Test status
Simulation time 26343355 ps
CPU time 0.96 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 215876 kb
Host smart-99474b5d-238f-43b3-8825-88b9a030a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930950939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.930950939
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.321475684
Short name T312
Test name
Test status
Simulation time 19569569 ps
CPU time 1.02 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 215604 kb
Host smart-726b6691-8569-448e-80a6-7ca84c5d3daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321475684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.321475684
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2882292396
Short name T694
Test name
Test status
Simulation time 169320538 ps
CPU time 2.35 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:21 AM PDT 24
Peak memory 217456 kb
Host smart-f22610c0-bf68-49bc-a7b6-1505a10e2d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882292396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2882292396
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.344430588
Short name T555
Test name
Test status
Simulation time 98718970760 ps
CPU time 1168.95 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 10:15:21 AM PDT 24
Peak memory 224116 kb
Host smart-77318fad-7e05-4582-8e7a-f318ee67430f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344430588 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.344430588
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3772543959
Short name T407
Test name
Test status
Simulation time 33067242 ps
CPU time 1.34 seconds
Started Jul 02 09:57:23 AM PDT 24
Finished Jul 02 09:57:27 AM PDT 24
Peak memory 218768 kb
Host smart-c82b1a4f-2391-4561-9906-6447a2bdc846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772543959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3772543959
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1278933958
Short name T616
Test name
Test status
Simulation time 40485728 ps
CPU time 1.37 seconds
Started Jul 02 09:57:21 AM PDT 24
Finished Jul 02 09:57:26 AM PDT 24
Peak memory 220064 kb
Host smart-c971c501-c3c4-47a3-bc09-ab130e9bd3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278933958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1278933958
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3909550188
Short name T355
Test name
Test status
Simulation time 41694643 ps
CPU time 1.85 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 218768 kb
Host smart-ca2e071d-2ec5-4970-a6cf-0a0849133eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909550188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3909550188
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.120667684
Short name T395
Test name
Test status
Simulation time 52923182 ps
CPU time 1.39 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 218856 kb
Host smart-67cf9ea5-a461-456f-8fff-888480970cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120667684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.120667684
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3198883115
Short name T828
Test name
Test status
Simulation time 68149548 ps
CPU time 1.01 seconds
Started Jul 02 09:57:16 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 217808 kb
Host smart-25284f6d-0907-472a-bfc0-66f003e452a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198883115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3198883115
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1288809459
Short name T797
Test name
Test status
Simulation time 159006391 ps
CPU time 1.46 seconds
Started Jul 02 09:57:13 AM PDT 24
Finished Jul 02 09:57:17 AM PDT 24
Peak memory 218028 kb
Host smart-8b7f25c1-ccbb-468f-8dfe-e24665598e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288809459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1288809459
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1428473261
Short name T738
Test name
Test status
Simulation time 31298832 ps
CPU time 1.28 seconds
Started Jul 02 09:57:18 AM PDT 24
Finished Jul 02 09:57:23 AM PDT 24
Peak memory 217552 kb
Host smart-93ab8022-f9f8-408f-a300-a9d6e7161905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428473261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1428473261
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1659141245
Short name T930
Test name
Test status
Simulation time 41776339 ps
CPU time 1.72 seconds
Started Jul 02 09:57:20 AM PDT 24
Finished Jul 02 09:57:25 AM PDT 24
Peak memory 218984 kb
Host smart-7da4420e-e222-4f7d-87f0-71a29bc7817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659141245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1659141245
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2636589356
Short name T48
Test name
Test status
Simulation time 97404758 ps
CPU time 1.23 seconds
Started Jul 02 09:57:12 AM PDT 24
Finished Jul 02 09:57:15 AM PDT 24
Peak memory 217688 kb
Host smart-fd19d2c4-39d9-48ab-8262-3e71b73ef286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636589356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2636589356
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3159671238
Short name T102
Test name
Test status
Simulation time 37985178 ps
CPU time 1.18 seconds
Started Jul 02 09:55:37 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 219152 kb
Host smart-180cc335-dd10-446b-b24c-b7778c5689ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159671238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3159671238
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1984541565
Short name T358
Test name
Test status
Simulation time 21468967 ps
CPU time 1.02 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 207192 kb
Host smart-b0c73b23-c37f-4941-800e-a6dffdb25562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984541565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1984541565
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2562135026
Short name T969
Test name
Test status
Simulation time 28244800 ps
CPU time 0.85 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 215716 kb
Host smart-e7232df7-4aec-40d1-99fc-df1f1ae2c898
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562135026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2562135026
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2277272862
Short name T501
Test name
Test status
Simulation time 49204063 ps
CPU time 1.05 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 217248 kb
Host smart-cea93aa0-7d48-445e-bd7d-ea6ff87178bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277272862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2277272862
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2102473946
Short name T208
Test name
Test status
Simulation time 21102204 ps
CPU time 0.92 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 219956 kb
Host smart-6519c6ed-7e95-4cfb-8805-b3c1b96fffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102473946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2102473946
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1836531217
Short name T357
Test name
Test status
Simulation time 68426000 ps
CPU time 1.34 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:32 AM PDT 24
Peak memory 217572 kb
Host smart-d56bd187-9471-490c-a045-b6bede952eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836531217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1836531217
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1035112675
Short name T748
Test name
Test status
Simulation time 22219641 ps
CPU time 0.93 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 216184 kb
Host smart-fee31d23-54ae-42c9-905f-34b5b103b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035112675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1035112675
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.62085612
Short name T692
Test name
Test status
Simulation time 109371742 ps
CPU time 0.87 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 207344 kb
Host smart-c431643f-bebb-403b-a1de-920b94364b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62085612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.62085612
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1160392435
Short name T389
Test name
Test status
Simulation time 32272650 ps
CPU time 0.93 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 215548 kb
Host smart-e47929c4-c041-497e-8ac9-c8b3f244c330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160392435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1160392435
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.306182599
Short name T924
Test name
Test status
Simulation time 747193909 ps
CPU time 2.72 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 217460 kb
Host smart-bdfb2917-0c51-4c22-863d-9347979f730f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306182599 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.306182599
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2808517923
Short name T580
Test name
Test status
Simulation time 146376762370 ps
CPU time 1840.54 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 10:26:17 AM PDT 24
Peak memory 229068 kb
Host smart-921cc683-e5af-4b7f-9926-1471296c59e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808517923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2808517923
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1624285324
Short name T702
Test name
Test status
Simulation time 104013610 ps
CPU time 1.24 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:55:57 AM PDT 24
Peak memory 216004 kb
Host smart-e37a6452-dc2c-44d0-935e-af3c31538304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624285324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1624285324
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2073005945
Short name T650
Test name
Test status
Simulation time 32871426 ps
CPU time 1.06 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 206996 kb
Host smart-5a5adac9-506a-4df6-8560-6b6b59309c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073005945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2073005945
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2641265140
Short name T403
Test name
Test status
Simulation time 11638359 ps
CPU time 0.86 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 216380 kb
Host smart-258b56f6-6d73-462d-b333-1149f277b8b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641265140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2641265140
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1631206548
Short name T992
Test name
Test status
Simulation time 105241409 ps
CPU time 1.11 seconds
Started Jul 02 09:55:42 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 218948 kb
Host smart-f4676161-041a-4cb8-b575-1a4e10492713
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631206548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1631206548
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.572143805
Short name T128
Test name
Test status
Simulation time 20708095 ps
CPU time 1.21 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 229848 kb
Host smart-caff3b34-1d6c-4174-ab9f-1e31969c5cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572143805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.572143805
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.620461533
Short name T700
Test name
Test status
Simulation time 48387779 ps
CPU time 1.45 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:53 AM PDT 24
Peak memory 215596 kb
Host smart-c88c513a-1b20-433e-94c5-84a23e41b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620461533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.620461533
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3492272265
Short name T599
Test name
Test status
Simulation time 22042709 ps
CPU time 1.07 seconds
Started Jul 02 09:55:49 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 215812 kb
Host smart-848e9cc2-145e-4279-8807-90dcce0851a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492272265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3492272265
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4015739549
Short name T966
Test name
Test status
Simulation time 27109619 ps
CPU time 0.91 seconds
Started Jul 02 09:56:00 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 215668 kb
Host smart-87dc2045-0a1d-4ee8-b7e0-52d5caf5f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015739549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4015739549
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.105830473
Short name T243
Test name
Test status
Simulation time 322705236 ps
CPU time 3.29 seconds
Started Jul 02 09:55:50 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 215636 kb
Host smart-2288391d-d287-4e00-8299-d2dc23e1f31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105830473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.105830473
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1993554679
Short name T655
Test name
Test status
Simulation time 64791610259 ps
CPU time 1615.9 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 10:22:51 AM PDT 24
Peak memory 226772 kb
Host smart-d7b3f738-b139-41d1-9d67-e3bd77d34cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993554679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1993554679
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2297592009
Short name T559
Test name
Test status
Simulation time 165719904 ps
CPU time 1.27 seconds
Started Jul 02 09:56:05 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 220024 kb
Host smart-46059d0c-7f0a-4d1b-890e-043b3a201452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297592009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2297592009
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2904897185
Short name T649
Test name
Test status
Simulation time 19211536 ps
CPU time 1.01 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:55:57 AM PDT 24
Peak memory 215156 kb
Host smart-d5b0bc4e-f924-46ca-87d8-fe3af644a71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904897185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2904897185
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2912498707
Short name T205
Test name
Test status
Simulation time 153641816 ps
CPU time 1.18 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 217300 kb
Host smart-58020f5b-28d6-488e-8b7b-bc16cbbdddab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912498707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2912498707
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4226727636
Short name T715
Test name
Test status
Simulation time 28418082 ps
CPU time 0.94 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 218936 kb
Host smart-d5195ed1-d29c-41b7-8143-55d882ba3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226727636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4226727636
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2244957535
Short name T65
Test name
Test status
Simulation time 51726422 ps
CPU time 1.18 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 219324 kb
Host smart-5f313125-15fa-43af-92e4-f6cf6bea7797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244957535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2244957535
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3547064985
Short name T840
Test name
Test status
Simulation time 20761957 ps
CPU time 1.15 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 216084 kb
Host smart-239b40b3-b32d-4c5a-9cef-228e7cec13db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547064985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3547064985
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1156315190
Short name T804
Test name
Test status
Simulation time 16324017 ps
CPU time 1 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 215628 kb
Host smart-f3165f09-d53a-48bf-b29b-5d22bb745a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156315190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1156315190
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3515441443
Short name T50
Test name
Test status
Simulation time 987595457 ps
CPU time 2.6 seconds
Started Jul 02 09:56:05 AM PDT 24
Finished Jul 02 09:56:09 AM PDT 24
Peak memory 217504 kb
Host smart-6caead2a-22e2-4c55-8b1d-eca6920c4514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515441443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3515441443
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.451802251
Short name T234
Test name
Test status
Simulation time 49947752607 ps
CPU time 1173.24 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 10:15:58 AM PDT 24
Peak memory 220764 kb
Host smart-f28ab9a5-ee7c-45cc-8249-b5d9f754a12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451802251 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.451802251
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1245620495
Short name T224
Test name
Test status
Simulation time 53652651 ps
CPU time 1.18 seconds
Started Jul 02 09:56:05 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 219256 kb
Host smart-4b2aa06c-001a-4a54-ab0d-6afdf9c749d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245620495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1245620495
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.567732592
Short name T49
Test name
Test status
Simulation time 14182958 ps
CPU time 0.93 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 215216 kb
Host smart-358b349f-f3bf-405b-9495-9ba10fc32a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567732592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.567732592
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.566544788
Short name T550
Test name
Test status
Simulation time 22929160 ps
CPU time 0.85 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 216516 kb
Host smart-2449f369-74f2-42ea-b18f-2de481ce313c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566544788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.566544788
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.363593890
Short name T144
Test name
Test status
Simulation time 22485044 ps
CPU time 1.05 seconds
Started Jul 02 09:56:15 AM PDT 24
Finished Jul 02 09:56:17 AM PDT 24
Peak memory 217276 kb
Host smart-fc9f3fea-31bf-46ca-923a-1248c30a83e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363593890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.363593890
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4071513874
Short name T783
Test name
Test status
Simulation time 27109479 ps
CPU time 1.01 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 09:56:05 AM PDT 24
Peak memory 224080 kb
Host smart-1918a99b-1016-44cf-94d0-6a34c67e2518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071513874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4071513874
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4163610666
Short name T641
Test name
Test status
Simulation time 76753349 ps
CPU time 1.65 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 219224 kb
Host smart-6f14fe1e-0d56-4fdc-a7ff-ecdbfee2d67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163610666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4163610666
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1323294799
Short name T790
Test name
Test status
Simulation time 51465814 ps
CPU time 1.01 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 224168 kb
Host smart-ca13b071-ad1d-465b-9f0b-f1883ec29aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323294799 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1323294799
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2589663152
Short name T884
Test name
Test status
Simulation time 23994582 ps
CPU time 1.02 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 215564 kb
Host smart-b160f0c4-7032-45a3-ab89-674a28caecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589663152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2589663152
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1391687081
Short name T817
Test name
Test status
Simulation time 160892418 ps
CPU time 3.72 seconds
Started Jul 02 09:55:55 AM PDT 24
Finished Jul 02 09:56:00 AM PDT 24
Peak memory 215688 kb
Host smart-27b58d37-4a3b-46de-aed3-198e5c3c6d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391687081 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1391687081
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3308351271
Short name T713
Test name
Test status
Simulation time 94436889668 ps
CPU time 335.71 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 10:01:40 AM PDT 24
Peak memory 219016 kb
Host smart-c1dd4704-9e2d-47df-8c17-71a9287d4433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308351271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3308351271
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.568978609
Short name T576
Test name
Test status
Simulation time 26142993 ps
CPU time 1.27 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 219028 kb
Host smart-aedf9beb-9e95-492c-ad5b-f7849961dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568978609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.568978609
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1679056315
Short name T353
Test name
Test status
Simulation time 17370850 ps
CPU time 0.98 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 207052 kb
Host smart-ba04c89b-a806-4aa2-aa01-255a402bfbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679056315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1679056315
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.865356628
Short name T177
Test name
Test status
Simulation time 21553927 ps
CPU time 0.85 seconds
Started Jul 02 09:56:10 AM PDT 24
Finished Jul 02 09:56:11 AM PDT 24
Peak memory 216556 kb
Host smart-2f19b8bf-f2e7-49e5-80ac-0ff1bc002d87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865356628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.865356628
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4219558750
Short name T283
Test name
Test status
Simulation time 114813898 ps
CPU time 1.03 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 218628 kb
Host smart-d5a9b690-4713-4e5e-98dc-f2936df52ce2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219558750 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4219558750
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3166208356
Short name T16
Test name
Test status
Simulation time 23233373 ps
CPU time 1.01 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 224224 kb
Host smart-7e312872-c732-487b-8efa-0d425594820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166208356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3166208356
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2206575367
Short name T351
Test name
Test status
Simulation time 41632378 ps
CPU time 1.57 seconds
Started Jul 02 09:55:54 AM PDT 24
Finished Jul 02 09:55:57 AM PDT 24
Peak memory 218784 kb
Host smart-7aa543f7-e6e7-424f-aa9d-7438e7138fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206575367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2206575367
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.879299259
Short name T36
Test name
Test status
Simulation time 28043007 ps
CPU time 0.82 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 215924 kb
Host smart-b9d4a6fa-60ba-4d26-99f7-6d1017f22a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879299259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.879299259
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4113640570
Short name T754
Test name
Test status
Simulation time 25958393 ps
CPU time 0.96 seconds
Started Jul 02 09:55:48 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 215600 kb
Host smart-c2e86779-c8e7-4b9d-b02a-02008db19306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113640570 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4113640570
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2844016752
Short name T766
Test name
Test status
Simulation time 137020799 ps
CPU time 2.89 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:57 AM PDT 24
Peak memory 215592 kb
Host smart-043015e4-b028-4d04-983d-fb2ae91a5b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844016752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2844016752
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.78969915
Short name T733
Test name
Test status
Simulation time 65093722816 ps
CPU time 363.04 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 10:02:01 AM PDT 24
Peak memory 224064 kb
Host smart-75906264-d296-40cf-9e3c-a3f98cfb9192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78969915 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.78969915
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2726433082
Short name T482
Test name
Test status
Simulation time 26906396 ps
CPU time 1.22 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 218940 kb
Host smart-10c35c5d-8fb9-4896-962d-c924c3f63fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726433082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2726433082
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3228865535
Short name T515
Test name
Test status
Simulation time 15753537 ps
CPU time 0.97 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 207048 kb
Host smart-ca46ab86-dafe-485a-aee5-b5223c2886e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228865535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3228865535
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2112620299
Short name T793
Test name
Test status
Simulation time 132010989 ps
CPU time 0.86 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 216292 kb
Host smart-6de3d53b-e44c-4c31-abfb-b3cfef27be93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112620299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2112620299
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1120518183
Short name T134
Test name
Test status
Simulation time 95090402 ps
CPU time 1.1 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 219824 kb
Host smart-658af12c-4e09-403a-a71f-1cf4545c17c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120518183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1120518183
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.378998427
Short name T526
Test name
Test status
Simulation time 22266363 ps
CPU time 1.02 seconds
Started Jul 02 09:56:06 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 224232 kb
Host smart-9516d80b-9151-46f0-8d26-2fc662b55adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378998427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.378998427
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3613078208
Short name T891
Test name
Test status
Simulation time 98489117 ps
CPU time 1.99 seconds
Started Jul 02 09:56:07 AM PDT 24
Finished Jul 02 09:56:10 AM PDT 24
Peak memory 219068 kb
Host smart-559dc676-48cc-48b2-b86d-a90e608b99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613078208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3613078208
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.825864080
Short name T479
Test name
Test status
Simulation time 35775578 ps
CPU time 0.89 seconds
Started Jul 02 09:55:57 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 215920 kb
Host smart-80d5c75d-b92b-4853-86ce-e422526cbaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825864080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.825864080
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1568947960
Short name T583
Test name
Test status
Simulation time 18631413 ps
CPU time 1.11 seconds
Started Jul 02 09:55:44 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 215552 kb
Host smart-775c64a0-dc73-4dc1-9fb8-7294e562a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568947960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1568947960
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2760970996
Short name T477
Test name
Test status
Simulation time 425106454 ps
CPU time 2.25 seconds
Started Jul 02 09:56:11 AM PDT 24
Finished Jul 02 09:56:13 AM PDT 24
Peak memory 215612 kb
Host smart-cc706fcf-bda1-4166-bece-aad07ca4a0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760970996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2760970996
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.311689815
Short name T235
Test name
Test status
Simulation time 156774322495 ps
CPU time 1736.61 seconds
Started Jul 02 09:56:10 AM PDT 24
Finished Jul 02 10:25:07 AM PDT 24
Peak memory 233580 kb
Host smart-bc43dac0-b98c-44d6-ac41-64aa37fe4e0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311689815 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.311689815
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3131766334
Short name T306
Test name
Test status
Simulation time 80463928 ps
CPU time 1.24 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 219772 kb
Host smart-84604ab0-f44f-4e89-b7c0-84ce916d3e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131766334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3131766334
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3134374135
Short name T451
Test name
Test status
Simulation time 22534543 ps
CPU time 1.06 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 207036 kb
Host smart-34f76dca-4747-41da-9981-fbd3b340cfcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134374135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3134374135
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2077564849
Short name T758
Test name
Test status
Simulation time 37337217 ps
CPU time 0.87 seconds
Started Jul 02 09:56:12 AM PDT 24
Finished Jul 02 09:56:14 AM PDT 24
Peak memory 216600 kb
Host smart-49687559-b742-4ae0-b136-6b3dbe69441c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077564849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2077564849
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2403264536
Short name T753
Test name
Test status
Simulation time 23917567 ps
CPU time 1.07 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 220116 kb
Host smart-c9079e94-5cda-4701-85d0-d3a7b868cc8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403264536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2403264536
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.127484107
Short name T113
Test name
Test status
Simulation time 47656052 ps
CPU time 1.17 seconds
Started Jul 02 09:55:51 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 230016 kb
Host smart-3ecaa555-08d4-434e-8fd9-1ab21eff8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127484107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.127484107
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_intr.4136914276
Short name T839
Test name
Test status
Simulation time 23735068 ps
CPU time 1.11 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 09:56:15 AM PDT 24
Peak memory 215792 kb
Host smart-948f7fe5-1fc5-47cc-a38b-d66ae0475987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136914276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4136914276
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.578358760
Short name T846
Test name
Test status
Simulation time 46407400 ps
CPU time 0.96 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 215576 kb
Host smart-3a2dbf53-6328-43b8-bd74-c068a5fed57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578358760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.578358760
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1091233827
Short name T716
Test name
Test status
Simulation time 246815016 ps
CPU time 2.3 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:29 AM PDT 24
Peak memory 217772 kb
Host smart-7b718301-3924-46b2-83b3-2314efa2b4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091233827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1091233827
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.670664915
Short name T643
Test name
Test status
Simulation time 122247763374 ps
CPU time 1424.28 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 10:19:48 AM PDT 24
Peak memory 224560 kb
Host smart-fb99abd7-7d36-4659-b19f-6a695106be12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670664915 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.670664915
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4109189033
Short name T108
Test name
Test status
Simulation time 71780325 ps
CPU time 1.17 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 220064 kb
Host smart-8a9c9dfd-1570-4218-a6fc-df83e11c68cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109189033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4109189033
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.214540080
Short name T592
Test name
Test status
Simulation time 41130358 ps
CPU time 0.87 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:58 AM PDT 24
Peak memory 207008 kb
Host smart-7ae34291-cdb1-489a-bdec-8e2455f61fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214540080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.214540080
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1387096415
Short name T412
Test name
Test status
Simulation time 19937229 ps
CPU time 0.88 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:56:16 AM PDT 24
Peak memory 216264 kb
Host smart-4f33e4b6-cd94-43c0-832f-62280dac07c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387096415 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1387096415
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4078050089
Short name T763
Test name
Test status
Simulation time 33253682 ps
CPU time 1.18 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 217336 kb
Host smart-8d13f2e8-ac2a-4c19-9134-39512986beca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078050089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4078050089
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4176716025
Short name T203
Test name
Test status
Simulation time 22043237 ps
CPU time 1.12 seconds
Started Jul 02 09:55:52 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 220380 kb
Host smart-14a66ec4-bffc-4891-bec0-5c43d3709fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176716025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4176716025
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1950284031
Short name T311
Test name
Test status
Simulation time 34321739 ps
CPU time 1.27 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 09:56:15 AM PDT 24
Peak memory 218884 kb
Host smart-54ffa9d3-cfd8-45a1-a9ea-598fca9c4a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950284031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1950284031
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3480782413
Short name T413
Test name
Test status
Simulation time 42276993 ps
CPU time 1.04 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 224360 kb
Host smart-28b8efd2-2e92-4344-bbfa-4e50bd29dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480782413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3480782413
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4080198689
Short name T962
Test name
Test status
Simulation time 18341049 ps
CPU time 0.98 seconds
Started Jul 02 09:56:00 AM PDT 24
Finished Jul 02 09:56:02 AM PDT 24
Peak memory 215652 kb
Host smart-ce675646-77a1-42a9-bfd1-84425f749426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080198689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4080198689
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3428960903
Short name T66
Test name
Test status
Simulation time 264535188 ps
CPU time 2.31 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 215660 kb
Host smart-fe96cda4-11b2-4266-b44e-ba5181ded384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428960903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3428960903
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4005912069
Short name T231
Test name
Test status
Simulation time 18654891641 ps
CPU time 437.77 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 10:03:38 AM PDT 24
Peak memory 223960 kb
Host smart-05c2d54b-41c7-4a86-8c3b-39a20e208ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005912069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4005912069
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1073964155
Short name T307
Test name
Test status
Simulation time 23665874 ps
CPU time 1.18 seconds
Started Jul 02 09:56:09 AM PDT 24
Finished Jul 02 09:56:11 AM PDT 24
Peak memory 221200 kb
Host smart-d5f29383-67a6-4c1c-8b1c-05e2678861c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073964155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1073964155
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.6307031
Short name T698
Test name
Test status
Simulation time 15232672 ps
CPU time 0.87 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:21 AM PDT 24
Peak memory 207004 kb
Host smart-b8f7ab19-2f72-41d4-82c0-4c524bbd82df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6307031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.6307031
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_genbits.3222018352
Short name T454
Test name
Test status
Simulation time 24024493 ps
CPU time 1.15 seconds
Started Jul 02 09:56:08 AM PDT 24
Finished Jul 02 09:56:09 AM PDT 24
Peak memory 220184 kb
Host smart-7b80747d-909b-4915-9ac3-e1e591ecd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222018352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3222018352
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2629605424
Short name T34
Test name
Test status
Simulation time 21783263 ps
CPU time 1.14 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 216132 kb
Host smart-2710731c-7d35-41ea-8dfa-fd31c48b8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629605424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2629605424
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2677870053
Short name T516
Test name
Test status
Simulation time 22301375 ps
CPU time 0.92 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:56:16 AM PDT 24
Peak memory 215624 kb
Host smart-3f3f17f4-268a-4b8f-aed0-211174d3be57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677870053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2677870053
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2599245050
Short name T96
Test name
Test status
Simulation time 2549878902 ps
CPU time 3.4 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 217972 kb
Host smart-f8868527-e64f-4908-8d52-4bf5d327d0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599245050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2599245050
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1764822598
Short name T317
Test name
Test status
Simulation time 38226222717 ps
CPU time 991.9 seconds
Started Jul 02 09:56:05 AM PDT 24
Finished Jul 02 10:12:39 AM PDT 24
Peak memory 221084 kb
Host smart-0dd525bb-b11a-4de0-94c4-8e31062bf01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764822598 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1764822598
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1987467393
Short name T107
Test name
Test status
Simulation time 196730063 ps
CPU time 1.28 seconds
Started Jul 02 09:55:58 AM PDT 24
Finished Jul 02 09:56:00 AM PDT 24
Peak memory 218900 kb
Host smart-3bbe8eb2-cda0-430c-896c-f5575704db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987467393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1987467393
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3266939772
Short name T560
Test name
Test status
Simulation time 21527884 ps
CPU time 0.84 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 206852 kb
Host smart-596c63ad-ddb7-4bb0-9dd5-a2dcfb100a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266939772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3266939772
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.50250072
Short name T164
Test name
Test status
Simulation time 14250743 ps
CPU time 0.96 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 09:56:15 AM PDT 24
Peak memory 216716 kb
Host smart-69f71f16-4117-4df9-9abb-372327310a63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50250072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.50250072
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4293701208
Short name T212
Test name
Test status
Simulation time 69692141 ps
CPU time 1.16 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 217428 kb
Host smart-d0f7b421-4e37-4d2c-9084-1e092286cd6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293701208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4293701208
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3803546950
Short name T651
Test name
Test status
Simulation time 35249702 ps
CPU time 1.12 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:56:16 AM PDT 24
Peak memory 221028 kb
Host smart-358333fa-7258-43c2-aa08-174d97e58239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803546950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3803546950
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3634440024
Short name T11
Test name
Test status
Simulation time 92167584 ps
CPU time 1.2 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 218932 kb
Host smart-e2791cb1-378a-462a-abe6-1b97b9fb0ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634440024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3634440024
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2087147878
Short name T471
Test name
Test status
Simulation time 59840077 ps
CPU time 0.88 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 215684 kb
Host smart-d98cb7aa-402f-4d94-a029-f42432f3cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087147878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2087147878
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.537867556
Short name T938
Test name
Test status
Simulation time 44336488 ps
CPU time 0.96 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:22 AM PDT 24
Peak memory 215640 kb
Host smart-9f6a4321-7735-4b6f-94bc-b199bf835ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537867556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.537867556
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.499974635
Short name T849
Test name
Test status
Simulation time 618082049 ps
CPU time 4.08 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:09 AM PDT 24
Peak memory 217808 kb
Host smart-5bf66e73-ada7-4b10-a59d-59bf7fab8d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499974635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.499974635
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2423649568
Short name T229
Test name
Test status
Simulation time 64477194203 ps
CPU time 365.24 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 10:02:28 AM PDT 24
Peak memory 219420 kb
Host smart-9a2d2e61-85de-4038-bde2-de64dfc97c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423649568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2423649568
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.901357766
Short name T483
Test name
Test status
Simulation time 41186913 ps
CPU time 1.21 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 219460 kb
Host smart-c4a6d30b-59da-4240-9444-51f862c0a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901357766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.901357766
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.483477870
Short name T865
Test name
Test status
Simulation time 34130232 ps
CPU time 0.8 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 207112 kb
Host smart-d5048e4d-61f9-47a6-8176-e45ccda078c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483477870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.483477870
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2997190423
Short name T705
Test name
Test status
Simulation time 12797407 ps
CPU time 0.94 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 216404 kb
Host smart-5e9212b6-e8c4-46e5-9ef5-f7b540553401
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997190423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2997190423
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.746155945
Short name T382
Test name
Test status
Simulation time 49161343 ps
CPU time 0.95 seconds
Started Jul 02 09:55:58 AM PDT 24
Finished Jul 02 09:56:00 AM PDT 24
Peak memory 218900 kb
Host smart-ba90ab3a-8aa5-4811-abaf-018ad65244ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746155945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.746155945
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1253503240
Short name T942
Test name
Test status
Simulation time 23674675 ps
CPU time 1.22 seconds
Started Jul 02 09:55:53 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 224292 kb
Host smart-504dc55a-7c31-4396-a9c2-6149e9fc86a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253503240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1253503240
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2221561117
Short name T91
Test name
Test status
Simulation time 149783015 ps
CPU time 2.41 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 220508 kb
Host smart-24bdafbc-5997-4bee-801e-10ebfe935f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221561117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2221561117
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3155840972
Short name T933
Test name
Test status
Simulation time 21847554 ps
CPU time 1.15 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 215728 kb
Host smart-597c661d-a99e-469d-ba53-249eaebdc1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155840972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3155840972
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3709282085
Short name T103
Test name
Test status
Simulation time 18104055 ps
CPU time 1.01 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 215632 kb
Host smart-0f51df5a-38fe-4949-a884-4ddb0efc847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709282085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3709282085
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1856074037
Short name T476
Test name
Test status
Simulation time 614239885 ps
CPU time 6.31 seconds
Started Jul 02 09:55:56 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 218992 kb
Host smart-5e8c1308-e002-43aa-83c5-e3509fe16aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856074037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1856074037
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1037632504
Short name T425
Test name
Test status
Simulation time 129345560623 ps
CPU time 765.35 seconds
Started Jul 02 09:56:15 AM PDT 24
Finished Jul 02 10:09:02 AM PDT 24
Peak memory 224036 kb
Host smart-1124006a-58a6-4053-bfc5-a014d025f12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037632504 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1037632504
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4252810972
Short name T160
Test name
Test status
Simulation time 47417884 ps
CPU time 1.22 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 219172 kb
Host smart-ec0aa007-da01-4ac9-8739-d04904998f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252810972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4252810972
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2038548143
Short name T380
Test name
Test status
Simulation time 67441163 ps
CPU time 0.81 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 206316 kb
Host smart-7d6ec7c2-a441-4775-929a-9e1414f4312f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038548143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2038548143
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.72757287
Short name T920
Test name
Test status
Simulation time 13593351 ps
CPU time 0.92 seconds
Started Jul 02 09:55:39 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 216712 kb
Host smart-0a3bd6e8-2cb5-41d9-aae2-45b4af7e58d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72757287 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.72757287
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.3512401065
Short name T693
Test name
Test status
Simulation time 141860525 ps
CPU time 1.17 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 225924 kb
Host smart-f696575a-d1fb-41da-a716-b6c58b7836d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512401065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3512401065
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2895474474
Short name T522
Test name
Test status
Simulation time 44960841 ps
CPU time 1.14 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 217568 kb
Host smart-dedbb8a5-0ba4-4f60-b332-e338562641a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895474474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2895474474
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.3333755771
Short name T958
Test name
Test status
Simulation time 61773089 ps
CPU time 0.96 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:29 AM PDT 24
Peak memory 207376 kb
Host smart-6c922ee6-9e9f-460e-9cdc-843a546d661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333755771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3333755771
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3159133805
Short name T843
Test name
Test status
Simulation time 43855018 ps
CPU time 0.91 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 215640 kb
Host smart-70934f85-8353-4d8c-a924-425d931461af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159133805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3159133805
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2835671883
Short name T794
Test name
Test status
Simulation time 106027706 ps
CPU time 1.32 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 217360 kb
Host smart-aade6095-84a8-4fe1-9033-6536337c5ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835671883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2835671883
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4070563800
Short name T233
Test name
Test status
Simulation time 112625007603 ps
CPU time 1046.89 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 10:13:08 AM PDT 24
Peak memory 224596 kb
Host smart-760a0dec-9bb4-44ac-a971-898257684f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070563800 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4070563800
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2742307361
Short name T60
Test name
Test status
Simulation time 30545765 ps
CPU time 1.3 seconds
Started Jul 02 09:56:07 AM PDT 24
Finished Jul 02 09:56:09 AM PDT 24
Peak memory 220848 kb
Host smart-67fbaf01-058f-4a10-9fed-118a0011a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742307361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2742307361
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2397340129
Short name T399
Test name
Test status
Simulation time 110525899 ps
CPU time 0.86 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:21 AM PDT 24
Peak memory 215020 kb
Host smart-66cfaff8-60cf-47f3-8e1d-dbbfa3e1aff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397340129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2397340129
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3014151001
Short name T218
Test name
Test status
Simulation time 56621771 ps
CPU time 1.2 seconds
Started Jul 02 09:56:12 AM PDT 24
Finished Jul 02 09:56:14 AM PDT 24
Peak memory 217264 kb
Host smart-f3cce31e-5a2a-426e-a441-7115ea1c0628
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014151001 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3014151001
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3156616622
Short name T636
Test name
Test status
Simulation time 46226071 ps
CPU time 0.94 seconds
Started Jul 02 09:55:59 AM PDT 24
Finished Jul 02 09:56:01 AM PDT 24
Peak memory 219960 kb
Host smart-df0e2070-e0bd-49b9-afbb-3e55c46e4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156616622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3156616622
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3923290803
Short name T565
Test name
Test status
Simulation time 74487411 ps
CPU time 1.13 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 217748 kb
Host smart-2b59f024-f59e-4a83-81b2-444f61f4d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923290803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3923290803
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4103591146
Short name T35
Test name
Test status
Simulation time 25360324 ps
CPU time 0.93 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 216212 kb
Host smart-370ab931-6bcd-46af-9b42-a173fc5bf14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103591146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4103591146
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.494309445
Short name T398
Test name
Test status
Simulation time 14588197 ps
CPU time 0.98 seconds
Started Jul 02 09:56:08 AM PDT 24
Finished Jul 02 09:56:10 AM PDT 24
Peak memory 215584 kb
Host smart-538fa478-d8ab-460e-a5b9-18768b7971d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494309445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.494309445
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.625620865
Short name T623
Test name
Test status
Simulation time 63952670 ps
CPU time 1.71 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 218568 kb
Host smart-96bcd488-a36a-40f3-9d03-a2bd13cf916c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625620865 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.625620865
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3848833914
Short name T240
Test name
Test status
Simulation time 343463541835 ps
CPU time 2035.13 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 10:30:13 AM PDT 24
Peak memory 226456 kb
Host smart-950c2685-c41c-49e4-8aa6-a44abaec64c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848833914 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3848833914
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3457261563
Short name T165
Test name
Test status
Simulation time 137755523 ps
CPU time 1.18 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:56:16 AM PDT 24
Peak memory 218900 kb
Host smart-8bc52403-f1b2-40b1-b4f9-85ac0f01ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457261563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3457261563
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3200677338
Short name T593
Test name
Test status
Simulation time 14429642 ps
CPU time 0.92 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:06 AM PDT 24
Peak memory 215192 kb
Host smart-b934bd76-98c7-48e6-996f-cae9f00587d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200677338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3200677338
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1457700115
Short name T919
Test name
Test status
Simulation time 9949774 ps
CPU time 0.85 seconds
Started Jul 02 09:56:25 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 216640 kb
Host smart-0af58fcb-e0ff-4b71-a295-7d8f4810aefa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457700115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1457700115
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2953984695
Short name T23
Test name
Test status
Simulation time 35639309 ps
CPU time 1.27 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 217140 kb
Host smart-9534cf18-829d-4568-98ed-40df1628bb70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953984695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2953984695
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1039339799
Short name T115
Test name
Test status
Simulation time 87230885 ps
CPU time 1 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 220928 kb
Host smart-602b8e10-94bc-4ab8-961f-0eb5bffa99d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039339799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1039339799
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2325535159
Short name T875
Test name
Test status
Simulation time 59153371 ps
CPU time 1.23 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 217928 kb
Host smart-a701a872-2a9b-43e5-8f8e-4648468e7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325535159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2325535159
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2173071265
Short name T32
Test name
Test status
Simulation time 23545369 ps
CPU time 1.17 seconds
Started Jul 02 09:56:02 AM PDT 24
Finished Jul 02 09:56:04 AM PDT 24
Peak memory 216088 kb
Host smart-1ab79da9-e813-4f98-ba3a-937dec4f4d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173071265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2173071265
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2856787055
Short name T791
Test name
Test status
Simulation time 15327584 ps
CPU time 1 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 215632 kb
Host smart-eebf356a-2870-43a6-a024-38cf78320fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856787055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2856787055
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1493115337
Short name T251
Test name
Test status
Simulation time 2038709024 ps
CPU time 4.43 seconds
Started Jul 02 09:56:06 AM PDT 24
Finished Jul 02 09:56:11 AM PDT 24
Peak memory 217532 kb
Host smart-6a2c9f6d-49c3-4bc8-b2ba-e3045cf498c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493115337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1493115337
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2639801008
Short name T492
Test name
Test status
Simulation time 219604555772 ps
CPU time 1268.75 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 10:17:36 AM PDT 24
Peak memory 223924 kb
Host smart-572c71a8-c8f6-48bc-b230-b7d68d599aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639801008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2639801008
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2830360623
Short name T464
Test name
Test status
Simulation time 53951686 ps
CPU time 1.27 seconds
Started Jul 02 09:56:04 AM PDT 24
Finished Jul 02 09:56:07 AM PDT 24
Peak memory 219520 kb
Host smart-bba4b95c-1f17-4d5e-90e4-13a5ee8e104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830360623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2830360623
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1208505934
Short name T811
Test name
Test status
Simulation time 40759308 ps
CPU time 0.94 seconds
Started Jul 02 09:56:15 AM PDT 24
Finished Jul 02 09:56:17 AM PDT 24
Peak memory 207024 kb
Host smart-b1122b78-9769-4e3a-8408-52e76e4ca239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208505934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1208505934
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1897563939
Short name T943
Test name
Test status
Simulation time 20650206 ps
CPU time 0.86 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 216252 kb
Host smart-0c5d1743-3402-4d15-b1ab-131983f31776
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897563939 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1897563939
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.992150846
Short name T922
Test name
Test status
Simulation time 20392042 ps
CPU time 0.98 seconds
Started Jul 02 09:56:27 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 218592 kb
Host smart-0b567684-eb45-4823-8b64-70eb8aa713fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992150846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.992150846
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3939473961
Short name T640
Test name
Test status
Simulation time 42774627 ps
CPU time 1.07 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:18 AM PDT 24
Peak memory 219900 kb
Host smart-dda697c3-0822-46c2-b0cc-61496988a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939473961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3939473961
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3614751150
Short name T714
Test name
Test status
Simulation time 2556541099 ps
CPU time 66.04 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:57:21 AM PDT 24
Peak memory 215776 kb
Host smart-3e85d461-e0cb-4839-9c68-3778d2339798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614751150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3614751150
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.107204875
Short name T94
Test name
Test status
Simulation time 20183810 ps
CPU time 1.17 seconds
Started Jul 02 09:56:08 AM PDT 24
Finished Jul 02 09:56:10 AM PDT 24
Peak memory 216284 kb
Host smart-d88ff163-4b40-4d16-8ea4-af2d4573bdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107204875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.107204875
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2577024492
Short name T470
Test name
Test status
Simulation time 29557132 ps
CPU time 0.98 seconds
Started Jul 02 09:56:12 AM PDT 24
Finished Jul 02 09:56:13 AM PDT 24
Peak memory 215612 kb
Host smart-71d8f154-277d-418d-b362-4b9a5568ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577024492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2577024492
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4280886162
Short name T200
Test name
Test status
Simulation time 688671407 ps
CPU time 4.03 seconds
Started Jul 02 09:56:26 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 220560 kb
Host smart-7a6e1e2f-57ab-4f5d-a763-eaccaa2307c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280886162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4280886162
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1815098583
Short name T39
Test name
Test status
Simulation time 34623438312 ps
CPU time 773.66 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 10:09:12 AM PDT 24
Peak memory 219476 kb
Host smart-98b3c4a3-afb7-47ef-84ad-06ca21e8e3ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815098583 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1815098583
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.469893225
Short name T802
Test name
Test status
Simulation time 23449139 ps
CPU time 1.15 seconds
Started Jul 02 09:56:03 AM PDT 24
Finished Jul 02 09:56:05 AM PDT 24
Peak memory 220344 kb
Host smart-1acc5f5e-21c0-45da-89ee-d2d8db78b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469893225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.469893225
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3284022909
Short name T678
Test name
Test status
Simulation time 136278372 ps
CPU time 0.82 seconds
Started Jul 02 09:56:12 AM PDT 24
Finished Jul 02 09:56:13 AM PDT 24
Peak memory 207104 kb
Host smart-8186338b-a032-4c8f-8cdc-6a82d9fef7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284022909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3284022909
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2881646140
Short name T934
Test name
Test status
Simulation time 11777055 ps
CPU time 0.85 seconds
Started Jul 02 09:56:07 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 216504 kb
Host smart-6ff50d3d-d135-4b78-a678-d0262aca5a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881646140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2881646140
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3198288625
Short name T375
Test name
Test status
Simulation time 240040091 ps
CPU time 1.11 seconds
Started Jul 02 09:56:01 AM PDT 24
Finished Jul 02 09:56:03 AM PDT 24
Peak memory 217148 kb
Host smart-4d8402c5-0aba-4c9a-a07e-9680a97c4dd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198288625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3198288625
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1514745466
Short name T556
Test name
Test status
Simulation time 42520063 ps
CPU time 0.81 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:22 AM PDT 24
Peak memory 218680 kb
Host smart-daeb9e81-bd76-4c66-a9ed-a37fad3b59eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514745466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1514745466
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1502841186
Short name T310
Test name
Test status
Simulation time 51224193 ps
CPU time 1.23 seconds
Started Jul 02 09:56:08 AM PDT 24
Finished Jul 02 09:56:10 AM PDT 24
Peak memory 217632 kb
Host smart-bca39d63-673e-4870-b901-0f3818ae3629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502841186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1502841186
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3195256325
Short name T452
Test name
Test status
Simulation time 22902993 ps
CPU time 1.1 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 215836 kb
Host smart-0d9c3b6c-ddd1-4151-b6eb-22ae4f894c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195256325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3195256325
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3616899900
Short name T886
Test name
Test status
Simulation time 26838075 ps
CPU time 0.96 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 215652 kb
Host smart-a37420af-0b65-4146-8e5a-848b29ce483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616899900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3616899900
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.4183683679
Short name T799
Test name
Test status
Simulation time 84343773 ps
CPU time 1.46 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:20 AM PDT 24
Peak memory 207508 kb
Host smart-6d642940-a7d4-4475-8791-f5e53386b6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183683679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4183683679
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3869186512
Short name T327
Test name
Test status
Simulation time 154501991031 ps
CPU time 1760.61 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 10:25:52 AM PDT 24
Peak memory 226636 kb
Host smart-029690aa-2d32-4591-8cbc-cf44e21cabb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869186512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3869186512
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3779708732
Short name T821
Test name
Test status
Simulation time 35496430 ps
CPU time 1.16 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 220184 kb
Host smart-a98a1cd4-4972-4c76-a28e-86eae857a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779708732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3779708732
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3761369200
Short name T976
Test name
Test status
Simulation time 83307724 ps
CPU time 0.92 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 215520 kb
Host smart-4b0504cd-70dc-4e36-96e6-571388c3c706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761369200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3761369200
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2401250518
Short name T213
Test name
Test status
Simulation time 21719984 ps
CPU time 0.86 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 216696 kb
Host smart-6d62d018-b529-45b6-a04e-799d0246309b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401250518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2401250518
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.3939831382
Short name T637
Test name
Test status
Simulation time 21065231 ps
CPU time 1.01 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 224036 kb
Host smart-972e9ee9-ac0a-4e65-bd78-2af28a540855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939831382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3939831382
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.623582594
Short name T426
Test name
Test status
Simulation time 36580633 ps
CPU time 1.15 seconds
Started Jul 02 09:56:11 AM PDT 24
Finished Jul 02 09:56:12 AM PDT 24
Peak memory 217620 kb
Host smart-269b5563-8c9a-4a5c-ab9d-06490db4e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623582594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.623582594
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.495656971
Short name T706
Test name
Test status
Simulation time 26877411 ps
CPU time 0.94 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 215916 kb
Host smart-84903851-5ee0-4fd1-900f-2b98a1900dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495656971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.495656971
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.5700483
Short name T756
Test name
Test status
Simulation time 17302647 ps
CPU time 0.97 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 215664 kb
Host smart-a65e19e4-2b9f-4885-a127-c4cca0d4e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5700483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.5700483
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1058265639
Short name T624
Test name
Test status
Simulation time 1294769300 ps
CPU time 3.17 seconds
Started Jul 02 09:56:07 AM PDT 24
Finished Jul 02 09:56:11 AM PDT 24
Peak memory 215716 kb
Host smart-aabfd004-74a9-4968-a23c-6780761b313c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058265639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1058265639
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2682518799
Short name T100
Test name
Test status
Simulation time 261433606025 ps
CPU time 3058.74 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 10:47:16 AM PDT 24
Peak memory 231120 kb
Host smart-ab201194-b5e1-43bc-8194-22731e586431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682518799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2682518799
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.326434649
Short name T419
Test name
Test status
Simulation time 26248872 ps
CPU time 1.17 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 219928 kb
Host smart-2a6b40bb-3b35-4cd6-ba36-5c1ce90a83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326434649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.326434649
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2537817610
Short name T687
Test name
Test status
Simulation time 25324421 ps
CPU time 0.91 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 207068 kb
Host smart-354e7d96-fb8e-4cf3-a06f-728ec6ea793c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537817610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2537817610
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4112667329
Short name T816
Test name
Test status
Simulation time 82254380 ps
CPU time 0.87 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 216376 kb
Host smart-cc7afd04-880b-4b36-b7a9-dd604007f61e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112667329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4112667329
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.587965691
Short name T216
Test name
Test status
Simulation time 36184486 ps
CPU time 1.23 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 217172 kb
Host smart-247191f4-5c7c-45f8-bd53-8a0d29e5ab63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587965691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.587965691
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2103111629
Short name T175
Test name
Test status
Simulation time 29679038 ps
CPU time 0.95 seconds
Started Jul 02 09:56:29 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 224044 kb
Host smart-821be3d3-23b7-4fa3-8c97-1aee76ddbc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103111629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2103111629
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1762952435
Short name T324
Test name
Test status
Simulation time 61813787 ps
CPU time 1.09 seconds
Started Jul 02 09:56:25 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 218896 kb
Host smart-6ba8aa26-25cb-4840-ba27-3ec3579f0d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762952435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1762952435
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3793184922
Short name T110
Test name
Test status
Simulation time 34921056 ps
CPU time 0.89 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 216024 kb
Host smart-bdd1431f-7640-4949-9d95-92fd216783ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793184922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3793184922
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2788760835
Short name T850
Test name
Test status
Simulation time 37951931 ps
CPU time 0.9 seconds
Started Jul 02 09:56:09 AM PDT 24
Finished Jul 02 09:56:11 AM PDT 24
Peak memory 215660 kb
Host smart-71e9b4a0-9a18-4137-aca2-c81205196146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788760835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2788760835
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1922236690
Short name T853
Test name
Test status
Simulation time 2399954822 ps
CPU time 3.56 seconds
Started Jul 02 09:56:27 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 217648 kb
Host smart-9d123f4d-2362-4a5e-a273-24e105026f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922236690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1922236690
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3170649406
Short name T232
Test name
Test status
Simulation time 43454320785 ps
CPU time 1102.11 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 10:14:49 AM PDT 24
Peak memory 221592 kb
Host smart-10fe8c09-3e49-4f14-ba47-5f851ae5933b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170649406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3170649406
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.4178835029
Short name T717
Test name
Test status
Simulation time 68278682 ps
CPU time 0.9 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:20 AM PDT 24
Peak memory 207064 kb
Host smart-9cd87958-9fba-4400-ba4a-ca9e1005f8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178835029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4178835029
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1037618464
Short name T156
Test name
Test status
Simulation time 38717088 ps
CPU time 0.82 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 09:56:15 AM PDT 24
Peak memory 215768 kb
Host smart-2acaa229-d761-4be2-8a4b-66bbe245cc0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037618464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1037618464
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1941150147
Short name T964
Test name
Test status
Simulation time 112256145 ps
CPU time 1.17 seconds
Started Jul 02 09:56:27 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 217104 kb
Host smart-bffa7731-2b5b-4312-9a5c-937b75387b6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941150147 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1941150147
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1154263265
Short name T138
Test name
Test status
Simulation time 35657588 ps
CPU time 1.15 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 09:56:16 AM PDT 24
Peak memory 232512 kb
Host smart-16cb1219-ddf6-4105-a7db-cc79c5ff39ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154263265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1154263265
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2866776704
Short name T937
Test name
Test status
Simulation time 219733857 ps
CPU time 2.63 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 220264 kb
Host smart-20842ee0-2877-4bee-905f-1904026d27b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866776704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2866776704
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.360632427
Short name T779
Test name
Test status
Simulation time 23546147 ps
CPU time 1.12 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 215904 kb
Host smart-abd35777-4432-4bc2-882f-2a5e3df81042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360632427 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.360632427
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3860196102
Short name T363
Test name
Test status
Simulation time 16279530 ps
CPU time 0.98 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:20 AM PDT 24
Peak memory 215644 kb
Host smart-ec4bcc43-29c2-4d00-bf0e-8bfe6f152d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860196102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3860196102
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4249744293
Short name T95
Test name
Test status
Simulation time 446384146 ps
CPU time 2.69 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 220164 kb
Host smart-5f557d84-f3b3-4099-ab61-b23a8cabfaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249744293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4249744293
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.845494337
Short name T728
Test name
Test status
Simulation time 83479346241 ps
CPU time 1045.48 seconds
Started Jul 02 09:56:13 AM PDT 24
Finished Jul 02 10:13:39 AM PDT 24
Peak memory 223244 kb
Host smart-99b14d09-dc6d-460f-b6e2-75c379d99785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845494337 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.845494337
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3038379211
Short name T948
Test name
Test status
Simulation time 51036132 ps
CPU time 1.23 seconds
Started Jul 02 09:56:11 AM PDT 24
Finished Jul 02 09:56:13 AM PDT 24
Peak memory 216052 kb
Host smart-4c871e75-9c43-4d18-98fe-cc4782b7ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038379211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3038379211
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3570473141
Short name T361
Test name
Test status
Simulation time 88871474 ps
CPU time 1 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 207088 kb
Host smart-4527ca0c-b8a5-463a-a6e2-b0563840303b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570473141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3570473141
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2056559019
Short name T927
Test name
Test status
Simulation time 49593618 ps
CPU time 0.87 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:19 AM PDT 24
Peak memory 216588 kb
Host smart-d1c3b67b-581e-494a-a7ef-d29d6e6e2b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056559019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2056559019
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2475452311
Short name T429
Test name
Test status
Simulation time 103885177 ps
CPU time 1.12 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 215928 kb
Host smart-511e8774-da24-4dc6-87db-6b24ef49da5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475452311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2475452311
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.76210055
Short name T837
Test name
Test status
Simulation time 36399628 ps
CPU time 0.92 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 223972 kb
Host smart-c79e85ed-1a04-4b70-b29e-82eda3030108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76210055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.76210055
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.794054301
Short name T24
Test name
Test status
Simulation time 29685692 ps
CPU time 1.26 seconds
Started Jul 02 09:56:29 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 220156 kb
Host smart-a1fd7740-19df-4472-8c94-2432ead774bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794054301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.794054301
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2850421737
Short name T615
Test name
Test status
Simulation time 26892196 ps
CPU time 0.97 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 215756 kb
Host smart-8e8b37e6-e845-4feb-a06f-8e2a75e51c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850421737 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2850421737
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1940176011
Short name T552
Test name
Test status
Simulation time 18589005 ps
CPU time 1.08 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 215600 kb
Host smart-30e4638f-fecb-4d54-b102-c36e5a5199ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940176011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1940176011
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3533657184
Short name T534
Test name
Test status
Simulation time 335741601 ps
CPU time 1.49 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 217816 kb
Host smart-628b2ea4-928b-4421-a443-d3b88bc1c74e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533657184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3533657184
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2547490233
Short name T914
Test name
Test status
Simulation time 59247198897 ps
CPU time 1296.51 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 10:18:04 AM PDT 24
Peak memory 222564 kb
Host smart-c7487c29-b31f-409c-b311-c3bf61210509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547490233 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2547490233
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3248638763
Short name T991
Test name
Test status
Simulation time 35491660 ps
CPU time 1.08 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 220116 kb
Host smart-5abd1abc-b7fa-4ab9-a0fb-7de8976569e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248638763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3248638763
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.432795341
Short name T701
Test name
Test status
Simulation time 63561386 ps
CPU time 0.92 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 207080 kb
Host smart-f2e6d3d6-86e7-456f-876e-fa942b047dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432795341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.432795341
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.693633650
Short name T97
Test name
Test status
Simulation time 14401740 ps
CPU time 0.92 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 216872 kb
Host smart-dcc0f928-3fc7-4fee-98b8-e47d5aad9db9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693633650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.693633650
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2854313570
Short name T712
Test name
Test status
Simulation time 53698638 ps
CPU time 1.2 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 217304 kb
Host smart-16a824b0-1d6d-43fa-83e2-db7560b6294e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854313570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2854313570
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2447290272
Short name T553
Test name
Test status
Simulation time 21177073 ps
CPU time 0.94 seconds
Started Jul 02 09:56:15 AM PDT 24
Finished Jul 02 09:56:17 AM PDT 24
Peak memory 218588 kb
Host smart-ebf61e22-8f1b-4657-85a1-1e5c2a9e75f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447290272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2447290272
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.598049100
Short name T645
Test name
Test status
Simulation time 54855258 ps
CPU time 1.27 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 217692 kb
Host smart-88beea09-3097-4dfe-9de8-6a550cf75327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598049100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.598049100
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3411038220
Short name T990
Test name
Test status
Simulation time 34630186 ps
CPU time 0.91 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 216196 kb
Host smart-0f14b704-0478-4475-a6e8-47b790cdaef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411038220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3411038220
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3739831595
Short name T485
Test name
Test status
Simulation time 16320000 ps
CPU time 0.95 seconds
Started Jul 02 09:56:30 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 215584 kb
Host smart-c756f58a-772c-4f75-a514-d659e82d0b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739831595 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3739831595
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3956544350
Short name T735
Test name
Test status
Simulation time 637235880 ps
CPU time 3.88 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 217416 kb
Host smart-09224db5-099c-4cb8-ae9c-2d245b0f807f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956544350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3956544350
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4002831285
Short name T780
Test name
Test status
Simulation time 106161950377 ps
CPU time 606.49 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 10:06:36 AM PDT 24
Peak memory 219976 kb
Host smart-59ce08c9-5832-4931-90bd-5c51d93a9d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002831285 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4002831285
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.353659004
Short name T21
Test name
Test status
Simulation time 84948152 ps
CPU time 1.23 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 221208 kb
Host smart-c4e1ae22-d42c-4a1f-842a-dddc9de03ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353659004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.353659004
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3314449622
Short name T72
Test name
Test status
Simulation time 37548744 ps
CPU time 1.16 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 207120 kb
Host smart-1e277fbf-fc46-40d6-8631-c61ca02a7a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314449622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3314449622
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2371750974
Short name T899
Test name
Test status
Simulation time 103577705 ps
CPU time 0.81 seconds
Started Jul 02 09:56:15 AM PDT 24
Finished Jul 02 09:56:17 AM PDT 24
Peak memory 216276 kb
Host smart-c549e379-1698-4680-9877-2948199ba166
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371750974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2371750974
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2133109504
Short name T124
Test name
Test status
Simulation time 60457892 ps
CPU time 1.24 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 218468 kb
Host smart-08537232-07c4-42db-a898-784157656d82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133109504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2133109504
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2006205391
Short name T765
Test name
Test status
Simulation time 19431134 ps
CPU time 1.09 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 219944 kb
Host smart-285e9f80-f90a-4a23-a4ed-848153e14be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006205391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2006205391
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1576403092
Short name T601
Test name
Test status
Simulation time 234004201 ps
CPU time 1.2 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 217696 kb
Host smart-6b1bb142-5711-485d-92e7-0bc8a37315ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576403092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1576403092
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.995135573
Short name T1
Test name
Test status
Simulation time 23273513 ps
CPU time 0.93 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 216120 kb
Host smart-cb3dca23-0f1f-451a-a76d-03f7651f735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995135573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.995135573
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.639031086
Short name T504
Test name
Test status
Simulation time 16437042 ps
CPU time 0.96 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 215836 kb
Host smart-697cf8a6-7bc6-4b41-906b-defe70973800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639031086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.639031086
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.990607548
Short name T396
Test name
Test status
Simulation time 353100001 ps
CPU time 6.95 seconds
Started Jul 02 09:56:16 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 217572 kb
Host smart-87dfddab-e5b0-452f-8e59-859d319aecce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990607548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.990607548
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3630689239
Short name T238
Test name
Test status
Simulation time 291900201797 ps
CPU time 1324.52 seconds
Started Jul 02 09:56:14 AM PDT 24
Finished Jul 02 10:18:20 AM PDT 24
Peak memory 222352 kb
Host smart-83ef2247-d22d-49a7-9336-63765550eca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630689239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3630689239
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3167273642
Short name T487
Test name
Test status
Simulation time 24574112 ps
CPU time 1.17 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 220292 kb
Host smart-e6c3c916-6c9e-4572-bc62-8f02a7e34f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167273642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3167273642
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1781659746
Short name T362
Test name
Test status
Simulation time 24145927 ps
CPU time 0.81 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:32 AM PDT 24
Peak memory 206800 kb
Host smart-49fbb628-0560-4286-bc3a-1363cbd45dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781659746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1781659746
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2510822913
Short name T227
Test name
Test status
Simulation time 17315591 ps
CPU time 0.82 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 215772 kb
Host smart-54142fa0-00a8-4ef5-bcaf-23c96e86c879
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510822913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2510822913
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1124750234
Short name T118
Test name
Test status
Simulation time 58839168 ps
CPU time 1 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 217128 kb
Host smart-8a1282a8-6ac9-4333-95a1-23b14e89e4a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124750234 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1124750234
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3867543454
Short name T53
Test name
Test status
Simulation time 23235765 ps
CPU time 1.04 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 224324 kb
Host smart-17395a96-df6d-43bc-b531-72c3b490638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867543454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3867543454
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3064347271
Short name T594
Test name
Test status
Simulation time 46753615 ps
CPU time 1.01 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 217808 kb
Host smart-f54bfad4-2a4f-406b-aa75-bfe3e1350d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064347271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3064347271
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2934237626
Short name T523
Test name
Test status
Simulation time 32427193 ps
CPU time 0.95 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 224384 kb
Host smart-8cae67e4-ae02-4ab2-a3ad-35ad1bc045da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934237626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2934237626
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3589930900
Short name T777
Test name
Test status
Simulation time 17838132 ps
CPU time 1.03 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 207484 kb
Host smart-44f6abfd-d097-44ea-88c1-f4c8803fbbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589930900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3589930900
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1949055558
Short name T536
Test name
Test status
Simulation time 70217307 ps
CPU time 0.94 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 215556 kb
Host smart-1af5796a-d468-4731-85d4-cd3442dd3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949055558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1949055558
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2137675861
Short name T835
Test name
Test status
Simulation time 244918742 ps
CPU time 5.15 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 215684 kb
Host smart-ea218a3a-a56b-4087-ba7a-cae09e87bbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137675861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2137675861
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1912011317
Short name T679
Test name
Test status
Simulation time 208242452104 ps
CPU time 2391.68 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 10:35:33 AM PDT 24
Peak memory 229324 kb
Host smart-008e2fb5-df47-4e3f-82d5-fbbbc91a7b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912011317 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1912011317
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2364668947
Short name T85
Test name
Test status
Simulation time 28195912 ps
CPU time 1.29 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 221208 kb
Host smart-ba566b8c-eb0c-4884-b9dd-815e95f159cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364668947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2364668947
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4132305073
Short name T869
Test name
Test status
Simulation time 19731405 ps
CPU time 1.02 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:42 AM PDT 24
Peak memory 219844 kb
Host smart-ae458b50-4bad-4cec-905f-7aff8d151b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132305073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4132305073
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1150127382
Short name T488
Test name
Test status
Simulation time 181143629 ps
CPU time 2.22 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 220544 kb
Host smart-f93dab72-5c3f-4922-9426-ab40108afd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150127382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1150127382
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3254095316
Short name T189
Test name
Test status
Simulation time 41267671 ps
CPU time 1.13 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:20 AM PDT 24
Peak memory 220360 kb
Host smart-c14f0626-42c8-41bd-812f-127649ed2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254095316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3254095316
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.784352175
Short name T167
Test name
Test status
Simulation time 24649649 ps
CPU time 0.92 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 218532 kb
Host smart-3944df60-9ff3-4450-8b00-5c10a2c8d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784352175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.784352175
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2061508741
Short name T506
Test name
Test status
Simulation time 49727653 ps
CPU time 1.85 seconds
Started Jul 02 09:56:05 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 217872 kb
Host smart-ebff1d7d-53f2-4c78-92fc-924724e59dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061508741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2061508741
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.78000671
Short name T507
Test name
Test status
Simulation time 25166723 ps
CPU time 1.14 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 218960 kb
Host smart-5d2abf35-16dd-41b3-abce-c882b8d7bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78000671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.78000671
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2284110231
Short name T8
Test name
Test status
Simulation time 19746676 ps
CPU time 1.09 seconds
Started Jul 02 09:56:44 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 218680 kb
Host smart-5895555f-cc24-4d05-841f-16346f8c9242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284110231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2284110231
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3183289021
Short name T585
Test name
Test status
Simulation time 42105610 ps
CPU time 1.07 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 217504 kb
Host smart-620300aa-24bd-450f-8c49-3bab926b732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183289021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3183289021
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.370958129
Short name T410
Test name
Test status
Simulation time 39973972 ps
CPU time 1.12 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:22 AM PDT 24
Peak memory 221444 kb
Host smart-5f7fa8b5-34f2-4be2-983c-760251a0bbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370958129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.370958129
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.254746455
Short name T670
Test name
Test status
Simulation time 19699296 ps
CPU time 1.17 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 224204 kb
Host smart-5421088b-f496-4d15-9787-9fa00298db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254746455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.254746455
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1392347891
Short name T862
Test name
Test status
Simulation time 69020768 ps
CPU time 1.87 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:22 AM PDT 24
Peak memory 218996 kb
Host smart-7b9bbb57-945a-458d-a6c6-cc2e4c939f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392347891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1392347891
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.4042334933
Short name T366
Test name
Test status
Simulation time 42235401 ps
CPU time 1.16 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 219036 kb
Host smart-2dc10fbb-bb11-4ea8-a52f-13790901f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042334933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.4042334933
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2230951364
Short name T181
Test name
Test status
Simulation time 24780885 ps
CPU time 0.93 seconds
Started Jul 02 09:56:26 AM PDT 24
Finished Jul 02 09:56:34 AM PDT 24
Peak memory 218884 kb
Host smart-70b88d42-624f-472d-8071-30d223eb3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230951364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2230951364
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.93671070
Short name T573
Test name
Test status
Simulation time 25144159 ps
CPU time 1.12 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 218832 kb
Host smart-75c3979f-9ecd-4193-afc9-763aa9cff0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93671070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.93671070
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1180998460
Short name T222
Test name
Test status
Simulation time 148383000 ps
CPU time 1.23 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 219992 kb
Host smart-8ef75b57-ce82-48d5-833b-bfb47937ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180998460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1180998460
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.4044521176
Short name T841
Test name
Test status
Simulation time 34469470 ps
CPU time 1.03 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 220060 kb
Host smart-8dc546a6-d9c3-4712-9784-9c17fbae212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044521176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4044521176
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1530094791
Short name T941
Test name
Test status
Simulation time 343935505 ps
CPU time 4.54 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 220604 kb
Host smart-09535475-ba47-4824-bdf6-fca2a72a9cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530094791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1530094791
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.4217125756
Short name T683
Test name
Test status
Simulation time 22813972 ps
CPU time 1.11 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 221264 kb
Host smart-7176c61e-13b9-4692-8408-c3ebbd113df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217125756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.4217125756
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.404539452
Short name T987
Test name
Test status
Simulation time 30882875 ps
CPU time 0.91 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 218464 kb
Host smart-9ca80cd7-cdc6-4e7d-b076-a0101b346923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404539452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.404539452
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1919240518
Short name T796
Test name
Test status
Simulation time 75585580 ps
CPU time 1.68 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 219324 kb
Host smart-7c83e631-1a3d-4c54-9ef8-7d8a3884e738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919240518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1919240518
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3976353685
Short name T525
Test name
Test status
Simulation time 141336438 ps
CPU time 1.13 seconds
Started Jul 02 09:56:28 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 219468 kb
Host smart-cccccc9b-c01b-4d3f-aede-74eeb732b751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976353685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3976353685
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1940398242
Short name T133
Test name
Test status
Simulation time 29572431 ps
CPU time 1.07 seconds
Started Jul 02 09:56:33 AM PDT 24
Finished Jul 02 09:56:38 AM PDT 24
Peak memory 219984 kb
Host smart-5ae488f4-d275-43d8-a1aa-a94043ac7110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940398242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1940398242
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.4007492730
Short name T293
Test name
Test status
Simulation time 53218295 ps
CPU time 1.15 seconds
Started Jul 02 09:56:30 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 217568 kb
Host smart-9e9908b0-6772-4752-9c5d-4d879a0cbbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007492730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.4007492730
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1454589301
Short name T210
Test name
Test status
Simulation time 36714884 ps
CPU time 0.88 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 218668 kb
Host smart-b8982e1c-c921-425e-80fd-3af223157677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454589301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1454589301
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.69133102
Short name T858
Test name
Test status
Simulation time 41520890 ps
CPU time 1.39 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 217628 kb
Host smart-f485d57c-add2-43ff-8a10-fedca7639f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69133102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.69133102
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1982123663
Short name T711
Test name
Test status
Simulation time 29795187 ps
CPU time 1.35 seconds
Started Jul 02 09:56:37 AM PDT 24
Finished Jul 02 09:56:42 AM PDT 24
Peak memory 219036 kb
Host smart-fb3e23d6-f68d-4407-9f52-9269046d0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982123663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1982123663
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3025421896
Short name T220
Test name
Test status
Simulation time 18622503 ps
CPU time 1 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 218816 kb
Host smart-0132da9b-2d90-481d-ac18-b1dc3ff8b0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025421896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3025421896
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1122918518
Short name T443
Test name
Test status
Simulation time 31243672 ps
CPU time 1.31 seconds
Started Jul 02 09:56:17 AM PDT 24
Finished Jul 02 09:56:20 AM PDT 24
Peak memory 220256 kb
Host smart-3352c923-13b8-47c4-9943-63a1cd2f4790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122918518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1122918518
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2048781563
Short name T478
Test name
Test status
Simulation time 30636317 ps
CPU time 1.29 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 219752 kb
Host smart-5ac42939-ad11-4f5a-ba32-2d10d7eccf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048781563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2048781563
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3324541052
Short name T414
Test name
Test status
Simulation time 27142158 ps
CPU time 0.87 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 215192 kb
Host smart-bf1597cd-a917-4446-97c2-842ad46a15dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324541052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3324541052
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2231650024
Short name T163
Test name
Test status
Simulation time 27660042 ps
CPU time 0.8 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 216532 kb
Host smart-e78b67fc-78b9-434d-a36e-c94ed531903f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231650024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2231650024
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.778214172
Short name T114
Test name
Test status
Simulation time 113105132 ps
CPU time 1.21 seconds
Started Jul 02 09:55:34 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 217288 kb
Host smart-1ff9ef71-cb73-4d4f-b8f2-36ee24f82c74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778214172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.778214172
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3085748297
Short name T207
Test name
Test status
Simulation time 19391982 ps
CPU time 1.03 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 218736 kb
Host smart-4b763c04-70c4-4267-9d4a-621cf1368ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085748297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3085748297
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3401026952
Short name T411
Test name
Test status
Simulation time 42124483 ps
CPU time 1.5 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 217784 kb
Host smart-8d043baf-41e3-4c17-b669-0514a93ed02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401026952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3401026952
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.381118326
Short name T719
Test name
Test status
Simulation time 23702809 ps
CPU time 1.04 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:37 AM PDT 24
Peak memory 215852 kb
Host smart-58fe26c0-8047-4d8a-8240-a1f00536aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381118326 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.381118326
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.999515492
Short name T908
Test name
Test status
Simulation time 23152145 ps
CPU time 0.9 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 207476 kb
Host smart-93fc8af5-40b7-47c5-b50e-c8f2b833ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999515492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.999515492
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3810042117
Short name T346
Test name
Test status
Simulation time 27282869 ps
CPU time 0.9 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 215644 kb
Host smart-be479ae1-d7e3-45d3-a47e-64dfdd2a1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810042117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3810042117
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2531735356
Short name T247
Test name
Test status
Simulation time 653761754 ps
CPU time 6.45 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:28 AM PDT 24
Peak memory 217688 kb
Host smart-d3faa68d-b70a-4f47-a417-c8f0bc6c667f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531735356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2531735356
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3348594363
Short name T432
Test name
Test status
Simulation time 184620619740 ps
CPU time 1106.72 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 10:13:50 AM PDT 24
Peak memory 224032 kb
Host smart-87fc6829-3661-4b43-af69-78b4532fed1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348594363 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3348594363
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1875736051
Short name T302
Test name
Test status
Simulation time 51922046 ps
CPU time 1.21 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 220212 kb
Host smart-e5061f30-952c-4cde-a511-7a0df3b35871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875736051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1875736051
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2315072161
Short name T785
Test name
Test status
Simulation time 20377354 ps
CPU time 1.04 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 218984 kb
Host smart-616724ea-06de-4c07-9729-e99986cc1326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315072161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2315072161
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3830031707
Short name T823
Test name
Test status
Simulation time 348417900 ps
CPU time 3.4 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 219100 kb
Host smart-7d3b59ef-5714-4333-aadc-3efb2b2245f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830031707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3830031707
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1551085554
Short name T73
Test name
Test status
Simulation time 70751434 ps
CPU time 1.04 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219740 kb
Host smart-f506c6c9-dc88-46a5-a7d1-94a53716a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551085554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1551085554
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3592990442
Short name T148
Test name
Test status
Simulation time 96099712 ps
CPU time 1 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 220068 kb
Host smart-e4e15db8-4675-4df0-8eac-eb28be3a5695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592990442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3592990442
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4024589307
Short name T810
Test name
Test status
Simulation time 42796247 ps
CPU time 1.4 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 218888 kb
Host smart-f8f8ba9a-52fe-4dc6-8b64-e3b676c53307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024589307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4024589307
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2474087482
Short name T855
Test name
Test status
Simulation time 29130083 ps
CPU time 1.23 seconds
Started Jul 02 09:56:25 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 220140 kb
Host smart-cf755ba7-d310-4cf0-aaae-c78fb786ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474087482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2474087482
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2269183590
Short name T980
Test name
Test status
Simulation time 43796680 ps
CPU time 1.09 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:27 AM PDT 24
Peak memory 219844 kb
Host smart-6e8a3fe8-1ad1-4fe4-a794-0d07d8683933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269183590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2269183590
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4174534843
Short name T13
Test name
Test status
Simulation time 44504314 ps
CPU time 1.49 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 215700 kb
Host smart-2d016217-ae1e-4cf2-8bae-8e259ba35bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174534843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4174534843
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2159528354
Short name T838
Test name
Test status
Simulation time 40324306 ps
CPU time 1.15 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 218880 kb
Host smart-5ed0746b-de15-4cb9-9fa4-cfac9828416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159528354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2159528354
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1091622802
Short name T74
Test name
Test status
Simulation time 30092106 ps
CPU time 1.21 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:39 AM PDT 24
Peak memory 219684 kb
Host smart-007b4335-17eb-4e35-b9b6-2b482bdcb31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091622802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1091622802
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3100710235
Short name T861
Test name
Test status
Simulation time 164172375 ps
CPU time 1.29 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 219244 kb
Host smart-6d153e27-a5a0-4c2d-932b-3e93f5490aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100710235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3100710235
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3924407803
Short name T166
Test name
Test status
Simulation time 46065712 ps
CPU time 1.1 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219900 kb
Host smart-0b67a63d-0088-438e-b618-36e5420b12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924407803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3924407803
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2215822701
Short name T155
Test name
Test status
Simulation time 18460674 ps
CPU time 1.17 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 224264 kb
Host smart-1f230dd0-146f-4911-a9dc-0f7baadba1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215822701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2215822701
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2315402152
Short name T84
Test name
Test status
Simulation time 228753172 ps
CPU time 1.05 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:21 AM PDT 24
Peak memory 217636 kb
Host smart-45746a9f-6066-4654-8526-06f7978fbd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315402152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2315402152
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.515075586
Short name T867
Test name
Test status
Simulation time 27902468 ps
CPU time 1.31 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 220668 kb
Host smart-0b3f7276-3b03-4a20-bcb0-3f45e685fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515075586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.515075586
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.766770028
Short name T161
Test name
Test status
Simulation time 117943448 ps
CPU time 0.9 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 218772 kb
Host smart-bd237573-8472-4bad-bbfc-5b4dd05075fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766770028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.766770028
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3846027648
Short name T61
Test name
Test status
Simulation time 72001794 ps
CPU time 1.3 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 219248 kb
Host smart-c1050233-18b3-4215-8092-20cc6d0d14c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846027648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3846027648
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2212323462
Short name T612
Test name
Test status
Simulation time 21951645 ps
CPU time 1.08 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 218708 kb
Host smart-835457c8-14e8-40da-ae76-5258e3115d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212323462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2212323462
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3429863563
Short name T169
Test name
Test status
Simulation time 20089335 ps
CPU time 1.18 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 224288 kb
Host smart-17d7b605-2c14-413c-95b4-9c7978d70c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429863563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3429863563
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1259595564
Short name T954
Test name
Test status
Simulation time 48144086 ps
CPU time 1.48 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 219112 kb
Host smart-f2a4e365-ce01-427f-810f-41d355f42583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259595564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1259595564
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.281838019
Short name T993
Test name
Test status
Simulation time 40170923 ps
CPU time 1.11 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 221124 kb
Host smart-286e7a7d-995a-408f-a185-946b3db9372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281838019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.281838019
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2639870651
Short name T977
Test name
Test status
Simulation time 23492949 ps
CPU time 1.25 seconds
Started Jul 02 09:56:30 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 229876 kb
Host smart-a0f604af-006c-4eff-97fb-7a6448409f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639870651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2639870651
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.373073263
Short name T666
Test name
Test status
Simulation time 58340937 ps
CPU time 1.23 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:23 AM PDT 24
Peak memory 217672 kb
Host smart-b24e585b-256f-4521-9d6d-c2542ca95f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373073263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.373073263
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1778666583
Short name T611
Test name
Test status
Simulation time 64958348 ps
CPU time 1.06 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 220708 kb
Host smart-dd44820d-add9-4835-86cc-8082860a1e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778666583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1778666583
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.4170154383
Short name T873
Test name
Test status
Simulation time 20870849 ps
CPU time 1.13 seconds
Started Jul 02 09:56:32 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 220248 kb
Host smart-23aeb220-0a97-44bc-9e9d-dbd85e7df362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170154383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4170154383
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1171528758
Short name T605
Test name
Test status
Simulation time 62183919 ps
CPU time 1.07 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 220264 kb
Host smart-a2a5c60a-adc1-4452-ba55-a91594357e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171528758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1171528758
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1311373811
Short name T575
Test name
Test status
Simulation time 55974149 ps
CPU time 1.24 seconds
Started Jul 02 09:56:19 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 220380 kb
Host smart-fbaadf82-5599-4164-98cf-90dfaefd6724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311373811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1311373811
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2021119022
Short name T149
Test name
Test status
Simulation time 26569849 ps
CPU time 1.32 seconds
Started Jul 02 09:56:27 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 230012 kb
Host smart-75060b4b-9d8a-4caf-92c4-f568154fd0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021119022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2021119022
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.90610989
Short name T674
Test name
Test status
Simulation time 151817070 ps
CPU time 3.3 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:42 AM PDT 24
Peak memory 217964 kb
Host smart-f507d8cc-b488-4698-b32a-49afee718ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90610989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.90610989
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.548643857
Short name T284
Test name
Test status
Simulation time 46207270 ps
CPU time 1.16 seconds
Started Jul 02 09:55:36 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 219648 kb
Host smart-d9dc8be4-aaf4-46ec-b44e-0864794ce995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548643857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.548643857
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.638105890
Short name T876
Test name
Test status
Simulation time 18338220 ps
CPU time 0.96 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 206972 kb
Host smart-bcc04d19-5e07-41f7-bade-eb9332349d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638105890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.638105890
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3437934535
Short name T172
Test name
Test status
Simulation time 12749196 ps
CPU time 0.98 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 216688 kb
Host smart-29a2485e-6c2e-4d93-a074-8755802e7061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437934535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3437934535
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1644183681
Short name T500
Test name
Test status
Simulation time 73300203 ps
CPU time 1.08 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:30 AM PDT 24
Peak memory 217340 kb
Host smart-ebf8201e-95cd-4613-9b31-8649ba027e58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644183681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1644183681
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4047847968
Short name T510
Test name
Test status
Simulation time 39488242 ps
CPU time 0.87 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 218636 kb
Host smart-7f78d289-5d28-418d-8b5b-f18e48618474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047847968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4047847968
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2524884355
Short name T497
Test name
Test status
Simulation time 79474767 ps
CPU time 1.8 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 219132 kb
Host smart-61a0645f-6705-4de7-8924-103fe12023b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524884355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2524884355
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1351768741
Short name T663
Test name
Test status
Simulation time 28299295 ps
CPU time 1.04 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 224332 kb
Host smart-4d439732-1bb1-464b-a7e8-1afa9fd0618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351768741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1351768741
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3612419775
Short name T25
Test name
Test status
Simulation time 57514704 ps
CPU time 0.93 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 207432 kb
Host smart-af74e9ab-eac2-499e-8973-b27abb4672a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612419775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3612419775
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.652539683
Short name T444
Test name
Test status
Simulation time 32458054 ps
CPU time 0.96 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 215644 kb
Host smart-f047d49a-c905-4b47-a00e-eeebc4ba0afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652539683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.652539683
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3053369350
Short name T894
Test name
Test status
Simulation time 226935625 ps
CPU time 2.45 seconds
Started Jul 02 09:55:38 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 217676 kb
Host smart-cf3097bd-4943-442c-911f-8f0c0e61151b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053369350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3053369350
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3910611192
Short name T928
Test name
Test status
Simulation time 24249760290 ps
CPU time 598.61 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 10:05:23 AM PDT 24
Peak memory 224040 kb
Host smart-2d058c19-77af-4a86-ac22-54eadd11a940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910611192 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3910611192
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1642090356
Short name T543
Test name
Test status
Simulation time 82560702 ps
CPU time 1.19 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 219452 kb
Host smart-011c8fd8-4a6b-4db1-bce9-b82d60388de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642090356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1642090356
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2164318480
Short name T787
Test name
Test status
Simulation time 65200765 ps
CPU time 1.16 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 232424 kb
Host smart-d46c573d-7267-49e1-8ded-fb60ffc9da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164318480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2164318480
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.254097827
Short name T348
Test name
Test status
Simulation time 116198030 ps
CPU time 2.38 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 220516 kb
Host smart-9f43a9e1-6366-4e34-b566-f1d586aeff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254097827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.254097827
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.762998369
Short name T569
Test name
Test status
Simulation time 28732959 ps
CPU time 1.27 seconds
Started Jul 02 09:56:28 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 221240 kb
Host smart-3c66f379-d00e-44d0-a238-9d8584ab9433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762998369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.762998369
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2072020102
Short name T201
Test name
Test status
Simulation time 28470863 ps
CPU time 0.87 seconds
Started Jul 02 09:56:25 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 218364 kb
Host smart-e47678b2-c517-4e3c-ac2a-b353215f569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072020102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2072020102
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3062527422
Short name T41
Test name
Test status
Simulation time 55764126 ps
CPU time 1.21 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 218960 kb
Host smart-4df3ac8d-bd41-45a2-a2e0-105e7b8a3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062527422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3062527422
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1053870508
Short name T729
Test name
Test status
Simulation time 30231458 ps
CPU time 1.31 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 220868 kb
Host smart-8b0025c1-84ea-43d4-bd2c-bde7e76282e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053870508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1053870508
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2603463023
Short name T558
Test name
Test status
Simulation time 22018815 ps
CPU time 1.01 seconds
Started Jul 02 09:57:17 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 224276 kb
Host smart-8d2d72c9-4078-4a38-a79d-2b2c287ada3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603463023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2603463023
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2444644836
Short name T983
Test name
Test status
Simulation time 84008962 ps
CPU time 1.18 seconds
Started Jul 02 09:56:35 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219076 kb
Host smart-695d1209-2510-47b9-b386-de87b57363fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444644836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2444644836
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2110271637
Short name T136
Test name
Test status
Simulation time 29315142 ps
CPU time 1.3 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 220072 kb
Host smart-e53f49bc-27ab-44cb-96cc-39e77ffda12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110271637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2110271637
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3176002168
Short name T392
Test name
Test status
Simulation time 38300088 ps
CPU time 0.87 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 218404 kb
Host smart-0d626133-77e5-44ae-801c-c803ea51acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176002168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3176002168
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1383776915
Short name T99
Test name
Test status
Simulation time 72201406 ps
CPU time 1.38 seconds
Started Jul 02 09:56:34 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 219256 kb
Host smart-59256dc1-b5f3-4d2a-9173-bcf7cc3f58ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383776915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1383776915
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1057767116
Short name T720
Test name
Test status
Simulation time 88435947 ps
CPU time 1.19 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:22 AM PDT 24
Peak memory 218956 kb
Host smart-7101b118-d4a3-42f6-8906-24c05bb9a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057767116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1057767116
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2892558931
Short name T834
Test name
Test status
Simulation time 19754188 ps
CPU time 1.08 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 218964 kb
Host smart-93cf0b6e-0b78-4664-be14-1f24bc80292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892558931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2892558931
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_alert.2470182985
Short name T27
Test name
Test status
Simulation time 25279211 ps
CPU time 1.2 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 220020 kb
Host smart-1a8f6d49-79ba-473c-88ea-c39e9cb94f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470182985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2470182985
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_genbits.2286607317
Short name T960
Test name
Test status
Simulation time 35227389 ps
CPU time 1.32 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:42 AM PDT 24
Peak memory 218800 kb
Host smart-2778636a-4438-4a62-81f0-ec5f52ab2a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286607317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2286607317
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.863734863
Short name T814
Test name
Test status
Simulation time 35999054 ps
CPU time 1.15 seconds
Started Jul 02 09:56:32 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 221396 kb
Host smart-9c6b438b-0467-4249-a6d3-024ddb755bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863734863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.863734863
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.903581506
Short name T906
Test name
Test status
Simulation time 68870307 ps
CPU time 0.9 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 220204 kb
Host smart-9e22d3e5-8b44-4f4c-ba40-3b810897bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903581506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.903581506
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3119894818
Short name T657
Test name
Test status
Simulation time 52187771 ps
CPU time 1.84 seconds
Started Jul 02 09:57:09 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 217668 kb
Host smart-bad1edc1-278d-4486-aeb9-06b741500777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119894818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3119894818
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.4085939603
Short name T190
Test name
Test status
Simulation time 261361625 ps
CPU time 1.4 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 220836 kb
Host smart-ce783bee-cbbb-4f34-9cd8-2bc0e8f0eae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085939603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.4085939603
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.677043134
Short name T458
Test name
Test status
Simulation time 18316659 ps
CPU time 1.02 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 218576 kb
Host smart-ffbdb585-9d65-4c7a-bb8b-60875371f935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677043134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.677043134
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.411917853
Short name T579
Test name
Test status
Simulation time 152680201 ps
CPU time 3.26 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 219576 kb
Host smart-6f345c57-f8a3-46a4-838b-008757a9f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411917853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.411917853
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1728805256
Short name T125
Test name
Test status
Simulation time 166695980 ps
CPU time 1.39 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 218924 kb
Host smart-c51436b1-71ca-4879-b545-d961e3e5ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728805256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1728805256
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2948875505
Short name T154
Test name
Test status
Simulation time 23462702 ps
CPU time 0.91 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 218744 kb
Host smart-1dde1dc9-5daf-4682-9f3a-03df9696e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948875505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2948875505
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3441129880
Short name T903
Test name
Test status
Simulation time 36382328 ps
CPU time 1.42 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 218892 kb
Host smart-7d402975-c32e-4ff1-bebd-f1c4cf046e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441129880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3441129880
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1258614443
Short name T89
Test name
Test status
Simulation time 28403036 ps
CPU time 1.16 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 218904 kb
Host smart-b718441e-a56d-4420-90b3-dc00031d3ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258614443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1258614443
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2580686928
Short name T183
Test name
Test status
Simulation time 20259596 ps
CPU time 1.14 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 224308 kb
Host smart-05d28722-33de-48b7-8c78-2c0f23ae3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580686928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2580686928
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1618898899
Short name T570
Test name
Test status
Simulation time 69216861 ps
CPU time 1.22 seconds
Started Jul 02 09:56:26 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 218772 kb
Host smart-7d601489-4b9e-4a3c-abd2-b9593c1ce09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618898899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1618898899
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1587235349
Short name T542
Test name
Test status
Simulation time 44217223 ps
CPU time 1.19 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 219256 kb
Host smart-9ba39496-326a-4f2a-b7ba-47b0ec8befd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587235349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1587235349
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3440946436
Short name T703
Test name
Test status
Simulation time 25865158 ps
CPU time 1.09 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 207068 kb
Host smart-8bdbce08-ca23-47f2-b4c0-0fee391f3d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440946436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3440946436
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.314814799
Short name T87
Test name
Test status
Simulation time 13352663 ps
CPU time 0.88 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 216428 kb
Host smart-9c4ad9c3-569e-4169-a548-c3c75284db2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314814799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.314814799
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3133512973
Short name T925
Test name
Test status
Simulation time 37517269 ps
CPU time 1.39 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 217136 kb
Host smart-afdbc0fe-6a9b-45e4-a2e3-8badfce55386
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133512973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3133512973
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3205623273
Short name T788
Test name
Test status
Simulation time 37459108 ps
CPU time 0.84 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 218652 kb
Host smart-3ebbebe7-738a-4233-bf2c-f9726605db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205623273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3205623273
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2164195895
Short name T10
Test name
Test status
Simulation time 61957744 ps
CPU time 2.37 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 220476 kb
Host smart-52e416ea-52c6-420d-a743-7c337adc6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164195895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2164195895
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3772685175
Short name T437
Test name
Test status
Simulation time 23311910 ps
CPU time 1.2 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:55:42 AM PDT 24
Peak memory 224272 kb
Host smart-ee6c8ab2-300f-48cf-b7d3-987efec20794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772685175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3772685175
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.2471639191
Short name T493
Test name
Test status
Simulation time 41916466 ps
CPU time 0.9 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 215648 kb
Host smart-9c47ed11-7db1-4833-9a7b-6f3e2bf993ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471639191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2471639191
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4020387681
Short name T767
Test name
Test status
Simulation time 2246381693 ps
CPU time 2.74 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:29 AM PDT 24
Peak memory 217580 kb
Host smart-44614482-51cc-447b-8d4c-268f914192c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020387681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4020387681
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1607403688
Short name T415
Test name
Test status
Simulation time 114670547046 ps
CPU time 1468.37 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 10:20:03 AM PDT 24
Peak memory 224172 kb
Host smart-66d6ced0-5fc9-42a2-90d4-51cfac50a668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607403688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1607403688
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1018938739
Short name T740
Test name
Test status
Simulation time 24577093 ps
CPU time 1.14 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 220188 kb
Host smart-c33505f0-0204-4e84-8e12-745f81e445a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018938739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1018938739
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2529069985
Short name T893
Test name
Test status
Simulation time 30094930 ps
CPU time 1.38 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 226080 kb
Host smart-27ae42e3-1e9f-44d0-8a28-7c93f2945447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529069985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2529069985
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2834260958
Short name T566
Test name
Test status
Simulation time 76886614 ps
CPU time 1.24 seconds
Started Jul 02 09:56:47 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 218884 kb
Host smart-d157f72d-8fb8-4d77-931b-c35563a32f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834260958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2834260958
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.652767020
Short name T586
Test name
Test status
Simulation time 362133529 ps
CPU time 1.7 seconds
Started Jul 02 09:56:26 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 218844 kb
Host smart-d7f439af-66c2-46ac-ba57-d8a1af196bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652767020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.652767020
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1241386996
Short name T112
Test name
Test status
Simulation time 136544406 ps
CPU time 0.96 seconds
Started Jul 02 09:56:52 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 221064 kb
Host smart-25750837-6680-4617-89a5-041db4239001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241386996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1241386996
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.979515383
Short name T490
Test name
Test status
Simulation time 54406064 ps
CPU time 1.99 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 220496 kb
Host smart-4a911f39-3545-4ad6-b926-3cb640d6d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979515383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.979515383
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3155063013
Short name T844
Test name
Test status
Simulation time 85060026 ps
CPU time 1.18 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 218768 kb
Host smart-4b1b7779-a5fe-4293-9f04-ff7d4b485823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155063013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3155063013
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2187768493
Short name T932
Test name
Test status
Simulation time 165187533 ps
CPU time 1.1 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 220044 kb
Host smart-fd88fe50-f831-4c51-a367-033e952b3177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187768493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2187768493
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3829728291
Short name T527
Test name
Test status
Simulation time 43763071 ps
CPU time 1.38 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 219544 kb
Host smart-71607da5-0864-4972-9a58-ae1a4f81cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829728291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3829728291
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.455028194
Short name T602
Test name
Test status
Simulation time 50012889 ps
CPU time 1.29 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 220288 kb
Host smart-05bd387f-473c-4d79-af34-1294792adfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455028194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.455028194
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2830492603
Short name T139
Test name
Test status
Simulation time 32481999 ps
CPU time 0.96 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 218904 kb
Host smart-3bf7f34e-abb6-40b6-98b3-63cc489ff169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830492603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2830492603
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3695274605
Short name T456
Test name
Test status
Simulation time 69398968 ps
CPU time 1.09 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 217804 kb
Host smart-21c70434-efdc-4043-9c14-2c8e2f4b9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695274605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3695274605
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2693199291
Short name T129
Test name
Test status
Simulation time 42908288 ps
CPU time 1.21 seconds
Started Jul 02 09:56:58 AM PDT 24
Finished Jul 02 09:57:03 AM PDT 24
Peak memory 218948 kb
Host smart-d94b7e19-43f9-44fb-b4da-991ecaa71921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693199291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2693199291
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.185213551
Short name T215
Test name
Test status
Simulation time 22020106 ps
CPU time 1.09 seconds
Started Jul 02 09:56:40 AM PDT 24
Finished Jul 02 09:56:44 AM PDT 24
Peak memory 224288 kb
Host smart-af5b10ad-36b6-44ff-8569-61fda22a7aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185213551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.185213551
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4289128157
Short name T635
Test name
Test status
Simulation time 79929263 ps
CPU time 1.35 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 217720 kb
Host smart-585baace-b6e0-4187-abbf-26ebffd7603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289128157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4289128157
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1271757921
Short name T223
Test name
Test status
Simulation time 116142340 ps
CPU time 1.22 seconds
Started Jul 02 09:56:48 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 221880 kb
Host smart-7507c363-a5b4-4228-a9a9-3edc15e9deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271757921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1271757921
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1126288323
Short name T394
Test name
Test status
Simulation time 73867812 ps
CPU time 0.77 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:29 AM PDT 24
Peak memory 218708 kb
Host smart-07d45079-2a1d-4089-b632-d25ce67b882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126288323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1126288323
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3148416820
Short name T248
Test name
Test status
Simulation time 70190335 ps
CPU time 1.12 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 218952 kb
Host smart-38879258-a59f-48bc-ac3c-9260d9c6ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148416820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3148416820
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.796111983
Short name T498
Test name
Test status
Simulation time 23249205 ps
CPU time 1.11 seconds
Started Jul 02 09:56:25 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 218908 kb
Host smart-be20ffa7-bcbe-41b4-8a31-a2ea0c666f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796111983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.796111983
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3058116315
Short name T157
Test name
Test status
Simulation time 25735149 ps
CPU time 1.05 seconds
Started Jul 02 09:56:28 AM PDT 24
Finished Jul 02 09:56:35 AM PDT 24
Peak memory 224288 kb
Host smart-bcd960fb-2247-4ced-9fdc-e3c5972b331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058116315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3058116315
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.908194732
Short name T629
Test name
Test status
Simulation time 63375148 ps
CPU time 1.34 seconds
Started Jul 02 09:56:30 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 219192 kb
Host smart-f8b3e7b0-d180-4ef1-ae56-b66e9f573b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908194732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.908194732
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.896245273
Short name T409
Test name
Test status
Simulation time 103823214 ps
CPU time 1.24 seconds
Started Jul 02 09:56:20 AM PDT 24
Finished Jul 02 09:56:28 AM PDT 24
Peak memory 216040 kb
Host smart-6c176e3e-49ae-4523-b988-9f73f4892ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896245273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.896245273
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1395858380
Short name T211
Test name
Test status
Simulation time 97282974 ps
CPU time 0.84 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 218664 kb
Host smart-92f66435-5659-4dad-8443-79889a854c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395858380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1395858380
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2538730926
Short name T319
Test name
Test status
Simulation time 53535463 ps
CPU time 1.66 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 218812 kb
Host smart-e79f23c4-5fe2-4ba2-9594-5030c66a8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538730926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2538730926
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3715311879
Short name T589
Test name
Test status
Simulation time 48639434 ps
CPU time 1.26 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:51 AM PDT 24
Peak memory 220256 kb
Host smart-ab50d7fc-7ece-4c66-a4bb-afbb9554bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715311879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3715311879
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.4270533455
Short name T935
Test name
Test status
Simulation time 19093354 ps
CPU time 1.06 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:47 AM PDT 24
Peak memory 218756 kb
Host smart-5ae98e46-fcd5-49b7-8e72-91cc03f1efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270533455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4270533455
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2202267044
Short name T877
Test name
Test status
Simulation time 141927132 ps
CPU time 1.78 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:42 AM PDT 24
Peak memory 219152 kb
Host smart-5a482d98-e62c-4d29-87da-f9157cdd6ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202267044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2202267044
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3937252314
Short name T141
Test name
Test status
Simulation time 59244811 ps
CPU time 1.13 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 221024 kb
Host smart-d50b7dd9-e0e1-4e13-972d-cacd217800d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937252314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3937252314
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2176627534
Short name T195
Test name
Test status
Simulation time 24211870 ps
CPU time 0.95 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:32 AM PDT 24
Peak memory 219820 kb
Host smart-a46c43af-7427-4574-9bdb-7e523d499bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176627534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2176627534
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.3467699801
Short name T104
Test name
Test status
Simulation time 81171191 ps
CPU time 1.31 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 218928 kb
Host smart-32311471-2501-4455-9dd3-45e3572f493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467699801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3467699801
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1406421960
Short name T647
Test name
Test status
Simulation time 44407827 ps
CPU time 0.87 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 206848 kb
Host smart-001c0286-f4a9-4269-bc72-dcac4e2a54d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406421960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1406421960
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4194397279
Short name T219
Test name
Test status
Simulation time 13464451 ps
CPU time 0.88 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 215740 kb
Host smart-05397c80-6733-48be-aa06-bf44049f7513
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194397279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4194397279
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4112516081
Short name T135
Test name
Test status
Simulation time 34249028 ps
CPU time 1.22 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 220296 kb
Host smart-686c156f-d0bf-4d05-a86c-77dc8a41080a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112516081 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4112516081
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1410496551
Short name T489
Test name
Test status
Simulation time 21524164 ps
CPU time 0.99 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 218804 kb
Host smart-33daf9b4-4759-4e11-8bd1-96363003fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410496551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1410496551
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2731786285
Short name T704
Test name
Test status
Simulation time 47865589 ps
CPU time 1.45 seconds
Started Jul 02 09:55:29 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 218976 kb
Host smart-02b53cfc-3216-4eca-975f-ce02e679f1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731786285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2731786285
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2018677635
Short name T52
Test name
Test status
Simulation time 20643392 ps
CPU time 1.16 seconds
Started Jul 02 09:55:30 AM PDT 24
Finished Jul 02 09:55:41 AM PDT 24
Peak memory 224364 kb
Host smart-9845e619-ed2b-42e8-afe8-17a5b3d86cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018677635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2018677635
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2772827641
Short name T978
Test name
Test status
Simulation time 116633226 ps
CPU time 0.93 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 207444 kb
Host smart-59cadd8a-9b91-4941-ae6d-fa87846cf5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772827641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2772827641
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1586897080
Short name T979
Test name
Test status
Simulation time 52699673 ps
CPU time 0.91 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 215664 kb
Host smart-23706a1a-1f32-4719-bc5b-9ee088f7bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586897080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1586897080
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2047136323
Short name T249
Test name
Test status
Simulation time 1777225332 ps
CPU time 4.04 seconds
Started Jul 02 09:55:35 AM PDT 24
Finished Jul 02 09:55:47 AM PDT 24
Peak memory 217708 kb
Host smart-7e2274a9-b178-4ad3-a0a4-f5b249ed3d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047136323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2047136323
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1210641108
Short name T408
Test name
Test status
Simulation time 46837837345 ps
CPU time 1061.35 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 10:13:06 AM PDT 24
Peak memory 220544 kb
Host smart-9f87fdb8-ba4f-4471-b75f-8e0f6a75dfbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210641108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1210641108
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2434759317
Short name T162
Test name
Test status
Simulation time 49998472 ps
CPU time 0.92 seconds
Started Jul 02 09:56:31 AM PDT 24
Finished Jul 02 09:56:36 AM PDT 24
Peak memory 224120 kb
Host smart-9ce921a2-88ab-462d-940a-63386ca5cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434759317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2434759317
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.235590246
Short name T349
Test name
Test status
Simulation time 121430768 ps
CPU time 1.26 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:55 AM PDT 24
Peak memory 218828 kb
Host smart-feb8059f-2d7b-4d8e-9af4-e35c8ef13e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235590246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.235590246
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.827387787
Short name T519
Test name
Test status
Simulation time 43317692 ps
CPU time 1.12 seconds
Started Jul 02 09:56:53 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 219056 kb
Host smart-0fba04f8-9451-42e3-8cdd-7422f2c7f211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827387787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.827387787
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3195076728
Short name T892
Test name
Test status
Simulation time 41973056 ps
CPU time 1.18 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:29 AM PDT 24
Peak memory 220156 kb
Host smart-bcb6f200-e5b7-498f-adc1-9ac20dcc536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195076728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3195076728
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2374752992
Short name T772
Test name
Test status
Simulation time 62227028 ps
CPU time 1.02 seconds
Started Jul 02 09:56:36 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 218996 kb
Host smart-db79e0af-6f1b-4f20-b28f-4745e9d16659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374752992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2374752992
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2673288363
Short name T547
Test name
Test status
Simulation time 90703260 ps
CPU time 1.18 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 219728 kb
Host smart-ccfed137-ba39-4971-a93c-e10a22087453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673288363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2673288363
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1569747259
Short name T424
Test name
Test status
Simulation time 18423552 ps
CPU time 1.06 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:29 AM PDT 24
Peak memory 218860 kb
Host smart-a9697873-6558-48fd-8492-89d87cb44c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569747259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1569747259
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1476536273
Short name T634
Test name
Test status
Simulation time 46209412 ps
CPU time 1.8 seconds
Started Jul 02 09:56:32 AM PDT 24
Finished Jul 02 09:56:38 AM PDT 24
Peak memory 218900 kb
Host smart-a2ac921d-88f2-436a-a7ad-8ea28df5f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476536273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1476536273
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3108635424
Short name T866
Test name
Test status
Simulation time 67250546 ps
CPU time 1.11 seconds
Started Jul 02 09:56:39 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 220052 kb
Host smart-8d436260-ef0a-4200-a69a-551a6bb93cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108635424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3108635424
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3737696687
Short name T768
Test name
Test status
Simulation time 26205371 ps
CPU time 0.87 seconds
Started Jul 02 09:56:23 AM PDT 24
Finished Jul 02 09:56:31 AM PDT 24
Peak memory 218744 kb
Host smart-bb127440-7516-4c1a-962e-8173d4c10288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737696687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3737696687
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2921208953
Short name T675
Test name
Test status
Simulation time 131891422 ps
CPU time 2.19 seconds
Started Jul 02 09:56:59 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 217836 kb
Host smart-9c300caa-acb9-42a7-9e2d-f924ce8bbae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921208953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2921208953
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2018009020
Short name T912
Test name
Test status
Simulation time 59966916 ps
CPU time 1.13 seconds
Started Jul 02 09:56:42 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 220052 kb
Host smart-cc234f58-c5a2-4c18-a3ad-f8bb2da361c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018009020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2018009020
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1675655748
Short name T75
Test name
Test status
Simulation time 143391178 ps
CPU time 1.03 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 220108 kb
Host smart-d8be6359-ad68-404e-a06c-f8e9ebd6972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675655748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1675655748
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2766866433
Short name T688
Test name
Test status
Simulation time 73966562 ps
CPU time 1.18 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 217480 kb
Host smart-65cd1ed4-f09b-44aa-96c8-27b7d4b59bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766866433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2766866433
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1852857147
Short name T878
Test name
Test status
Simulation time 109114786 ps
CPU time 1.2 seconds
Started Jul 02 09:56:37 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 219952 kb
Host smart-38adc28f-c00d-4ba1-ba0d-1d8a3ed956a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852857147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1852857147
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3405344533
Short name T944
Test name
Test status
Simulation time 93411862 ps
CPU time 1.23 seconds
Started Jul 02 09:57:07 AM PDT 24
Finished Jul 02 09:57:10 AM PDT 24
Peak memory 226160 kb
Host smart-e62a3d23-b19a-4278-8464-8b3682b24192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405344533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3405344533
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2549775825
Short name T484
Test name
Test status
Simulation time 173866824 ps
CPU time 1.15 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 217784 kb
Host smart-cbc78547-b04a-4ee1-ad6d-ef722685139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549775825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2549775825
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1660477908
Short name T291
Test name
Test status
Simulation time 92903028 ps
CPU time 1.17 seconds
Started Jul 02 09:56:24 AM PDT 24
Finished Jul 02 09:56:33 AM PDT 24
Peak memory 220220 kb
Host smart-39912b9f-e205-4cde-975c-d15550f262c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660477908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1660477908
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2505887236
Short name T192
Test name
Test status
Simulation time 30051195 ps
CPU time 0.84 seconds
Started Jul 02 09:57:02 AM PDT 24
Finished Jul 02 09:57:05 AM PDT 24
Peak memory 218492 kb
Host smart-c8a2209b-bec4-4fb9-bcbe-9a1a3264250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505887236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2505887236
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1918583217
Short name T696
Test name
Test status
Simulation time 33081886 ps
CPU time 1.43 seconds
Started Jul 02 09:56:38 AM PDT 24
Finished Jul 02 09:56:43 AM PDT 24
Peak memory 218844 kb
Host smart-cf88c7ca-c72c-4cac-9b06-fce055bfb95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918583217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1918583217
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.4176032600
Short name T342
Test name
Test status
Simulation time 176239341 ps
CPU time 1.2 seconds
Started Jul 02 09:56:45 AM PDT 24
Finished Jul 02 09:56:49 AM PDT 24
Peak memory 220016 kb
Host smart-4972cf16-d36c-484e-9d15-056c9aeac164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176032600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.4176032600
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3684258445
Short name T185
Test name
Test status
Simulation time 24164651 ps
CPU time 1.04 seconds
Started Jul 02 09:56:22 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 224244 kb
Host smart-3a352091-14b9-444e-8fe5-9ceab59c1e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684258445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3684258445
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2415054730
Short name T725
Test name
Test status
Simulation time 44359606 ps
CPU time 1.72 seconds
Started Jul 02 09:56:43 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 220592 kb
Host smart-30354e6a-101e-4db1-8e7b-3f43a5bc86a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415054730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2415054730
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.406791676
Short name T225
Test name
Test status
Simulation time 47457679 ps
CPU time 1.14 seconds
Started Jul 02 09:56:21 AM PDT 24
Finished Jul 02 09:56:30 AM PDT 24
Peak memory 218964 kb
Host smart-910079f0-32b1-44d0-b3e0-9b4826ba23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406791676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.406791676
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.564965306
Short name T902
Test name
Test status
Simulation time 19641083 ps
CPU time 1.03 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:46 AM PDT 24
Peak memory 219080 kb
Host smart-ffc9d417-3085-4d2b-8c49-e1b44f4857fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564965306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.564965306
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1221670696
Short name T462
Test name
Test status
Simulation time 102178922 ps
CPU time 1.3 seconds
Started Jul 02 09:56:18 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 220244 kb
Host smart-18ccc4ab-08c6-4e90-95f0-6be58aae9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221670696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1221670696
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2365973413
Short name T182
Test name
Test status
Simulation time 23623002 ps
CPU time 1.16 seconds
Started Jul 02 09:56:41 AM PDT 24
Finished Jul 02 09:56:45 AM PDT 24
Peak memory 218956 kb
Host smart-e3b87ca6-6362-462a-8d90-9dce52e3c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365973413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2365973413
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3926914910
Short name T15
Test name
Test status
Simulation time 18909792 ps
CPU time 1.18 seconds
Started Jul 02 09:56:55 AM PDT 24
Finished Jul 02 09:57:01 AM PDT 24
Peak memory 224272 kb
Host smart-7cf8296d-8143-4ecf-9ab5-2c39aa3edcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926914910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3926914910
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1119656784
Short name T957
Test name
Test status
Simulation time 57280443 ps
CPU time 1.91 seconds
Started Jul 02 09:56:51 AM PDT 24
Finished Jul 02 09:56:56 AM PDT 24
Peak memory 218724 kb
Host smart-47bffc03-0fa9-425d-bf21-7b838ef94ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119656784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1119656784
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%