Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.87 98.25 93.91 97.07 93.60 96.37 99.77 92.08


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T284 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2429613739 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:02 PM PDT 24 32223233 ps
T285 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1404308073 Jul 03 05:22:57 PM PDT 24 Jul 03 05:22:59 PM PDT 24 131214920 ps
T1027 /workspace/coverage/cover_reg_top/17.edn_intr_test.87249716 Jul 03 05:22:57 PM PDT 24 Jul 03 05:22:59 PM PDT 24 12433137 ps
T297 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1128453366 Jul 03 05:22:38 PM PDT 24 Jul 03 05:22:41 PM PDT 24 177529040 ps
T1028 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1431899750 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:03 PM PDT 24 30457566 ps
T286 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3830921517 Jul 03 05:22:51 PM PDT 24 Jul 03 05:22:52 PM PDT 24 14413235 ps
T267 /workspace/coverage/cover_reg_top/12.edn_csr_rw.4070997042 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 38414518 ps
T1029 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3420382672 Jul 03 05:22:55 PM PDT 24 Jul 03 05:22:57 PM PDT 24 46069927 ps
T1030 /workspace/coverage/cover_reg_top/28.edn_intr_test.2864247415 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 38313557 ps
T1031 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1048039794 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 79585610 ps
T1032 /workspace/coverage/cover_reg_top/21.edn_intr_test.2652619909 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:01 PM PDT 24 45247212 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1025352558 Jul 03 05:22:49 PM PDT 24 Jul 03 05:22:51 PM PDT 24 25646256 ps
T1034 /workspace/coverage/cover_reg_top/15.edn_intr_test.3604967065 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 20315331 ps
T287 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4199009521 Jul 03 05:22:44 PM PDT 24 Jul 03 05:22:47 PM PDT 24 73730497 ps
T1035 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3224258884 Jul 03 05:23:07 PM PDT 24 Jul 03 05:23:09 PM PDT 24 50843720 ps
T303 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1331733996 Jul 03 05:23:09 PM PDT 24 Jul 03 05:23:12 PM PDT 24 320366596 ps
T1036 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1168217034 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:57 PM PDT 24 120125383 ps
T304 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2250034644 Jul 03 05:22:51 PM PDT 24 Jul 03 05:22:54 PM PDT 24 94787106 ps
T1037 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3887078577 Jul 03 05:22:41 PM PDT 24 Jul 03 05:22:43 PM PDT 24 29743635 ps
T307 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2923120356 Jul 03 05:22:38 PM PDT 24 Jul 03 05:22:40 PM PDT 24 161968932 ps
T1038 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2279519307 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:01 PM PDT 24 13306248 ps
T305 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1116492857 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:56 PM PDT 24 304231344 ps
T268 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3416023225 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:04 PM PDT 24 11915372 ps
T1039 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4058368525 Jul 03 05:22:51 PM PDT 24 Jul 03 05:22:54 PM PDT 24 84624755 ps
T1040 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4070494672 Jul 03 05:22:52 PM PDT 24 Jul 03 05:22:55 PM PDT 24 142906965 ps
T1041 /workspace/coverage/cover_reg_top/1.edn_intr_test.329846207 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:04 PM PDT 24 37529289 ps
T1042 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4036217210 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 36262556 ps
T1043 /workspace/coverage/cover_reg_top/47.edn_intr_test.4021465711 Jul 03 05:23:12 PM PDT 24 Jul 03 05:23:14 PM PDT 24 24076587 ps
T1044 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1316617514 Jul 03 05:22:48 PM PDT 24 Jul 03 05:22:51 PM PDT 24 187513028 ps
T269 /workspace/coverage/cover_reg_top/5.edn_csr_rw.457920098 Jul 03 05:22:54 PM PDT 24 Jul 03 05:22:55 PM PDT 24 13433568 ps
T1045 /workspace/coverage/cover_reg_top/39.edn_intr_test.2503608831 Jul 03 05:23:19 PM PDT 24 Jul 03 05:23:21 PM PDT 24 19255210 ps
T270 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2529638356 Jul 03 05:22:45 PM PDT 24 Jul 03 05:22:48 PM PDT 24 36907587 ps
T1046 /workspace/coverage/cover_reg_top/12.edn_intr_test.2050664614 Jul 03 05:22:50 PM PDT 24 Jul 03 05:22:51 PM PDT 24 13820804 ps
T1047 /workspace/coverage/cover_reg_top/42.edn_intr_test.3046548862 Jul 03 05:23:06 PM PDT 24 Jul 03 05:23:08 PM PDT 24 33570048 ps
T1048 /workspace/coverage/cover_reg_top/20.edn_intr_test.3569549731 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:02 PM PDT 24 26841161 ps
T1049 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3921490512 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:02 PM PDT 24 26298006 ps
T1050 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3196620763 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:57 PM PDT 24 27591131 ps
T1051 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1980064187 Jul 03 05:23:04 PM PDT 24 Jul 03 05:23:07 PM PDT 24 118837405 ps
T1052 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3603801984 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:59 PM PDT 24 619391566 ps
T271 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2294634014 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 29677116 ps
T1053 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1418985944 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:02 PM PDT 24 169361442 ps
T1054 /workspace/coverage/cover_reg_top/17.edn_csr_rw.564283177 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 167496561 ps
T1055 /workspace/coverage/cover_reg_top/41.edn_intr_test.2747734035 Jul 03 05:23:03 PM PDT 24 Jul 03 05:23:06 PM PDT 24 52953888 ps
T1056 /workspace/coverage/cover_reg_top/30.edn_intr_test.2285462706 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 18850306 ps
T1057 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3602023052 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:03 PM PDT 24 46248454 ps
T1058 /workspace/coverage/cover_reg_top/40.edn_intr_test.2239646028 Jul 03 05:23:14 PM PDT 24 Jul 03 05:23:15 PM PDT 24 12534778 ps
T1059 /workspace/coverage/cover_reg_top/11.edn_intr_test.2454656688 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:02 PM PDT 24 20950941 ps
T1060 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3319697239 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:56 PM PDT 24 204299487 ps
T1061 /workspace/coverage/cover_reg_top/48.edn_intr_test.2042625683 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:03 PM PDT 24 23180865 ps
T308 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.834647128 Jul 03 05:22:41 PM PDT 24 Jul 03 05:22:44 PM PDT 24 179828587 ps
T1062 /workspace/coverage/cover_reg_top/14.edn_tl_errors.61762124 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:05 PM PDT 24 47454078 ps
T1063 /workspace/coverage/cover_reg_top/33.edn_intr_test.4146141112 Jul 03 05:23:05 PM PDT 24 Jul 03 05:23:07 PM PDT 24 47915002 ps
T1064 /workspace/coverage/cover_reg_top/18.edn_intr_test.405179913 Jul 03 05:23:10 PM PDT 24 Jul 03 05:23:12 PM PDT 24 67947453 ps
T1065 /workspace/coverage/cover_reg_top/8.edn_intr_test.3291374308 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:57 PM PDT 24 13390058 ps
T1066 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4083202865 Jul 03 05:23:03 PM PDT 24 Jul 03 05:23:08 PM PDT 24 707644023 ps
T1067 /workspace/coverage/cover_reg_top/45.edn_intr_test.4276341327 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 47778181 ps
T1068 /workspace/coverage/cover_reg_top/26.edn_intr_test.1502264684 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 46594923 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3718030237 Jul 03 05:22:35 PM PDT 24 Jul 03 05:22:36 PM PDT 24 38283032 ps
T1070 /workspace/coverage/cover_reg_top/36.edn_intr_test.2603067023 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 19377764 ps
T1071 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.599025230 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:57 PM PDT 24 69038574 ps
T1072 /workspace/coverage/cover_reg_top/16.edn_intr_test.3404686449 Jul 03 05:23:04 PM PDT 24 Jul 03 05:23:07 PM PDT 24 13075493 ps
T1073 /workspace/coverage/cover_reg_top/6.edn_csr_rw.743610216 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:58 PM PDT 24 14028110 ps
T1074 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3951287115 Jul 03 05:22:56 PM PDT 24 Jul 03 05:22:59 PM PDT 24 287239923 ps
T1075 /workspace/coverage/cover_reg_top/5.edn_intr_test.2138436677 Jul 03 05:22:40 PM PDT 24 Jul 03 05:22:42 PM PDT 24 44825108 ps
T1076 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4000171421 Jul 03 05:22:52 PM PDT 24 Jul 03 05:22:54 PM PDT 24 26009549 ps
T1077 /workspace/coverage/cover_reg_top/27.edn_intr_test.2294515046 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 27853788 ps
T1078 /workspace/coverage/cover_reg_top/46.edn_intr_test.3077273316 Jul 03 05:23:13 PM PDT 24 Jul 03 05:23:15 PM PDT 24 21330311 ps
T1079 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3054617490 Jul 03 05:23:07 PM PDT 24 Jul 03 05:23:09 PM PDT 24 207951759 ps
T272 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3123741681 Jul 03 05:22:50 PM PDT 24 Jul 03 05:22:52 PM PDT 24 146505157 ps
T1080 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2832643966 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:56 PM PDT 24 64506200 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1068938923 Jul 03 05:23:09 PM PDT 24 Jul 03 05:23:14 PM PDT 24 227202640 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.59559039 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 42115426 ps
T1083 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1471308800 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:09 PM PDT 24 131417603 ps
T273 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1103023489 Jul 03 05:22:57 PM PDT 24 Jul 03 05:22:59 PM PDT 24 18590262 ps
T1084 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.114958631 Jul 03 05:22:54 PM PDT 24 Jul 03 05:22:57 PM PDT 24 148421701 ps
T1085 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.61682892 Jul 03 05:22:57 PM PDT 24 Jul 03 05:23:00 PM PDT 24 315075761 ps
T274 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2460703451 Jul 03 05:22:40 PM PDT 24 Jul 03 05:22:42 PM PDT 24 35096762 ps
T1086 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1474533560 Jul 03 05:22:55 PM PDT 24 Jul 03 05:22:58 PM PDT 24 308263354 ps
T275 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3051567632 Jul 03 05:22:52 PM PDT 24 Jul 03 05:22:54 PM PDT 24 14744184 ps
T1087 /workspace/coverage/cover_reg_top/49.edn_intr_test.2831685248 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:02 PM PDT 24 34083857 ps
T1088 /workspace/coverage/cover_reg_top/10.edn_csr_rw.219506753 Jul 03 05:23:05 PM PDT 24 Jul 03 05:23:07 PM PDT 24 45829185 ps
T1089 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3215410515 Jul 03 05:22:44 PM PDT 24 Jul 03 05:22:46 PM PDT 24 17723915 ps
T1090 /workspace/coverage/cover_reg_top/1.edn_csr_rw.239584230 Jul 03 05:22:45 PM PDT 24 Jul 03 05:22:47 PM PDT 24 20723621 ps
T1091 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3963702048 Jul 03 05:22:55 PM PDT 24 Jul 03 05:22:56 PM PDT 24 63532237 ps
T309 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.347520140 Jul 03 05:22:51 PM PDT 24 Jul 03 05:22:54 PM PDT 24 268418406 ps
T1092 /workspace/coverage/cover_reg_top/19.edn_intr_test.2412229624 Jul 03 05:23:37 PM PDT 24 Jul 03 05:23:39 PM PDT 24 21375055 ps
T306 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1834417658 Jul 03 05:23:03 PM PDT 24 Jul 03 05:23:07 PM PDT 24 287169156 ps
T1093 /workspace/coverage/cover_reg_top/7.edn_intr_test.1194734527 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 16573419 ps
T1094 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2981232662 Jul 03 05:23:05 PM PDT 24 Jul 03 05:23:11 PM PDT 24 210641146 ps
T1095 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3945454391 Jul 03 05:22:49 PM PDT 24 Jul 03 05:22:51 PM PDT 24 277067630 ps
T1096 /workspace/coverage/cover_reg_top/44.edn_intr_test.3524846174 Jul 03 05:23:03 PM PDT 24 Jul 03 05:23:06 PM PDT 24 11653674 ps
T1097 /workspace/coverage/cover_reg_top/35.edn_intr_test.1536250729 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:01 PM PDT 24 23375387 ps
T277 /workspace/coverage/cover_reg_top/18.edn_csr_rw.17967104 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:05 PM PDT 24 15378748 ps
T1098 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4027290413 Jul 03 05:22:55 PM PDT 24 Jul 03 05:22:57 PM PDT 24 71894229 ps
T1099 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2353852211 Jul 03 05:22:45 PM PDT 24 Jul 03 05:22:49 PM PDT 24 29578031 ps
T1100 /workspace/coverage/cover_reg_top/3.edn_intr_test.2191875023 Jul 03 05:22:44 PM PDT 24 Jul 03 05:22:45 PM PDT 24 73878888 ps
T1101 /workspace/coverage/cover_reg_top/9.edn_intr_test.3169649531 Jul 03 05:22:44 PM PDT 24 Jul 03 05:22:47 PM PDT 24 17072405 ps
T1102 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.804911314 Jul 03 05:22:41 PM PDT 24 Jul 03 05:22:43 PM PDT 24 76832249 ps
T276 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3707314092 Jul 03 05:23:07 PM PDT 24 Jul 03 05:23:09 PM PDT 24 41170918 ps
T278 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2982845953 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 19197249 ps
T1103 /workspace/coverage/cover_reg_top/25.edn_intr_test.3781890154 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:04 PM PDT 24 45843143 ps
T1104 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3440913738 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:05 PM PDT 24 108851163 ps
T1105 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.807724956 Jul 03 05:22:57 PM PDT 24 Jul 03 05:22:59 PM PDT 24 17229261 ps
T1106 /workspace/coverage/cover_reg_top/24.edn_intr_test.3246208370 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:04 PM PDT 24 31611931 ps
T1107 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.695495874 Jul 03 05:22:51 PM PDT 24 Jul 03 05:22:53 PM PDT 24 19359689 ps
T279 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2457270406 Jul 03 05:22:45 PM PDT 24 Jul 03 05:22:48 PM PDT 24 17183048 ps
T1108 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2738608977 Jul 03 05:22:50 PM PDT 24 Jul 03 05:22:52 PM PDT 24 44435130 ps
T1109 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2895411656 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:06 PM PDT 24 74388784 ps
T280 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4250033319 Jul 03 05:22:48 PM PDT 24 Jul 03 05:22:49 PM PDT 24 16980276 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.916645933 Jul 03 05:22:58 PM PDT 24 Jul 03 05:23:00 PM PDT 24 59818186 ps
T1111 /workspace/coverage/cover_reg_top/31.edn_intr_test.517963045 Jul 03 05:22:53 PM PDT 24 Jul 03 05:22:55 PM PDT 24 21475747 ps
T1112 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3438544614 Jul 03 05:22:41 PM PDT 24 Jul 03 05:22:42 PM PDT 24 24723777 ps
T1113 /workspace/coverage/cover_reg_top/9.edn_tl_errors.209245540 Jul 03 05:22:57 PM PDT 24 Jul 03 05:23:00 PM PDT 24 244934355 ps
T1114 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1918453650 Jul 03 05:22:50 PM PDT 24 Jul 03 05:22:57 PM PDT 24 343766360 ps
T1115 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3738324925 Jul 03 05:22:44 PM PDT 24 Jul 03 05:22:47 PM PDT 24 50845435 ps
T1116 /workspace/coverage/cover_reg_top/22.edn_intr_test.903779569 Jul 03 05:22:59 PM PDT 24 Jul 03 05:23:02 PM PDT 24 16781012 ps
T1117 /workspace/coverage/cover_reg_top/10.edn_intr_test.554243322 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 22810204 ps
T1118 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1122012239 Jul 03 05:22:47 PM PDT 24 Jul 03 05:22:49 PM PDT 24 18702152 ps
T1119 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.905588001 Jul 03 05:22:52 PM PDT 24 Jul 03 05:22:54 PM PDT 24 50281241 ps
T1120 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2084921202 Jul 03 05:22:54 PM PDT 24 Jul 03 05:22:55 PM PDT 24 15132813 ps
T1121 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2102092176 Jul 03 05:22:45 PM PDT 24 Jul 03 05:22:49 PM PDT 24 303558201 ps
T1122 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4015570014 Jul 03 05:23:00 PM PDT 24 Jul 03 05:23:02 PM PDT 24 26490097 ps
T1123 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2740621059 Jul 03 05:22:57 PM PDT 24 Jul 03 05:23:00 PM PDT 24 25586205 ps
T1124 /workspace/coverage/cover_reg_top/29.edn_intr_test.2538480657 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:05 PM PDT 24 49941747 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_tl_errors.492843616 Jul 03 05:23:02 PM PDT 24 Jul 03 05:23:08 PM PDT 24 479563321 ps
T1126 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1357124241 Jul 03 05:22:47 PM PDT 24 Jul 03 05:22:50 PM PDT 24 238981427 ps
T1127 /workspace/coverage/cover_reg_top/43.edn_intr_test.1218360158 Jul 03 05:23:01 PM PDT 24 Jul 03 05:23:04 PM PDT 24 15372796 ps
T1128 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2416967258 Jul 03 05:22:43 PM PDT 24 Jul 03 05:22:45 PM PDT 24 17297763 ps
T1129 /workspace/coverage/cover_reg_top/6.edn_intr_test.4141570669 Jul 03 05:22:50 PM PDT 24 Jul 03 05:22:51 PM PDT 24 38246744 ps

Test location /workspace/coverage/default/37.edn_genbits.1738805930
Short name T26
Test name
Test status
Simulation time 119080477 ps
CPU time 1.5 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 219072 kb
Host smart-e0bb6810-4469-4a72-bc37-adfc9f743d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738805930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1738805930
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3940096828
Short name T12
Test name
Test status
Simulation time 46942938 ps
CPU time 1.62 seconds
Started Jul 03 05:31:46 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 220424 kb
Host smart-d0cdc4e6-503a-4598-b2fd-838f638eee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940096828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3940096828
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2604458012
Short name T39
Test name
Test status
Simulation time 11744333966 ps
CPU time 156.87 seconds
Started Jul 03 05:30:29 PM PDT 24
Finished Jul 03 05:33:06 PM PDT 24
Peak memory 222548 kb
Host smart-59b40b4e-a096-41d2-8935-0e628bc79924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604458012 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2604458012
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_err.1796530901
Short name T5
Test name
Test status
Simulation time 29898572 ps
CPU time 1.39 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 226116 kb
Host smart-e11d5e66-6dc8-44fb-b2a5-1d9c9a244f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796530901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1796530901
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.374436426
Short name T17
Test name
Test status
Simulation time 1884980602 ps
CPU time 9.35 seconds
Started Jul 03 05:29:28 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 237788 kb
Host smart-c468731b-2274-4c7b-aaca-b3314db2c8f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374436426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.374436426
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/41.edn_alert.3082609174
Short name T32
Test name
Test status
Simulation time 83483204 ps
CPU time 1.19 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 220040 kb
Host smart-d209a8e7-5a5d-4e97-b7c6-bf961eecb1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082609174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3082609174
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2420913768
Short name T20
Test name
Test status
Simulation time 46501635 ps
CPU time 1.1 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 218856 kb
Host smart-52d65e29-e453-4f1c-93a0-7d031a9fa8d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420913768 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2420913768
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2996370044
Short name T209
Test name
Test status
Simulation time 53423751247 ps
CPU time 1205.73 seconds
Started Jul 03 05:29:38 PM PDT 24
Finished Jul 03 05:49:45 PM PDT 24
Peak memory 221292 kb
Host smart-77ba6d57-51a5-4620-bbd0-98aad154b821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996370044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2996370044
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.edn_alert.801327750
Short name T31
Test name
Test status
Simulation time 88026598 ps
CPU time 1.18 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 220360 kb
Host smart-a8e4d1a8-24da-46cb-9729-23c7463226a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801327750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.801327750
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/189.edn_alert.1480730505
Short name T50
Test name
Test status
Simulation time 92069050 ps
CPU time 1.37 seconds
Started Jul 03 05:31:40 PM PDT 24
Finished Jul 03 05:31:42 PM PDT 24
Peak memory 218772 kb
Host smart-2e12936e-5cdc-499c-8956-caf970579262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480730505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1480730505
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.1199308498
Short name T29
Test name
Test status
Simulation time 61005514 ps
CPU time 0.92 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 207388 kb
Host smart-daa064ff-a9fc-4fa3-9947-868ed41f8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199308498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1199308498
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_disable.940864462
Short name T25
Test name
Test status
Simulation time 10955579 ps
CPU time 0.91 seconds
Started Jul 03 05:29:33 PM PDT 24
Finished Jul 03 05:29:35 PM PDT 24
Peak memory 216600 kb
Host smart-b125b770-e91d-4726-a5d0-3b4025e67b7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940864462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.940864462
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/137.edn_alert.1138080185
Short name T112
Test name
Test status
Simulation time 41881970 ps
CPU time 1.22 seconds
Started Jul 03 05:31:27 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 219652 kb
Host smart-765437b1-2c58-47af-8f7f-1f9d21147335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138080185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1138080185
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1116492857
Short name T305
Test name
Test status
Simulation time 304231344 ps
CPU time 2.36 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:56 PM PDT 24
Peak memory 215124 kb
Host smart-51e9e061-7a6a-4f5d-ada8-7613c612df21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116492857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1116492857
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4070997042
Short name T267
Test name
Test status
Simulation time 38414518 ps
CPU time 0.85 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206884 kb
Host smart-a2346a73-5381-4d63-9b3f-6963e5d0aec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070997042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4070997042
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.746518348
Short name T225
Test name
Test status
Simulation time 42837218 ps
CPU time 1.38 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 217236 kb
Host smart-b98f1041-da94-4a55-a87a-dab7649b4010
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746518348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.746518348
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3175183565
Short name T155
Test name
Test status
Simulation time 37269961 ps
CPU time 1.22 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 217188 kb
Host smart-1e4e781f-3a43-4c0d-bcd2-57ea5c67da92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175183565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3175183565
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/81.edn_genbits.2888234883
Short name T24
Test name
Test status
Simulation time 46998123 ps
CPU time 1.19 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 217676 kb
Host smart-db6807d9-f01c-483c-b142-16785f98e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888234883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2888234883
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable.239435197
Short name T77
Test name
Test status
Simulation time 30295883 ps
CPU time 0.94 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 216496 kb
Host smart-f6d1ac60-4096-4cfd-a565-0e06dc013a81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239435197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.239435197
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.3342689286
Short name T175
Test name
Test status
Simulation time 90402105 ps
CPU time 0.86 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 216612 kb
Host smart-5ec470f6-f513-41bd-ba2f-59132024a893
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342689286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3342689286
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/164.edn_alert.809086130
Short name T230
Test name
Test status
Simulation time 30077918 ps
CPU time 1.27 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 216004 kb
Host smart-17d7768a-c81d-4e01-a899-f81ab767e2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809086130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.809086130
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.4174499577
Short name T156
Test name
Test status
Simulation time 72919237 ps
CPU time 1.19 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 219084 kb
Host smart-4a9f4ea9-2e7a-49d5-808c-72dc41a67728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174499577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.4174499577
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.779756505
Short name T351
Test name
Test status
Simulation time 64126141 ps
CPU time 1.14 seconds
Started Jul 03 05:31:35 PM PDT 24
Finished Jul 03 05:31:37 PM PDT 24
Peak memory 220772 kb
Host smart-d5bee423-e066-4e2d-9974-9946079e827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779756505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.779756505
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3462976037
Short name T10
Test name
Test status
Simulation time 66897460 ps
CPU time 1.38 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 220204 kb
Host smart-7f91c807-17cc-4ac7-ba68-2050a2f5752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462976037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3462976037
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.181739962
Short name T237
Test name
Test status
Simulation time 36815390280 ps
CPU time 771.37 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 218376 kb
Host smart-5de5e8b6-10ed-4740-bd74-e5ab3d0abd40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181739962 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.181739962
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.2931002935
Short name T43
Test name
Test status
Simulation time 37124827 ps
CPU time 1.03 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 218660 kb
Host smart-5f64bbbc-f3e5-479d-860b-2522254fd216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931002935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2931002935
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.1115107533
Short name T514
Test name
Test status
Simulation time 130407449 ps
CPU time 1.29 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220852 kb
Host smart-4bb86431-123e-48f0-ac9b-75ee21b84ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115107533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1115107533
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/51.edn_alert.2374205878
Short name T702
Test name
Test status
Simulation time 37164441 ps
CPU time 1.12 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 220528 kb
Host smart-76a9f9c3-f7e7-46d2-959e-06cbd2f31153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374205878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2374205878
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.3243322041
Short name T853
Test name
Test status
Simulation time 115959896 ps
CPU time 1.36 seconds
Started Jul 03 05:31:46 PM PDT 24
Finished Jul 03 05:31:48 PM PDT 24
Peak memory 220500 kb
Host smart-62412819-e8b1-477a-8f37-2b6ac3efd032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243322041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3243322041
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert.3504329431
Short name T151
Test name
Test status
Simulation time 84634909 ps
CPU time 1.26 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 218740 kb
Host smart-91e0a460-b94c-465a-9630-18cefadfd269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504329431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3504329431
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/25.edn_intr.1592360125
Short name T33
Test name
Test status
Simulation time 53723829 ps
CPU time 0.95 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 216140 kb
Host smart-959284a7-4f2b-4c51-90ee-4ea046b7003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592360125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1592360125
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.612962552
Short name T1
Test name
Test status
Simulation time 17368871 ps
CPU time 0.96 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 217232 kb
Host smart-1b6ca28c-5f67-46ea-99fd-fae95388b0c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612962552 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.612962552
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/178.edn_alert.3364998744
Short name T97
Test name
Test status
Simulation time 56576075 ps
CPU time 1.21 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 221168 kb
Host smart-d91aee5c-f0cb-43b5-8cad-4784b82e04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364998744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3364998744
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/4.edn_genbits.3085782793
Short name T314
Test name
Test status
Simulation time 81332044 ps
CPU time 1.2 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 217728 kb
Host smart-6db1c91e-5a5a-4b5d-be57-e844b5588266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085782793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3085782793
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_disable.1157557502
Short name T86
Test name
Test status
Simulation time 23423963 ps
CPU time 0.9 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 215852 kb
Host smart-4c7ce2df-aa86-4ebe-a024-4e6a4c4abe16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157557502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1157557502
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.4249033180
Short name T220
Test name
Test status
Simulation time 16283393 ps
CPU time 0.82 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 216616 kb
Host smart-d01710fe-10d3-4785-a254-46fd5ef883fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249033180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4249033180
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/20.edn_intr.777627277
Short name T36
Test name
Test status
Simulation time 28454273 ps
CPU time 1.01 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 216080 kb
Host smart-5ec8320d-b8ac-4287-9c16-ee6355340a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777627277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.777627277
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/10.edn_alert.1996732116
Short name T261
Test name
Test status
Simulation time 102660027 ps
CPU time 1.28 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 220084 kb
Host smart-43887419-9e2f-4258-8fbe-523bb625653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996732116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1996732116
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/13.edn_err.3682660078
Short name T195
Test name
Test status
Simulation time 24439071 ps
CPU time 0.94 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 218856 kb
Host smart-643852a5-cbdf-49b4-bd91-35132d9e73e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682660078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3682660078
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.1857128449
Short name T4
Test name
Test status
Simulation time 20933436 ps
CPU time 1.05 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 215644 kb
Host smart-c5d2789c-265d-4d2c-9901-6c3db8bc3b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857128449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1857128449
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/14.edn_disable.375196228
Short name T215
Test name
Test status
Simulation time 13658035 ps
CPU time 0.93 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 216884 kb
Host smart-963481e6-e682-47cb-ad9e-c7db427336a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375196228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.375196228
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/149.edn_alert.513757768
Short name T908
Test name
Test status
Simulation time 273754618 ps
CPU time 1.09 seconds
Started Jul 03 05:31:22 PM PDT 24
Finished Jul 03 05:31:23 PM PDT 24
Peak memory 219920 kb
Host smart-e38d5970-2767-47e6-a170-5215edf05261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513757768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.513757768
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.1288263042
Short name T179
Test name
Test status
Simulation time 36034037 ps
CPU time 0.89 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 216612 kb
Host smart-7e187065-3ce9-4191-8e10-adf445aa283c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288263042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1288263042
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.726548062
Short name T134
Test name
Test status
Simulation time 86834166 ps
CPU time 1.06 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 217108 kb
Host smart-279972be-1103-4020-9e63-41a28cb69ad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726548062 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.726548062
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/186.edn_alert.99475847
Short name T191
Test name
Test status
Simulation time 140308449 ps
CPU time 1.28 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 220404 kb
Host smart-8f95bede-0297-449f-b3b4-f5538f199ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99475847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.99475847
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable.2959456019
Short name T212
Test name
Test status
Simulation time 11943469 ps
CPU time 0.9 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 216648 kb
Host smart-b0d231a8-6c20-4515-a2db-15899663966c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959456019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2959456019
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.966402256
Short name T159
Test name
Test status
Simulation time 49471385 ps
CPU time 1.13 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 217076 kb
Host smart-2498bacb-ce36-43dc-bfde-f62b62a4c28d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966402256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.966402256
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1514706594
Short name T199
Test name
Test status
Simulation time 23012537 ps
CPU time 0.96 seconds
Started Jul 03 05:30:15 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 219780 kb
Host smart-f3480370-93a3-4a5f-9913-745d1226514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514706594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1514706594
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/27.edn_err.974587941
Short name T186
Test name
Test status
Simulation time 22626944 ps
CPU time 0.93 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 218660 kb
Host smart-152811d5-89eb-4bea-89ea-481a3d501a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974587941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.974587941
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/36.edn_disable.996164491
Short name T88
Test name
Test status
Simulation time 11631669 ps
CPU time 0.86 seconds
Started Jul 03 05:30:37 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 216600 kb
Host smart-c5b769e5-09aa-4ef4-bd87-1ca19e366499
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996164491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.996164491
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable.1156435388
Short name T221
Test name
Test status
Simulation time 13941541 ps
CPU time 0.92 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 216780 kb
Host smart-98acc6dc-c358-42af-b360-bce8925d307c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156435388 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1156435388
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.824972221
Short name T224
Test name
Test status
Simulation time 27234325 ps
CPU time 0.81 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 216548 kb
Host smart-e7e8f239-365d-401f-a0a8-a89aa628df9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824972221 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.824972221
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.3410837751
Short name T208
Test name
Test status
Simulation time 14350110 ps
CPU time 0.97 seconds
Started Jul 03 05:29:36 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 216800 kb
Host smart-e264b2b8-9a58-4129-8915-5c0900b9a1cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410837751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3410837751
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/80.edn_genbits.1102088456
Short name T47
Test name
Test status
Simulation time 77654163 ps
CPU time 1.03 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 217612 kb
Host smart-805b308d-eebc-4e2e-99dd-5aec606e8760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102088456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1102088456
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.3335312512
Short name T393
Test name
Test status
Simulation time 76338750 ps
CPU time 1.23 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 215280 kb
Host smart-c25d8920-0d6a-4fe6-8439-41f4ac2ebfb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335312512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3335312512
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/139.edn_genbits.3117270556
Short name T339
Test name
Test status
Simulation time 41535176 ps
CPU time 1.44 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220240 kb
Host smart-fb4efb56-bad6-4650-80f0-8a0d01d8e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117270556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3117270556
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3461514581
Short name T316
Test name
Test status
Simulation time 238792353 ps
CPU time 1.79 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 219228 kb
Host smart-0b24738f-ebeb-48cd-a6f1-935274e9db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461514581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3461514581
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.552787215
Short name T104
Test name
Test status
Simulation time 74804400542 ps
CPU time 1720.99 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:58:49 PM PDT 24
Peak memory 225236 kb
Host smart-eee73be1-fa11-4b23-a805-ecde875509d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552787215 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.552787215
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_intr.2049552486
Short name T96
Test name
Test status
Simulation time 30877044 ps
CPU time 0.84 seconds
Started Jul 03 05:29:32 PM PDT 24
Finished Jul 03 05:29:33 PM PDT 24
Peak memory 215876 kb
Host smart-f72f3054-870d-4a1c-8001-93c058a7cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049552486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2049552486
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/216.edn_genbits.1130867618
Short name T87
Test name
Test status
Simulation time 34943020 ps
CPU time 1.48 seconds
Started Jul 03 05:31:32 PM PDT 24
Finished Jul 03 05:31:34 PM PDT 24
Peak memory 217892 kb
Host smart-86880a42-f933-41b0-b67f-74a13d2d2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130867618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1130867618
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2457270406
Short name T279
Test name
Test status
Simulation time 17183048 ps
CPU time 0.99 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:48 PM PDT 24
Peak memory 206560 kb
Host smart-ee115119-5851-4193-b20f-e2c3fbf5e0fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457270406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2457270406
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2102092176
Short name T1121
Test name
Test status
Simulation time 303558201 ps
CPU time 2.17 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:49 PM PDT 24
Peak memory 206700 kb
Host smart-514131b1-745c-4c98-94ce-7049b98fffa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102092176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2102092176
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_err.95594878
Short name T127
Test name
Test status
Simulation time 24557383 ps
CPU time 1.18 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 219868 kb
Host smart-3a6e952a-a427-4dbc-bbed-fa32c60091d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95594878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.95594878
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/106.edn_genbits.2697834504
Short name T335
Test name
Test status
Simulation time 91473938 ps
CPU time 2 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 219704 kb
Host smart-d2a3fd5d-349b-4740-83bc-b8b3cae4c32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697834504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2697834504
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2062528208
Short name T321
Test name
Test status
Simulation time 182854371 ps
CPU time 1.3 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 219008 kb
Host smart-7433295e-ae06-4ac0-be99-17e4bbae42d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062528208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2062528208
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1728121464
Short name T873
Test name
Test status
Simulation time 75463746 ps
CPU time 1.37 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 218648 kb
Host smart-636c30c4-48ec-4309-85e9-8a41e21182b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728121464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1728121464
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1094018071
Short name T772
Test name
Test status
Simulation time 54723678 ps
CPU time 1.1 seconds
Started Jul 03 05:31:10 PM PDT 24
Finished Jul 03 05:31:12 PM PDT 24
Peak memory 219400 kb
Host smart-a07581fa-6417-492d-8068-5758f51224c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094018071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1094018071
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.147448026
Short name T326
Test name
Test status
Simulation time 117193420 ps
CPU time 1.74 seconds
Started Jul 03 05:30:03 PM PDT 24
Finished Jul 03 05:30:05 PM PDT 24
Peak memory 219020 kb
Host smart-03c2e65a-e479-455c-93c3-5c44434b8df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147448026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.147448026
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2113739117
Short name T329
Test name
Test status
Simulation time 47223231 ps
CPU time 1.58 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 220292 kb
Host smart-03ee16c9-941b-4cec-b8bb-975bc40e77b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113739117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2113739117
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3795951185
Short name T320
Test name
Test status
Simulation time 86328018 ps
CPU time 2.31 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:36 PM PDT 24
Peak memory 218240 kb
Host smart-307bf91e-6989-4674-8288-73dda4113086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795951185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3795951185
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2939251226
Short name T291
Test name
Test status
Simulation time 38717594 ps
CPU time 1.31 seconds
Started Jul 03 05:29:34 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 217220 kb
Host smart-d137fed8-d86d-40a0-97c3-7965680647a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939251226 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2939251226
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_intr.1319925367
Short name T38
Test name
Test status
Simulation time 22734484 ps
CPU time 0.96 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 216104 kb
Host smart-ab3080cb-fbd8-4492-bea8-7f6d55f55ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319925367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1319925367
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/147.edn_alert.3396058906
Short name T115
Test name
Test status
Simulation time 26355345 ps
CPU time 1.21 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 220960 kb
Host smart-cc74b1fc-37aa-422f-b9ea-de73c918963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396058906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3396058906
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.46242993
Short name T143
Test name
Test status
Simulation time 28970526 ps
CPU time 1.3 seconds
Started Jul 03 05:29:27 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 229912 kb
Host smart-7f0aacd2-65a8-472e-9865-0afda5958719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46242993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.46242993
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/128.edn_genbits.787574553
Short name T556
Test name
Test status
Simulation time 50270108 ps
CPU time 1.69 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 218960 kb
Host smart-1a4a3c22-2a33-4e8b-a68e-9f70f18687a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787574553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.787574553
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2460703451
Short name T274
Test name
Test status
Simulation time 35096762 ps
CPU time 1.47 seconds
Started Jul 03 05:22:40 PM PDT 24
Finished Jul 03 05:22:42 PM PDT 24
Peak memory 206900 kb
Host smart-6dbd07a1-e79e-4a3f-bd0c-f4cb29d4df31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460703451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2460703451
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3474059799
Short name T262
Test name
Test status
Simulation time 251180018 ps
CPU time 6.21 seconds
Started Jul 03 05:22:46 PM PDT 24
Finished Jul 03 05:22:53 PM PDT 24
Peak memory 206952 kb
Host smart-2629530a-8f65-4807-be3e-bac2731b1923
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474059799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3474059799
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2738608977
Short name T1108
Test name
Test status
Simulation time 44435130 ps
CPU time 0.89 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:52 PM PDT 24
Peak memory 206928 kb
Host smart-e0ed9b70-cf21-474a-abbd-c13a3605516d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738608977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2738608977
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3945454391
Short name T1095
Test name
Test status
Simulation time 277067630 ps
CPU time 2.05 seconds
Started Jul 03 05:22:49 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 215200 kb
Host smart-af830b18-03bc-4266-af1f-920ebcf201fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945454391 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3945454391
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.469928453
Short name T1024
Test name
Test status
Simulation time 30872577 ps
CPU time 0.76 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206612 kb
Host smart-adf290e1-cc8c-41eb-aab6-019972e36a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469928453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.469928453
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3887078577
Short name T1037
Test name
Test status
Simulation time 29743635 ps
CPU time 1.36 seconds
Started Jul 03 05:22:41 PM PDT 24
Finished Jul 03 05:22:43 PM PDT 24
Peak memory 206956 kb
Host smart-1f7470e5-1b09-4594-b0f5-d6e0d21847ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887078577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3887078577
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2093068182
Short name T1015
Test name
Test status
Simulation time 173313599 ps
CPU time 3.62 seconds
Started Jul 03 05:22:39 PM PDT 24
Finished Jul 03 05:22:43 PM PDT 24
Peak memory 223404 kb
Host smart-c1f0bf51-7086-4e5e-a82e-9941f95447d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093068182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2093068182
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2529638356
Short name T270
Test name
Test status
Simulation time 36907587 ps
CPU time 1.56 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:48 PM PDT 24
Peak memory 206848 kb
Host smart-36059539-e1c5-4097-9adc-e1b84106948b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529638356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2529638356
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1316617514
Short name T1044
Test name
Test status
Simulation time 187513028 ps
CPU time 2.98 seconds
Started Jul 03 05:22:48 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206932 kb
Host smart-feb37b72-18ce-48d8-a69a-af22d4a1f0d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316617514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1316617514
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3738324925
Short name T1115
Test name
Test status
Simulation time 50845435 ps
CPU time 0.9 seconds
Started Jul 03 05:22:44 PM PDT 24
Finished Jul 03 05:22:47 PM PDT 24
Peak memory 206932 kb
Host smart-6211560c-76fc-478a-902b-1a835bfa5de2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738324925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3738324925
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3718030237
Short name T1069
Test name
Test status
Simulation time 38283032 ps
CPU time 1.09 seconds
Started Jul 03 05:22:35 PM PDT 24
Finished Jul 03 05:22:36 PM PDT 24
Peak memory 215228 kb
Host smart-9429bf44-db2f-4a7e-b42d-abc07e607b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718030237 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3718030237
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.239584230
Short name T1090
Test name
Test status
Simulation time 20723621 ps
CPU time 0.82 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:47 PM PDT 24
Peak memory 206836 kb
Host smart-77417338-8fdb-46af-9b01-0f918bffce99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239584230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.239584230
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.329846207
Short name T1041
Test name
Test status
Simulation time 37529289 ps
CPU time 0.77 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:04 PM PDT 24
Peak memory 206648 kb
Host smart-114dced1-c2d6-4a8b-9d5c-afecd40d4639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329846207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.329846207
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3438544614
Short name T1112
Test name
Test status
Simulation time 24723777 ps
CPU time 1.11 seconds
Started Jul 03 05:22:41 PM PDT 24
Finished Jul 03 05:22:42 PM PDT 24
Peak memory 206984 kb
Host smart-2f86f855-21cf-4b44-8081-2e0b561f656d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438544614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3438544614
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1357124241
Short name T1126
Test name
Test status
Simulation time 238981427 ps
CPU time 2.83 seconds
Started Jul 03 05:22:47 PM PDT 24
Finished Jul 03 05:22:50 PM PDT 24
Peak memory 215212 kb
Host smart-f05b0ace-62f3-42e7-8274-b9e24f0eb24f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357124241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1357124241
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2923120356
Short name T307
Test name
Test status
Simulation time 161968932 ps
CPU time 1.58 seconds
Started Jul 03 05:22:38 PM PDT 24
Finished Jul 03 05:22:40 PM PDT 24
Peak memory 207032 kb
Host smart-c9c19af6-7ce6-4043-b34d-b27396974bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923120356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2923120356
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1048039794
Short name T1031
Test name
Test status
Simulation time 79585610 ps
CPU time 1.16 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 215292 kb
Host smart-ed221004-b65b-4770-bf0a-b5de465a6846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048039794 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1048039794
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.219506753
Short name T1088
Test name
Test status
Simulation time 45829185 ps
CPU time 0.88 seconds
Started Jul 03 05:23:05 PM PDT 24
Finished Jul 03 05:23:07 PM PDT 24
Peak memory 206944 kb
Host smart-bba80aed-ace7-40be-aed6-ae6899326f95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219506753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.219506753
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.554243322
Short name T1117
Test name
Test status
Simulation time 22810204 ps
CPU time 0.82 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206796 kb
Host smart-d85119f0-a778-43e0-9c33-dbaa97a04928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554243322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.554243322
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1404308073
Short name T285
Test name
Test status
Simulation time 131214920 ps
CPU time 1.13 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 207040 kb
Host smart-18a3a3f5-b49f-47cb-9f7a-0ebd8d842dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404308073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1404308073
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2353852211
Short name T1099
Test name
Test status
Simulation time 29578031 ps
CPU time 1.99 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:49 PM PDT 24
Peak memory 215132 kb
Host smart-3975a93b-2d4b-4597-b947-244a84c135db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353852211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2353852211
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3603801984
Short name T1052
Test name
Test status
Simulation time 619391566 ps
CPU time 5.21 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 215116 kb
Host smart-196fc655-76f1-43e9-8039-09a1d2bd1410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603801984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3603801984
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2740621059
Short name T1123
Test name
Test status
Simulation time 25586205 ps
CPU time 1.19 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 215176 kb
Host smart-98b6ca4e-4235-467d-ab3f-d72b9ffc2fb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740621059 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2740621059
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1122012239
Short name T1118
Test name
Test status
Simulation time 18702152 ps
CPU time 0.82 seconds
Started Jul 03 05:22:47 PM PDT 24
Finished Jul 03 05:22:49 PM PDT 24
Peak memory 206720 kb
Host smart-a9a5d7df-84fe-4afb-9c68-9834d00a096e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122012239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1122012239
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2454656688
Short name T1059
Test name
Test status
Simulation time 20950941 ps
CPU time 0.87 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206808 kb
Host smart-b65d9361-2a9e-4319-ba95-4e356c059a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454656688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2454656688
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4036217210
Short name T1042
Test name
Test status
Simulation time 36262556 ps
CPU time 1.15 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206908 kb
Host smart-56f357e3-10f3-425c-a782-a69020866571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036217210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4036217210
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3440913738
Short name T1104
Test name
Test status
Simulation time 108851163 ps
CPU time 1.55 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 215188 kb
Host smart-99475e8e-2db6-415e-85dc-06785e1e08e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440913738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3440913738
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1474533560
Short name T1086
Test name
Test status
Simulation time 308263354 ps
CPU time 2.37 seconds
Started Jul 03 05:22:55 PM PDT 24
Finished Jul 03 05:22:58 PM PDT 24
Peak memory 206852 kb
Host smart-53ec4fa0-0283-4750-8f54-ef45a075607d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474533560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1474533560
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1168217034
Short name T1036
Test name
Test status
Simulation time 120125383 ps
CPU time 1.15 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 215176 kb
Host smart-2cccf003-9d39-46a3-a9e6-a8caf917fcdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168217034 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1168217034
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2050664614
Short name T1046
Test name
Test status
Simulation time 13820804 ps
CPU time 0.91 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206836 kb
Host smart-41112eed-29a8-4d48-b934-15d75f663d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050664614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2050664614
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.515510867
Short name T282
Test name
Test status
Simulation time 147136044 ps
CPU time 1.43 seconds
Started Jul 03 05:23:09 PM PDT 24
Finished Jul 03 05:23:11 PM PDT 24
Peak memory 206960 kb
Host smart-af1a24a0-26c7-4fa7-8a1c-a87e45be5c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515510867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.515510867
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3951287115
Short name T1074
Test name
Test status
Simulation time 287239923 ps
CPU time 2.65 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 215192 kb
Host smart-c8bcf169-d6d5-4cd9-b8b5-164f447c8ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951287115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3951287115
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2832643966
Short name T1080
Test name
Test status
Simulation time 64506200 ps
CPU time 1.88 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:56 PM PDT 24
Peak memory 206876 kb
Host smart-de857a4d-879b-48ae-8a03-d4ca347450d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832643966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2832643966
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.605494030
Short name T1019
Test name
Test status
Simulation time 71504192 ps
CPU time 1.4 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:58 PM PDT 24
Peak memory 215188 kb
Host smart-66aabbe4-2853-43d1-bda1-1562988bc3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605494030 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.605494030
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1103023489
Short name T273
Test name
Test status
Simulation time 18590262 ps
CPU time 1 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 206900 kb
Host smart-c1aabc74-b37c-40a7-bd64-3ceb65be62e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103023489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1103023489
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3202036952
Short name T1002
Test name
Test status
Simulation time 128963836 ps
CPU time 0.83 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:52 PM PDT 24
Peak memory 206608 kb
Host smart-438a730e-3a60-4fdd-988f-3c9af043f8d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202036952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3202036952
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4000171421
Short name T1076
Test name
Test status
Simulation time 26009549 ps
CPU time 0.98 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 206936 kb
Host smart-662ada53-59fa-4733-8da8-83855af661b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000171421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4000171421
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1471308800
Short name T1083
Test name
Test status
Simulation time 131417603 ps
CPU time 4.49 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 215300 kb
Host smart-9b418c51-ce47-41f0-8e56-e23836048d08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471308800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1471308800
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3629669316
Short name T296
Test name
Test status
Simulation time 134549507 ps
CPU time 2.09 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206888 kb
Host smart-11da93cd-46bb-42c5-8619-62dc4337fc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629669316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3629669316
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1431899750
Short name T1028
Test name
Test status
Simulation time 30457566 ps
CPU time 1.24 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:03 PM PDT 24
Peak memory 215228 kb
Host smart-be3d1fdf-24b2-47db-b667-d3f6d73ef489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431899750 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1431899750
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3921490512
Short name T1049
Test name
Test status
Simulation time 26298006 ps
CPU time 0.88 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206968 kb
Host smart-fcbeada9-7248-471d-bdfc-7892812605a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921490512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3921490512
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1832421951
Short name T1011
Test name
Test status
Simulation time 15566549 ps
CPU time 0.93 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 206920 kb
Host smart-1375e14d-9e78-4c8b-ba2f-df2bfb63ea0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832421951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1832421951
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.599025230
Short name T1071
Test name
Test status
Simulation time 69038574 ps
CPU time 0.94 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 206980 kb
Host smart-5bce1299-435b-481b-ae97-4ba59f0e62cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599025230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.599025230
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.61762124
Short name T1062
Test name
Test status
Simulation time 47454078 ps
CPU time 3.29 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 223356 kb
Host smart-f3a2d85b-c97a-4529-95c5-2c3011aae32f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61762124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.61762124
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1834417658
Short name T306
Test name
Test status
Simulation time 287169156 ps
CPU time 2.36 seconds
Started Jul 03 05:23:03 PM PDT 24
Finished Jul 03 05:23:07 PM PDT 24
Peak memory 207012 kb
Host smart-17f29d49-6ad7-497c-a95b-c9544c6689f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834417658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1834417658
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4015570014
Short name T1122
Test name
Test status
Simulation time 26490097 ps
CPU time 1.23 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 215276 kb
Host smart-b2e5cc79-ae05-41ec-83b9-73e15ba85f63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015570014 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4015570014
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2982845953
Short name T278
Test name
Test status
Simulation time 19197249 ps
CPU time 0.85 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206872 kb
Host smart-9a9399ba-ff1a-4f51-9c85-c9d962286107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982845953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2982845953
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3604967065
Short name T1034
Test name
Test status
Simulation time 20315331 ps
CPU time 0.83 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206648 kb
Host smart-1b1ea5fe-1d16-459e-a7f4-e72eb2a17c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604967065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3604967065
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1040740609
Short name T263
Test name
Test status
Simulation time 38119492 ps
CPU time 1.17 seconds
Started Jul 03 05:23:05 PM PDT 24
Finished Jul 03 05:23:08 PM PDT 24
Peak memory 206936 kb
Host smart-2057b7af-ad0c-4e91-9c29-0124fbed5ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040740609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1040740609
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2413155853
Short name T1018
Test name
Test status
Simulation time 118423608 ps
CPU time 3.65 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 215236 kb
Host smart-0d7343fb-0f70-462d-8f76-059f5cf095e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413155853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2413155853
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1331733996
Short name T303
Test name
Test status
Simulation time 320366596 ps
CPU time 2.4 seconds
Started Jul 03 05:23:09 PM PDT 24
Finished Jul 03 05:23:12 PM PDT 24
Peak memory 215128 kb
Host smart-741bbc17-b980-45a3-b776-fb5446eaf65f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331733996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1331733996
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3196620763
Short name T1050
Test name
Test status
Simulation time 27591131 ps
CPU time 1.05 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 215176 kb
Host smart-033c037c-3e19-426d-a46b-55427fffe315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196620763 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3196620763
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3707314092
Short name T276
Test name
Test status
Simulation time 41170918 ps
CPU time 0.85 seconds
Started Jul 03 05:23:07 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 206988 kb
Host smart-704174a1-a5e8-4c9c-8d89-c06fd646ceaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707314092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3707314092
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3404686449
Short name T1072
Test name
Test status
Simulation time 13075493 ps
CPU time 0.84 seconds
Started Jul 03 05:23:04 PM PDT 24
Finished Jul 03 05:23:07 PM PDT 24
Peak memory 206816 kb
Host smart-82501bad-68f4-4e5b-8fb3-19545bd1212a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404686449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3404686449
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2754610
Short name T266
Test name
Test status
Simulation time 24518328 ps
CPU time 1.11 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 206920 kb
Host smart-7132e69a-ad4b-4682-9051-f2de26a25332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outs
tanding.2754610
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1068938923
Short name T1081
Test name
Test status
Simulation time 227202640 ps
CPU time 4.68 seconds
Started Jul 03 05:23:09 PM PDT 24
Finished Jul 03 05:23:14 PM PDT 24
Peak memory 215216 kb
Host smart-0d672532-7460-4055-9e9f-21a027b95188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068938923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1068938923
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.114958631
Short name T1084
Test name
Test status
Simulation time 148421701 ps
CPU time 2.22 seconds
Started Jul 03 05:22:54 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 206920 kb
Host smart-9a65eb5d-4336-4676-bf30-870c1c132b11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114958631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.114958631
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.530161319
Short name T1008
Test name
Test status
Simulation time 204591503 ps
CPU time 1.23 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 215256 kb
Host smart-07c7ac3b-05e1-4608-bb04-0b5243e74937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530161319 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.530161319
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.564283177
Short name T1054
Test name
Test status
Simulation time 167496561 ps
CPU time 0.88 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206900 kb
Host smart-3dd122a7-ec80-4d21-b093-c04a2799761c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564283177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.564283177
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.87249716
Short name T1027
Test name
Test status
Simulation time 12433137 ps
CPU time 0.87 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 206872 kb
Host smart-1e1bc42f-1c80-49ee-a175-2174257826cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87249716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.87249716
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2429613739
Short name T284
Test name
Test status
Simulation time 32223233 ps
CPU time 1.44 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206964 kb
Host smart-d233f9eb-b48b-4122-a9ae-08fc5d7d577e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429613739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2429613739
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1418985944
Short name T1053
Test name
Test status
Simulation time 169361442 ps
CPU time 2.86 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 215240 kb
Host smart-d846660c-f5eb-4158-a7a0-ad8b620eba04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418985944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1418985944
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2981232662
Short name T1094
Test name
Test status
Simulation time 210641146 ps
CPU time 4.12 seconds
Started Jul 03 05:23:05 PM PDT 24
Finished Jul 03 05:23:11 PM PDT 24
Peak memory 215836 kb
Host smart-f1e26e11-a0b0-4cfb-9d77-417556d8a358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981232662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2981232662
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.632709654
Short name T1026
Test name
Test status
Simulation time 34605003 ps
CPU time 1.33 seconds
Started Jul 03 05:22:49 PM PDT 24
Finished Jul 03 05:22:50 PM PDT 24
Peak memory 215176 kb
Host smart-594e0700-fb71-4153-b757-b9287d51ee73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632709654 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.632709654
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.17967104
Short name T277
Test name
Test status
Simulation time 15378748 ps
CPU time 0.94 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206960 kb
Host smart-c3de79fd-89c3-4e4b-b884-8934f4cdb8d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17967104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.17967104
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.405179913
Short name T1064
Test name
Test status
Simulation time 67947453 ps
CPU time 0.81 seconds
Started Jul 03 05:23:10 PM PDT 24
Finished Jul 03 05:23:12 PM PDT 24
Peak memory 206632 kb
Host smart-0e9119bd-7768-4106-929d-b0a9b03cb85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405179913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.405179913
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2895411656
Short name T1109
Test name
Test status
Simulation time 74388784 ps
CPU time 1.54 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 206912 kb
Host smart-66051f35-205d-4330-9894-d2ae9fcf6dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895411656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2895411656
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3802546765
Short name T1025
Test name
Test status
Simulation time 46019542 ps
CPU time 2.99 seconds
Started Jul 03 05:23:05 PM PDT 24
Finished Jul 03 05:23:10 PM PDT 24
Peak memory 215176 kb
Host smart-efc50797-56d4-41b5-a243-f95880a3ce4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802546765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3802546765
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.347520140
Short name T309
Test name
Test status
Simulation time 268418406 ps
CPU time 2.17 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 207004 kb
Host smart-eadd9268-f0a6-4de0-b0db-7ec8561eb69f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347520140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.347520140
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3224258884
Short name T1035
Test name
Test status
Simulation time 50843720 ps
CPU time 0.96 seconds
Started Jul 03 05:23:07 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 206956 kb
Host smart-b3018f1b-480f-4778-8e7f-c57213a1ca31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224258884 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3224258884
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2927663045
Short name T265
Test name
Test status
Simulation time 20142647 ps
CPU time 0.86 seconds
Started Jul 03 05:22:49 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206700 kb
Host smart-31ab1b43-ff66-4229-a82d-c8bacd159727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927663045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2927663045
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2412229624
Short name T1092
Test name
Test status
Simulation time 21375055 ps
CPU time 0.91 seconds
Started Jul 03 05:23:37 PM PDT 24
Finished Jul 03 05:23:39 PM PDT 24
Peak memory 206924 kb
Host smart-bbac3dc6-a0ef-4b85-b495-4b6f1e2476e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412229624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2412229624
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3054617490
Short name T1079
Test name
Test status
Simulation time 207951759 ps
CPU time 1.41 seconds
Started Jul 03 05:23:07 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 206860 kb
Host smart-992345e3-d5a7-4eca-bc8e-d8952ed6293e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054617490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3054617490
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1025352558
Short name T1033
Test name
Test status
Simulation time 25646256 ps
CPU time 1.4 seconds
Started Jul 03 05:22:49 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 215160 kb
Host smart-1179e762-5329-4b45-94e4-903847cf471b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025352558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1025352558
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2250034644
Short name T304
Test name
Test status
Simulation time 94787106 ps
CPU time 2.63 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 207008 kb
Host smart-32748782-7536-40aa-9a5d-b2767e83b659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250034644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2250034644
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2079822359
Short name T1006
Test name
Test status
Simulation time 27730786 ps
CPU time 1.02 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 207024 kb
Host smart-6a059834-c354-47ce-a315-61d5edfb877a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079822359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2079822359
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1918453650
Short name T1114
Test name
Test status
Simulation time 343766360 ps
CPU time 5.92 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 206860 kb
Host smart-efaa2e84-6c41-4643-931e-7dad452fc81e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918453650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1918453650
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4250033319
Short name T280
Test name
Test status
Simulation time 16980276 ps
CPU time 1.01 seconds
Started Jul 03 05:22:48 PM PDT 24
Finished Jul 03 05:22:49 PM PDT 24
Peak memory 206872 kb
Host smart-8dec5ec1-daf1-4f81-9418-0a2dcf0ba8f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250033319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4250033319
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.682651876
Short name T1022
Test name
Test status
Simulation time 30248199 ps
CPU time 1.2 seconds
Started Jul 03 05:22:55 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 215240 kb
Host smart-311cf3b0-63b0-486f-bbc2-2408d4d0d4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682651876 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.682651876
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3215410515
Short name T1089
Test name
Test status
Simulation time 17723915 ps
CPU time 0.86 seconds
Started Jul 03 05:22:44 PM PDT 24
Finished Jul 03 05:22:46 PM PDT 24
Peak memory 206824 kb
Host smart-822fb841-ea33-41b0-bff6-f0d3b9683294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215410515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3215410515
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1290734
Short name T1007
Test name
Test status
Simulation time 17246877 ps
CPU time 0.94 seconds
Started Jul 03 05:22:40 PM PDT 24
Finished Jul 03 05:22:42 PM PDT 24
Peak memory 206896 kb
Host smart-a82887e3-af74-44b6-a810-9275fb2c084c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1290734
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4199009521
Short name T287
Test name
Test status
Simulation time 73730497 ps
CPU time 1.04 seconds
Started Jul 03 05:22:44 PM PDT 24
Finished Jul 03 05:22:47 PM PDT 24
Peak memory 206984 kb
Host smart-10594178-b517-485a-8bac-1f26ec3266c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199009521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4199009521
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1214887529
Short name T1001
Test name
Test status
Simulation time 456980729 ps
CPU time 2.09 seconds
Started Jul 03 05:22:42 PM PDT 24
Finished Jul 03 05:22:45 PM PDT 24
Peak memory 215204 kb
Host smart-3675dd0c-f3da-4149-b736-ab690354a7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214887529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1214887529
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.804911314
Short name T1102
Test name
Test status
Simulation time 76832249 ps
CPU time 1.65 seconds
Started Jul 03 05:22:41 PM PDT 24
Finished Jul 03 05:22:43 PM PDT 24
Peak memory 215056 kb
Host smart-0a1d66dc-752e-4cee-ab77-d6f9af9f6355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804911314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.804911314
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3569549731
Short name T1048
Test name
Test status
Simulation time 26841161 ps
CPU time 0.93 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206832 kb
Host smart-03b3ccda-b532-4c2d-8e5b-805b41a6fae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569549731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3569549731
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2652619909
Short name T1032
Test name
Test status
Simulation time 45247212 ps
CPU time 0.82 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:01 PM PDT 24
Peak memory 206812 kb
Host smart-4ee0e868-0cb1-4f58-a01b-d116c63a62ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652619909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2652619909
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.903779569
Short name T1116
Test name
Test status
Simulation time 16781012 ps
CPU time 0.95 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206908 kb
Host smart-cf144930-116b-4bd8-9134-8135185b56e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903779569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.903779569
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3419811233
Short name T1003
Test name
Test status
Simulation time 31820714 ps
CPU time 0.88 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:58 PM PDT 24
Peak memory 206836 kb
Host smart-5753f84a-c795-424f-a697-7d0af9b4e711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419811233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3419811233
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3246208370
Short name T1106
Test name
Test status
Simulation time 31611931 ps
CPU time 0.79 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:04 PM PDT 24
Peak memory 206680 kb
Host smart-c6a5458d-86db-4f7a-8660-7843de296fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246208370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3246208370
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3781890154
Short name T1103
Test name
Test status
Simulation time 45843143 ps
CPU time 0.85 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:04 PM PDT 24
Peak memory 206856 kb
Host smart-829a3d3d-9789-4511-8d86-17a62ede4c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781890154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3781890154
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1502264684
Short name T1068
Test name
Test status
Simulation time 46594923 ps
CPU time 0.85 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206868 kb
Host smart-e9f8435e-bea2-4457-94e1-c9b2f2891a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502264684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1502264684
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2294515046
Short name T1077
Test name
Test status
Simulation time 27853788 ps
CPU time 0.87 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206916 kb
Host smart-52b89380-a5fa-413d-9c9f-597be7c1c4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294515046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2294515046
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2864247415
Short name T1030
Test name
Test status
Simulation time 38313557 ps
CPU time 0.8 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206656 kb
Host smart-a66eb804-4797-457c-8c18-313f5b2ee26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864247415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2864247415
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2538480657
Short name T1124
Test name
Test status
Simulation time 49941747 ps
CPU time 0.89 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206900 kb
Host smart-bf2c59c9-a107-4fbb-a4f7-ea6f54fc26b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538480657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2538480657
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3123741681
Short name T272
Test name
Test status
Simulation time 146505157 ps
CPU time 1.54 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:52 PM PDT 24
Peak memory 206956 kb
Host smart-f79e4ed8-053c-4458-8994-525a4976adac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123741681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3123741681
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1328632264
Short name T1020
Test name
Test status
Simulation time 954662344 ps
CPU time 3.59 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:03 PM PDT 24
Peak memory 206924 kb
Host smart-a22e86f6-719c-44d1-bc9f-5c168dd2537e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328632264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1328632264
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1179695854
Short name T1021
Test name
Test status
Simulation time 86826350 ps
CPU time 0.96 seconds
Started Jul 03 05:22:47 PM PDT 24
Finished Jul 03 05:22:49 PM PDT 24
Peak memory 206984 kb
Host smart-e6cde2de-c5cb-4e92-9bbe-682aac23034b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179695854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1179695854
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1980064187
Short name T1051
Test name
Test status
Simulation time 118837405 ps
CPU time 1.2 seconds
Started Jul 03 05:23:04 PM PDT 24
Finished Jul 03 05:23:07 PM PDT 24
Peak memory 215236 kb
Host smart-c8edf7ff-0e46-41d1-aa91-965f46078746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980064187 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1980064187
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.69170823
Short name T283
Test name
Test status
Simulation time 32864386 ps
CPU time 0.85 seconds
Started Jul 03 05:22:43 PM PDT 24
Finished Jul 03 05:22:44 PM PDT 24
Peak memory 206828 kb
Host smart-aaf6f703-4cd9-4510-8087-ab611431d7ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69170823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.69170823
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2191875023
Short name T1100
Test name
Test status
Simulation time 73878888 ps
CPU time 0.83 seconds
Started Jul 03 05:22:44 PM PDT 24
Finished Jul 03 05:22:45 PM PDT 24
Peak memory 206768 kb
Host smart-e607bce1-eacb-435d-b26c-1b8b588a47fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191875023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2191875023
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.916645933
Short name T1110
Test name
Test status
Simulation time 59818186 ps
CPU time 1.04 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206948 kb
Host smart-3df0b5ac-e8d3-4d53-b413-a1551b9b0092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916645933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.916645933
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3420382672
Short name T1029
Test name
Test status
Simulation time 46069927 ps
CPU time 1.63 seconds
Started Jul 03 05:22:55 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 215244 kb
Host smart-1ec14387-6bf5-41e1-8d9c-715f6e7898da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420382672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3420382672
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2143336195
Short name T295
Test name
Test status
Simulation time 61012148 ps
CPU time 1.9 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 207248 kb
Host smart-b7d17acc-c265-4da3-bd02-8f76f4c8184a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143336195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2143336195
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2285462706
Short name T1056
Test name
Test status
Simulation time 18850306 ps
CPU time 0.79 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206688 kb
Host smart-0acfe995-8219-4fe0-a574-b3a8a76e5544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285462706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2285462706
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.517963045
Short name T1111
Test name
Test status
Simulation time 21475747 ps
CPU time 0.83 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206860 kb
Host smart-d56fcddf-668a-4115-96ac-5ad05dba3c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517963045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.517963045
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2684688104
Short name T1017
Test name
Test status
Simulation time 10933555 ps
CPU time 0.77 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:58 PM PDT 24
Peak memory 207104 kb
Host smart-dcf16196-2031-481f-9bcf-e5c25eaee91c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684688104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2684688104
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4146141112
Short name T1063
Test name
Test status
Simulation time 47915002 ps
CPU time 0.82 seconds
Started Jul 03 05:23:05 PM PDT 24
Finished Jul 03 05:23:07 PM PDT 24
Peak memory 206916 kb
Host smart-0f434640-6396-4f06-a376-3ca2511fb163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146141112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4146141112
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.573179547
Short name T1023
Test name
Test status
Simulation time 32382253 ps
CPU time 0.89 seconds
Started Jul 03 05:23:08 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 206856 kb
Host smart-5465b067-953b-4eeb-b4f5-b93ead0c342d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573179547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.573179547
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1536250729
Short name T1097
Test name
Test status
Simulation time 23375387 ps
CPU time 0.86 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:01 PM PDT 24
Peak memory 206720 kb
Host smart-20f76e1a-7fcc-4ec7-903f-65291ca3884f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536250729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1536250729
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2603067023
Short name T1070
Test name
Test status
Simulation time 19377764 ps
CPU time 0.87 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:05 PM PDT 24
Peak memory 206824 kb
Host smart-54b86134-be4d-4a8e-acda-d73e30739f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603067023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2603067023
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1808168246
Short name T1009
Test name
Test status
Simulation time 22454552 ps
CPU time 0.85 seconds
Started Jul 03 05:23:18 PM PDT 24
Finished Jul 03 05:23:19 PM PDT 24
Peak memory 206924 kb
Host smart-204e3467-c4c8-431c-970b-e32895b90a5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808168246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1808168246
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.151260420
Short name T1012
Test name
Test status
Simulation time 57495034 ps
CPU time 0.82 seconds
Started Jul 03 05:23:03 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 206680 kb
Host smart-a45305b8-b715-481f-b414-d868ef769b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151260420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.151260420
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2503608831
Short name T1045
Test name
Test status
Simulation time 19255210 ps
CPU time 0.88 seconds
Started Jul 03 05:23:19 PM PDT 24
Finished Jul 03 05:23:21 PM PDT 24
Peak memory 206920 kb
Host smart-9b96e66c-3961-454b-a474-5c62af0da2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503608831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2503608831
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2416967258
Short name T1128
Test name
Test status
Simulation time 17297763 ps
CPU time 1.04 seconds
Started Jul 03 05:22:43 PM PDT 24
Finished Jul 03 05:22:45 PM PDT 24
Peak memory 207000 kb
Host smart-aefd8c97-9864-44c5-af13-125ff559950a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416967258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2416967258
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3190550156
Short name T264
Test name
Test status
Simulation time 171666389 ps
CPU time 3.22 seconds
Started Jul 03 05:22:47 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206984 kb
Host smart-1f75a946-cfe3-4917-bc9f-f44ace4dbe96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190550156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3190550156
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2084921202
Short name T1120
Test name
Test status
Simulation time 15132813 ps
CPU time 0.97 seconds
Started Jul 03 05:22:54 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206892 kb
Host smart-4d719998-7efa-4939-a375-a5651b301294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084921202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2084921202
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.59559039
Short name T1082
Test name
Test status
Simulation time 42115426 ps
CPU time 1.23 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 215196 kb
Host smart-9b3f6e6a-d5ed-47e4-853a-9be3052ac9d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59559039 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.59559039
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.998263320
Short name T281
Test name
Test status
Simulation time 24512654 ps
CPU time 1.04 seconds
Started Jul 03 05:22:45 PM PDT 24
Finished Jul 03 05:22:48 PM PDT 24
Peak memory 206868 kb
Host smart-a129e368-8716-4393-b381-a240c894e011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998263320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.998263320
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1662168360
Short name T1010
Test name
Test status
Simulation time 18652152 ps
CPU time 0.84 seconds
Started Jul 03 05:22:46 PM PDT 24
Finished Jul 03 05:22:48 PM PDT 24
Peak memory 206664 kb
Host smart-dc459700-a3ac-4d7d-8cf5-fc4d36610cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662168360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1662168360
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3963702048
Short name T1091
Test name
Test status
Simulation time 63532237 ps
CPU time 1.28 seconds
Started Jul 03 05:22:55 PM PDT 24
Finished Jul 03 05:22:56 PM PDT 24
Peak memory 206992 kb
Host smart-27f6b1ae-a420-4ebd-9333-ab7747a3efa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963702048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3963702048
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4134167288
Short name T1016
Test name
Test status
Simulation time 236665771 ps
CPU time 4.22 seconds
Started Jul 03 05:22:49 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 215200 kb
Host smart-a7932192-22d0-4773-8127-f0f33107901a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134167288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4134167288
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.834647128
Short name T308
Test name
Test status
Simulation time 179828587 ps
CPU time 2.55 seconds
Started Jul 03 05:22:41 PM PDT 24
Finished Jul 03 05:22:44 PM PDT 24
Peak memory 206984 kb
Host smart-0c433122-c3a6-4ec6-ad1b-ecda33672cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834647128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.834647128
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2239646028
Short name T1058
Test name
Test status
Simulation time 12534778 ps
CPU time 0.87 seconds
Started Jul 03 05:23:14 PM PDT 24
Finished Jul 03 05:23:15 PM PDT 24
Peak memory 206892 kb
Host smart-2ae3dbd1-411f-4460-b837-df420eecad53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239646028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2239646028
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2747734035
Short name T1055
Test name
Test status
Simulation time 52953888 ps
CPU time 0.82 seconds
Started Jul 03 05:23:03 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 206680 kb
Host smart-acd478cd-4d1f-498c-8315-a8fc51d7d2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747734035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2747734035
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3046548862
Short name T1047
Test name
Test status
Simulation time 33570048 ps
CPU time 0.8 seconds
Started Jul 03 05:23:06 PM PDT 24
Finished Jul 03 05:23:08 PM PDT 24
Peak memory 206888 kb
Host smart-12341312-c45a-41bc-b859-1659eeb465d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046548862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3046548862
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1218360158
Short name T1127
Test name
Test status
Simulation time 15372796 ps
CPU time 0.91 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:04 PM PDT 24
Peak memory 206840 kb
Host smart-668b146a-1e91-464b-a1c6-213d03df922a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218360158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1218360158
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3524846174
Short name T1096
Test name
Test status
Simulation time 11653674 ps
CPU time 0.82 seconds
Started Jul 03 05:23:03 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 206868 kb
Host smart-5e2c449e-4b6d-4cd1-a0b5-ae99f2bd3c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524846174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3524846174
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4276341327
Short name T1067
Test name
Test status
Simulation time 47778181 ps
CPU time 0.84 seconds
Started Jul 03 05:22:58 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206864 kb
Host smart-dde0e686-b79c-4d90-95c6-740fb770ca43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276341327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4276341327
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3077273316
Short name T1078
Test name
Test status
Simulation time 21330311 ps
CPU time 0.92 seconds
Started Jul 03 05:23:13 PM PDT 24
Finished Jul 03 05:23:15 PM PDT 24
Peak memory 206864 kb
Host smart-f8c02648-0d71-4c0f-92b2-b02bec2c0c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077273316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3077273316
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4021465711
Short name T1043
Test name
Test status
Simulation time 24076587 ps
CPU time 0.8 seconds
Started Jul 03 05:23:12 PM PDT 24
Finished Jul 03 05:23:14 PM PDT 24
Peak memory 206844 kb
Host smart-c598a15b-f221-4b74-9af7-a7ca2088560f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021465711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4021465711
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2042625683
Short name T1061
Test name
Test status
Simulation time 23180865 ps
CPU time 0.85 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:03 PM PDT 24
Peak memory 206860 kb
Host smart-340c3f22-da23-4a5f-8ca0-bba02d46fae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042625683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2042625683
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2831685248
Short name T1087
Test name
Test status
Simulation time 34083857 ps
CPU time 0.8 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:02 PM PDT 24
Peak memory 206692 kb
Host smart-0f763f06-00a3-4eba-ac37-cd62153a60c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831685248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2831685248
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.695495874
Short name T1107
Test name
Test status
Simulation time 19359689 ps
CPU time 1.07 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:53 PM PDT 24
Peak memory 215272 kb
Host smart-96d7402d-9cd6-46bd-acdf-216ae2096241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695495874 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.695495874
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.457920098
Short name T269
Test name
Test status
Simulation time 13433568 ps
CPU time 0.85 seconds
Started Jul 03 05:22:54 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206912 kb
Host smart-e5964056-ba02-4047-a1cd-7aaf289bebbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457920098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.457920098
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2138436677
Short name T1075
Test name
Test status
Simulation time 44825108 ps
CPU time 0.85 seconds
Started Jul 03 05:22:40 PM PDT 24
Finished Jul 03 05:22:42 PM PDT 24
Peak memory 206812 kb
Host smart-ba08a37d-f4f4-4264-8ea5-f5b1a10930df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138436677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2138436677
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.905588001
Short name T1119
Test name
Test status
Simulation time 50281241 ps
CPU time 1 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 206944 kb
Host smart-6753bc76-c1f6-4ff8-9c91-12e285cf1eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905588001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.905588001
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4070494672
Short name T1040
Test name
Test status
Simulation time 142906965 ps
CPU time 1.73 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 215208 kb
Host smart-a44023a5-8b8c-4ad8-9eef-2792ed39c462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070494672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4070494672
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1128453366
Short name T297
Test name
Test status
Simulation time 177529040 ps
CPU time 2.41 seconds
Started Jul 03 05:22:38 PM PDT 24
Finished Jul 03 05:22:41 PM PDT 24
Peak memory 207216 kb
Host smart-3f96111b-abc6-49ff-b2dd-aadf56c7c8a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128453366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1128453366
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2034273199
Short name T1004
Test name
Test status
Simulation time 119257250 ps
CPU time 1.43 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 217604 kb
Host smart-3be33ecc-6be3-4f32-96c2-defc28c491b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034273199 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2034273199
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.743610216
Short name T1073
Test name
Test status
Simulation time 14028110 ps
CPU time 0.95 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:58 PM PDT 24
Peak memory 206912 kb
Host smart-c984c897-6e73-4e5d-89f1-34e9600c4b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743610216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.743610216
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4141570669
Short name T1129
Test name
Test status
Simulation time 38246744 ps
CPU time 0.84 seconds
Started Jul 03 05:22:50 PM PDT 24
Finished Jul 03 05:22:51 PM PDT 24
Peak memory 206808 kb
Host smart-4a9363b3-3294-433a-b547-74a77d13401e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141570669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4141570669
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.807724956
Short name T1105
Test name
Test status
Simulation time 17229261 ps
CPU time 1.11 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:22:59 PM PDT 24
Peak memory 206964 kb
Host smart-82f67e7d-4bf4-43e6-9b23-1834c4d1e267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807724956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.807724956
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.492843616
Short name T1125
Test name
Test status
Simulation time 479563321 ps
CPU time 3.84 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:08 PM PDT 24
Peak memory 215188 kb
Host smart-54b69710-0de0-4b47-95e6-ac928d4323a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492843616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.492843616
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3319697239
Short name T1060
Test name
Test status
Simulation time 204299487 ps
CPU time 2.53 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:56 PM PDT 24
Peak memory 206964 kb
Host smart-6566c5ce-d42b-4884-b2e9-74ef7025a660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319697239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3319697239
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4027290413
Short name T1098
Test name
Test status
Simulation time 71894229 ps
CPU time 1.58 seconds
Started Jul 03 05:22:55 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 215156 kb
Host smart-3313414c-c07a-4c24-981d-7a0559c388eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027290413 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.4027290413
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2294634014
Short name T271
Test name
Test status
Simulation time 29677116 ps
CPU time 0.97 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206912 kb
Host smart-2609d55b-63eb-41f2-a636-2a1bd969e6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294634014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2294634014
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1194734527
Short name T1093
Test name
Test status
Simulation time 16573419 ps
CPU time 0.97 seconds
Started Jul 03 05:22:53 PM PDT 24
Finished Jul 03 05:22:55 PM PDT 24
Peak memory 206860 kb
Host smart-bbfb21c9-4294-4175-9e7c-d9e9bc3d4434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194734527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1194734527
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.61682892
Short name T1085
Test name
Test status
Simulation time 315075761 ps
CPU time 1.4 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 206988 kb
Host smart-5358985c-1406-4d0d-9e55-ae8f79d62473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61682892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.61682892
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3100865037
Short name T1005
Test name
Test status
Simulation time 36393859 ps
CPU time 2.4 seconds
Started Jul 03 05:22:47 PM PDT 24
Finished Jul 03 05:22:50 PM PDT 24
Peak memory 215212 kb
Host smart-dfd5541b-a106-4ddd-a29e-b10e3f92fd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100865037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3100865037
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.354110054
Short name T1013
Test name
Test status
Simulation time 45588392 ps
CPU time 1.51 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 215176 kb
Host smart-5c655c9d-3990-47c0-9c0c-f5d617a6c498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354110054 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.354110054
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3416023225
Short name T268
Test name
Test status
Simulation time 11915372 ps
CPU time 0.91 seconds
Started Jul 03 05:23:01 PM PDT 24
Finished Jul 03 05:23:04 PM PDT 24
Peak memory 206888 kb
Host smart-66e88ae2-7b81-46de-b4cf-d2a93e5ffede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416023225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3416023225
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3291374308
Short name T1065
Test name
Test status
Simulation time 13390058 ps
CPU time 0.9 seconds
Started Jul 03 05:22:56 PM PDT 24
Finished Jul 03 05:22:57 PM PDT 24
Peak memory 206872 kb
Host smart-4f1f2a99-480f-462b-83f4-d3f5013af2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291374308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3291374308
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3830921517
Short name T286
Test name
Test status
Simulation time 14413235 ps
CPU time 0.98 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:52 PM PDT 24
Peak memory 207064 kb
Host smart-5712ddcc-e341-437e-8203-ba845148a80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830921517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3830921517
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3850389968
Short name T1014
Test name
Test status
Simulation time 36274448 ps
CPU time 1.54 seconds
Started Jul 03 05:23:02 PM PDT 24
Finished Jul 03 05:23:06 PM PDT 24
Peak memory 215216 kb
Host smart-0d81e7a0-e0d6-4c4b-8a52-14beef379049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850389968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3850389968
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4058368525
Short name T1039
Test name
Test status
Simulation time 84624755 ps
CPU time 2.31 seconds
Started Jul 03 05:22:51 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 215176 kb
Host smart-80535be5-99a8-4dea-9fbd-c871b825ac00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058368525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4058368525
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3602023052
Short name T1057
Test name
Test status
Simulation time 46248454 ps
CPU time 1.05 seconds
Started Jul 03 05:23:00 PM PDT 24
Finished Jul 03 05:23:03 PM PDT 24
Peak memory 215256 kb
Host smart-82ae9fea-5304-45f9-a104-7d116f4157af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602023052 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3602023052
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3051567632
Short name T275
Test name
Test status
Simulation time 14744184 ps
CPU time 0.92 seconds
Started Jul 03 05:22:52 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 206864 kb
Host smart-bc1a1e8f-5cf7-40b5-9159-b20a2778829e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051567632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3051567632
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3169649531
Short name T1101
Test name
Test status
Simulation time 17072405 ps
CPU time 0.9 seconds
Started Jul 03 05:22:44 PM PDT 24
Finished Jul 03 05:22:47 PM PDT 24
Peak memory 206924 kb
Host smart-5a006584-b0ad-4bff-bb5b-1d44f61134a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169649531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3169649531
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2279519307
Short name T1038
Test name
Test status
Simulation time 13306248 ps
CPU time 0.98 seconds
Started Jul 03 05:22:59 PM PDT 24
Finished Jul 03 05:23:01 PM PDT 24
Peak memory 207108 kb
Host smart-cf7a2a7a-0040-46c5-b828-10cce4bfb684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279519307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2279519307
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.209245540
Short name T1113
Test name
Test status
Simulation time 244934355 ps
CPU time 2.3 seconds
Started Jul 03 05:22:57 PM PDT 24
Finished Jul 03 05:23:00 PM PDT 24
Peak memory 215220 kb
Host smart-12f0290c-f0a0-4d55-b19a-d80f2f9466b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209245540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.209245540
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4083202865
Short name T1066
Test name
Test status
Simulation time 707644023 ps
CPU time 2.72 seconds
Started Jul 03 05:23:03 PM PDT 24
Finished Jul 03 05:23:08 PM PDT 24
Peak memory 206992 kb
Host smart-ef23fb71-4f15-4fd0-b80b-43797a480a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083202865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4083202865
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.11518552
Short name T352
Test name
Test status
Simulation time 101186221 ps
CPU time 1.3 seconds
Started Jul 03 05:29:31 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 216008 kb
Host smart-c0b15c49-4a55-46d4-a243-12b735073292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11518552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.11518552
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1619721324
Short name T529
Test name
Test status
Simulation time 18699299 ps
CPU time 0.85 seconds
Started Jul 03 05:29:30 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 206744 kb
Host smart-bf299550-47f2-4d89-87bf-9c81b0db65f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619721324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1619721324
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.918749260
Short name T379
Test name
Test status
Simulation time 16223258 ps
CPU time 0.84 seconds
Started Jul 03 05:29:31 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 216288 kb
Host smart-4c248c7e-bd8c-41b3-858a-43a0964b270d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918749260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.918749260
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1863660835
Short name T21
Test name
Test status
Simulation time 142388565 ps
CPU time 1.03 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:29:30 PM PDT 24
Peak memory 218716 kb
Host smart-14cec888-abff-4884-a1ed-600858a59046
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863660835 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1863660835
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.2943286139
Short name T610
Test name
Test status
Simulation time 42595106 ps
CPU time 1.34 seconds
Started Jul 03 05:29:28 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 220260 kb
Host smart-5f9937fd-1991-40c4-a5c2-2b94ad501b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943286139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2943286139
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3892167696
Short name T909
Test name
Test status
Simulation time 25862884 ps
CPU time 1.03 seconds
Started Jul 03 05:29:31 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 215876 kb
Host smart-ab04d5cd-44c9-4620-898e-43171b66795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892167696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3892167696
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3620179678
Short name T341
Test name
Test status
Simulation time 31761605 ps
CPU time 1 seconds
Started Jul 03 05:29:27 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 207332 kb
Host smart-1650c9db-471f-4761-97d7-05d9cd6016bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620179678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3620179678
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2575967968
Short name T866
Test name
Test status
Simulation time 19059758 ps
CPU time 1.05 seconds
Started Jul 03 05:29:24 PM PDT 24
Finished Jul 03 05:29:25 PM PDT 24
Peak memory 215564 kb
Host smart-9ca52834-237e-4271-8cc4-c5ebfe2d2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575967968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2575967968
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.258589473
Short name T683
Test name
Test status
Simulation time 425267974 ps
CPU time 8.35 seconds
Started Jul 03 05:29:27 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 217516 kb
Host smart-5db4d3b4-83c4-4346-afde-d643afbcc3bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258589473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.258589473
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.916882288
Short name T625
Test name
Test status
Simulation time 23662280730 ps
CPU time 254.21 seconds
Started Jul 03 05:29:30 PM PDT 24
Finished Jul 03 05:33:44 PM PDT 24
Peak memory 223880 kb
Host smart-132ca20f-23a1-4dd4-8350-6cd336c5bcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916882288 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.916882288
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.932623725
Short name T260
Test name
Test status
Simulation time 27238836 ps
CPU time 1.22 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:29:31 PM PDT 24
Peak memory 219032 kb
Host smart-27fcfaeb-35dc-4434-b8a3-f79a16b4e1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932623725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.932623725
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3306704427
Short name T834
Test name
Test status
Simulation time 82104282 ps
CPU time 0.95 seconds
Started Jul 03 05:29:32 PM PDT 24
Finished Jul 03 05:29:34 PM PDT 24
Peak memory 207076 kb
Host smart-cd8f00e5-0b3b-40e3-b3ea-54f947413f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306704427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3306704427
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1860225147
Short name T128
Test name
Test status
Simulation time 42913403 ps
CPU time 1.43 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:29:31 PM PDT 24
Peak memory 217188 kb
Host smart-2b15fd70-4261-44b1-8d43-5a7d22fce390
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860225147 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1860225147
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3410150329
Short name T648
Test name
Test status
Simulation time 39488290 ps
CPU time 1.19 seconds
Started Jul 03 05:29:30 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 220900 kb
Host smart-f9ad880f-7e8d-4e77-bed8-80816efaa80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410150329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3410150329
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1196993946
Short name T813
Test name
Test status
Simulation time 229447068 ps
CPU time 1.05 seconds
Started Jul 03 05:29:28 PM PDT 24
Finished Jul 03 05:29:30 PM PDT 24
Peak memory 217704 kb
Host smart-6e7ec83c-447a-403b-bd77-68ccdd09e020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196993946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1196993946
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.446785797
Short name T102
Test name
Test status
Simulation time 19952188 ps
CPU time 1.06 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:29:30 PM PDT 24
Peak memory 216164 kb
Host smart-cd7a110c-90f3-4044-bc69-0eeb476d64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446785797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.446785797
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.451479155
Short name T28
Test name
Test status
Simulation time 15150494 ps
CPU time 0.96 seconds
Started Jul 03 05:29:28 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 207352 kb
Host smart-3a8e3521-0be5-49ea-9d62-1c43fd79dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451479155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.451479155
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.620133449
Short name T15
Test name
Test status
Simulation time 1895283700 ps
CPU time 7.2 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 235980 kb
Host smart-a250665d-563b-4de8-a7f4-1519b4e11b44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620133449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.620133449
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3453944151
Short name T449
Test name
Test status
Simulation time 51139266 ps
CPU time 0.95 seconds
Started Jul 03 05:29:31 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 215604 kb
Host smart-1db0f648-f068-4e0f-82f6-d500f497d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453944151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3453944151
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2880200768
Short name T863
Test name
Test status
Simulation time 144173624 ps
CPU time 1.98 seconds
Started Jul 03 05:29:30 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 219724 kb
Host smart-cafe4d72-85f1-4415-8016-403c9ce25787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880200768 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2880200768
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1212792075
Short name T420
Test name
Test status
Simulation time 16262901825 ps
CPU time 373.32 seconds
Started Jul 03 05:29:29 PM PDT 24
Finished Jul 03 05:35:42 PM PDT 24
Peak memory 218192 kb
Host smart-5ac86d2e-38da-4a35-88a1-135dc1093883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212792075 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1212792075
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable.3117415532
Short name T662
Test name
Test status
Simulation time 20116979 ps
CPU time 0.87 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215772 kb
Host smart-f4dd6d44-e212-4110-931b-271a738360a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117415532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3117415532
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2277084944
Short name T821
Test name
Test status
Simulation time 136384023 ps
CPU time 1.1 seconds
Started Jul 03 05:29:43 PM PDT 24
Finished Jul 03 05:29:44 PM PDT 24
Peak memory 220096 kb
Host smart-d40f4f24-0980-4bbc-b54b-f85bddb712b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277084944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2277084944
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.418150997
Short name T587
Test name
Test status
Simulation time 37730912 ps
CPU time 1.07 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 217716 kb
Host smart-a8b893c5-3520-4b49-97d5-a3f72298dea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418150997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.418150997
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.166500157
Short name T489
Test name
Test status
Simulation time 25864424 ps
CPU time 0.97 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 215644 kb
Host smart-93112874-bb0c-4db4-9548-bff911a5921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166500157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.166500157
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.620021278
Short name T532
Test name
Test status
Simulation time 94362103 ps
CPU time 0.96 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215640 kb
Host smart-f35a96cc-000b-4840-9c68-98a8fdf7e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620021278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.620021278
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1105851393
Short name T572
Test name
Test status
Simulation time 205291773 ps
CPU time 4.3 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 217560 kb
Host smart-c28a2dd2-7a94-4a43-8b02-032f88467233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105851393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1105851393
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4053016107
Short name T718
Test name
Test status
Simulation time 48319632756 ps
CPU time 1166.89 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:49:19 PM PDT 24
Peak memory 224072 kb
Host smart-24c44136-0db2-4d7e-b82f-6e67fb381888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053016107 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4053016107
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2633514827
Short name T748
Test name
Test status
Simulation time 32282175 ps
CPU time 1.35 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 215988 kb
Host smart-9a31d56e-0a5d-4920-ae12-fa52117b26c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633514827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2633514827
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1997501654
Short name T987
Test name
Test status
Simulation time 286847600 ps
CPU time 4.05 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 219728 kb
Host smart-7bbe2c66-1a46-4898-a90d-c74942e05aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997501654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1997501654
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.853365488
Short name T557
Test name
Test status
Simulation time 59131550 ps
CPU time 1.29 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 221944 kb
Host smart-6e548457-8247-4239-9b10-9ec4a9bd881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853365488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.853365488
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3942313397
Short name T523
Test name
Test status
Simulation time 27708120 ps
CPU time 1.25 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 218928 kb
Host smart-5ba567ef-fbc3-45fc-9aab-909b2ee9c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942313397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3942313397
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3481715437
Short name T617
Test name
Test status
Simulation time 50177789 ps
CPU time 1.24 seconds
Started Jul 03 05:31:10 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 219836 kb
Host smart-a6cdc602-5ff0-43f9-999d-62660ff65ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481715437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3481715437
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.4105869494
Short name T508
Test name
Test status
Simulation time 30289172 ps
CPU time 1.26 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 217628 kb
Host smart-eadfa886-080e-4b3d-ac49-17800cb069e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105869494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.4105869494
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1410193797
Short name T872
Test name
Test status
Simulation time 76494710 ps
CPU time 1.17 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 219040 kb
Host smart-c9478dc6-2302-4dc9-9151-23fbe7a31506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410193797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1410193797
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2736316755
Short name T842
Test name
Test status
Simulation time 171620167 ps
CPU time 2.1 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 220388 kb
Host smart-7ade943f-54e2-4861-bd33-ef6356de97cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736316755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2736316755
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.892266309
Short name T534
Test name
Test status
Simulation time 130827004 ps
CPU time 1.22 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 221680 kb
Host smart-9f2047cd-b31b-4f62-aa5f-131683a6e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892266309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.892266309
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2978964140
Short name T951
Test name
Test status
Simulation time 46522074 ps
CPU time 1.24 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:22 PM PDT 24
Peak memory 220328 kb
Host smart-9b66bd2f-5faf-499a-97fe-a018285cf82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978964140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2978964140
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2320116993
Short name T940
Test name
Test status
Simulation time 45421045 ps
CPU time 1.11 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:07 PM PDT 24
Peak memory 220268 kb
Host smart-18ad5ccb-b031-4fe0-9ced-1576235935f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320116993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2320116993
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2188525627
Short name T613
Test name
Test status
Simulation time 50987877 ps
CPU time 1.95 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 217956 kb
Host smart-a32e1e7a-dee5-42b9-b338-c87c36071590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188525627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2188525627
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2612650643
Short name T137
Test name
Test status
Simulation time 28307998 ps
CPU time 1.26 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 219040 kb
Host smart-138f6cb5-c7c5-4352-8b08-d3bc54d0b827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612650643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2612650643
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.2209846980
Short name T857
Test name
Test status
Simulation time 73603163 ps
CPU time 1.17 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 219524 kb
Host smart-ed246b5f-76b6-4f25-a653-00049b472daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209846980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2209846980
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2926178884
Short name T952
Test name
Test status
Simulation time 29752716 ps
CPU time 1.15 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 217700 kb
Host smart-1b1b3627-c0fc-48f9-92db-1050e4fbc2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926178884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2926178884
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1779278053
Short name T827
Test name
Test status
Simulation time 28983054 ps
CPU time 1.33 seconds
Started Jul 03 05:30:53 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 219920 kb
Host smart-dda24a7b-a882-4db1-ae15-9291a360cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779278053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1779278053
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.967945536
Short name T931
Test name
Test status
Simulation time 36796129 ps
CPU time 1.1 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 217616 kb
Host smart-1f74f48b-d880-4468-aa4d-2592483abbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967945536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.967945536
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.2923991969
Short name T841
Test name
Test status
Simulation time 46166333 ps
CPU time 1.19 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 219236 kb
Host smart-e8ff3dd0-2795-42a9-836a-48fd2cf2c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923991969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2923991969
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3012018902
Short name T258
Test name
Test status
Simulation time 20281327 ps
CPU time 1.11 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 217748 kb
Host smart-861bd3c1-ea27-410a-961d-e39c41b696ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012018902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3012018902
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2575696758
Short name T527
Test name
Test status
Simulation time 36670780 ps
CPU time 0.84 seconds
Started Jul 03 05:29:42 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 207068 kb
Host smart-e171ec7d-0221-4cf4-8f3d-392eac378d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575696758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2575696758
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.615655986
Short name T501
Test name
Test status
Simulation time 35964652 ps
CPU time 0.93 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 215708 kb
Host smart-fbf4bf87-dcfa-4f83-8aa0-d95e1cc1f89e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615655986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.615655986
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2461907921
Short name T129
Test name
Test status
Simulation time 104250444 ps
CPU time 1.05 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 217236 kb
Host smart-ff1f7d9a-f102-46eb-9344-a7c638705260
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461907921 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2461907921
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3252106359
Short name T207
Test name
Test status
Simulation time 19913064 ps
CPU time 1.14 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 219020 kb
Host smart-08f64298-e447-4c1f-a422-e05eca1967b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252106359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3252106359
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3081482802
Short name T606
Test name
Test status
Simulation time 51145807 ps
CPU time 1.8 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 217716 kb
Host smart-45d8010b-3ded-40bf-94a7-e87136d8ff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081482802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3081482802
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1940255460
Short name T101
Test name
Test status
Simulation time 27602785 ps
CPU time 0.88 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 216008 kb
Host smart-4dbdb4e6-146e-42a8-9d5b-bb94f1e34cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940255460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1940255460
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4288918326
Short name T552
Test name
Test status
Simulation time 30873358 ps
CPU time 0.97 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 215628 kb
Host smart-5d4432ba-3a7f-426a-aa5e-15bcf3ad607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288918326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4288918326
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.411891445
Short name T463
Test name
Test status
Simulation time 459590760 ps
CPU time 4.92 seconds
Started Jul 03 05:29:52 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 220232 kb
Host smart-68eb84e6-03e2-43ef-9fa7-ef4a468f8f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411891445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.411891445
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.620421799
Short name T671
Test name
Test status
Simulation time 34430214002 ps
CPU time 771.15 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:42:43 PM PDT 24
Peak memory 224016 kb
Host smart-6f4a61f2-3b6f-40cc-b92d-7d1f9109d2b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620421799 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.620421799
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2984408041
Short name T429
Test name
Test status
Simulation time 267425727 ps
CPU time 1.06 seconds
Started Jul 03 05:31:10 PM PDT 24
Finished Jul 03 05:31:12 PM PDT 24
Peak memory 218672 kb
Host smart-ce866aab-9c40-4a53-8211-1497b9b62fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984408041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2984408041
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.811980362
Short name T582
Test name
Test status
Simulation time 42971194 ps
CPU time 1.67 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 218296 kb
Host smart-aa009b95-c35d-4c78-8ae4-55678d11a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811980362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.811980362
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2777079326
Short name T837
Test name
Test status
Simulation time 44596201 ps
CPU time 1.14 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 219032 kb
Host smart-b66681d7-a1c9-4b2b-984c-ede14c6b55d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777079326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2777079326
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.941846888
Short name T999
Test name
Test status
Simulation time 27536808 ps
CPU time 1.23 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 218676 kb
Host smart-50c5b93a-da49-477d-8ca2-548168bc0f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941846888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.941846888
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1109851192
Short name T130
Test name
Test status
Simulation time 61711065 ps
CPU time 1.09 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 218956 kb
Host smart-e277b723-3b00-4d4a-8fe3-c381e8b39d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109851192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1109851192
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3871575569
Short name T806
Test name
Test status
Simulation time 48045992 ps
CPU time 2 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 219164 kb
Host smart-27bba415-4ce4-411c-b838-8a64dffe3f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871575569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3871575569
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3096803285
Short name T723
Test name
Test status
Simulation time 26043416 ps
CPU time 1.18 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 218892 kb
Host smart-f4d649f4-a8bd-4ad0-a3e4-21264755a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096803285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3096803285
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.4213053863
Short name T976
Test name
Test status
Simulation time 202787407 ps
CPU time 1.18 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 220568 kb
Host smart-1ae53f92-4239-4995-9222-4e7757e84229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213053863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4213053863
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1095966688
Short name T197
Test name
Test status
Simulation time 24266628 ps
CPU time 1.18 seconds
Started Jul 03 05:31:25 PM PDT 24
Finished Jul 03 05:31:27 PM PDT 24
Peak memory 220208 kb
Host smart-d423a5ef-f7f5-48bb-a060-01a9af661976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095966688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1095966688
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.479802383
Short name T402
Test name
Test status
Simulation time 89929612 ps
CPU time 1.61 seconds
Started Jul 03 05:31:30 PM PDT 24
Finished Jul 03 05:31:32 PM PDT 24
Peak memory 219836 kb
Host smart-36d13d8c-b1ba-4deb-a0f6-fb97690cdd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479802383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.479802383
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3569873527
Short name T347
Test name
Test status
Simulation time 25044637 ps
CPU time 1.16 seconds
Started Jul 03 05:31:31 PM PDT 24
Finished Jul 03 05:31:32 PM PDT 24
Peak memory 220024 kb
Host smart-7509dff2-6e4a-458b-9ed0-351162dd8f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569873527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3569873527
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3118353983
Short name T45
Test name
Test status
Simulation time 42046520 ps
CPU time 1.72 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 219088 kb
Host smart-9957a104-b2c0-49cb-94d7-c2bd8e613bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118353983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3118353983
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2142228230
Short name T741
Test name
Test status
Simulation time 82819618 ps
CPU time 1.13 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:07 PM PDT 24
Peak memory 220196 kb
Host smart-9992b908-0a4f-40b9-8201-90de45152d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142228230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2142228230
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1032243742
Short name T417
Test name
Test status
Simulation time 68324678 ps
CPU time 1.32 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217608 kb
Host smart-c7151958-9c0d-4ca5-a4d4-03771cd64852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032243742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1032243742
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.4134670402
Short name T963
Test name
Test status
Simulation time 66080542 ps
CPU time 1.09 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 220492 kb
Host smart-49cacbcf-0ba4-4597-ac87-c8c02e4ce8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134670402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.4134670402
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2145354628
Short name T801
Test name
Test status
Simulation time 41854612 ps
CPU time 1.19 seconds
Started Jul 03 05:31:27 PM PDT 24
Finished Jul 03 05:31:34 PM PDT 24
Peak memory 217596 kb
Host smart-1ef52e0b-2080-40b9-8973-69ccfdc0ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145354628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2145354628
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1052705489
Short name T920
Test name
Test status
Simulation time 50739094 ps
CPU time 1.34 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220584 kb
Host smart-0ed95f59-eb8d-4f36-91a0-34d0b3de173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052705489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1052705489
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.1940307691
Short name T643
Test name
Test status
Simulation time 90319250 ps
CPU time 1.11 seconds
Started Jul 03 05:31:14 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 219932 kb
Host smart-bec70b08-9aea-43dd-8650-46bae88cd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940307691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1940307691
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.1556096857
Short name T168
Test name
Test status
Simulation time 80078045 ps
CPU time 1.06 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 219064 kb
Host smart-73914e29-d72c-4f61-8cea-58cbf3b84e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556096857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1556096857
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3082723642
Short name T632
Test name
Test status
Simulation time 65177048 ps
CPU time 0.88 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 207048 kb
Host smart-c5389693-b618-41d9-8df0-f54e1d88e9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082723642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3082723642
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1373664854
Short name T700
Test name
Test status
Simulation time 169157310 ps
CPU time 0.9 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 216532 kb
Host smart-a29861e6-d6e8-40f0-a8c9-6051924804b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373664854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1373664854
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3394248723
Short name T982
Test name
Test status
Simulation time 43679448 ps
CPU time 1.1 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 218464 kb
Host smart-a5cec6d2-c07c-40aa-9ed2-823248504151
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394248723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3394248723
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.3552648277
Short name T624
Test name
Test status
Simulation time 91808088 ps
CPU time 1.88 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 220292 kb
Host smart-7d964f62-d514-409d-9639-74a8ee5e1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552648277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3552648277
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1062173704
Short name T679
Test name
Test status
Simulation time 39008308 ps
CPU time 0.91 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215740 kb
Host smart-01b5f84b-f0f8-4177-8616-4bf04af5598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062173704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1062173704
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.310941343
Short name T372
Test name
Test status
Simulation time 17935903 ps
CPU time 1.01 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215564 kb
Host smart-0b5057da-f0db-44aa-be18-aa7192b07b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310941343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.310941343
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1316136678
Short name T639
Test name
Test status
Simulation time 439352745 ps
CPU time 5.47 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 217456 kb
Host smart-b42f85f3-ea4c-459c-a43c-a8ca26051c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316136678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1316136678
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.502259204
Short name T315
Test name
Test status
Simulation time 406763163449 ps
CPU time 1862.79 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 06:00:51 PM PDT 24
Peak memory 229188 kb
Host smart-2311c9c0-6015-4007-8e4e-1037a4d511ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502259204 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.502259204
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3788405469
Short name T135
Test name
Test status
Simulation time 90869409 ps
CPU time 1.27 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 218844 kb
Host smart-1817e232-2585-4ab0-aff0-fb3a53fb35eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788405469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3788405469
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1548321283
Short name T654
Test name
Test status
Simulation time 307029955 ps
CPU time 0.98 seconds
Started Jul 03 05:31:10 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217744 kb
Host smart-6de8ce3b-fb5a-4127-ac6a-ebd9e493fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548321283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1548321283
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.618705520
Short name T656
Test name
Test status
Simulation time 31340546 ps
CPU time 1.07 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220180 kb
Host smart-9d321aaa-6ec7-4bf2-b501-d17e368bd519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618705520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.618705520
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3698279071
Short name T878
Test name
Test status
Simulation time 57890041 ps
CPU time 1.28 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 218684 kb
Host smart-ae9fae64-eaad-49c6-953d-59c0f3579390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698279071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3698279071
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.4105800722
Short name T641
Test name
Test status
Simulation time 90784286 ps
CPU time 1.16 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 219412 kb
Host smart-ee1a7cc0-d7b4-4bd2-a597-abf73621fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105800722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4105800722
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1705860015
Short name T424
Test name
Test status
Simulation time 58032415 ps
CPU time 1.24 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217676 kb
Host smart-3711814c-607b-4a3b-9977-c9772d0f3bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705860015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1705860015
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2599713638
Short name T113
Test name
Test status
Simulation time 33695332 ps
CPU time 1.42 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 216056 kb
Host smart-97761afa-9dbb-4469-b0aa-06e43b6d915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599713638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2599713638
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.4037147847
Short name T487
Test name
Test status
Simulation time 58410232 ps
CPU time 1.21 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217608 kb
Host smart-8fe65aa9-8ae4-4d72-95c7-6641e6854010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037147847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4037147847
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2026606238
Short name T667
Test name
Test status
Simulation time 54893406 ps
CPU time 1.39 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 219848 kb
Host smart-5ae3aea1-5b81-4d00-a09b-60648a2d09fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026606238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2026606238
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2258601079
Short name T918
Test name
Test status
Simulation time 54047317 ps
CPU time 1.57 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 218780 kb
Host smart-36ee7c0d-8c42-428e-bbf0-d70b00c41c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258601079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2258601079
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3651307464
Short name T1000
Test name
Test status
Simulation time 333102089 ps
CPU time 1.42 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 219416 kb
Host smart-15cce321-f803-41c1-97f0-ce6483132379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651307464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3651307464
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1108670037
Short name T363
Test name
Test status
Simulation time 55338270 ps
CPU time 1 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 217636 kb
Host smart-8bdb9d24-7fa5-48fc-ac93-0d21a7977e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108670037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1108670037
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2605653000
Short name T142
Test name
Test status
Simulation time 31477969 ps
CPU time 1.35 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 215940 kb
Host smart-9386655c-f8e4-4540-9da8-597062d2ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605653000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2605653000
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1542014631
Short name T65
Test name
Test status
Simulation time 55743284 ps
CPU time 1.02 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 218964 kb
Host smart-be8d7c42-3ab8-41d8-95c5-e11032c83653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542014631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1542014631
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1732231053
Short name T575
Test name
Test status
Simulation time 28817249 ps
CPU time 1.38 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220196 kb
Host smart-0e47ec56-443d-45ff-a1ae-d1e219c0af84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732231053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1732231053
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.1077960548
Short name T854
Test name
Test status
Simulation time 28625262 ps
CPU time 1.24 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 215708 kb
Host smart-e99b9782-fc20-4f48-8233-c2851dc95910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077960548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1077960548
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3222824501
Short name T604
Test name
Test status
Simulation time 46197892 ps
CPU time 2.01 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 219108 kb
Host smart-c0674406-b549-43ae-a0e7-30d063572f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222824501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3222824501
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3805187766
Short name T95
Test name
Test status
Simulation time 73499219 ps
CPU time 1.13 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 219008 kb
Host smart-cfd87269-dada-43d0-8730-2a487e667242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805187766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3805187766
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2692752182
Short name T673
Test name
Test status
Simulation time 66918528 ps
CPU time 0.9 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 215536 kb
Host smart-0f57f0d3-f3e9-4619-a536-2977a5a5d544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692752182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2692752182
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.413336681
Short name T176
Test name
Test status
Simulation time 20660925 ps
CPU time 0.87 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 216668 kb
Host smart-1132eab0-56cf-4fc1-9cbb-2c6557e2d607
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413336681 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.413336681
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3855992913
Short name T146
Test name
Test status
Simulation time 66567379 ps
CPU time 1.2 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 217360 kb
Host smart-240f73a0-fd36-43a4-afb3-23f870e86a07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855992913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3855992913
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.3166848859
Short name T331
Test name
Test status
Simulation time 52631401 ps
CPU time 1.25 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 217744 kb
Host smart-7a4abec0-157d-4e5d-af70-1eb82579a7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166848859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3166848859
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.87970059
Short name T690
Test name
Test status
Simulation time 44806023 ps
CPU time 0.95 seconds
Started Jul 03 05:29:52 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 215668 kb
Host smart-7d3dbd56-4cfc-4c47-ae05-12a0a7aa97fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87970059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.87970059
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1450268522
Short name T983
Test name
Test status
Simulation time 171256415 ps
CPU time 2.3 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 220228 kb
Host smart-82f9f46d-5125-439f-927f-b7a8575579f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450268522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1450268522
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3537844728
Short name T439
Test name
Test status
Simulation time 41697682283 ps
CPU time 944.97 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:45:34 PM PDT 24
Peak memory 220760 kb
Host smart-bc4c38a6-56c2-4cc6-82db-43bc445963fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537844728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3537844728
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2227396667
Short name T584
Test name
Test status
Simulation time 45326918 ps
CPU time 1.23 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 218972 kb
Host smart-d78b8136-371f-4a5c-9ab3-a7fdf0ae8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227396667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2227396667
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.307311334
Short name T300
Test name
Test status
Simulation time 27721832 ps
CPU time 1.29 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217480 kb
Host smart-73a87f6b-2ff7-4cf3-addb-83c40a805333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307311334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.307311334
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1479148374
Short name T492
Test name
Test status
Simulation time 31213588 ps
CPU time 1.33 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 220060 kb
Host smart-e58f93fe-2313-4c98-8f22-a73f3c4fd091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479148374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1479148374
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1996330924
Short name T89
Test name
Test status
Simulation time 51231412 ps
CPU time 1.45 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:07 PM PDT 24
Peak memory 218828 kb
Host smart-ec99aa93-3f5b-4c96-b671-e9a450c77614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996330924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1996330924
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3695091226
Short name T623
Test name
Test status
Simulation time 40721760 ps
CPU time 1.21 seconds
Started Jul 03 05:31:02 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 220120 kb
Host smart-42856e65-25ac-4672-bc2a-e10a3da919ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695091226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3695091226
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2732121410
Short name T336
Test name
Test status
Simulation time 259256947 ps
CPU time 3.03 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220440 kb
Host smart-f1ed552d-73d2-4244-81d9-199b31caf8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732121410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2732121410
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2740953011
Short name T470
Test name
Test status
Simulation time 23873445 ps
CPU time 1.17 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 220252 kb
Host smart-069a5614-986f-40fe-b619-29c919c8457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740953011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2740953011
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2067612421
Short name T71
Test name
Test status
Simulation time 96951180 ps
CPU time 1.02 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 217876 kb
Host smart-4ff22aa1-0c24-4a4c-b75d-a10324a0fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067612421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2067612421
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1435481353
Short name T762
Test name
Test status
Simulation time 307716166 ps
CPU time 1.56 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 216068 kb
Host smart-e6a78047-c5cb-4178-a00e-eec52004d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435481353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1435481353
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3020822742
Short name T354
Test name
Test status
Simulation time 151482291 ps
CPU time 2.89 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:12 PM PDT 24
Peak memory 220148 kb
Host smart-1bf3ea9c-9532-434f-917d-c5aff61a2c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020822742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3020822742
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3202109570
Short name T253
Test name
Test status
Simulation time 110458222 ps
CPU time 1.3 seconds
Started Jul 03 05:31:02 PM PDT 24
Finished Jul 03 05:31:04 PM PDT 24
Peak memory 220176 kb
Host smart-77729fcc-6d8d-427d-a669-40f5715fe6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202109570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3202109570
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1092381470
Short name T367
Test name
Test status
Simulation time 32981040 ps
CPU time 1.3 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:23 PM PDT 24
Peak memory 219044 kb
Host smart-e82e6f84-42ad-4ab4-a117-a7d49ffb15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092381470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1092381470
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.264199240
Short name T997
Test name
Test status
Simulation time 25993433 ps
CPU time 1.22 seconds
Started Jul 03 05:31:40 PM PDT 24
Finished Jul 03 05:31:41 PM PDT 24
Peak memory 218896 kb
Host smart-6e72ca1e-49e5-4ccf-8c37-0533d23f3cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264199240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.264199240
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2259989799
Short name T318
Test name
Test status
Simulation time 48663280 ps
CPU time 1.73 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 217620 kb
Host smart-3b073f51-d548-4f5f-ad35-672a87239bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259989799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2259989799
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1427154123
Short name T669
Test name
Test status
Simulation time 57209344 ps
CPU time 1.71 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 218988 kb
Host smart-48d376e5-39d0-4f70-a921-55d72052a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427154123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1427154123
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.4107394189
Short name T292
Test name
Test status
Simulation time 27631739 ps
CPU time 1.25 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 221044 kb
Host smart-0a07ad2e-4411-4063-bd34-380e88b11171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107394189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.4107394189
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.401001739
Short name T880
Test name
Test status
Simulation time 684362435 ps
CPU time 4.39 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 218976 kb
Host smart-6c1dcf5d-a450-4e83-a715-2c4ebb3f681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401001739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.401001739
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2811447846
Short name T456
Test name
Test status
Simulation time 70280321 ps
CPU time 1.19 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 219860 kb
Host smart-59209ac8-f0b5-4da1-b7cb-52c1ff183dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811447846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2811447846
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.2637867354
Short name T546
Test name
Test status
Simulation time 25942048 ps
CPU time 1.2 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 220268 kb
Host smart-3a634e33-9411-4140-988a-7565fa32c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637867354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2637867354
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2115154686
Short name T441
Test name
Test status
Simulation time 31574326 ps
CPU time 1 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 215436 kb
Host smart-ad738f67-88d5-4253-98d0-e4ba468715cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115154686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2115154686
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4043644597
Short name T695
Test name
Test status
Simulation time 88055320 ps
CPU time 1.04 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 218704 kb
Host smart-9399ad21-b360-4b0b-94d4-b067d21323a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043644597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4043644597
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1437876145
Short name T619
Test name
Test status
Simulation time 18457030 ps
CPU time 1.22 seconds
Started Jul 03 05:30:04 PM PDT 24
Finished Jul 03 05:30:05 PM PDT 24
Peak memory 224240 kb
Host smart-cc49a5c6-174e-4154-9e16-40f9069b11c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437876145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1437876145
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.671833736
Short name T943
Test name
Test status
Simulation time 25303788 ps
CPU time 0.99 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 217620 kb
Host smart-d558cecb-87cd-4e73-8b53-cb31479c9940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671833736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.671833736
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4279728839
Short name T375
Test name
Test status
Simulation time 43795554 ps
CPU time 0.94 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215708 kb
Host smart-f11e7049-1c40-4417-a4a5-4193677d2330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279728839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4279728839
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3974863460
Short name T503
Test name
Test status
Simulation time 16929136 ps
CPU time 1.08 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 215508 kb
Host smart-9d21a628-301f-4cfe-8f68-9da200a7a0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974863460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3974863460
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3909454561
Short name T686
Test name
Test status
Simulation time 1116684784 ps
CPU time 3.43 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 217520 kb
Host smart-289e5301-7137-4028-8cb4-9355c87ea9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909454561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3909454561
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.687048459
Short name T469
Test name
Test status
Simulation time 57406789766 ps
CPU time 719.72 seconds
Started Jul 03 05:30:04 PM PDT 24
Finished Jul 03 05:42:10 PM PDT 24
Peak memory 223968 kb
Host smart-6af31b0f-66f5-4095-9a35-a4e1f961a699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687048459 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.687048459
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.963556105
Short name T760
Test name
Test status
Simulation time 26511595 ps
CPU time 1.25 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 220160 kb
Host smart-acb9e874-532a-4c6f-a018-037a29ea2cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963556105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.963556105
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3290309429
Short name T578
Test name
Test status
Simulation time 380871293 ps
CPU time 4.09 seconds
Started Jul 03 05:31:10 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 220192 kb
Host smart-8054b0df-61b9-4f1c-b65e-cc2695c1a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290309429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3290309429
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.577971774
Short name T414
Test name
Test status
Simulation time 190740402 ps
CPU time 1.23 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 219688 kb
Host smart-d4890230-dfc3-4ed0-b59c-07ece4ba1c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577971774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.577971774
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2000451808
Short name T108
Test name
Test status
Simulation time 55177195 ps
CPU time 1.27 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:04 PM PDT 24
Peak memory 219188 kb
Host smart-1bf3936c-0e4f-4304-8d06-2d9d584e0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000451808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2000451808
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3139969016
Short name T11
Test name
Test status
Simulation time 32706146 ps
CPU time 1.15 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 220216 kb
Host smart-c90a360c-9477-4720-8fe0-50ceb213095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139969016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3139969016
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2379502556
Short name T46
Test name
Test status
Simulation time 61912051 ps
CPU time 1.15 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 217512 kb
Host smart-8a3b44ab-935c-4a5e-99a0-cbcaf0a67c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379502556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2379502556
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3529264376
Short name T311
Test name
Test status
Simulation time 46487885 ps
CPU time 1.16 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 217536 kb
Host smart-c4772003-2497-4baf-94b3-49020aedf0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529264376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3529264376
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3111125710
Short name T793
Test name
Test status
Simulation time 47559893 ps
CPU time 1.13 seconds
Started Jul 03 05:31:23 PM PDT 24
Finished Jul 03 05:31:25 PM PDT 24
Peak memory 218912 kb
Host smart-ba25315c-dfad-4805-a9da-882bc44239bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111125710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3111125710
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.389113356
Short name T862
Test name
Test status
Simulation time 273277015 ps
CPU time 3.61 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 220652 kb
Host smart-3f976a9a-8212-4203-a682-ae9075ae164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389113356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.389113356
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2132027693
Short name T601
Test name
Test status
Simulation time 39829037 ps
CPU time 1.11 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 220120 kb
Host smart-fc6b5553-b4e0-49d8-bace-70533d282112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132027693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2132027693
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.362422877
Short name T323
Test name
Test status
Simulation time 36520349 ps
CPU time 1.55 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 218948 kb
Host smart-e7dddd4f-d24e-450c-ae6f-bd349e39abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362422877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.362422877
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.697171910
Short name T655
Test name
Test status
Simulation time 25142738 ps
CPU time 1.2 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 218888 kb
Host smart-9f4d1111-50bc-43dc-97e2-f2eb5deacb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697171910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.697171910
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3624420766
Short name T426
Test name
Test status
Simulation time 79113374 ps
CPU time 1.25 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 217852 kb
Host smart-857b8070-4377-42c3-a9a4-e5662918342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624420766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3624420766
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1806145090
Short name T974
Test name
Test status
Simulation time 86589937 ps
CPU time 2.73 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 218940 kb
Host smart-d5ee7389-6c8d-4d4e-b110-874432508382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806145090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1806145090
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2737863968
Short name T498
Test name
Test status
Simulation time 64007483 ps
CPU time 1.08 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 220980 kb
Host smart-975ee607-d8f9-4f86-b738-c66177987a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737863968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2737863968
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3389078451
Short name T90
Test name
Test status
Simulation time 31004985 ps
CPU time 1.37 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 220216 kb
Host smart-71f65dbc-adb3-45ca-9476-35d16585d4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389078451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3389078451
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1794186448
Short name T894
Test name
Test status
Simulation time 141230246 ps
CPU time 2.95 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 220464 kb
Host smart-26c6e40b-8e5c-4564-bd9f-ee0e7ee6aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794186448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1794186448
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3330208388
Short name T998
Test name
Test status
Simulation time 25225423 ps
CPU time 1.16 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:06 PM PDT 24
Peak memory 219032 kb
Host smart-ff538358-275e-47a8-9614-06611dec0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330208388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3330208388
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1720853030
Short name T64
Test name
Test status
Simulation time 19331554 ps
CPU time 0.89 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 206980 kb
Host smart-912613be-f7a3-4611-88e7-b4d7cda12696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720853030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1720853030
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3419719037
Short name T602
Test name
Test status
Simulation time 38770418 ps
CPU time 1.11 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 218536 kb
Host smart-c76609dc-e883-4ae1-af7f-a35586553320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419719037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3419719037
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3304731536
Short name T157
Test name
Test status
Simulation time 24689526 ps
CPU time 1.29 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 220172 kb
Host smart-24326bcc-e8cb-40f3-b431-2fdde425daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304731536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3304731536
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1120742622
Short name T877
Test name
Test status
Simulation time 37005007 ps
CPU time 1.42 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 220256 kb
Host smart-17a7ef72-77fa-4ef4-9286-a833b1373408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120742622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1120742622
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.353125059
Short name T849
Test name
Test status
Simulation time 72616915 ps
CPU time 0.81 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 215816 kb
Host smart-be748207-15be-4e1f-abe5-8016e401ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353125059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.353125059
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2302893640
Short name T569
Test name
Test status
Simulation time 24055756 ps
CPU time 0.88 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 215576 kb
Host smart-e9be748d-5131-403b-8384-6f071d119ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302893640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2302893640
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3636320030
Short name T377
Test name
Test status
Simulation time 57915160 ps
CPU time 1.79 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 215612 kb
Host smart-496f99c1-aa6b-40cf-82b0-dccb5637875d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636320030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3636320030
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.59176571
Short name T677
Test name
Test status
Simulation time 48848524871 ps
CPU time 268.64 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:34:20 PM PDT 24
Peak memory 218068 kb
Host smart-b9cdba5e-0ddc-42c7-8031-2bc5e6791b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59176571 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.59176571
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2471776240
Short name T141
Test name
Test status
Simulation time 126801528 ps
CPU time 1.16 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 218852 kb
Host smart-a76790a2-ebc6-48c9-93aa-c0b07d699743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471776240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2471776240
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2048154501
Short name T27
Test name
Test status
Simulation time 53403369 ps
CPU time 1.41 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 218688 kb
Host smart-d96245d8-a4f0-4d8b-8019-4cdc353debaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048154501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2048154501
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.261614331
Short name T765
Test name
Test status
Simulation time 95610036 ps
CPU time 1.25 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 216052 kb
Host smart-3ec403ea-b5c6-4c3b-ab06-0519cfe84182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261614331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.261614331
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.460686654
Short name T334
Test name
Test status
Simulation time 227615404 ps
CPU time 3.06 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 220620 kb
Host smart-f4258d00-f267-4b08-b774-528198003967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460686654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.460686654
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4128908984
Short name T681
Test name
Test status
Simulation time 22351096 ps
CPU time 1.17 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 221192 kb
Host smart-64a2b636-af36-4d32-a959-16929f1b1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128908984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4128908984
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.324141987
Short name T956
Test name
Test status
Simulation time 54592394 ps
CPU time 1.68 seconds
Started Jul 03 05:31:22 PM PDT 24
Finished Jul 03 05:31:24 PM PDT 24
Peak memory 217624 kb
Host smart-1751afbc-55c4-4018-8b40-67d209a9501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324141987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.324141987
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1682875414
Short name T622
Test name
Test status
Simulation time 32622944 ps
CPU time 1.22 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 219996 kb
Host smart-95840189-16c7-46e9-822d-95b9fe0ad7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682875414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1682875414
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.4057313136
Short name T547
Test name
Test status
Simulation time 124994690 ps
CPU time 1.13 seconds
Started Jul 03 05:31:16 PM PDT 24
Finished Jul 03 05:31:18 PM PDT 24
Peak memory 217664 kb
Host smart-3ea925a6-ada0-421d-9aaf-fa62f0209c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057313136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4057313136
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1683282849
Short name T526
Test name
Test status
Simulation time 41862065 ps
CPU time 1.19 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 220480 kb
Host smart-43b29c95-9f7b-44dd-998d-735d97752c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683282849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1683282849
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.546812070
Short name T989
Test name
Test status
Simulation time 44274818 ps
CPU time 1.37 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 218852 kb
Host smart-daac157f-4d8c-4f3f-8688-aa217d5abb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546812070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.546812070
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2025657698
Short name T897
Test name
Test status
Simulation time 70339954 ps
CPU time 1.21 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:23 PM PDT 24
Peak memory 218960 kb
Host smart-d24020ff-c5a0-4c14-b16b-43fe61bdc426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025657698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2025657698
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3912527920
Short name T434
Test name
Test status
Simulation time 76447122 ps
CPU time 2.46 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 220116 kb
Host smart-d8a5a554-96f9-48fd-97f1-2bc380a30841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912527920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3912527920
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2840096277
Short name T988
Test name
Test status
Simulation time 27416742 ps
CPU time 1.13 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 218792 kb
Host smart-9aeb74a4-e3d5-4a28-bd38-6a792f57e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840096277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2840096277
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.327622963
Short name T332
Test name
Test status
Simulation time 57526616 ps
CPU time 1.45 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 218896 kb
Host smart-17ea1bba-ca2a-49ed-a9c0-1d9f35291e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327622963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.327622963
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1465762286
Short name T937
Test name
Test status
Simulation time 22461902 ps
CPU time 1.12 seconds
Started Jul 03 05:31:24 PM PDT 24
Finished Jul 03 05:31:26 PM PDT 24
Peak memory 219868 kb
Host smart-e4c59f85-ee4d-4c44-87c4-d2f4ef43319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465762286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1465762286
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2225394413
Short name T957
Test name
Test status
Simulation time 58234588 ps
CPU time 1.29 seconds
Started Jul 03 05:31:16 PM PDT 24
Finished Jul 03 05:31:18 PM PDT 24
Peak memory 219300 kb
Host smart-ec831e5f-2b88-432d-aa31-40dcfa060911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225394413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2225394413
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.4102623947
Short name T533
Test name
Test status
Simulation time 27122034 ps
CPU time 1.2 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:10 PM PDT 24
Peak memory 220004 kb
Host smart-55961798-9b05-4cfa-8cfd-bfc35bad5771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102623947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.4102623947
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.4122297332
Short name T942
Test name
Test status
Simulation time 40336728 ps
CPU time 1.42 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 218720 kb
Host smart-5363f6af-33c6-4745-bfe2-69df78be6c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122297332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.4122297332
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4119742209
Short name T520
Test name
Test status
Simulation time 103515484 ps
CPU time 1.09 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 220208 kb
Host smart-95411796-61af-481b-ad45-a190f2f46c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119742209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4119742209
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2514654137
Short name T392
Test name
Test status
Simulation time 379520217 ps
CPU time 1.57 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 219400 kb
Host smart-eb65268e-0693-4816-8145-8bc4b4525c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514654137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2514654137
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2252467667
Short name T231
Test name
Test status
Simulation time 123766921 ps
CPU time 1.18 seconds
Started Jul 03 05:29:52 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 220008 kb
Host smart-0db523c6-58ec-45dc-8528-e98154e96c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252467667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2252467667
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2927916577
Short name T477
Test name
Test status
Simulation time 29102785 ps
CPU time 1.14 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 207008 kb
Host smart-58ff6568-fb6f-4f22-b8fe-b21adc0ea596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927916577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2927916577
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2918657377
Short name T590
Test name
Test status
Simulation time 30159921 ps
CPU time 0.82 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 215716 kb
Host smart-fd7b7490-20bf-43a7-aa34-b924bb16014a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918657377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2918657377
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.4134877715
Short name T478
Test name
Test status
Simulation time 20629860 ps
CPU time 1.17 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 218764 kb
Host smart-61647c49-f60f-4cd8-8158-99f3fde3d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134877715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4134877715
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.298908643
Short name T73
Test name
Test status
Simulation time 35704190 ps
CPU time 1.43 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 217580 kb
Host smart-e7ff76a2-57d5-4f2b-9c0f-daf84ff9e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298908643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.298908643
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1933766133
Short name T502
Test name
Test status
Simulation time 35265739 ps
CPU time 0.91 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 215788 kb
Host smart-d2d82c10-f256-4dd0-90b2-961fa08004c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933766133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1933766133
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3657857072
Short name T376
Test name
Test status
Simulation time 19141378 ps
CPU time 1.07 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 215560 kb
Host smart-99b44042-92f3-4d60-88bf-9f10d613e722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657857072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3657857072
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2363089734
Short name T592
Test name
Test status
Simulation time 761390226 ps
CPU time 2.39 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 215588 kb
Host smart-1cf2f457-23c7-41f3-89e1-6714e3863352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363089734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2363089734
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2363036720
Short name T40
Test name
Test status
Simulation time 53199132276 ps
CPU time 1195.28 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:49:51 PM PDT 24
Peak memory 220068 kb
Host smart-d35ac653-f138-44ad-875b-33dd7398e4bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363036720 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2363036720
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3113487569
Short name T984
Test name
Test status
Simulation time 182008151 ps
CPU time 1.18 seconds
Started Jul 03 05:31:14 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 218808 kb
Host smart-6514f5ca-95e6-47ad-b7c3-d06e40683e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113487569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3113487569
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2379980439
Short name T490
Test name
Test status
Simulation time 46245542 ps
CPU time 1.64 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 218712 kb
Host smart-f7a40a10-e4ce-4236-a798-bc0857dcc960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379980439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2379980439
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3919942433
Short name T814
Test name
Test status
Simulation time 24084480 ps
CPU time 1.14 seconds
Started Jul 03 05:31:14 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 216032 kb
Host smart-ff7132ed-f470-4d5a-ace2-1df38d6249ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919942433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3919942433
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3332085982
Short name T255
Test name
Test status
Simulation time 147825575 ps
CPU time 1.19 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 220252 kb
Host smart-4df1e689-d691-4b27-a16f-f4999e597aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332085982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3332085982
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.414638034
Short name T657
Test name
Test status
Simulation time 53556018 ps
CPU time 1.3 seconds
Started Jul 03 05:31:12 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 216024 kb
Host smart-54c194eb-520f-4abe-a130-2e2a6d4bf3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414638034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.414638034
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.2588147621
Short name T406
Test name
Test status
Simulation time 29262677 ps
CPU time 1.24 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 219984 kb
Host smart-57ff9c76-07cb-49d2-b198-5e4497102611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588147621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2588147621
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.513003063
Short name T42
Test name
Test status
Simulation time 85046925 ps
CPU time 1.71 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:15 PM PDT 24
Peak memory 219196 kb
Host smart-b15d18cf-263e-4fb0-80b9-c742d4c421a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513003063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.513003063
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2875525230
Short name T876
Test name
Test status
Simulation time 352648530 ps
CPU time 1.17 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 217656 kb
Host smart-c58d4c54-cc33-49c0-a82f-2bd0f17947dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875525230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2875525230
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.447153859
Short name T890
Test name
Test status
Simulation time 51495394 ps
CPU time 1.17 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 220124 kb
Host smart-5bfcbbdc-561c-42af-b8bb-d05e6a8496e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447153859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.447153859
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.144218882
Short name T692
Test name
Test status
Simulation time 62193071 ps
CPU time 1.3 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 217632 kb
Host smart-bcaed397-be75-40ee-94d4-07707cc0fadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144218882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.144218882
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3767438586
Short name T901
Test name
Test status
Simulation time 28525287 ps
CPU time 1.2 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 216004 kb
Host smart-b3e5ba0d-9d36-40ed-ae48-33e4e40c0d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767438586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3767438586
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3766065399
Short name T728
Test name
Test status
Simulation time 68929160 ps
CPU time 1.12 seconds
Started Jul 03 05:31:11 PM PDT 24
Finished Jul 03 05:31:12 PM PDT 24
Peak memory 219428 kb
Host smart-0c5d812b-24e4-4dc1-875f-184b15539418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766065399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3766065399
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2541909204
Short name T716
Test name
Test status
Simulation time 29116642 ps
CPU time 1.24 seconds
Started Jul 03 05:31:13 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 215980 kb
Host smart-2679bab2-b386-4e92-9968-4b58056a7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541909204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2541909204
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2839920173
Short name T672
Test name
Test status
Simulation time 231864733 ps
CPU time 2.03 seconds
Started Jul 03 05:31:24 PM PDT 24
Finished Jul 03 05:31:26 PM PDT 24
Peak memory 218944 kb
Host smart-695a9adf-90e3-4de8-ae33-fb884a4fd30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839920173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2839920173
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3029757428
Short name T638
Test name
Test status
Simulation time 38804062 ps
CPU time 1.1 seconds
Started Jul 03 05:31:24 PM PDT 24
Finished Jul 03 05:31:25 PM PDT 24
Peak memory 220176 kb
Host smart-cd4485e2-70bd-4f12-94d3-9d151fb051e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029757428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3029757428
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3707840919
Short name T543
Test name
Test status
Simulation time 38674358 ps
CPU time 1.36 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 217644 kb
Host smart-763b50dc-7d78-4dc8-bf27-42dab37a06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707840919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3707840919
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2061991534
Short name T348
Test name
Test status
Simulation time 30964722 ps
CPU time 1.28 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:35 PM PDT 24
Peak memory 220168 kb
Host smart-b8ec1a47-bcf7-4867-a4ef-1445edf6b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061991534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2061991534
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1101402413
Short name T482
Test name
Test status
Simulation time 117167518 ps
CPU time 1.28 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 217704 kb
Host smart-e0d6b5a1-6236-40ec-89df-9b153ebacdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101402413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1101402413
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.471182612
Short name T79
Test name
Test status
Simulation time 40506551 ps
CPU time 1.15 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 219580 kb
Host smart-b64534f5-2250-4ab5-adf3-47495066b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471182612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.471182612
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3502769364
Short name T767
Test name
Test status
Simulation time 21488776 ps
CPU time 0.84 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 207076 kb
Host smart-93163523-3bf5-4194-8113-84291f7d5bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502769364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3502769364
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3071640552
Short name T205
Test name
Test status
Simulation time 27671091 ps
CPU time 0.93 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 216640 kb
Host smart-0f893fea-4f4e-4081-b1cc-89ed36a4c5f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071640552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3071640552
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1689006844
Short name T888
Test name
Test status
Simulation time 37738484 ps
CPU time 0.96 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 218524 kb
Host smart-46698679-b0bd-49b9-95ac-7bdcd5f9dd55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689006844 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1689006844
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2683680263
Short name T218
Test name
Test status
Simulation time 23320489 ps
CPU time 0.91 seconds
Started Jul 03 05:29:52 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 218892 kb
Host smart-f05db495-ab89-4723-ae2f-cda70b0390b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683680263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2683680263
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.3071114657
Short name T905
Test name
Test status
Simulation time 30454190 ps
CPU time 0.94 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 215776 kb
Host smart-99105955-b84a-4337-ac2c-fd18424deb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071114657 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3071114657
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2137040087
Short name T808
Test name
Test status
Simulation time 16674008 ps
CPU time 0.98 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 215576 kb
Host smart-04a287ca-7e31-4ba7-8764-a8a688734448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137040087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2137040087
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4180035315
Short name T505
Test name
Test status
Simulation time 596665466 ps
CPU time 6.12 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 218868 kb
Host smart-20bbd098-28d3-4563-ab33-15bffd94376a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180035315 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4180035315
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3229954347
Short name T464
Test name
Test status
Simulation time 79929781495 ps
CPU time 961.56 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:46:04 PM PDT 24
Peak memory 223560 kb
Host smart-27f3c089-1b22-4078-9f96-755d01bc37dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229954347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3229954347
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.694033174
Short name T123
Test name
Test status
Simulation time 96154783 ps
CPU time 1.13 seconds
Started Jul 03 05:31:24 PM PDT 24
Finished Jul 03 05:31:26 PM PDT 24
Peak memory 218672 kb
Host smart-49292c5b-24e2-4c02-80d6-d01f3101986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694033174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.694033174
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1118193571
Short name T899
Test name
Test status
Simulation time 244325581 ps
CPU time 1.54 seconds
Started Jul 03 05:31:31 PM PDT 24
Finished Jul 03 05:31:33 PM PDT 24
Peak memory 219296 kb
Host smart-b94c96b2-9eca-4114-b85d-08037fcc2618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118193571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1118193571
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2098678190
Short name T664
Test name
Test status
Simulation time 32868980 ps
CPU time 1.25 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 216060 kb
Host smart-8065ea41-4af8-43c1-a309-559afb8a571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098678190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2098678190
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3066426126
Short name T106
Test name
Test status
Simulation time 103363474 ps
CPU time 1.63 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 219072 kb
Host smart-018cc0c2-0c8f-4a10-85e7-34a287e363ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066426126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3066426126
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3578932331
Short name T586
Test name
Test status
Simulation time 23117534 ps
CPU time 1.17 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 220232 kb
Host smart-3b9cd45d-9fc2-4d24-b930-288b8810cffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578932331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3578932331
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1794365248
Short name T549
Test name
Test status
Simulation time 70737306 ps
CPU time 1.47 seconds
Started Jul 03 05:31:18 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 220440 kb
Host smart-f7a23144-548a-4642-93fe-5846b7a3a3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794365248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1794365248
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2241156849
Short name T651
Test name
Test status
Simulation time 66721493 ps
CPU time 1.08 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 218924 kb
Host smart-285c8199-5d01-4ac9-a2a9-50be87c0804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241156849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2241156849
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1489915431
Short name T922
Test name
Test status
Simulation time 394920194 ps
CPU time 1.43 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 220428 kb
Host smart-c3e08201-f36f-4e64-81fd-c20bf055e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489915431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1489915431
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2604084168
Short name T947
Test name
Test status
Simulation time 38214288 ps
CPU time 1.13 seconds
Started Jul 03 05:31:30 PM PDT 24
Finished Jul 03 05:31:31 PM PDT 24
Peak memory 218808 kb
Host smart-e4028f49-5690-4392-9dc1-0fc319676648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604084168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2604084168
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3473069956
Short name T560
Test name
Test status
Simulation time 59362305 ps
CPU time 2.5 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 219404 kb
Host smart-e14f6801-3782-424e-8b3a-628e1722cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473069956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3473069956
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3132747261
Short name T93
Test name
Test status
Simulation time 32034540 ps
CPU time 1.21 seconds
Started Jul 03 05:31:22 PM PDT 24
Finished Jul 03 05:31:24 PM PDT 24
Peak memory 221488 kb
Host smart-b69a75e6-d407-4fa1-8977-605c312ccd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132747261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3132747261
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2927272916
Short name T94
Test name
Test status
Simulation time 36682391 ps
CPU time 1.64 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 218852 kb
Host smart-b74b98c4-8bcc-4b86-8e96-c9e1b562556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927272916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2927272916
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1966008839
Short name T164
Test name
Test status
Simulation time 68507874 ps
CPU time 1.14 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 219720 kb
Host smart-bc72ed2e-f120-46f5-9cf3-02f14d2a765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966008839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1966008839
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.286974801
Short name T531
Test name
Test status
Simulation time 57304134 ps
CPU time 1.21 seconds
Started Jul 03 05:31:27 PM PDT 24
Finished Jul 03 05:31:29 PM PDT 24
Peak memory 219512 kb
Host smart-9351b70f-7cba-443e-856b-dae07d3d1018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286974801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.286974801
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2377346035
Short name T733
Test name
Test status
Simulation time 42727728 ps
CPU time 1.47 seconds
Started Jul 03 05:31:32 PM PDT 24
Finished Jul 03 05:31:34 PM PDT 24
Peak memory 215668 kb
Host smart-41afb3fc-7024-46be-99e8-874925217c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377346035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2377346035
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1765939997
Short name T22
Test name
Test status
Simulation time 65941876 ps
CPU time 1.51 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 220672 kb
Host smart-fde0924f-2ddd-4051-9420-2b64321b2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765939997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1765939997
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2294902764
Short name T149
Test name
Test status
Simulation time 49460821 ps
CPU time 1.22 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 218724 kb
Host smart-1da0e282-2d3b-48e4-990b-812b9603b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294902764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2294902764
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.893781152
Short name T661
Test name
Test status
Simulation time 200476717 ps
CPU time 3.57 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:57 PM PDT 24
Peak memory 218924 kb
Host smart-1d4cd9db-eb3a-4422-8147-c1bf68e02129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893781152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.893781152
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.219594866
Short name T472
Test name
Test status
Simulation time 103045602 ps
CPU time 1.3 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 220128 kb
Host smart-e2118d5f-21f5-4680-8c18-074a1699831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219594866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.219594866
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1280698438
Short name T778
Test name
Test status
Simulation time 14778132 ps
CPU time 0.93 seconds
Started Jul 03 05:30:04 PM PDT 24
Finished Jul 03 05:30:06 PM PDT 24
Peak memory 206992 kb
Host smart-354a9dab-a686-4e8c-93bb-ae31ab628508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280698438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1280698438
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.765981576
Short name T181
Test name
Test status
Simulation time 18030291 ps
CPU time 0.84 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 216592 kb
Host smart-89fa19d9-abf8-47c1-bb34-4e62ad58ced3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765981576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.765981576
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2405554681
Short name T861
Test name
Test status
Simulation time 56412793 ps
CPU time 1.18 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 219040 kb
Host smart-e1583c04-a3db-47f0-a9e7-0fb634cec3d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405554681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2405554681
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1463801998
Short name T222
Test name
Test status
Simulation time 136195543 ps
CPU time 1.12 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 219940 kb
Host smart-b67a749e-b135-4ebc-b0ea-8b6981277e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463801998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1463801998
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2201412484
Short name T964
Test name
Test status
Simulation time 42394208 ps
CPU time 1.49 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 219092 kb
Host smart-c0267bf5-2bbe-435a-b612-69ed06cbc75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201412484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2201412484
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.197303579
Short name T53
Test name
Test status
Simulation time 49753211 ps
CPU time 0.87 seconds
Started Jul 03 05:29:57 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 215564 kb
Host smart-050b7059-03e0-440b-b35b-8535428a8bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197303579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.197303579
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3624801172
Short name T423
Test name
Test status
Simulation time 43353924 ps
CPU time 0.98 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 215608 kb
Host smart-f77f47dd-e538-4c27-b7a6-f4739e928936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624801172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3624801172
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1675834637
Short name T968
Test name
Test status
Simulation time 507190829 ps
CPU time 5.13 seconds
Started Jul 03 05:30:04 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 217428 kb
Host smart-b0ba4655-64b4-4de6-ab3a-529b78ea015e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675834637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1675834637
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.2148516053
Short name T116
Test name
Test status
Simulation time 87247725 ps
CPU time 1.2 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:22 PM PDT 24
Peak memory 218808 kb
Host smart-d411efc0-09d9-4195-8500-1e2bdc0bf36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148516053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2148516053
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1736843962
Short name T365
Test name
Test status
Simulation time 45753765 ps
CPU time 1.7 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 218904 kb
Host smart-90de8874-6d6f-457b-93c7-3fd5f9d4f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736843962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1736843962
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3236737165
Short name T504
Test name
Test status
Simulation time 103098493 ps
CPU time 1.14 seconds
Started Jul 03 05:31:16 PM PDT 24
Finished Jul 03 05:31:18 PM PDT 24
Peak memory 219348 kb
Host smart-5f52a378-454a-4c79-9c59-c8e45ee2a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236737165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3236737165
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3835123765
Short name T247
Test name
Test status
Simulation time 36103236 ps
CPU time 1.03 seconds
Started Jul 03 05:31:30 PM PDT 24
Finished Jul 03 05:31:32 PM PDT 24
Peak memory 217728 kb
Host smart-e268caa0-8545-42f4-be85-ae45f9e7c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835123765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3835123765
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3029126082
Short name T343
Test name
Test status
Simulation time 36764709 ps
CPU time 1.07 seconds
Started Jul 03 05:31:29 PM PDT 24
Finished Jul 03 05:31:30 PM PDT 24
Peak memory 218760 kb
Host smart-95133301-7c34-4074-9207-556e4af5ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029126082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3029126082
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.141710075
Short name T234
Test name
Test status
Simulation time 37289479 ps
CPU time 1.36 seconds
Started Jul 03 05:31:25 PM PDT 24
Finished Jul 03 05:31:27 PM PDT 24
Peak memory 219900 kb
Host smart-8ec2e2a3-6509-444a-a260-8ca8e0170701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141710075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.141710075
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.77589001
Short name T907
Test name
Test status
Simulation time 21319696 ps
CPU time 1.15 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:51 PM PDT 24
Peak memory 220064 kb
Host smart-bc076a26-1b27-4803-a6b9-9233e740b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77589001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.77589001
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2993880035
Short name T804
Test name
Test status
Simulation time 132348575 ps
CPU time 1.23 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 217560 kb
Host smart-3561a47f-cf68-4edb-8713-1c6d05d4fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993880035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2993880035
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.4185998359
Short name T944
Test name
Test status
Simulation time 31076876 ps
CPU time 1.29 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 215976 kb
Host smart-6591d5d8-a47b-485f-a7eb-915fd842be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185998359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4185998359
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2384979042
Short name T360
Test name
Test status
Simulation time 103717798 ps
CPU time 1.32 seconds
Started Jul 03 05:31:20 PM PDT 24
Finished Jul 03 05:31:22 PM PDT 24
Peak memory 219088 kb
Host smart-7252b7c7-8b3b-418b-acd7-b8b0c2c5a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384979042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2384979042
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3563303024
Short name T616
Test name
Test status
Simulation time 41411264 ps
CPU time 1.57 seconds
Started Jul 03 05:31:22 PM PDT 24
Finished Jul 03 05:31:24 PM PDT 24
Peak memory 218700 kb
Host smart-2a01d033-e04b-4c42-a480-3a9c3af4ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563303024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3563303024
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1580593394
Short name T124
Test name
Test status
Simulation time 22208986 ps
CPU time 1.16 seconds
Started Jul 03 05:31:19 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 219932 kb
Host smart-b508505c-50d2-48bc-82e2-34f0f5220032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580593394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1580593394
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1739461440
Short name T791
Test name
Test status
Simulation time 94899676 ps
CPU time 1.11 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:34 PM PDT 24
Peak memory 219172 kb
Host smart-623fa0e5-11b2-4a7b-b164-4bb3c89dec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739461440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1739461440
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1209274699
Short name T676
Test name
Test status
Simulation time 69136018 ps
CPU time 1.14 seconds
Started Jul 03 05:31:30 PM PDT 24
Finished Jul 03 05:31:32 PM PDT 24
Peak memory 219844 kb
Host smart-c5d3f624-449d-43e4-92d8-c8318dfafbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209274699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1209274699
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.4253598508
Short name T447
Test name
Test status
Simulation time 66446164 ps
CPU time 1.14 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:35 PM PDT 24
Peak memory 219856 kb
Host smart-45e179cd-f935-4831-a499-0b22cdccc84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253598508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.4253598508
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2127024101
Short name T635
Test name
Test status
Simulation time 56229798 ps
CPU time 1.6 seconds
Started Jul 03 05:31:42 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 215572 kb
Host smart-40c92f57-17f4-4c8a-b51f-bbf6bf07cc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127024101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2127024101
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.791529659
Short name T147
Test name
Test status
Simulation time 25575660 ps
CPU time 1.12 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 218828 kb
Host smart-6dab7eb5-54ce-49db-8c1a-753c8ae66d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791529659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.791529659
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.29315882
Short name T970
Test name
Test status
Simulation time 50471501 ps
CPU time 0.89 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 215528 kb
Host smart-37312caf-f273-4774-82f3-86ffd87e914f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.29315882
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.2194542000
Short name T126
Test name
Test status
Simulation time 35240235 ps
CPU time 1.12 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 220960 kb
Host smart-4fcde0e2-d399-41fe-8fc1-373de4b35b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194542000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2194542000
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1660721724
Short name T374
Test name
Test status
Simulation time 92227964 ps
CPU time 1.2 seconds
Started Jul 03 05:29:53 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 218796 kb
Host smart-b9081a03-58a6-4f5d-8e4c-7d1a045e878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660721724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1660721724
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1107454639
Short name T366
Test name
Test status
Simulation time 35181086 ps
CPU time 0.95 seconds
Started Jul 03 05:29:54 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 215912 kb
Host smart-61377018-e5b4-45d1-a8de-3ba91979e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107454639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1107454639
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2765780069
Short name T109
Test name
Test status
Simulation time 17888330 ps
CPU time 1.06 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:04 PM PDT 24
Peak memory 215528 kb
Host smart-dc1bf02c-1d05-4ef7-9c49-e8f7a7742d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765780069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2765780069
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3019985907
Short name T568
Test name
Test status
Simulation time 112667804 ps
CPU time 2.49 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 215616 kb
Host smart-3bf20382-9c16-49f0-9b88-0a6c4f9b4807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019985907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3019985907
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3458016942
Short name T726
Test name
Test status
Simulation time 74992615354 ps
CPU time 1870.06 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 06:01:16 PM PDT 24
Peak memory 236576 kb
Host smart-6d0cb1ef-5e7b-4bff-809f-3c7b9d0432a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458016942 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3458016942
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3481434343
Short name T599
Test name
Test status
Simulation time 78217315 ps
CPU time 1.09 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:22 PM PDT 24
Peak memory 218632 kb
Host smart-624f8e1e-741c-44e4-a7fc-5554796950a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481434343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3481434343
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3857111716
Short name T850
Test name
Test status
Simulation time 33464218 ps
CPU time 1.39 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 218976 kb
Host smart-f788e53d-73ed-421d-bfba-b416292ec0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857111716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3857111716
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1244480364
Short name T182
Test name
Test status
Simulation time 44861979 ps
CPU time 1.16 seconds
Started Jul 03 05:31:23 PM PDT 24
Finished Jul 03 05:31:24 PM PDT 24
Peak memory 219984 kb
Host smart-18408e95-31f3-4552-b78f-c3e42415d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244480364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1244480364
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1522201775
Short name T731
Test name
Test status
Simulation time 299170398 ps
CPU time 3.95 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:41 PM PDT 24
Peak memory 218796 kb
Host smart-9f608598-7a63-422b-93cf-a85f8864111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522201775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1522201775
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2465248050
Short name T642
Test name
Test status
Simulation time 26500901 ps
CPU time 1.19 seconds
Started Jul 03 05:31:30 PM PDT 24
Finished Jul 03 05:31:31 PM PDT 24
Peak memory 220252 kb
Host smart-81d1893a-860f-493d-96ce-b63268f880cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465248050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2465248050
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3667390652
Short name T930
Test name
Test status
Simulation time 44215095 ps
CPU time 1.6 seconds
Started Jul 03 05:31:44 PM PDT 24
Finished Jul 03 05:31:46 PM PDT 24
Peak memory 218880 kb
Host smart-34dc4333-b567-4667-9e44-b2c5b76b5518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667390652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3667390652
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3681691531
Short name T346
Test name
Test status
Simulation time 28095347 ps
CPU time 1.25 seconds
Started Jul 03 05:31:23 PM PDT 24
Finished Jul 03 05:31:25 PM PDT 24
Peak memory 220256 kb
Host smart-ada7cf4c-0767-46b4-8ff6-7418a2c7c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681691531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3681691531
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1789335713
Short name T537
Test name
Test status
Simulation time 344268834 ps
CPU time 2.7 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:24 PM PDT 24
Peak memory 218912 kb
Host smart-49e6c2d9-4d14-4ba2-9d7e-1f5262586b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789335713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1789335713
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3496475594
Short name T925
Test name
Test status
Simulation time 59423903 ps
CPU time 1.02 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 218788 kb
Host smart-e207abfb-076f-405e-ba14-601e1c8fa1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496475594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3496475594
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3430213506
Short name T75
Test name
Test status
Simulation time 132106210 ps
CPU time 1.32 seconds
Started Jul 03 05:31:42 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 219132 kb
Host smart-b3349350-5b74-42b3-823d-b69093043a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430213506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3430213506
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.563839875
Short name T749
Test name
Test status
Simulation time 80001644 ps
CPU time 1.11 seconds
Started Jul 03 05:31:35 PM PDT 24
Finished Jul 03 05:31:36 PM PDT 24
Peak memory 220016 kb
Host smart-5f6b7bdc-3498-46e1-b175-f0b9fe80de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563839875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.563839875
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1472205524
Short name T670
Test name
Test status
Simulation time 110379996 ps
CPU time 1.11 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 217648 kb
Host smart-371ff9f2-f8f0-4b22-b16f-11a555f9db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472205524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1472205524
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2673027034
Short name T131
Test name
Test status
Simulation time 39104460 ps
CPU time 1.21 seconds
Started Jul 03 05:31:34 PM PDT 24
Finished Jul 03 05:31:36 PM PDT 24
Peak memory 219904 kb
Host smart-a5626d7f-6a52-4a7b-9c8e-3343b532ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673027034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2673027034
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3844592047
Short name T750
Test name
Test status
Simulation time 49949980 ps
CPU time 1.36 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 218860 kb
Host smart-8404d61e-2b26-4957-bd0f-08b129e96cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844592047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3844592047
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.105368679
Short name T183
Test name
Test status
Simulation time 41790377 ps
CPU time 1.08 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:27 PM PDT 24
Peak memory 221108 kb
Host smart-af915544-2c4b-4a16-907a-1571d6abbc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105368679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.105368679
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.765095180
Short name T797
Test name
Test status
Simulation time 27372555 ps
CPU time 1.21 seconds
Started Jul 03 05:31:25 PM PDT 24
Finished Jul 03 05:31:27 PM PDT 24
Peak memory 219840 kb
Host smart-58dae4c7-50c7-462d-8382-e314c85951b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765095180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.765095180
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2225497635
Short name T293
Test name
Test status
Simulation time 337701732 ps
CPU time 1.33 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:35 PM PDT 24
Peak memory 220172 kb
Host smart-6db8b81d-2230-4011-a6cf-f87e578759c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225497635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2225497635
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3039523907
Short name T538
Test name
Test status
Simulation time 53723489 ps
CPU time 1.09 seconds
Started Jul 03 05:31:35 PM PDT 24
Finished Jul 03 05:31:37 PM PDT 24
Peak memory 219012 kb
Host smart-077bafa9-e87d-4388-9e7b-c2c36940b271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039523907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3039523907
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2048640842
Short name T233
Test name
Test status
Simulation time 95224323 ps
CPU time 1.28 seconds
Started Jul 03 05:31:44 PM PDT 24
Finished Jul 03 05:31:46 PM PDT 24
Peak memory 220564 kb
Host smart-7db6867d-dfee-4aac-9a68-8eab4de4f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048640842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2048640842
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1106318296
Short name T710
Test name
Test status
Simulation time 58081425 ps
CPU time 1.31 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 217932 kb
Host smart-a2736c53-9b49-4079-91bb-be381d064374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106318296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1106318296
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2372576473
Short name T177
Test name
Test status
Simulation time 40909973 ps
CPU time 1.13 seconds
Started Jul 03 05:29:33 PM PDT 24
Finished Jul 03 05:29:35 PM PDT 24
Peak memory 219092 kb
Host smart-92042cf3-507a-4be9-ab71-31adc2fa0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372576473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2372576473
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2797578865
Short name T824
Test name
Test status
Simulation time 40664589 ps
CPU time 0.84 seconds
Started Jul 03 05:29:34 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 206832 kb
Host smart-973c6642-3430-4fa6-a0be-c2c21df3ce23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797578865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2797578865
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2197476490
Short name T413
Test name
Test status
Simulation time 11610885 ps
CPU time 0.9 seconds
Started Jul 03 05:29:33 PM PDT 24
Finished Jul 03 05:29:34 PM PDT 24
Peak memory 216292 kb
Host smart-b3f8d723-662d-46a9-9bbe-76ee82fed4f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197476490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2197476490
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1761456248
Short name T969
Test name
Test status
Simulation time 125316570 ps
CPU time 1.07 seconds
Started Jul 03 05:29:33 PM PDT 24
Finished Jul 03 05:29:35 PM PDT 24
Peak memory 218684 kb
Host smart-c3e7fa62-89c3-4886-be38-f41acb34864c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761456248 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1761456248
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2663819940
Short name T815
Test name
Test status
Simulation time 19319256 ps
CPU time 1.01 seconds
Started Jul 03 05:29:50 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 218644 kb
Host smart-7edc55a6-4b5c-4363-a71d-d6196c790a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663819940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2663819940
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1264156412
Short name T783
Test name
Test status
Simulation time 257884469 ps
CPU time 1.1 seconds
Started Jul 03 05:29:40 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 217672 kb
Host smart-56814b27-5c7c-462f-9f97-a1ce253dec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264156412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1264156412
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1255142585
Short name T818
Test name
Test status
Simulation time 19342653 ps
CPU time 0.95 seconds
Started Jul 03 05:29:31 PM PDT 24
Finished Jul 03 05:29:33 PM PDT 24
Peak memory 207440 kb
Host smart-061d0777-a334-47b8-8588-7383bd9dad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255142585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1255142585
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2881109466
Short name T60
Test name
Test status
Simulation time 251850415 ps
CPU time 4.54 seconds
Started Jul 03 05:29:34 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 235936 kb
Host smart-82c801c6-111c-4462-99ff-9ebc10c6f9fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881109466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2881109466
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3042676496
Short name T358
Test name
Test status
Simulation time 44420449 ps
CPU time 0.91 seconds
Started Jul 03 05:29:30 PM PDT 24
Finished Jul 03 05:29:31 PM PDT 24
Peak memory 215604 kb
Host smart-b0078c98-2814-4301-b49d-6d54b60c01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042676496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3042676496
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2784225013
Short name T337
Test name
Test status
Simulation time 326814019 ps
CPU time 6.48 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 218808 kb
Host smart-e421af08-d863-4848-b498-f873bb5fd614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784225013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2784225013
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1774168655
Short name T685
Test name
Test status
Simulation time 65140142431 ps
CPU time 833.76 seconds
Started Jul 03 05:29:38 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 221888 kb
Host smart-ee7add39-6c6d-4389-b28f-0f7d6aa1c58c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774168655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1774168655
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.160198745
Short name T851
Test name
Test status
Simulation time 105656002 ps
CPU time 1.15 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 219128 kb
Host smart-e6be82b6-938e-49eb-a06b-9dba70111e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160198745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.160198745
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1668896841
Short name T257
Test name
Test status
Simulation time 26446809 ps
CPU time 0.92 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 207040 kb
Host smart-34afe589-c2b4-4424-8698-0af126fb3556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668896841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1668896841
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1143631136
Short name T513
Test name
Test status
Simulation time 11809764 ps
CPU time 0.9 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:00 PM PDT 24
Peak memory 215720 kb
Host smart-28d87558-337e-4f87-883d-f6c12ec3ef4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143631136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1143631136
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1900754540
Short name T457
Test name
Test status
Simulation time 225522977 ps
CPU time 1.16 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 217316 kb
Host smart-7790f46d-d88c-4de2-b3d9-ecd1bff2c31a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900754540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1900754540
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3288050290
Short name T7
Test name
Test status
Simulation time 53207966 ps
CPU time 1 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 218984 kb
Host smart-e1c5d658-47a7-45b6-978a-14a44d0b2334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288050290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3288050290
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3026328472
Short name T317
Test name
Test status
Simulation time 34753113 ps
CPU time 1.31 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 218920 kb
Host smart-ed8c994b-490c-4145-8f81-b62d925ad79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026328472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3026328472
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.746047980
Short name T752
Test name
Test status
Simulation time 26391469 ps
CPU time 0.97 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 215632 kb
Host smart-21134936-3159-4473-99ec-9a37ed01e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746047980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.746047980
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2698226283
Short name T506
Test name
Test status
Simulation time 233767487 ps
CPU time 4.53 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 215668 kb
Host smart-694822a4-1e26-4eb9-9ddd-e49dae5df5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698226283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2698226283
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.622604869
Short name T461
Test name
Test status
Simulation time 45392864401 ps
CPU time 504.62 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:38:23 PM PDT 24
Peak memory 218524 kb
Host smart-45e650a2-bafa-42e0-94df-cdfaf1ad13c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622604869 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.622604869
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1327152060
Short name T515
Test name
Test status
Simulation time 69339496 ps
CPU time 1.97 seconds
Started Jul 03 05:31:26 PM PDT 24
Finished Jul 03 05:31:28 PM PDT 24
Peak memory 218864 kb
Host smart-cc6fb319-22a9-414f-831d-b338e96ceba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327152060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1327152060
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1692221311
Short name T571
Test name
Test status
Simulation time 294626165 ps
CPU time 2.01 seconds
Started Jul 03 05:31:35 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 218988 kb
Host smart-6b0a9140-bed9-4485-b350-8609596df6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692221311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1692221311
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2397965913
Short name T859
Test name
Test status
Simulation time 159801870 ps
CPU time 1.25 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 219104 kb
Host smart-78231151-bea9-490f-8646-2f151e211abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397965913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2397965913
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2409011958
Short name T539
Test name
Test status
Simulation time 43763049 ps
CPU time 1.13 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 217616 kb
Host smart-83069acb-3144-4660-a42c-a0551325d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409011958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2409011958
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2194796728
Short name T591
Test name
Test status
Simulation time 65054012 ps
CPU time 1.35 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 219852 kb
Host smart-0221f774-e113-4092-aedf-baa3afbcbba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194796728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2194796728
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2458154455
Short name T981
Test name
Test status
Simulation time 44175348 ps
CPU time 1.5 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 215572 kb
Host smart-b3081efb-5ae0-486d-88b4-7196a6ff1184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458154455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2458154455
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1079672942
Short name T13
Test name
Test status
Simulation time 21472417 ps
CPU time 1.12 seconds
Started Jul 03 05:31:31 PM PDT 24
Finished Jul 03 05:31:32 PM PDT 24
Peak memory 220256 kb
Host smart-aaaae415-a84e-4324-98e3-3bbcb6a88117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079672942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1079672942
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3727972592
Short name T387
Test name
Test status
Simulation time 534103461 ps
CPU time 5 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 219232 kb
Host smart-bf61a435-6f29-404f-ac10-f22f997f07f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727972592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3727972592
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2376492549
Short name T446
Test name
Test status
Simulation time 103722868 ps
CPU time 1.22 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 218660 kb
Host smart-7f750fe0-1736-4fda-844a-23eb613af990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376492549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2376492549
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.528787060
Short name T595
Test name
Test status
Simulation time 80766857 ps
CPU time 1.2 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 219996 kb
Host smart-6ac7f7d6-49d8-42ee-928c-4caab1dbd76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528787060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.528787060
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.26742780
Short name T843
Test name
Test status
Simulation time 213016873 ps
CPU time 0.92 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 207012 kb
Host smart-c53a8bc0-af97-4c6d-ac2a-003e62d7703d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26742780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.26742780
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4279761330
Short name T174
Test name
Test status
Simulation time 12993763 ps
CPU time 0.95 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 216676 kb
Host smart-f2915ea0-ce89-455a-b3ad-2002cfb47736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279761330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4279761330
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.664941478
Short name T892
Test name
Test status
Simulation time 87031966 ps
CPU time 1.15 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 218772 kb
Host smart-d03fdba9-fa74-4a5f-adb6-843c79612d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664941478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.664941478
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.575400543
Short name T158
Test name
Test status
Simulation time 24798716 ps
CPU time 1.13 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 221012 kb
Host smart-30511e27-f8a7-4166-89cb-b172b612f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575400543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.575400543
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.350726380
Short name T288
Test name
Test status
Simulation time 265503979 ps
CPU time 1.07 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 217632 kb
Host smart-aad7869b-90ea-4483-b2ee-21db972931cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350726380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.350726380
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1436241918
Short name T473
Test name
Test status
Simulation time 23620386 ps
CPU time 0.94 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 215680 kb
Host smart-2352a24e-10da-48a7-9fa7-eb2238e7c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436241918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1436241918
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.784467136
Short name T739
Test name
Test status
Simulation time 54780559 ps
CPU time 0.89 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 215636 kb
Host smart-becaa019-92a8-4c2f-b1ae-ceea80f5b726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784467136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.784467136
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.717305198
Short name T605
Test name
Test status
Simulation time 498686722 ps
CPU time 5.6 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 217364 kb
Host smart-10793b64-8855-4342-b760-1b9740db28fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717305198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.717305198
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2337102006
Short name T235
Test name
Test status
Simulation time 219247569034 ps
CPU time 1243.6 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:50:40 PM PDT 24
Peak memory 223548 kb
Host smart-de84402e-b87c-41b8-9634-e753ecda06a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337102006 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2337102006
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2104571166
Short name T993
Test name
Test status
Simulation time 155127182 ps
CPU time 1.12 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 217636 kb
Host smart-5c581125-7605-4056-857c-94c9750529eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104571166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2104571166
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3343110306
Short name T822
Test name
Test status
Simulation time 49460193 ps
CPU time 0.98 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 217592 kb
Host smart-a6087b93-00ab-42f6-8764-eb7d3012198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343110306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3343110306
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2435208196
Short name T946
Test name
Test status
Simulation time 43491751 ps
CPU time 1.64 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 218944 kb
Host smart-494c8cee-672d-40aa-bc8e-25394414510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435208196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2435208196
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.464002241
Short name T313
Test name
Test status
Simulation time 110653069 ps
CPU time 1.37 seconds
Started Jul 03 05:31:36 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 219316 kb
Host smart-d066857c-8d2b-424d-b4a3-2c3f402ac086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464002241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.464002241
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2400823852
Short name T333
Test name
Test status
Simulation time 48523595 ps
CPU time 1.68 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 218772 kb
Host smart-b88bec05-37f2-4d76-b26d-197d7125d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400823852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2400823852
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.966987448
Short name T879
Test name
Test status
Simulation time 100321915 ps
CPU time 1.22 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 218912 kb
Host smart-48eaa758-ae44-4561-a098-dcb02e855765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966987448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.966987448
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2118007865
Short name T919
Test name
Test status
Simulation time 45773544 ps
CPU time 1.43 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 217540 kb
Host smart-27e7d62c-ffad-4c3e-a67b-5e025f2ab300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118007865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2118007865
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1480177484
Short name T678
Test name
Test status
Simulation time 45256493 ps
CPU time 0.9 seconds
Started Jul 03 05:31:34 PM PDT 24
Finished Jul 03 05:31:35 PM PDT 24
Peak memory 217736 kb
Host smart-29e31c37-61be-41ff-8e24-e61b9f32f851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480177484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1480177484
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2243058765
Short name T817
Test name
Test status
Simulation time 25106175 ps
CPU time 1.17 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 215952 kb
Host smart-d990c51a-7c17-47fa-8d67-691d603cc671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243058765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2243058765
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2670435630
Short name T704
Test name
Test status
Simulation time 20564392 ps
CPU time 0.88 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 206940 kb
Host smart-08055554-da78-4420-9598-469fe5153352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670435630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2670435630
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3163060301
Short name T44
Test name
Test status
Simulation time 58560279 ps
CPU time 0.81 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 216268 kb
Host smart-dd2f7dce-c626-4cd6-92de-357dba9d5801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163060301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3163060301
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.389391592
Short name T204
Test name
Test status
Simulation time 19540821 ps
CPU time 1.01 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 218608 kb
Host smart-a22aa8a5-7812-4cf5-bbaf-c6db8456e9b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389391592 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.389391592
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2979194825
Short name T6
Test name
Test status
Simulation time 25914486 ps
CPU time 1.11 seconds
Started Jul 03 05:29:55 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 224236 kb
Host smart-1d0bc78c-bfd6-4e45-a0c3-bd9c5db15442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979194825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2979194825
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.371514400
Short name T649
Test name
Test status
Simulation time 46441838 ps
CPU time 1.75 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 220416 kb
Host smart-452974de-3baa-47b3-9ef6-20cd038c1f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371514400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.371514400
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3217611912
Short name T551
Test name
Test status
Simulation time 31857203 ps
CPU time 0.89 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 215884 kb
Host smart-9b9269fa-0b37-42b1-8fc6-cdb5f4bfd250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217611912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3217611912
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.761842612
Short name T371
Test name
Test status
Simulation time 109591869 ps
CPU time 0.86 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 215572 kb
Host smart-b9860e7c-73c3-4bdd-a03a-eb3f971ad9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761842612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.761842612
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3777704411
Short name T443
Test name
Test status
Simulation time 1824118148 ps
CPU time 4.88 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 217616 kb
Host smart-c1671ff3-2fc2-4134-9d08-45968577d971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777704411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3777704411
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.277250503
Short name T948
Test name
Test status
Simulation time 52748075026 ps
CPU time 1113.76 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:48:42 PM PDT 24
Peak memory 224120 kb
Host smart-6f4d15d0-211c-4ad7-9e8b-1e4315a3d663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277250503 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.277250503
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1211782
Short name T484
Test name
Test status
Simulation time 56501597 ps
CPU time 1.17 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 215576 kb
Host smart-954a448d-d5f8-4c6f-875a-92672a354e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1211782
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3289845543
Short name T436
Test name
Test status
Simulation time 44227696 ps
CPU time 1.67 seconds
Started Jul 03 05:31:45 PM PDT 24
Finished Jul 03 05:31:47 PM PDT 24
Peak memory 219896 kb
Host smart-be3077ed-ab82-4f63-8489-6f2fa1e98514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289845543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3289845543
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3916078970
Short name T407
Test name
Test status
Simulation time 26021111 ps
CPU time 1.09 seconds
Started Jul 03 05:31:52 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 218868 kb
Host smart-92f986f2-5550-4f2c-937f-9d628c391fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916078970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3916078970
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2016388477
Short name T84
Test name
Test status
Simulation time 40646335 ps
CPU time 1.63 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:52 PM PDT 24
Peak memory 218700 kb
Host smart-6919f406-a308-4ffa-806e-0dc35efd8afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016388477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2016388477
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2159720107
Short name T786
Test name
Test status
Simulation time 104629037 ps
CPU time 1.24 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 219000 kb
Host smart-59d97945-00bc-47b2-a18c-94080d5801bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159720107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2159720107
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1741669158
Short name T594
Test name
Test status
Simulation time 36908732 ps
CPU time 1.38 seconds
Started Jul 03 05:31:39 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 219896 kb
Host smart-7715ec33-9d9d-476f-bbef-140d9d57cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741669158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1741669158
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.712135368
Short name T545
Test name
Test status
Simulation time 93425831 ps
CPU time 1.44 seconds
Started Jul 03 05:31:42 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 217876 kb
Host smart-3a02829a-379c-4399-8b9a-c83ef7e05aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712135368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.712135368
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3265264160
Short name T254
Test name
Test status
Simulation time 47321625 ps
CPU time 1.63 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 219052 kb
Host smart-2a6069c7-fcb5-4513-b5da-5b8bc3dab907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265264160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3265264160
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.136910934
Short name T294
Test name
Test status
Simulation time 31176665 ps
CPU time 1.26 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 220092 kb
Host smart-fe11c898-cc20-471f-a43d-3c0006c07b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136910934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.136910934
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4292441554
Short name T421
Test name
Test status
Simulation time 26404579 ps
CPU time 0.91 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 215468 kb
Host smart-caa0101a-efea-41c7-bd47-cf12291a9a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292441554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4292441554
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3356502048
Short name T732
Test name
Test status
Simulation time 101827954 ps
CPU time 0.89 seconds
Started Jul 03 05:30:03 PM PDT 24
Finished Jul 03 05:30:05 PM PDT 24
Peak memory 216608 kb
Host smart-b5bbaa8f-1c6e-4b97-87a4-341a37dc9046
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356502048 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3356502048
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.4121044558
Short name T219
Test name
Test status
Simulation time 25122807 ps
CPU time 0.99 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 220104 kb
Host smart-359dd82b-b8e5-4204-a4cb-a6c0195ea8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121044558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4121044558
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.649758104
Short name T697
Test name
Test status
Simulation time 35146169 ps
CPU time 1.37 seconds
Started Jul 03 05:30:03 PM PDT 24
Finished Jul 03 05:30:05 PM PDT 24
Peak memory 217544 kb
Host smart-2edb115b-4917-4975-9249-c3443621aed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649758104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.649758104
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1507597782
Short name T758
Test name
Test status
Simulation time 27557377 ps
CPU time 0.86 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:00 PM PDT 24
Peak memory 216044 kb
Host smart-b0fe56de-2da2-4d2e-a4dd-7e1e257f6a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507597782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1507597782
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2048925327
Short name T978
Test name
Test status
Simulation time 18453629 ps
CPU time 1.08 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 215624 kb
Host smart-00a0aef7-86ea-4b15-8668-d6da3358997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048925327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2048925327
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4253850731
Short name T68
Test name
Test status
Simulation time 475239348 ps
CPU time 6.91 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 217512 kb
Host smart-082cc1fb-34f0-452e-91f0-26994aab3662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253850731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4253850731
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1927215092
Short name T835
Test name
Test status
Simulation time 243274751117 ps
CPU time 1329.26 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:52:22 PM PDT 24
Peak memory 224264 kb
Host smart-40f4193b-9bb8-4676-834c-79495067d8f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927215092 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1927215092
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1313946109
Short name T381
Test name
Test status
Simulation time 28424049 ps
CPU time 1.21 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 218900 kb
Host smart-0c00287e-7863-45bc-8d7e-7adf2573abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313946109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1313946109
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2367135801
Short name T401
Test name
Test status
Simulation time 100648894 ps
CPU time 1.11 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 217868 kb
Host smart-668964f7-3a38-4593-ab06-636cff2f7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367135801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2367135801
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3300098625
Short name T768
Test name
Test status
Simulation time 3143264911 ps
CPU time 78.76 seconds
Started Jul 03 05:31:52 PM PDT 24
Finished Jul 03 05:33:13 PM PDT 24
Peak memory 221020 kb
Host smart-80ef6479-e645-428d-9f43-e75f33f5153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300098625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3300098625
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2873540734
Short name T312
Test name
Test status
Simulation time 61518559 ps
CPU time 1.33 seconds
Started Jul 03 05:31:33 PM PDT 24
Finished Jul 03 05:31:35 PM PDT 24
Peak memory 220260 kb
Host smart-46b174ab-2ff2-42b7-a618-35783f3dd457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873540734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2873540734
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.169278416
Short name T499
Test name
Test status
Simulation time 84082474 ps
CPU time 1.12 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 220020 kb
Host smart-75a3591d-a6ff-450f-877e-d86f4d5e862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169278416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.169278416
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1639543323
Short name T608
Test name
Test status
Simulation time 63971658 ps
CPU time 1.37 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 219352 kb
Host smart-4fa3c1a9-de62-4997-92f2-5199e469bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639543323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1639543323
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3613400150
Short name T418
Test name
Test status
Simulation time 93153092 ps
CPU time 1.34 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 217752 kb
Host smart-e13f4898-dff5-4e23-bec0-2ed7f5f13257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613400150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3613400150
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.479809239
Short name T445
Test name
Test status
Simulation time 286555310 ps
CPU time 1.31 seconds
Started Jul 03 05:31:52 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 219328 kb
Host smart-eac3fdc5-9ce6-4e46-89cf-70ee4c05d8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479809239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.479809239
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1700367771
Short name T518
Test name
Test status
Simulation time 74121336 ps
CPU time 1.12 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 220180 kb
Host smart-ddb9e866-9185-4092-a71d-a92d756cdcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700367771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1700367771
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4112323729
Short name T977
Test name
Test status
Simulation time 105946618 ps
CPU time 0.99 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:52 PM PDT 24
Peak memory 217704 kb
Host smart-ce10d3ef-9840-41e1-80b2-2fbc84bfbdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112323729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4112323729
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2193438437
Short name T645
Test name
Test status
Simulation time 24763734 ps
CPU time 1.2 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 218804 kb
Host smart-5aac2dd9-eb37-4436-b685-cc7326bed0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193438437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2193438437
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.163416709
Short name T738
Test name
Test status
Simulation time 14345265 ps
CPU time 0.89 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 215184 kb
Host smart-090f59ba-2a9a-4519-a89b-615e9688995f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163416709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.163416709
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_err.4130908527
Short name T382
Test name
Test status
Simulation time 21132363 ps
CPU time 1.13 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 220260 kb
Host smart-d8f8ae4a-a700-4df6-8fea-f3484b6e7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130908527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4130908527
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3145874801
Short name T465
Test name
Test status
Simulation time 44404339 ps
CPU time 1.67 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 218892 kb
Host smart-08ebd53e-ff9a-481c-87f6-a0c525f72f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145874801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3145874801
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2238837413
Short name T563
Test name
Test status
Simulation time 45362064 ps
CPU time 0.95 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:06 PM PDT 24
Peak memory 224136 kb
Host smart-d67fbbd5-31c7-4b69-b78d-6a5b2579a488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238837413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2238837413
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1198055379
Short name T450
Test name
Test status
Simulation time 34281128 ps
CPU time 0.87 seconds
Started Jul 03 05:29:59 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 215568 kb
Host smart-84b2d0cf-ab95-4851-bf75-9bfadf9fd267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198055379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1198055379
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.450620645
Short name T462
Test name
Test status
Simulation time 489868051 ps
CPU time 5.13 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 215664 kb
Host smart-8de8d626-6abe-4b9e-b4f1-19b4030477c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450620645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.450620645
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1859189383
Short name T467
Test name
Test status
Simulation time 15572023182 ps
CPU time 392.02 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:36:41 PM PDT 24
Peak memory 218676 kb
Host smart-eb2c8aa1-088f-435c-b080-c3cdd0ff6d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859189383 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1859189383
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1915345592
Short name T936
Test name
Test status
Simulation time 102422930 ps
CPU time 1.32 seconds
Started Jul 03 05:31:45 PM PDT 24
Finished Jul 03 05:31:47 PM PDT 24
Peak memory 219340 kb
Host smart-cedca9e5-e8b0-4472-b163-856ebd71c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915345592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1915345592
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1365379133
Short name T338
Test name
Test status
Simulation time 279341523 ps
CPU time 2.99 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:46 PM PDT 24
Peak memory 220100 kb
Host smart-53c1dd26-7850-4902-8391-3f6284b6c9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365379133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1365379133
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4247069865
Short name T597
Test name
Test status
Simulation time 166094034 ps
CPU time 1.22 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 220276 kb
Host smart-b2719ad6-74e4-4fb2-b047-1b89f3787232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247069865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4247069865
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3001824036
Short name T422
Test name
Test status
Simulation time 87188689 ps
CPU time 1.16 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 215620 kb
Host smart-516c06a4-5021-451d-ade3-47db3530532b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001824036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3001824036
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1535052942
Short name T972
Test name
Test status
Simulation time 84105340 ps
CPU time 1.55 seconds
Started Jul 03 05:31:57 PM PDT 24
Finished Jul 03 05:32:00 PM PDT 24
Peak memory 219036 kb
Host smart-c9816657-e750-4674-a022-0e21db687f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535052942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1535052942
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1682028995
Short name T666
Test name
Test status
Simulation time 35652565 ps
CPU time 1.38 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:52 PM PDT 24
Peak memory 218896 kb
Host smart-7e5884db-477e-4bb3-a640-11129c91b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682028995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1682028995
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1198401526
Short name T687
Test name
Test status
Simulation time 59237167 ps
CPU time 1.17 seconds
Started Jul 03 05:31:54 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 217712 kb
Host smart-6c548dc6-1bdd-4d28-9d0b-79b43e3f3f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198401526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1198401526
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3363392365
Short name T831
Test name
Test status
Simulation time 84422470 ps
CPU time 1.25 seconds
Started Jul 03 05:31:52 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 215660 kb
Host smart-a48aac82-1f8c-4da1-a2c5-dbde012f6908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363392365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3363392365
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3483623703
Short name T941
Test name
Test status
Simulation time 77150453 ps
CPU time 2.65 seconds
Started Jul 03 05:31:55 PM PDT 24
Finished Jul 03 05:31:59 PM PDT 24
Peak memory 220128 kb
Host smart-20219a3a-5dc6-4f99-a94d-5879caf46f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483623703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3483623703
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3845211123
Short name T777
Test name
Test status
Simulation time 157496763 ps
CPU time 3.28 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:47 PM PDT 24
Peak memory 220428 kb
Host smart-8c66aaf7-3281-4478-816e-548873462e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845211123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3845211123
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.966556949
Short name T885
Test name
Test status
Simulation time 112110675 ps
CPU time 1.46 seconds
Started Jul 03 05:30:01 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 216036 kb
Host smart-94b4ae2b-2327-4835-a181-65ca2b5a881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966556949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.966556949
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1387335243
Short name T67
Test name
Test status
Simulation time 30332050 ps
CPU time 0.97 seconds
Started Jul 03 05:30:02 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 207000 kb
Host smart-8d20bb6e-7902-42d6-8872-2a5ac41fb50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387335243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1387335243
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.428372022
Short name T836
Test name
Test status
Simulation time 11389926 ps
CPU time 0.87 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 207504 kb
Host smart-17bfa589-57dd-4388-8437-e8643c298141
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428372022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.428372022
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1261856359
Short name T693
Test name
Test status
Simulation time 17538492 ps
CPU time 0.98 seconds
Started Jul 03 05:30:05 PM PDT 24
Finished Jul 03 05:30:06 PM PDT 24
Peak memory 218700 kb
Host smart-98ad1117-8166-4082-9548-e42ae46ca129
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261856359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1261856359
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1797215003
Short name T178
Test name
Test status
Simulation time 28667257 ps
CPU time 0.87 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 218632 kb
Host smart-46978c70-427b-4a9e-8227-7d1562932ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797215003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1797215003
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2248965046
Short name T110
Test name
Test status
Simulation time 44349026 ps
CPU time 1.01 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 217748 kb
Host smart-dcf4643d-5fa9-4294-a86f-b468895e5c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248965046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2248965046
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.2086048124
Short name T511
Test name
Test status
Simulation time 23583467 ps
CPU time 0.9 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 215556 kb
Host smart-21749dd2-29fe-4137-8337-efb75180a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086048124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2086048124
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2071444569
Short name T949
Test name
Test status
Simulation time 1274165065 ps
CPU time 2.28 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 215660 kb
Host smart-d8becc06-80f0-4c4d-ae3b-7b5ae7ad1a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071444569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2071444569
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2206958816
Short name T238
Test name
Test status
Simulation time 179428067717 ps
CPU time 1161.11 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:49:31 PM PDT 24
Peak memory 225108 kb
Host smart-862294d2-5acd-421b-a569-f50b0bf8a724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206958816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2206958816
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.333059603
Short name T496
Test name
Test status
Simulation time 111704756 ps
CPU time 1.08 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 217808 kb
Host smart-cb7c443f-009b-4e25-8a77-44466573ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333059603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.333059603
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4073019320
Short name T802
Test name
Test status
Simulation time 52946108 ps
CPU time 2.01 seconds
Started Jul 03 05:31:40 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 219088 kb
Host smart-6ce5fae0-538a-4527-b34a-1ed2e4fa02e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073019320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4073019320
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3134750703
Short name T475
Test name
Test status
Simulation time 31527708 ps
CPU time 1.46 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 219092 kb
Host smart-3ceaeac2-5135-4c3d-adf7-88f818de4e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134750703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3134750703
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1360403135
Short name T536
Test name
Test status
Simulation time 44834763 ps
CPU time 1.12 seconds
Started Jul 03 05:31:44 PM PDT 24
Finished Jul 03 05:31:46 PM PDT 24
Peak memory 219884 kb
Host smart-9413e463-8607-4eee-a9bc-628833fbdac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360403135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1360403135
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.363162610
Short name T986
Test name
Test status
Simulation time 110552984 ps
CPU time 1.53 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 219024 kb
Host smart-45116ba6-70e4-4eee-bcff-4b715765270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363162610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.363162610
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3623025701
Short name T471
Test name
Test status
Simulation time 57602618 ps
CPU time 1.47 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 219008 kb
Host smart-8443eb8b-e858-4c05-8ea4-bce7e3c166c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623025701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3623025701
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2828394545
Short name T558
Test name
Test status
Simulation time 38508692 ps
CPU time 1.33 seconds
Started Jul 03 05:31:37 PM PDT 24
Finished Jul 03 05:31:38 PM PDT 24
Peak memory 219132 kb
Host smart-aaf62d50-ca28-4f2d-be10-c5399e93f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828394545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2828394545
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.752229935
Short name T380
Test name
Test status
Simulation time 61550282 ps
CPU time 1.37 seconds
Started Jul 03 05:31:39 PM PDT 24
Finished Jul 03 05:31:40 PM PDT 24
Peak memory 218880 kb
Host smart-f0f6122f-40ce-4d2c-aecc-8aff63a5fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752229935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.752229935
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1821397012
Short name T691
Test name
Test status
Simulation time 34402111 ps
CPU time 1.45 seconds
Started Jul 03 05:31:46 PM PDT 24
Finished Jul 03 05:31:48 PM PDT 24
Peak memory 218952 kb
Host smart-6ae57daf-64f0-47a8-a96a-fd76e2d8342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821397012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1821397012
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2061244914
Short name T966
Test name
Test status
Simulation time 54363014 ps
CPU time 1.21 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:51 PM PDT 24
Peak memory 215612 kb
Host smart-979263f5-bb8b-4cca-8b97-84901950cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061244914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2061244914
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2636685450
Short name T192
Test name
Test status
Simulation time 99847048 ps
CPU time 1.12 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 220092 kb
Host smart-f60675ae-77ca-48d5-8d17-58ad5b090388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636685450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2636685450
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4030915966
Short name T51
Test name
Test status
Simulation time 14667316 ps
CPU time 0.9 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 207076 kb
Host smart-870c444d-716e-4a46-ab9c-4025bbc19a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030915966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4030915966
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2309058070
Short name T743
Test name
Test status
Simulation time 52653484 ps
CPU time 0.96 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 219844 kb
Host smart-1c73af8a-7933-4e13-bc97-4579c89f13ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309058070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2309058070
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.3099828783
Short name T248
Test name
Test status
Simulation time 86053907 ps
CPU time 1.1 seconds
Started Jul 03 05:30:00 PM PDT 24
Finished Jul 03 05:30:02 PM PDT 24
Peak memory 215624 kb
Host smart-4162f97d-39b5-4e05-886d-c71b851cd461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099828783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3099828783
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3884557292
Short name T848
Test name
Test status
Simulation time 19892885 ps
CPU time 1.08 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 216180 kb
Host smart-ecef3d7f-3a86-4e36-af9d-a62b7632b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884557292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3884557292
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2036289430
Short name T773
Test name
Test status
Simulation time 27447905 ps
CPU time 0.94 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 215624 kb
Host smart-4579e520-ab7a-447f-8730-24b5efbe00d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036289430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2036289430
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3913067889
Short name T550
Test name
Test status
Simulation time 57432163 ps
CPU time 1.71 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 215656 kb
Host smart-6d6b3c8d-d392-4a1c-a595-6f0a0805b110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913067889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3913067889
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1995133343
Short name T41
Test name
Test status
Simulation time 40389571712 ps
CPU time 584.16 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:39:58 PM PDT 24
Peak memory 218240 kb
Host smart-b5b46503-9eea-4c20-8328-0e082de1ff97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995133343 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1995133343
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.484296724
Short name T960
Test name
Test status
Simulation time 33895328 ps
CPU time 1.04 seconds
Started Jul 03 05:31:48 PM PDT 24
Finished Jul 03 05:31:50 PM PDT 24
Peak memory 217528 kb
Host smart-d2202225-88fe-4066-b0ac-3f852c4feeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484296724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.484296724
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.913245021
Short name T744
Test name
Test status
Simulation time 33339797 ps
CPU time 1.44 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 218800 kb
Host smart-253bb9d5-be52-4f92-bb70-42f417f570af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913245021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.913245021
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3751644880
Short name T83
Test name
Test status
Simulation time 64158281 ps
CPU time 1.76 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:50 PM PDT 24
Peak memory 219116 kb
Host smart-5ed989cf-e840-49d6-b0da-e66b11c9c2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751644880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3751644880
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.590943371
Short name T647
Test name
Test status
Simulation time 42259263 ps
CPU time 1.36 seconds
Started Jul 03 05:31:48 PM PDT 24
Finished Jul 03 05:31:50 PM PDT 24
Peak memory 217548 kb
Host smart-3c639eee-6fb1-4713-a12e-495d8dfa1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590943371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.590943371
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3146713673
Short name T900
Test name
Test status
Simulation time 33507197 ps
CPU time 1.32 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 218908 kb
Host smart-dc104e9d-3033-460b-aa39-4b116f3dafce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146713673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3146713673
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3505477866
Short name T49
Test name
Test status
Simulation time 31024464 ps
CPU time 1.39 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 218712 kb
Host smart-396c2bae-9484-45ac-aa5d-a7cd79702b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505477866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3505477866
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1970772677
Short name T355
Test name
Test status
Simulation time 53742109 ps
CPU time 1.25 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 220188 kb
Host smart-d81d8f22-e418-49c0-981d-474f09e6698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970772677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1970772677
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2312743937
Short name T711
Test name
Test status
Simulation time 64682383 ps
CPU time 1.25 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:57 PM PDT 24
Peak memory 219132 kb
Host smart-eac64d15-040e-4d44-b605-f74ca0ee641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312743937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2312743937
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2312089525
Short name T394
Test name
Test status
Simulation time 57211917 ps
CPU time 1.69 seconds
Started Jul 03 05:31:55 PM PDT 24
Finished Jul 03 05:31:58 PM PDT 24
Peak memory 218752 kb
Host smart-4d3541e4-ff89-45ba-8044-f9c4d3848590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312089525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2312089525
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1643562053
Short name T328
Test name
Test status
Simulation time 85612773 ps
CPU time 1.49 seconds
Started Jul 03 05:31:45 PM PDT 24
Finished Jul 03 05:31:47 PM PDT 24
Peak memory 218864 kb
Host smart-a71c8a39-1697-47cb-a42c-22c21d40f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643562053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1643562053
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3980518076
Short name T708
Test name
Test status
Simulation time 40758227 ps
CPU time 1.09 seconds
Started Jul 03 05:30:24 PM PDT 24
Finished Jul 03 05:30:26 PM PDT 24
Peak memory 219036 kb
Host smart-364d58de-ffc0-4fab-8740-a8d2a3589970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980518076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3980518076
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.808362772
Short name T886
Test name
Test status
Simulation time 19462131 ps
CPU time 0.86 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 215168 kb
Host smart-52f88a8c-697d-4c07-83b5-932f632baa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808362772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.808362772
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3099098586
Short name T926
Test name
Test status
Simulation time 39018322 ps
CPU time 0.87 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 216544 kb
Host smart-79217b19-302f-4903-90d3-f75f62e4ed96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099098586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3099098586
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_genbits.565407392
Short name T455
Test name
Test status
Simulation time 204723675 ps
CPU time 1.81 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 220272 kb
Host smart-a9c659af-58b0-4d69-8274-4acce2500c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565407392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.565407392
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.175465323
Short name T100
Test name
Test status
Simulation time 35572390 ps
CPU time 0.89 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 215896 kb
Host smart-81731104-86dc-49c8-95ab-efb904c67768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175465323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.175465323
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.167762568
Short name T488
Test name
Test status
Simulation time 117014686 ps
CPU time 1 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 215576 kb
Host smart-9d3bd9e8-6761-46ee-a761-2ce6d49c0556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167762568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.167762568
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3508435088
Short name T803
Test name
Test status
Simulation time 341926691 ps
CPU time 3.52 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 215568 kb
Host smart-893663f2-1537-441c-9030-252506589669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508435088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3508435088
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.674599654
Short name T239
Test name
Test status
Simulation time 186730644035 ps
CPU time 2332.13 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 06:08:59 PM PDT 24
Peak memory 231948 kb
Host smart-4e57d6f5-ed10-42c1-8433-51b98a821ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674599654 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.674599654
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2998809642
Short name T540
Test name
Test status
Simulation time 65288784 ps
CPU time 1.11 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:51 PM PDT 24
Peak memory 217776 kb
Host smart-6a60ccc7-6f26-4f86-8577-d04bec2cfdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998809642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2998809642
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3473452648
Short name T454
Test name
Test status
Simulation time 133485848 ps
CPU time 1.25 seconds
Started Jul 03 05:31:48 PM PDT 24
Finished Jul 03 05:31:50 PM PDT 24
Peak memory 219056 kb
Host smart-4f1f82e9-35ff-4b94-a7d9-2e999c70180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473452648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3473452648
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.425463011
Short name T898
Test name
Test status
Simulation time 31837658 ps
CPU time 1.25 seconds
Started Jul 03 05:31:40 PM PDT 24
Finished Jul 03 05:31:42 PM PDT 24
Peak memory 220376 kb
Host smart-9df75267-0009-401c-806c-8f07b2378745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425463011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.425463011
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4046388656
Short name T870
Test name
Test status
Simulation time 31615593 ps
CPU time 1.04 seconds
Started Jul 03 05:31:53 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 217684 kb
Host smart-899f22e2-66eb-4b37-b9ce-b5279ec80178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046388656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4046388656
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3423376456
Short name T412
Test name
Test status
Simulation time 45940363 ps
CPU time 1.13 seconds
Started Jul 03 05:31:38 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 220164 kb
Host smart-ce0cd456-515d-49bb-bd56-f16ead2b49d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423376456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3423376456
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2339677328
Short name T736
Test name
Test status
Simulation time 192395077 ps
CPU time 3.27 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 220440 kb
Host smart-20296649-02b5-4b01-baa9-a2e63a9bb02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339677328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2339677328
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2197916403
Short name T400
Test name
Test status
Simulation time 33390362 ps
CPU time 1.26 seconds
Started Jul 03 05:31:52 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 218708 kb
Host smart-68531cd0-bd8a-495c-bc11-3a7e4aa79024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197916403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2197916403
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3848993109
Short name T250
Test name
Test status
Simulation time 56326918 ps
CPU time 2.13 seconds
Started Jul 03 05:31:59 PM PDT 24
Finished Jul 03 05:32:01 PM PDT 24
Peak memory 219280 kb
Host smart-d58640b9-d1f7-4667-8b63-2adb0579c2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848993109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3848993109
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.849278994
Short name T675
Test name
Test status
Simulation time 143686675 ps
CPU time 1.19 seconds
Started Jul 03 05:31:41 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 219452 kb
Host smart-5b04fd35-a400-4159-9a73-0e448b84417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849278994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.849278994
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1358874686
Short name T579
Test name
Test status
Simulation time 44619811 ps
CPU time 1.41 seconds
Started Jul 03 05:31:42 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 218856 kb
Host smart-2df9054e-bed2-46ed-a6fe-7fd51317df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358874686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1358874686
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3373320405
Short name T706
Test name
Test status
Simulation time 52343700 ps
CPU time 1.21 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 216064 kb
Host smart-888042a6-6762-4cb0-bb43-5fc5b8838186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373320405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3373320405
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3099237440
Short name T438
Test name
Test status
Simulation time 112004599 ps
CPU time 0.83 seconds
Started Jul 03 05:30:27 PM PDT 24
Finished Jul 03 05:30:28 PM PDT 24
Peak memory 206816 kb
Host smart-b8412ed2-8c57-492c-a494-a12d39f183dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099237440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3099237440
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3703506977
Short name T746
Test name
Test status
Simulation time 18123199 ps
CPU time 0.94 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 215776 kb
Host smart-e2f1114d-8750-4763-82eb-ede5b1ca0a53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703506977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3703506977
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.479581964
Short name T206
Test name
Test status
Simulation time 25945686 ps
CPU time 0.97 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 219016 kb
Host smart-fac4da4a-5223-4024-b0f2-c53abe4652e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479581964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.479581964
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3487805651
Short name T2
Test name
Test status
Simulation time 63986163 ps
CPU time 1.4 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 219748 kb
Host smart-96cb1d4d-38f4-4031-82ce-ee346227a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487805651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3487805651
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1202956033
Short name T98
Test name
Test status
Simulation time 30237537 ps
CPU time 0.86 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 216016 kb
Host smart-fd0034a9-1fdb-4a0a-9621-7b4de9cfca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202956033 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1202956033
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3517655469
Short name T660
Test name
Test status
Simulation time 29731682 ps
CPU time 0.94 seconds
Started Jul 03 05:30:09 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 215632 kb
Host smart-0d0136cf-d16f-4423-beea-d28dffa82efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517655469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3517655469
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1143461816
Short name T564
Test name
Test status
Simulation time 881833657 ps
CPU time 3.54 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 217692 kb
Host smart-ad99c7e9-d3bf-45aa-a70b-8b2303fc2ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143461816 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1143461816
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1990643034
Short name T245
Test name
Test status
Simulation time 27369081251 ps
CPU time 580.83 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:39:54 PM PDT 24
Peak memory 223976 kb
Host smart-72aa00a6-9b47-4aba-bcac-ba53ef4413e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990643034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1990643034
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.288805114
Short name T756
Test name
Test status
Simulation time 58422020 ps
CPU time 1.23 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:45 PM PDT 24
Peak memory 217640 kb
Host smart-be9f89fa-0211-49a5-82d5-f4be1ce8e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288805114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.288805114
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2464410695
Short name T775
Test name
Test status
Simulation time 41144359 ps
CPU time 1.39 seconds
Started Jul 03 05:31:47 PM PDT 24
Finished Jul 03 05:31:49 PM PDT 24
Peak memory 218856 kb
Host smart-b587af46-c5cf-45b2-a737-0f99dcd218a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464410695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2464410695
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1252231797
Short name T844
Test name
Test status
Simulation time 167052776 ps
CPU time 2.34 seconds
Started Jul 03 05:31:55 PM PDT 24
Finished Jul 03 05:31:58 PM PDT 24
Peak memory 220272 kb
Host smart-ceba5180-3960-4b9a-95fa-b8b62917d76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252231797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1252231797
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3324043848
Short name T893
Test name
Test status
Simulation time 31994673 ps
CPU time 1.44 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 218984 kb
Host smart-d7ac01ca-8b0d-4eb4-8970-4abb2f5f2fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324043848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3324043848
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1992995762
Short name T753
Test name
Test status
Simulation time 32526129 ps
CPU time 1.15 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 218768 kb
Host smart-d73ae726-7524-42b3-876e-776a254935c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992995762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1992995762
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.262071971
Short name T240
Test name
Test status
Simulation time 83926632 ps
CPU time 1.39 seconds
Started Jul 03 05:31:58 PM PDT 24
Finished Jul 03 05:32:00 PM PDT 24
Peak memory 219068 kb
Host smart-a03b9308-afb6-4af1-aecf-6dee1d630b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262071971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.262071971
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2050646142
Short name T612
Test name
Test status
Simulation time 135766110 ps
CPU time 1.13 seconds
Started Jul 03 05:31:45 PM PDT 24
Finished Jul 03 05:31:47 PM PDT 24
Peak memory 217572 kb
Host smart-2fa2e6c9-8247-4736-80c6-27846a09b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050646142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2050646142
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1874211926
Short name T611
Test name
Test status
Simulation time 69868436 ps
CPU time 1.15 seconds
Started Jul 03 05:31:44 PM PDT 24
Finished Jul 03 05:31:46 PM PDT 24
Peak memory 219100 kb
Host smart-e3bc88af-7f88-4a4b-8f4a-2222352b992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874211926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1874211926
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.892837418
Short name T512
Test name
Test status
Simulation time 50773792 ps
CPU time 0.99 seconds
Started Jul 03 05:31:46 PM PDT 24
Finished Jul 03 05:31:48 PM PDT 24
Peak memory 217592 kb
Host smart-907a0730-0f2a-426a-8fba-6dfe9a2d453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892837418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.892837418
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.603133545
Short name T359
Test name
Test status
Simulation time 67772619 ps
CPU time 1.17 seconds
Started Jul 03 05:32:00 PM PDT 24
Finished Jul 03 05:32:01 PM PDT 24
Peak memory 219300 kb
Host smart-62c34547-c160-4d70-be67-b8900e208eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603133545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.603133545
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2682494521
Short name T516
Test name
Test status
Simulation time 53297389 ps
CPU time 1.21 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 218976 kb
Host smart-fd4cf2a1-1376-416d-a78e-87f22f73ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682494521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2682494521
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1857963282
Short name T618
Test name
Test status
Simulation time 38418377 ps
CPU time 0.88 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 215264 kb
Host smart-50962695-0447-4d7c-ba93-977d17d299be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857963282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1857963282
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2603581640
Short name T784
Test name
Test status
Simulation time 11150760 ps
CPU time 0.88 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 215700 kb
Host smart-05ef7887-9fef-401b-9351-142ae97aaffd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603581640 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2603581640
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2590878381
Short name T996
Test name
Test status
Simulation time 26435351 ps
CPU time 0.92 seconds
Started Jul 03 05:30:07 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 217084 kb
Host smart-21a0f6ee-0e3b-4dc9-8a55-900af82c291d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590878381 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2590878381
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2194668637
Short name T153
Test name
Test status
Simulation time 26461418 ps
CPU time 1.36 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 230220 kb
Host smart-9cf08706-fa73-4e80-88cf-8767253cf320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194668637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2194668637
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.740041335
Short name T833
Test name
Test status
Simulation time 225999036 ps
CPU time 3.33 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 220432 kb
Host smart-ab85b306-88a9-4555-9ff4-0f32854c7003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740041335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.740041335
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1919025814
Short name T37
Test name
Test status
Simulation time 24165858 ps
CPU time 0.96 seconds
Started Jul 03 05:30:20 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 216076 kb
Host smart-6e5b8d41-cbf0-4771-b957-c86cc36e4312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919025814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1919025814
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4106950163
Short name T410
Test name
Test status
Simulation time 19884280 ps
CPU time 1.02 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 215640 kb
Host smart-75c113da-059e-41a9-97b4-360c6348bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106950163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4106950163
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2493699325
Short name T828
Test name
Test status
Simulation time 503214573 ps
CPU time 5.39 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:17 PM PDT 24
Peak memory 215640 kb
Host smart-29d56b0e-a417-4c46-80ad-09bc398614b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493699325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2493699325
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.619341307
Short name T761
Test name
Test status
Simulation time 84960718957 ps
CPU time 420.81 seconds
Started Jul 03 05:30:15 PM PDT 24
Finished Jul 03 05:37:17 PM PDT 24
Peak memory 219152 kb
Host smart-e7c920b3-97f2-48e2-b551-d6d9ac578234
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619341307 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.619341307
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2834459692
Short name T289
Test name
Test status
Simulation time 30706842 ps
CPU time 1.19 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 219024 kb
Host smart-3c7c5c22-f68c-43d2-b63f-e5e5494d69e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834459692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2834459692
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2080526083
Short name T509
Test name
Test status
Simulation time 59708231 ps
CPU time 1.24 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:51 PM PDT 24
Peak memory 218692 kb
Host smart-1d4c3280-5dc1-4341-9b35-4f50a44c532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080526083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2080526083
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1289613041
Short name T322
Test name
Test status
Simulation time 65745280 ps
CPU time 1.48 seconds
Started Jul 03 05:31:49 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 219004 kb
Host smart-b8b8e2af-4c93-44fb-b8bb-dd0c6116b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289613041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1289613041
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1005865265
Short name T327
Test name
Test status
Simulation time 44569894 ps
CPU time 1.34 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 218712 kb
Host smart-c58018ad-8b97-499a-9408-1bc22c4229d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005865265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1005865265
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3695975435
Short name T567
Test name
Test status
Simulation time 61032172 ps
CPU time 1.6 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 218864 kb
Host smart-3e40bfc2-a488-4404-9133-3b1c960fc3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695975435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3695975435
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.570677230
Short name T715
Test name
Test status
Simulation time 40901233 ps
CPU time 1.37 seconds
Started Jul 03 05:31:50 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 218772 kb
Host smart-474a3ff5-ccff-430e-b58d-602d23b80464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570677230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.570677230
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.239372088
Short name T468
Test name
Test status
Simulation time 180509315 ps
CPU time 1.2 seconds
Started Jul 03 05:31:46 PM PDT 24
Finished Jul 03 05:31:48 PM PDT 24
Peak memory 217716 kb
Host smart-74ee24f2-3a70-4f12-a38d-78377f8046d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239372088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.239372088
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4089055112
Short name T388
Test name
Test status
Simulation time 164980198 ps
CPU time 1.06 seconds
Started Jul 03 05:31:53 PM PDT 24
Finished Jul 03 05:31:56 PM PDT 24
Peak memory 217744 kb
Host smart-fb281974-4e85-4d5d-94da-0397f458fe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089055112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4089055112
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2959053376
Short name T330
Test name
Test status
Simulation time 58250604 ps
CPU time 1.32 seconds
Started Jul 03 05:31:51 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 220552 kb
Host smart-fb45424a-1e49-4306-aa64-3776b31714f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959053376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2959053376
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.555885383
Short name T319
Test name
Test status
Simulation time 61610461 ps
CPU time 1.03 seconds
Started Jul 03 05:31:43 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 217688 kb
Host smart-37f6f4f2-3735-4608-93ed-0bcd8dcde51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555885383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.555885383
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1846318129
Short name T229
Test name
Test status
Simulation time 28906080 ps
CPU time 1.26 seconds
Started Jul 03 05:29:34 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 220140 kb
Host smart-5302c0e6-34ca-448a-8a60-ed37d36d005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846318129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1846318129
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2698452922
Short name T404
Test name
Test status
Simulation time 135461039 ps
CPU time 0.85 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 206780 kb
Host smart-1a910dc3-e0a3-4b8b-9e23-86ee6410a476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698452922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2698452922
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.763387880
Short name T694
Test name
Test status
Simulation time 175477054 ps
CPU time 1.14 seconds
Started Jul 03 05:29:41 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 219852 kb
Host smart-242cd5df-fab8-48e1-9d78-b759e89ce0cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763387880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.763387880
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3041681743
Short name T200
Test name
Test status
Simulation time 19570495 ps
CPU time 1.09 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 219808 kb
Host smart-7d1d808e-2554-4b0d-b433-029a470588ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041681743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3041681743
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4101623321
Short name T535
Test name
Test status
Simulation time 62278435 ps
CPU time 1.01 seconds
Started Jul 03 05:29:34 PM PDT 24
Finished Jul 03 05:29:35 PM PDT 24
Peak memory 217568 kb
Host smart-b2e84cf1-e6a8-4eb6-970a-1b6e470da3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101623321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4101623321
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4189553998
Short name T99
Test name
Test status
Simulation time 30285737 ps
CPU time 1.17 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 216700 kb
Host smart-711295ee-ff42-4732-9081-f30d91dead8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189553998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4189553998
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3442575321
Short name T61
Test name
Test status
Simulation time 664650188 ps
CPU time 3.89 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 235684 kb
Host smart-fd7c1d87-0af7-4429-ae6a-0fd27f7635e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442575321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3442575321
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1570204268
Short name T659
Test name
Test status
Simulation time 54692065 ps
CPU time 0.91 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 215604 kb
Host smart-b0d0e2da-b306-4b92-9f98-d303bdbd65b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570204268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1570204268
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1911140685
Short name T745
Test name
Test status
Simulation time 661849480 ps
CPU time 5.76 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 217656 kb
Host smart-5cae262a-2d49-4f98-b9ee-3a8d80f02585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911140685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1911140685
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1846638661
Short name T242
Test name
Test status
Simulation time 330827852595 ps
CPU time 1391.13 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:52:56 PM PDT 24
Peak memory 224472 kb
Host smart-7788167d-d306-4515-831c-2a6c1d15799b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846638661 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1846638661
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.634390074
Short name T150
Test name
Test status
Simulation time 26406291 ps
CPU time 1.18 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 221148 kb
Host smart-ea80708d-294f-4a93-97c2-428ed2babf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634390074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.634390074
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2854419003
Short name T460
Test name
Test status
Simulation time 13022590 ps
CPU time 0.89 seconds
Started Jul 03 05:30:27 PM PDT 24
Finished Jul 03 05:30:28 PM PDT 24
Peak memory 207024 kb
Host smart-7a0df1d6-97f5-481a-adc1-520ebaa8f758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854419003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2854419003
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.926210883
Short name T847
Test name
Test status
Simulation time 17782753 ps
CPU time 0.86 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 216244 kb
Host smart-cccc74ef-a570-494a-95d4-7c7b3945d8ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926210883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.926210883
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2196747673
Short name T91
Test name
Test status
Simulation time 28356365 ps
CPU time 1.11 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 217180 kb
Host smart-62a2a611-f379-450e-b9ef-0ccd57dc68fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196747673 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2196747673
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3855317915
Short name T530
Test name
Test status
Simulation time 19918056 ps
CPU time 1.18 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 224280 kb
Host smart-ffb9ade1-f9a9-4f4a-b4ea-418eba601831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855317915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3855317915
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2359745369
Short name T561
Test name
Test status
Simulation time 40176390 ps
CPU time 1.1 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:10 PM PDT 24
Peak memory 218908 kb
Host smart-b6749c87-c512-4a6c-b4e7-2ce64aea8b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359745369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2359745369
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3489267401
Short name T459
Test name
Test status
Simulation time 22856951 ps
CPU time 1.08 seconds
Started Jul 03 05:30:10 PM PDT 24
Finished Jul 03 05:30:12 PM PDT 24
Peak memory 215852 kb
Host smart-3bed690c-6369-41a8-9cf3-390a1bfc6401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489267401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3489267401
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2406449824
Short name T397
Test name
Test status
Simulation time 15896544 ps
CPU time 1 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 215648 kb
Host smart-82a368bc-f340-496c-81a6-fb2204ab5db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406449824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2406449824
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3131024500
Short name T52
Test name
Test status
Simulation time 573952581 ps
CPU time 3.34 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 218716 kb
Host smart-91168c43-8e2d-466e-a819-bcd0f3743d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131024500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3131024500
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.444293227
Short name T864
Test name
Test status
Simulation time 103869552446 ps
CPU time 1182.56 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:50:02 PM PDT 24
Peak memory 223760 kb
Host smart-ef30b665-65be-4430-883b-c019528ca14a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444293227 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.444293227
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.324613141
Short name T232
Test name
Test status
Simulation time 23758073 ps
CPU time 1.21 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 220456 kb
Host smart-5d2c18e7-9324-4e13-a87c-bc6c12f2299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324613141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.324613141
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3651795414
Short name T644
Test name
Test status
Simulation time 193959507 ps
CPU time 0.98 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 215540 kb
Host smart-35ed8ba2-e29c-4eb6-8682-13f1f73d75f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651795414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3651795414
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1111648801
Short name T211
Test name
Test status
Simulation time 47751710 ps
CPU time 0.82 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 216520 kb
Host smart-c48e8a62-b765-42b3-bb76-bb16178ce90e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111648801 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1111648801
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3206149553
Short name T226
Test name
Test status
Simulation time 78096816 ps
CPU time 1.17 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 217200 kb
Host smart-4c10e4a7-e8de-4ba7-a436-3ee7e46584aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206149553 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3206149553
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.882042537
Short name T145
Test name
Test status
Simulation time 25941344 ps
CPU time 1.15 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 229832 kb
Host smart-db6b5102-5fcf-4450-adf7-6570f10f0acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882042537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.882042537
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3136650451
Short name T921
Test name
Test status
Simulation time 94984371 ps
CPU time 1.55 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 218868 kb
Host smart-bee77aaa-7d68-449d-b66a-c063ed50363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136650451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3136650451
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2132872398
Short name T548
Test name
Test status
Simulation time 32375375 ps
CPU time 1.09 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 224408 kb
Host smart-e08c448c-1ac3-4de8-949c-5cb5429edc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132872398 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2132872398
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2671477163
Short name T680
Test name
Test status
Simulation time 31899481 ps
CPU time 0.93 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 215520 kb
Host smart-1d875140-3f04-40ee-8f4b-c713a7a4b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671477163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2671477163
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2534313334
Short name T609
Test name
Test status
Simulation time 1164140655 ps
CPU time 4.88 seconds
Started Jul 03 05:30:08 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 217672 kb
Host smart-fe0f62a1-f894-4731-ad0e-0c6d18cd785c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534313334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2534313334
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1124427441
Short name T682
Test name
Test status
Simulation time 126951276344 ps
CPU time 792.26 seconds
Started Jul 03 05:30:06 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 220796 kb
Host smart-116e704a-8703-4499-83dc-0bf3c2af0505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124427441 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1124427441
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3496369415
Short name T640
Test name
Test status
Simulation time 100355410 ps
CPU time 1.06 seconds
Started Jul 03 05:30:22 PM PDT 24
Finished Jul 03 05:30:24 PM PDT 24
Peak memory 218916 kb
Host smart-7e19ba4b-01c8-4a57-891c-6984d83fb6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496369415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3496369415
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.226112533
Short name T889
Test name
Test status
Simulation time 194417723 ps
CPU time 0.89 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 215500 kb
Host smart-609fbad0-7176-4f2a-b1c7-f3b030ad9811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226112533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.226112533
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2978377532
Short name T650
Test name
Test status
Simulation time 12811893 ps
CPU time 0.84 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 216332 kb
Host smart-baba7c16-3b88-4a10-81af-bbb239d8344c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978377532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2978377532
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1124016992
Short name T757
Test name
Test status
Simulation time 81992903 ps
CPU time 1.05 seconds
Started Jul 03 05:30:23 PM PDT 24
Finished Jul 03 05:30:25 PM PDT 24
Peak memory 219020 kb
Host smart-5ae3bc1a-b868-43d9-8239-3675c732db03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124016992 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1124016992
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2999205564
Short name T58
Test name
Test status
Simulation time 23978651 ps
CPU time 1.3 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 232464 kb
Host smart-96a081fb-adfd-4476-9a0a-44959e4eca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999205564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2999205564
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4140675899
Short name T626
Test name
Test status
Simulation time 37293352 ps
CPU time 0.91 seconds
Started Jul 03 05:30:23 PM PDT 24
Finished Jul 03 05:30:24 PM PDT 24
Peak memory 217540 kb
Host smart-8ca401cb-71ea-42b9-94be-5b3b3cc1a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140675899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4140675899
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.1111099999
Short name T357
Test name
Test status
Simulation time 16720806 ps
CPU time 0.95 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:19 PM PDT 24
Peak memory 215692 kb
Host smart-38baba96-1b59-4859-8198-936967d1abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111099999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1111099999
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3510621209
Short name T448
Test name
Test status
Simulation time 506880500 ps
CPU time 5.16 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:19 PM PDT 24
Peak memory 215652 kb
Host smart-94832f7e-1d80-487d-b37e-48197fa561d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510621209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3510621209
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2529751857
Short name T674
Test name
Test status
Simulation time 334628342157 ps
CPU time 2563.49 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 06:13:02 PM PDT 24
Peak memory 229940 kb
Host smart-9b606d09-7d9e-4c02-99e5-538b4b0ef487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529751857 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2529751857
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1553254366
Short name T576
Test name
Test status
Simulation time 81713301 ps
CPU time 1.15 seconds
Started Jul 03 05:30:16 PM PDT 24
Finished Jul 03 05:30:17 PM PDT 24
Peak memory 219996 kb
Host smart-747dacf7-71d3-4be4-8cd5-fe6560dc2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553254366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1553254366
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.600884953
Short name T476
Test name
Test status
Simulation time 44356365 ps
CPU time 0.86 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 207044 kb
Host smart-15d190c7-7a59-49ae-8fd4-b603426933da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600884953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.600884953
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1611350714
Short name T180
Test name
Test status
Simulation time 31121408 ps
CPU time 0.85 seconds
Started Jul 03 05:30:26 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 216504 kb
Host smart-067c8e49-ca1f-4f8d-a742-e7891f2821a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611350714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1611350714
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.760736145
Short name T796
Test name
Test status
Simulation time 84615993 ps
CPU time 1.2 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 217180 kb
Host smart-2413e53a-f493-4fba-8181-b858f474947b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760736145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.760736145
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1709666035
Short name T432
Test name
Test status
Simulation time 27994456 ps
CPU time 0.9 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 218536 kb
Host smart-919e941b-803b-423e-94df-f84a3163c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709666035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1709666035
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1533476056
Short name T325
Test name
Test status
Simulation time 75286126 ps
CPU time 1.19 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 215708 kb
Host smart-edaadefc-58fa-44f1-b77a-57aa8f0eda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533476056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1533476056
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.619874632
Short name T811
Test name
Test status
Simulation time 23093016 ps
CPU time 1.03 seconds
Started Jul 03 05:30:12 PM PDT 24
Finished Jul 03 05:30:13 PM PDT 24
Peak memory 215832 kb
Host smart-7074f584-67b2-4e4f-b4dd-47a0e2571901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619874632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.619874632
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1950589926
Short name T737
Test name
Test status
Simulation time 16662795 ps
CPU time 1.03 seconds
Started Jul 03 05:30:25 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 215656 kb
Host smart-8c81ab4c-1249-4a44-a12c-831237cf99e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950589926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1950589926
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1774512583
Short name T251
Test name
Test status
Simulation time 227034562 ps
CPU time 2.32 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 220420 kb
Host smart-5ea490ff-510e-496b-ab85-6a78af233c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774512583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1774512583
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2952892310
Short name T453
Test name
Test status
Simulation time 404887025839 ps
CPU time 2500.21 seconds
Started Jul 03 05:30:11 PM PDT 24
Finished Jul 03 06:11:52 PM PDT 24
Peak memory 240376 kb
Host smart-28f6eb1f-a409-4dee-b240-0065f6ee1c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952892310 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2952892310
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.177057654
Short name T554
Test name
Test status
Simulation time 121171591 ps
CPU time 1.18 seconds
Started Jul 03 05:30:23 PM PDT 24
Finished Jul 03 05:30:24 PM PDT 24
Peak memory 218996 kb
Host smart-9b89dacd-b299-4646-8ac6-ce232cd88f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177057654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.177057654
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2303238060
Short name T882
Test name
Test status
Simulation time 22829580 ps
CPU time 0.92 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 215232 kb
Host smart-0394cd8c-7b90-4287-9a72-9d4f9c804ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303238060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2303238060
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1083887396
Short name T81
Test name
Test status
Simulation time 16167034 ps
CPU time 0.82 seconds
Started Jul 03 05:30:14 PM PDT 24
Finished Jul 03 05:30:16 PM PDT 24
Peak memory 215656 kb
Host smart-9a759854-e59e-4b87-aa97-74230c9b2244
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083887396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1083887396
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2140929368
Short name T713
Test name
Test status
Simulation time 29051578 ps
CPU time 1.04 seconds
Started Jul 03 05:30:28 PM PDT 24
Finished Jul 03 05:30:29 PM PDT 24
Peak memory 220124 kb
Host smart-5ce15614-957b-4f47-a88d-cf18b06686fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140929368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2140929368
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4265066418
Short name T148
Test name
Test status
Simulation time 23795492 ps
CPU time 1.07 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:39 PM PDT 24
Peak memory 224260 kb
Host smart-f3368a52-d31f-4e49-b32f-9786cde81fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265066418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4265066418
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1690243592
Short name T840
Test name
Test status
Simulation time 128651352 ps
CPU time 2.49 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 220348 kb
Host smart-b2204f3c-643b-402e-b15e-bd19030ec904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690243592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1690243592
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1819975134
Short name T634
Test name
Test status
Simulation time 24662588 ps
CPU time 0.93 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:14 PM PDT 24
Peak memory 215768 kb
Host smart-e0ca41a0-d246-483b-991c-0fcce18cdb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819975134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1819975134
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.745484124
Short name T668
Test name
Test status
Simulation time 17644296 ps
CPU time 0.96 seconds
Started Jul 03 05:30:16 PM PDT 24
Finished Jul 03 05:30:17 PM PDT 24
Peak memory 207492 kb
Host smart-5e00029c-2624-4574-ba8b-2ce2a2e17c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745484124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.745484124
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1036153914
Short name T720
Test name
Test status
Simulation time 71579063 ps
CPU time 1.98 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:22 PM PDT 24
Peak memory 215644 kb
Host smart-6d2489da-c5d2-44a5-9fe4-64f4f6502008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036153914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1036153914
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2194655073
Short name T244
Test name
Test status
Simulation time 105462179403 ps
CPU time 625.74 seconds
Started Jul 03 05:30:21 PM PDT 24
Finished Jul 03 05:40:52 PM PDT 24
Peak memory 224108 kb
Host smart-ddadb7e9-614d-46f6-8ed6-dbe2ab3f2d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194655073 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2194655073
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.61840941
Short name T345
Test name
Test status
Simulation time 52647166 ps
CPU time 1.27 seconds
Started Jul 03 05:30:13 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 216000 kb
Host smart-2ec31922-e77b-4553-8ce1-2638853ad368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61840941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.61840941
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1887941417
Short name T903
Test name
Test status
Simulation time 23460051 ps
CPU time 0.99 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:19 PM PDT 24
Peak memory 215212 kb
Host smart-018c5812-b415-4940-8c2a-baca8af65b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887941417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1887941417
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1008657095
Short name T620
Test name
Test status
Simulation time 12108251 ps
CPU time 0.88 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 216716 kb
Host smart-1a777df0-beb2-4d70-b9bc-7a2d50ef7eb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008657095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1008657095
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2216188318
Short name T522
Test name
Test status
Simulation time 89342324 ps
CPU time 1.02 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:30:19 PM PDT 24
Peak memory 217112 kb
Host smart-389b1ecd-d9df-41c5-a1b1-2e063c961e6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216188318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2216188318
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3552504183
Short name T466
Test name
Test status
Simulation time 30412938 ps
CPU time 0.85 seconds
Started Jul 03 05:30:24 PM PDT 24
Finished Jul 03 05:30:25 PM PDT 24
Peak memory 218804 kb
Host smart-5d764dc8-63cc-4a87-996e-28d5798d7251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552504183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3552504183
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1496823731
Short name T809
Test name
Test status
Simulation time 53815828 ps
CPU time 1.05 seconds
Started Jul 03 05:30:26 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 220212 kb
Host smart-078db26f-53da-4d86-9abb-a32237bb2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496823731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1496823731
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1974641421
Short name T823
Test name
Test status
Simulation time 29385638 ps
CPU time 0.97 seconds
Started Jul 03 05:30:22 PM PDT 24
Finished Jul 03 05:30:23 PM PDT 24
Peak memory 215692 kb
Host smart-bb39c10a-7753-40b9-b435-6a9c3ac8c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974641421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1974641421
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1247845450
Short name T3
Test name
Test status
Simulation time 29812956 ps
CPU time 0.93 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:19 PM PDT 24
Peak memory 207468 kb
Host smart-11770514-3e4d-4775-8916-b391acb9049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247845450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1247845450
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2945195574
Short name T559
Test name
Test status
Simulation time 211308940 ps
CPU time 2.76 seconds
Started Jul 03 05:30:15 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 215696 kb
Host smart-a08fa011-7a27-4c74-9dcb-ac3ff31253bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945195574 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2945195574
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2638846517
Short name T939
Test name
Test status
Simulation time 41816266667 ps
CPU time 280.08 seconds
Started Jul 03 05:30:17 PM PDT 24
Finished Jul 03 05:34:57 PM PDT 24
Peak memory 219104 kb
Host smart-a6973ef1-d6b7-4a3a-b0f9-126e2e225402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638846517 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2638846517
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.157615238
Short name T785
Test name
Test status
Simulation time 62792631 ps
CPU time 1.12 seconds
Started Jul 03 05:30:20 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 219400 kb
Host smart-75bf80ab-ad24-4972-a377-8c81f880ae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157615238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.157615238
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3009476424
Short name T491
Test name
Test status
Simulation time 15523465 ps
CPU time 0.87 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 207052 kb
Host smart-720a22fd-fd86-4b9b-9a54-f38a7995bb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009476424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3009476424
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2131039802
Short name T440
Test name
Test status
Simulation time 25338719 ps
CPU time 1.11 seconds
Started Jul 03 05:30:19 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 218680 kb
Host smart-f15fdadf-fc33-4ac6-ae4a-e125c60c1df3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131039802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2131039802
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4188306074
Short name T120
Test name
Test status
Simulation time 58123325 ps
CPU time 1.02 seconds
Started Jul 03 05:30:35 PM PDT 24
Finished Jul 03 05:30:36 PM PDT 24
Peak memory 217584 kb
Host smart-3a9a128a-17be-4023-95ad-c33580660164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188306074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4188306074
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1221214806
Short name T629
Test name
Test status
Simulation time 359952234 ps
CPU time 3.07 seconds
Started Jul 03 05:30:29 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 220556 kb
Host smart-e3d50a18-fa6a-4334-87a8-137c8a80ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221214806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1221214806
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2512673472
Short name T994
Test name
Test status
Simulation time 51034347 ps
CPU time 0.83 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:40 PM PDT 24
Peak memory 215600 kb
Host smart-11df0450-37bf-4547-ab44-4f6f036ece97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512673472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2512673472
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2400369609
Short name T665
Test name
Test status
Simulation time 17238086 ps
CPU time 0.93 seconds
Started Jul 03 05:30:28 PM PDT 24
Finished Jul 03 05:30:29 PM PDT 24
Peak memory 215660 kb
Host smart-6fbc2bd5-a097-43d7-8362-b6217d2d23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400369609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2400369609
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.213569026
Short name T727
Test name
Test status
Simulation time 365673475 ps
CPU time 2.9 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 217708 kb
Host smart-a4922ee5-f685-4e98-b949-ee09f4a14f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213569026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.213569026
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.884613134
Short name T714
Test name
Test status
Simulation time 121483782468 ps
CPU time 391.69 seconds
Started Jul 03 05:30:21 PM PDT 24
Finished Jul 03 05:36:53 PM PDT 24
Peak memory 224108 kb
Host smart-92024acf-bde4-4f6b-825b-c819a5d4b40e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884613134 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.884613134
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3451137042
Short name T114
Test name
Test status
Simulation time 161017499 ps
CPU time 1.14 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 219664 kb
Host smart-c93fedd4-5471-40dd-b911-2a6e7fc97161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451137042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3451137042
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.175468610
Short name T442
Test name
Test status
Simulation time 33605640 ps
CPU time 0.86 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 206996 kb
Host smart-13444884-d09c-4460-9758-5b73de5891be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175468610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.175468610
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.915238435
Short name T23
Test name
Test status
Simulation time 165405449 ps
CPU time 0.99 seconds
Started Jul 03 05:30:37 PM PDT 24
Finished Jul 03 05:30:39 PM PDT 24
Peak memory 215716 kb
Host smart-3186a02e-9d7b-40fc-9731-56c60b2e30cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915238435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.915238435
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3444347422
Short name T133
Test name
Test status
Simulation time 46890196 ps
CPU time 1.42 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 217204 kb
Host smart-0feefb77-2d8b-4e2e-be33-a0215d9888d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444347422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3444347422
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1784275608
Short name T495
Test name
Test status
Simulation time 53087999 ps
CPU time 0.98 seconds
Started Jul 03 05:30:16 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 220300 kb
Host smart-4881e4c7-41e6-406d-b9ba-52c2493621d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784275608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1784275608
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_intr.1897946792
Short name T950
Test name
Test status
Simulation time 28769131 ps
CPU time 1.05 seconds
Started Jul 03 05:30:30 PM PDT 24
Finished Jul 03 05:30:31 PM PDT 24
Peak memory 224300 kb
Host smart-5f63599e-050a-4abd-abdc-e3f526bf55b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897946792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1897946792
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2289179292
Short name T839
Test name
Test status
Simulation time 15737359 ps
CPU time 1.01 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 215576 kb
Host smart-65c326fe-172a-4640-9664-2afba1d90573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289179292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2289179292
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.394183611
Short name T425
Test name
Test status
Simulation time 323623848 ps
CPU time 2.14 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 217648 kb
Host smart-cd16fed8-cf33-4929-b138-afff9efd42c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394183611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.394183611
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.105923715
Short name T991
Test name
Test status
Simulation time 76793229694 ps
CPU time 429.5 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:37:46 PM PDT 24
Peak memory 224032 kb
Host smart-c752dffc-4a74-41eb-81ca-0e2325595190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105923715 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.105923715
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.718922947
Short name T74
Test name
Test status
Simulation time 58218924 ps
CPU time 1.24 seconds
Started Jul 03 05:30:25 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 216248 kb
Host smart-978483a0-4847-4eff-bc42-0567798c6fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718922947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.718922947
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3280941868
Short name T256
Test name
Test status
Simulation time 17927473 ps
CPU time 0.77 seconds
Started Jul 03 05:30:35 PM PDT 24
Finished Jul 03 05:30:36 PM PDT 24
Peak memory 207104 kb
Host smart-6697b74c-83c7-4de5-930f-a41dce02ec07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280941868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3280941868
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.312307836
Short name T216
Test name
Test status
Simulation time 21385231 ps
CPU time 0.84 seconds
Started Jul 03 05:30:25 PM PDT 24
Finished Jul 03 05:30:26 PM PDT 24
Peak memory 216536 kb
Host smart-e618a0a4-2f30-4f22-87b1-cec1ae29d682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312307836 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.312307836
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2484171684
Short name T528
Test name
Test status
Simulation time 74873739 ps
CPU time 1.07 seconds
Started Jul 03 05:30:33 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 218704 kb
Host smart-599cf902-8073-457a-a303-9e1a4787cb36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484171684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2484171684
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.10570492
Short name T144
Test name
Test status
Simulation time 35056759 ps
CPU time 1.14 seconds
Started Jul 03 05:30:25 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 229736 kb
Host smart-cb47b7b4-f4aa-458b-81c9-c000b0803122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10570492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.10570492
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4100370967
Short name T965
Test name
Test status
Simulation time 73229598 ps
CPU time 2.46 seconds
Started Jul 03 05:30:33 PM PDT 24
Finished Jul 03 05:30:36 PM PDT 24
Peak memory 220484 kb
Host smart-8ed0692c-80cf-46f1-ba2d-4d58f563e50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100370967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4100370967
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4030863497
Short name T593
Test name
Test status
Simulation time 25268319 ps
CPU time 1.05 seconds
Started Jul 03 05:30:37 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 224288 kb
Host smart-dd86274b-42b7-4dc6-abbe-3d34a6ccb4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030863497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4030863497
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1652784876
Short name T596
Test name
Test status
Simulation time 14514419 ps
CPU time 0.97 seconds
Started Jul 03 05:30:28 PM PDT 24
Finished Jul 03 05:30:29 PM PDT 24
Peak memory 215608 kb
Host smart-709c9ac4-3127-4335-bcea-d614dd54722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652784876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1652784876
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3521712030
Short name T373
Test name
Test status
Simulation time 193864384 ps
CPU time 4.17 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 217676 kb
Host smart-6f4785ce-5183-4fef-b881-8e18ebf7f6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521712030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3521712030
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2950754603
Short name T962
Test name
Test status
Simulation time 688100678879 ps
CPU time 1141.59 seconds
Started Jul 03 05:30:24 PM PDT 24
Finished Jul 03 05:49:26 PM PDT 24
Peak memory 224712 kb
Host smart-b3eca4b9-c5ae-41b6-8e65-4d76c7e66ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950754603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2950754603
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1996964069
Short name T805
Test name
Test status
Simulation time 22323405 ps
CPU time 1.13 seconds
Started Jul 03 05:30:29 PM PDT 24
Finished Jul 03 05:30:31 PM PDT 24
Peak memory 220256 kb
Host smart-8c2e3fd7-56ab-43b6-851a-43b0757ca9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996964069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1996964069
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1640963121
Short name T398
Test name
Test status
Simulation time 60468454 ps
CPU time 0.98 seconds
Started Jul 03 05:30:35 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 215256 kb
Host smart-e455929b-63dd-404c-9c9c-c7bf49a15875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640963121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1640963121
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3719949953
Short name T190
Test name
Test status
Simulation time 29788338 ps
CPU time 0.78 seconds
Started Jul 03 05:30:32 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 216508 kb
Host smart-6c497d80-b0c0-44c9-87e1-526ce0114902
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719949953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3719949953
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3027599861
Short name T776
Test name
Test status
Simulation time 164392434 ps
CPU time 1.03 seconds
Started Jul 03 05:30:26 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 218828 kb
Host smart-4a546880-95af-40da-b359-ae734c631a7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027599861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3027599861
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1177841786
Short name T154
Test name
Test status
Simulation time 46999385 ps
CPU time 1.24 seconds
Started Jul 03 05:30:46 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 230000 kb
Host smart-bdd393e5-10d6-408c-9023-afdd57ba9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177841786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1177841786
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.451425512
Short name T517
Test name
Test status
Simulation time 43509679 ps
CPU time 1.53 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 217880 kb
Host smart-fa96bb1b-b964-457a-91f2-cb660fbc6a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451425512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.451425512
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2613058260
Short name T119
Test name
Test status
Simulation time 20707252 ps
CPU time 1.08 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 217036 kb
Host smart-d23af9c5-a40f-464b-97b2-99b417d9565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613058260 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2613058260
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4186178525
Short name T574
Test name
Test status
Simulation time 25910610 ps
CPU time 0.89 seconds
Started Jul 03 05:30:33 PM PDT 24
Finished Jul 03 05:30:34 PM PDT 24
Peak memory 215616 kb
Host smart-bca35817-1809-4459-9d3e-44fce06fe7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186178525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4186178525
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.797864359
Short name T435
Test name
Test status
Simulation time 55804021 ps
CPU time 1.33 seconds
Started Jul 03 05:30:25 PM PDT 24
Finished Jul 03 05:30:26 PM PDT 24
Peak memory 215524 kb
Host smart-a47890d8-69ee-4af3-b187-a64506c9b718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797864359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.797864359
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3282726675
Short name T825
Test name
Test status
Simulation time 21101422767 ps
CPU time 270.33 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:35:02 PM PDT 24
Peak memory 221188 kb
Host smart-f37a9fe3-aaac-4176-9a72-8a8e7091dd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282726675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3282726675
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1722908757
Short name T858
Test name
Test status
Simulation time 114498936 ps
CPU time 1.09 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 219988 kb
Host smart-4e918de6-57b0-4ea5-9ef1-05807bae9881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722908757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1722908757
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1153485144
Short name T707
Test name
Test status
Simulation time 23041742 ps
CPU time 0.92 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 207076 kb
Host smart-43069624-be54-45e7-b9d2-e8a551a3047a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153485144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1153485144
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2174137452
Short name T881
Test name
Test status
Simulation time 11145747 ps
CPU time 0.88 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 216600 kb
Host smart-93ebcd0a-310b-4f8a-8bbf-11ca71a7d515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174137452 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2174137452
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.575407277
Short name T185
Test name
Test status
Simulation time 28326665 ps
CPU time 0.99 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 224040 kb
Host smart-467f1d7c-4a41-47ec-8635-6f8cf3d7f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575407277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.575407277
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_intr.1102021171
Short name T663
Test name
Test status
Simulation time 26797198 ps
CPU time 0.96 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 215692 kb
Host smart-8c96fa92-87cc-460c-8b72-6a6ab3f6c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102021171 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1102021171
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4053573122
Short name T510
Test name
Test status
Simulation time 14778046 ps
CPU time 0.99 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 207432 kb
Host smart-57d09a60-400a-475d-8939-98a9e1a57365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053573122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4053573122
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.699128482
Short name T18
Test name
Test status
Simulation time 570636130 ps
CPU time 4.72 seconds
Started Jul 03 05:29:43 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 235548 kb
Host smart-bfc0ff58-05bd-4ad9-861a-06012900719f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699128482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.699128482
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2553392335
Short name T405
Test name
Test status
Simulation time 28382698 ps
CPU time 0.96 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 215584 kb
Host smart-a3902918-6656-44d9-b424-bf5b5694d3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553392335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2553392335
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.893824425
Short name T203
Test name
Test status
Simulation time 214761479 ps
CPU time 2.48 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 217492 kb
Host smart-a4aa2c21-cdef-4748-84e5-92232294511a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893824425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.893824425
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.444899469
Short name T915
Test name
Test status
Simulation time 23103746180 ps
CPU time 253.37 seconds
Started Jul 03 05:29:33 PM PDT 24
Finished Jul 03 05:33:46 PM PDT 24
Peak memory 218312 kb
Host smart-f50501e5-836b-4597-b6df-a1afe4142bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444899469 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.444899469
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3043802434
Short name T928
Test name
Test status
Simulation time 47674065 ps
CPU time 1.17 seconds
Started Jul 03 05:30:26 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 220100 kb
Host smart-1d2eaef8-9b8a-45dd-ad4b-e7b14437b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043802434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3043802434
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.625872239
Short name T621
Test name
Test status
Simulation time 37395719 ps
CPU time 0.82 seconds
Started Jul 03 05:30:24 PM PDT 24
Finished Jul 03 05:30:25 PM PDT 24
Peak memory 207060 kb
Host smart-2610a145-735d-42cf-9f52-b8b426ea221c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625872239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.625872239
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.553980776
Short name T213
Test name
Test status
Simulation time 14104111 ps
CPU time 0.88 seconds
Started Jul 03 05:30:30 PM PDT 24
Finished Jul 03 05:30:31 PM PDT 24
Peak memory 216976 kb
Host smart-e4ac0aa6-eb8b-4f51-b444-6f05f16603d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553980776 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.553980776
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.299833409
Short name T845
Test name
Test status
Simulation time 81742011 ps
CPU time 1.01 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 217308 kb
Host smart-fff7e35d-4ea1-4533-87bb-f17bdbe41633
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299833409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.299833409
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2920793369
Short name T852
Test name
Test status
Simulation time 21152400 ps
CPU time 1.1 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 218932 kb
Host smart-04b61232-4693-4b83-bfaf-aff9c1449542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920793369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2920793369
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1741181027
Short name T390
Test name
Test status
Simulation time 41689118 ps
CPU time 1.34 seconds
Started Jul 03 05:30:18 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 218820 kb
Host smart-2b958d92-73dc-480c-8b5e-2d12cf290c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741181027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1741181027
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3281529540
Short name T973
Test name
Test status
Simulation time 29565881 ps
CPU time 0.95 seconds
Started Jul 03 05:30:30 PM PDT 24
Finished Jul 03 05:30:31 PM PDT 24
Peak memory 215692 kb
Host smart-dec8c363-86f0-422c-896b-cba8a7193736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281529540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3281529540
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3117189342
Short name T362
Test name
Test status
Simulation time 18239045 ps
CPU time 0.94 seconds
Started Jul 03 05:30:20 PM PDT 24
Finished Jul 03 05:30:21 PM PDT 24
Peak memory 215620 kb
Host smart-191c22dc-fbf4-48a0-95c7-83513a88597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117189342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3117189342
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1026367615
Short name T524
Test name
Test status
Simulation time 612267661 ps
CPU time 5.91 seconds
Started Jul 03 05:30:28 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 217424 kb
Host smart-f18e485b-4462-4d49-9eb2-0fd81c46c9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026367615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1026367615
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1881821691
Short name T246
Test name
Test status
Simulation time 58966177554 ps
CPU time 646.58 seconds
Started Jul 03 05:30:26 PM PDT 24
Finished Jul 03 05:41:13 PM PDT 24
Peak memory 224008 kb
Host smart-89879203-90ab-4fdf-af75-da50bd36c659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881821691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1881821691
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.2613275236
Short name T544
Test name
Test status
Simulation time 22073215 ps
CPU time 1.08 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 207132 kb
Host smart-2e8a3d37-7846-44a5-836a-8b5f36b0423a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613275236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2613275236
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2326743124
Short name T223
Test name
Test status
Simulation time 14053485 ps
CPU time 0.92 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 216640 kb
Host smart-39044a1b-0ef2-4f82-a361-26fe7edd7daa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326743124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2326743124
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2751045587
Short name T161
Test name
Test status
Simulation time 65527990 ps
CPU time 1.21 seconds
Started Jul 03 05:30:27 PM PDT 24
Finished Jul 03 05:30:28 PM PDT 24
Peak memory 217084 kb
Host smart-a666e89c-0a56-439b-b4c5-1a5b0bd3fcc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751045587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2751045587
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2914638613
Short name T995
Test name
Test status
Simulation time 34163835 ps
CPU time 0.86 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 219360 kb
Host smart-8d2f8f38-d4cb-458e-a27c-a7c3875c64e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914638613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2914638613
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1651492567
Short name T910
Test name
Test status
Simulation time 98676133 ps
CPU time 1.13 seconds
Started Jul 03 05:30:24 PM PDT 24
Finished Jul 03 05:30:25 PM PDT 24
Peak memory 217676 kb
Host smart-1efa780a-c69c-4cd2-8428-44b62afcce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651492567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1651492567
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.217237083
Short name T780
Test name
Test status
Simulation time 27607621 ps
CPU time 1.05 seconds
Started Jul 03 05:30:30 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 224284 kb
Host smart-afd4ae60-9546-4411-944e-ccdf4e7a4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217237083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.217237083
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1009067850
Short name T111
Test name
Test status
Simulation time 52863354 ps
CPU time 0.87 seconds
Started Jul 03 05:30:29 PM PDT 24
Finished Jul 03 05:30:30 PM PDT 24
Peak memory 215628 kb
Host smart-b2ad6b39-a8d2-4c1a-a398-7e2c06903dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009067850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1009067850
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3802224560
Short name T856
Test name
Test status
Simulation time 577971453 ps
CPU time 4.14 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 217908 kb
Host smart-eb7ce2dc-4d34-456c-9895-53b77025e41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802224560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3802224560
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.360444268
Short name T243
Test name
Test status
Simulation time 42818816203 ps
CPU time 901.96 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:45:33 PM PDT 24
Peak memory 223980 kb
Host smart-f690ba8c-f038-4395-aa37-9faf19e2f0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360444268 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.360444268
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.70786064
Short name T763
Test name
Test status
Simulation time 26828145 ps
CPU time 1.24 seconds
Started Jul 03 05:30:34 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 218976 kb
Host smart-d16a8669-d62d-4113-b9d8-b88f34a7b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70786064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.70786064
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2187395664
Short name T868
Test name
Test status
Simulation time 130449492 ps
CPU time 0.74 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 206452 kb
Host smart-d31e3212-16a3-4915-b67f-9a899b801622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187395664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2187395664
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.272734706
Short name T570
Test name
Test status
Simulation time 85248512 ps
CPU time 1.43 seconds
Started Jul 03 05:30:49 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 217160 kb
Host smart-e23164c9-d037-44d5-b9df-8e5d86ac9074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272734706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.272734706
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3251407335
Short name T924
Test name
Test status
Simulation time 75237836 ps
CPU time 0.85 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 218448 kb
Host smart-a6d51097-5970-4f6f-bf25-6be0be741ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251407335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3251407335
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3626339177
Short name T855
Test name
Test status
Simulation time 101821869 ps
CPU time 1.51 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 219116 kb
Host smart-a9270743-39e3-417c-8ed6-470ab9c51c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626339177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3626339177
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1896128680
Short name T696
Test name
Test status
Simulation time 26615294 ps
CPU time 1.06 seconds
Started Jul 03 05:30:37 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 224296 kb
Host smart-508a7cef-e5e2-4a59-b487-9ba6c63c4f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896128680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1896128680
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1295970966
Short name T361
Test name
Test status
Simulation time 34276398 ps
CPU time 0.96 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 215604 kb
Host smart-b9d319d1-aaf6-42b8-b1ca-ea03475a5390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295970966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1295970966
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4272247357
Short name T396
Test name
Test status
Simulation time 235155025 ps
CPU time 2.88 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 217432 kb
Host smart-cd89837b-9d90-4235-bc52-e15253df72be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272247357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4272247357
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.1658059355
Short name T631
Test name
Test status
Simulation time 29885342 ps
CPU time 1.31 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 219016 kb
Host smart-ff29740b-ced8-4a95-aae8-84eb5c8627d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658059355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1658059355
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1293670570
Short name T703
Test name
Test status
Simulation time 35911901 ps
CPU time 1 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 215468 kb
Host smart-dd04459f-7ecd-4431-ba2a-e0b30df9b5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293670570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1293670570
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2532243870
Short name T975
Test name
Test status
Simulation time 32328317 ps
CPU time 1.08 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 217144 kb
Host smart-4b4bd476-b6a9-4c66-8836-bc91cbc77bb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532243870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2532243870
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3525254359
Short name T658
Test name
Test status
Simulation time 58507668 ps
CPU time 0.97 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 219976 kb
Host smart-1be3e3fa-a1bd-4ec9-816d-b5e88249d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525254359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3525254359
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.490078948
Short name T902
Test name
Test status
Simulation time 212177948 ps
CPU time 1.51 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 218820 kb
Host smart-240f757d-5e3d-4fb6-9868-25fb7ba2ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490078948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.490078948
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3013120230
Short name T891
Test name
Test status
Simulation time 24668748 ps
CPU time 0.96 seconds
Started Jul 03 05:30:48 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 216108 kb
Host smart-c16ad802-8f9b-41e7-8e72-0cd3a8dbf899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013120230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3013120230
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1767901146
Short name T364
Test name
Test status
Simulation time 52675609 ps
CPU time 0.93 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 215580 kb
Host smart-fe8d7aa5-3f29-49c7-8c58-61d7e8ad1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767901146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1767901146
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3405513330
Short name T368
Test name
Test status
Simulation time 735501825 ps
CPU time 3.58 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 215632 kb
Host smart-abe36ae7-e4cf-49a6-8445-3ef3b2a3ad9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405513330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3405513330
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3493410785
Short name T236
Test name
Test status
Simulation time 151098051066 ps
CPU time 327.46 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:36:07 PM PDT 24
Peak memory 219304 kb
Host smart-cd6e406c-3a65-44bd-81fa-95185ecf9a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493410785 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3493410785
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3118270378
Short name T740
Test name
Test status
Simulation time 43343728 ps
CPU time 1.14 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 220028 kb
Host smart-6cc47f44-269a-490f-bea4-593267540f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118270378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3118270378
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4014263096
Short name T938
Test name
Test status
Simulation time 15050203 ps
CPU time 0.92 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 207020 kb
Host smart-3fb7aa83-9f1e-45ba-9601-c1b2ea10683c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014263096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4014263096
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1135040438
Short name T132
Test name
Test status
Simulation time 91036563 ps
CPU time 0.97 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 217004 kb
Host smart-a2337a35-e80d-45f8-bb97-587cec87384c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135040438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1135040438
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3416251287
Short name T427
Test name
Test status
Simulation time 42121215 ps
CPU time 0.96 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 220060 kb
Host smart-526d8d75-af25-4c9a-853a-d36fe58aa4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416251287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3416251287
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.79774872
Short name T302
Test name
Test status
Simulation time 34858724 ps
CPU time 1.32 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 217800 kb
Host smart-d897e8c0-3a84-49df-91e8-c37de8b88e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79774872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.79774872
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3629156958
Short name T369
Test name
Test status
Simulation time 31148016 ps
CPU time 0.93 seconds
Started Jul 03 05:30:33 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 215772 kb
Host smart-40308354-92dd-40e6-ad8c-a3e10c1923a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629156958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3629156958
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2707613756
Short name T389
Test name
Test status
Simulation time 14881676 ps
CPU time 0.95 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 215656 kb
Host smart-b8098cc1-4dbb-44f6-90c1-4ed567fe1c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707613756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2707613756
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2809438761
Short name T912
Test name
Test status
Simulation time 68454219 ps
CPU time 1.76 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 215412 kb
Host smart-6a82f8e5-bcf0-4583-b392-ef6700502f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809438761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2809438761
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3006517793
Short name T458
Test name
Test status
Simulation time 25582777420 ps
CPU time 326.3 seconds
Started Jul 03 05:30:30 PM PDT 24
Finished Jul 03 05:35:56 PM PDT 24
Peak memory 224032 kb
Host smart-c4e4edc7-d84d-49d5-8bfb-39cf6505e0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006517793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3006517793
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2937337595
Short name T826
Test name
Test status
Simulation time 52619553 ps
CPU time 1.21 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:40 PM PDT 24
Peak memory 220164 kb
Host smart-f23c6d89-dec6-4ae8-84a2-3a887dd6fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937337595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2937337595
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.333136773
Short name T581
Test name
Test status
Simulation time 46907337 ps
CPU time 0.79 seconds
Started Jul 03 05:30:33 PM PDT 24
Finished Jul 03 05:30:34 PM PDT 24
Peak memory 206860 kb
Host smart-82f05a79-5e11-42ad-8754-12879fdf149c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333136773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.333136773
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1893693356
Short name T202
Test name
Test status
Simulation time 43823687 ps
CPU time 0.88 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 216636 kb
Host smart-51b2e3b0-09f8-462c-b409-dad214a036e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893693356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1893693356
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1879754828
Short name T812
Test name
Test status
Simulation time 31720083 ps
CPU time 1.09 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 218628 kb
Host smart-eb916307-c2e9-4d02-99a5-3092d0c3ca8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879754828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1879754828
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1489235209
Short name T953
Test name
Test status
Simulation time 30525949 ps
CPU time 0.89 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 215480 kb
Host smart-a6faf336-54e5-4a8a-bdc9-00adafd75dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489235209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1489235209
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1420328817
Short name T884
Test name
Test status
Simulation time 40431355 ps
CPU time 1.35 seconds
Started Jul 03 05:30:28 PM PDT 24
Finished Jul 03 05:30:30 PM PDT 24
Peak memory 219080 kb
Host smart-c2b6345b-9bd7-498e-8645-36f48d1a6a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420328817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1420328817
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1369318395
Short name T59
Test name
Test status
Simulation time 26643072 ps
CPU time 1.03 seconds
Started Jul 03 05:30:32 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 224320 kb
Host smart-a06cd7f6-0831-43ab-bb2b-c8d6a798bb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369318395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1369318395
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3548513434
Short name T810
Test name
Test status
Simulation time 19072187 ps
CPU time 1.02 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 215532 kb
Host smart-a45d11de-4896-45e1-8b7d-3089a0830bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548513434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3548513434
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1183675708
Short name T871
Test name
Test status
Simulation time 477752584 ps
CPU time 2.66 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 217432 kb
Host smart-e3e4052a-d0ab-44e7-96fa-ea26224687bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183675708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1183675708
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1401705722
Short name T787
Test name
Test status
Simulation time 193542985927 ps
CPU time 1292.64 seconds
Started Jul 03 05:30:34 PM PDT 24
Finished Jul 03 05:52:07 PM PDT 24
Peak memory 224812 kb
Host smart-f43d4e33-ecf8-424e-a93b-42542af1810b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401705722 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1401705722
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.593059799
Short name T730
Test name
Test status
Simulation time 43290303 ps
CPU time 1.14 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 220744 kb
Host smart-cf2afc53-16f4-4d58-831c-7c41d6a5fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593059799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.593059799
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4184762437
Short name T883
Test name
Test status
Simulation time 26485467 ps
CPU time 0.86 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:39 PM PDT 24
Peak memory 206984 kb
Host smart-15e22adc-a5df-4b74-aadd-c639d0e43638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184762437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4184762437
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2167619434
Short name T210
Test name
Test status
Simulation time 64936315 ps
CPU time 0.91 seconds
Started Jul 03 05:30:31 PM PDT 24
Finished Jul 03 05:30:33 PM PDT 24
Peak memory 216636 kb
Host smart-3ea48ae1-6778-4d4d-b8ae-a008362efcb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167619434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2167619434
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.655605031
Short name T301
Test name
Test status
Simulation time 66670826 ps
CPU time 1.09 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 217256 kb
Host smart-8b890810-7c9a-4331-999d-524087fc78b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655605031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.655605031
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.238741619
Short name T992
Test name
Test status
Simulation time 107446505 ps
CPU time 1.02 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 218796 kb
Host smart-bd9152a9-01ea-4859-b56e-21e9aaed840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238741619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.238741619
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4148671222
Short name T652
Test name
Test status
Simulation time 39643760 ps
CPU time 1.55 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 217580 kb
Host smart-3262eca1-d2d9-46ea-926f-ad6c24c2e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148671222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4148671222
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1244981366
Short name T70
Test name
Test status
Simulation time 24186450 ps
CPU time 0.93 seconds
Started Jul 03 05:30:34 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 215732 kb
Host smart-c3c2e179-f5a9-4372-8f97-e966f7d529d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244981366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1244981366
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1517162284
Short name T699
Test name
Test status
Simulation time 52292802 ps
CPU time 0.9 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 215624 kb
Host smart-a0cf4d38-20f2-4cbe-8295-587d1ea66e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517162284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1517162284
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1348308071
Short name T105
Test name
Test status
Simulation time 2087057156 ps
CPU time 4.35 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 215604 kb
Host smart-999720df-ffbf-4749-ae88-55cc7806041a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348308071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1348308071
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3403337306
Short name T653
Test name
Test status
Simulation time 73812883554 ps
CPU time 1630.12 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:57:50 PM PDT 24
Peak memory 227004 kb
Host smart-6735ea53-237a-46b5-b45f-71aa1b96e5c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403337306 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3403337306
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2887429709
Short name T867
Test name
Test status
Simulation time 24326353 ps
CPU time 1.19 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 218952 kb
Host smart-c4da4868-bf65-4fdf-8546-e3b4f1dc1bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887429709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2887429709
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1397362171
Short name T600
Test name
Test status
Simulation time 70108940 ps
CPU time 0.81 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 207096 kb
Host smart-d7a7a4c6-ea05-41f6-9942-8150cf7ef307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397362171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1397362171
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1214916026
Short name T934
Test name
Test status
Simulation time 21335981 ps
CPU time 0.87 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:38 PM PDT 24
Peak memory 216220 kb
Host smart-9d886c70-a088-46ad-81ab-d0b607295b14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214916026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1214916026
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2290772323
Short name T160
Test name
Test status
Simulation time 106351088 ps
CPU time 1.14 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 217416 kb
Host smart-195597c4-f297-4074-9d26-65e291747f5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290772323 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2290772323
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.486291323
Short name T196
Test name
Test status
Simulation time 31077510 ps
CPU time 0.97 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 224144 kb
Host smart-1085810e-b30b-4aeb-a822-fc15d3f47c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486291323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.486291323
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3807977416
Short name T521
Test name
Test status
Simulation time 50607009 ps
CPU time 1.3 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 219148 kb
Host smart-3780d001-b2a9-4db9-a6db-e58ca69837bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807977416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3807977416
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2697788696
Short name T69
Test name
Test status
Simulation time 54330649 ps
CPU time 0.89 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 215540 kb
Host smart-c4b71083-adc9-49d6-b67a-7b6195fb0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697788696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2697788696
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3645792136
Short name T628
Test name
Test status
Simulation time 29998362 ps
CPU time 0.95 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 215588 kb
Host smart-c907d0ca-bc20-4adb-ac24-e0823b4495c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645792136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3645792136
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.295951481
Short name T789
Test name
Test status
Simulation time 295605720 ps
CPU time 5.47 seconds
Started Jul 03 05:30:38 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 215692 kb
Host smart-5fe65570-b5a5-464a-bd45-a58114729c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295951481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.295951481
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2922588253
Short name T795
Test name
Test status
Simulation time 168408396904 ps
CPU time 1792.05 seconds
Started Jul 03 05:30:48 PM PDT 24
Finished Jul 03 06:00:41 PM PDT 24
Peak memory 226464 kb
Host smart-02930098-12ea-4f23-96d0-093e2d08ca8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922588253 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2922588253
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.1937823229
Short name T688
Test name
Test status
Simulation time 13260474 ps
CPU time 0.91 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 207244 kb
Host smart-bb070e0b-a63b-4ba0-8a86-44fd7b366185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937823229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1937823229
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1950176957
Short name T958
Test name
Test status
Simulation time 12619834 ps
CPU time 0.9 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 216720 kb
Host smart-8178f4c4-ffd0-4f6e-9eb6-750c534774f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950176957 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1950176957
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2757467170
Short name T904
Test name
Test status
Simulation time 44480434 ps
CPU time 1.32 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 219692 kb
Host smart-14869823-677d-4949-9c0b-97f565595cbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757467170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2757467170
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3589559252
Short name T754
Test name
Test status
Simulation time 20972284 ps
CPU time 0.93 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 218856 kb
Host smart-8fb6c710-9a47-40a7-9beb-8077d96c6805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589559252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3589559252
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1181617728
Short name T607
Test name
Test status
Simulation time 34333422 ps
CPU time 1.37 seconds
Started Jul 03 05:30:48 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 220472 kb
Host smart-4e5a4d75-512e-43c7-86e0-ac4c582201b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181617728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1181617728
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1147541559
Short name T35
Test name
Test status
Simulation time 24055309 ps
CPU time 0.92 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 216228 kb
Host smart-d7e6cb5c-75c5-4bb1-bc11-413b812d8f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147541559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1147541559
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3325902831
Short name T914
Test name
Test status
Simulation time 14680652 ps
CPU time 1.01 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 215608 kb
Host smart-5f29a30e-0d47-4d82-bd6b-a881168996ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325902831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3325902831
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1163280108
Short name T249
Test name
Test status
Simulation time 706675619 ps
CPU time 5.47 seconds
Started Jul 03 05:30:29 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 217444 kb
Host smart-cd9fe507-555d-44f3-9d43-e8abb276c0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163280108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1163280108
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3389222020
Short name T955
Test name
Test status
Simulation time 141382084128 ps
CPU time 1096.96 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:49:02 PM PDT 24
Peak memory 222496 kb
Host smart-369d1ed1-2b08-456e-88eb-990a81865606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389222020 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3389222020
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3689140300
Short name T565
Test name
Test status
Simulation time 91648180 ps
CPU time 1.27 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 219056 kb
Host smart-718669c6-79fa-4443-bd48-90abe135be10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689140300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3689140300
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1119199310
Short name T66
Test name
Test status
Simulation time 15147622 ps
CPU time 0.94 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 207060 kb
Host smart-ef5c8caa-7870-47b7-95cf-5c5aa7884e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119199310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1119199310
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2165399929
Short name T525
Test name
Test status
Simulation time 113182720 ps
CPU time 0.9 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 215648 kb
Host smart-9093f447-27c7-4363-b4f6-96471b3abb43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165399929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2165399929
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3872286427
Short name T399
Test name
Test status
Simulation time 74566683 ps
CPU time 1.11 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 218828 kb
Host smart-2b516af0-9b2b-4a98-9e52-c4d00e3b9975
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872286427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3872286427
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.649277805
Short name T378
Test name
Test status
Simulation time 31114411 ps
CPU time 1.07 seconds
Started Jul 03 05:30:35 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 218864 kb
Host smart-a16a2539-c572-4d39-95e3-fb5acb0336d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649277805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.649277805
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1535765893
Short name T755
Test name
Test status
Simulation time 29487605 ps
CPU time 1.22 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 220372 kb
Host smart-63b270d8-f6a2-489f-8cd6-50270361f9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535765893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1535765893
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.41762027
Short name T103
Test name
Test status
Simulation time 43129388 ps
CPU time 0.83 seconds
Started Jul 03 05:30:34 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 215860 kb
Host smart-3affd647-08dd-45b1-8c5e-04c4b172b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41762027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.41762027
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.409607640
Short name T580
Test name
Test status
Simulation time 50483410 ps
CPU time 0.97 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 215528 kb
Host smart-d3a96c94-c736-465d-a04b-d4e3483be525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409607640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.409607640
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2929121684
Short name T107
Test name
Test status
Simulation time 148249378 ps
CPU time 3.32 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 217780 kb
Host smart-47697606-7800-492b-830d-4c7ebacefdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929121684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2929121684
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.3374088088
Short name T169
Test name
Test status
Simulation time 81205916 ps
CPU time 1.08 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 218800 kb
Host smart-184ba4b0-4990-4e4e-87a4-9befdd7a3c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374088088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3374088088
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3536676560
Short name T959
Test name
Test status
Simulation time 26516916 ps
CPU time 0.93 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 215232 kb
Host smart-54dc3298-4e78-4e35-b4b4-369295c9436a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536676560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3536676560
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2903763223
Short name T838
Test name
Test status
Simulation time 260654241 ps
CPU time 1.12 seconds
Started Jul 03 05:29:42 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 219968 kb
Host smart-11a83b98-45df-47b1-9838-9320f080e66b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903763223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2903763223
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3621762589
Short name T187
Test name
Test status
Simulation time 25774923 ps
CPU time 0.95 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 218756 kb
Host smart-a036c91f-e360-4e97-9e0d-18249feb3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621762589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3621762589
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2246816197
Short name T493
Test name
Test status
Simulation time 32522743 ps
CPU time 1.31 seconds
Started Jul 03 05:29:38 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 219120 kb
Host smart-c228276e-fe89-4ef9-ad63-6e483741e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246816197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2246816197
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2856302836
Short name T80
Test name
Test status
Simulation time 22609873 ps
CPU time 1.02 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 215792 kb
Host smart-bf707d14-8422-4618-a303-7306896a2ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856302836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2856302836
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.4070576794
Short name T507
Test name
Test status
Simulation time 44916258 ps
CPU time 0.92 seconds
Started Jul 03 05:29:40 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 207332 kb
Host smart-f5fbb3ac-54a8-4468-9313-15ecd6834aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070576794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4070576794
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1341839176
Short name T437
Test name
Test status
Simulation time 16128811 ps
CPU time 0.93 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 215604 kb
Host smart-81b35fb5-223f-41c2-96c4-e920dc314311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341839176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1341839176
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2381419634
Short name T722
Test name
Test status
Simulation time 262454806 ps
CPU time 3.33 seconds
Started Jul 03 05:29:36 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 215568 kb
Host smart-68a48b47-c13c-4c2d-abdd-e1e6b9696f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381419634 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2381419634
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1317426517
Short name T479
Test name
Test status
Simulation time 129506642183 ps
CPU time 1528.74 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:55:07 PM PDT 24
Peak memory 224932 kb
Host smart-a3284393-ae63-49d0-b9ed-46c01b790974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317426517 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1317426517
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.718376271
Short name T497
Test name
Test status
Simulation time 36165310 ps
CPU time 1.34 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 216000 kb
Host smart-43cba952-616c-41d3-aa2e-3b7d4d3ddc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718376271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.718376271
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1727655429
Short name T954
Test name
Test status
Simulation time 32027467 ps
CPU time 0.92 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 218676 kb
Host smart-bac5b89e-1173-412a-9e8c-a9d840b9600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727655429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1727655429
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4290920773
Short name T356
Test name
Test status
Simulation time 56838634 ps
CPU time 2.05 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 219616 kb
Host smart-01a5bdfb-0957-426a-95bc-e25d1f9c4b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290920773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4290920773
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.4120580074
Short name T139
Test name
Test status
Simulation time 22154853 ps
CPU time 1.14 seconds
Started Jul 03 05:30:40 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 220888 kb
Host smart-930250ed-e80a-481d-83e1-2376d46d2a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120580074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4120580074
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3991942622
Short name T712
Test name
Test status
Simulation time 110488901 ps
CPU time 1.26 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 220656 kb
Host smart-58b97cb7-774e-43d9-93c9-16a2da09477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991942622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3991942622
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1475815528
Short name T794
Test name
Test status
Simulation time 25759436 ps
CPU time 1.15 seconds
Started Jul 03 05:30:36 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 220104 kb
Host smart-dc2773bc-c4ec-4db1-b165-6d74a53f3816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475815528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1475815528
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3958351555
Short name T481
Test name
Test status
Simulation time 190160786 ps
CPU time 1.26 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 225936 kb
Host smart-bcc320d1-469e-4e9c-8ce7-334c71aaf6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958351555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3958351555
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.216806622
Short name T630
Test name
Test status
Simulation time 71540229 ps
CPU time 1.04 seconds
Started Jul 03 05:30:46 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 217568 kb
Host smart-ce1501a8-0150-4470-b941-3e34e5c7feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216806622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.216806622
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1608920072
Short name T832
Test name
Test status
Simulation time 414415262 ps
CPU time 1.63 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 218748 kb
Host smart-6eb4c27e-7ac8-4e3a-8534-f017856a678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608920072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1608920072
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.643173438
Short name T188
Test name
Test status
Simulation time 19229191 ps
CPU time 0.95 seconds
Started Jul 03 05:30:49 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 218892 kb
Host smart-eaf2ae4b-5a9d-4d42-84d4-e49248b1526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643173438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.643173438
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3889535304
Short name T779
Test name
Test status
Simulation time 58370263 ps
CPU time 1.25 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 219276 kb
Host smart-41ce56d7-e1a1-4e32-84d8-54ffde670c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889535304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3889535304
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3907136734
Short name T830
Test name
Test status
Simulation time 36472523 ps
CPU time 0.91 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 218460 kb
Host smart-4cc9f3da-b4a9-4b57-82b9-bb58ddc0c333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907136734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3907136734
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3243269168
Short name T62
Test name
Test status
Simulation time 86316738 ps
CPU time 0.9 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:40 PM PDT 24
Peak memory 217560 kb
Host smart-b95c8cf8-db86-4c9b-99da-bf030fbcff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243269168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3243269168
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2328028769
Short name T170
Test name
Test status
Simulation time 59977170 ps
CPU time 1.08 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 218764 kb
Host smart-562503aa-782b-4698-a445-edd8a97fb79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328028769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2328028769
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2114211737
Short name T56
Test name
Test status
Simulation time 43334185 ps
CPU time 1.21 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 225924 kb
Host smart-de2a3430-668e-4a80-b7a8-c5c28d6a82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114211737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2114211737
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1201020958
Short name T747
Test name
Test status
Simulation time 76537396 ps
CPU time 1.2 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 215672 kb
Host smart-d3f30067-5f31-4b76-a2a5-be0e65f2cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201020958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1201020958
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2378711891
Short name T259
Test name
Test status
Simulation time 32941925 ps
CPU time 1.33 seconds
Started Jul 03 05:30:42 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 220000 kb
Host smart-aaf8bea6-a732-46a0-b46c-e3a25b138ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378711891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2378711891
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3067850112
Short name T967
Test name
Test status
Simulation time 21560302 ps
CPU time 1.17 seconds
Started Jul 03 05:30:49 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 229836 kb
Host smart-4fecd630-fb4b-4df4-b546-f68f92e057ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067850112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3067850112
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.960820252
Short name T383
Test name
Test status
Simulation time 38027654 ps
CPU time 1.41 seconds
Started Jul 03 05:30:48 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 218936 kb
Host smart-3a780bcf-3978-4bdc-9ee6-61524f09ef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960820252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.960820252
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1551599715
Short name T917
Test name
Test status
Simulation time 24988935 ps
CPU time 1.2 seconds
Started Jul 03 05:30:39 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 218752 kb
Host smart-bd4a1d42-0a89-4f3e-95a2-d70d49aef9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551599715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1551599715
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.430033262
Short name T227
Test name
Test status
Simulation time 30267609 ps
CPU time 0.89 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 218616 kb
Host smart-6b8fd758-32d3-49a4-a4e0-96536b3a993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430033262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.430033262
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3026190631
Short name T553
Test name
Test status
Simulation time 208437732 ps
CPU time 1.47 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 218952 kb
Host smart-411d63d1-275c-454b-806e-7d871443f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026190631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3026190631
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.626421650
Short name T117
Test name
Test status
Simulation time 38399648 ps
CPU time 1.1 seconds
Started Jul 03 05:30:48 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 218988 kb
Host smart-6888142d-4b51-4093-a79f-f682c0c9f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626421650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.626421650
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2572764225
Short name T431
Test name
Test status
Simulation time 22982435 ps
CPU time 0.95 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 218900 kb
Host smart-ca88f6bd-2d41-47d9-8d6c-1d82177f4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572764225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2572764225
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3316864047
Short name T782
Test name
Test status
Simulation time 52079256 ps
CPU time 1.09 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 217556 kb
Host smart-c4710d38-f4ca-49e6-b49f-ddb0dab52cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316864047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3316864047
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3383812435
Short name T816
Test name
Test status
Simulation time 23081955 ps
CPU time 1.12 seconds
Started Jul 03 05:30:46 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 219008 kb
Host smart-cc4fd41c-d198-463e-8779-85207d0343c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383812435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3383812435
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.803240982
Short name T173
Test name
Test status
Simulation time 31208372 ps
CPU time 0.86 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 218784 kb
Host smart-ed661f7c-ce58-492a-aaa3-c2ac8169071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803240982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.803240982
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3358345680
Short name T85
Test name
Test status
Simulation time 235017384 ps
CPU time 1.26 seconds
Started Jul 03 05:30:53 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 217732 kb
Host smart-6cde83a2-f907-4052-ba6f-36fd8fa97fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358345680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3358345680
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2719480023
Short name T724
Test name
Test status
Simulation time 27731065 ps
CPU time 1.27 seconds
Started Jul 03 05:29:36 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 220256 kb
Host smart-19f25607-f751-4a3d-965d-b27700c8c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719480023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2719480023
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2999276807
Short name T769
Test name
Test status
Simulation time 33264320 ps
CPU time 1.01 seconds
Started Jul 03 05:29:41 PM PDT 24
Finished Jul 03 05:29:42 PM PDT 24
Peak memory 207032 kb
Host smart-a649fc0a-a327-4ff7-8494-aa22371e08ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999276807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2999276807
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3094624569
Short name T588
Test name
Test status
Simulation time 13399902 ps
CPU time 0.91 seconds
Started Jul 03 05:29:41 PM PDT 24
Finished Jul 03 05:29:42 PM PDT 24
Peak memory 216712 kb
Host smart-a4bf5f0b-b276-4757-a9ef-6710edf1f012
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094624569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3094624569
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2437623896
Short name T451
Test name
Test status
Simulation time 97322649 ps
CPU time 0.98 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 217220 kb
Host smart-a1e4d684-81d0-4056-8167-482aeb11a479
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437623896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2437623896
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2317157181
Short name T485
Test name
Test status
Simulation time 31879446 ps
CPU time 1.19 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 224304 kb
Host smart-6faf0fc9-acca-456c-8fc1-5c8f754f5d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317157181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2317157181
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2574310662
Short name T82
Test name
Test status
Simulation time 27061277 ps
CPU time 1.4 seconds
Started Jul 03 05:29:43 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 220456 kb
Host smart-4b37e5d6-64a8-4c3d-b5dd-32069e69b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574310662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2574310662
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.619926711
Short name T34
Test name
Test status
Simulation time 21892422 ps
CPU time 1.12 seconds
Started Jul 03 05:29:36 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 216132 kb
Host smart-3c8877b7-5b64-4b7f-ad24-642968305bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619926711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.619926711
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1845615497
Short name T30
Test name
Test status
Simulation time 27387371 ps
CPU time 0.94 seconds
Started Jul 03 05:29:35 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 207428 kb
Host smart-877ad62b-2407-4b6f-beed-91d88df556c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845615497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1845615497
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.915947170
Short name T403
Test name
Test status
Simulation time 15437716 ps
CPU time 0.99 seconds
Started Jul 03 05:29:37 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 215584 kb
Host smart-17f62899-1070-402f-b952-f4098b1736e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915947170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.915947170
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2913152893
Short name T252
Test name
Test status
Simulation time 531967121 ps
CPU time 5.36 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 218880 kb
Host smart-f2b3a8a0-76d2-4d35-8df6-2f5b623b04fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913152893 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2913152893
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.394412005
Short name T896
Test name
Test status
Simulation time 98583086 ps
CPU time 1.27 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 220012 kb
Host smart-de637b5d-3c0b-4ba6-a7a3-ce6e048e5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394412005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.394412005
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2384348325
Short name T932
Test name
Test status
Simulation time 29120199 ps
CPU time 1.04 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 218952 kb
Host smart-e8e40c68-288b-4719-9f2f-3d3dc35095d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384348325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2384348325
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2517874926
Short name T541
Test name
Test status
Simulation time 38612021 ps
CPU time 1.43 seconds
Started Jul 03 05:30:49 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 217624 kb
Host smart-f8ffbfbc-c4f0-46e8-bd1f-22a506373705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517874926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2517874926
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3053518012
Short name T717
Test name
Test status
Simulation time 45346102 ps
CPU time 1.18 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 220104 kb
Host smart-0a8cca85-4e17-4f2f-ab20-efa10c2bd192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053518012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3053518012
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1746159235
Short name T573
Test name
Test status
Simulation time 21777959 ps
CPU time 0.9 seconds
Started Jul 03 05:30:49 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 218924 kb
Host smart-31480351-b67f-4575-b71f-cbad38b6e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746159235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1746159235
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3527443021
Short name T788
Test name
Test status
Simulation time 74561137 ps
CPU time 1.36 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 217508 kb
Host smart-94088ae2-20cc-4ebe-9e1d-05cbbabaf876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527443021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3527443021
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2263419772
Short name T770
Test name
Test status
Simulation time 26986605 ps
CPU time 1.23 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 220168 kb
Host smart-9b155b08-67b7-4b20-9065-dc5c9d9974b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263419772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2263419772
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2032341206
Short name T391
Test name
Test status
Simulation time 29793472 ps
CPU time 0.99 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 218536 kb
Host smart-9161dade-fc6d-461d-8ba9-984b9fe97aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032341206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2032341206
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1923258507
Short name T705
Test name
Test status
Simulation time 60073975 ps
CPU time 1.15 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 217704 kb
Host smart-11de2993-b36d-42c8-8b5f-bfb99dc946f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923258507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1923258507
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1971527744
Short name T193
Test name
Test status
Simulation time 30485089 ps
CPU time 1.29 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 221216 kb
Host smart-2bc4730b-6d67-44f7-a97f-e6e0b5841732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971527744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1971527744
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3509624095
Short name T57
Test name
Test status
Simulation time 97660630 ps
CPU time 1.17 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 226080 kb
Host smart-f2820ce5-dc55-4b97-a308-66de7dde6f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509624095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3509624095
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4102780319
Short name T386
Test name
Test status
Simulation time 49790333 ps
CPU time 1.52 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 217660 kb
Host smart-e8831ea8-ec8a-4b34-ad4b-f017b8a04f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102780319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4102780319
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3226474312
Short name T961
Test name
Test status
Simulation time 23542793 ps
CPU time 1.19 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 218972 kb
Host smart-c28329d0-926b-4cb6-856d-dbe13b00397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226474312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3226474312
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2247846022
Short name T152
Test name
Test status
Simulation time 33251803 ps
CPU time 1.21 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 230032 kb
Host smart-46e4f30d-572a-4c56-9cd2-2e8d24abb84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247846022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2247846022
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1699358929
Short name T627
Test name
Test status
Simulation time 79608287 ps
CPU time 2.71 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 215616 kb
Host smart-68366aef-eebe-412a-a408-ee9d7aa0c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699358929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1699358929
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.615045407
Short name T494
Test name
Test status
Simulation time 49961543 ps
CPU time 1.26 seconds
Started Jul 03 05:30:45 PM PDT 24
Finished Jul 03 05:30:47 PM PDT 24
Peak memory 220172 kb
Host smart-ee6bd69f-d7b7-4b8c-91f9-15e883f78ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615045407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.615045407
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3205321149
Short name T820
Test name
Test status
Simulation time 89841814 ps
CPU time 0.83 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 218420 kb
Host smart-4a29e2ad-10c0-4db8-90ea-b30b96b2a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205321149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3205321149
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4209900330
Short name T409
Test name
Test status
Simulation time 101231847 ps
CPU time 1.01 seconds
Started Jul 03 05:30:41 PM PDT 24
Finished Jul 03 05:30:43 PM PDT 24
Peak memory 217748 kb
Host smart-b273e728-11ad-4bfb-bab5-cad1df625ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209900330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4209900330
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.649231009
Short name T428
Test name
Test status
Simulation time 53126923 ps
CPU time 1.2 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 220068 kb
Host smart-317b70dc-9666-4ed6-802e-7db2974bdc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649231009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.649231009
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1352691640
Short name T598
Test name
Test status
Simulation time 28442632 ps
CPU time 0.94 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 218796 kb
Host smart-04c8c8f2-b695-4569-9dd4-1d6a27024e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352691640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1352691640
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4061625395
Short name T684
Test name
Test status
Simulation time 71010204 ps
CPU time 1.49 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 218860 kb
Host smart-d3511342-ff97-4fe8-bfe1-d441b59bf748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061625395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4061625395
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1874203675
Short name T163
Test name
Test status
Simulation time 78188070 ps
CPU time 1.11 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 220196 kb
Host smart-e7e19ffc-ef49-4789-8d89-3798a08659d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874203675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1874203675
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.4253860361
Short name T162
Test name
Test status
Simulation time 19689959 ps
CPU time 1.13 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 218836 kb
Host smart-b1c0418a-c641-4ce0-b233-963131956224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253860361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4253860361
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1353071482
Short name T385
Test name
Test status
Simulation time 36786658 ps
CPU time 1.48 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 219164 kb
Host smart-bd979d78-0882-41aa-9a05-d74871e9e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353071482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1353071482
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1421807628
Short name T933
Test name
Test status
Simulation time 26624072 ps
CPU time 1.2 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 218736 kb
Host smart-6ccef360-80de-40e1-88c7-5530ad36a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421807628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1421807628
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.228023092
Short name T125
Test name
Test status
Simulation time 35988847 ps
CPU time 1.03 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 229912 kb
Host smart-86d6e4b1-8a72-4264-8657-6caa8ed3be54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228023092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.228023092
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1580707899
Short name T411
Test name
Test status
Simulation time 519516872 ps
CPU time 3.75 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 219960 kb
Host smart-50c000a1-1164-4a2a-ae77-52c984fe917f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580707899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1580707899
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3253075380
Short name T353
Test name
Test status
Simulation time 181252953 ps
CPU time 1.24 seconds
Started Jul 03 05:30:43 PM PDT 24
Finished Jul 03 05:30:44 PM PDT 24
Peak memory 219628 kb
Host smart-a4d1aa94-1fb1-48e5-be8a-fb7a9d343f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253075380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3253075380
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.447958864
Short name T935
Test name
Test status
Simulation time 19683890 ps
CPU time 1.22 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 224240 kb
Host smart-cb33125c-3d5c-4f63-8794-69c5b45277a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447958864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.447958864
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2416939933
Short name T734
Test name
Test status
Simulation time 42911769 ps
CPU time 1.48 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 219088 kb
Host smart-8e378ea1-9cbb-4bd8-8eff-7828e3f9b262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416939933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2416939933
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3822824421
Short name T298
Test name
Test status
Simulation time 23041361 ps
CPU time 1.23 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 219100 kb
Host smart-f5ac0380-fa3a-4f1a-924a-8cdb3e530812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822824421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3822824421
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2407038084
Short name T615
Test name
Test status
Simulation time 22056160 ps
CPU time 1 seconds
Started Jul 03 05:29:41 PM PDT 24
Finished Jul 03 05:29:42 PM PDT 24
Peak memory 215192 kb
Host smart-4e2d4754-787d-42ab-9ae0-44f99a02355e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407038084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2407038084
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4204189721
Short name T214
Test name
Test status
Simulation time 51197175 ps
CPU time 0.8 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 216656 kb
Host smart-b119f950-fbe8-42c6-a39b-049be859c3bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204189721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4204189721
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2190253367
Short name T781
Test name
Test status
Simulation time 62597964 ps
CPU time 1.12 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 217304 kb
Host smart-b504ca3c-2bf9-41ab-a6e3-c11e491c2723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190253367 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2190253367
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.839709534
Short name T9
Test name
Test status
Simulation time 19633327 ps
CPU time 1.12 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 219008 kb
Host smart-a663f20e-1ec9-4d79-9934-104a5380014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839709534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.839709534
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3819334391
Short name T800
Test name
Test status
Simulation time 73857583 ps
CPU time 1.08 seconds
Started Jul 03 05:29:44 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 217464 kb
Host smart-c0b2d273-3c5e-447d-a7a0-eb266cd2230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819334391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3819334391
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4271270639
Short name T698
Test name
Test status
Simulation time 53250794 ps
CPU time 0.86 seconds
Started Jul 03 05:29:40 PM PDT 24
Finished Jul 03 05:29:42 PM PDT 24
Peak memory 215968 kb
Host smart-e21f85c5-a36d-4e85-a028-5392f5376b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271270639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4271270639
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.488114487
Short name T829
Test name
Test status
Simulation time 24084579 ps
CPU time 0.91 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 207408 kb
Host smart-ac218966-6097-4b24-b793-bd04b23e7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488114487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.488114487
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2433891201
Short name T990
Test name
Test status
Simulation time 121421182 ps
CPU time 0.9 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 215584 kb
Host smart-b96ebedf-a9e2-4581-a591-d525b55fdba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433891201 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2433891201
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3952242495
Short name T911
Test name
Test status
Simulation time 228842058 ps
CPU time 4.43 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 218764 kb
Host smart-5e953f5f-11e1-4b4e-82fc-086171f5b2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952242495 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3952242495
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.796815402
Short name T985
Test name
Test status
Simulation time 874883245216 ps
CPU time 1603.51 seconds
Started Jul 03 05:29:38 PM PDT 24
Finished Jul 03 05:56:22 PM PDT 24
Peak memory 225268 kb
Host smart-21f5ff86-3ab8-4c6e-bd09-dd0ed781502a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796815402 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.796815402
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1598570120
Short name T349
Test name
Test status
Simulation time 29087362 ps
CPU time 1.32 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 219360 kb
Host smart-6a1ff4d2-c7a6-4e4f-9d78-b1c964aa8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598570120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1598570120
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2745166690
Short name T689
Test name
Test status
Simulation time 34387070 ps
CPU time 0.89 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 219528 kb
Host smart-60367595-5745-4f0c-b8f4-a48aa3b84d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745166690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2745166690
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3854402090
Short name T771
Test name
Test status
Simulation time 56800033 ps
CPU time 1.1 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 217532 kb
Host smart-cc8d81c9-dd7a-4a85-8f4a-45aa9af70b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854402090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3854402090
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.4270392407
Short name T198
Test name
Test status
Simulation time 95460979 ps
CPU time 1.15 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:46 PM PDT 24
Peak memory 220280 kb
Host smart-974098c0-5e80-437c-9978-2d6a43cd85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270392407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.4270392407
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2142775249
Short name T54
Test name
Test status
Simulation time 32210572 ps
CPU time 0.94 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 224056 kb
Host smart-62a350c9-cedd-4a7d-bb71-9dab30a4331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142775249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2142775249
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2988930552
Short name T980
Test name
Test status
Simulation time 54014154 ps
CPU time 1.42 seconds
Started Jul 03 05:30:53 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 218952 kb
Host smart-9b0808ed-3bc0-4bdf-9914-4e91c075e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988930552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2988930552
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1757769033
Short name T184
Test name
Test status
Simulation time 25488350 ps
CPU time 1.19 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:51 PM PDT 24
Peak memory 221072 kb
Host smart-694e1736-164e-462f-9230-39cc38115a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757769033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1757769033
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3132417730
Short name T138
Test name
Test status
Simulation time 33896769 ps
CPU time 1.07 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 229968 kb
Host smart-cd083d27-5096-4ae8-9138-203f2abe4eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132417730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3132417730
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.384863824
Short name T486
Test name
Test status
Simulation time 81394042 ps
CPU time 1.16 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 217812 kb
Host smart-ed4b3894-2a49-4a23-9d1f-9bccd6ec1d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384863824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.384863824
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2232075566
Short name T430
Test name
Test status
Simulation time 34827835 ps
CPU time 1.19 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 219044 kb
Host smart-bc52f2c2-4e3a-4f07-bdde-48805aa48971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232075566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2232075566
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3061083250
Short name T166
Test name
Test status
Simulation time 18492993 ps
CPU time 1.09 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 218828 kb
Host smart-0d25114a-7d23-4700-b2ca-1d9b65c83989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061083250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3061083250
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1020880569
Short name T395
Test name
Test status
Simulation time 86748637 ps
CPU time 1.27 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 219212 kb
Host smart-a3da75ed-ecd2-4602-8679-1e546817c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020880569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1020880569
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.926153579
Short name T860
Test name
Test status
Simulation time 61982130 ps
CPU time 1.2 seconds
Started Jul 03 05:30:50 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 218960 kb
Host smart-3162cff1-b89c-4edf-95f2-95f9617f2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926153579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.926153579
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3673706526
Short name T742
Test name
Test status
Simulation time 42025852 ps
CPU time 1.25 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 225828 kb
Host smart-1ed71523-d082-45a2-8bdf-875a646785e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673706526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3673706526
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3741802403
Short name T92
Test name
Test status
Simulation time 67552828 ps
CPU time 1.31 seconds
Started Jul 03 05:30:44 PM PDT 24
Finished Jul 03 05:30:45 PM PDT 24
Peak memory 220188 kb
Host smart-7549c7d0-c804-4104-a195-85a9387642cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741802403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3741802403
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1752548366
Short name T342
Test name
Test status
Simulation time 39817973 ps
CPU time 1.17 seconds
Started Jul 03 05:30:47 PM PDT 24
Finished Jul 03 05:30:49 PM PDT 24
Peak memory 219128 kb
Host smart-45d94010-e445-40bd-a4b5-f50f3b29868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752548366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1752548366
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1418784351
Short name T201
Test name
Test status
Simulation time 24169803 ps
CPU time 1.11 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 229776 kb
Host smart-220a7e27-87e8-453e-8054-a062f04b4940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418784351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1418784351
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1349159182
Short name T846
Test name
Test status
Simulation time 34657761 ps
CPU time 1.43 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 218904 kb
Host smart-4e1c2130-e809-4188-b8e7-c28239f3b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349159182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1349159182
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.4060699174
Short name T290
Test name
Test status
Simulation time 75719333 ps
CPU time 1.16 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 220088 kb
Host smart-69a54341-e986-4a79-be65-2f854f543545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060699174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.4060699174
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1855163286
Short name T121
Test name
Test status
Simulation time 27821421 ps
CPU time 1.4 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 230080 kb
Host smart-19a8badc-36cf-4a01-b356-dbd2b3e74da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855163286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1855163286
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1194512230
Short name T929
Test name
Test status
Simulation time 46169970 ps
CPU time 1.17 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 218664 kb
Host smart-6ed548ec-141d-4849-8284-97b3bd8d4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194512230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1194512230
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2570163963
Short name T350
Test name
Test status
Simulation time 40249040 ps
CPU time 1.2 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 220584 kb
Host smart-930a8416-220d-4ca5-a0cf-23577a98cfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570163963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2570163963
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3007892388
Short name T217
Test name
Test status
Simulation time 38448251 ps
CPU time 0.95 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 224148 kb
Host smart-c6c3c8cd-4039-425a-8742-624c8659d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007892388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3007892388
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.268319769
Short name T562
Test name
Test status
Simulation time 127784766 ps
CPU time 1.1 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 217744 kb
Host smart-0e28c7b9-c6dd-425d-89b4-447f023d05df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268319769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.268319769
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.606850959
Short name T566
Test name
Test status
Simulation time 23855619 ps
CPU time 1.13 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 219868 kb
Host smart-3f06307e-53a6-473d-aad1-ebbeb141f50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606850959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.606850959
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3282889805
Short name T194
Test name
Test status
Simulation time 29612031 ps
CPU time 0.96 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 218664 kb
Host smart-e2c6545d-5ca3-48af-8702-6dbb3093a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282889805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3282889805
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1188828843
Short name T241
Test name
Test status
Simulation time 79522610 ps
CPU time 1.36 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 218940 kb
Host smart-a9c31193-6554-470d-88d8-e8bdb3b3a8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188828843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1188828843
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1423753691
Short name T807
Test name
Test status
Simulation time 28490821 ps
CPU time 1.15 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 220060 kb
Host smart-5915077f-7731-405a-b87f-67f5cdde07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423753691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1423753691
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3021184687
Short name T865
Test name
Test status
Simulation time 18019682 ps
CPU time 1.13 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 219064 kb
Host smart-783a45a1-d254-446f-bfc3-b92adfa95ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021184687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3021184687
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.116998343
Short name T875
Test name
Test status
Simulation time 63348971 ps
CPU time 2.06 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 217948 kb
Host smart-5dfe793c-3aea-4dd0-8795-ddac96420d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116998343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.116998343
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.631507972
Short name T310
Test name
Test status
Simulation time 67050624 ps
CPU time 1.24 seconds
Started Jul 03 05:29:49 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 221136 kb
Host smart-9f2ef2b9-5682-480d-946c-98fb900c0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631507972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.631507972
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3431995369
Short name T519
Test name
Test status
Simulation time 22990309 ps
CPU time 0.86 seconds
Started Jul 03 05:29:51 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 207000 kb
Host smart-f9e3bfa5-fc4b-498f-8c8c-2547e3dc9cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431995369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3431995369
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2131492820
Short name T542
Test name
Test status
Simulation time 11705806 ps
CPU time 0.95 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 216732 kb
Host smart-8982bfb2-9e10-4fc4-807b-2855c1f7ee8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131492820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2131492820
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4117731648
Short name T729
Test name
Test status
Simulation time 60005903 ps
CPU time 1.25 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 217260 kb
Host smart-41694408-31bb-42af-8a78-fe260d2feb03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117731648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4117731648
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1494666916
Short name T172
Test name
Test status
Simulation time 24782440 ps
CPU time 0.95 seconds
Started Jul 03 05:29:47 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 218644 kb
Host smart-de28506a-e8a8-45fe-995c-0f970e069c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494666916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1494666916
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.590438843
Short name T819
Test name
Test status
Simulation time 67279299 ps
CPU time 1.51 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 218888 kb
Host smart-0ff653e2-f9bf-4894-972f-cea268c975db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590438843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.590438843
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3356872612
Short name T452
Test name
Test status
Simulation time 32783075 ps
CPU time 0.97 seconds
Started Jul 03 05:29:45 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 224288 kb
Host smart-e1193cb1-b310-4ba0-baca-8afcc5db776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356872612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3356872612
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3603966623
Short name T945
Test name
Test status
Simulation time 24190842 ps
CPU time 0.92 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 207440 kb
Host smart-3d29046e-62ee-4297-adb8-71a5d5927f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603966623 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3603966623
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4047601393
Short name T701
Test name
Test status
Simulation time 65674124 ps
CPU time 0.91 seconds
Started Jul 03 05:29:39 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 215568 kb
Host smart-ec0666d7-8268-4e03-94b6-f8b5dd598912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047601393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4047601393
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3603879634
Short name T923
Test name
Test status
Simulation time 130099768 ps
CPU time 3.02 seconds
Started Jul 03 05:29:42 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 215596 kb
Host smart-2aabbc59-8045-49da-8294-97d444806474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603879634 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3603879634
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4208297612
Short name T603
Test name
Test status
Simulation time 18719157457 ps
CPU time 438.03 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:37:05 PM PDT 24
Peak memory 223980 kb
Host smart-eb93788a-5086-4072-b885-4425759eb583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208297612 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.4208297612
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.4256520277
Short name T299
Test name
Test status
Simulation time 95088055 ps
CPU time 1.24 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 219348 kb
Host smart-2effc924-a9f3-4e5c-b591-5e22bbdfa917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256520277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.4256520277
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.718418600
Short name T8
Test name
Test status
Simulation time 45523093 ps
CPU time 0.95 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 218836 kb
Host smart-6ee6eb3b-5ab3-497c-989d-fdd24586df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718418600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.718418600
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_alert.285827128
Short name T633
Test name
Test status
Simulation time 24962596 ps
CPU time 1.2 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 219056 kb
Host smart-d6a9e6a4-ae62-4211-b662-3ea1ef1cba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285827128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.285827128
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2088805369
Short name T798
Test name
Test status
Simulation time 49774985 ps
CPU time 1 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 219060 kb
Host smart-c0e96ee9-9814-4aaa-a3c8-db05b77e62cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088805369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2088805369
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_alert.370846146
Short name T927
Test name
Test status
Simulation time 30888797 ps
CPU time 1.33 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 219068 kb
Host smart-4e566adf-e3f2-4b21-a071-921731e039b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370846146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.370846146
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4128116490
Short name T55
Test name
Test status
Simulation time 20069999 ps
CPU time 1.15 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 224300 kb
Host smart-9a391309-6ed7-4b91-809b-22b6ebe70a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128116490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4128116490
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2370723540
Short name T751
Test name
Test status
Simulation time 41965256 ps
CPU time 1.78 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 218976 kb
Host smart-8d7288cd-3427-4baa-a867-b5f6f97b1a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370723540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2370723540
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.765589607
Short name T759
Test name
Test status
Simulation time 24599609 ps
CPU time 1.14 seconds
Started Jul 03 05:30:51 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 220208 kb
Host smart-7d2c1597-39a5-4d26-8ab9-1fcbae811aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765589607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.765589607
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4020799655
Short name T444
Test name
Test status
Simulation time 21143567 ps
CPU time 1.07 seconds
Started Jul 03 05:30:52 PM PDT 24
Finished Jul 03 05:30:54 PM PDT 24
Peak memory 218940 kb
Host smart-90aadbb5-9a94-405b-b52d-c0b41eadba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020799655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4020799655
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3096664625
Short name T480
Test name
Test status
Simulation time 80378844 ps
CPU time 1.04 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 217672 kb
Host smart-f5a78056-06ab-44da-afff-1e51c1de657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096664625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3096664625
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.4201473125
Short name T583
Test name
Test status
Simulation time 45070911 ps
CPU time 1.13 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 218836 kb
Host smart-4c1d42a0-7017-4c46-9a94-3381d54dc919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201473125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.4201473125
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.635308248
Short name T167
Test name
Test status
Simulation time 32070815 ps
CPU time 0.91 seconds
Started Jul 03 05:31:02 PM PDT 24
Finished Jul 03 05:31:04 PM PDT 24
Peak memory 218440 kb
Host smart-666b5a23-754c-45ec-8057-349c90feb14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635308248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.635308248
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.531078668
Short name T766
Test name
Test status
Simulation time 35717602 ps
CPU time 1.35 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 219048 kb
Host smart-6da65dd4-1649-4946-9e18-1b1b5fb7c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531078668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.531078668
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1700417752
Short name T725
Test name
Test status
Simulation time 51202576 ps
CPU time 1.32 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 216048 kb
Host smart-41e9e554-2b6a-44cd-963d-c3a7f63a6aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700417752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1700417752
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.12232622
Short name T799
Test name
Test status
Simulation time 19368643 ps
CPU time 1.09 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 218908 kb
Host smart-3cdee13f-c018-446d-8ed0-4d50bc7fb73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12232622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.12232622
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2929770712
Short name T324
Test name
Test status
Simulation time 81225210 ps
CPU time 1.2 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 220204 kb
Host smart-4d76e8e6-e5a3-4763-ab9b-9a952af7f42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929770712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2929770712
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.958322621
Short name T140
Test name
Test status
Simulation time 41916798 ps
CPU time 1.08 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 218324 kb
Host smart-cdfd8d2e-3cc7-4bcf-8d48-ab829bb38f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958322621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.958322621
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3119532239
Short name T419
Test name
Test status
Simulation time 45038957 ps
CPU time 1.13 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 220008 kb
Host smart-5ea9cf68-204d-4a4b-b1b2-1d5bbd4c798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119532239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3119532239
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.145268714
Short name T869
Test name
Test status
Simulation time 139415240 ps
CPU time 1.25 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 217588 kb
Host smart-67994e79-e93b-4084-95ed-17f78564f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145268714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.145268714
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3401669850
Short name T78
Test name
Test status
Simulation time 42829024 ps
CPU time 1.19 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 219108 kb
Host smart-5092e9e0-1a0e-4835-9208-0adf39d2a483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401669850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3401669850
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2172181162
Short name T189
Test name
Test status
Simulation time 35937338 ps
CPU time 0.88 seconds
Started Jul 03 05:31:02 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 218644 kb
Host smart-fd769502-228f-4c30-8113-9a3b91b465af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172181162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2172181162
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3592449641
Short name T48
Test name
Test status
Simulation time 69796929 ps
CPU time 1.5 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 219132 kb
Host smart-d349439e-6682-4dec-b15d-7f50148ca239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592449641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3592449641
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3123794167
Short name T165
Test name
Test status
Simulation time 43565683 ps
CPU time 1.13 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 220208 kb
Host smart-9e069247-9b4d-4ed8-95bf-7b4cbd57625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123794167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3123794167
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2962440357
Short name T916
Test name
Test status
Simulation time 86729827 ps
CPU time 1.01 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 224132 kb
Host smart-1174abd2-4f79-4c49-920e-02e65f3d741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962440357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2962440357
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4167118101
Short name T14
Test name
Test status
Simulation time 51125732 ps
CPU time 1.32 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 220252 kb
Host smart-728265bb-2926-492d-b443-84e0071affb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167118101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4167118101
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2037953292
Short name T887
Test name
Test status
Simulation time 100669898 ps
CPU time 1.14 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 218900 kb
Host smart-007bccee-4baf-4be2-bae5-457495de5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037953292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2037953292
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3155638553
Short name T63
Test name
Test status
Simulation time 112312776 ps
CPU time 1.11 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 219936 kb
Host smart-5122ef47-c326-47ca-a779-c1300831506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155638553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3155638553
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1158592807
Short name T709
Test name
Test status
Simulation time 35532376 ps
CPU time 1.47 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 218872 kb
Host smart-c7a0e067-d70d-4388-9c5c-220500b30b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158592807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1158592807
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.197355396
Short name T433
Test name
Test status
Simulation time 26473201 ps
CPU time 1.19 seconds
Started Jul 03 05:29:43 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 219836 kb
Host smart-73db5233-304e-4751-a067-28b9984aeb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197355396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.197355396
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4050612059
Short name T895
Test name
Test status
Simulation time 25159382 ps
CPU time 0.87 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 206988 kb
Host smart-b16eb4b7-1853-4da6-afdc-29b27b353e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050612059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4050612059
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.990113622
Short name T790
Test name
Test status
Simulation time 38170375 ps
CPU time 0.83 seconds
Started Jul 03 05:29:43 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 216680 kb
Host smart-ed85e097-cd9f-47e9-97c3-6fc8d8023791
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990113622 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.990113622
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3140156254
Short name T384
Test name
Test status
Simulation time 106608061 ps
CPU time 1.11 seconds
Started Jul 03 05:29:56 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 220224 kb
Host smart-a895807a-fc98-4c02-a93c-567d879163e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140156254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3140156254
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1434488669
Short name T913
Test name
Test status
Simulation time 21735235 ps
CPU time 1.04 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 218908 kb
Host smart-4c11e6a2-910c-4896-97c6-4d868e600892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434488669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1434488669
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4211566906
Short name T555
Test name
Test status
Simulation time 165789202 ps
CPU time 1.34 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 219048 kb
Host smart-eeeb5d51-d83e-4638-b6e4-e3bcb5522f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211566906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4211566906
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.851600250
Short name T637
Test name
Test status
Simulation time 38834607 ps
CPU time 1.02 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 224376 kb
Host smart-f041fb72-1793-4516-9d4e-194f50a82a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851600250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.851600250
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2079880847
Short name T764
Test name
Test status
Simulation time 35781052 ps
CPU time 0.98 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 207456 kb
Host smart-508f92bf-1d1d-453f-8c93-285a3d180aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079880847 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2079880847
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3920217352
Short name T774
Test name
Test status
Simulation time 29009285 ps
CPU time 0.99 seconds
Started Jul 03 05:29:48 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 215660 kb
Host smart-b5d5dabc-60f8-41e5-8842-a5ff43589e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920217352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3920217352
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2092033617
Short name T589
Test name
Test status
Simulation time 326140391 ps
CPU time 2.87 seconds
Started Jul 03 05:29:42 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 217616 kb
Host smart-1f72ef1d-1f52-4799-b791-c2b111ba125c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092033617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2092033617
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1315660393
Short name T577
Test name
Test status
Simulation time 41175034048 ps
CPU time 1008.56 seconds
Started Jul 03 05:29:46 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 223988 kb
Host smart-ed9de641-0b4e-4bf0-be44-077192a589ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315660393 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1315660393
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3278437509
Short name T136
Test name
Test status
Simulation time 36978074 ps
CPU time 1.19 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 219272 kb
Host smart-57fab465-86d8-49d0-9b92-4c687050b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278437509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3278437509
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3131140668
Short name T416
Test name
Test status
Simulation time 71203954 ps
CPU time 0.96 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 218704 kb
Host smart-4bc380fd-fd6a-4ab1-bbbd-8a0a601b225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131140668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3131140668
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.622707233
Short name T721
Test name
Test status
Simulation time 56281217 ps
CPU time 1.35 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 219048 kb
Host smart-826abbb8-6049-489a-9a12-324ead5dcc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622707233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.622707233
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2817572966
Short name T16
Test name
Test status
Simulation time 21935033 ps
CPU time 1.11 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 220048 kb
Host smart-f03f88a8-5355-44ab-bb73-0a7c99c479ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817572966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2817572966
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2560790168
Short name T122
Test name
Test status
Simulation time 36129435 ps
CPU time 0.95 seconds
Started Jul 03 05:31:09 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 219820 kb
Host smart-d7a6067b-e39f-4bee-87ae-ec61ffdd74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560790168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2560790168
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.438313700
Short name T735
Test name
Test status
Simulation time 56347465 ps
CPU time 1.2 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 218736 kb
Host smart-f3a9ad04-76e1-4f4e-9328-681d1f1c89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438313700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.438313700
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.553856382
Short name T636
Test name
Test status
Simulation time 49151851 ps
CPU time 1.55 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 222612 kb
Host smart-e2dffdff-c403-4ffb-8c0b-2982001faa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553856382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.553856382
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2450471974
Short name T971
Test name
Test status
Simulation time 31682246 ps
CPU time 0.86 seconds
Started Jul 03 05:30:55 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 218412 kb
Host smart-28c2afb6-75a1-4457-8a45-0c8d0fc7425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450471974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2450471974
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2930386686
Short name T585
Test name
Test status
Simulation time 61712486 ps
CPU time 1.39 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 219228 kb
Host smart-9f643cf9-d368-470d-a070-f50bee31cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930386686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2930386686
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1099264171
Short name T719
Test name
Test status
Simulation time 67567244 ps
CPU time 1.04 seconds
Started Jul 03 05:31:15 PM PDT 24
Finished Jul 03 05:31:16 PM PDT 24
Peak memory 219980 kb
Host smart-57d53dd7-366e-42af-b211-92a571a35cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099264171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1099264171
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3062371566
Short name T500
Test name
Test status
Simulation time 38050593 ps
CPU time 1.38 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:31:00 PM PDT 24
Peak memory 220008 kb
Host smart-ef21a3ab-22d9-4606-bc8e-82c351a30dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062371566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3062371566
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1262593376
Short name T614
Test name
Test status
Simulation time 39014478 ps
CPU time 1.59 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 218928 kb
Host smart-204caf0f-6c49-4893-bb27-b2e7bb88535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262593376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1262593376
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2607044999
Short name T76
Test name
Test status
Simulation time 152088061 ps
CPU time 1.23 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:06 PM PDT 24
Peak memory 220764 kb
Host smart-17789beb-92ac-48f5-9895-68381b8474d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607044999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2607044999
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.4050269963
Short name T415
Test name
Test status
Simulation time 105745872 ps
CPU time 1.03 seconds
Started Jul 03 05:31:21 PM PDT 24
Finished Jul 03 05:31:22 PM PDT 24
Peak memory 219872 kb
Host smart-195570be-79b9-4af9-ba93-0847c3357b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050269963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4050269963
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2664123469
Short name T792
Test name
Test status
Simulation time 100288712 ps
CPU time 1.17 seconds
Started Jul 03 05:30:59 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 217548 kb
Host smart-f33a61c5-0f00-4b57-92dd-283eeac3fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664123469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2664123469
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2130106131
Short name T72
Test name
Test status
Simulation time 74779686 ps
CPU time 1.19 seconds
Started Jul 03 05:31:03 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 219420 kb
Host smart-a569915f-da28-4040-909d-34e861c5617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130106131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2130106131
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4152229882
Short name T646
Test name
Test status
Simulation time 40759489 ps
CPU time 1.13 seconds
Started Jul 03 05:31:07 PM PDT 24
Finished Jul 03 05:31:09 PM PDT 24
Peak memory 217856 kb
Host smart-0bcb1bf5-62d4-44fa-8bdf-f17b83abf869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152229882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4152229882
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.49954319
Short name T19
Test name
Test status
Simulation time 255940362 ps
CPU time 1.31 seconds
Started Jul 03 05:30:58 PM PDT 24
Finished Jul 03 05:31:01 PM PDT 24
Peak memory 219176 kb
Host smart-03496015-6b0d-450d-9af4-ed4b51c47e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49954319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.49954319
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1934610398
Short name T228
Test name
Test status
Simulation time 30101762 ps
CPU time 1.26 seconds
Started Jul 03 05:31:17 PM PDT 24
Finished Jul 03 05:31:29 PM PDT 24
Peak memory 216020 kb
Host smart-61406c50-8231-4e78-bed5-7ebcdcd30021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934610398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1934610398
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.684612421
Short name T408
Test name
Test status
Simulation time 38858903 ps
CPU time 0.91 seconds
Started Jul 03 05:30:57 PM PDT 24
Finished Jul 03 05:30:59 PM PDT 24
Peak memory 223496 kb
Host smart-77dfe3e9-2bd8-4a9c-9ce6-7291db320e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684612421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.684612421
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4114092705
Short name T483
Test name
Test status
Simulation time 95635535 ps
CPU time 3.06 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:05 PM PDT 24
Peak memory 219012 kb
Host smart-58cb61de-b66f-462a-b4ba-3ecd27c911b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114092705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4114092705
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2736140061
Short name T874
Test name
Test status
Simulation time 23271060 ps
CPU time 1.16 seconds
Started Jul 03 05:31:06 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 220112 kb
Host smart-ad576b8f-6236-4ad1-9dce-d3fb819e2a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736140061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2736140061
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1005228946
Short name T906
Test name
Test status
Simulation time 19143907 ps
CPU time 1.13 seconds
Started Jul 03 05:31:01 PM PDT 24
Finished Jul 03 05:31:02 PM PDT 24
Peak memory 224300 kb
Host smart-58e0a7b6-1f89-41e5-983f-9b3df0fc4e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005228946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1005228946
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3372158091
Short name T118
Test name
Test status
Simulation time 270412557 ps
CPU time 4 seconds
Started Jul 03 05:31:08 PM PDT 24
Finished Jul 03 05:31:13 PM PDT 24
Peak memory 220604 kb
Host smart-9b4aaad7-23ef-473f-8bf9-265108e813c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372158091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3372158091
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1911731502
Short name T344
Test name
Test status
Simulation time 28228902 ps
CPU time 1.13 seconds
Started Jul 03 05:31:05 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 219020 kb
Host smart-95e3c675-fb1f-4842-a828-8d5adb63d77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911731502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1911731502
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.641812616
Short name T979
Test name
Test status
Simulation time 23352302 ps
CPU time 1.05 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 220172 kb
Host smart-a84a16ad-9748-4af8-b183-885fc132cc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641812616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.641812616
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2380226110
Short name T370
Test name
Test status
Simulation time 51391788 ps
CPU time 1.36 seconds
Started Jul 03 05:31:00 PM PDT 24
Finished Jul 03 05:31:03 PM PDT 24
Peak memory 218372 kb
Host smart-944971ea-4702-4535-8b1a-6b75c4fbe467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380226110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2380226110
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1818077008
Short name T474
Test name
Test status
Simulation time 24888254 ps
CPU time 1.15 seconds
Started Jul 03 05:30:54 PM PDT 24
Finished Jul 03 05:30:55 PM PDT 24
Peak memory 220108 kb
Host smart-d6498786-6dac-4c8d-b8cd-9ecfc7e9d868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818077008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1818077008
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2155402290
Short name T171
Test name
Test status
Simulation time 30053385 ps
CPU time 0.84 seconds
Started Jul 03 05:30:56 PM PDT 24
Finished Jul 03 05:30:57 PM PDT 24
Peak memory 218628 kb
Host smart-3f5a52aa-fac5-4ecb-9efe-8a1c5b7e223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155402290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2155402290
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3514096870
Short name T340
Test name
Test status
Simulation time 142859982 ps
CPU time 3.1 seconds
Started Jul 03 05:31:04 PM PDT 24
Finished Jul 03 05:31:08 PM PDT 24
Peak memory 219712 kb
Host smart-526bac6f-65a8-4c67-81ae-894f18d57807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514096870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3514096870
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%