Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
116045 |
1 |
|
|
T1 |
57 |
|
T2 |
77 |
|
T10 |
17 |
all_pins[1] |
116045 |
1 |
|
|
T1 |
57 |
|
T2 |
77 |
|
T10 |
17 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
221494 |
1 |
|
|
T1 |
114 |
|
T2 |
154 |
|
T10 |
34 |
values[0x1] |
10596 |
1 |
|
|
T23 |
2 |
|
T6 |
58 |
|
T35 |
51 |
transitions[0x0=>0x1] |
9767 |
1 |
|
|
T23 |
1 |
|
T6 |
54 |
|
T35 |
41 |
transitions[0x1=>0x0] |
9784 |
1 |
|
|
T23 |
2 |
|
T6 |
55 |
|
T35 |
41 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
107218 |
1 |
|
|
T1 |
57 |
|
T2 |
77 |
|
T10 |
17 |
all_pins[0] |
values[0x1] |
8827 |
1 |
|
|
T23 |
1 |
|
T6 |
46 |
|
T35 |
40 |
all_pins[0] |
transitions[0x0=>0x1] |
8378 |
1 |
|
|
T23 |
1 |
|
T6 |
44 |
|
T35 |
34 |
all_pins[0] |
transitions[0x1=>0x0] |
1320 |
1 |
|
|
T23 |
1 |
|
T6 |
10 |
|
T35 |
5 |
all_pins[1] |
values[0x0] |
114276 |
1 |
|
|
T1 |
57 |
|
T2 |
77 |
|
T10 |
17 |
all_pins[1] |
values[0x1] |
1769 |
1 |
|
|
T23 |
1 |
|
T6 |
12 |
|
T35 |
11 |
all_pins[1] |
transitions[0x0=>0x1] |
1389 |
1 |
|
|
T6 |
10 |
|
T35 |
7 |
|
T36 |
8 |
all_pins[1] |
transitions[0x1=>0x0] |
8464 |
1 |
|
|
T23 |
1 |
|
T6 |
45 |
|
T35 |
36 |