Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.53 98.25 93.91 97.02 91.28 96.37 99.77 92.08


Total test records in report: 1130
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T1017 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2631890914 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:04 PM PDT 24 26903317 ps
T1018 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4172050487 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:11 PM PDT 24 20864533 ps
T244 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.451903371 Jul 04 05:29:09 PM PDT 24 Jul 04 05:29:11 PM PDT 24 42159506 ps
T1019 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3781278852 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:04 PM PDT 24 178292164 ps
T245 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2139907989 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:08 PM PDT 24 124919258 ps
T1020 /workspace/coverage/cover_reg_top/41.edn_intr_test.753149851 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:23 PM PDT 24 41780397 ps
T1021 /workspace/coverage/cover_reg_top/9.edn_csr_rw.581081536 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:11 PM PDT 24 13644812 ps
T280 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2491615947 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:07 PM PDT 24 61235240 ps
T1022 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.491613706 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 31193186 ps
T1023 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.229895572 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 47530606 ps
T1024 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1156252468 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 49315588 ps
T282 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1314200001 Jul 04 05:29:17 PM PDT 24 Jul 04 05:29:19 PM PDT 24 181246527 ps
T1025 /workspace/coverage/cover_reg_top/12.edn_intr_test.3424703443 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:11 PM PDT 24 25911898 ps
T1026 /workspace/coverage/cover_reg_top/25.edn_intr_test.3916625560 Jul 04 05:29:22 PM PDT 24 Jul 04 05:29:23 PM PDT 24 10997923 ps
T1027 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3339878926 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 14571129 ps
T1028 /workspace/coverage/cover_reg_top/13.edn_intr_test.939519649 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:12 PM PDT 24 44837411 ps
T1029 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1987344071 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:15 PM PDT 24 41013408 ps
T1030 /workspace/coverage/cover_reg_top/40.edn_intr_test.521976906 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:22 PM PDT 24 13925531 ps
T1031 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.80502300 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:09 PM PDT 24 119808996 ps
T1032 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2402318674 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:09 PM PDT 24 27525527 ps
T1033 /workspace/coverage/cover_reg_top/5.edn_intr_test.793360188 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:09 PM PDT 24 12772652 ps
T1034 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1868562395 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:12 PM PDT 24 43875788 ps
T1035 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1127236317 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:15 PM PDT 24 32424022 ps
T1036 /workspace/coverage/cover_reg_top/17.edn_tl_errors.144854497 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:18 PM PDT 24 605383109 ps
T1037 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2245976621 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:10 PM PDT 24 63170329 ps
T1038 /workspace/coverage/cover_reg_top/6.edn_intr_test.4067523419 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:13 PM PDT 24 32474642 ps
T1039 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2110616403 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:01 PM PDT 24 88406714 ps
T1040 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2720806087 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:07 PM PDT 24 39171147 ps
T1041 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4213167392 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 37362778 ps
T1042 /workspace/coverage/cover_reg_top/27.edn_intr_test.619507222 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:25 PM PDT 24 16464351 ps
T1043 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2307028895 Jul 04 05:29:17 PM PDT 24 Jul 04 05:29:19 PM PDT 24 298613278 ps
T1044 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3270812761 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:11 PM PDT 24 351707237 ps
T1045 /workspace/coverage/cover_reg_top/34.edn_intr_test.1115560439 Jul 04 05:29:26 PM PDT 24 Jul 04 05:29:27 PM PDT 24 12155358 ps
T1046 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3188614506 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:15 PM PDT 24 39282643 ps
T1047 /workspace/coverage/cover_reg_top/37.edn_intr_test.846590748 Jul 04 05:29:22 PM PDT 24 Jul 04 05:29:23 PM PDT 24 43633732 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_intr_test.2690039780 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:11 PM PDT 24 17628831 ps
T1049 /workspace/coverage/cover_reg_top/10.edn_intr_test.3336292125 Jul 04 05:29:09 PM PDT 24 Jul 04 05:29:10 PM PDT 24 11799090 ps
T1050 /workspace/coverage/cover_reg_top/31.edn_intr_test.2977004576 Jul 04 05:29:24 PM PDT 24 Jul 04 05:29:25 PM PDT 24 34664595 ps
T1051 /workspace/coverage/cover_reg_top/14.edn_csr_rw.495513008 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 56432271 ps
T1052 /workspace/coverage/cover_reg_top/19.edn_intr_test.131397877 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:15 PM PDT 24 15527624 ps
T283 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2013511476 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:11 PM PDT 24 532480286 ps
T1053 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2334326490 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 25090341 ps
T1054 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.883639865 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:15 PM PDT 24 71753370 ps
T1055 /workspace/coverage/cover_reg_top/20.edn_intr_test.3021840048 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:16 PM PDT 24 71258374 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2267591038 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:09 PM PDT 24 52655561 ps
T1057 /workspace/coverage/cover_reg_top/36.edn_intr_test.3233412298 Jul 04 05:29:22 PM PDT 24 Jul 04 05:29:23 PM PDT 24 50709620 ps
T1058 /workspace/coverage/cover_reg_top/38.edn_intr_test.3473601226 Jul 04 05:29:24 PM PDT 24 Jul 04 05:29:25 PM PDT 24 17723401 ps
T1059 /workspace/coverage/cover_reg_top/35.edn_intr_test.3870298348 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:24 PM PDT 24 39095455 ps
T1060 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2775098558 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:08 PM PDT 24 22981989 ps
T1061 /workspace/coverage/cover_reg_top/39.edn_intr_test.2470427788 Jul 04 05:29:24 PM PDT 24 Jul 04 05:29:25 PM PDT 24 35887587 ps
T1062 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1499037563 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:02 PM PDT 24 405753308 ps
T1063 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1563407251 Jul 04 05:29:09 PM PDT 24 Jul 04 05:29:12 PM PDT 24 210758540 ps
T1064 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4193629223 Jul 04 05:28:58 PM PDT 24 Jul 04 05:28:59 PM PDT 24 71321178 ps
T1065 /workspace/coverage/cover_reg_top/14.edn_intr_test.1133749969 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:16 PM PDT 24 11477653 ps
T1066 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1390462476 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:08 PM PDT 24 150001736 ps
T1067 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3757592813 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:15 PM PDT 24 32788044 ps
T1068 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1754476760 Jul 04 05:29:17 PM PDT 24 Jul 04 05:29:20 PM PDT 24 158896805 ps
T1069 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1589525862 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:14 PM PDT 24 77086521 ps
T246 /workspace/coverage/cover_reg_top/3.edn_csr_rw.850040049 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:09 PM PDT 24 24375826 ps
T1070 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1719355802 Jul 04 05:29:00 PM PDT 24 Jul 04 05:29:01 PM PDT 24 49190619 ps
T1071 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2297930500 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 87446109 ps
T247 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3117028768 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:10 PM PDT 24 17979096 ps
T1072 /workspace/coverage/cover_reg_top/46.edn_intr_test.1047973686 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:23 PM PDT 24 14098411 ps
T1073 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1228805084 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:08 PM PDT 24 277259021 ps
T1074 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1597112140 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:16 PM PDT 24 540076362 ps
T284 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1295702634 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:13 PM PDT 24 95865563 ps
T1075 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2796344189 Jul 04 05:29:09 PM PDT 24 Jul 04 05:29:11 PM PDT 24 134116840 ps
T1076 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.875928503 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:07 PM PDT 24 64049552 ps
T1077 /workspace/coverage/cover_reg_top/33.edn_intr_test.1216968259 Jul 04 05:29:22 PM PDT 24 Jul 04 05:29:23 PM PDT 24 12269818 ps
T1078 /workspace/coverage/cover_reg_top/30.edn_intr_test.3258632252 Jul 04 05:29:26 PM PDT 24 Jul 04 05:29:27 PM PDT 24 32711991 ps
T1079 /workspace/coverage/cover_reg_top/22.edn_intr_test.672059782 Jul 04 05:29:16 PM PDT 24 Jul 04 05:29:17 PM PDT 24 24063434 ps
T248 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1143029559 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:00 PM PDT 24 23379486 ps
T1080 /workspace/coverage/cover_reg_top/15.edn_intr_test.1939391215 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:16 PM PDT 24 38294756 ps
T1081 /workspace/coverage/cover_reg_top/21.edn_intr_test.3857387918 Jul 04 05:29:14 PM PDT 24 Jul 04 05:29:15 PM PDT 24 38304148 ps
T1082 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4084813133 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:17 PM PDT 24 24127037 ps
T1083 /workspace/coverage/cover_reg_top/49.edn_intr_test.3846812575 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:23 PM PDT 24 24314043 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3340559713 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:13 PM PDT 24 14523848 ps
T1085 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2203980812 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:16 PM PDT 24 211377850 ps
T249 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2446094481 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:12 PM PDT 24 12359788 ps
T1086 /workspace/coverage/cover_reg_top/1.edn_intr_test.980464210 Jul 04 05:29:00 PM PDT 24 Jul 04 05:29:01 PM PDT 24 13238784 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3743699848 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:09 PM PDT 24 74713715 ps
T1088 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.952613966 Jul 04 05:29:10 PM PDT 24 Jul 04 05:29:12 PM PDT 24 94030064 ps
T252 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2876034185 Jul 04 05:29:01 PM PDT 24 Jul 04 05:29:08 PM PDT 24 1001024319 ps
T1089 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3634699079 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:15 PM PDT 24 315626662 ps
T1090 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1467119124 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:14 PM PDT 24 26598260 ps
T1091 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1465840506 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:15 PM PDT 24 39623808 ps
T1092 /workspace/coverage/cover_reg_top/43.edn_intr_test.4202062123 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:24 PM PDT 24 60255572 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4018495128 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:08 PM PDT 24 109567580 ps
T1094 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1180085400 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:04 PM PDT 24 178960324 ps
T1095 /workspace/coverage/cover_reg_top/44.edn_intr_test.2176200823 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:22 PM PDT 24 36289373 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3411004056 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:08 PM PDT 24 476300920 ps
T1097 /workspace/coverage/cover_reg_top/0.edn_intr_test.879431076 Jul 04 05:28:58 PM PDT 24 Jul 04 05:28:59 PM PDT 24 26446831 ps
T1098 /workspace/coverage/cover_reg_top/48.edn_intr_test.3108518192 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:22 PM PDT 24 15739433 ps
T1099 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2645995345 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 12380721 ps
T1100 /workspace/coverage/cover_reg_top/26.edn_intr_test.1740272502 Jul 04 05:29:22 PM PDT 24 Jul 04 05:29:23 PM PDT 24 30414991 ps
T1101 /workspace/coverage/cover_reg_top/47.edn_intr_test.3044524047 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:23 PM PDT 24 47303693 ps
T1102 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1187217845 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:15 PM PDT 24 13376701 ps
T1103 /workspace/coverage/cover_reg_top/28.edn_intr_test.106467019 Jul 04 05:29:24 PM PDT 24 Jul 04 05:29:25 PM PDT 24 24712868 ps
T1104 /workspace/coverage/cover_reg_top/42.edn_intr_test.2222522708 Jul 04 05:29:21 PM PDT 24 Jul 04 05:29:23 PM PDT 24 45950494 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3351584869 Jul 04 05:29:02 PM PDT 24 Jul 04 05:29:03 PM PDT 24 12525098 ps
T250 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2733261487 Jul 04 05:29:15 PM PDT 24 Jul 04 05:29:16 PM PDT 24 93056889 ps
T251 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1398655304 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:07 PM PDT 24 14407353 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2402052609 Jul 04 05:29:01 PM PDT 24 Jul 04 05:29:02 PM PDT 24 29248544 ps
T1107 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1915690294 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:14 PM PDT 24 229927695 ps
T281 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2381822735 Jul 04 05:29:17 PM PDT 24 Jul 04 05:29:20 PM PDT 24 198538722 ps
T1108 /workspace/coverage/cover_reg_top/29.edn_intr_test.3383367716 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:24 PM PDT 24 29134914 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.384270560 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:12 PM PDT 24 121079702 ps
T1110 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3191941835 Jul 04 05:28:58 PM PDT 24 Jul 04 05:29:00 PM PDT 24 300317417 ps
T1111 /workspace/coverage/cover_reg_top/10.edn_csr_rw.561857401 Jul 04 05:29:09 PM PDT 24 Jul 04 05:29:10 PM PDT 24 17467378 ps
T1112 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.233640513 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:15 PM PDT 24 116556225 ps
T1113 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.97332167 Jul 04 05:28:59 PM PDT 24 Jul 04 05:29:20 PM PDT 24 1312341264 ps
T1114 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1185919330 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:09 PM PDT 24 104757649 ps
T1115 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.290519144 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:14 PM PDT 24 1276423335 ps
T1116 /workspace/coverage/cover_reg_top/17.edn_intr_test.1922650436 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:15 PM PDT 24 82791816 ps
T1117 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2597257585 Jul 04 05:29:12 PM PDT 24 Jul 04 05:29:14 PM PDT 24 182774303 ps
T253 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1148941200 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:07 PM PDT 24 27117992 ps
T1118 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2493787592 Jul 04 05:29:08 PM PDT 24 Jul 04 05:29:12 PM PDT 24 40976438 ps
T1119 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2571368750 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:07 PM PDT 24 60297951 ps
T1120 /workspace/coverage/cover_reg_top/45.edn_intr_test.4081711694 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:24 PM PDT 24 17291088 ps
T1121 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4143766983 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:12 PM PDT 24 23524992 ps
T1122 /workspace/coverage/cover_reg_top/24.edn_intr_test.3703940459 Jul 04 05:29:23 PM PDT 24 Jul 04 05:29:24 PM PDT 24 90041206 ps
T1123 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3455326842 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:11 PM PDT 24 1302942414 ps
T1124 /workspace/coverage/cover_reg_top/8.edn_tl_errors.311750996 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:15 PM PDT 24 96913878 ps
T254 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3779677476 Jul 04 05:29:06 PM PDT 24 Jul 04 05:29:07 PM PDT 24 20886855 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2922394875 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:08 PM PDT 24 16658728 ps
T1126 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2607434461 Jul 04 05:29:11 PM PDT 24 Jul 04 05:29:13 PM PDT 24 28007465 ps
T1127 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3856343543 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:08 PM PDT 24 27524988 ps
T1128 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4014421545 Jul 04 05:29:07 PM PDT 24 Jul 04 05:29:10 PM PDT 24 822885277 ps
T1129 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.525790907 Jul 04 05:29:13 PM PDT 24 Jul 04 05:29:15 PM PDT 24 47507921 ps
T1130 /workspace/coverage/cover_reg_top/11.edn_intr_test.2125707334 Jul 04 05:29:05 PM PDT 24 Jul 04 05:29:06 PM PDT 24 16525261 ps

Test location /workspace/coverage/default/288.edn_genbits.3035024711
Short name T10
Test name
Test status
Simulation time 31432569 ps
CPU time 1.35 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 220232 kb
Host smart-815ddf7a-80c0-4f15-a7c5-667d8f532032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035024711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3035024711
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.426856724
Short name T38
Test name
Test status
Simulation time 148720336 ps
CPU time 1.65 seconds
Started Jul 04 06:27:09 PM PDT 24
Finished Jul 04 06:27:10 PM PDT 24
Peak memory 219260 kb
Host smart-e2d4cc43-da09-4c44-bd0a-87347e854e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426856724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.426856724
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4021220119
Short name T6
Test name
Test status
Simulation time 131894003808 ps
CPU time 621.12 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:36:01 PM PDT 24
Peak memory 222324 kb
Host smart-cf13d29a-3539-4331-98a1-dfd7ee13d883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021220119 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4021220119
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_sec_cm.614599322
Short name T16
Test name
Test status
Simulation time 1045579527 ps
CPU time 7.94 seconds
Started Jul 04 06:24:30 PM PDT 24
Finished Jul 04 06:24:38 PM PDT 24
Peak memory 236676 kb
Host smart-e40464c7-c5ea-421b-a1cc-c0a70197f37e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614599322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.614599322
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/58.edn_alert.3991430403
Short name T3
Test name
Test status
Simulation time 87000180 ps
CPU time 1.16 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 219140 kb
Host smart-2813a6aa-037d-4e4b-acd4-00f5e696b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991430403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3991430403
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/3.edn_err.1428835970
Short name T49
Test name
Test status
Simulation time 22634871 ps
CPU time 1.12 seconds
Started Jul 04 06:24:51 PM PDT 24
Finished Jul 04 06:24:52 PM PDT 24
Peak memory 224304 kb
Host smart-2d5ae19d-33f4-4d5e-8417-dbf39dd9870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428835970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1428835970
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/34.edn_disable.3078772354
Short name T167
Test name
Test status
Simulation time 11581803 ps
CPU time 0.85 seconds
Started Jul 04 06:25:32 PM PDT 24
Finished Jul 04 06:25:33 PM PDT 24
Peak memory 216480 kb
Host smart-75d347ec-c9a8-44f1-b94a-e20841760015
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078772354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3078772354
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/169.edn_alert.410436325
Short name T44
Test name
Test status
Simulation time 60134135 ps
CPU time 1.18 seconds
Started Jul 04 06:26:40 PM PDT 24
Finished Jul 04 06:26:42 PM PDT 24
Peak memory 221728 kb
Host smart-4c5bb2cf-4cc8-4f94-a7c9-568c3220d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410436325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.410436325
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.512969951
Short name T65
Test name
Test status
Simulation time 146680098013 ps
CPU time 1345.76 seconds
Started Jul 04 06:25:53 PM PDT 24
Finished Jul 04 06:48:20 PM PDT 24
Peak memory 226404 kb
Host smart-16310f5e-0dc2-4a08-a2fb-c9a3ae0f79a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512969951 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.512969951
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.edn_alert.3654296038
Short name T109
Test name
Test status
Simulation time 41032835 ps
CPU time 1.28 seconds
Started Jul 04 06:26:17 PM PDT 24
Finished Jul 04 06:26:24 PM PDT 24
Peak memory 218800 kb
Host smart-cc01c1d5-79cb-4702-bdd8-082dcde51f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654296038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3654296038
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3423928491
Short name T108
Test name
Test status
Simulation time 92018013 ps
CPU time 1.07 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 217332 kb
Host smart-a520758a-7735-45fd-a9d2-fcdc8fd1e8a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423928491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3423928491
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_regwen.167483845
Short name T24
Test name
Test status
Simulation time 58358567 ps
CPU time 0.89 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 207392 kb
Host smart-01d068d3-6e71-4913-a101-de6c7e0094eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167483845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.167483845
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2440344859
Short name T270
Test name
Test status
Simulation time 67782609 ps
CPU time 1.74 seconds
Started Jul 04 05:29:03 PM PDT 24
Finished Jul 04 05:29:05 PM PDT 24
Peak memory 207080 kb
Host smart-e410bae1-96ef-407d-92a0-01614cbe76e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440344859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2440344859
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3097406932
Short name T113
Test name
Test status
Simulation time 66396379 ps
CPU time 1.18 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 217084 kb
Host smart-3a08dd7a-c44d-47db-8ad1-9d9e5789c2f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097406932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3097406932
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_disable.1438960694
Short name T176
Test name
Test status
Simulation time 40497521 ps
CPU time 0.85 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:42 PM PDT 24
Peak memory 216540 kb
Host smart-5316d707-2d9a-4503-af8b-4dbe7af4a7a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438960694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1438960694
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/9.edn_alert.3698068084
Short name T263
Test name
Test status
Simulation time 67461682 ps
CPU time 1.12 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 219740 kb
Host smart-89ebce40-1e1a-4fed-96d6-7a7e47b1bea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698068084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3698068084
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.1964119503
Short name T161
Test name
Test status
Simulation time 41891334 ps
CPU time 0.83 seconds
Started Jul 04 06:24:34 PM PDT 24
Finished Jul 04 06:24:35 PM PDT 24
Peak memory 216552 kb
Host smart-f168baf0-1fcf-410b-b680-ad3096982af9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964119503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1964119503
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3759362340
Short name T140
Test name
Test status
Simulation time 41190375 ps
CPU time 1.37 seconds
Started Jul 04 06:25:26 PM PDT 24
Finished Jul 04 06:25:27 PM PDT 24
Peak memory 217300 kb
Host smart-17d3bdf9-7d85-41b2-8afc-169d0b6ecf2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759362340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3759362340
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_disable.1109284335
Short name T194
Test name
Test status
Simulation time 16725256 ps
CPU time 0.89 seconds
Started Jul 04 06:25:29 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 216664 kb
Host smart-8feaf8d5-7e95-4be5-9803-da238f4552e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109284335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1109284335
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3628741879
Short name T239
Test name
Test status
Simulation time 21260701 ps
CPU time 0.89 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206896 kb
Host smart-de1e314c-f2e8-483d-9390-d3ecbb25b2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628741879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3628741879
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/default/188.edn_genbits.3697575358
Short name T289
Test name
Test status
Simulation time 52997776 ps
CPU time 1.23 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 220328 kb
Host smart-4aef99ad-ef71-49f3-a660-9696dcc3995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697575358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3697575358
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.427875567
Short name T169
Test name
Test status
Simulation time 68751764 ps
CPU time 1.21 seconds
Started Jul 04 06:26:30 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 220988 kb
Host smart-d861f80b-9731-482e-bea9-07606436569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427875567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.427875567
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.1423928865
Short name T60
Test name
Test status
Simulation time 54791204 ps
CPU time 1.18 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 220000 kb
Host smart-c61e4e92-1e37-4351-90d0-c5d0a93e0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423928865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1423928865
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/179.edn_alert.2663484863
Short name T146
Test name
Test status
Simulation time 113769885 ps
CPU time 1.31 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219360 kb
Host smart-4147fb11-0af8-4107-b050-c686fa9c293d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663484863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2663484863
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.1236211815
Short name T286
Test name
Test status
Simulation time 44629419 ps
CPU time 1.02 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 219980 kb
Host smart-24f02c14-67dd-4c4e-a188-68368c806fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236211815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1236211815
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/85.edn_alert.3725589458
Short name T103
Test name
Test status
Simulation time 200191959 ps
CPU time 1.16 seconds
Started Jul 04 06:26:13 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 219116 kb
Host smart-86cf7111-0677-412c-869e-6e0a9a9b65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725589458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3725589458
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3006588203
Short name T13
Test name
Test status
Simulation time 104723537 ps
CPU time 1.32 seconds
Started Jul 04 06:26:41 PM PDT 24
Finished Jul 04 06:26:42 PM PDT 24
Peak memory 220304 kb
Host smart-1f61cfd1-8872-455c-ba15-ae1dbbca5e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006588203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3006588203
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1713499717
Short name T100
Test name
Test status
Simulation time 44542203 ps
CPU time 1.15 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218688 kb
Host smart-24d15ab0-1a05-475c-93b8-71924446173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713499717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1713499717
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/197.edn_alert.4082609715
Short name T62
Test name
Test status
Simulation time 85934765 ps
CPU time 1.18 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219084 kb
Host smart-a7f3a115-4f20-4574-a24c-062e2d0b58d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082609715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4082609715
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.3430007327
Short name T807
Test name
Test status
Simulation time 49174180 ps
CPU time 1.22 seconds
Started Jul 04 06:27:05 PM PDT 24
Finished Jul 04 06:27:07 PM PDT 24
Peak memory 216036 kb
Host smart-9465e0b9-5207-4ae0-9924-1c521771d8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430007327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3430007327
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/15.edn_intr.677704379
Short name T91
Test name
Test status
Simulation time 21751089 ps
CPU time 1 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 216084 kb
Host smart-33c99cab-bc45-464d-8e6b-9867537f13c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677704379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.677704379
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/24.edn_genbits.2447598951
Short name T295
Test name
Test status
Simulation time 89665299 ps
CPU time 1.11 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 217760 kb
Host smart-f1bbd551-c879-43b4-b5ce-d7ba0756b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447598951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2447598951
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_alert.2669675795
Short name T12
Test name
Test status
Simulation time 97839547 ps
CPU time 1.14 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 218896 kb
Host smart-0deb0d30-c116-4101-a3bb-84900745fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669675795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2669675795
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable.399112057
Short name T79
Test name
Test status
Simulation time 13406621 ps
CPU time 0.93 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 215920 kb
Host smart-8f1fac5b-050d-40c4-813c-088df08af26f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399112057 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.399112057
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.2670106335
Short name T776
Test name
Test status
Simulation time 36849557 ps
CPU time 0.84 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 216084 kb
Host smart-e4c970a3-6a1c-4ff7-bb0d-e4c236a126fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670106335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2670106335
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.1430737423
Short name T126
Test name
Test status
Simulation time 44692299 ps
CPU time 1.16 seconds
Started Jul 04 06:24:33 PM PDT 24
Finished Jul 04 06:24:35 PM PDT 24
Peak memory 218812 kb
Host smart-83561827-5a7b-4fe4-855c-2d05908dca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430737423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1430737423
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3433759249
Short name T119
Test name
Test status
Simulation time 95312804 ps
CPU time 1.07 seconds
Started Jul 04 06:24:34 PM PDT 24
Finished Jul 04 06:24:35 PM PDT 24
Peak memory 217332 kb
Host smart-fdec3b9f-8b61-404e-8008-aa7e836a5373
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433759249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3433759249
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3055838497
Short name T863
Test name
Test status
Simulation time 47419339 ps
CPU time 1.15 seconds
Started Jul 04 06:24:43 PM PDT 24
Finished Jul 04 06:24:45 PM PDT 24
Peak memory 217128 kb
Host smart-677acda0-1778-41ea-8e7a-ee7de3b5540c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055838497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3055838497
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/107.edn_alert.1220011858
Short name T769
Test name
Test status
Simulation time 219217957 ps
CPU time 1.12 seconds
Started Jul 04 06:26:41 PM PDT 24
Finished Jul 04 06:26:42 PM PDT 24
Peak memory 219972 kb
Host smart-96cef7ae-120b-41b2-a728-2bb96bff4add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220011858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1220011858
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.927653666
Short name T736
Test name
Test status
Simulation time 19023669 ps
CPU time 1.16 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 224276 kb
Host smart-2d50f36d-153f-41b1-ba90-9d14102f0403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927653666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.927653666
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/113.edn_alert.1079458008
Short name T915
Test name
Test status
Simulation time 32936210 ps
CPU time 1.16 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 221292 kb
Host smart-71fab62f-be9f-4c19-8352-e7efe6503f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079458008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1079458008
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3179010319
Short name T812
Test name
Test status
Simulation time 62298221 ps
CPU time 1.12 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 220084 kb
Host smart-21fb14b9-4e80-42ee-a189-bc6d9624dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179010319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3179010319
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.171686039
Short name T112
Test name
Test status
Simulation time 42072794 ps
CPU time 1.42 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 217112 kb
Host smart-dd2ebf92-1188-4209-b8d9-c4c0e2b6417e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171686039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.171686039
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.980387002
Short name T193
Test name
Test status
Simulation time 129019667 ps
CPU time 0.93 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 216576 kb
Host smart-94008560-454e-4c07-988e-5fe66536ea16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980387002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.980387002
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.3558683406
Short name T185
Test name
Test status
Simulation time 20673729 ps
CPU time 1.12 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 219780 kb
Host smart-8525ee04-b237-444d-aa4d-bada3c297613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558683406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3558683406
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.312257188
Short name T114
Test name
Test status
Simulation time 47473320 ps
CPU time 1.18 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 217308 kb
Host smart-f2782b1d-ff1f-43a5-974d-38125623dcaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312257188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.312257188
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_disable.3074993239
Short name T87
Test name
Test status
Simulation time 14232521 ps
CPU time 0.98 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 216760 kb
Host smart-33bc61db-3b02-469d-9aa0-47e63c743a5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074993239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3074993239
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/66.edn_err.2652354852
Short name T172
Test name
Test status
Simulation time 18641212 ps
CPU time 1.07 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 218788 kb
Host smart-e6cb4874-c73b-4c12-a563-9dcae22fa7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652354852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2652354852
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/116.edn_genbits.1022793473
Short name T310
Test name
Test status
Simulation time 50178653 ps
CPU time 1.19 seconds
Started Jul 04 06:26:33 PM PDT 24
Finished Jul 04 06:26:34 PM PDT 24
Peak memory 219932 kb
Host smart-26aa5ad6-dcfa-4ed6-a5ae-4fb6c1cc2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022793473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1022793473
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3901837875
Short name T317
Test name
Test status
Simulation time 81712064 ps
CPU time 1.82 seconds
Started Jul 04 06:26:38 PM PDT 24
Finished Jul 04 06:26:40 PM PDT 24
Peak memory 220620 kb
Host smart-820d46b6-b3e6-476f-924c-3c3681f3bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901837875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3901837875
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert_test.961891697
Short name T334
Test name
Test status
Simulation time 54727288 ps
CPU time 0.87 seconds
Started Jul 04 06:24:34 PM PDT 24
Finished Jul 04 06:24:35 PM PDT 24
Peak memory 207028 kb
Host smart-2bd01d7f-03b9-46c2-b2a7-98b7b1d5cebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961891697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.961891697
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3117028768
Short name T247
Test name
Test status
Simulation time 17979096 ps
CPU time 1.28 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 206956 kb
Host smart-1d9eaf3c-b81e-48c1-8430-b515bc413b05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117028768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3117028768
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/default/44.edn_genbits.2134836446
Short name T276
Test name
Test status
Simulation time 139429366 ps
CPU time 2.14 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 220424 kb
Host smart-69403aaf-7eec-4a5e-940d-0a57b420f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134836446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2134836446
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2831360403
Short name T785
Test name
Test status
Simulation time 22042628 ps
CPU time 1 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 216128 kb
Host smart-d4ad2179-8b02-4f1d-b17a-92e9eed0fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831360403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2831360403
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/107.edn_genbits.2898928173
Short name T303
Test name
Test status
Simulation time 123655353 ps
CPU time 1.62 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 219320 kb
Host smart-98a1fcbf-db22-45fa-abee-75b7193587df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898928173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2898928173
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2866565280
Short name T278
Test name
Test status
Simulation time 53677528 ps
CPU time 1.63 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 218928 kb
Host smart-6416a336-f292-403b-b2ab-ff41c81ccbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866565280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2866565280
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1575316806
Short name T862
Test name
Test status
Simulation time 65588482 ps
CPU time 1.19 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 219184 kb
Host smart-4a43348d-71b7-431c-8dad-239c146adfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575316806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1575316806
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1429574426
Short name T372
Test name
Test status
Simulation time 26492883 ps
CPU time 1.17 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 220096 kb
Host smart-ade503d4-0407-40d2-b434-430e38d080fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429574426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1429574426
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3770985036
Short name T315
Test name
Test status
Simulation time 43236678 ps
CPU time 1.65 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 218976 kb
Host smart-087cc07a-8074-4172-a12a-c5f3e95185f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770985036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3770985036
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all.1049466283
Short name T532
Test name
Test status
Simulation time 2016454595 ps
CPU time 3.3 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 215596 kb
Host smart-6dd57724-0792-4c67-9934-0eaba08ded6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049466283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1049466283
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/124.edn_genbits.1582858069
Short name T297
Test name
Test status
Simulation time 56300528 ps
CPU time 1.36 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 218968 kb
Host smart-f4398da2-3027-4969-8173-554243f82801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582858069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1582858069
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.4008734836
Short name T293
Test name
Test status
Simulation time 37264452 ps
CPU time 1.39 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218772 kb
Host smart-ff228b1b-4204-4a79-b1a6-229969a2f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008734836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4008734836
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3701448721
Short name T941
Test name
Test status
Simulation time 110028480 ps
CPU time 1.22 seconds
Started Jul 04 06:26:38 PM PDT 24
Finished Jul 04 06:26:40 PM PDT 24
Peak memory 218784 kb
Host smart-468ba145-710c-4844-9303-7741677dab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701448721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3701448721
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_genbits.3313704044
Short name T309
Test name
Test status
Simulation time 32481310 ps
CPU time 1.31 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 219056 kb
Host smart-699b1318-95fb-47f1-a209-115a28577ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313704044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3313704044
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2423829814
Short name T277
Test name
Test status
Simulation time 41466188 ps
CPU time 1.31 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 219940 kb
Host smart-f946446b-a101-43e1-ae7e-178bf38653ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423829814 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2423829814
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_intr.4025265012
Short name T92
Test name
Test status
Simulation time 24231958 ps
CPU time 0.9 seconds
Started Jul 04 06:25:28 PM PDT 24
Finished Jul 04 06:25:29 PM PDT 24
Peak memory 216080 kb
Host smart-e551167b-c324-4971-bb41-6e8d589fc624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025265012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4025265012
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/105.edn_alert.880691562
Short name T991
Test name
Test status
Simulation time 298797358 ps
CPU time 1.2 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 215956 kb
Host smart-217b7a36-9755-439e-88d4-d7106c05c441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880691562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.880691562
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.1906147861
Short name T209
Test name
Test status
Simulation time 25746961 ps
CPU time 1.11 seconds
Started Jul 04 06:26:24 PM PDT 24
Finished Jul 04 06:26:26 PM PDT 24
Peak memory 220208 kb
Host smart-35147a48-4b77-4f27-bd3b-394edf916dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906147861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1906147861
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/1.edn_err.1761921414
Short name T102
Test name
Test status
Simulation time 28727631 ps
CPU time 1.23 seconds
Started Jul 04 06:24:32 PM PDT 24
Finished Jul 04 06:24:34 PM PDT 24
Peak memory 217692 kb
Host smart-6b20f1a7-c6de-4c76-ba6a-846ab49d5dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761921414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1761921414
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/228.edn_genbits.2555214890
Short name T588
Test name
Test status
Simulation time 35043913 ps
CPU time 1.46 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 220356 kb
Host smart-ae369306-4869-4f4d-a8c2-298509f3a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555214890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2555214890
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2143374881
Short name T1011
Test name
Test status
Simulation time 47648254 ps
CPU time 1.03 seconds
Started Jul 04 05:28:58 PM PDT 24
Finished Jul 04 05:28:59 PM PDT 24
Peak memory 206992 kb
Host smart-07184788-860a-4e14-a9aa-670046eda35b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143374881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2143374881
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3805304630
Short name T242
Test name
Test status
Simulation time 175914319 ps
CPU time 5.3 seconds
Started Jul 04 05:29:01 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206908 kb
Host smart-86df3397-edda-4a5e-8b7d-ac2ead69a2b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805304630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3805304630
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1156252468
Short name T1024
Test name
Test status
Simulation time 49315588 ps
CPU time 0.9 seconds
Started Jul 04 05:29:02 PM PDT 24
Finished Jul 04 05:29:03 PM PDT 24
Peak memory 206876 kb
Host smart-8e77363a-a378-4044-af78-5c5f8327ec6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156252468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1156252468
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.139540472
Short name T1008
Test name
Test status
Simulation time 15516596 ps
CPU time 1.04 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:00 PM PDT 24
Peak memory 215200 kb
Host smart-654e1d6f-e239-4ddc-b68a-6983957b726e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139540472 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.139540472
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2645995345
Short name T1099
Test name
Test status
Simulation time 12380721 ps
CPU time 0.85 seconds
Started Jul 04 05:29:02 PM PDT 24
Finished Jul 04 05:29:03 PM PDT 24
Peak memory 206892 kb
Host smart-2c52426e-34f3-4b60-9203-ec98519a87dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645995345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2645995345
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.879431076
Short name T1097
Test name
Test status
Simulation time 26446831 ps
CPU time 0.82 seconds
Started Jul 04 05:28:58 PM PDT 24
Finished Jul 04 05:28:59 PM PDT 24
Peak memory 206828 kb
Host smart-0dd2f4e8-2af4-43ef-bad6-205a1c7fcd6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879431076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.879431076
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4193629223
Short name T1064
Test name
Test status
Simulation time 71321178 ps
CPU time 1.19 seconds
Started Jul 04 05:28:58 PM PDT 24
Finished Jul 04 05:28:59 PM PDT 24
Peak memory 206900 kb
Host smart-9fdc556a-92ae-477e-8efe-957230e92ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193629223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4193629223
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3781278852
Short name T1019
Test name
Test status
Simulation time 178292164 ps
CPU time 4.76 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:04 PM PDT 24
Peak memory 215252 kb
Host smart-620c6c02-bd77-4ce1-8107-a4a2f5a8f9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781278852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3781278852
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1180085400
Short name T1094
Test name
Test status
Simulation time 178960324 ps
CPU time 1.85 seconds
Started Jul 04 05:29:02 PM PDT 24
Finished Jul 04 05:29:04 PM PDT 24
Peak memory 215112 kb
Host smart-11a5ece4-54ef-4d8f-9d71-12e834a8dd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180085400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1180085400
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2110616403
Short name T1039
Test name
Test status
Simulation time 88406714 ps
CPU time 1.79 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:01 PM PDT 24
Peak memory 206864 kb
Host smart-cfba88d5-7173-4ce3-90ec-977758a8301d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110616403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2110616403
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2876034185
Short name T252
Test name
Test status
Simulation time 1001024319 ps
CPU time 6.85 seconds
Started Jul 04 05:29:01 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206916 kb
Host smart-4c6b3e47-5471-4ddc-be48-bfcabd973b2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876034185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2876034185
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1143029559
Short name T248
Test name
Test status
Simulation time 23379486 ps
CPU time 0.86 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:00 PM PDT 24
Peak memory 206860 kb
Host smart-f7c59aec-d835-4342-b33f-1f00a1aedca7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143029559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1143029559
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1719355802
Short name T1070
Test name
Test status
Simulation time 49190619 ps
CPU time 1.13 seconds
Started Jul 04 05:29:00 PM PDT 24
Finished Jul 04 05:29:01 PM PDT 24
Peak memory 217916 kb
Host smart-12750791-86e0-4ff4-be8d-36b4c84e3d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719355802 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1719355802
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2402052609
Short name T1106
Test name
Test status
Simulation time 29248544 ps
CPU time 0.96 seconds
Started Jul 04 05:29:01 PM PDT 24
Finished Jul 04 05:29:02 PM PDT 24
Peak memory 206892 kb
Host smart-e99f7a72-3394-4dfc-abfd-e5b7bd41d74f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402052609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2402052609
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.980464210
Short name T1086
Test name
Test status
Simulation time 13238784 ps
CPU time 0.88 seconds
Started Jul 04 05:29:00 PM PDT 24
Finished Jul 04 05:29:01 PM PDT 24
Peak memory 206856 kb
Host smart-78d06c40-92d2-4d1c-9531-36533c286b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980464210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.980464210
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2297930500
Short name T1071
Test name
Test status
Simulation time 87446109 ps
CPU time 1.18 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:00 PM PDT 24
Peak memory 206884 kb
Host smart-e4c708d9-ba4a-4ee4-b27d-d6d50b28e1b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297930500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2297930500
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2093698870
Short name T1010
Test name
Test status
Simulation time 32450620 ps
CPU time 2.27 seconds
Started Jul 04 05:28:58 PM PDT 24
Finished Jul 04 05:29:01 PM PDT 24
Peak memory 215120 kb
Host smart-40fe81e2-7bb2-4ab7-8905-521db78533d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093698870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2093698870
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.97332167
Short name T1113
Test name
Test status
Simulation time 1312341264 ps
CPU time 20.49 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:20 PM PDT 24
Peak memory 215104 kb
Host smart-f69c8924-fddd-433f-8025-0f0c301b8641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97332167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.97332167
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2597257585
Short name T1117
Test name
Test status
Simulation time 182774303 ps
CPU time 2.08 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 215156 kb
Host smart-832eae38-ce5c-42bc-8301-089513f607df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597257585 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2597257585
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.561857401
Short name T1111
Test name
Test status
Simulation time 17467378 ps
CPU time 0.97 seconds
Started Jul 04 05:29:09 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 206868 kb
Host smart-3d48ee97-9e0a-4c8a-b0ac-7f33e4f70e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561857401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.561857401
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3336292125
Short name T1049
Test name
Test status
Simulation time 11799090 ps
CPU time 0.83 seconds
Started Jul 04 05:29:09 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 206792 kb
Host smart-62c5460c-3fc8-4aab-991b-79ef14138684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336292125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3336292125
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4143766983
Short name T1121
Test name
Test status
Simulation time 23524992 ps
CPU time 1.14 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206900 kb
Host smart-f0411323-8533-4ae0-9660-b20afcf4eeec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143766983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4143766983
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2111261600
Short name T1000
Test name
Test status
Simulation time 91529491 ps
CPU time 3.48 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 215236 kb
Host smart-25602564-bc0c-46d7-9412-0bb861ff47ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111261600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2111261600
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1390462476
Short name T1066
Test name
Test status
Simulation time 150001736 ps
CPU time 1.87 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206912 kb
Host smart-684f90fc-a4eb-4ac6-8e41-b126be84c1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390462476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1390462476
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.645998129
Short name T1009
Test name
Test status
Simulation time 106765291 ps
CPU time 1.08 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 215544 kb
Host smart-2c08eef3-0289-428b-8448-87da22a85b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645998129 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.645998129
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.995563867
Short name T256
Test name
Test status
Simulation time 21766608 ps
CPU time 0.86 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206884 kb
Host smart-c622dcb2-6736-43d6-b7d6-2cfbfc816bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995563867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.995563867
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2125707334
Short name T1130
Test name
Test status
Simulation time 16525261 ps
CPU time 0.92 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:06 PM PDT 24
Peak memory 206820 kb
Host smart-636ba7d9-695d-4675-8fe3-144aaafe8766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125707334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2125707334
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2607434461
Short name T1126
Test name
Test status
Simulation time 28007465 ps
CPU time 1.19 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206900 kb
Host smart-410b2a77-615e-48c7-8301-4575a11f8439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607434461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2607434461
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1563407251
Short name T1063
Test name
Test status
Simulation time 210758540 ps
CPU time 2.44 seconds
Started Jul 04 05:29:09 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 215164 kb
Host smart-87597f87-e793-4182-9965-af865d4c5e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563407251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1563407251
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4014421545
Short name T1128
Test name
Test status
Simulation time 822885277 ps
CPU time 1.67 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 206920 kb
Host smart-a6a6cfca-06b7-45f1-96d6-8b8162a0cc50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014421545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4014421545
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1915690294
Short name T1107
Test name
Test status
Simulation time 229927695 ps
CPU time 1.53 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 218840 kb
Host smart-b482f303-8ef3-465f-a2d9-cb6cd19ca6be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915690294 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1915690294
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2646301851
Short name T238
Test name
Test status
Simulation time 19818598 ps
CPU time 0.79 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:06 PM PDT 24
Peak memory 206716 kb
Host smart-7e8fa9c1-6863-4c29-984a-c5217b23afcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646301851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2646301851
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3424703443
Short name T1025
Test name
Test status
Simulation time 25911898 ps
CPU time 0.87 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206820 kb
Host smart-adc08360-27d6-449b-9c7e-f727822128fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424703443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3424703443
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.80502300
Short name T1031
Test name
Test status
Simulation time 119808996 ps
CPU time 1.2 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206864 kb
Host smart-75d16e19-e498-4d2f-841c-3f613e1a8bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80502300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_out
standing.80502300
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1589525862
Short name T1069
Test name
Test status
Simulation time 77086521 ps
CPU time 2.78 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 219344 kb
Host smart-bfb758b5-e277-4ccf-8227-c1e09a41dc57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589525862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1589525862
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2298464052
Short name T271
Test name
Test status
Simulation time 178694031 ps
CPU time 2.5 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 207004 kb
Host smart-151fad1c-5747-4fd2-ac62-0384724748fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298464052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2298464052
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2521162892
Short name T1013
Test name
Test status
Simulation time 80204339 ps
CPU time 1.15 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 217240 kb
Host smart-7a2a1d1b-2c23-43d9-a10c-9059fe4b92c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521162892 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2521162892
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.662242418
Short name T1012
Test name
Test status
Simulation time 37245867 ps
CPU time 0.87 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206592 kb
Host smart-1dfca631-bba3-4ac8-8572-85f1c3659488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662242418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.662242418
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.939519649
Short name T1028
Test name
Test status
Simulation time 44837411 ps
CPU time 0.87 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206852 kb
Host smart-7a9b175b-debf-4792-a6b4-5730eaa4b698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939519649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.939519649
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4172050487
Short name T1018
Test name
Test status
Simulation time 20864533 ps
CPU time 0.94 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206956 kb
Host smart-9294ae5f-2405-4714-af7e-198faba9502a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172050487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4172050487
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4123783379
Short name T996
Test name
Test status
Simulation time 90835853 ps
CPU time 1.93 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 219164 kb
Host smart-668eff68-9cb5-4add-a4cb-750f631b4744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123783379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4123783379
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1295702634
Short name T284
Test name
Test status
Simulation time 95865563 ps
CPU time 2.74 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206640 kb
Host smart-1170716c-262a-4d00-b4d9-da5fdfdda2cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295702634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1295702634
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2334326490
Short name T1053
Test name
Test status
Simulation time 25090341 ps
CPU time 1.52 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 215120 kb
Host smart-fc8030db-a322-4682-a028-717a98241e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334326490 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2334326490
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.495513008
Short name T1051
Test name
Test status
Simulation time 56432271 ps
CPU time 0.81 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 206712 kb
Host smart-cc563c97-a560-4844-b0e1-983ebf43bc0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495513008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.495513008
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1133749969
Short name T1065
Test name
Test status
Simulation time 11477653 ps
CPU time 0.86 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206832 kb
Host smart-71754dbb-8cdf-4353-a68e-6366ab95b092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133749969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1133749969
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.528837754
Short name T259
Test name
Test status
Simulation time 41390263 ps
CPU time 1.15 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206848 kb
Host smart-01509dbe-e449-4f9e-b510-e1313ba6016c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528837754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.528837754
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1597112140
Short name T1074
Test name
Test status
Simulation time 540076362 ps
CPU time 4.33 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 215180 kb
Host smart-1e211d3f-1daf-454e-b538-59bb56392559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597112140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1597112140
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2796344189
Short name T1075
Test name
Test status
Simulation time 134116840 ps
CPU time 2.11 seconds
Started Jul 04 05:29:09 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206996 kb
Host smart-cf982b3e-dd65-403e-b7ab-2c7166126cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796344189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2796344189
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1127236317
Short name T1035
Test name
Test status
Simulation time 32424022 ps
CPU time 2.16 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215216 kb
Host smart-c5ef0848-f320-4463-83a5-91b85820addf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127236317 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1127236317
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1187217845
Short name T1102
Test name
Test status
Simulation time 13376701 ps
CPU time 0.83 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206860 kb
Host smart-fcca6960-3b5b-4b8d-aca2-c2c76d99f4dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187217845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1187217845
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1939391215
Short name T1080
Test name
Test status
Simulation time 38294756 ps
CPU time 0.85 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206672 kb
Host smart-ee0a5a16-69e8-4fe2-932b-5fc88b11fd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939391215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1939391215
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3757592813
Short name T1067
Test name
Test status
Simulation time 32788044 ps
CPU time 1.05 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206892 kb
Host smart-1470ecd2-1703-4ffc-826b-68d40d98ae7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757592813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3757592813
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2307028895
Short name T1043
Test name
Test status
Simulation time 298613278 ps
CPU time 2.49 seconds
Started Jul 04 05:29:17 PM PDT 24
Finished Jul 04 05:29:19 PM PDT 24
Peak memory 215284 kb
Host smart-aa802a82-4319-485c-b2b5-a415e7efc602
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307028895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2307028895
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2203980812
Short name T1085
Test name
Test status
Simulation time 211377850 ps
CPU time 2.75 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206852 kb
Host smart-1edfe522-ec8a-43d1-ad26-c2329878aea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203980812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2203980812
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.883639865
Short name T1054
Test name
Test status
Simulation time 71753370 ps
CPU time 1.47 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215240 kb
Host smart-c670266e-853e-4963-81ef-963da3d3c783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883639865 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.883639865
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2285421940
Short name T1016
Test name
Test status
Simulation time 16012959 ps
CPU time 0.87 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206776 kb
Host smart-ef95d757-6712-4d9e-aad1-ca66800c8e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285421940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2285421940
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1987344071
Short name T1029
Test name
Test status
Simulation time 41013408 ps
CPU time 1.11 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206800 kb
Host smart-2bfb5db1-1ee9-41b5-a48a-8d26a9127fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987344071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1987344071
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1465840506
Short name T1091
Test name
Test status
Simulation time 39623808 ps
CPU time 2.59 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215188 kb
Host smart-587eadc8-bfd2-4f3d-bca3-b5a530112f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465840506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1465840506
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2381822735
Short name T281
Test name
Test status
Simulation time 198538722 ps
CPU time 2.63 seconds
Started Jul 04 05:29:17 PM PDT 24
Finished Jul 04 05:29:20 PM PDT 24
Peak memory 206884 kb
Host smart-269d1990-77d9-4647-b8a0-1e4cac1ace50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381822735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2381822735
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.229895572
Short name T1023
Test name
Test status
Simulation time 47530606 ps
CPU time 1.29 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 215156 kb
Host smart-c06f83f3-392f-49db-b7d1-0ec0999fc8da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229895572 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.229895572
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3188614506
Short name T1046
Test name
Test status
Simulation time 39282643 ps
CPU time 0.87 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206652 kb
Host smart-1876b498-fd81-4cd7-84d1-abc1173dc049
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188614506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3188614506
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1922650436
Short name T1116
Test name
Test status
Simulation time 82791816 ps
CPU time 0.8 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206672 kb
Host smart-59723e2f-62d1-4200-826b-861d5a7a771b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922650436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1922650436
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4198548007
Short name T255
Test name
Test status
Simulation time 39827533 ps
CPU time 1.09 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206968 kb
Host smart-47e8ecf9-2a2b-4f3e-93d3-28fcd381a53a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198548007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4198548007
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.144854497
Short name T1036
Test name
Test status
Simulation time 605383109 ps
CPU time 2.67 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:18 PM PDT 24
Peak memory 215152 kb
Host smart-c519e977-cbf8-46a6-be80-72f200eac6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144854497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.144854497
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3634699079
Short name T1089
Test name
Test status
Simulation time 315626662 ps
CPU time 2.18 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215104 kb
Host smart-c2189ffc-6219-43c7-8f3f-29673531a366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634699079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3634699079
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.491613706
Short name T1022
Test name
Test status
Simulation time 31193186 ps
CPU time 1.06 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 216792 kb
Host smart-b3c6f2de-65bf-406a-82f0-a49d3d8cf83f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491613706 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.491613706
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2733261487
Short name T250
Test name
Test status
Simulation time 93056889 ps
CPU time 0.78 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206720 kb
Host smart-a1da4402-8c69-4773-9155-09c495d005d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733261487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2733261487
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2064465661
Short name T997
Test name
Test status
Simulation time 18496708 ps
CPU time 0.87 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 206844 kb
Host smart-0f5ad93e-b152-46f9-a482-4827afc1986d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064465661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2064465661
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4084813133
Short name T1082
Test name
Test status
Simulation time 24127037 ps
CPU time 0.96 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 206888 kb
Host smart-8121f279-ebb6-4cbe-bf29-0fc4381de383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084813133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4084813133
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1754476760
Short name T1068
Test name
Test status
Simulation time 158896805 ps
CPU time 2.29 seconds
Started Jul 04 05:29:17 PM PDT 24
Finished Jul 04 05:29:20 PM PDT 24
Peak memory 215212 kb
Host smart-d0b7e23f-b4e1-4253-bcdf-dc3616bed2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754476760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1754476760
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1314200001
Short name T282
Test name
Test status
Simulation time 181246527 ps
CPU time 2.39 seconds
Started Jul 04 05:29:17 PM PDT 24
Finished Jul 04 05:29:19 PM PDT 24
Peak memory 207204 kb
Host smart-6c5828fb-1a5a-4ef4-aaad-72007a63d71d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314200001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1314200001
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4213167392
Short name T1041
Test name
Test status
Simulation time 37362778 ps
CPU time 1.59 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 217668 kb
Host smart-5b56fb61-084d-42a4-920c-fe3fc4e82bf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213167392 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4213167392
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3339878926
Short name T1027
Test name
Test status
Simulation time 14571129 ps
CPU time 0.83 seconds
Started Jul 04 05:29:15 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 206720 kb
Host smart-c9505fa2-9b8e-4f87-9a82-9d5b9b8e509b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339878926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3339878926
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.131397877
Short name T1052
Test name
Test status
Simulation time 15527624 ps
CPU time 0.85 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206788 kb
Host smart-97cd1e45-6557-48de-8b60-dc0a5169e87a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131397877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.131397877
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4227539891
Short name T257
Test name
Test status
Simulation time 140986622 ps
CPU time 1.07 seconds
Started Jul 04 05:29:16 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 206964 kb
Host smart-1ee034ab-b691-4569-bde5-6691015ca526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227539891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4227539891
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.171788988
Short name T1001
Test name
Test status
Simulation time 175675619 ps
CPU time 3.14 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 219288 kb
Host smart-a99c4da8-2023-45d3-9acc-b6982334d71f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171788988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.171788988
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1973263674
Short name T272
Test name
Test status
Simulation time 59968887 ps
CPU time 1.76 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 215044 kb
Host smart-5f57382d-3201-458a-b13e-5333c0cb8b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973263674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1973263674
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2631890914
Short name T1017
Test name
Test status
Simulation time 26903317 ps
CPU time 1.07 seconds
Started Jul 04 05:29:02 PM PDT 24
Finished Jul 04 05:29:04 PM PDT 24
Peak memory 206996 kb
Host smart-6100c794-ff98-4575-896c-a199a3fc57fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631890914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2631890914
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1499037563
Short name T1062
Test name
Test status
Simulation time 405753308 ps
CPU time 3.19 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:02 PM PDT 24
Peak memory 206900 kb
Host smart-2d8e92e4-0081-44ef-b58b-3052111f11f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499037563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1499037563
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3351584869
Short name T1105
Test name
Test status
Simulation time 12525098 ps
CPU time 0.9 seconds
Started Jul 04 05:29:02 PM PDT 24
Finished Jul 04 05:29:03 PM PDT 24
Peak memory 206872 kb
Host smart-ccaee90c-f919-4225-b3d8-4350e738334e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351584869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3351584869
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1109881133
Short name T1003
Test name
Test status
Simulation time 14672843 ps
CPU time 1 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206952 kb
Host smart-5a601ad2-d074-4d35-8494-b6e20f9323ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109881133 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1109881133
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2081132722
Short name T258
Test name
Test status
Simulation time 13665501 ps
CPU time 0.89 seconds
Started Jul 04 05:29:00 PM PDT 24
Finished Jul 04 05:29:01 PM PDT 24
Peak memory 206888 kb
Host smart-7f561fc2-ce9f-49fd-a6f9-3fb950d6baab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081132722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2081132722
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2246987866
Short name T1014
Test name
Test status
Simulation time 65004963 ps
CPU time 0.81 seconds
Started Jul 04 05:28:59 PM PDT 24
Finished Jul 04 05:29:00 PM PDT 24
Peak memory 206592 kb
Host smart-4bb0f4a2-77c7-4619-81ed-9ebed10f3fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246987866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2246987866
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.952613966
Short name T1088
Test name
Test status
Simulation time 94030064 ps
CPU time 1.51 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206896 kb
Host smart-8043ec59-f99c-4c9a-978e-2540ff689c86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952613966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.952613966
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3191941835
Short name T1110
Test name
Test status
Simulation time 300317417 ps
CPU time 1.81 seconds
Started Jul 04 05:28:58 PM PDT 24
Finished Jul 04 05:29:00 PM PDT 24
Peak memory 223324 kb
Host smart-243ddac6-88ed-4460-8b67-1caa1c5bfea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191941835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3191941835
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3021840048
Short name T1055
Test name
Test status
Simulation time 71258374 ps
CPU time 0.83 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206864 kb
Host smart-69919789-c5db-4bc4-8ca6-571651ac239e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021840048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3021840048
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3857387918
Short name T1081
Test name
Test status
Simulation time 38304148 ps
CPU time 0.83 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206668 kb
Host smart-e4bd1150-2750-4e49-812a-4757f444abc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857387918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3857387918
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.672059782
Short name T1079
Test name
Test status
Simulation time 24063434 ps
CPU time 0.91 seconds
Started Jul 04 05:29:16 PM PDT 24
Finished Jul 04 05:29:17 PM PDT 24
Peak memory 206828 kb
Host smart-730953db-7e72-49fb-b1ee-44791f9d11b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672059782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.672059782
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3102762297
Short name T1015
Test name
Test status
Simulation time 78293689 ps
CPU time 0.83 seconds
Started Jul 04 05:29:26 PM PDT 24
Finished Jul 04 05:29:27 PM PDT 24
Peak memory 206680 kb
Host smart-8a73a471-0228-4b77-ba41-fd318ae3958c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102762297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3102762297
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3703940459
Short name T1122
Test name
Test status
Simulation time 90041206 ps
CPU time 0.86 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:24 PM PDT 24
Peak memory 206812 kb
Host smart-0bdebbbf-f4b1-4973-b494-bb83d58ca837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703940459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3703940459
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3916625560
Short name T1026
Test name
Test status
Simulation time 10997923 ps
CPU time 0.87 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206836 kb
Host smart-0ec6ecf1-8fd5-4819-84ce-df9eac42176c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916625560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3916625560
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1740272502
Short name T1100
Test name
Test status
Simulation time 30414991 ps
CPU time 0.79 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206616 kb
Host smart-302c6ce2-9dd2-4a85-b107-f78c787f04ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740272502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1740272502
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.619507222
Short name T1042
Test name
Test status
Simulation time 16464351 ps
CPU time 0.94 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:25 PM PDT 24
Peak memory 206836 kb
Host smart-d760ea59-74f9-4ae1-b2cd-5da6e7e06bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619507222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.619507222
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.106467019
Short name T1103
Test name
Test status
Simulation time 24712868 ps
CPU time 0.89 seconds
Started Jul 04 05:29:24 PM PDT 24
Finished Jul 04 05:29:25 PM PDT 24
Peak memory 206852 kb
Host smart-e7dd930b-3991-447e-879d-4ba882eaf61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106467019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.106467019
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3383367716
Short name T1108
Test name
Test status
Simulation time 29134914 ps
CPU time 0.77 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:24 PM PDT 24
Peak memory 206604 kb
Host smart-ba80affe-e220-4a9a-8800-6efaa1290f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383367716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3383367716
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.384270560
Short name T1109
Test name
Test status
Simulation time 121079702 ps
CPU time 3.41 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206864 kb
Host smart-633dbcd5-364c-4bb5-93c7-a29552ac9b9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384270560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.384270560
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3779677476
Short name T254
Test name
Test status
Simulation time 20886855 ps
CPU time 0.99 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 207052 kb
Host smart-311dc8c8-5706-4469-85d4-8604fa14cac0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779677476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3779677476
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1396088651
Short name T999
Test name
Test status
Simulation time 19140017 ps
CPU time 1.07 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 206852 kb
Host smart-cf5eb52e-98a4-45ac-9ec4-f767f4950f94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396088651 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1396088651
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.850040049
Short name T246
Test name
Test status
Simulation time 24375826 ps
CPU time 0.88 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206908 kb
Host smart-976b373e-45f3-4cd5-ae30-bed57542d729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850040049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.850040049
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4211207703
Short name T1004
Test name
Test status
Simulation time 28535891 ps
CPU time 0.84 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206672 kb
Host smart-9794d848-e28e-474b-8ca7-a415a898a604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211207703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4211207703
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1185919330
Short name T1114
Test name
Test status
Simulation time 104757649 ps
CPU time 1.4 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206972 kb
Host smart-9a0e9eee-2b1d-4d2f-8770-8c23c3ab9a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185919330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1185919330
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1868562395
Short name T1034
Test name
Test status
Simulation time 43875788 ps
CPU time 2.99 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 218996 kb
Host smart-1d01c8cf-9d56-4d6e-9ca6-8434909813f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868562395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1868562395
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3411004056
Short name T1096
Test name
Test status
Simulation time 476300920 ps
CPU time 2.61 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206976 kb
Host smart-370a5767-240f-4126-a14a-12c9eec6251b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411004056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3411004056
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3258632252
Short name T1078
Test name
Test status
Simulation time 32711991 ps
CPU time 0.8 seconds
Started Jul 04 05:29:26 PM PDT 24
Finished Jul 04 05:29:27 PM PDT 24
Peak memory 206632 kb
Host smart-fa55a805-bc25-4534-8d11-889001336494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258632252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3258632252
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2977004576
Short name T1050
Test name
Test status
Simulation time 34664595 ps
CPU time 0.78 seconds
Started Jul 04 05:29:24 PM PDT 24
Finished Jul 04 05:29:25 PM PDT 24
Peak memory 206644 kb
Host smart-ef36b8f7-7e61-4fc6-8ec3-efc4e036659a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977004576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2977004576
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4127168035
Short name T998
Test name
Test status
Simulation time 14966149 ps
CPU time 0.91 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206756 kb
Host smart-89c2405e-0f44-4c5f-925e-fca811bdb77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127168035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4127168035
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1216968259
Short name T1077
Test name
Test status
Simulation time 12269818 ps
CPU time 0.87 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206776 kb
Host smart-4457901c-4d32-4ba6-ac23-8f5caf4bf087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216968259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1216968259
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1115560439
Short name T1045
Test name
Test status
Simulation time 12155358 ps
CPU time 0.81 seconds
Started Jul 04 05:29:26 PM PDT 24
Finished Jul 04 05:29:27 PM PDT 24
Peak memory 206856 kb
Host smart-5b8c9ea6-4387-415c-b48f-bdcbf8175174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115560439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1115560439
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3870298348
Short name T1059
Test name
Test status
Simulation time 39095455 ps
CPU time 0.86 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:24 PM PDT 24
Peak memory 206636 kb
Host smart-e756f23e-426d-4465-900b-c80076ab4a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870298348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3870298348
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3233412298
Short name T1057
Test name
Test status
Simulation time 50709620 ps
CPU time 0.85 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206828 kb
Host smart-beb245af-3ce6-4f76-a9e5-c5b67b894b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233412298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3233412298
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.846590748
Short name T1047
Test name
Test status
Simulation time 43633732 ps
CPU time 0.83 seconds
Started Jul 04 05:29:22 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206844 kb
Host smart-92c93e9b-3323-476d-955b-1426d571030a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846590748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.846590748
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3473601226
Short name T1058
Test name
Test status
Simulation time 17723401 ps
CPU time 0.86 seconds
Started Jul 04 05:29:24 PM PDT 24
Finished Jul 04 05:29:25 PM PDT 24
Peak memory 206852 kb
Host smart-8c9b46f7-40da-4364-aec8-6ca8fe11cf07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473601226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3473601226
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2470427788
Short name T1061
Test name
Test status
Simulation time 35887587 ps
CPU time 0.89 seconds
Started Jul 04 05:29:24 PM PDT 24
Finished Jul 04 05:29:25 PM PDT 24
Peak memory 206844 kb
Host smart-6435757b-bf03-48c8-99e8-5e3c1e8371bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470427788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2470427788
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.451903371
Short name T244
Test name
Test status
Simulation time 42159506 ps
CPU time 1.56 seconds
Started Jul 04 05:29:09 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206908 kb
Host smart-104b2373-2c72-432b-9725-02b3cfecbe17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451903371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.451903371
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3455326842
Short name T1123
Test name
Test status
Simulation time 1302942414 ps
CPU time 5.26 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206952 kb
Host smart-bb3acdbf-4801-4a03-915e-eb962b08b35b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455326842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3455326842
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.875928503
Short name T1076
Test name
Test status
Simulation time 64049552 ps
CPU time 0.94 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206900 kb
Host smart-7bd3c73e-139c-4b1d-b6d2-910e544950ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875928503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.875928503
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2775098558
Short name T1060
Test name
Test status
Simulation time 22981989 ps
CPU time 1.17 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 217012 kb
Host smart-fe8fda31-67c1-4529-a480-6632e1d79fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775098558 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2775098558
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2139907989
Short name T245
Test name
Test status
Simulation time 124919258 ps
CPU time 0.94 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206892 kb
Host smart-871d2ef5-3c3c-46d0-a866-1a1d298cd24c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139907989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2139907989
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1638292218
Short name T1002
Test name
Test status
Simulation time 11215654 ps
CPU time 0.88 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206820 kb
Host smart-34a50b4f-3cd7-49cd-a451-8082aa306fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638292218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1638292218
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2402318674
Short name T1032
Test name
Test status
Simulation time 27525527 ps
CPU time 1.04 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206968 kb
Host smart-cf3454c5-04cd-4c65-8e4d-9dfda6ac0f0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402318674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2402318674
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.564354171
Short name T1007
Test name
Test status
Simulation time 954866462 ps
CPU time 2.33 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215228 kb
Host smart-4e2409e5-7824-4a06-acb4-b769ff02744e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564354171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.564354171
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2013511476
Short name T283
Test name
Test status
Simulation time 532480286 ps
CPU time 2.44 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 215524 kb
Host smart-bcce2e89-5b79-4dd3-8bfe-557754f7d820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013511476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2013511476
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.521976906
Short name T1030
Test name
Test status
Simulation time 13925531 ps
CPU time 0.96 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:22 PM PDT 24
Peak memory 206784 kb
Host smart-e73140f0-e003-4bce-b9a5-2b6f6830b9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521976906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.521976906
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.753149851
Short name T1020
Test name
Test status
Simulation time 41780397 ps
CPU time 0.82 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206672 kb
Host smart-d5269440-916a-4b68-9de3-736d21321b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753149851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.753149851
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2222522708
Short name T1104
Test name
Test status
Simulation time 45950494 ps
CPU time 0.87 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206844 kb
Host smart-ad7ba28a-2ce2-42ef-8074-f1be427cf75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222522708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2222522708
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4202062123
Short name T1092
Test name
Test status
Simulation time 60255572 ps
CPU time 0.79 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:24 PM PDT 24
Peak memory 206600 kb
Host smart-6b9c9817-1ee0-4bbd-b011-5ad13c4b4169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202062123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4202062123
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2176200823
Short name T1095
Test name
Test status
Simulation time 36289373 ps
CPU time 0.86 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:22 PM PDT 24
Peak memory 206840 kb
Host smart-9e0276f3-e755-4f0f-b251-4178190eb7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176200823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2176200823
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4081711694
Short name T1120
Test name
Test status
Simulation time 17291088 ps
CPU time 0.84 seconds
Started Jul 04 05:29:23 PM PDT 24
Finished Jul 04 05:29:24 PM PDT 24
Peak memory 206860 kb
Host smart-25ca2e63-1d54-4c85-81b9-0f4f98c70746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081711694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4081711694
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1047973686
Short name T1072
Test name
Test status
Simulation time 14098411 ps
CPU time 0.84 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206800 kb
Host smart-15a1b99c-e5a0-4bb2-bf04-95459a207c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047973686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1047973686
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3044524047
Short name T1101
Test name
Test status
Simulation time 47303693 ps
CPU time 0.84 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206856 kb
Host smart-a7e882a9-ccb3-4c1a-80b4-ae2d8566d606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044524047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3044524047
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3108518192
Short name T1098
Test name
Test status
Simulation time 15739433 ps
CPU time 0.93 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:22 PM PDT 24
Peak memory 206840 kb
Host smart-86418d7c-c2e9-47f0-8426-e1a046febfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108518192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3108518192
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3846812575
Short name T1083
Test name
Test status
Simulation time 24314043 ps
CPU time 0.86 seconds
Started Jul 04 05:29:21 PM PDT 24
Finished Jul 04 05:29:23 PM PDT 24
Peak memory 206820 kb
Host smart-b74d1a43-9f0c-4c6c-8a61-11181f8de100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846812575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3846812575
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1228805084
Short name T1073
Test name
Test status
Simulation time 277259021 ps
CPU time 2.08 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 215268 kb
Host smart-9201e96b-5134-4f53-a5f2-46d04c853072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228805084 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1228805084
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2446094481
Short name T249
Test name
Test status
Simulation time 12359788 ps
CPU time 0.88 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 206644 kb
Host smart-5e4ef399-4bb4-408c-a408-7a135ff743d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446094481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2446094481
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.793360188
Short name T1033
Test name
Test status
Simulation time 12772652 ps
CPU time 0.86 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206856 kb
Host smart-c1e5e5ec-b2f8-4533-8992-4b0e9f601563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793360188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.793360188
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4018495128
Short name T1093
Test name
Test status
Simulation time 109567580 ps
CPU time 0.99 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206932 kb
Host smart-dd77ef2b-c537-4416-8a6c-a42589abe165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018495128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4018495128
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2493787592
Short name T1118
Test name
Test status
Simulation time 40976438 ps
CPU time 2.89 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 223320 kb
Host smart-65b6778f-8590-4175-abbd-f8ff3079f960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493787592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2493787592
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2571368750
Short name T1119
Test name
Test status
Simulation time 60297951 ps
CPU time 1.84 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 215120 kb
Host smart-d62673d0-4799-4202-b6df-badfdb8ec44c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571368750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2571368750
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3743699848
Short name T1087
Test name
Test status
Simulation time 74713715 ps
CPU time 1.46 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 215280 kb
Host smart-6987f2b5-c284-47f8-bea0-c6036f3077c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743699848 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3743699848
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1148941200
Short name T253
Test name
Test status
Simulation time 27117992 ps
CPU time 0.8 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206752 kb
Host smart-e71f631a-25f5-4748-b4cc-8e5ee7590a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148941200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1148941200
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4067523419
Short name T1038
Test name
Test status
Simulation time 32474642 ps
CPU time 0.88 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206840 kb
Host smart-85f805cb-48f7-4f21-8a85-14c4f0ab306a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067523419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4067523419
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2922394875
Short name T1125
Test name
Test status
Simulation time 16658728 ps
CPU time 1.13 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206880 kb
Host smart-88228412-4aaf-46cc-ad42-933a906161b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922394875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2922394875
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3270812761
Short name T1044
Test name
Test status
Simulation time 351707237 ps
CPU time 4.26 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 215252 kb
Host smart-f038ab64-48c9-4f7a-aae3-33580f8a7894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270812761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3270812761
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.233640513
Short name T1112
Test name
Test status
Simulation time 116556225 ps
CPU time 2.72 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206892 kb
Host smart-b190ba3f-1376-4ce4-b86b-97326766db2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233640513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.233640513
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3340559713
Short name T1084
Test name
Test status
Simulation time 14523848 ps
CPU time 1 seconds
Started Jul 04 05:29:12 PM PDT 24
Finished Jul 04 05:29:13 PM PDT 24
Peak memory 206960 kb
Host smart-61224859-8d20-43ab-8864-00fa64de9e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340559713 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3340559713
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1398655304
Short name T251
Test name
Test status
Simulation time 14407353 ps
CPU time 0.98 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 206816 kb
Host smart-1909d4f1-9fbf-4a40-a85c-d35fd5943692
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398655304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1398655304
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4215081548
Short name T1005
Test name
Test status
Simulation time 35621440 ps
CPU time 0.8 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206624 kb
Host smart-e72c8712-f42a-4f68-b777-3b5604028fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215081548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4215081548
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1467119124
Short name T1090
Test name
Test status
Simulation time 26598260 ps
CPU time 0.98 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 206944 kb
Host smart-546c2582-4117-4f43-b816-919ac6411f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467119124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1467119124
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3856343543
Short name T1127
Test name
Test status
Simulation time 27524988 ps
CPU time 1.93 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 218992 kb
Host smart-01374449-9b11-4fc5-90a4-3cd640483b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856343543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3856343543
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2491615947
Short name T280
Test name
Test status
Simulation time 61235240 ps
CPU time 1.6 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 215192 kb
Host smart-24b0c5a9-30d0-47f6-9f78-c5d893928d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491615947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2491615947
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2267591038
Short name T1056
Test name
Test status
Simulation time 52655561 ps
CPU time 1.22 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 215148 kb
Host smart-0a1068b1-b4e3-4d25-9131-165c51b655c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267591038 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2267591038
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1666722309
Short name T241
Test name
Test status
Simulation time 12749725 ps
CPU time 0.97 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 206872 kb
Host smart-1de67785-69ac-4f8c-a725-15c3997458ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666722309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1666722309
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1487075397
Short name T1006
Test name
Test status
Simulation time 73907166 ps
CPU time 0.89 seconds
Started Jul 04 05:29:05 PM PDT 24
Finished Jul 04 05:29:06 PM PDT 24
Peak memory 206844 kb
Host smart-2a8e84c4-a866-40bd-bcb6-7270d1009198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487075397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1487075397
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1808295358
Short name T240
Test name
Test status
Simulation time 115640991 ps
CPU time 0.95 seconds
Started Jul 04 05:29:08 PM PDT 24
Finished Jul 04 05:29:09 PM PDT 24
Peak memory 206896 kb
Host smart-4a7859c7-b4cb-4aa5-b9f5-4545c58513dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808295358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1808295358
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.311750996
Short name T1124
Test name
Test status
Simulation time 96913878 ps
CPU time 2.15 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 215152 kb
Host smart-bcade82d-3eb3-46b1-9170-8e6556ecb673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311750996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.311750996
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.290519144
Short name T1115
Test name
Test status
Simulation time 1276423335 ps
CPU time 2.45 seconds
Started Jul 04 05:29:11 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 206984 kb
Host smart-fb362857-fb38-453d-8dfe-9c99effad60c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290519144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.290519144
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2720806087
Short name T1040
Test name
Test status
Simulation time 39171147 ps
CPU time 1.15 seconds
Started Jul 04 05:29:06 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 216664 kb
Host smart-4d94c18e-5718-4489-b419-21b89749d8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720806087 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2720806087
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.581081536
Short name T1021
Test name
Test status
Simulation time 13644812 ps
CPU time 0.93 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206844 kb
Host smart-27f33552-7ecc-48f8-a5f7-ae69063aa67e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581081536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.581081536
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2690039780
Short name T1048
Test name
Test status
Simulation time 17628831 ps
CPU time 0.8 seconds
Started Jul 04 05:29:10 PM PDT 24
Finished Jul 04 05:29:11 PM PDT 24
Peak memory 206616 kb
Host smart-a1981380-9c68-4180-add5-e0ba815488da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690039780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2690039780
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1069468851
Short name T243
Test name
Test status
Simulation time 30056292 ps
CPU time 1.35 seconds
Started Jul 04 05:29:14 PM PDT 24
Finished Jul 04 05:29:16 PM PDT 24
Peak memory 206968 kb
Host smart-905a8268-adce-4a4c-a9b5-7971f591fbe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069468851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1069468851
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2245976621
Short name T1037
Test name
Test status
Simulation time 63170329 ps
CPU time 2.49 seconds
Started Jul 04 05:29:07 PM PDT 24
Finished Jul 04 05:29:10 PM PDT 24
Peak memory 215248 kb
Host smart-c7b19a40-9bf5-4370-917e-f7d73f42459e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245976621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2245976621
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.525790907
Short name T1129
Test name
Test status
Simulation time 47507921 ps
CPU time 1.64 seconds
Started Jul 04 05:29:13 PM PDT 24
Finished Jul 04 05:29:15 PM PDT 24
Peak memory 206908 kb
Host smart-4abe54b1-1024-4e1f-9942-8e40414ad0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525790907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.525790907
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2543769818
Short name T792
Test name
Test status
Simulation time 157328206 ps
CPU time 0.93 seconds
Started Jul 04 06:24:53 PM PDT 24
Finished Jul 04 06:24:54 PM PDT 24
Peak memory 215208 kb
Host smart-af6539a1-ecae-4902-b599-4dd7b0952c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543769818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2543769818
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.4221477087
Short name T110
Test name
Test status
Simulation time 62961879 ps
CPU time 1 seconds
Started Jul 04 06:24:47 PM PDT 24
Finished Jul 04 06:24:48 PM PDT 24
Peak memory 220900 kb
Host smart-cf9a254e-4536-408e-8681-c0d8d1494f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221477087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.4221477087
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3120696854
Short name T348
Test name
Test status
Simulation time 73854544 ps
CPU time 1.12 seconds
Started Jul 04 06:24:52 PM PDT 24
Finished Jul 04 06:24:53 PM PDT 24
Peak memory 217448 kb
Host smart-702c65a0-5f38-4166-ab0f-fd92b4d90c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120696854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3120696854
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1805962426
Short name T666
Test name
Test status
Simulation time 45346305 ps
CPU time 0.94 seconds
Started Jul 04 06:24:50 PM PDT 24
Finished Jul 04 06:24:51 PM PDT 24
Peak memory 215996 kb
Host smart-579a0613-95c4-483e-981f-ed60c88b79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805962426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1805962426
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.615058213
Short name T907
Test name
Test status
Simulation time 29453918 ps
CPU time 1.04 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:24:59 PM PDT 24
Peak memory 207432 kb
Host smart-234e77eb-96ad-40aa-ac74-6e0c0ae4f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615058213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.615058213
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.799715476
Short name T19
Test name
Test status
Simulation time 2496629805 ps
CPU time 4.41 seconds
Started Jul 04 06:24:56 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 236548 kb
Host smart-1678a6c0-45d8-4f9a-b641-5531224ca862
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799715476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.799715476
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.306192925
Short name T640
Test name
Test status
Simulation time 54609231 ps
CPU time 0.92 seconds
Started Jul 04 06:24:31 PM PDT 24
Finished Jul 04 06:24:32 PM PDT 24
Peak memory 215580 kb
Host smart-de691ac5-7481-4555-9b24-b2fe93bc60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306192925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.306192925
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3600280744
Short name T186
Test name
Test status
Simulation time 244158752 ps
CPU time 1.78 seconds
Started Jul 04 06:24:36 PM PDT 24
Finished Jul 04 06:24:38 PM PDT 24
Peak memory 220464 kb
Host smart-18259ef7-1e62-4f25-b693-d554af2a7ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600280744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3600280744
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3654140425
Short name T691
Test name
Test status
Simulation time 97331758941 ps
CPU time 1008.83 seconds
Started Jul 04 06:24:34 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 223480 kb
Host smart-55c643ad-9b96-4f2b-b524-a9cf499430d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654140425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3654140425
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1140215336
Short name T612
Test name
Test status
Simulation time 38709959 ps
CPU time 1.2 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 220488 kb
Host smart-43c6754b-5537-4549-ba7f-d6977dcff1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140215336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1140215336
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.2659536528
Short name T910
Test name
Test status
Simulation time 12393381 ps
CPU time 0.93 seconds
Started Jul 04 06:24:51 PM PDT 24
Finished Jul 04 06:24:52 PM PDT 24
Peak memory 216408 kb
Host smart-e224177d-15ea-46e4-9271-45ab6118099e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659536528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2659536528
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_genbits.1616256083
Short name T834
Test name
Test status
Simulation time 40068407 ps
CPU time 1.62 seconds
Started Jul 04 06:24:40 PM PDT 24
Finished Jul 04 06:24:42 PM PDT 24
Peak memory 217532 kb
Host smart-541b55ad-a2c0-48cb-b7ee-0dbff721458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616256083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1616256083
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3104242694
Short name T928
Test name
Test status
Simulation time 23030303 ps
CPU time 1.03 seconds
Started Jul 04 06:24:34 PM PDT 24
Finished Jul 04 06:24:35 PM PDT 24
Peak memory 215820 kb
Host smart-1161b01d-14ff-4624-add2-4b969a3027da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104242694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3104242694
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.305758071
Short name T868
Test name
Test status
Simulation time 26072046 ps
CPU time 0.89 seconds
Started Jul 04 06:24:45 PM PDT 24
Finished Jul 04 06:24:46 PM PDT 24
Peak memory 207392 kb
Host smart-81da2fc2-e1f8-44ea-86db-c6ed63f8491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305758071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.305758071
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1964864372
Short name T969
Test name
Test status
Simulation time 22863660 ps
CPU time 0.86 seconds
Started Jul 04 06:24:36 PM PDT 24
Finished Jul 04 06:24:37 PM PDT 24
Peak memory 215592 kb
Host smart-dcee6a4f-48bf-47dc-97b5-a7749b56a5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964864372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1964864372
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.807290346
Short name T500
Test name
Test status
Simulation time 2294621243 ps
CPU time 6.18 seconds
Started Jul 04 06:24:54 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 215724 kb
Host smart-67eaee03-4a6d-42a0-88bd-99556f383e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807290346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.807290346
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.203651277
Short name T441
Test name
Test status
Simulation time 33911458363 ps
CPU time 792.15 seconds
Started Jul 04 06:24:37 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 224080 kb
Host smart-dc4b8a71-02c0-4a0d-83bd-905785d814c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203651277 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.203651277
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2422269122
Short name T326
Test name
Test status
Simulation time 40393666 ps
CPU time 1.14 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 220316 kb
Host smart-4c30c8ce-9aef-4352-ac75-dbbe94f98140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422269122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2422269122
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3573041021
Short name T448
Test name
Test status
Simulation time 40889103 ps
CPU time 0.86 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 206992 kb
Host smart-f070180f-5fa0-49f1-a03b-a43c5ac21530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573041021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3573041021
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2093638044
Short name T540
Test name
Test status
Simulation time 12798801 ps
CPU time 0.89 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 216444 kb
Host smart-c0e0c844-7a87-495d-b58a-6ab3ea0f0d15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093638044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2093638044
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1916257831
Short name T496
Test name
Test status
Simulation time 103368680 ps
CPU time 1.08 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 217296 kb
Host smart-9dde87a2-3efd-44f3-a5dc-257ee0decd4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916257831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1916257831
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.350843962
Short name T190
Test name
Test status
Simulation time 18606326 ps
CPU time 1 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 218796 kb
Host smart-1f061cf0-e221-4b6d-8fa0-e9023dea5e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350843962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.350843962
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3792057945
Short name T965
Test name
Test status
Simulation time 63343641 ps
CPU time 1.38 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 219156 kb
Host smart-a2f6158d-5687-4fe1-bf0d-2b9452d6f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792057945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3792057945
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2498672092
Short name T716
Test name
Test status
Simulation time 43196760 ps
CPU time 1.19 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 225544 kb
Host smart-0647ec55-498e-4888-9c2c-074c000be3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498672092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2498672092
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.533073302
Short name T648
Test name
Test status
Simulation time 17628970 ps
CPU time 1 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 215576 kb
Host smart-3199b8b1-aa99-4bd2-8d68-73021ff96c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533073302 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.533073302
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3380744480
Short name T230
Test name
Test status
Simulation time 677119657 ps
CPU time 2.19 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 217600 kb
Host smart-d8658932-5f22-4250-a603-000e3bb3440b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380744480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3380744480
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3193213932
Short name T906
Test name
Test status
Simulation time 100667203014 ps
CPU time 630.67 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:35:46 PM PDT 24
Peak memory 220980 kb
Host smart-144bc321-808a-46b2-9aa6-f2f09cf7fd9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193213932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3193213932
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.791573457
Short name T674
Test name
Test status
Simulation time 94728384 ps
CPU time 1.16 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 220560 kb
Host smart-12edcb33-0c87-482b-a7b9-29669fea3922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791573457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.791573457
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2667426921
Short name T839
Test name
Test status
Simulation time 107294446 ps
CPU time 2.6 seconds
Started Jul 04 06:26:15 PM PDT 24
Finished Jul 04 06:26:18 PM PDT 24
Peak memory 218948 kb
Host smart-9e1c789c-1125-49b2-84d5-24abf88d8d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667426921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2667426921
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.35455530
Short name T593
Test name
Test status
Simulation time 58051277 ps
CPU time 1.22 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 218816 kb
Host smart-a18cd4ea-63cf-413d-ba45-f0f432368d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35455530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.35455530
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3366228527
Short name T581
Test name
Test status
Simulation time 61851221 ps
CPU time 1.29 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 217716 kb
Host smart-7ce5d69d-8c69-4c1b-875c-3b27be9a0e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366228527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3366228527
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2375950022
Short name T68
Test name
Test status
Simulation time 43474964 ps
CPU time 1.16 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 218952 kb
Host smart-8c7d2008-59c9-42e6-8065-c06243cf0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375950022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2375950022
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2259610628
Short name T848
Test name
Test status
Simulation time 365010809 ps
CPU time 3.79 seconds
Started Jul 04 06:26:16 PM PDT 24
Finished Jul 04 06:26:20 PM PDT 24
Peak memory 220196 kb
Host smart-2f506f12-e0da-4d90-9936-a7a332a81848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259610628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2259610628
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.4235000043
Short name T432
Test name
Test status
Simulation time 69542086 ps
CPU time 1.16 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 219100 kb
Host smart-50955fb4-28db-49c4-b528-f4ba0643b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235000043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.4235000043
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3470421101
Short name T939
Test name
Test status
Simulation time 89500965 ps
CPU time 1.11 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 217512 kb
Host smart-ad246e46-c794-40c8-9069-0324f80a6f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470421101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3470421101
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3374957320
Short name T589
Test name
Test status
Simulation time 28302423 ps
CPU time 1.35 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 219944 kb
Host smart-5a86ab5e-193e-4f38-ba4c-35c08828d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374957320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3374957320
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.1902602690
Short name T395
Test name
Test status
Simulation time 48450424 ps
CPU time 1.83 seconds
Started Jul 04 06:26:33 PM PDT 24
Finished Jul 04 06:26:35 PM PDT 24
Peak memory 217824 kb
Host smart-5cd794b0-8a16-4fe8-a14a-6940610ff00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902602690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1902602690
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3001336528
Short name T380
Test name
Test status
Simulation time 93213896 ps
CPU time 1.3 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 217792 kb
Host smart-291144df-7025-45d9-8f15-4c0494d0d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001336528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3001336528
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2465554639
Short name T592
Test name
Test status
Simulation time 25322543 ps
CPU time 1.21 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 219812 kb
Host smart-7bf3d79e-8905-4131-bb4f-360542182112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465554639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2465554639
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.4030381175
Short name T678
Test name
Test status
Simulation time 79390417 ps
CPU time 1.3 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 219168 kb
Host smart-3d7a6796-8b0e-4154-ba0f-370e58f3d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030381175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4030381175
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1196959664
Short name T591
Test name
Test status
Simulation time 38669798 ps
CPU time 1.32 seconds
Started Jul 04 06:26:13 PM PDT 24
Finished Jul 04 06:26:16 PM PDT 24
Peak memory 215936 kb
Host smart-a445affa-cac5-40d7-8bf4-73363c2fdaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196959664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1196959664
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.2485850615
Short name T793
Test name
Test status
Simulation time 30649546 ps
CPU time 1.18 seconds
Started Jul 04 06:26:36 PM PDT 24
Finished Jul 04 06:26:37 PM PDT 24
Peak memory 220856 kb
Host smart-48d334a3-59e2-429f-a330-b42cf88b7d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485850615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2485850615
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.344811221
Short name T658
Test name
Test status
Simulation time 27336492 ps
CPU time 1.3 seconds
Started Jul 04 06:26:32 PM PDT 24
Finished Jul 04 06:26:34 PM PDT 24
Peak memory 219048 kb
Host smart-37067dfe-84ef-4b22-b63c-a0359e94c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344811221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.344811221
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2968015850
Short name T264
Test name
Test status
Simulation time 26223969 ps
CPU time 1.21 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 219948 kb
Host smart-7b3cf7be-1b18-4336-b339-5671c4218432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968015850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2968015850
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1205229960
Short name T410
Test name
Test status
Simulation time 52720724 ps
CPU time 0.98 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 215516 kb
Host smart-41cd5e35-ce1d-43bd-be9a-8172abda21e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205229960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1205229960
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3994233865
Short name T690
Test name
Test status
Simulation time 36152134 ps
CPU time 0.86 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 216188 kb
Host smart-f81db1dd-7100-43de-91c7-ce68279e2cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994233865 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3994233865
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1963750855
Short name T393
Test name
Test status
Simulation time 93341858 ps
CPU time 1.03 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 217268 kb
Host smart-39fe3277-eab0-40e4-8e41-1ba5c921b47b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963750855 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1963750855
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.1603120976
Short name T353
Test name
Test status
Simulation time 34850424 ps
CPU time 1.28 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 217644 kb
Host smart-1764db5a-2eb8-4750-8152-80512b8ab0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603120976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1603120976
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.3032158272
Short name T879
Test name
Test status
Simulation time 31419883 ps
CPU time 0.95 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 215612 kb
Host smart-763b8727-f59f-4c00-a606-ab348902b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032158272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3032158272
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1133868165
Short name T841
Test name
Test status
Simulation time 390621733 ps
CPU time 4.51 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 215640 kb
Host smart-2651cbfe-2552-40ac-ac1d-07a36e005c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133868165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1133868165
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2652363654
Short name T387
Test name
Test status
Simulation time 37506129745 ps
CPU time 445.08 seconds
Started Jul 04 06:25:04 PM PDT 24
Finished Jul 04 06:32:29 PM PDT 24
Peak memory 223984 kb
Host smart-52cff66e-0f68-4a10-913f-4ebd60ed3106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652363654 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2652363654
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.414304455
Short name T408
Test name
Test status
Simulation time 82219848 ps
CPU time 1.64 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 220232 kb
Host smart-60ad4159-52ab-41cc-be1e-557995328e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414304455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.414304455
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3113067236
Short name T937
Test name
Test status
Simulation time 105270222 ps
CPU time 1.07 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 218820 kb
Host smart-acd758ba-44eb-4c1f-802a-9e19b1a866dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113067236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3113067236
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.3477579998
Short name T369
Test name
Test status
Simulation time 37427681 ps
CPU time 1.3 seconds
Started Jul 04 06:26:29 PM PDT 24
Finished Jul 04 06:26:31 PM PDT 24
Peak memory 220188 kb
Host smart-30aa095b-30e8-4d02-a64f-099ec30c708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477579998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3477579998
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1562137415
Short name T234
Test name
Test status
Simulation time 28916527 ps
CPU time 1.49 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 218744 kb
Host smart-191fc6c7-2d8d-476a-8b37-1e76a2c80960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562137415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1562137415
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2338877865
Short name T653
Test name
Test status
Simulation time 51326604 ps
CPU time 1.15 seconds
Started Jul 04 06:26:36 PM PDT 24
Finished Jul 04 06:26:37 PM PDT 24
Peak memory 220364 kb
Host smart-cd46c402-d67c-4881-a4e5-920348949383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338877865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2338877865
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2359130948
Short name T733
Test name
Test status
Simulation time 100969553 ps
CPU time 1.47 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 219192 kb
Host smart-ef7f2b12-760b-4448-8595-af55833d3cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359130948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2359130948
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3876661437
Short name T882
Test name
Test status
Simulation time 31279745 ps
CPU time 1.09 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 218860 kb
Host smart-95ff616e-f889-49c1-a5f9-e8bb23f85de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876661437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3876661437
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.828372376
Short name T638
Test name
Test status
Simulation time 59358062 ps
CPU time 1.35 seconds
Started Jul 04 06:26:39 PM PDT 24
Finished Jul 04 06:26:40 PM PDT 24
Peak memory 220140 kb
Host smart-a43df124-6f9c-4f3b-ba8f-2b2f5be533bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828372376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.828372376
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2521649509
Short name T903
Test name
Test status
Simulation time 79630225 ps
CPU time 1.14 seconds
Started Jul 04 06:26:27 PM PDT 24
Finished Jul 04 06:26:28 PM PDT 24
Peak memory 218904 kb
Host smart-468e89c2-6c5c-4ab1-97ae-18f9d4333c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521649509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2521649509
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.12543100
Short name T325
Test name
Test status
Simulation time 70229957 ps
CPU time 1.15 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 220056 kb
Host smart-1ec1ddb3-de35-416e-8a97-9ef8776c94b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12543100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.12543100
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2079727876
Short name T856
Test name
Test status
Simulation time 59387183 ps
CPU time 1.23 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 215724 kb
Host smart-ff2f070e-9c8d-418c-af82-ff6ab592a2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079727876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2079727876
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2338750585
Short name T634
Test name
Test status
Simulation time 64236420 ps
CPU time 1.31 seconds
Started Jul 04 06:26:20 PM PDT 24
Finished Jul 04 06:26:21 PM PDT 24
Peak memory 218844 kb
Host smart-eaf56104-9864-4031-93fb-991a6a2892d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338750585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2338750585
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1777076276
Short name T712
Test name
Test status
Simulation time 306884788 ps
CPU time 1.31 seconds
Started Jul 04 06:26:31 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 220928 kb
Host smart-ed42d306-fe60-4da3-984e-4d213a1d579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777076276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1777076276
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.3777514214
Short name T925
Test name
Test status
Simulation time 129931625 ps
CPU time 1.3 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 218904 kb
Host smart-e289d0ab-7647-43d4-bc9c-d858c5e86649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777514214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3777514214
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1988096257
Short name T67
Test name
Test status
Simulation time 24971212 ps
CPU time 0.9 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 207040 kb
Host smart-8a81b6c1-88ce-4950-83b9-c474175b9a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988096257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1988096257
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3132839337
Short name T783
Test name
Test status
Simulation time 40803727 ps
CPU time 0.87 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 216568 kb
Host smart-65592502-c73d-4f91-b893-65aca19415b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132839337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3132839337
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.13680431
Short name T434
Test name
Test status
Simulation time 39829441 ps
CPU time 1.34 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 217264 kb
Host smart-f327832e-9ba7-4122-a74f-1f4500bd6a7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13680431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_dis
able_auto_req_mode.13680431
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1394771585
Short name T661
Test name
Test status
Simulation time 23551269 ps
CPU time 1.25 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 224184 kb
Host smart-3444cba6-8243-4e62-b3e2-a6f32d223840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394771585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1394771585
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.456090190
Short name T376
Test name
Test status
Simulation time 168801405 ps
CPU time 1.42 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 219292 kb
Host smart-25fa9485-44c9-455d-bb86-f9419b5fe7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456090190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.456090190
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2726022660
Short name T815
Test name
Test status
Simulation time 20004932 ps
CPU time 1.1 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 217020 kb
Host smart-d490d60a-14d9-4b27-8783-2fa8e55418a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726022660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2726022660
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1287497984
Short name T740
Test name
Test status
Simulation time 18885241 ps
CPU time 0.98 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 215632 kb
Host smart-ded65079-b11e-433e-915c-0a7040304fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287497984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1287497984
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.95825417
Short name T220
Test name
Test status
Simulation time 17762176572 ps
CPU time 404.51 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:31:52 PM PDT 24
Peak memory 223940 kb
Host smart-37513e82-dbe3-4409-a964-2e8e9f5ba4a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95825417 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.95825417
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1473202540
Short name T724
Test name
Test status
Simulation time 103212769 ps
CPU time 1.17 seconds
Started Jul 04 06:26:31 PM PDT 24
Finished Jul 04 06:26:33 PM PDT 24
Peak memory 216008 kb
Host smart-f8960b90-07c9-4b49-9b53-2882a33d294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473202540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1473202540
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.4284034606
Short name T605
Test name
Test status
Simulation time 46184520 ps
CPU time 1.23 seconds
Started Jul 04 06:26:24 PM PDT 24
Finished Jul 04 06:26:25 PM PDT 24
Peak memory 218972 kb
Host smart-00d98724-42c2-4760-8176-2a4e2b8fe19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284034606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4284034606
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.424049888
Short name T985
Test name
Test status
Simulation time 50581662 ps
CPU time 1.29 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 220440 kb
Host smart-69ac8b42-7496-4ccf-b5c2-8a2bf4ee39a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424049888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.424049888
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2722775608
Short name T972
Test name
Test status
Simulation time 104787126 ps
CPU time 1.12 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 217672 kb
Host smart-b31921fc-239c-43b9-bf31-48506dc71713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722775608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2722775608
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3914629807
Short name T428
Test name
Test status
Simulation time 21566979 ps
CPU time 1.1 seconds
Started Jul 04 06:26:30 PM PDT 24
Finished Jul 04 06:26:31 PM PDT 24
Peak memory 219080 kb
Host smart-2152b632-dec5-49db-a36c-6adbd412c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914629807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3914629807
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1336424440
Short name T899
Test name
Test status
Simulation time 51708915 ps
CPU time 1.48 seconds
Started Jul 04 06:26:23 PM PDT 24
Finished Jul 04 06:26:25 PM PDT 24
Peak memory 218856 kb
Host smart-1bd431e0-6dfc-4a94-ab55-a6e61457036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336424440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1336424440
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1735871831
Short name T622
Test name
Test status
Simulation time 62576567 ps
CPU time 1.32 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 216040 kb
Host smart-300bdee3-6e21-4431-919f-2f537845cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735871831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1735871831
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2542819454
Short name T579
Test name
Test status
Simulation time 29417653 ps
CPU time 1.29 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 218788 kb
Host smart-de239e8a-1df9-4ade-bcc0-e8c5d245dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542819454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2542819454
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.4006680812
Short name T170
Test name
Test status
Simulation time 49686383 ps
CPU time 1.22 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 218936 kb
Host smart-088105a4-6c94-4bd2-b7c0-a46579068af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006680812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.4006680812
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2300395351
Short name T314
Test name
Test status
Simulation time 175667126 ps
CPU time 1.9 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 219260 kb
Host smart-c09ba602-fc41-4c0b-a366-ab709d20d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300395351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2300395351
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1135615182
Short name T721
Test name
Test status
Simulation time 50818919 ps
CPU time 1.18 seconds
Started Jul 04 06:26:29 PM PDT 24
Finished Jul 04 06:26:30 PM PDT 24
Peak memory 219112 kb
Host smart-fca6401d-7fa5-496a-880c-744d95b5ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135615182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1135615182
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2835017342
Short name T77
Test name
Test status
Simulation time 82107901 ps
CPU time 1.21 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 218800 kb
Host smart-71b6b7ee-fbab-42d8-b78b-07262152af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835017342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2835017342
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3549148351
Short name T631
Test name
Test status
Simulation time 39834298 ps
CPU time 1.14 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 220348 kb
Host smart-006bbc07-3789-45f1-b5fb-9b07329adf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549148351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3549148351
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3377041241
Short name T466
Test name
Test status
Simulation time 29151955 ps
CPU time 1.17 seconds
Started Jul 04 06:26:33 PM PDT 24
Finished Jul 04 06:26:34 PM PDT 24
Peak memory 219132 kb
Host smart-7ed0b980-3811-4570-aad7-25339f7f1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377041241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3377041241
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3075872688
Short name T867
Test name
Test status
Simulation time 65106330 ps
CPU time 1.07 seconds
Started Jul 04 06:26:31 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 215716 kb
Host smart-f63483a9-9238-4fbb-b6d7-1d3b6198f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075872688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3075872688
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2402726681
Short name T285
Test name
Test status
Simulation time 74573410 ps
CPU time 1.15 seconds
Started Jul 04 06:26:20 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 219184 kb
Host smart-e96a15a2-78f4-4cfd-a715-7cb1941fd83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402726681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2402726681
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.198666636
Short name T39
Test name
Test status
Simulation time 50049993 ps
CPU time 1.62 seconds
Started Jul 04 06:26:17 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 218932 kb
Host smart-23441182-6f42-42de-9a14-bf4abe78f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198666636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.198666636
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.74296010
Short name T713
Test name
Test status
Simulation time 36578441 ps
CPU time 0.83 seconds
Started Jul 04 06:25:02 PM PDT 24
Finished Jul 04 06:25:03 PM PDT 24
Peak memory 206796 kb
Host smart-8a513472-c7d2-4904-8b72-aefe1ba58fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74296010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.74296010
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2577361489
Short name T153
Test name
Test status
Simulation time 13022842 ps
CPU time 0.97 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 216664 kb
Host smart-2626370c-e9e3-49a2-98a2-5bb6d391fbde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577361489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2577361489
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.3089705339
Short name T228
Test name
Test status
Simulation time 24435849 ps
CPU time 1.06 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 224260 kb
Host smart-d0a9c878-c0d8-4ab8-b2b9-84da0e04a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089705339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3089705339
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3650529502
Short name T757
Test name
Test status
Simulation time 66037157 ps
CPU time 1.11 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215700 kb
Host smart-62e22f78-e744-4e12-8c28-f629a53fd3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650529502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3650529502
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.3599805727
Short name T350
Test name
Test status
Simulation time 39150573 ps
CPU time 0.88 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 215604 kb
Host smart-20efab1f-c131-4734-a4b2-2bd1d5081116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599805727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3599805727
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4117552809
Short name T482
Test name
Test status
Simulation time 1646289367 ps
CPU time 4.23 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 217400 kb
Host smart-f9ba5a3d-cf29-4b2a-a83b-5c4b5c8d668e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117552809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4117552809
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2803685844
Short name T430
Test name
Test status
Simulation time 41661427380 ps
CPU time 157.59 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:27:51 PM PDT 24
Peak memory 223988 kb
Host smart-845423f9-c1a5-45db-8e71-e443e5913d34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803685844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2803685844
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1521389142
Short name T529
Test name
Test status
Simulation time 45154571 ps
CPU time 1.13 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 220000 kb
Host smart-b443502d-8c32-494d-bff7-03c7774c9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521389142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1521389142
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1448877600
Short name T731
Test name
Test status
Simulation time 34836424 ps
CPU time 1.29 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 218612 kb
Host smart-c5fc4bda-6246-479d-a699-208f3ef0d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448877600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1448877600
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1995255052
Short name T872
Test name
Test status
Simulation time 28062596 ps
CPU time 1.26 seconds
Started Jul 04 06:26:27 PM PDT 24
Finished Jul 04 06:26:29 PM PDT 24
Peak memory 220328 kb
Host smart-f28b9651-3071-4b70-a4b5-c2bbd4f29005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995255052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1995255052
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.4175050608
Short name T371
Test name
Test status
Simulation time 26106508 ps
CPU time 1.13 seconds
Started Jul 04 06:26:13 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 217456 kb
Host smart-14fd9563-e6a6-43b2-85ba-5fd223d64d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175050608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4175050608
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4203221187
Short name T679
Test name
Test status
Simulation time 71449648 ps
CPU time 1.14 seconds
Started Jul 04 06:26:40 PM PDT 24
Finished Jul 04 06:26:42 PM PDT 24
Peak memory 219084 kb
Host smart-55ad89f2-b1e1-45c8-adea-0b7bc25ef0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203221187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4203221187
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3539687180
Short name T306
Test name
Test status
Simulation time 94694010 ps
CPU time 2.87 seconds
Started Jul 04 06:26:14 PM PDT 24
Finished Jul 04 06:26:17 PM PDT 24
Peak memory 219940 kb
Host smart-3ad152ca-feef-4b71-8322-05e342e15ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539687180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3539687180
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.183707479
Short name T494
Test name
Test status
Simulation time 40216146 ps
CPU time 1.16 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 215980 kb
Host smart-c4a018b3-9171-43bb-9fff-f559d5d8d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183707479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.183707479
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.4186297610
Short name T453
Test name
Test status
Simulation time 97525832 ps
CPU time 1.09 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 215620 kb
Host smart-372c5886-c560-4205-bb67-ef8751de396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186297610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4186297610
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1108097109
Short name T801
Test name
Test status
Simulation time 27206911 ps
CPU time 1.25 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 218908 kb
Host smart-1c974480-24d4-4a0c-b260-90789a4e27da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108097109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1108097109
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2176298179
Short name T312
Test name
Test status
Simulation time 114911717 ps
CPU time 2.26 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:16 PM PDT 24
Peak memory 220176 kb
Host smart-987552e0-aaef-453d-9ec5-eef50cc79163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176298179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2176298179
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1985584840
Short name T995
Test name
Test status
Simulation time 39264397 ps
CPU time 1.1 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 218640 kb
Host smart-42b1c8c2-6a93-4ac9-8f95-71fba9e654cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985584840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1985584840
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.695599308
Short name T892
Test name
Test status
Simulation time 54654914 ps
CPU time 1.98 seconds
Started Jul 04 06:26:25 PM PDT 24
Finished Jul 04 06:26:27 PM PDT 24
Peak memory 218748 kb
Host smart-f2b4617c-1edd-4401-8378-27ed097f2540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695599308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.695599308
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.266576565
Short name T450
Test name
Test status
Simulation time 24130846 ps
CPU time 1.2 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 220816 kb
Host smart-266c5df0-efb9-4e53-b068-1a4a969e354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266576565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.266576565
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.3315941727
Short name T179
Test name
Test status
Simulation time 100270553 ps
CPU time 1.15 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 219436 kb
Host smart-bff90c6f-2c91-4f15-8e54-87ded23e28aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315941727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3315941727
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2048136459
Short name T637
Test name
Test status
Simulation time 91228705 ps
CPU time 1.39 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 219240 kb
Host smart-ffc07d98-a5e9-454e-a67a-a95842548c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048136459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2048136459
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2623144833
Short name T627
Test name
Test status
Simulation time 33575435 ps
CPU time 1.31 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 220880 kb
Host smart-b228c480-4f0f-41e9-843b-383e5ba468b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623144833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2623144833
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.534089836
Short name T837
Test name
Test status
Simulation time 78176045 ps
CPU time 1.11 seconds
Started Jul 04 06:26:27 PM PDT 24
Finished Jul 04 06:26:29 PM PDT 24
Peak memory 220800 kb
Host smart-342d80ff-e67e-4dd2-80f0-72fb0bcba4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534089836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.534089836
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1815724601
Short name T782
Test name
Test status
Simulation time 31386250 ps
CPU time 1.3 seconds
Started Jul 04 06:26:28 PM PDT 24
Finished Jul 04 06:26:29 PM PDT 24
Peak memory 217748 kb
Host smart-142d06de-8d8a-41a6-89c7-72d9de1c7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815724601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1815724601
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.798812655
Short name T374
Test name
Test status
Simulation time 50262906 ps
CPU time 1.11 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 218972 kb
Host smart-042326aa-1db3-4b59-854d-b622f420925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798812655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.798812655
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.658769917
Short name T685
Test name
Test status
Simulation time 24468772 ps
CPU time 0.87 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 207092 kb
Host smart-ec8ffbbc-0312-448f-b794-086151aa01c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658769917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.658769917
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2475551940
Short name T546
Test name
Test status
Simulation time 11559223 ps
CPU time 0.92 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 216480 kb
Host smart-ec22a393-6b03-4312-80dc-4a1b458c12cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475551940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2475551940
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1638633597
Short name T486
Test name
Test status
Simulation time 83988077 ps
CPU time 1.21 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 217224 kb
Host smart-513465dc-375b-47f0-a9aa-582f4d54393e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638633597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1638633597
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2534891317
Short name T861
Test name
Test status
Simulation time 69716739 ps
CPU time 0.99 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 220132 kb
Host smart-66b8b680-64b5-4d31-8ace-26ee43d078f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534891317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2534891317
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1500397834
Short name T383
Test name
Test status
Simulation time 71992950 ps
CPU time 1.41 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 218744 kb
Host smart-0a961673-871c-4ace-9a6d-68df7050dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500397834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1500397834
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4244746438
Short name T873
Test name
Test status
Simulation time 24197456 ps
CPU time 0.99 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 215888 kb
Host smart-1024186a-4442-4f6e-b5f6-ad51dc20569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244746438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4244746438
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3238832174
Short name T556
Test name
Test status
Simulation time 36759830 ps
CPU time 0.91 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215592 kb
Host smart-c4756ba4-c804-42fa-90e2-f1dc5cee08a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238832174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3238832174
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2761780203
Short name T935
Test name
Test status
Simulation time 63047346 ps
CPU time 1.75 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 217548 kb
Host smart-3d258d48-01a2-493c-aeaa-44b2138b21a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761780203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2761780203
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.820122413
Short name T321
Test name
Test status
Simulation time 152135461050 ps
CPU time 920.46 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:40:26 PM PDT 24
Peak memory 224024 kb
Host smart-4e9d82c1-a456-4c26-89ce-2de0a87f212e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820122413 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.820122413
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.720871646
Short name T481
Test name
Test status
Simulation time 23010440 ps
CPU time 1.23 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 219012 kb
Host smart-255f0607-217f-42e1-9a2d-17c1c651a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720871646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.720871646
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1247676312
Short name T602
Test name
Test status
Simulation time 119116694 ps
CPU time 1.18 seconds
Started Jul 04 06:26:25 PM PDT 24
Finished Jul 04 06:26:26 PM PDT 24
Peak memory 217680 kb
Host smart-20d8fcfb-95b2-41ca-a300-c65b5f2ae87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247676312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1247676312
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.985097715
Short name T654
Test name
Test status
Simulation time 123386713 ps
CPU time 1.71 seconds
Started Jul 04 06:26:26 PM PDT 24
Finished Jul 04 06:26:28 PM PDT 24
Peak memory 218820 kb
Host smart-2434c10d-4b71-4ea6-b062-f9d4ffd530f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985097715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.985097715
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2039582325
Short name T155
Test name
Test status
Simulation time 118802934 ps
CPU time 1.13 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 220792 kb
Host smart-5553ac0e-0f12-4f51-88ed-7898ccfb7cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039582325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2039582325
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2589480566
Short name T391
Test name
Test status
Simulation time 35020618 ps
CPU time 1.69 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 218700 kb
Host smart-71753b0b-3603-4800-93e5-c65f00d8c927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589480566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2589480566
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3595846389
Short name T46
Test name
Test status
Simulation time 51217535 ps
CPU time 1.26 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 218856 kb
Host smart-5a573c11-283d-4e04-8a9b-90438ad6c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595846389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3595846389
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3075393479
Short name T689
Test name
Test status
Simulation time 118321235 ps
CPU time 2.08 seconds
Started Jul 04 06:26:36 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 220608 kb
Host smart-fb63a465-8be6-4c36-8df2-27a7f34ad3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075393479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3075393479
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2624338147
Short name T517
Test name
Test status
Simulation time 52916312 ps
CPU time 1.19 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 221200 kb
Host smart-bf17ffba-bdd6-4be0-97ba-86add9c67db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624338147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2624338147
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.446962819
Short name T521
Test name
Test status
Simulation time 33780052 ps
CPU time 1.34 seconds
Started Jul 04 06:26:17 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 220060 kb
Host smart-147f59dc-b4b7-456d-89ba-6b2c50ff07e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446962819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.446962819
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1198014706
Short name T164
Test name
Test status
Simulation time 56774238 ps
CPU time 1.15 seconds
Started Jul 04 06:26:16 PM PDT 24
Finished Jul 04 06:26:18 PM PDT 24
Peak memory 219008 kb
Host smart-27bdf3b1-2bfb-40aa-9b4b-f61e735514c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198014706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1198014706
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.467246298
Short name T961
Test name
Test status
Simulation time 40768751 ps
CPU time 1.53 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:39 PM PDT 24
Peak memory 218832 kb
Host smart-04099dff-26aa-4a75-9a88-db12661b8e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467246298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.467246298
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2752462616
Short name T157
Test name
Test status
Simulation time 90493555 ps
CPU time 1.17 seconds
Started Jul 04 06:26:17 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 216020 kb
Host smart-f9e1a8c7-32b0-4952-8a95-23b781c8f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752462616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2752462616
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.483879568
Short name T300
Test name
Test status
Simulation time 169321294 ps
CPU time 2.43 seconds
Started Jul 04 06:26:19 PM PDT 24
Finished Jul 04 06:26:21 PM PDT 24
Peak memory 218996 kb
Host smart-cb9fd0e8-43b2-44d7-bf15-fe4c0350dd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483879568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.483879568
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.2175420874
Short name T967
Test name
Test status
Simulation time 50367716 ps
CPU time 1.08 seconds
Started Jul 04 06:26:16 PM PDT 24
Finished Jul 04 06:26:17 PM PDT 24
Peak memory 219896 kb
Host smart-0db48de3-fb46-4f33-8fbe-e48783b89597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175420874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2175420874
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3832586229
Short name T427
Test name
Test status
Simulation time 151072990 ps
CPU time 3.15 seconds
Started Jul 04 06:26:42 PM PDT 24
Finished Jul 04 06:26:45 PM PDT 24
Peak memory 219160 kb
Host smart-e6f4ed35-5c84-425a-9204-62141c78b49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832586229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3832586229
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2887933145
Short name T399
Test name
Test status
Simulation time 32900206 ps
CPU time 1.43 seconds
Started Jul 04 06:26:42 PM PDT 24
Finished Jul 04 06:26:43 PM PDT 24
Peak memory 218972 kb
Host smart-72433ff9-83b2-427b-a496-68b36fba4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887933145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2887933145
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3724727203
Short name T814
Test name
Test status
Simulation time 98895678 ps
CPU time 1.2 seconds
Started Jul 04 06:26:45 PM PDT 24
Finished Jul 04 06:26:47 PM PDT 24
Peak memory 219664 kb
Host smart-6e1cb8dc-3322-4f2a-9d85-a18053ab1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724727203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3724727203
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3782914821
Short name T896
Test name
Test status
Simulation time 139630284 ps
CPU time 2.8 seconds
Started Jul 04 06:26:35 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 215660 kb
Host smart-8620fb00-1caf-45b7-91af-1fcf0314a655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782914821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3782914821
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2717585065
Short name T809
Test name
Test status
Simulation time 22376382 ps
CPU time 1.19 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 220148 kb
Host smart-37d500d3-30f1-4985-926c-9ed7e3e1d46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717585065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2717585065
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1986114731
Short name T838
Test name
Test status
Simulation time 42128060 ps
CPU time 0.84 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 206832 kb
Host smart-83d59fa5-145c-467e-a56c-beae1268c30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986114731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1986114731
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3342820720
Short name T894
Test name
Test status
Simulation time 17254784 ps
CPU time 0.81 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 216472 kb
Host smart-74611382-854f-4305-bab8-fd156a85ade4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342820720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3342820720
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2218423881
Short name T720
Test name
Test status
Simulation time 37228027 ps
CPU time 1.01 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 217044 kb
Host smart-45abe81d-9c80-4df7-84c4-ce0a5080b136
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218423881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2218423881
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1453311528
Short name T198
Test name
Test status
Simulation time 51058718 ps
CPU time 0.81 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 219728 kb
Host smart-5c6423a5-aee1-4a7d-af5d-69d5012a2b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453311528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1453311528
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2921441723
Short name T850
Test name
Test status
Simulation time 79551843 ps
CPU time 1.26 seconds
Started Jul 04 06:25:03 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 220136 kb
Host smart-dc743ed0-2af8-4a3c-9aff-f97d384b616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921441723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2921441723
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2020069530
Short name T512
Test name
Test status
Simulation time 19954845 ps
CPU time 1.01 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 215588 kb
Host smart-5411d0c3-fa23-4430-9c38-361c51d625dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020069530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2020069530
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4168776727
Short name T763
Test name
Test status
Simulation time 265387543 ps
CPU time 3.54 seconds
Started Jul 04 06:25:39 PM PDT 24
Finished Jul 04 06:25:43 PM PDT 24
Peak memory 215520 kb
Host smart-28b6f198-7fa9-4c1a-99db-839a59a471e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168776727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4168776727
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2683335438
Short name T388
Test name
Test status
Simulation time 194071790415 ps
CPU time 983.32 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:41:31 PM PDT 24
Peak memory 222104 kb
Host smart-059201c3-6014-4012-8678-9572b7390b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683335438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2683335438
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.408160517
Short name T69
Test name
Test status
Simulation time 26248785 ps
CPU time 1.23 seconds
Started Jul 04 06:26:51 PM PDT 24
Finished Jul 04 06:26:53 PM PDT 24
Peak memory 219948 kb
Host smart-c3c81779-32e3-4a35-80f0-c2681879fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408160517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.408160517
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3367931661
Short name T754
Test name
Test status
Simulation time 58244854 ps
CPU time 2.07 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:39 PM PDT 24
Peak memory 220392 kb
Host smart-bb5f28e8-2356-4c81-9f78-4ab47e30bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367931661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3367931661
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3316170347
Short name T132
Test name
Test status
Simulation time 29829150 ps
CPU time 1.26 seconds
Started Jul 04 06:26:18 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 219800 kb
Host smart-892eaed9-126b-41fe-afc5-bd3ecdedea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316170347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3316170347
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3268148512
Short name T288
Test name
Test status
Simulation time 27101744 ps
CPU time 1.2 seconds
Started Jul 04 06:26:19 PM PDT 24
Finished Jul 04 06:26:20 PM PDT 24
Peak memory 217632 kb
Host smart-82594fe5-6bf4-4f1f-8725-2251ca631e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268148512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3268148512
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1239074281
Short name T527
Test name
Test status
Simulation time 115940307 ps
CPU time 1.16 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:23 PM PDT 24
Peak memory 219932 kb
Host smart-de05d289-520e-4c79-915a-9a2b0b88e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239074281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1239074281
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4013145129
Short name T606
Test name
Test status
Simulation time 38406447 ps
CPU time 1.39 seconds
Started Jul 04 06:26:33 PM PDT 24
Finished Jul 04 06:26:35 PM PDT 24
Peak memory 218792 kb
Host smart-4e3040fd-9bf1-4ff8-8262-fcf21c9c7946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013145129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4013145129
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2981598789
Short name T717
Test name
Test status
Simulation time 147936831 ps
CPU time 1.16 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 219364 kb
Host smart-e11d7a53-6a46-4839-b6fa-245fc74f30d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981598789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2981598789
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.730392445
Short name T919
Test name
Test status
Simulation time 34789692 ps
CPU time 1.38 seconds
Started Jul 04 06:26:29 PM PDT 24
Finished Jul 04 06:26:30 PM PDT 24
Peak memory 220404 kb
Host smart-a9e68904-57df-4dee-8d72-684f2d6d330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730392445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.730392445
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.822906225
Short name T125
Test name
Test status
Simulation time 47399429 ps
CPU time 1.21 seconds
Started Jul 04 06:26:35 PM PDT 24
Finished Jul 04 06:26:36 PM PDT 24
Peak memory 215920 kb
Host smart-75350dbc-4a72-41fe-9297-271d6f54361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822906225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.822906225
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1000040925
Short name T772
Test name
Test status
Simulation time 47464069 ps
CPU time 1.67 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:23 PM PDT 24
Peak memory 218984 kb
Host smart-2cbb2d51-8030-4ee5-bfc8-873a02ce3ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000040925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1000040925
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3194755280
Short name T267
Test name
Test status
Simulation time 69103415 ps
CPU time 1.14 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 219716 kb
Host smart-dd43b7dd-c5de-4610-8125-f116abfcaf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194755280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3194755280
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3019273172
Short name T318
Test name
Test status
Simulation time 126257903 ps
CPU time 2.95 seconds
Started Jul 04 06:26:19 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 220472 kb
Host smart-9948079f-186e-4a53-b28e-32eaa4a22814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019273172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3019273172
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2010528441
Short name T269
Test name
Test status
Simulation time 83753091 ps
CPU time 1.23 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:39 PM PDT 24
Peak memory 220232 kb
Host smart-47c9a7d3-62f4-4854-bb55-f3807863a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010528441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2010528441
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1188287633
Short name T506
Test name
Test status
Simulation time 194941461 ps
CPU time 1.14 seconds
Started Jul 04 06:26:22 PM PDT 24
Finished Jul 04 06:26:23 PM PDT 24
Peak memory 217612 kb
Host smart-71d0ab2d-ac89-4e3b-af24-1ba65ea40e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188287633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1188287633
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.4082824412
Short name T171
Test name
Test status
Simulation time 89095319 ps
CPU time 1.03 seconds
Started Jul 04 06:26:31 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 218696 kb
Host smart-fa274892-e488-44e5-8931-07df9d19e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082824412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.4082824412
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3589359978
Short name T784
Test name
Test status
Simulation time 48618702 ps
CPU time 1.65 seconds
Started Jul 04 06:26:42 PM PDT 24
Finished Jul 04 06:26:44 PM PDT 24
Peak memory 218908 kb
Host smart-cef09952-d865-4e8a-bbcd-7c69b07f1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589359978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3589359978
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1836248517
Short name T810
Test name
Test status
Simulation time 43952786 ps
CPU time 1.22 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 221148 kb
Host smart-85793cc8-6855-4772-ba3c-f5c0ae8d9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836248517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1836248517
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3366794641
Short name T331
Test name
Test status
Simulation time 54633121 ps
CPU time 1.24 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 220216 kb
Host smart-f74a6506-3eb0-4e7d-b378-078af2ef7681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366794641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3366794641
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3360051058
Short name T462
Test name
Test status
Simulation time 81900051 ps
CPU time 1.17 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 220096 kb
Host smart-cc3bf532-8ebc-42c6-aaf4-b325585357f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360051058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3360051058
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert.711024989
Short name T274
Test name
Test status
Simulation time 99774467 ps
CPU time 1.3 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 216008 kb
Host smart-087b3ba0-f66b-4b68-8c3d-ca366a248527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711024989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.711024989
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.4016698102
Short name T797
Test name
Test status
Simulation time 28403424 ps
CPU time 0.88 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 215392 kb
Host smart-f830c8be-37f7-43bd-994b-53d47a5fab51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016698102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4016698102
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_err.3621395693
Short name T802
Test name
Test status
Simulation time 25959192 ps
CPU time 1.01 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 220196 kb
Host smart-c32676fc-4139-4a17-966f-6bcd55ec149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621395693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3621395693
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3620004370
Short name T542
Test name
Test status
Simulation time 108882944 ps
CPU time 1.86 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 219360 kb
Host smart-11927861-c4ea-41e1-9c47-7e78b36749b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620004370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3620004370
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2148485707
Short name T585
Test name
Test status
Simulation time 24612009 ps
CPU time 1.02 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 224420 kb
Host smart-1aa09ba9-044c-43aa-b6b9-5e63869bec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148485707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2148485707
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1507113290
Short name T626
Test name
Test status
Simulation time 23240697 ps
CPU time 0.93 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 215636 kb
Host smart-36f7fef9-213b-4ef3-b01c-8733847008b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507113290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1507113290
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.320667971
Short name T229
Test name
Test status
Simulation time 476943798 ps
CPU time 5.32 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 217560 kb
Host smart-20890f8f-e569-4338-ac5e-66f3a61fb0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320667971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.320667971
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.13683834
Short name T214
Test name
Test status
Simulation time 10147468595 ps
CPU time 251.36 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:29:21 PM PDT 24
Peak memory 217856 kb
Host smart-f6410cc3-c5cb-4133-b1e8-7cc9fc0e43f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13683834 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.13683834
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.356464705
Short name T11
Test name
Test status
Simulation time 46758974 ps
CPU time 1.15 seconds
Started Jul 04 06:26:41 PM PDT 24
Finished Jul 04 06:26:43 PM PDT 24
Peak memory 218780 kb
Host smart-c7da5c57-fafd-4d99-9da0-a933ee8515ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356464705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.356464705
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.251543528
Short name T319
Test name
Test status
Simulation time 64314978 ps
CPU time 1.49 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 219076 kb
Host smart-161b9b8f-c9ca-4ebd-a90e-0cd1a18d51fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251543528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.251543528
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3938360526
Short name T165
Test name
Test status
Simulation time 361276225 ps
CPU time 1.23 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 220624 kb
Host smart-b281e98f-a69f-4b3f-834c-a7a5324c76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938360526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3938360526
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2911934547
Short name T358
Test name
Test status
Simulation time 97523752 ps
CPU time 1.03 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 217784 kb
Host smart-345fa936-53ee-4061-a307-33c8eacd720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911934547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2911934547
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2438734812
Short name T75
Test name
Test status
Simulation time 90880958 ps
CPU time 1.24 seconds
Started Jul 04 06:26:45 PM PDT 24
Finished Jul 04 06:26:47 PM PDT 24
Peak memory 215972 kb
Host smart-0a6c3383-cfff-4ab6-8d43-8c78a571a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438734812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2438734812
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3047107631
Short name T947
Test name
Test status
Simulation time 101484623 ps
CPU time 1.45 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 220780 kb
Host smart-188d01ea-544d-4d97-b9fa-3c49fcd4b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047107631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3047107631
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1171154091
Short name T665
Test name
Test status
Simulation time 100736080 ps
CPU time 1.13 seconds
Started Jul 04 06:26:38 PM PDT 24
Finished Jul 04 06:26:40 PM PDT 24
Peak memory 220192 kb
Host smart-a7b8a216-309e-4cea-a25a-409c666620bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171154091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1171154091
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.293264135
Short name T755
Test name
Test status
Simulation time 60122050 ps
CPU time 1.82 seconds
Started Jul 04 06:26:46 PM PDT 24
Finished Jul 04 06:26:48 PM PDT 24
Peak memory 218696 kb
Host smart-05a0ade0-2dc9-4833-aa76-5c1699beaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293264135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.293264135
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.93353467
Short name T207
Test name
Test status
Simulation time 78518620 ps
CPU time 1.19 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 219832 kb
Host smart-d286c4cb-ca5e-449b-8bac-cfa58162216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93353467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.93353467
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3290857356
Short name T826
Test name
Test status
Simulation time 85610031 ps
CPU time 1.28 seconds
Started Jul 04 06:26:40 PM PDT 24
Finished Jul 04 06:26:41 PM PDT 24
Peak memory 219300 kb
Host smart-c061eb8c-7e6f-4491-bc50-9e7a84c2b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290857356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3290857356
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2099124301
Short name T944
Test name
Test status
Simulation time 30412452 ps
CPU time 1.27 seconds
Started Jul 04 06:26:43 PM PDT 24
Finished Jul 04 06:26:44 PM PDT 24
Peak memory 218908 kb
Host smart-d30880dd-f719-4300-83d4-b59d53ceed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099124301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2099124301
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2822546431
Short name T438
Test name
Test status
Simulation time 66686295 ps
CPU time 1.37 seconds
Started Jul 04 06:26:43 PM PDT 24
Finished Jul 04 06:26:45 PM PDT 24
Peak memory 220188 kb
Host smart-c38e5440-7e7f-4385-aec8-dcd748dd5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822546431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2822546431
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3446040052
Short name T994
Test name
Test status
Simulation time 68268480 ps
CPU time 1.21 seconds
Started Jul 04 06:26:39 PM PDT 24
Finished Jul 04 06:26:41 PM PDT 24
Peak memory 218808 kb
Host smart-e2daae1b-2ad0-4639-bd11-85040a0c9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446040052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3446040052
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.4266194595
Short name T608
Test name
Test status
Simulation time 57805910 ps
CPU time 2.05 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:58 PM PDT 24
Peak memory 218740 kb
Host smart-50a68359-b704-4fa6-adbb-69f09122e328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266194595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4266194595
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3727818035
Short name T436
Test name
Test status
Simulation time 93284396 ps
CPU time 1.23 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 215976 kb
Host smart-cdde03a9-caa6-4f0a-9719-89525130618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727818035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3727818035
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1408850373
Short name T706
Test name
Test status
Simulation time 24167225 ps
CPU time 1.16 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 217740 kb
Host smart-1230ce6b-8eef-44dd-af7a-160bd72c5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408850373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1408850373
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3494033188
Short name T549
Test name
Test status
Simulation time 81387624 ps
CPU time 1.12 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 220980 kb
Host smart-e8c33153-21a3-4a59-9def-499352df2ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494033188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3494033188
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2535359327
Short name T876
Test name
Test status
Simulation time 117933556 ps
CPU time 1.33 seconds
Started Jul 04 06:26:39 PM PDT 24
Finished Jul 04 06:26:41 PM PDT 24
Peak memory 219016 kb
Host smart-4a68c024-8438-49d4-8356-5c055aa5f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535359327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2535359327
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2372033134
Short name T652
Test name
Test status
Simulation time 47316015 ps
CPU time 1.09 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 220128 kb
Host smart-eb1fb217-8080-45e2-9817-bf333cc09db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372033134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2372033134
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3165473086
Short name T439
Test name
Test status
Simulation time 25459659 ps
CPU time 1.14 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 220072 kb
Host smart-b49f7bcb-8f48-4362-bd57-3969f453aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165473086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3165473086
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.704442218
Short name T642
Test name
Test status
Simulation time 57972698 ps
CPU time 0.84 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 207048 kb
Host smart-a030e406-7564-45b0-bce0-36e016398725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704442218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.704442218
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.296030363
Short name T610
Test name
Test status
Simulation time 23385929 ps
CPU time 0.88 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 216552 kb
Host smart-ae5e5135-be09-47b0-96fc-f35be3adcf21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296030363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.296030363
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1165835042
Short name T139
Test name
Test status
Simulation time 130725429 ps
CPU time 1.14 seconds
Started Jul 04 06:25:29 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 217100 kb
Host smart-ae4eff48-9316-46e6-a715-0e31bd46e763
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165835042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1165835042
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4054810181
Short name T946
Test name
Test status
Simulation time 19843853 ps
CPU time 1.08 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 218856 kb
Host smart-3a4f99b1-0446-4c27-9648-85a8c275a9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054810181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4054810181
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1709075626
Short name T571
Test name
Test status
Simulation time 83089102 ps
CPU time 2.79 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 220144 kb
Host smart-47f33a3c-d47a-4b8e-8dd9-edcb9b1b4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709075626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1709075626
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3659343192
Short name T345
Test name
Test status
Simulation time 31016982 ps
CPU time 0.85 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 215544 kb
Host smart-5a93a5d4-f012-40c6-be96-984095031377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659343192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3659343192
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2932871005
Short name T464
Test name
Test status
Simulation time 24076449 ps
CPU time 0.9 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 215632 kb
Host smart-b7b10c0a-906a-471a-b927-375bf2b15f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932871005 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2932871005
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3516844260
Short name T818
Test name
Test status
Simulation time 23185898 ps
CPU time 1.01 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 206828 kb
Host smart-e931451b-83f0-4b0b-bf0a-a2cde0b95899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516844260 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3516844260
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.477639767
Short name T223
Test name
Test status
Simulation time 135333236183 ps
CPU time 1476.48 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:49:46 PM PDT 24
Peak memory 224312 kb
Host smart-302ed22d-6349-48c9-8007-33ea5d03f071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477639767 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.477639767
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1467560579
Short name T951
Test name
Test status
Simulation time 195774701 ps
CPU time 1.25 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:38 PM PDT 24
Peak memory 220788 kb
Host smart-deb2306f-c9b6-47db-8581-0156adc1b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467560579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1467560579
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.720113731
Short name T366
Test name
Test status
Simulation time 55448962 ps
CPU time 1.8 seconds
Started Jul 04 06:26:43 PM PDT 24
Finished Jul 04 06:26:45 PM PDT 24
Peak memory 220036 kb
Host smart-044956fa-61a4-4f3d-82bb-10eb47654280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720113731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.720113731
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.125305661
Short name T80
Test name
Test status
Simulation time 93969806 ps
CPU time 1.27 seconds
Started Jul 04 06:26:37 PM PDT 24
Finished Jul 04 06:26:39 PM PDT 24
Peak memory 220204 kb
Host smart-c2490151-8f5c-4cfe-8119-0f301e38a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125305661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.125305661
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.4165116593
Short name T924
Test name
Test status
Simulation time 61106596 ps
CPU time 1.37 seconds
Started Jul 04 06:26:45 PM PDT 24
Finished Jul 04 06:26:47 PM PDT 24
Peak memory 218836 kb
Host smart-3332407d-d0b8-40ee-ba6e-d6dc92c8fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165116593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4165116593
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3464748565
Short name T442
Test name
Test status
Simulation time 30018764 ps
CPU time 1.27 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 216032 kb
Host smart-ac20ecd4-4c69-46e4-b344-8c761b350a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464748565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3464748565
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4076243974
Short name T943
Test name
Test status
Simulation time 177951058 ps
CPU time 2.99 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 220508 kb
Host smart-2396141e-15a5-47cb-809b-f1d08bb23228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076243974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4076243974
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2284865480
Short name T663
Test name
Test status
Simulation time 22882939 ps
CPU time 1.13 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 220868 kb
Host smart-540830ca-c73b-469e-8238-1671c5ff2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284865480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2284865480
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.977555722
Short name T836
Test name
Test status
Simulation time 55200723 ps
CPU time 1.2 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 217716 kb
Host smart-0e3e2b52-b56c-4bb4-ba04-35c719c382d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977555722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.977555722
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2762679310
Short name T463
Test name
Test status
Simulation time 78352102 ps
CPU time 1.14 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 220988 kb
Host smart-82d44067-ba94-4531-b69e-b012cccef95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762679310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2762679310
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.4282506525
Short name T582
Test name
Test status
Simulation time 29931117 ps
CPU time 1.09 seconds
Started Jul 04 06:26:44 PM PDT 24
Finished Jul 04 06:26:46 PM PDT 24
Peak memory 217716 kb
Host smart-93b252b3-1e23-4a07-a648-57f072fff5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282506525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4282506525
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3151274162
Short name T544
Test name
Test status
Simulation time 46913666 ps
CPU time 1.2 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 218896 kb
Host smart-f84f5ff6-8f65-499d-a29a-3c57b061d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151274162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3151274162
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.917489082
Short name T950
Test name
Test status
Simulation time 111333396 ps
CPU time 1.31 seconds
Started Jul 04 06:26:46 PM PDT 24
Finished Jul 04 06:26:47 PM PDT 24
Peak memory 218948 kb
Host smart-01f33602-5ff0-4640-8039-6d15abccd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917489082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.917489082
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3241326233
Short name T874
Test name
Test status
Simulation time 85073786 ps
CPU time 1.16 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 218900 kb
Host smart-dbcda840-574c-47d4-bece-d9bb0aad84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241326233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3241326233
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1932994565
Short name T971
Test name
Test status
Simulation time 105196744 ps
CPU time 1.51 seconds
Started Jul 04 06:26:46 PM PDT 24
Finished Jul 04 06:26:48 PM PDT 24
Peak memory 219096 kb
Host smart-f01a557d-0b2f-4922-af78-6f33a29c3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932994565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1932994565
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.292548333
Short name T677
Test name
Test status
Simulation time 25958332 ps
CPU time 1.19 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219116 kb
Host smart-6286d06a-2fde-4331-98c0-02997d30c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292548333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.292548333
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.446993111
Short name T504
Test name
Test status
Simulation time 17966834 ps
CPU time 1.15 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 220176 kb
Host smart-8189428a-0440-42a1-9134-159de5a89d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446993111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.446993111
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2282903628
Short name T180
Test name
Test status
Simulation time 69194163 ps
CPU time 1.08 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 220976 kb
Host smart-8131be6e-3bd2-47cd-b3d2-d0a16f2ce46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282903628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2282903628
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2210854467
Short name T82
Test name
Test status
Simulation time 50212139 ps
CPU time 1.64 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 218852 kb
Host smart-3fe501c2-98ad-476a-b62e-71967c23a1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210854467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2210854467
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2575849665
Short name T883
Test name
Test status
Simulation time 53987322 ps
CPU time 1.47 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 218736 kb
Host smart-51ef18bf-2bf7-4a4c-bbd5-2f216bb12f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575849665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2575849665
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3011999864
Short name T748
Test name
Test status
Simulation time 26329775 ps
CPU time 1.25 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 216004 kb
Host smart-72143e09-fea3-4620-b6bf-5bb795440534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011999864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3011999864
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3890364432
Short name T778
Test name
Test status
Simulation time 15483606 ps
CPU time 0.94 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 207012 kb
Host smart-5763e10a-f7ec-4423-8547-7a66ff2573d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890364432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3890364432
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2412527921
Short name T341
Test name
Test status
Simulation time 16480914 ps
CPU time 0.85 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 216276 kb
Host smart-d7cf5789-ee8b-4440-aa0a-11146bb25a8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412527921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2412527921
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1846480765
Short name T142
Test name
Test status
Simulation time 38918030 ps
CPU time 1.26 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 217148 kb
Host smart-f0ac2395-e986-4e95-aff7-bf1f294d2a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846480765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1846480765
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1877762496
Short name T489
Test name
Test status
Simulation time 28884061 ps
CPU time 1.23 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 224268 kb
Host smart-9b158cf7-fb5a-4579-835c-a507393d5e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877762496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1877762496
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1268844981
Short name T332
Test name
Test status
Simulation time 103720135 ps
CPU time 1.67 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 220484 kb
Host smart-12676572-785b-4e88-ad64-5cd272999114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268844981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1268844981
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2777541125
Short name T758
Test name
Test status
Simulation time 30200991 ps
CPU time 0.87 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 216356 kb
Host smart-2fe30dc4-692e-493a-afa4-680ee38a78f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777541125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2777541125
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3149056955
Short name T743
Test name
Test status
Simulation time 29942630 ps
CPU time 0.92 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 215548 kb
Host smart-62c11803-b2cc-4c1b-aca9-c1ff9ad1932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149056955 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3149056955
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3481637925
Short name T852
Test name
Test status
Simulation time 114576207 ps
CPU time 2.74 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 215580 kb
Host smart-fbe726ca-fdd2-49bf-b036-70463d6380f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481637925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3481637925
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3291673915
Short name T578
Test name
Test status
Simulation time 62954088618 ps
CPU time 734.94 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:37:26 PM PDT 24
Peak memory 219100 kb
Host smart-2d0b37cf-36e7-4087-9516-dd672f5ac996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291673915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3291673915
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3959077954
Short name T520
Test name
Test status
Simulation time 64251019 ps
CPU time 1.12 seconds
Started Jul 04 06:26:46 PM PDT 24
Finished Jul 04 06:26:47 PM PDT 24
Peak memory 219616 kb
Host smart-4273bf06-8c68-426e-bd18-74c0eca85aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959077954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3959077954
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3672757944
Short name T613
Test name
Test status
Simulation time 105269898 ps
CPU time 1.48 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:04 PM PDT 24
Peak memory 219244 kb
Host smart-d35bb99c-470b-47bb-8d05-2647940a192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672757944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3672757944
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3130602389
Short name T551
Test name
Test status
Simulation time 44032205 ps
CPU time 1.24 seconds
Started Jul 04 06:26:43 PM PDT 24
Finished Jul 04 06:26:44 PM PDT 24
Peak memory 219100 kb
Host smart-6efbc2ae-206a-474f-8d1f-66f6092905bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130602389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3130602389
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2962986462
Short name T668
Test name
Test status
Simulation time 289284673 ps
CPU time 1.37 seconds
Started Jul 04 06:26:35 PM PDT 24
Finished Jul 04 06:26:37 PM PDT 24
Peak memory 219348 kb
Host smart-ef16647d-74e2-4647-adda-57f9efe9c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962986462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2962986462
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.738819659
Short name T206
Test name
Test status
Simulation time 73109303 ps
CPU time 1.24 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 221156 kb
Host smart-f0f21a58-dcaa-4143-ba9b-f6ba854df8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738819659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.738819659
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.2762646563
Short name T235
Test name
Test status
Simulation time 63585514 ps
CPU time 1.37 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 215984 kb
Host smart-2298f2a0-5439-4e88-b8c9-a43135580e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762646563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2762646563
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.898312408
Short name T435
Test name
Test status
Simulation time 64954730 ps
CPU time 1.37 seconds
Started Jul 04 06:26:39 PM PDT 24
Finished Jul 04 06:26:41 PM PDT 24
Peak memory 218936 kb
Host smart-329c9800-79f5-4f66-bb6f-b707f04dfa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898312408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.898312408
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2288637744
Short name T444
Test name
Test status
Simulation time 26878396 ps
CPU time 1.3 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219716 kb
Host smart-c41e7d7b-6383-4f50-8a28-04ad4dde202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288637744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2288637744
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.4055039709
Short name T415
Test name
Test status
Simulation time 37097836 ps
CPU time 1.53 seconds
Started Jul 04 06:27:06 PM PDT 24
Finished Jul 04 06:27:08 PM PDT 24
Peak memory 218668 kb
Host smart-12070564-b43b-4c49-a10e-11077ea3d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055039709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4055039709
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2936601940
Short name T930
Test name
Test status
Simulation time 38414247 ps
CPU time 1.07 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 218916 kb
Host smart-03cfa9b5-5450-468b-944b-1d87cbebdbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936601940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2936601940
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2764930557
Short name T745
Test name
Test status
Simulation time 87693410 ps
CPU time 1.08 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:27:06 PM PDT 24
Peak memory 217516 kb
Host smart-56bdaa88-d449-4387-b9b3-08b36f038cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764930557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2764930557
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1717965146
Short name T567
Test name
Test status
Simulation time 59611321 ps
CPU time 2.15 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 220216 kb
Host smart-24ef9fb2-e956-45f7-935b-a8f37f334b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717965146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1717965146
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1318259809
Short name T869
Test name
Test status
Simulation time 68185461 ps
CPU time 1.16 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 219692 kb
Host smart-cefcc86c-25c0-4ee7-97b8-7713a4793a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318259809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1318259809
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2962348664
Short name T275
Test name
Test status
Simulation time 105822222 ps
CPU time 1.34 seconds
Started Jul 04 06:26:45 PM PDT 24
Finished Jul 04 06:26:46 PM PDT 24
Peak memory 219276 kb
Host smart-169b9285-d75d-4759-adba-bc3bbe9c98c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962348664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2962348664
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1721912296
Short name T443
Test name
Test status
Simulation time 25517305 ps
CPU time 1.2 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 215952 kb
Host smart-6d70bbef-72ae-415a-9bf5-2a7a9b7967fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721912296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1721912296
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/189.edn_alert.2916740899
Short name T530
Test name
Test status
Simulation time 99253808 ps
CPU time 1.24 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 218860 kb
Host smart-09b15e6a-16f5-43a5-8471-8f666f529bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916740899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2916740899
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.4024254836
Short name T561
Test name
Test status
Simulation time 35257924 ps
CPU time 1.57 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 217808 kb
Host smart-168e1944-f82a-4bdd-8492-f4b7cb034e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024254836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4024254836
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.854027431
Short name T843
Test name
Test status
Simulation time 25339162 ps
CPU time 1.21 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 218912 kb
Host smart-7d3a80c8-ac90-4995-9522-50d228fe8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854027431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.854027431
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3419157933
Short name T787
Test name
Test status
Simulation time 110684624 ps
CPU time 0.98 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 207068 kb
Host smart-1f20c7eb-8b8e-488e-a8cf-4c94a15e8c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419157933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3419157933
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2753012670
Short name T816
Test name
Test status
Simulation time 39474670 ps
CPU time 0.89 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 216224 kb
Host smart-4fc10b38-5898-4586-9bec-f817cf8d6f17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753012670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2753012670
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2573485987
Short name T130
Test name
Test status
Simulation time 24806971 ps
CPU time 1.14 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 218728 kb
Host smart-eff346ec-4454-43b5-beae-75968cee9437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573485987 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2573485987
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.471307084
Short name T767
Test name
Test status
Simulation time 48188947 ps
CPU time 0.97 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 220036 kb
Host smart-a536d688-4520-436d-8b2a-d36138b0d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471307084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.471307084
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2044273974
Short name T538
Test name
Test status
Simulation time 106148220 ps
CPU time 2.36 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 219712 kb
Host smart-a24a3c38-d9dc-4eaa-99ca-e1c9b5210120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044273974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2044273974
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2669316127
Short name T107
Test name
Test status
Simulation time 87355566 ps
CPU time 0.82 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 215824 kb
Host smart-43199cfe-d9fa-4818-aa91-b47e58a4c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669316127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2669316127
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1544246768
Short name T355
Test name
Test status
Simulation time 31859639 ps
CPU time 0.92 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 215636 kb
Host smart-8b94d3a3-2717-421f-bb1a-5d68d6e41ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544246768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1544246768
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1189442090
Short name T800
Test name
Test status
Simulation time 794293253 ps
CPU time 5.17 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 217740 kb
Host smart-bdddbd82-e61a-49b8-94e2-8b04677fe903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189442090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1189442090
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2382209906
Short name T749
Test name
Test status
Simulation time 89233650850 ps
CPU time 1076.44 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 223112 kb
Host smart-44e99ce0-63eb-4a9b-a617-a04d9302db7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382209906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2382209906
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1270819876
Short name T205
Test name
Test status
Simulation time 42968135 ps
CPU time 1.15 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219036 kb
Host smart-3cab1309-721b-416d-81e2-3ec46438c7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270819876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1270819876
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.4011574490
Short name T647
Test name
Test status
Simulation time 148846739 ps
CPU time 3.2 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 220592 kb
Host smart-ae86367d-7ee1-4a37-a0c9-4c18b070bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011574490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4011574490
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2027319263
Short name T498
Test name
Test status
Simulation time 69950434 ps
CPU time 1.32 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 218836 kb
Host smart-8b399595-27bd-491c-91e8-8cafa77cb8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027319263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2027319263
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3413088590
Short name T547
Test name
Test status
Simulation time 83175814 ps
CPU time 1.35 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 219252 kb
Host smart-3ecb150d-6dcc-4cdb-a5fe-4f98a5ce5a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413088590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3413088590
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2482661822
Short name T411
Test name
Test status
Simulation time 267527148 ps
CPU time 1.41 seconds
Started Jul 04 06:26:46 PM PDT 24
Finished Jul 04 06:26:48 PM PDT 24
Peak memory 219924 kb
Host smart-007eb4dc-6325-4fd2-abe6-f877db58193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482661822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2482661822
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3244045957
Short name T320
Test name
Test status
Simulation time 115798505 ps
CPU time 1.71 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 219316 kb
Host smart-e857ea96-02cf-4772-afbd-a0937ad601ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244045957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3244045957
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2013109715
Short name T88
Test name
Test status
Simulation time 30087894 ps
CPU time 1.29 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 219444 kb
Host smart-11e1a632-22db-4aee-9fb9-3d64c164238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013109715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2013109715
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3882409793
Short name T565
Test name
Test status
Simulation time 165884673 ps
CPU time 2.41 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 218052 kb
Host smart-99568f1c-2783-4f86-ab7e-f24e055c872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882409793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3882409793
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.4031234869
Short name T726
Test name
Test status
Simulation time 85198373 ps
CPU time 1.07 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:48 PM PDT 24
Peak memory 219328 kb
Host smart-5ecf820e-cf2a-4356-9883-8804cf40fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031234869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.4031234869
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2700032676
Short name T614
Test name
Test status
Simulation time 99011534 ps
CPU time 1.43 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 219112 kb
Host smart-2b790435-23f8-4e27-bf2c-9a0709a315f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700032676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2700032676
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3913610116
Short name T502
Test name
Test status
Simulation time 55498343 ps
CPU time 1.66 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 218936 kb
Host smart-43ce4e36-7c0f-4506-bb6e-44dfddb8c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913610116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3913610116
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.826863406
Short name T901
Test name
Test status
Simulation time 32757185 ps
CPU time 1.14 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 218788 kb
Host smart-a7d9d874-7642-42ac-98df-e0430bbca99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826863406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.826863406
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3297392311
Short name T854
Test name
Test status
Simulation time 64943853 ps
CPU time 1.91 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 218168 kb
Host smart-e9b676bd-7614-48d7-9acc-76bc5a7a9835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297392311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3297392311
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4006373133
Short name T957
Test name
Test status
Simulation time 50468004 ps
CPU time 1.98 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 218092 kb
Host smart-cc425142-a7d0-4ae2-8cc1-05b13f7b4440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006373133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4006373133
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.4119753491
Short name T844
Test name
Test status
Simulation time 39849511 ps
CPU time 1.16 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 220780 kb
Host smart-c1e66238-4462-4fbe-8527-3688f8264379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119753491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.4119753491
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2463496805
Short name T515
Test name
Test status
Simulation time 43015223 ps
CPU time 1.08 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 217572 kb
Host smart-99ec2389-3571-4f71-bb47-58f177b9b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463496805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2463496805
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.550901576
Short name T135
Test name
Test status
Simulation time 48531767 ps
CPU time 1.21 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 220236 kb
Host smart-b5ca6d24-83e9-4c58-81fb-0149f9ef68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550901576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.550901576
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2046126630
Short name T357
Test name
Test status
Simulation time 131289633 ps
CPU time 1.23 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 217792 kb
Host smart-55b9419b-2d35-44be-bb5d-65d6199b8020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046126630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2046126630
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4110631976
Short name T681
Test name
Test status
Simulation time 83749028 ps
CPU time 1.22 seconds
Started Jul 04 06:25:01 PM PDT 24
Finished Jul 04 06:25:03 PM PDT 24
Peak memory 218652 kb
Host smart-908fdc24-9c6d-4a70-9d87-8988d53f323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110631976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4110631976
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.396299591
Short name T47
Test name
Test status
Simulation time 20551824 ps
CPU time 0.88 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 207004 kb
Host smart-cd2d776d-8577-4677-a898-093dd0592127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396299591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.396299591
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.477968316
Short name T920
Test name
Test status
Simulation time 32396690 ps
CPU time 0.88 seconds
Started Jul 04 06:24:38 PM PDT 24
Finished Jul 04 06:24:39 PM PDT 24
Peak memory 215732 kb
Host smart-932309a5-659e-47b6-a99b-d11a37d384d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477968316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.477968316
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1057458406
Short name T268
Test name
Test status
Simulation time 39253825 ps
CPU time 1.01 seconds
Started Jul 04 06:25:01 PM PDT 24
Finished Jul 04 06:25:03 PM PDT 24
Peak memory 218720 kb
Host smart-88cd7079-c4fb-4d6a-b6e4-c4da99c77445
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057458406 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1057458406
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.606481994
Short name T55
Test name
Test status
Simulation time 65121868 ps
CPU time 1.12 seconds
Started Jul 04 06:24:32 PM PDT 24
Finished Jul 04 06:24:33 PM PDT 24
Peak memory 217624 kb
Host smart-74b2b665-8acd-4227-97d0-32edb2ff3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606481994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.606481994
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.104634044
Short name T48
Test name
Test status
Simulation time 67013021 ps
CPU time 0.93 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 224172 kb
Host smart-3bb68ec1-7d84-4a40-8e0a-17ea568a3445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104634044 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.104634044
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1413612494
Short name T539
Test name
Test status
Simulation time 36618952 ps
CPU time 0.91 seconds
Started Jul 04 06:24:45 PM PDT 24
Finished Jul 04 06:24:46 PM PDT 24
Peak memory 207456 kb
Host smart-322c3cb0-d3b4-4b65-9208-983aae5ea9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413612494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1413612494
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2423894560
Short name T56
Test name
Test status
Simulation time 875124973 ps
CPU time 4.15 seconds
Started Jul 04 06:25:01 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 235500 kb
Host smart-c2d39a0e-2c42-41ec-8d57-de762d693947
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423894560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2423894560
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1002743376
Short name T418
Test name
Test status
Simulation time 52489210 ps
CPU time 0.88 seconds
Started Jul 04 06:24:33 PM PDT 24
Finished Jul 04 06:24:34 PM PDT 24
Peak memory 215596 kb
Host smart-f744fcb0-5e52-47a3-b83d-ec6d023a26e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002743376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1002743376
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.436092232
Short name T918
Test name
Test status
Simulation time 108928189 ps
CPU time 2.74 seconds
Started Jul 04 06:24:50 PM PDT 24
Finished Jul 04 06:24:53 PM PDT 24
Peak memory 215636 kb
Host smart-c35fe6a6-6f0c-4e02-a423-b9c2c89e3543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436092232 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.436092232
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2982148686
Short name T221
Test name
Test status
Simulation time 51127056650 ps
CPU time 1117.19 seconds
Started Jul 04 06:24:54 PM PDT 24
Finished Jul 04 06:43:31 PM PDT 24
Peak memory 224132 kb
Host smart-0fbcfcf5-8697-4334-904f-8079cc775161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982148686 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2982148686
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1033668278
Short name T545
Test name
Test status
Simulation time 95123781 ps
CPU time 1.08 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 218752 kb
Host smart-12f7b6ed-f893-4b4b-b696-23f7bc6675ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033668278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1033668278
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3966013399
Short name T338
Test name
Test status
Simulation time 23841399 ps
CPU time 0.89 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 207040 kb
Host smart-bb6ca497-f14a-49d4-a2cd-2e1dc0ee51aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966013399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3966013399
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3493904835
Short name T163
Test name
Test status
Simulation time 28710338 ps
CPU time 0.86 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 216492 kb
Host smart-6b2e1522-1603-47b1-b697-529b439b690d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493904835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3493904835
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2427056222
Short name T200
Test name
Test status
Simulation time 187808147 ps
CPU time 1.17 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 217300 kb
Host smart-33604c3b-3ab0-4d5e-9c95-bb78d5c47e82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427056222 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2427056222
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3366687541
Short name T819
Test name
Test status
Simulation time 34073282 ps
CPU time 0.9 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 220132 kb
Host smart-1a11614b-369e-450e-89c4-bf70aefe58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366687541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3366687541
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.222382397
Short name T630
Test name
Test status
Simulation time 64070810 ps
CPU time 1.33 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 220400 kb
Host smart-240e6446-8b7b-431c-bca9-43faa8a69a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222382397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.222382397
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2632765931
Short name T659
Test name
Test status
Simulation time 22229878 ps
CPU time 1.06 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 216128 kb
Host smart-37d54f42-77bd-42b1-894b-c3cb9babf524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632765931 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2632765931
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.57118349
Short name T336
Test name
Test status
Simulation time 26442248 ps
CPU time 0.96 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 215588 kb
Host smart-acff21ac-38e3-45e1-b357-ba66562a7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57118349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.57118349
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1737065750
Short name T700
Test name
Test status
Simulation time 82636704 ps
CPU time 1.14 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 217560 kb
Host smart-dbcf4d30-206c-4603-8a69-033592fbfb6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737065750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1737065750
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3846212957
Short name T400
Test name
Test status
Simulation time 71858168017 ps
CPU time 905.91 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:40:19 PM PDT 24
Peak memory 223984 kb
Host smart-e89e9229-fab9-40f9-9d19-e5717c20d3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846212957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3846212957
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3264397104
Short name T76
Test name
Test status
Simulation time 86234304 ps
CPU time 1.73 seconds
Started Jul 04 06:26:51 PM PDT 24
Finished Jul 04 06:26:53 PM PDT 24
Peak memory 219336 kb
Host smart-3f989276-8aed-4590-9a4e-7d1534c0209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264397104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3264397104
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2470277824
Short name T364
Test name
Test status
Simulation time 65084622 ps
CPU time 0.96 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 217520 kb
Host smart-f93b6da7-c46a-43af-8448-d8de3a9f0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470277824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2470277824
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2601618503
Short name T962
Test name
Test status
Simulation time 50402404 ps
CPU time 1.06 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 217568 kb
Host smart-4b0b8f2b-c579-4e68-bad4-8191d992b649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601618503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2601618503
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2720765715
Short name T693
Test name
Test status
Simulation time 151610965 ps
CPU time 1.33 seconds
Started Jul 04 06:26:51 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 219116 kb
Host smart-811a030d-9ebf-4d9b-bcfb-68940877c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720765715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2720765715
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3678870131
Short name T389
Test name
Test status
Simulation time 31186791 ps
CPU time 1.04 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 217588 kb
Host smart-813af6e8-e415-4a4d-9e9e-c76837f3efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678870131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3678870131
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3886469004
Short name T762
Test name
Test status
Simulation time 73616832 ps
CPU time 1.15 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 217500 kb
Host smart-25f6097c-12e3-45c3-9a28-826283d41aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886469004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3886469004
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.78939893
Short name T835
Test name
Test status
Simulation time 68689735 ps
CPU time 1.19 seconds
Started Jul 04 06:27:10 PM PDT 24
Finished Jul 04 06:27:11 PM PDT 24
Peak memory 218928 kb
Host smart-dd8f7dbc-72fd-47d2-88f4-e0c414d80d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78939893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.78939893
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.90371169
Short name T893
Test name
Test status
Simulation time 51374100 ps
CPU time 1.07 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:58 PM PDT 24
Peak memory 217656 kb
Host smart-f82fb3e8-bf78-4049-a210-b15be9f32681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90371169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.90371169
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3046964595
Short name T779
Test name
Test status
Simulation time 51911043 ps
CPU time 0.96 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:58 PM PDT 24
Peak memory 217620 kb
Host smart-61abaf7d-d123-453c-a87f-b7fdd4733f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046964595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3046964595
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1039857980
Short name T509
Test name
Test status
Simulation time 42652646 ps
CPU time 1.06 seconds
Started Jul 04 06:27:09 PM PDT 24
Finished Jul 04 06:27:10 PM PDT 24
Peak memory 220060 kb
Host smart-33b85652-a93f-4de0-8cc1-212ff428657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039857980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1039857980
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.881897925
Short name T405
Test name
Test status
Simulation time 28269980 ps
CPU time 1.23 seconds
Started Jul 04 06:25:47 PM PDT 24
Finished Jul 04 06:25:48 PM PDT 24
Peak memory 220304 kb
Host smart-dcbbbc46-dc15-4622-b312-0556dde37f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881897925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.881897925
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1652032717
Short name T738
Test name
Test status
Simulation time 35781343 ps
CPU time 0.99 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 215268 kb
Host smart-f7233745-a642-4f27-9515-4e6a8cae9b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652032717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1652032717
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3463790044
Short name T669
Test name
Test status
Simulation time 23731632 ps
CPU time 0.87 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 216624 kb
Host smart-df902bfb-8d53-499e-a272-0b55f1b1c756
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463790044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3463790044
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.578671229
Short name T912
Test name
Test status
Simulation time 60928680 ps
CPU time 0.99 seconds
Started Jul 04 06:25:43 PM PDT 24
Finished Jul 04 06:25:44 PM PDT 24
Peak memory 218956 kb
Host smart-0b97cc52-7338-4988-9437-947a49804a13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578671229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.578671229
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1308543847
Short name T827
Test name
Test status
Simulation time 20152841 ps
CPU time 1.15 seconds
Started Jul 04 06:25:29 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 224268 kb
Host smart-1694262f-9fbe-4748-bbc6-c1b02dbb191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308543847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1308543847
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2939149912
Short name T45
Test name
Test status
Simulation time 35393034 ps
CPU time 1.32 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 218916 kb
Host smart-ca5c93a7-80c5-434a-ab15-85e4249f9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939149912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2939149912
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.405859705
Short name T860
Test name
Test status
Simulation time 23638938 ps
CPU time 0.98 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 216216 kb
Host smart-231bae1c-7eb8-437d-bb34-ae03b61d6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405859705 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.405859705
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3351262366
Short name T688
Test name
Test status
Simulation time 25815672 ps
CPU time 0.92 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 207404 kb
Host smart-83d10712-cb9e-471c-8655-de10f205af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351262366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3351262366
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2940220906
Short name T460
Test name
Test status
Simulation time 234062163 ps
CPU time 1.7 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 215600 kb
Host smart-d457f4f4-f99d-4d2a-8dc8-98e382974042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940220906 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2940220906
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3017991933
Short name T224
Test name
Test status
Simulation time 73518722673 ps
CPU time 427.19 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:32:25 PM PDT 24
Peak memory 218220 kb
Host smart-dc5d2bde-5fe0-43fc-a4bf-c53a0bbecfd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017991933 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3017991933
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3765902082
Short name T469
Test name
Test status
Simulation time 60735419 ps
CPU time 2.07 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 218856 kb
Host smart-9dd0e35a-2043-4956-a83a-afbaa8a00b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765902082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3765902082
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.939130424
Short name T990
Test name
Test status
Simulation time 38822254 ps
CPU time 1.11 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 217776 kb
Host smart-b034d63e-a656-4180-9d51-c3555ed7258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939130424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.939130424
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3623394665
Short name T703
Test name
Test status
Simulation time 45682034 ps
CPU time 1.55 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 218772 kb
Host smart-c91fff18-96b9-45f4-82b0-e18f69cec9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623394665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3623394665
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.695364959
Short name T446
Test name
Test status
Simulation time 69989337 ps
CPU time 1.12 seconds
Started Jul 04 06:26:48 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 220180 kb
Host smart-e09f3ebd-0ea1-4dd1-82b9-867120b62ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695364959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.695364959
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.89969906
Short name T14
Test name
Test status
Simulation time 111970379 ps
CPU time 1.48 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 220608 kb
Host smart-bbe46b3e-5429-41d1-8553-100b12e4b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89969906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.89969906
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3363897869
Short name T617
Test name
Test status
Simulation time 26207916 ps
CPU time 1.22 seconds
Started Jul 04 06:27:03 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 220136 kb
Host smart-62828e65-16c5-4fa7-8ebf-c9f22daa685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363897869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3363897869
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1084154331
Short name T584
Test name
Test status
Simulation time 38812344 ps
CPU time 1.35 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 220296 kb
Host smart-180dbc92-3381-4ae4-9c37-2520ebceab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084154331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1084154331
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1571884493
Short name T573
Test name
Test status
Simulation time 440719853 ps
CPU time 3.94 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 218808 kb
Host smart-03d2baa7-5ab8-4319-959c-34883197504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571884493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1571884493
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3741159927
Short name T948
Test name
Test status
Simulation time 49022257 ps
CPU time 1.94 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 219100 kb
Host smart-d3884e0f-8f39-4829-975a-a8ab21b19c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741159927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3741159927
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3953525505
Short name T333
Test name
Test status
Simulation time 67192692 ps
CPU time 2.45 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 220384 kb
Host smart-04836a4a-7db0-4428-bdd7-39550fa62afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953525505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3953525505
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1605068898
Short name T120
Test name
Test status
Simulation time 90405473 ps
CPU time 1.2 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 219924 kb
Host smart-573fc464-2805-4c10-80c0-a6bee51fe757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605068898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1605068898
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1676915973
Short name T620
Test name
Test status
Simulation time 41997422 ps
CPU time 0.86 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 215448 kb
Host smart-83550502-ddb1-46e5-b74a-7f241c34c648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676915973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1676915973
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3591528563
Short name T880
Test name
Test status
Simulation time 14097538 ps
CPU time 0.86 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 215668 kb
Host smart-9adb44bc-bd96-4f7e-857c-28154f986cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591528563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3591528563
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.81400010
Short name T657
Test name
Test status
Simulation time 67944634 ps
CPU time 1.14 seconds
Started Jul 04 06:25:37 PM PDT 24
Finished Jul 04 06:25:38 PM PDT 24
Peak memory 219800 kb
Host smart-a577bc82-3f21-4d65-ae06-1fab4e90aec3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81400010 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_dis
able_auto_req_mode.81400010
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2267629945
Short name T50
Test name
Test status
Simulation time 18178747 ps
CPU time 1.11 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 224228 kb
Host smart-6913178d-af6c-462a-aa8e-31328a13950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267629945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2267629945
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2332156639
Short name T914
Test name
Test status
Simulation time 101551162 ps
CPU time 1 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 217784 kb
Host smart-838fcafe-76a4-4acf-aa65-3cd96994ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332156639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2332156639
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.13443360
Short name T692
Test name
Test status
Simulation time 35966922 ps
CPU time 0.87 seconds
Started Jul 04 06:25:32 PM PDT 24
Finished Jul 04 06:25:33 PM PDT 24
Peak memory 215572 kb
Host smart-4c08f74a-3983-4be8-83e0-ad4f69c207b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13443360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.13443360
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3071416510
Short name T639
Test name
Test status
Simulation time 28485749 ps
CPU time 0.89 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 215632 kb
Host smart-72302312-553d-44a1-8202-ab13c5f52cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071416510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3071416510
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1250712914
Short name T187
Test name
Test status
Simulation time 626010134 ps
CPU time 4.11 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 215756 kb
Host smart-a93b96f0-bb18-47d2-9a22-17e1d662f18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250712914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1250712914
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4236361238
Short name T218
Test name
Test status
Simulation time 52372207591 ps
CPU time 445.43 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:32:37 PM PDT 24
Peak memory 224040 kb
Host smart-da9898aa-5c97-47d1-864b-a567ef03d5fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236361238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4236361238
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.756424321
Short name T830
Test name
Test status
Simulation time 51493647 ps
CPU time 1.33 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 218644 kb
Host smart-fe2439a3-b67b-48b8-a988-cbeff15c6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756424321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.756424321
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1519216086
Short name T609
Test name
Test status
Simulation time 57016495 ps
CPU time 1.73 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 218660 kb
Host smart-5e1f3735-e7e5-43cc-9887-26925bbbff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519216086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1519216086
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.916054420
Short name T643
Test name
Test status
Simulation time 54013696 ps
CPU time 1.3 seconds
Started Jul 04 06:27:05 PM PDT 24
Finished Jul 04 06:27:07 PM PDT 24
Peak memory 219604 kb
Host smart-1745ca55-5157-4721-a41e-29d15662f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916054420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.916054420
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1321016828
Short name T296
Test name
Test status
Simulation time 65104323 ps
CPU time 1.59 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 219116 kb
Host smart-b8e18cfe-4f4e-4cc5-ab73-31adad772f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321016828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1321016828
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1223279096
Short name T85
Test name
Test status
Simulation time 67220937 ps
CPU time 2.61 seconds
Started Jul 04 06:27:04 PM PDT 24
Finished Jul 04 06:27:07 PM PDT 24
Peak memory 220668 kb
Host smart-a7942747-8a18-4a3c-a214-a7923ee31d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223279096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1223279096
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2676487867
Short name T599
Test name
Test status
Simulation time 56073354 ps
CPU time 1.43 seconds
Started Jul 04 06:27:08 PM PDT 24
Finished Jul 04 06:27:10 PM PDT 24
Peak memory 220288 kb
Host smart-fe8751b0-7e5d-4169-b7f1-71a91f143a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676487867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2676487867
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1134324756
Short name T304
Test name
Test status
Simulation time 61242518 ps
CPU time 1.52 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:00 PM PDT 24
Peak memory 219132 kb
Host smart-4c7a3d30-50cc-426f-9795-1995e29c854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134324756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1134324756
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3622717693
Short name T580
Test name
Test status
Simulation time 99948459 ps
CPU time 1.03 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 217732 kb
Host smart-97bdbcae-e688-462c-a2f7-b8dc91448540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622717693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3622717693
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2236925371
Short name T601
Test name
Test status
Simulation time 32344070 ps
CPU time 1.17 seconds
Started Jul 04 06:27:05 PM PDT 24
Finished Jul 04 06:27:06 PM PDT 24
Peak memory 218772 kb
Host smart-645c6764-51e2-41a2-bf08-c847f4db2cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236925371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2236925371
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2132011769
Short name T646
Test name
Test status
Simulation time 26958995 ps
CPU time 1.14 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 218648 kb
Host smart-299588e4-94db-4123-93e8-d133708dc2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132011769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2132011769
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4240655
Short name T64
Test name
Test status
Simulation time 171387696 ps
CPU time 1.06 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:41 PM PDT 24
Peak memory 215204 kb
Host smart-9a15e236-ee5e-4e55-b022-f221c4f09495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4240655
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.152866514
Short name T503
Test name
Test status
Simulation time 16093290 ps
CPU time 0.87 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 216576 kb
Host smart-64a0e1bd-5452-4165-a81f-d77803db5a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152866514 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.152866514
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.3087129421
Short name T774
Test name
Test status
Simulation time 18239238 ps
CPU time 1.21 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:46 PM PDT 24
Peak memory 224268 kb
Host smart-8d3d3b67-31cf-4f06-935d-9352341bcbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087129421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3087129421
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3197544766
Short name T422
Test name
Test status
Simulation time 126035925 ps
CPU time 1.2 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 217488 kb
Host smart-423a6801-3854-4d80-9a89-8f37844ffab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197544766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3197544766
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.3988244474
Short name T386
Test name
Test status
Simulation time 39105070 ps
CPU time 0.94 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215536 kb
Host smart-e73d5da1-d979-4a87-8362-d223d6165224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988244474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3988244474
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3037424010
Short name T373
Test name
Test status
Simulation time 61348912 ps
CPU time 1.65 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 218936 kb
Host smart-425989d5-3c99-422d-82ef-9c6bad480eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037424010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3037424010
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3103762977
Short name T97
Test name
Test status
Simulation time 146449277228 ps
CPU time 911.64 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:40:26 PM PDT 24
Peak memory 224116 kb
Host smart-58e3d281-7f3e-4e20-ab74-79734a55fa0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103762977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3103762977
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.42177095
Short name T505
Test name
Test status
Simulation time 80798150 ps
CPU time 1.14 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 217620 kb
Host smart-cfd69736-254d-4e0d-a61d-4ada4ba931e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42177095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.42177095
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1506716150
Short name T394
Test name
Test status
Simulation time 68896297 ps
CPU time 1.18 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 220204 kb
Host smart-794ec934-78fb-4a36-9860-6ddaec342ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506716150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1506716150
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2464703400
Short name T625
Test name
Test status
Simulation time 52106100 ps
CPU time 1.6 seconds
Started Jul 04 06:26:50 PM PDT 24
Finished Jul 04 06:26:52 PM PDT 24
Peak memory 218852 kb
Host smart-1865e5c2-6da7-44a3-a40f-0cdfb852f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464703400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2464703400
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3675127226
Short name T980
Test name
Test status
Simulation time 41611580 ps
CPU time 1.24 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 220296 kb
Host smart-35d42479-12d5-4cd5-a38e-405dd85663d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675127226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3675127226
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2587407242
Short name T477
Test name
Test status
Simulation time 46944160 ps
CPU time 1.6 seconds
Started Jul 04 06:27:05 PM PDT 24
Finished Jul 04 06:27:12 PM PDT 24
Peak memory 218904 kb
Host smart-0123f336-ebee-4adc-b14a-6f174229e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587407242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2587407242
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.17944631
Short name T938
Test name
Test status
Simulation time 65146813 ps
CPU time 2.5 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 220484 kb
Host smart-09c69331-a8dc-499e-87df-43798448c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17944631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.17944631
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1315871971
Short name T379
Test name
Test status
Simulation time 53026764 ps
CPU time 1.43 seconds
Started Jul 04 06:26:53 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 218908 kb
Host smart-79f5a114-7f0b-4f89-af96-19422991f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315871971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1315871971
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1526139436
Short name T543
Test name
Test status
Simulation time 32157956 ps
CPU time 1.26 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 218776 kb
Host smart-1e2e8ab0-7da7-4fb3-80c2-1d6384fdb458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526139436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1526139436
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3461020373
Short name T629
Test name
Test status
Simulation time 82849710 ps
CPU time 1.25 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 219300 kb
Host smart-978c7f2d-8549-4e49-9a55-39bf71bb4082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461020373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3461020373
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2139817248
Short name T523
Test name
Test status
Simulation time 423801062 ps
CPU time 1.22 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 217472 kb
Host smart-a5044390-4125-45f8-91e9-4cd0694f9f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139817248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2139817248
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1988705000
Short name T959
Test name
Test status
Simulation time 74623522 ps
CPU time 1.1 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 220132 kb
Host smart-a3f1aa93-5e05-46b4-9fa2-ed1248d595e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988705000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1988705000
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2365947082
Short name T771
Test name
Test status
Simulation time 19854436 ps
CPU time 0.99 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 207096 kb
Host smart-9c8a2bfb-d25d-4146-943b-3ce39b7f9ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365947082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2365947082
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2120197700
Short name T655
Test name
Test status
Simulation time 11349048 ps
CPU time 0.85 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215976 kb
Host smart-7d21172b-b3d6-433e-97e0-cf408282f3ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120197700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2120197700
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.1785647251
Short name T133
Test name
Test status
Simulation time 186119657 ps
CPU time 1.04 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 218784 kb
Host smart-cfe508fa-ea18-4417-ae7b-78bb6021bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785647251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1785647251
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.4241171927
Short name T384
Test name
Test status
Simulation time 33703635 ps
CPU time 0.89 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 215676 kb
Host smart-c7fda574-e739-4d38-9aeb-88581b7a9eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241171927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4241171927
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.756695578
Short name T621
Test name
Test status
Simulation time 37089348 ps
CPU time 0.88 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 215604 kb
Host smart-6235515c-e8c6-4dd4-acf3-1bc580151181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756695578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.756695578
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3239685573
Short name T232
Test name
Test status
Simulation time 300703521 ps
CPU time 1.94 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 217344 kb
Host smart-7002e0ce-da74-4cb6-8b1c-97d3cf5a659b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239685573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3239685573
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2829279259
Short name T302
Test name
Test status
Simulation time 67326851063 ps
CPU time 758.53 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 219400 kb
Host smart-2ef2acf8-39c2-4220-bd97-634a4b1df262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829279259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2829279259
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3159089991
Short name T43
Test name
Test status
Simulation time 164639970 ps
CPU time 2.98 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 220520 kb
Host smart-a74f6158-1181-4a17-ab65-8628f51cac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159089991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3159089991
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3221968315
Short name T595
Test name
Test status
Simulation time 74868283 ps
CPU time 1.11 seconds
Started Jul 04 06:27:19 PM PDT 24
Finished Jul 04 06:27:20 PM PDT 24
Peak memory 217764 kb
Host smart-03419e3c-70a8-4e11-98f2-eaa0b76bb96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221968315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3221968315
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.826965208
Short name T298
Test name
Test status
Simulation time 268408613 ps
CPU time 1.72 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 219200 kb
Host smart-d1027d40-f876-459c-b2bf-46d260530876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826965208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.826965208
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.979830020
Short name T313
Test name
Test status
Simulation time 87466124 ps
CPU time 1.36 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:07 PM PDT 24
Peak memory 219052 kb
Host smart-76c67766-8c6f-4c79-8a9f-93022c6c3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979830020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.979830020
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2100781986
Short name T555
Test name
Test status
Simulation time 39093674 ps
CPU time 1.53 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 220104 kb
Host smart-d6da8b2f-76a2-40b9-ac81-0337c23363c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100781986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2100781986
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1382975440
Short name T750
Test name
Test status
Simulation time 28623620 ps
CPU time 1.31 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 218680 kb
Host smart-e154a73a-0bc1-499f-9e5d-af976b0248bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382975440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1382975440
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.282337514
Short name T459
Test name
Test status
Simulation time 43458215 ps
CPU time 1.43 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 218840 kb
Host smart-8a57375e-a3af-4437-98af-67bffbf6e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282337514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.282337514
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1811265507
Short name T378
Test name
Test status
Simulation time 39472387 ps
CPU time 1.11 seconds
Started Jul 04 06:27:02 PM PDT 24
Finished Jul 04 06:27:04 PM PDT 24
Peak memory 218948 kb
Host smart-d529c051-1e54-4b6c-9e11-0a8245dd55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811265507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1811265507
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2673650086
Short name T866
Test name
Test status
Simulation time 410658322 ps
CPU time 2.42 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 219644 kb
Host smart-26ab90f5-db4a-47be-bc7c-84f9473c64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673650086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2673650086
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1599504690
Short name T81
Test name
Test status
Simulation time 113644866 ps
CPU time 0.97 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 217536 kb
Host smart-e51cfc33-29be-4bb7-a375-74b0d7926fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599504690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1599504690
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1438222812
Short name T575
Test name
Test status
Simulation time 25638802 ps
CPU time 1.23 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 221060 kb
Host smart-de460581-96bb-430f-b105-f942b50d13f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438222812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1438222812
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3629088258
Short name T623
Test name
Test status
Simulation time 103907107 ps
CPU time 0.9 seconds
Started Jul 04 06:25:31 PM PDT 24
Finished Jul 04 06:25:32 PM PDT 24
Peak memory 207064 kb
Host smart-8b5ca1ae-716a-40d7-b494-5b76a9499269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629088258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3629088258
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2831935183
Short name T699
Test name
Test status
Simulation time 110371690 ps
CPU time 1.16 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 217104 kb
Host smart-fa49d8f3-3ddc-40c9-a386-93f18372deb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831935183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2831935183
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.163107570
Short name T403
Test name
Test status
Simulation time 27320603 ps
CPU time 0.85 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 218628 kb
Host smart-5b14be2a-6563-4267-b01c-ad96019760f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163107570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.163107570
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1888313271
Short name T977
Test name
Test status
Simulation time 63547942 ps
CPU time 1.28 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 217656 kb
Host smart-28e2abad-668d-433c-9689-f25c1fe037f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888313271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1888313271
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3759329570
Short name T33
Test name
Test status
Simulation time 67318886 ps
CPU time 0.85 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215832 kb
Host smart-8911d934-3629-4de2-b969-7bfdd3c3a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759329570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3759329570
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1490488556
Short name T891
Test name
Test status
Simulation time 18751361 ps
CPU time 1.01 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 215856 kb
Host smart-589614c5-254b-4d02-a94c-dd15a4c53095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490488556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1490488556
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1112650504
Short name T99
Test name
Test status
Simulation time 234776907 ps
CPU time 2.57 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 217524 kb
Host smart-95d176ad-7b93-4093-b2c4-490b64e919f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112650504 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1112650504
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2067332483
Short name T402
Test name
Test status
Simulation time 395596336534 ps
CPU time 3163.48 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 07:17:56 PM PDT 24
Peak memory 232876 kb
Host smart-09d5f6b1-7d50-4929-9925-76b7eec44562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067332483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2067332483
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.860274384
Short name T370
Test name
Test status
Simulation time 63381486 ps
CPU time 1.51 seconds
Started Jul 04 06:27:17 PM PDT 24
Finished Jul 04 06:27:19 PM PDT 24
Peak memory 219148 kb
Host smart-97150195-dedb-4ffe-826a-5a4f0c959496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860274384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.860274384
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2200596424
Short name T780
Test name
Test status
Simulation time 35432807 ps
CPU time 1.34 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 218968 kb
Host smart-bcd5f9e6-0743-4943-bf5e-2e7ce0a64136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200596424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2200596424
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1720212129
Short name T597
Test name
Test status
Simulation time 69499341 ps
CPU time 1.11 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 218956 kb
Host smart-24d9e693-7107-45d3-a428-2edae5a3b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720212129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1720212129
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3314809055
Short name T40
Test name
Test status
Simulation time 36531065 ps
CPU time 1.17 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 217676 kb
Host smart-c9e95726-3be9-4053-b8eb-4bfc5dab5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314809055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3314809055
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.416024127
Short name T926
Test name
Test status
Simulation time 115749713 ps
CPU time 1.36 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 217680 kb
Host smart-52bd8336-3df8-4510-a022-ebab6c08073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416024127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.416024127
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3234280594
Short name T855
Test name
Test status
Simulation time 80505608 ps
CPU time 1.06 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 217548 kb
Host smart-23152a0c-a057-4c85-b21f-402eb81dd88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234280594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3234280594
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2384043048
Short name T753
Test name
Test status
Simulation time 51694012 ps
CPU time 1.51 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 219096 kb
Host smart-fcff692a-876a-4b51-8c21-bad000b2ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384043048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2384043048
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3700183676
Short name T823
Test name
Test status
Simulation time 57544653 ps
CPU time 1.35 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 218928 kb
Host smart-dce1307f-a0db-4c84-a73b-5772eb53d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700183676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3700183676
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1738867442
Short name T260
Test name
Test status
Simulation time 290398454 ps
CPU time 3.19 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 220108 kb
Host smart-0c17581f-cdd0-4f98-a3fe-382a8428736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738867442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1738867442
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2295412322
Short name T744
Test name
Test status
Simulation time 89741148 ps
CPU time 1.17 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 219580 kb
Host smart-fd0ca630-de55-4588-81be-845b721c814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295412322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2295412322
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2602207723
Short name T695
Test name
Test status
Simulation time 100702276 ps
CPU time 0.98 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215212 kb
Host smart-8f036804-50ca-41f6-8f6b-2843d480f22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602207723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2602207723
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.490334059
Short name T195
Test name
Test status
Simulation time 39558013 ps
CPU time 0.84 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 216536 kb
Host smart-4c642a17-df0f-4a8a-9dd5-5e07b8ad3157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490334059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.490334059
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1167165513
Short name T322
Test name
Test status
Simulation time 37422090 ps
CPU time 1.29 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 217160 kb
Host smart-977b9dd1-8f3c-4c5a-9480-441f9da39398
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167165513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1167165513
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1360104544
Short name T531
Test name
Test status
Simulation time 44868215 ps
CPU time 1.25 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:42 PM PDT 24
Peak memory 225736 kb
Host smart-1f3bc467-a408-4056-9bbe-eaa5dc9342f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360104544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1360104544
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2687968223
Short name T525
Test name
Test status
Simulation time 70213323 ps
CPU time 1.16 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 220288 kb
Host smart-a707cece-49a1-442c-9a08-de2870690311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687968223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2687968223
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4284200827
Short name T53
Test name
Test status
Simulation time 56743718 ps
CPU time 0.98 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 224168 kb
Host smart-7ea392ce-31d1-48d9-8926-61239d071df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284200827 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4284200827
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1711812070
Short name T343
Test name
Test status
Simulation time 132342384 ps
CPU time 0.91 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 215440 kb
Host smart-02223818-078e-4219-91d8-a9ba701ccc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711812070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1711812070
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1890510922
Short name T722
Test name
Test status
Simulation time 499763418 ps
CPU time 3.05 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 217724 kb
Host smart-c6d4f921-2ebe-4ed2-b076-d1dd89f13b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890510922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1890510922
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.866516924
Short name T849
Test name
Test status
Simulation time 42059821202 ps
CPU time 962.22 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:41:15 PM PDT 24
Peak memory 224012 kb
Host smart-c9465f2e-a6be-4e91-89c9-158e572ff8ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866516924 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.866516924
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3855618994
Short name T455
Test name
Test status
Simulation time 47076104 ps
CPU time 1.49 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 218692 kb
Host smart-8ff8ce82-bfb2-41dc-aa3c-3989feba457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855618994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3855618994
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1749124754
Short name T365
Test name
Test status
Simulation time 59286249 ps
CPU time 2.03 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 220444 kb
Host smart-c6022f98-5166-489d-ada6-984809965697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749124754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1749124754
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2385734999
Short name T765
Test name
Test status
Simulation time 745827114 ps
CPU time 4.51 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:05 PM PDT 24
Peak memory 219180 kb
Host smart-cc5fadc2-ef10-41b6-a43f-d5aa1b5212c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385734999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2385734999
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3693565617
Short name T760
Test name
Test status
Simulation time 52389072 ps
CPU time 1.94 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 218960 kb
Host smart-3142ad50-0f3d-41e1-a647-9b183360a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693565617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3693565617
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4080350078
Short name T404
Test name
Test status
Simulation time 55292235 ps
CPU time 1.71 seconds
Started Jul 04 06:27:04 PM PDT 24
Finished Jul 04 06:27:06 PM PDT 24
Peak memory 219080 kb
Host smart-f053a4ba-147d-485e-ac3d-0c218b5e1f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080350078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4080350078
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.688266200
Short name T381
Test name
Test status
Simulation time 132248266 ps
CPU time 2.06 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 218000 kb
Host smart-4053cc44-7365-44d8-90b6-b46d87d71eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688266200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.688266200
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.420504961
Short name T572
Test name
Test status
Simulation time 41908429 ps
CPU time 1.64 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 217628 kb
Host smart-a0b7ba9d-db05-4c18-af86-cbc4b7e966b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420504961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.420504961
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3094312051
Short name T952
Test name
Test status
Simulation time 33720157 ps
CPU time 1.14 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:55 PM PDT 24
Peak memory 217676 kb
Host smart-73bea135-4bdb-4505-92f2-0d5c0c97807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094312051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3094312051
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3535578759
Short name T806
Test name
Test status
Simulation time 78630562 ps
CPU time 1.26 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 217984 kb
Host smart-1819ba86-d808-4bb7-8e07-a3317269710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535578759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3535578759
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.432850800
Short name T290
Test name
Test status
Simulation time 66648530 ps
CPU time 1.35 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 218836 kb
Host smart-5ff90ec3-1f3b-4a97-ab5b-e9e20c0ac250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432850800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.432850800
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1641300407
Short name T61
Test name
Test status
Simulation time 23776187 ps
CPU time 1.17 seconds
Started Jul 04 06:25:31 PM PDT 24
Finished Jul 04 06:25:32 PM PDT 24
Peak memory 219092 kb
Host smart-7bc0347f-1316-457e-b49b-f8151d050922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641300407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1641300407
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2488257355
Short name T811
Test name
Test status
Simulation time 109933496 ps
CPU time 0.98 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 207088 kb
Host smart-86b239ad-0f44-4e92-977f-d181804b193d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488257355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2488257355
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3803233771
Short name T934
Test name
Test status
Simulation time 27749462 ps
CPU time 0.78 seconds
Started Jul 04 06:25:14 PM PDT 24
Finished Jul 04 06:25:16 PM PDT 24
Peak memory 215752 kb
Host smart-c19ead17-0967-4d39-bd1c-93ee52dd9cd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803233771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3803233771
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4253762763
Short name T426
Test name
Test status
Simulation time 105301824 ps
CPU time 1.22 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 217200 kb
Host smart-5e4627cf-d3e0-4a9a-9cfb-432d17af1629
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253762763 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4253762763
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1325421640
Short name T160
Test name
Test status
Simulation time 45283749 ps
CPU time 0.99 seconds
Started Jul 04 06:25:38 PM PDT 24
Finished Jul 04 06:25:40 PM PDT 24
Peak memory 224016 kb
Host smart-533d2365-62af-4624-9304-d6b7d1848f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325421640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1325421640
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2003136594
Short name T425
Test name
Test status
Simulation time 220550699 ps
CPU time 3 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 217788 kb
Host smart-6262e560-3487-48b3-91ae-f0cb9d808399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003136594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2003136594
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.915365349
Short name T461
Test name
Test status
Simulation time 26126726 ps
CPU time 1.07 seconds
Started Jul 04 06:25:15 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 224188 kb
Host smart-3f769f08-48e1-4950-810a-a255d1691388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915365349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.915365349
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3686124124
Short name T493
Test name
Test status
Simulation time 48777359 ps
CPU time 0.94 seconds
Started Jul 04 06:25:28 PM PDT 24
Finished Jul 04 06:25:29 PM PDT 24
Peak memory 215544 kb
Host smart-5f543360-284b-4f26-a2e6-b970cf9b1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686124124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3686124124
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3876647777
Short name T470
Test name
Test status
Simulation time 343556924 ps
CPU time 5.36 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 217536 kb
Host smart-22785e31-4fed-467d-9b3b-95d621bc018c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876647777 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3876647777
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3756673757
Short name T212
Test name
Test status
Simulation time 42071268323 ps
CPU time 941.18 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:41:02 PM PDT 24
Peak memory 224028 kb
Host smart-29a9eb5c-7987-4d47-bf41-8f45d242cde5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756673757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3756673757
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2715621886
Short name T291
Test name
Test status
Simulation time 49048370 ps
CPU time 1.27 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 217816 kb
Host smart-6793b027-af0a-4071-8c33-af98bddcc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715621886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2715621886
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.319590754
Short name T351
Test name
Test status
Simulation time 42093927 ps
CPU time 1.34 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:53 PM PDT 24
Peak memory 217484 kb
Host smart-a3923ba8-09aa-4f52-892e-75274dd1e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319590754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.319590754
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2399611507
Short name T955
Test name
Test status
Simulation time 56452496 ps
CPU time 1.08 seconds
Started Jul 04 06:26:54 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 217856 kb
Host smart-b777aa90-9c47-4a68-ba14-238f20f74f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399611507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2399611507
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4186708095
Short name T301
Test name
Test status
Simulation time 50467535 ps
CPU time 1.06 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:54 PM PDT 24
Peak memory 220124 kb
Host smart-0b4f363b-976b-4136-b08f-0e61ecf7fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186708095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4186708095
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.246321175
Short name T510
Test name
Test status
Simulation time 43041908 ps
CPU time 1.58 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:26:57 PM PDT 24
Peak memory 218932 kb
Host smart-4fe7c5ec-0a4c-4777-97ad-0fabf6b8a665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246321175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.246321175
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2471543037
Short name T902
Test name
Test status
Simulation time 44720521 ps
CPU time 1.08 seconds
Started Jul 04 06:27:10 PM PDT 24
Finished Jul 04 06:27:12 PM PDT 24
Peak memory 219216 kb
Host smart-c4345e22-9bf1-4c77-aa0c-dedfad398d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471543037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2471543037
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4289862467
Short name T635
Test name
Test status
Simulation time 570370280 ps
CPU time 3.99 seconds
Started Jul 04 06:26:55 PM PDT 24
Finished Jul 04 06:27:00 PM PDT 24
Peak memory 220480 kb
Host smart-3d39600d-4ce5-4298-8993-4313d9b856f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289862467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4289862467
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.339536231
Short name T1
Test name
Test status
Simulation time 100689037 ps
CPU time 1.23 seconds
Started Jul 04 06:26:59 PM PDT 24
Finished Jul 04 06:27:02 PM PDT 24
Peak memory 217600 kb
Host smart-a76fa28e-fee0-4176-ae7b-2bc8f73a762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339536231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.339536231
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1414187667
Short name T305
Test name
Test status
Simulation time 89286858 ps
CPU time 1.49 seconds
Started Jul 04 06:26:49 PM PDT 24
Finished Jul 04 06:26:51 PM PDT 24
Peak memory 219228 kb
Host smart-3a3c0fc1-1062-4893-ab94-622ff19daed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414187667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1414187667
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2096304908
Short name T687
Test name
Test status
Simulation time 88718419 ps
CPU time 1.43 seconds
Started Jul 04 06:27:05 PM PDT 24
Finished Jul 04 06:27:07 PM PDT 24
Peak memory 219128 kb
Host smart-f77c42c3-994a-47df-84a6-6e55b085d01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096304908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2096304908
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1525256614
Short name T986
Test name
Test status
Simulation time 231064173 ps
CPU time 1.2 seconds
Started Jul 04 06:25:53 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 219692 kb
Host smart-2c4bc28b-3d1c-444a-929b-e94126defedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525256614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1525256614
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.126493754
Short name T909
Test name
Test status
Simulation time 26234938 ps
CPU time 1.06 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:41 PM PDT 24
Peak memory 207024 kb
Host smart-24e39dda-48cf-421d-a583-f45676f41788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126493754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.126493754
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1196720052
Short name T978
Test name
Test status
Simulation time 13600807 ps
CPU time 0.85 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 215748 kb
Host smart-0c1478cb-573f-4632-bf8d-fe163ec60884
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196720052 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1196720052
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.502627416
Short name T600
Test name
Test status
Simulation time 29554294 ps
CPU time 1.12 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 217212 kb
Host smart-9956f09d-f492-40bb-b780-15c08d4e5096
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502627416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.502627416
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.4054858388
Short name T184
Test name
Test status
Simulation time 26496307 ps
CPU time 0.86 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 219632 kb
Host smart-b6029051-a97c-4b5c-806c-19ab5b12b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054858388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.4054858388
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2315087461
Short name T618
Test name
Test status
Simulation time 74767834 ps
CPU time 1.24 seconds
Started Jul 04 06:25:33 PM PDT 24
Finished Jul 04 06:25:35 PM PDT 24
Peak memory 219032 kb
Host smart-67d55577-7310-4899-b88c-0d93b158a784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315087461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2315087461
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1031878342
Short name T649
Test name
Test status
Simulation time 59500622 ps
CPU time 0.8 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 215700 kb
Host smart-e5cd0ba9-3573-41c2-be83-1b305e62b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031878342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1031878342
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1128591538
Short name T445
Test name
Test status
Simulation time 31718897 ps
CPU time 0.95 seconds
Started Jul 04 06:25:29 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 215620 kb
Host smart-8f0d11b7-c1af-483b-bb03-973db057be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128591538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1128591538
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.381930893
Short name T226
Test name
Test status
Simulation time 291798478 ps
CPU time 3.13 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:49 PM PDT 24
Peak memory 215596 kb
Host smart-a32a910f-5f0b-47f2-b1e6-c47ac8824a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381930893 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.381930893
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3562888287
Short name T511
Test name
Test status
Simulation time 23919781897 ps
CPU time 591.77 seconds
Started Jul 04 06:25:29 PM PDT 24
Finished Jul 04 06:35:21 PM PDT 24
Peak memory 224016 kb
Host smart-69fb8597-05d1-4cc8-ae85-665f00f1d483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562888287 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3562888287
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.927651071
Short name T458
Test name
Test status
Simulation time 92962992 ps
CPU time 1.4 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:04 PM PDT 24
Peak memory 219436 kb
Host smart-8720405d-d3e9-4ee0-af55-7649dce6dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927651071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.927651071
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2366918007
Short name T279
Test name
Test status
Simulation time 112862960 ps
CPU time 1.25 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 219048 kb
Host smart-c7be096f-42c4-4def-9412-709ee35f5ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366918007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2366918007
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.408530339
Short name T37
Test name
Test status
Simulation time 48584478 ps
CPU time 1.44 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:00 PM PDT 24
Peak memory 218856 kb
Host smart-a94a4472-6f32-4028-b03d-35303e3a5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408530339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.408530339
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.315490676
Short name T474
Test name
Test status
Simulation time 74274866 ps
CPU time 1.28 seconds
Started Jul 04 06:27:11 PM PDT 24
Finished Jul 04 06:27:17 PM PDT 24
Peak memory 217636 kb
Host smart-e9b879c1-2274-4fc6-9604-06aa36472a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315490676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.315490676
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3531312505
Short name T825
Test name
Test status
Simulation time 37269145 ps
CPU time 1.32 seconds
Started Jul 04 06:26:57 PM PDT 24
Finished Jul 04 06:26:59 PM PDT 24
Peak memory 218692 kb
Host smart-976285f2-a8ec-4fb2-b1f5-c3958afd74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531312505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3531312505
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1258145717
Short name T42
Test name
Test status
Simulation time 52554160 ps
CPU time 1.63 seconds
Started Jul 04 06:26:51 PM PDT 24
Finished Jul 04 06:26:53 PM PDT 24
Peak memory 218744 kb
Host smart-ea4c6836-0cf4-4d11-9c08-468d515d2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258145717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1258145717
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.720571175
Short name T982
Test name
Test status
Simulation time 79538982 ps
CPU time 1.07 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:04 PM PDT 24
Peak memory 217560 kb
Host smart-d712417b-baca-416c-99df-0e6d1680b001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720571175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.720571175
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.986451430
Short name T342
Test name
Test status
Simulation time 68133123 ps
CPU time 1.43 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 219012 kb
Host smart-1aab8952-8176-4e74-bb7a-b6161ffde2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986451430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.986451430
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1853101826
Short name T15
Test name
Test status
Simulation time 36950665 ps
CPU time 1.46 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:01 PM PDT 24
Peak memory 219768 kb
Host smart-3a80c002-2f47-46f9-9271-94a6492fe681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853101826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1853101826
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.292632666
Short name T945
Test name
Test status
Simulation time 55898071 ps
CPU time 1.21 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:26 PM PDT 24
Peak memory 220380 kb
Host smart-fb8f477e-d10d-45a8-9eae-f6ef9569c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292632666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.292632666
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3790020652
Short name T586
Test name
Test status
Simulation time 64261798 ps
CPU time 0.85 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 215484 kb
Host smart-80f73147-2c4d-4935-98f0-0414d8a3e3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790020652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3790020652
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3935635164
Short name T548
Test name
Test status
Simulation time 56957885 ps
CPU time 0.8 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 216260 kb
Host smart-0f95b520-8c4a-4158-bc63-7b786647b149
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935635164 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3935635164
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.698992312
Short name T864
Test name
Test status
Simulation time 35611745 ps
CPU time 1.17 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:25:43 PM PDT 24
Peak memory 218596 kb
Host smart-0fd7d1db-dc97-4698-b71f-cc53f475ea6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698992312 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.698992312
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2877865096
Short name T137
Test name
Test status
Simulation time 31811088 ps
CPU time 1.12 seconds
Started Jul 04 06:25:27 PM PDT 24
Finished Jul 04 06:25:28 PM PDT 24
Peak memory 230312 kb
Host smart-1f68e359-ee66-4b69-b0f5-7d7224d3d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877865096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2877865096
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.2457269102
Short name T93
Test name
Test status
Simulation time 20927540 ps
CPU time 1.09 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 216088 kb
Host smart-5c44ff2d-1327-4ff6-a098-528d2814121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457269102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2457269102
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.159494009
Short name T886
Test name
Test status
Simulation time 22981398 ps
CPU time 0.87 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 215604 kb
Host smart-445aa5a2-1d5d-4fb7-9b78-aef1a48bd52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159494009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.159494009
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1726760600
Short name T347
Test name
Test status
Simulation time 433907376 ps
CPU time 3.13 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 215652 kb
Host smart-07762adf-f67d-434f-8b84-b87c85238289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726760600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1726760600
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1778031906
Short name T701
Test name
Test status
Simulation time 343069339270 ps
CPU time 1961.1 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:58:01 PM PDT 24
Peak memory 227492 kb
Host smart-e4abd505-ed56-4236-b496-25fd615cb687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778031906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1778031906
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.388402119
Short name T633
Test name
Test status
Simulation time 42376399 ps
CPU time 1.25 seconds
Started Jul 04 06:27:13 PM PDT 24
Finished Jul 04 06:27:15 PM PDT 24
Peak memory 220308 kb
Host smart-8f51b16e-1dc5-4122-9ade-ae3024e330fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388402119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.388402119
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2857084246
Short name T916
Test name
Test status
Simulation time 206208060 ps
CPU time 1.34 seconds
Started Jul 04 06:27:37 PM PDT 24
Finished Jul 04 06:27:39 PM PDT 24
Peak memory 219072 kb
Host smart-8b99a9a6-2aeb-4d06-bd16-ec854a2d8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857084246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2857084246
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4157417086
Short name T501
Test name
Test status
Simulation time 35070824 ps
CPU time 1.45 seconds
Started Jul 04 06:26:58 PM PDT 24
Finished Jul 04 06:27:00 PM PDT 24
Peak memory 219892 kb
Host smart-cdbf2d01-b84a-472a-bc5e-62c7aadc31a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157417086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4157417086
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3312767696
Short name T2
Test name
Test status
Simulation time 44803857 ps
CPU time 1.55 seconds
Started Jul 04 06:26:56 PM PDT 24
Finished Jul 04 06:26:58 PM PDT 24
Peak memory 218740 kb
Host smart-a3af912c-1e2d-48f0-92a3-7c1b941a72ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312767696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3312767696
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3571448930
Short name T923
Test name
Test status
Simulation time 35086624 ps
CPU time 1.32 seconds
Started Jul 04 06:27:14 PM PDT 24
Finished Jul 04 06:27:15 PM PDT 24
Peak memory 218924 kb
Host smart-2e1bfbff-60d1-4fd3-85d0-96d36cf77fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571448930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3571448930
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1464087506
Short name T340
Test name
Test status
Simulation time 81378394 ps
CPU time 1.17 seconds
Started Jul 04 06:27:00 PM PDT 24
Finished Jul 04 06:27:03 PM PDT 24
Peak memory 217716 kb
Host smart-95e57b57-471a-485e-be89-1dc48a3d9ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464087506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1464087506
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3006845947
Short name T898
Test name
Test status
Simulation time 137581570 ps
CPU time 3.07 seconds
Started Jul 04 06:26:52 PM PDT 24
Finished Jul 04 06:26:56 PM PDT 24
Peak memory 220520 kb
Host smart-f58dbba5-feac-42c2-b4fd-9735049228f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006845947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3006845947
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2868694452
Short name T641
Test name
Test status
Simulation time 39721556 ps
CPU time 1.68 seconds
Started Jul 04 06:27:18 PM PDT 24
Finished Jul 04 06:27:20 PM PDT 24
Peak memory 218784 kb
Host smart-9d1c253a-ecff-4ff7-909e-9a16a886012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868694452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2868694452
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1271000613
Short name T491
Test name
Test status
Simulation time 60927612 ps
CPU time 1.43 seconds
Started Jul 04 06:27:01 PM PDT 24
Finished Jul 04 06:27:04 PM PDT 24
Peak memory 217760 kb
Host smart-7c9a8abe-6006-4c2e-82ca-319c10ce560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271000613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1271000613
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2063308829
Short name T887
Test name
Test status
Simulation time 49821606 ps
CPU time 1.75 seconds
Started Jul 04 06:27:06 PM PDT 24
Finished Jul 04 06:27:08 PM PDT 24
Peak memory 217692 kb
Host smart-26f15b8d-43a3-41b5-8c97-430422e0bdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063308829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2063308829
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.829986735
Short name T468
Test name
Test status
Simulation time 24108724 ps
CPU time 1.14 seconds
Started Jul 04 06:24:44 PM PDT 24
Finished Jul 04 06:24:45 PM PDT 24
Peak memory 219032 kb
Host smart-1f25ce56-29cf-4ddc-b9df-8819d0ebfe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829986735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.829986735
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3435460568
Short name T672
Test name
Test status
Simulation time 21992096 ps
CPU time 0.82 seconds
Started Jul 04 06:24:36 PM PDT 24
Finished Jul 04 06:24:37 PM PDT 24
Peak memory 206856 kb
Host smart-50e4df0c-ac5e-4d8f-91c5-5a5f2523c90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435460568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3435460568
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2371030476
Short name T697
Test name
Test status
Simulation time 43668427 ps
CPU time 0.85 seconds
Started Jul 04 06:24:57 PM PDT 24
Finished Jul 04 06:24:58 PM PDT 24
Peak memory 215732 kb
Host smart-b52894b6-db5b-4042-94b2-4abcec742897
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371030476 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2371030476
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2998694198
Short name T987
Test name
Test status
Simulation time 53235659 ps
CPU time 1.16 seconds
Started Jul 04 06:24:44 PM PDT 24
Finished Jul 04 06:24:46 PM PDT 24
Peak memory 217224 kb
Host smart-3ea8beaa-4e8f-4603-ad5c-a835efef36cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998694198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2998694198
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.835311348
Short name T363
Test name
Test status
Simulation time 79612644 ps
CPU time 1.4 seconds
Started Jul 04 06:24:37 PM PDT 24
Finished Jul 04 06:24:39 PM PDT 24
Peak memory 218948 kb
Host smart-d303721f-f34b-42b6-8185-78b7a061fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835311348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.835311348
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4059107408
Short name T28
Test name
Test status
Simulation time 54068234 ps
CPU time 0.83 seconds
Started Jul 04 06:24:37 PM PDT 24
Finished Jul 04 06:24:38 PM PDT 24
Peak memory 215832 kb
Host smart-2b5683be-f6d4-4379-a2f5-5a29cbb6266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059107408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4059107408
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1089289526
Short name T25
Test name
Test status
Simulation time 229080220 ps
CPU time 0.92 seconds
Started Jul 04 06:25:03 PM PDT 24
Finished Jul 04 06:25:04 PM PDT 24
Peak memory 207392 kb
Host smart-0cc5979a-c21d-425e-a9e5-d1a8aafea7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089289526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1089289526
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3919562599
Short name T57
Test name
Test status
Simulation time 1030332762 ps
CPU time 7.91 seconds
Started Jul 04 06:24:52 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 235468 kb
Host smart-b53cbed2-aa72-476a-9b6c-451341434d35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919562599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3919562599
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2564849713
Short name T979
Test name
Test status
Simulation time 48378959 ps
CPU time 0.93 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 215644 kb
Host smart-4d652e18-20ea-4647-b23c-fb774cca9994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564849713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2564849713
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1743826728
Short name T773
Test name
Test status
Simulation time 241650922 ps
CPU time 2.82 seconds
Started Jul 04 06:24:37 PM PDT 24
Finished Jul 04 06:24:40 PM PDT 24
Peak memory 217516 kb
Host smart-d33a1238-1a64-4541-a756-a49950e80f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743826728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1743826728
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3380746785
Short name T513
Test name
Test status
Simulation time 152554545947 ps
CPU time 789.38 seconds
Started Jul 04 06:24:53 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 224096 kb
Host smart-655bc46c-c478-4812-bf5c-5ad9c477937c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380746785 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3380746785
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2397201781
Short name T115
Test name
Test status
Simulation time 28686733 ps
CPU time 1.26 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 219804 kb
Host smart-4ee3b488-498e-413b-98b6-70e07643cc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397201781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2397201781
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3499181877
Short name T262
Test name
Test status
Simulation time 21518568 ps
CPU time 0.96 seconds
Started Jul 04 06:25:30 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 215440 kb
Host smart-4c361c29-62ae-40ec-b136-cda8a0179490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499181877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3499181877
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3590936218
Short name T664
Test name
Test status
Simulation time 27341153 ps
CPU time 0.86 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 216284 kb
Host smart-e7a4b244-84f5-4f3a-87bb-1cdf68a9d736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590936218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3590936218
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2488588300
Short name T90
Test name
Test status
Simulation time 48178582 ps
CPU time 1.03 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 218780 kb
Host smart-09b764da-494f-4ab2-b242-98c3beecafcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488588300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2488588300
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1348689959
Short name T182
Test name
Test status
Simulation time 20683702 ps
CPU time 1.19 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 224264 kb
Host smart-25b62542-e367-424f-afe2-10f1b737d415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348689959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1348689959
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2909172192
Short name T746
Test name
Test status
Simulation time 52526886 ps
CPU time 1.66 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 217704 kb
Host smart-f94aa1b9-719b-486a-9da9-b448feda8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909172192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2909172192
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2872057505
Short name T725
Test name
Test status
Simulation time 21707582 ps
CPU time 1.11 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 216088 kb
Host smart-78ffd165-a314-427c-bf20-ef3d1d5db2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872057505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2872057505
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2166537613
Short name T454
Test name
Test status
Simulation time 15641633 ps
CPU time 0.93 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 207432 kb
Host smart-65a24653-4955-4835-828d-6d93986f36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166537613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2166537613
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3991924352
Short name T741
Test name
Test status
Simulation time 122449424 ps
CPU time 2.83 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:51 PM PDT 24
Peak memory 215800 kb
Host smart-9fd6dd3c-db59-44a7-80e0-e0f2e12d0408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991924352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3991924352
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2147919271
Short name T222
Test name
Test status
Simulation time 34700958201 ps
CPU time 387.63 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:31:44 PM PDT 24
Peak memory 216880 kb
Host smart-983b0752-cd50-444c-a4eb-c60d34c182e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147919271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2147919271
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3892362245
Short name T328
Test name
Test status
Simulation time 38058272 ps
CPU time 1.18 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 215992 kb
Host smart-cc4ff9a2-50ba-43f3-9092-a264fa153ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892362245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3892362245
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.507058139
Short name T497
Test name
Test status
Simulation time 44221929 ps
CPU time 0.86 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 207048 kb
Host smart-92d9bec1-a5d6-41e2-b024-ca219c2af92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507058139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.507058139
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2764422403
Short name T705
Test name
Test status
Simulation time 40297782 ps
CPU time 0.82 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 216260 kb
Host smart-c173dc5b-7813-4a33-ae5d-df7f185bd8d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764422403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2764422403
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2469377843
Short name T604
Test name
Test status
Simulation time 21944095 ps
CPU time 1.02 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:46 PM PDT 24
Peak memory 218632 kb
Host smart-144a8edb-b9cd-43ef-8316-b1bb312bf157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469377843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2469377843
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1205919098
Short name T181
Test name
Test status
Simulation time 22006760 ps
CPU time 0.93 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:52 PM PDT 24
Peak memory 218660 kb
Host smart-413c7f41-1129-4a61-b413-fd2e74f4ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205919098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1205919098
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.227245047
Short name T594
Test name
Test status
Simulation time 53160382 ps
CPU time 1.27 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:41 PM PDT 24
Peak memory 220284 kb
Host smart-f2f40eff-4dce-43b1-a914-8fe1d162807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227245047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.227245047
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.218870154
Short name T709
Test name
Test status
Simulation time 64784815 ps
CPU time 0.88 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 215680 kb
Host smart-04f770fe-caca-4c5d-ba1a-f4cfd1a4f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218870154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.218870154
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3938843784
Short name T518
Test name
Test status
Simulation time 45718240 ps
CPU time 0.96 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 215588 kb
Host smart-e116b608-14ad-4bd5-b393-6d3a4ba83b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938843784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3938843784
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1501273414
Short name T859
Test name
Test status
Simulation time 450539574 ps
CPU time 4.61 seconds
Started Jul 04 06:25:43 PM PDT 24
Finished Jul 04 06:25:48 PM PDT 24
Peak memory 217716 kb
Host smart-c4701bbc-9f5b-4c17-97b5-a513465ba516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501273414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1501273414
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1206380174
Short name T66
Test name
Test status
Simulation time 10833327078 ps
CPU time 222.1 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:29:01 PM PDT 24
Peak memory 217960 kb
Host smart-fbb97180-e72a-482c-8657-b49e862871c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206380174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1206380174
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1820939392
Short name T533
Test name
Test status
Simulation time 49277926 ps
CPU time 1.18 seconds
Started Jul 04 06:25:30 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 220140 kb
Host smart-cbd8ae95-aa95-42f9-93a1-2751607a8c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820939392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1820939392
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1836916941
Short name T644
Test name
Test status
Simulation time 55123562 ps
CPU time 0.94 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 215532 kb
Host smart-5da8d02d-6644-456e-ba52-ce8637fe0496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836916941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1836916941
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.561236906
Short name T203
Test name
Test status
Simulation time 37154151 ps
CPU time 0.87 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 216512 kb
Host smart-e21ada34-fcea-415c-897a-30cf01308ba4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561236906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.561236906
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.975874700
Short name T569
Test name
Test status
Simulation time 60492766 ps
CPU time 1.01 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:28 PM PDT 24
Peak memory 218468 kb
Host smart-da9cc62c-156f-47c0-9ec8-d9fe335ab006
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975874700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.975874700
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1897954478
Short name T4
Test name
Test status
Simulation time 41115780 ps
CPU time 0.94 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 224092 kb
Host smart-90bc73ac-acb6-48a9-bcd7-d42643580c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897954478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1897954478
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.255965328
Short name T719
Test name
Test status
Simulation time 54985362 ps
CPU time 1.61 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 218664 kb
Host smart-17cf7354-2e9e-4317-9467-ed969a40afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255965328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.255965328
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3789336466
Short name T95
Test name
Test status
Simulation time 23847630 ps
CPU time 0.93 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 216092 kb
Host smart-16c461ca-6fde-40fa-b6da-e3069b4b5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789336466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3789336466
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1653202027
Short name T536
Test name
Test status
Simulation time 29958878 ps
CPU time 0.94 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 215600 kb
Host smart-ecb18c08-2787-484c-8a10-0dba9fbd2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653202027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1653202027
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.911249976
Short name T723
Test name
Test status
Simulation time 287432940 ps
CPU time 5.57 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:26 PM PDT 24
Peak memory 215572 kb
Host smart-b82b3672-3acf-4340-a80a-26950ac32afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911249976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.911249976
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2088451360
Short name T847
Test name
Test status
Simulation time 107304488879 ps
CPU time 1131.31 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:44:33 PM PDT 24
Peak memory 222680 kb
Host smart-648736f0-ab13-4553-9a25-40201cd67410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088451360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2088451360
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.956744066
Short name T680
Test name
Test status
Simulation time 27996373 ps
CPU time 1.29 seconds
Started Jul 04 06:25:34 PM PDT 24
Finished Jul 04 06:25:35 PM PDT 24
Peak memory 219040 kb
Host smart-26e3845a-5544-4787-8c9c-7e4c526b9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956744066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.956744066
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3486958252
Short name T686
Test name
Test status
Simulation time 103087018 ps
CPU time 1.42 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 207104 kb
Host smart-6d74a917-908a-4875-916c-332954ff3f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486958252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3486958252
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2353667202
Short name T177
Test name
Test status
Simulation time 41058976 ps
CPU time 0.84 seconds
Started Jul 04 06:25:30 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 216656 kb
Host smart-1f0611bd-0812-4bda-9774-fa6fe7b1e60a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353667202 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2353667202
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.953077187
Short name T735
Test name
Test status
Simulation time 72088501 ps
CPU time 1.23 seconds
Started Jul 04 06:25:17 PM PDT 24
Finished Jul 04 06:25:19 PM PDT 24
Peak memory 217404 kb
Host smart-e25d6519-671e-4292-bdeb-a0c52f2b02de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953077187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.953077187
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2500193534
Short name T183
Test name
Test status
Simulation time 19512671 ps
CPU time 1.03 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 218872 kb
Host smart-c16dc624-93ad-4fc2-9e78-6fce30b2984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500193534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2500193534
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1220649023
Short name T981
Test name
Test status
Simulation time 44681406 ps
CPU time 1.43 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 217732 kb
Host smart-9ab358a1-794e-4033-b164-87409accea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220649023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1220649023
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2607256405
Short name T992
Test name
Test status
Simulation time 38206534 ps
CPU time 0.91 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:25:42 PM PDT 24
Peak memory 216120 kb
Host smart-da601591-8961-4f53-a806-b1450e59a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607256405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2607256405
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.419794718
Short name T857
Test name
Test status
Simulation time 36305020 ps
CPU time 0.87 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 215576 kb
Host smart-a67fbee6-fe02-472f-a2b0-cf72854825c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419794718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.419794718
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2543325471
Short name T233
Test name
Test status
Simulation time 298176745 ps
CPU time 5.49 seconds
Started Jul 04 06:25:34 PM PDT 24
Finished Jul 04 06:25:39 PM PDT 24
Peak memory 217536 kb
Host smart-897ff8e3-06b1-4c94-bdd4-2050a74b3623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543325471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2543325471
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3739037413
Short name T718
Test name
Test status
Simulation time 46397917488 ps
CPU time 1150.12 seconds
Started Jul 04 06:25:30 PM PDT 24
Finished Jul 04 06:44:40 PM PDT 24
Peak memory 224084 kb
Host smart-62bb7135-fe72-4af7-b135-d1387a6d7e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739037413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3739037413
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3316400533
Short name T74
Test name
Test status
Simulation time 47181026 ps
CPU time 1.16 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 219100 kb
Host smart-74a8ae9d-ebe5-4098-b056-bbdde3ecff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316400533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3316400533
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3179624748
Short name T704
Test name
Test status
Simulation time 42489767 ps
CPU time 0.83 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:20 PM PDT 24
Peak memory 215204 kb
Host smart-948227e6-b06e-4f72-9a6d-8a19be9ba17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179624748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3179624748
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2708423816
Short name T975
Test name
Test status
Simulation time 47077295 ps
CPU time 1.53 seconds
Started Jul 04 06:25:35 PM PDT 24
Finished Jul 04 06:25:37 PM PDT 24
Peak memory 217148 kb
Host smart-133edea5-966c-4f49-a6e5-20a088075502
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708423816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2708423816
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1977393851
Short name T151
Test name
Test status
Simulation time 37625494 ps
CPU time 1.27 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 219936 kb
Host smart-7a546d45-72e5-43ee-a2e7-c5d06286206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977393851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1977393851
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2707610612
Short name T385
Test name
Test status
Simulation time 35815095 ps
CPU time 1.39 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 218808 kb
Host smart-a488cdf5-dc87-4480-a9c7-5673911676c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707610612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2707610612
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.864024919
Short name T739
Test name
Test status
Simulation time 39209925 ps
CPU time 0.97 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 224296 kb
Host smart-c159c7da-b57f-4689-a505-cecda5dddcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864024919 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.864024919
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1075744245
Short name T805
Test name
Test status
Simulation time 17609750 ps
CPU time 1 seconds
Started Jul 04 06:25:36 PM PDT 24
Finished Jul 04 06:25:37 PM PDT 24
Peak memory 215608 kb
Host smart-3fceb820-405f-4351-9c43-babf663946cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075744245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1075744245
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3360488184
Short name T23
Test name
Test status
Simulation time 48417709 ps
CPU time 1.49 seconds
Started Jul 04 06:25:33 PM PDT 24
Finished Jul 04 06:25:35 PM PDT 24
Peak memory 215500 kb
Host smart-f42ed55f-c842-49ae-aa47-f4ebe335be2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360488184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3360488184
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3110008811
Short name T36
Test name
Test status
Simulation time 42674322774 ps
CPU time 569.25 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:35:14 PM PDT 24
Peak memory 224032 kb
Host smart-e8df21aa-be79-4473-a45c-8c0bb7c7838a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110008811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3110008811
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.543444447
Short name T237
Test name
Test status
Simulation time 147583907 ps
CPU time 1.29 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 218952 kb
Host smart-5cdb4a00-f6a4-485e-9967-9bc5bffb6429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543444447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.543444447
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1073770082
Short name T715
Test name
Test status
Simulation time 16067768 ps
CPU time 0.91 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 215176 kb
Host smart-ca3c7681-af3d-4621-bb49-37d72bf7624a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073770082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1073770082
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.641639725
Short name T960
Test name
Test status
Simulation time 36449459 ps
CPU time 0.79 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 215680 kb
Host smart-24c561b5-ab79-43ff-b008-73c237d77f4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641639725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.641639725
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1007549484
Short name T651
Test name
Test status
Simulation time 204397146 ps
CPU time 1.14 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 218816 kb
Host smart-b771810c-edc2-4473-9b0a-6a0b671b94b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007549484 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1007549484
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.500041730
Short name T152
Test name
Test status
Simulation time 19044311 ps
CPU time 1.17 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 224220 kb
Host smart-2439047c-268a-4ccd-b542-ab8e0f240d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500041730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.500041730
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3291928434
Short name T420
Test name
Test status
Simulation time 61608852 ps
CPU time 1.27 seconds
Started Jul 04 06:25:30 PM PDT 24
Finished Jul 04 06:25:31 PM PDT 24
Peak memory 220324 kb
Host smart-eb12637d-ad7d-451f-b526-23c7adcc27f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291928434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3291928434
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3635517109
Short name T845
Test name
Test status
Simulation time 28851084 ps
CPU time 0.95 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 215896 kb
Host smart-fdccb342-091f-4b99-b750-6396bb01c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635517109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3635517109
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1539798692
Short name T598
Test name
Test status
Simulation time 14941608 ps
CPU time 0.97 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 215648 kb
Host smart-029b833c-25e9-4733-962a-dc03b09e9c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539798692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1539798692
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2944314179
Short name T417
Test name
Test status
Simulation time 57866473 ps
CPU time 1.7 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 215596 kb
Host smart-670a68a3-2018-4e76-abb2-446b3372e89c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944314179 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2944314179
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.180097985
Short name T213
Test name
Test status
Simulation time 48228984925 ps
CPU time 544.04 seconds
Started Jul 04 06:25:31 PM PDT 24
Finished Jul 04 06:34:35 PM PDT 24
Peak memory 218364 kb
Host smart-28541fcd-16fa-4c1f-8069-40e3d0ce3638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180097985 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.180097985
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.532034282
Short name T104
Test name
Test status
Simulation time 98611393 ps
CPU time 1.21 seconds
Started Jul 04 06:25:19 PM PDT 24
Finished Jul 04 06:25:21 PM PDT 24
Peak memory 219964 kb
Host smart-d04e83d1-2e35-4124-87cb-82f12349a8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532034282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.532034282
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3239860772
Short name T707
Test name
Test status
Simulation time 36748708 ps
CPU time 0.79 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 207028 kb
Host smart-27c081eb-7587-4a32-9cdc-3c9a2091aec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239860772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3239860772
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2160538638
Short name T225
Test name
Test status
Simulation time 17131786 ps
CPU time 0.84 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 207476 kb
Host smart-4675ebb6-fd7f-4347-8505-2c1c171d051c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160538638 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2160538638
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.2276929976
Short name T473
Test name
Test status
Simulation time 18097243 ps
CPU time 1.07 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 218948 kb
Host smart-28031ebe-19a2-45ed-8ff4-e6f37915ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276929976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2276929976
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2392595379
Short name T931
Test name
Test status
Simulation time 31513819 ps
CPU time 1.5 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 217640 kb
Host smart-fe21b041-3286-4be6-b344-bc0b0056d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392595379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2392595379
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.929289110
Short name T490
Test name
Test status
Simulation time 38996349 ps
CPU time 0.99 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 224300 kb
Host smart-b0c20871-2662-4f85-a6b4-062bdf0f1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929289110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.929289110
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.795550308
Short name T471
Test name
Test status
Simulation time 42024903 ps
CPU time 0.94 seconds
Started Jul 04 06:25:49 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 215608 kb
Host smart-cdbd5fe9-fd8c-46c3-973d-f94b7e58d775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795550308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.795550308
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1888944036
Short name T5
Test name
Test status
Simulation time 875100548 ps
CPU time 3.34 seconds
Started Jul 04 06:25:18 PM PDT 24
Finished Jul 04 06:25:22 PM PDT 24
Peak memory 217656 kb
Host smart-d7e35dfa-ab96-47a1-a50c-e754702e857a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888944036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1888944036
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.4137168130
Short name T933
Test name
Test status
Simulation time 53928405 ps
CPU time 1.12 seconds
Started Jul 04 06:25:43 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 220516 kb
Host smart-30b6b084-5c40-47ef-b44a-e148682e9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137168130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4137168130
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1689463273
Short name T865
Test name
Test status
Simulation time 14036275 ps
CPU time 0.88 seconds
Started Jul 04 06:25:25 PM PDT 24
Finished Jul 04 06:25:26 PM PDT 24
Peak memory 215168 kb
Host smart-7f502d1e-2ff7-412f-9897-0266b3c28e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689463273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1689463273
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2068098703
Short name T966
Test name
Test status
Simulation time 47434182 ps
CPU time 0.82 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:41 PM PDT 24
Peak memory 216232 kb
Host smart-70ed88df-aec6-448c-bbde-d7aa7ebe6a25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068098703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2068098703
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1634947674
Short name T550
Test name
Test status
Simulation time 42304280 ps
CPU time 1.06 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 215912 kb
Host smart-9ada2779-3285-4033-b562-c8cb909e50d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634947674 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1634947674
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2951813960
Short name T437
Test name
Test status
Simulation time 29255748 ps
CPU time 1.26 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 217808 kb
Host smart-9b35729c-a14c-41ec-81de-193943d3da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951813960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2951813960
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2556148399
Short name T795
Test name
Test status
Simulation time 47451387 ps
CPU time 1.63 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:25:43 PM PDT 24
Peak memory 218832 kb
Host smart-dde48dc8-07a5-406e-961b-8952508c8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556148399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2556148399
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2158579384
Short name T106
Test name
Test status
Simulation time 21787534 ps
CPU time 1.09 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 216112 kb
Host smart-461856bf-8271-41ac-8289-cd288c5651b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158579384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2158579384
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1149061213
Short name T949
Test name
Test status
Simulation time 20782163 ps
CPU time 1 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 215636 kb
Host smart-f18a0424-6307-4043-b158-b1740f104aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149061213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1149061213
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2766230239
Short name T881
Test name
Test status
Simulation time 115965358 ps
CPU time 2.6 seconds
Started Jul 04 06:25:20 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 217552 kb
Host smart-4fd936b0-ecf1-4b7c-a07e-a2ed9d3f60e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766230239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2766230239
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3098098173
Short name T219
Test name
Test status
Simulation time 111679636743 ps
CPU time 633.57 seconds
Started Jul 04 06:25:13 PM PDT 24
Finished Jul 04 06:35:47 PM PDT 24
Peak memory 223204 kb
Host smart-d7368f6f-4965-415f-bb36-f10e0158c8a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098098173 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3098098173
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.158323750
Short name T86
Test name
Test status
Simulation time 26705812 ps
CPU time 1.2 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 220244 kb
Host smart-937475e1-a5b7-437a-8fd2-171726060e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158323750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.158323750
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4202696305
Short name T988
Test name
Test status
Simulation time 24078354 ps
CPU time 1.13 seconds
Started Jul 04 06:25:43 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 206988 kb
Host smart-ab21276c-cb45-4e6a-878b-2b345582a771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202696305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4202696305
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1668578504
Short name T356
Test name
Test status
Simulation time 56252993 ps
CPU time 1.23 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 217140 kb
Host smart-bcad571a-2605-47a2-a2fe-2c952d0eecbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668578504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1668578504
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3999600074
Short name T508
Test name
Test status
Simulation time 30591309 ps
CPU time 0.99 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 218848 kb
Host smart-5a858880-da1e-4625-90fd-fa6f5246b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999600074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3999600074
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3864676
Short name T292
Test name
Test status
Simulation time 53366139 ps
CPU time 1.2 seconds
Started Jul 04 06:25:25 PM PDT 24
Finished Jul 04 06:25:26 PM PDT 24
Peak memory 217780 kb
Host smart-bd0bfd13-86bb-4a3d-a2c6-8381dc73c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3864676
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3376233064
Short name T31
Test name
Test status
Simulation time 20861435 ps
CPU time 1.07 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:24 PM PDT 24
Peak memory 216184 kb
Host smart-c15f61a4-ce46-4e5e-88e7-a8d7680f2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376233064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3376233064
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3852114513
Short name T590
Test name
Test status
Simulation time 18142453 ps
CPU time 1.04 seconds
Started Jul 04 06:25:27 PM PDT 24
Finished Jul 04 06:25:28 PM PDT 24
Peak memory 215632 kb
Host smart-5044a853-22ff-4f1c-b778-d6009d86382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852114513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3852114513
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.277956719
Short name T790
Test name
Test status
Simulation time 815718275 ps
CPU time 4 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 217720 kb
Host smart-7a257c3b-51b1-4be8-bf83-fd1a3795a981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277956719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.277956719
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1156644915
Short name T215
Test name
Test status
Simulation time 108155351176 ps
CPU time 1401.37 seconds
Started Jul 04 06:25:22 PM PDT 24
Finished Jul 04 06:48:48 PM PDT 24
Peak memory 226576 kb
Host smart-ccde7c34-6d07-4eb1-b8e5-4e8c30b96ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156644915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1156644915
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2869132013
Short name T144
Test name
Test status
Simulation time 31508940 ps
CPU time 1.35 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 219552 kb
Host smart-34749c38-0221-4ed3-8b97-dea799cee00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869132013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2869132013
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3508453122
Short name T495
Test name
Test status
Simulation time 13989541 ps
CPU time 0.95 seconds
Started Jul 04 06:25:49 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 206996 kb
Host smart-f7264318-614e-45ea-a901-163a49b35ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508453122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3508453122
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3519531247
Short name T199
Test name
Test status
Simulation time 34245714 ps
CPU time 0.85 seconds
Started Jul 04 06:25:24 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 216616 kb
Host smart-659a016d-a15a-4538-af8d-771e7116264a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519531247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3519531247
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2814779272
Short name T645
Test name
Test status
Simulation time 58366696 ps
CPU time 1.17 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:25:43 PM PDT 24
Peak memory 217332 kb
Host smart-77753d49-94e6-4484-a863-82115c703a4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814779272 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2814779272
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2324667893
Short name T136
Test name
Test status
Simulation time 74265489 ps
CPU time 0.97 seconds
Started Jul 04 06:25:41 PM PDT 24
Finished Jul 04 06:25:43 PM PDT 24
Peak memory 220148 kb
Host smart-9f5eb702-b648-4b7a-97a3-783bfef38272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324667893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2324667893
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1978602648
Short name T875
Test name
Test status
Simulation time 67262500 ps
CPU time 1.29 seconds
Started Jul 04 06:25:21 PM PDT 24
Finished Jul 04 06:25:23 PM PDT 24
Peak memory 219628 kb
Host smart-68c8772c-5360-42dc-b0f4-04a337d60c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978602648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1978602648
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3724564966
Short name T94
Test name
Test status
Simulation time 26266801 ps
CPU time 0.95 seconds
Started Jul 04 06:25:54 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 216160 kb
Host smart-2b52ccb6-54b4-4b95-b94c-be6fd62e012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724564966 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3724564966
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.461139130
Short name T397
Test name
Test status
Simulation time 34236920 ps
CPU time 0.87 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:45 PM PDT 24
Peak memory 215592 kb
Host smart-a5db11fa-347b-4d42-95e0-d89aa7af7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461139130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.461139130
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1589780209
Short name T483
Test name
Test status
Simulation time 246568370 ps
CPU time 4.83 seconds
Started Jul 04 06:25:43 PM PDT 24
Finished Jul 04 06:25:48 PM PDT 24
Peak memory 220320 kb
Host smart-8787efa8-7ca7-4111-95fb-d9bc32b44832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589780209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1589780209
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2026315771
Short name T360
Test name
Test status
Simulation time 10251347545 ps
CPU time 273.87 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:29:57 PM PDT 24
Peak memory 222236 kb
Host smart-ee0b4769-b370-4b90-9c85-5461596dc0e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026315771 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2026315771
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1590032090
Short name T537
Test name
Test status
Simulation time 47279753 ps
CPU time 1.1 seconds
Started Jul 04 06:25:04 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 219184 kb
Host smart-e1681059-0f67-4648-9ca9-ea03a9a72fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590032090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1590032090
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2366953061
Short name T817
Test name
Test status
Simulation time 14498972 ps
CPU time 0.96 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:24:59 PM PDT 24
Peak memory 215196 kb
Host smart-fd48b232-1bcd-4a89-b195-5382efb5851d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366953061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2366953061
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2894394884
Short name T168
Test name
Test status
Simulation time 13452621 ps
CPU time 0.9 seconds
Started Jul 04 06:25:01 PM PDT 24
Finished Jul 04 06:25:02 PM PDT 24
Peak memory 216508 kb
Host smart-564f56fe-91a6-4cd8-b34e-e642fe95ff83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894394884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2894394884
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4162094888
Short name T559
Test name
Test status
Simulation time 51951538 ps
CPU time 1.04 seconds
Started Jul 04 06:24:54 PM PDT 24
Finished Jul 04 06:24:55 PM PDT 24
Peak memory 217220 kb
Host smart-ce026bc1-a22a-41e6-85c9-5276c7dee75e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162094888 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4162094888
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3602135766
Short name T479
Test name
Test status
Simulation time 50490258 ps
CPU time 1.03 seconds
Started Jul 04 06:24:51 PM PDT 24
Finished Jul 04 06:24:52 PM PDT 24
Peak memory 219060 kb
Host smart-8063fc9f-306b-4861-84f8-af98557ba189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602135766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3602135766
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3672408598
Short name T553
Test name
Test status
Simulation time 45592105 ps
CPU time 1.31 seconds
Started Jul 04 06:24:52 PM PDT 24
Finished Jul 04 06:24:53 PM PDT 24
Peak memory 218824 kb
Host smart-57af37d9-c078-4bdb-a39b-cf43972900a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672408598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3672408598
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1592349303
Short name T917
Test name
Test status
Simulation time 22853819 ps
CPU time 1.24 seconds
Started Jul 04 06:24:55 PM PDT 24
Finished Jul 04 06:24:57 PM PDT 24
Peak memory 224320 kb
Host smart-5811788d-07de-4dc7-9347-a1a7d667dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592349303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1592349303
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2416386032
Short name T535
Test name
Test status
Simulation time 53111404 ps
CPU time 0.95 seconds
Started Jul 04 06:24:55 PM PDT 24
Finished Jul 04 06:24:56 PM PDT 24
Peak memory 207440 kb
Host smart-75238c07-6290-493a-a58e-322c0e3f9eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416386032 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2416386032
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.46750001
Short name T18
Test name
Test status
Simulation time 279298731 ps
CPU time 4.62 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:15 PM PDT 24
Peak memory 235628 kb
Host smart-ce9a0495-f9de-4940-a37a-352eb5ac621c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46750001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.46750001
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.948471184
Short name T499
Test name
Test status
Simulation time 23250082 ps
CPU time 1.01 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 215620 kb
Host smart-23fd81ee-491f-42ba-8ff6-5bdd262a630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948471184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.948471184
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2020754940
Short name T519
Test name
Test status
Simulation time 1472111678 ps
CPU time 2.56 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 217644 kb
Host smart-4867fa48-ddb7-4b64-9599-44b93a6688c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020754940 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2020754940
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.66314138
Short name T963
Test name
Test status
Simulation time 58589445374 ps
CPU time 810.21 seconds
Started Jul 04 06:24:45 PM PDT 24
Finished Jul 04 06:38:16 PM PDT 24
Peak memory 220092 kb
Host smart-481e29c5-c413-413f-aeae-59e587cf13d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66314138 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.66314138
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1799917819
Short name T145
Test name
Test status
Simulation time 124663911 ps
CPU time 1.28 seconds
Started Jul 04 06:25:49 PM PDT 24
Finished Jul 04 06:25:51 PM PDT 24
Peak memory 220132 kb
Host smart-96de1d73-945a-428f-9efa-cedc5c1ebffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799917819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1799917819
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.4112411375
Short name T349
Test name
Test status
Simulation time 24394366 ps
CPU time 1.04 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:49 PM PDT 24
Peak memory 207000 kb
Host smart-01a6ca5c-7cfa-4308-b111-f3eb8a4cf8e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112411375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4112411375
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2762446684
Short name T478
Test name
Test status
Simulation time 11900360 ps
CPU time 0.87 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 216260 kb
Host smart-c3183801-6eaa-448e-ae9d-5f617dc955aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762446684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2762446684
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3829073027
Short name T117
Test name
Test status
Simulation time 28267921 ps
CPU time 1.12 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 217324 kb
Host smart-b61f46b2-a0c1-40e2-a7cd-1b794a30e059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829073027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3829073027
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1038481746
Short name T72
Test name
Test status
Simulation time 18964170 ps
CPU time 1.04 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 218676 kb
Host smart-109c455d-2c73-4eee-a4e6-284a19da9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038481746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1038481746
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3806696128
Short name T421
Test name
Test status
Simulation time 178521523 ps
CPU time 1.6 seconds
Started Jul 04 06:25:23 PM PDT 24
Finished Jul 04 06:25:25 PM PDT 24
Peak memory 219376 kb
Host smart-315ff3d0-0671-47b8-915c-375a6fe01ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806696128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3806696128
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.531539271
Short name T921
Test name
Test status
Simulation time 27167294 ps
CPU time 0.93 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:49 PM PDT 24
Peak memory 215884 kb
Host smart-5d5156df-5196-4363-b8d1-6bfa443e8fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531539271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.531539271
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.4278616302
Short name T344
Test name
Test status
Simulation time 29890590 ps
CPU time 0.91 seconds
Started Jul 04 06:25:40 PM PDT 24
Finished Jul 04 06:25:42 PM PDT 24
Peak memory 215424 kb
Host smart-38836605-8e93-4cee-b7f4-715f910e6542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278616302 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.4278616302
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3256930101
Short name T853
Test name
Test status
Simulation time 430781407 ps
CPU time 4.58 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 217536 kb
Host smart-c4f6eabf-82eb-4389-af11-dfd1bf75439d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256930101 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3256930101
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2257390238
Short name T566
Test name
Test status
Simulation time 244716773263 ps
CPU time 701.28 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:37:28 PM PDT 24
Peak memory 224088 kb
Host smart-20173b02-524a-49d7-ac36-a8ffdd9d0c3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257390238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2257390238
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1463498360
Short name T127
Test name
Test status
Simulation time 72938013 ps
CPU time 1.14 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 220136 kb
Host smart-869ce6f0-a8d5-4280-8212-d2ebdafc4f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463498360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1463498360
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2629143343
Short name T416
Test name
Test status
Simulation time 23505447 ps
CPU time 0.82 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 207052 kb
Host smart-6b5b410c-954c-4ed7-bd49-451a7b736a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629143343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2629143343
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4152137783
Short name T650
Test name
Test status
Simulation time 54428144 ps
CPU time 1.12 seconds
Started Jul 04 06:25:54 PM PDT 24
Finished Jul 04 06:25:55 PM PDT 24
Peak memory 217220 kb
Host smart-17e1f7f5-8b12-48f5-92cb-4ce3b8ccfd90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152137783 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4152137783
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3629779091
Short name T367
Test name
Test status
Simulation time 17948569 ps
CPU time 1.04 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 218700 kb
Host smart-85934fba-f7bb-4316-acf0-1af16a3c6309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629779091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3629779091
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4118136922
Short name T299
Test name
Test status
Simulation time 57691907 ps
CPU time 1.48 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:47 PM PDT 24
Peak memory 219048 kb
Host smart-779ac020-7da4-4796-85d0-d71a17716837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118136922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4118136922
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.264383782
Short name T34
Test name
Test status
Simulation time 20831319 ps
CPU time 1.06 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 216096 kb
Host smart-36088e30-18d1-4e83-99f4-91a30fea05f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264383782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.264383782
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3492875629
Short name T732
Test name
Test status
Simulation time 30836704 ps
CPU time 0.92 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 215660 kb
Host smart-c2c5aed4-9f98-4f9f-8c5a-655664a65bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492875629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3492875629
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3365216361
Short name T833
Test name
Test status
Simulation time 618747573 ps
CPU time 5.19 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 218796 kb
Host smart-ffb7b8bf-068e-49aa-a986-81292bb841a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365216361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3365216361
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3986354048
Short name T727
Test name
Test status
Simulation time 37300611409 ps
CPU time 901.47 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:40:53 PM PDT 24
Peak memory 219532 kb
Host smart-9828440e-1fde-4277-90f6-ccc2c3de5f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986354048 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3986354048
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1416142401
Short name T534
Test name
Test status
Simulation time 62274758 ps
CPU time 1.19 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 219176 kb
Host smart-0cb1adc1-343d-4a5b-8778-6d94f8e6520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416142401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1416142401
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.634355269
Short name T456
Test name
Test status
Simulation time 50094011 ps
CPU time 0.88 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:52 PM PDT 24
Peak memory 206980 kb
Host smart-60b562a0-79e5-485f-806d-740a02208961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634355269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.634355269
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2123984478
Short name T192
Test name
Test status
Simulation time 15649591 ps
CPU time 0.85 seconds
Started Jul 04 06:25:45 PM PDT 24
Finished Jul 04 06:25:46 PM PDT 24
Peak memory 216536 kb
Host smart-9d5fac51-e11b-4ce9-93fb-e2e348f06802
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123984478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2123984478
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1405429301
Short name T138
Test name
Test status
Simulation time 70005163 ps
CPU time 1.53 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 217112 kb
Host smart-8d9b9d73-4141-4dde-9a18-303d558bf41a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405429301 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1405429301
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4273782688
Short name T204
Test name
Test status
Simulation time 46852885 ps
CPU time 1.18 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:49 PM PDT 24
Peak memory 219900 kb
Host smart-2c9fab76-7f2a-46a4-b553-588f7d19a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273782688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4273782688
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.184184348
Short name T897
Test name
Test status
Simulation time 56691864 ps
CPU time 1.92 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 218872 kb
Host smart-f0782c88-a076-417f-9c0e-ec5576f2c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184184348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.184184348
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3590804009
Short name T615
Test name
Test status
Simulation time 34000172 ps
CPU time 1.02 seconds
Started Jul 04 06:25:44 PM PDT 24
Finished Jul 04 06:25:46 PM PDT 24
Peak memory 224348 kb
Host smart-0227b19b-3c73-4b38-a721-c10a35d5707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590804009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3590804009
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3005080285
Short name T377
Test name
Test status
Simulation time 18785569 ps
CPU time 1.09 seconds
Started Jul 04 06:25:53 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 215576 kb
Host smart-55e2417e-739d-49e1-9624-e3415eeb9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005080285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3005080285
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.672554419
Short name T656
Test name
Test status
Simulation time 1780010218 ps
CPU time 5.89 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 215708 kb
Host smart-5feb4ea3-7791-4434-8cc0-f97bb798e0a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672554419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.672554419
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2128246752
Short name T382
Test name
Test status
Simulation time 135447723940 ps
CPU time 1634.75 seconds
Started Jul 04 06:25:47 PM PDT 24
Finished Jul 04 06:53:02 PM PDT 24
Peak memory 225660 kb
Host smart-336c3163-f809-4d8d-9ce8-b62c7c5935b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128246752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2128246752
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2384214796
Short name T156
Test name
Test status
Simulation time 28440917 ps
CPU time 1.15 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 219932 kb
Host smart-1528c34a-a1fe-47bc-80bc-755b687c92e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384214796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2384214796
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2326003777
Short name T964
Test name
Test status
Simulation time 51656251 ps
CPU time 0.89 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:52 PM PDT 24
Peak memory 207048 kb
Host smart-1300bd3f-9aa2-4875-8acb-80f2a9eb1107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326003777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2326003777
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4150307694
Short name T210
Test name
Test status
Simulation time 13307640 ps
CPU time 0.82 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 216560 kb
Host smart-7edf217d-fa31-47d0-8c6e-cc937f719b0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150307694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4150307694
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1463674858
Short name T522
Test name
Test status
Simulation time 50912375 ps
CPU time 1.12 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 217168 kb
Host smart-673b4019-fd23-4b9f-834b-f7ad730c3b48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463674858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1463674858
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.968265246
Short name T52
Test name
Test status
Simulation time 34166057 ps
CPU time 0.99 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:00 PM PDT 24
Peak memory 229644 kb
Host smart-731b0649-104e-43f4-b6e5-2a68e57d4569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968265246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.968265246
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.194625292
Short name T21
Test name
Test status
Simulation time 72124467 ps
CPU time 1.18 seconds
Started Jul 04 06:25:58 PM PDT 24
Finished Jul 04 06:25:59 PM PDT 24
Peak memory 219052 kb
Host smart-895863f9-436f-4791-8f5a-20b3d0d44b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194625292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.194625292
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.51371601
Short name T32
Test name
Test status
Simulation time 22575780 ps
CPU time 1.08 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 216140 kb
Host smart-73164935-0b6d-40ec-aea2-aa283f23eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51371601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.51371601
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1953713276
Short name T684
Test name
Test status
Simulation time 19485825 ps
CPU time 1.01 seconds
Started Jul 04 06:25:46 PM PDT 24
Finished Jul 04 06:25:48 PM PDT 24
Peak memory 215572 kb
Host smart-efb7a3c1-2efc-488e-a97c-bb5aec58d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953713276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1953713276
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2381829932
Short name T583
Test name
Test status
Simulation time 202784457 ps
CPU time 2.01 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:59 PM PDT 24
Peak memory 217488 kb
Host smart-71eea153-268e-476c-9e32-12b00bb3c1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381829932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2381829932
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4096650565
Short name T884
Test name
Test status
Simulation time 83765205751 ps
CPU time 1889.29 seconds
Started Jul 04 06:25:54 PM PDT 24
Finished Jul 04 06:57:24 PM PDT 24
Peak memory 226960 kb
Host smart-803d18a0-ffa7-4b78-93c8-891fc91d01c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096650565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4096650565
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3745963079
Short name T777
Test name
Test status
Simulation time 27192968 ps
CPU time 1.19 seconds
Started Jul 04 06:25:50 PM PDT 24
Finished Jul 04 06:25:52 PM PDT 24
Peak memory 220980 kb
Host smart-3eda24e9-c089-4778-95f4-60de3abbb106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745963079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3745963079
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3168676451
Short name T485
Test name
Test status
Simulation time 24248373 ps
CPU time 0.95 seconds
Started Jul 04 06:25:57 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 215188 kb
Host smart-0e1e6ab8-fee8-4207-bf50-526b951395f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168676451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3168676451
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3492164215
Short name T162
Test name
Test status
Simulation time 20620232 ps
CPU time 0.85 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:49 PM PDT 24
Peak memory 216668 kb
Host smart-85fbe9df-407b-49f2-8bff-649cc990b8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492164215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3492164215
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4152638014
Short name T526
Test name
Test status
Simulation time 34051818 ps
CPU time 1.28 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 219992 kb
Host smart-53464249-8958-45f3-b7b2-c7f44924c205
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152638014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4152638014
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2095108469
Short name T154
Test name
Test status
Simulation time 198762363 ps
CPU time 1.03 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 219960 kb
Host smart-96b6bb15-7fd1-4de0-9027-6dada7c9c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095108469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2095108469
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_intr.4110207726
Short name T29
Test name
Test status
Simulation time 32360834 ps
CPU time 0.89 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 215868 kb
Host smart-3d4ea45e-e05c-4ab2-8c12-d4bdd7359edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110207726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4110207726
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1851715341
Short name T911
Test name
Test status
Simulation time 43393963 ps
CPU time 0.88 seconds
Started Jul 04 06:25:57 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 215612 kb
Host smart-a035c3ec-2d20-4e6a-98a7-45bb2de84fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851715341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1851715341
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3458802893
Short name T794
Test name
Test status
Simulation time 84291301 ps
CPU time 2.15 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:55 PM PDT 24
Peak memory 218680 kb
Host smart-d9cd46fd-c8ec-4455-9056-fee12dd8847c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458802893 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3458802893
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.380681916
Short name T429
Test name
Test status
Simulation time 100214396382 ps
CPU time 2698.9 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 07:11:00 PM PDT 24
Peak memory 240428 kb
Host smart-a1e676c1-9d78-43c1-96d5-0bb2bb9b7dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380681916 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.380681916
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2680419374
Short name T158
Test name
Test status
Simulation time 27498323 ps
CPU time 1.07 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 219892 kb
Host smart-f504092f-171a-414c-9d9e-2825cac7222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680419374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2680419374
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.225494896
Short name T616
Test name
Test status
Simulation time 38316571 ps
CPU time 0.84 seconds
Started Jul 04 06:25:51 PM PDT 24
Finished Jul 04 06:25:53 PM PDT 24
Peak memory 207084 kb
Host smart-bc630506-0bad-4ef1-bbaa-53af0148d3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225494896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.225494896
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3887388343
Short name T406
Test name
Test status
Simulation time 20181672 ps
CPU time 0.9 seconds
Started Jul 04 06:25:50 PM PDT 24
Finished Jul 04 06:25:51 PM PDT 24
Peak memory 215736 kb
Host smart-cf8f29ed-ffca-42ba-be6a-3ad7005525fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887388343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3887388343
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.370958375
Short name T78
Test name
Test status
Simulation time 73052458 ps
CPU time 1.11 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 217116 kb
Host smart-10a5e246-04da-4af3-9c98-d781fc312a2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370958375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.370958375
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3116485393
Short name T922
Test name
Test status
Simulation time 56170474 ps
CPU time 1.1 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 224240 kb
Host smart-4250242c-73f1-4030-958d-a1418a7261f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116485393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3116485393
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.824582685
Short name T682
Test name
Test status
Simulation time 67886163 ps
CPU time 1.35 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 217456 kb
Host smart-d069e4c4-c819-4e74-82b7-6fbdb8656d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824582685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.824582685
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3822271126
Short name T696
Test name
Test status
Simulation time 36619804 ps
CPU time 0.92 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 215700 kb
Host smart-6ecea7cd-c413-48e5-b1f9-f86b0119b814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822271126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3822271126
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.498303097
Short name T335
Test name
Test status
Simulation time 18963537 ps
CPU time 0.99 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 215576 kb
Host smart-10feeeae-a653-478a-81c9-b786ed0c9b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498303097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.498303097
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1061096763
Short name T789
Test name
Test status
Simulation time 669795023 ps
CPU time 2.65 seconds
Started Jul 04 06:25:53 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 215652 kb
Host smart-aa00b553-fa79-47ef-9895-6115158c86fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061096763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1061096763
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3425182369
Short name T217
Test name
Test status
Simulation time 56281543565 ps
CPU time 1251.4 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:46:51 PM PDT 24
Peak memory 223988 kb
Host smart-2a132c5f-011b-4d67-9fad-72dc02a7bb2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425182369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3425182369
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3088339039
Short name T570
Test name
Test status
Simulation time 41673847 ps
CPU time 1.13 seconds
Started Jul 04 06:25:50 PM PDT 24
Finished Jul 04 06:25:51 PM PDT 24
Peak memory 220152 kb
Host smart-486fd13d-8009-45ee-8fe2-dd1a966553f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088339039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3088339039
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.550681814
Short name T751
Test name
Test status
Simulation time 67582178 ps
CPU time 1.2 seconds
Started Jul 04 06:25:52 PM PDT 24
Finished Jul 04 06:25:54 PM PDT 24
Peak memory 207140 kb
Host smart-61cfc68b-23d5-4b7b-ac91-479edb1eaa08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550681814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.550681814
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1326696512
Short name T409
Test name
Test status
Simulation time 40060690 ps
CPU time 0.87 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 216268 kb
Host smart-ba3712d7-b108-4b51-9036-3f1a634faf6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326696512 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1326696512
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.2270739953
Short name T149
Test name
Test status
Simulation time 60158105 ps
CPU time 0.96 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 224100 kb
Host smart-7d4f66e9-142a-4377-b9c9-2d6838fc350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270739953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2270739953
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2666141053
Short name T339
Test name
Test status
Simulation time 158330043 ps
CPU time 2.73 seconds
Started Jul 04 06:25:57 PM PDT 24
Finished Jul 04 06:26:00 PM PDT 24
Peak memory 220016 kb
Host smart-f0ff8e2a-2fdb-492a-a7c4-aa021cfa3451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666141053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2666141053
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3854798248
Short name T756
Test name
Test status
Simulation time 37888355 ps
CPU time 0.91 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 215856 kb
Host smart-d10af663-4b99-4e60-9c0b-27429ad03b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854798248 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3854798248
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2344311249
Short name T337
Test name
Test status
Simulation time 47337191 ps
CPU time 0.9 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 215612 kb
Host smart-f403fee6-ff73-450f-be14-ff2783b4ebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344311249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2344311249
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.363434629
Short name T728
Test name
Test status
Simulation time 161885162 ps
CPU time 1.41 seconds
Started Jul 04 06:25:48 PM PDT 24
Finished Jul 04 06:25:50 PM PDT 24
Peak memory 217632 kb
Host smart-eb074471-fc8b-4bff-94ec-f4b5397c9e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363434629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.363434629
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.1130392529
Short name T84
Test name
Test status
Simulation time 95092503 ps
CPU time 1.03 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 220324 kb
Host smart-0718ee81-c6a4-4e06-920b-7d3645c0aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130392529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1130392529
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1572027399
Short name T667
Test name
Test status
Simulation time 58537623 ps
CPU time 0.89 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 207052 kb
Host smart-9dd6e398-89c3-4256-b97a-5f24249ef97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572027399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1572027399
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3646306772
Short name T143
Test name
Test status
Simulation time 41105672 ps
CPU time 1.12 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 217184 kb
Host smart-ed3a2f2a-1b2f-44bb-9050-3da154c8ba07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646306772 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3646306772
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1178687271
Short name T516
Test name
Test status
Simulation time 72167321 ps
CPU time 1.2 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 225836 kb
Host smart-d7fbe3f9-5ce6-4e3b-9be9-a162c2bbccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178687271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1178687271
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.251372584
Short name T96
Test name
Test status
Simulation time 77414623 ps
CPU time 1.14 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 217708 kb
Host smart-b24f5ccb-70ea-4515-8854-7d000bafe36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251372584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.251372584
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2643536336
Short name T927
Test name
Test status
Simulation time 24855838 ps
CPU time 0.96 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 216184 kb
Host smart-136c877d-eedf-4b30-a3ba-50ebceee420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643536336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2643536336
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1883209505
Short name T484
Test name
Test status
Simulation time 107689002 ps
CPU time 0.89 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 215616 kb
Host smart-ec12d3d5-4478-4845-99d1-c9c59519f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883209505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1883209505
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4084537473
Short name T885
Test name
Test status
Simulation time 468459758 ps
CPU time 5.07 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 217448 kb
Host smart-bd6ba5fd-16cb-4eaf-a1f4-f5a0105388cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084537473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4084537473
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3184647130
Short name T970
Test name
Test status
Simulation time 121499181873 ps
CPU time 1318.46 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:48:05 PM PDT 24
Peak memory 224196 kb
Host smart-9b0c12e5-d258-424f-87af-db141ff50915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184647130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3184647130
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1604061890
Short name T265
Test name
Test status
Simulation time 68723952 ps
CPU time 1.12 seconds
Started Jul 04 06:25:58 PM PDT 24
Finished Jul 04 06:25:59 PM PDT 24
Peak memory 221140 kb
Host smart-f3bc4b83-9746-48fc-b243-3e40479d039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604061890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1604061890
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1012118005
Short name T58
Test name
Test status
Simulation time 48778843 ps
CPU time 0.87 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 206976 kb
Host smart-ebe844c4-5c61-4b85-b911-c0eb9f4ace98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012118005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1012118005
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2513541571
Short name T89
Test name
Test status
Simulation time 33518159 ps
CPU time 0.83 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 216336 kb
Host smart-80dfc32d-4d9e-47d9-962c-4e8d26929479
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513541571 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2513541571
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2790953050
Short name T392
Test name
Test status
Simulation time 41237721 ps
CPU time 1.25 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 218588 kb
Host smart-877c42ed-c8af-4126-8699-8a5e6820e3ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790953050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2790953050
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.341031398
Short name T798
Test name
Test status
Simulation time 23535727 ps
CPU time 0.99 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 218932 kb
Host smart-1a2451ea-b6b4-45b3-9015-b1c1bf98c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341031398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.341031398
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.721773389
Short name T227
Test name
Test status
Simulation time 203472645 ps
CPU time 1.18 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 220328 kb
Host smart-7eea724b-a2bc-4abb-b21b-b6c9eed9d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721773389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.721773389
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2905763835
Short name T974
Test name
Test status
Simulation time 31708454 ps
CPU time 0.95 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 215852 kb
Host smart-881108bb-b2b3-4fe6-8d5e-5038ad277869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905763835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2905763835
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2317251567
Short name T359
Test name
Test status
Simulation time 42965033 ps
CPU time 0.91 seconds
Started Jul 04 06:25:58 PM PDT 24
Finished Jul 04 06:25:59 PM PDT 24
Peak memory 215616 kb
Host smart-231c8abb-45e8-44ab-85c9-56b3093e2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317251567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2317251567
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3057336980
Short name T307
Test name
Test status
Simulation time 252136905 ps
CPU time 5.16 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 215640 kb
Host smart-80e67453-352a-42e1-a35e-9fe39c270316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057336980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3057336980
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1798013946
Short name T905
Test name
Test status
Simulation time 91437764618 ps
CPU time 2331.85 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 07:05:05 PM PDT 24
Peak memory 231624 kb
Host smart-6c2a16b8-8c51-4f2e-a144-462ced60ddf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798013946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1798013946
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4010710440
Short name T936
Test name
Test status
Simulation time 44889746 ps
CPU time 1.14 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 220000 kb
Host smart-0a0a7c3b-e356-42f5-90b7-50766183c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010710440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4010710440
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2201697765
Short name T361
Test name
Test status
Simulation time 40197285 ps
CPU time 0.85 seconds
Started Jul 04 06:25:57 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 206880 kb
Host smart-19e13603-d148-4e33-ae80-df1c5836ba34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201697765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2201697765
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.356987449
Short name T188
Test name
Test status
Simulation time 11731890 ps
CPU time 0.85 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 216568 kb
Host smart-aae4a72c-bac9-4d00-8264-6918ebc4c8a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356987449 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.356987449
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1904406152
Short name T976
Test name
Test status
Simulation time 71153245 ps
CPU time 1.42 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 217100 kb
Host smart-e059d7bf-2e0c-42e3-aecd-a0a883c6827f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904406152 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1904406152
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4045002960
Short name T702
Test name
Test status
Simulation time 29475617 ps
CPU time 0.95 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 224036 kb
Host smart-678b0826-ef7b-4fb9-8fbe-a456a095c906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045002960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4045002960
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1022377853
Short name T828
Test name
Test status
Simulation time 51872755 ps
CPU time 1.63 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 217604 kb
Host smart-07e9bf28-5393-4e61-9a29-60df4b41256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022377853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1022377853
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1235179190
Short name T30
Test name
Test status
Simulation time 48594132 ps
CPU time 0.82 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 215880 kb
Host smart-9df79378-2742-45e5-80d4-778ccac9e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235179190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1235179190
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3954385338
Short name T799
Test name
Test status
Simulation time 17887311 ps
CPU time 1.03 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 215580 kb
Host smart-ac6a7646-7a1e-4481-a637-b7709df22a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954385338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3954385338
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2352107444
Short name T476
Test name
Test status
Simulation time 1682512368 ps
CPU time 5.27 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 220392 kb
Host smart-fd7a0a60-d787-4862-8691-501d8d8bc72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352107444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2352107444
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3431376108
Short name T35
Test name
Test status
Simulation time 25594753839 ps
CPU time 171.8 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:28:54 PM PDT 24
Peak memory 222020 kb
Host smart-813248b2-2526-4651-9d0f-3c4946491a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431376108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3431376108
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1084392083
Short name T178
Test name
Test status
Simulation time 28989460 ps
CPU time 1.09 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 219192 kb
Host smart-0795f3ef-75b0-416c-b6c5-d19871ded875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084392083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1084392083
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3346491412
Short name T354
Test name
Test status
Simulation time 26303936 ps
CPU time 0.91 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 207068 kb
Host smart-b5e1f488-dc90-4e46-9c0d-7a91f661cb5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346491412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3346491412
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3649836508
Short name T451
Test name
Test status
Simulation time 19594345 ps
CPU time 0.94 seconds
Started Jul 04 06:25:02 PM PDT 24
Finished Jul 04 06:25:03 PM PDT 24
Peak memory 216708 kb
Host smart-38f77ffc-477d-490e-928c-06203a229e32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649836508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3649836508
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.64052269
Short name T492
Test name
Test status
Simulation time 108685543 ps
CPU time 1.13 seconds
Started Jul 04 06:25:07 PM PDT 24
Finished Jul 04 06:25:08 PM PDT 24
Peak memory 218600 kb
Host smart-6c04614c-59c6-4260-a1c5-80546f3a321b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64052269 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.64052269
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.887723490
Short name T958
Test name
Test status
Simulation time 58055574 ps
CPU time 1.37 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 225912 kb
Host smart-416c634c-5a55-41d3-a105-4c436cc84182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887723490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.887723490
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2972608541
Short name T636
Test name
Test status
Simulation time 46916333 ps
CPU time 1.26 seconds
Started Jul 04 06:25:03 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 217472 kb
Host smart-cfb9f815-e7e6-4abe-8e0c-82d667fc05d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972608541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2972608541
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.994766154
Short name T407
Test name
Test status
Simulation time 31553196 ps
CPU time 0.89 seconds
Started Jul 04 06:25:04 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 215972 kb
Host smart-07ca910d-19e4-49ce-9490-98f44cdd5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994766154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.994766154
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2220391566
Short name T26
Test name
Test status
Simulation time 104410370 ps
CPU time 0.94 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 207388 kb
Host smart-dc98fb89-e870-4c0a-a054-015cadd8ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220391566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2220391566
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1484602977
Short name T710
Test name
Test status
Simulation time 28966749 ps
CPU time 0.96 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 215632 kb
Host smart-2a51f630-317e-4965-bc76-b2c0782834c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484602977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1484602977
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1482336384
Short name T829
Test name
Test status
Simulation time 551749568 ps
CPU time 3.05 seconds
Started Jul 04 06:25:03 PM PDT 24
Finished Jul 04 06:25:06 PM PDT 24
Peak memory 220176 kb
Host smart-425ae184-2d21-4d8b-8c59-90f2f900dc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482336384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1482336384
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.37043525
Short name T759
Test name
Test status
Simulation time 989908985474 ps
CPU time 2149.38 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 07:00:58 PM PDT 24
Peak memory 225600 kb
Host smart-4c4909da-a916-43ca-8c59-23f66e971611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37043525 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.37043525
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.899718364
Short name T101
Test name
Test status
Simulation time 29055871 ps
CPU time 1.21 seconds
Started Jul 04 06:25:55 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 218852 kb
Host smart-3346b34a-6b53-4515-82bc-201edd946004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899718364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.899718364
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3170522732
Short name T148
Test name
Test status
Simulation time 19742166 ps
CPU time 1.33 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 224284 kb
Host smart-7b4797b9-fdfa-4660-8567-7a83f4413112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170522732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3170522732
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4039233354
Short name T842
Test name
Test status
Simulation time 116435716 ps
CPU time 1.38 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 219388 kb
Host smart-22b3b048-36cd-4770-9f21-2c7cbaeaec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039233354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4039233354
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.4265629951
Short name T554
Test name
Test status
Simulation time 98501760 ps
CPU time 1.26 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 215932 kb
Host smart-91dc222f-9a6d-4866-859f-f7978e6f4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265629951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.4265629951
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.43256655
Short name T111
Test name
Test status
Simulation time 116352408 ps
CPU time 1.07 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 229848 kb
Host smart-7664e58a-50dc-4b8b-b165-020829627b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43256655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.43256655
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2763914140
Short name T729
Test name
Test status
Simulation time 65126634 ps
CPU time 1.63 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 219032 kb
Host smart-6ba0abfe-f44c-4065-b88a-f7ef8dcdf072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763914140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2763914140
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2932935405
Short name T541
Test name
Test status
Simulation time 25995436 ps
CPU time 1.19 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 218912 kb
Host smart-829ee6ea-71b3-48e8-85e5-f72f5836e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932935405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2932935405
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3661068078
Short name T166
Test name
Test status
Simulation time 19250442 ps
CPU time 1.04 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218748 kb
Host smart-7bfee6f4-ee92-48f0-b0ba-3513ee63cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661068078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3661068078
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3310494566
Short name T568
Test name
Test status
Simulation time 44111969 ps
CPU time 1.27 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 219164 kb
Host smart-5b3ebc68-1263-4ad8-8311-969d78ad1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310494566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3310494566
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3091289329
Short name T737
Test name
Test status
Simulation time 27894365 ps
CPU time 1.28 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 221096 kb
Host smart-2293bb2e-ebbc-4910-9d39-2a34d611d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091289329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3091289329
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2016039877
Short name T175
Test name
Test status
Simulation time 19360239 ps
CPU time 1.06 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 218900 kb
Host smart-06fa552d-6cee-4158-acad-5b38445a674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016039877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2016039877
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2299558681
Short name T330
Test name
Test status
Simulation time 57201050 ps
CPU time 1.02 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 217528 kb
Host smart-c21dd368-8a66-4685-ac23-d940754186d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299558681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2299558681
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1362709788
Short name T449
Test name
Test status
Simulation time 22073648 ps
CPU time 1.09 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218688 kb
Host smart-92530b7b-ab3d-4f58-bad5-4476557392ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362709788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1362709788
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3076900617
Short name T17
Test name
Test status
Simulation time 81073898 ps
CPU time 1.15 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 226048 kb
Host smart-1c036578-b110-48cc-8122-a7070545927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076900617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3076900617
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4109493044
Short name T419
Test name
Test status
Simulation time 33647809 ps
CPU time 1.42 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:58 PM PDT 24
Peak memory 217584 kb
Host smart-fab5573d-484f-4b99-852a-fc2e04fa9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109493044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4109493044
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2073872618
Short name T564
Test name
Test status
Simulation time 45841932 ps
CPU time 1.15 seconds
Started Jul 04 06:25:54 PM PDT 24
Finished Jul 04 06:25:55 PM PDT 24
Peak memory 219988 kb
Host smart-1c913994-674e-4297-9358-08c12e841636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073872618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2073872618
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3834935623
Short name T51
Test name
Test status
Simulation time 49377643 ps
CPU time 1.09 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 224348 kb
Host smart-2b28722f-c928-451d-b68f-0eb975cfebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834935623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3834935623
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3639320266
Short name T808
Test name
Test status
Simulation time 59576875 ps
CPU time 1.34 seconds
Started Jul 04 06:26:00 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 219152 kb
Host smart-8f5ac390-50dd-4d36-be8c-f9d82e977955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639320266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3639320266
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1238133254
Short name T813
Test name
Test status
Simulation time 25176616 ps
CPU time 1.18 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 219688 kb
Host smart-c1399f0d-8d44-44c0-8789-bd28913b3e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238133254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1238133254
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.220606381
Short name T698
Test name
Test status
Simulation time 27910753 ps
CPU time 0.9 seconds
Started Jul 04 06:26:20 PM PDT 24
Finished Jul 04 06:26:21 PM PDT 24
Peak memory 215804 kb
Host smart-48356ecf-53a4-4810-a804-24e5e49beff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220606381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.220606381
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2149895165
Short name T375
Test name
Test status
Simulation time 51722630 ps
CPU time 1.86 seconds
Started Jul 04 06:26:14 PM PDT 24
Finished Jul 04 06:26:17 PM PDT 24
Peak memory 219172 kb
Host smart-0456176b-72b7-4dda-be90-9b0413443a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149895165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2149895165
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.326852819
Short name T287
Test name
Test status
Simulation time 40603835 ps
CPU time 1.1 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 220284 kb
Host smart-50324bc9-4a8c-4798-8df1-b1a3d7a8fa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326852819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.326852819
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1007816397
Short name T147
Test name
Test status
Simulation time 39482353 ps
CPU time 0.84 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 218612 kb
Host smart-c4caeb78-5be3-472c-84b1-fdf859aaec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007816397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1007816397
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.852657254
Short name T752
Test name
Test status
Simulation time 38750630 ps
CPU time 1.49 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:01 PM PDT 24
Peak memory 217792 kb
Host smart-c09355c1-bb18-4b53-9e5d-967a9a19ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852657254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.852657254
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3260543809
Short name T888
Test name
Test status
Simulation time 32999681 ps
CPU time 0.83 seconds
Started Jul 04 06:26:21 PM PDT 24
Finished Jul 04 06:26:22 PM PDT 24
Peak memory 218252 kb
Host smart-1ccc674b-cd11-48de-973d-9cae3968cab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260543809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3260543809
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2404883268
Short name T294
Test name
Test status
Simulation time 40188223 ps
CPU time 1.37 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218696 kb
Host smart-d6f11572-df71-4b1e-8713-17555bf8d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404883268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2404883268
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3435876474
Short name T131
Test name
Test status
Simulation time 105763479 ps
CPU time 1.33 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 216052 kb
Host smart-0b29751e-5489-4c7e-b9f7-663c2516815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435876474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3435876474
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3655396139
Short name T70
Test name
Test status
Simulation time 26016380 ps
CPU time 0.95 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 219024 kb
Host smart-6cf66d82-0cc8-4abb-ab88-0296499b20d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655396139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3655396139
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.302359545
Short name T786
Test name
Test status
Simulation time 103381060 ps
CPU time 1.26 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 217764 kb
Host smart-4351a56e-dcec-4959-834d-c12637b23181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302359545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.302359545
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4060576382
Short name T768
Test name
Test status
Simulation time 60458591 ps
CPU time 1.3 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 216052 kb
Host smart-8ceb1c49-ee03-4212-bb96-6803104a2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060576382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4060576382
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3894293408
Short name T22
Test name
Test status
Simulation time 24569421 ps
CPU time 0.85 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215168 kb
Host smart-fedf8d24-1260-4141-8cd3-680a0f85b3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894293408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3894293408
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1281739791
Short name T41
Test name
Test status
Simulation time 59716483 ps
CPU time 0.85 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 216512 kb
Host smart-43f49e6e-e254-42d4-b369-a6833be3777b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281739791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1281739791
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3972733764
Short name T63
Test name
Test status
Simulation time 29991555 ps
CPU time 1.12 seconds
Started Jul 04 06:25:16 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 217212 kb
Host smart-596a560a-1ff1-4a96-b994-0562f0923179
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972733764 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3972733764
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2209720188
Short name T9
Test name
Test status
Simulation time 61286037 ps
CPU time 1.02 seconds
Started Jul 04 06:24:52 PM PDT 24
Finished Jul 04 06:24:54 PM PDT 24
Peak memory 220724 kb
Host smart-7fc946d3-cd3d-4088-af6a-3d0e6cba3f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209720188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2209720188
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2924058359
Short name T895
Test name
Test status
Simulation time 71960692 ps
CPU time 1.15 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 217508 kb
Host smart-f505fb11-8844-4870-90d1-ead8832fa38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924058359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2924058359
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4229192354
Short name T942
Test name
Test status
Simulation time 20990860 ps
CPU time 1.07 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 216184 kb
Host smart-bcd1e48b-ca10-4d8f-a7fd-a3e8389a8aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229192354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4229192354
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.851770873
Short name T59
Test name
Test status
Simulation time 17417259 ps
CPU time 1.12 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 207436 kb
Host smart-ba6dc4dd-ef58-4640-a7b0-b6d215d92b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851770873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.851770873
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3943751569
Short name T231
Test name
Test status
Simulation time 289654173 ps
CPU time 5.67 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 215556 kb
Host smart-56f42e02-264e-4bca-bbb4-5ff6d6766f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943751569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3943751569
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1224051093
Short name T507
Test name
Test status
Simulation time 32895642825 ps
CPU time 361.97 seconds
Started Jul 04 06:24:56 PM PDT 24
Finished Jul 04 06:30:58 PM PDT 24
Peak memory 224028 kb
Host smart-5b7fab5c-32c4-4eee-b88e-87713083e4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224051093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1224051093
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3029200179
Short name T889
Test name
Test status
Simulation time 45325598 ps
CPU time 1.12 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 218720 kb
Host smart-5d9e38b4-ab2a-454e-9114-9513cbb8f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029200179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3029200179
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3820281121
Short name T487
Test name
Test status
Simulation time 36415623 ps
CPU time 1.55 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:10 PM PDT 24
Peak memory 226036 kb
Host smart-ad5c0b1c-0f2f-488e-993d-65b39d9c5902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820281121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3820281121
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.599848239
Short name T308
Test name
Test status
Simulation time 287162862 ps
CPU time 1.71 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 219544 kb
Host smart-106cb82c-2c14-464e-b5f4-51496bc709be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599848239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.599848239
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3357445188
Short name T414
Test name
Test status
Simulation time 72533874 ps
CPU time 1.15 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 219240 kb
Host smart-f4871a2f-fc21-4f77-9aee-9737c14f812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357445188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3357445188
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.57187063
Short name T7
Test name
Test status
Simulation time 57154097 ps
CPU time 0.88 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218652 kb
Host smart-d26fa707-ac63-4592-baf0-ba2242bdee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57187063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.57187063
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3696952061
Short name T211
Test name
Test status
Simulation time 617424746 ps
CPU time 4.79 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 220268 kb
Host smart-7181eb31-c809-42a9-8875-200f714223a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696952061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3696952061
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.260885961
Short name T742
Test name
Test status
Simulation time 24867957 ps
CPU time 1.14 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 220000 kb
Host smart-129f573e-7357-47f6-bbff-b6bef1e39b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260885961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.260885961
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3097933163
Short name T123
Test name
Test status
Simulation time 22889951 ps
CPU time 1.17 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 219996 kb
Host smart-712eda20-b8c4-423e-a500-74ce0b27cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097933163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3097933163
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3388611778
Short name T791
Test name
Test status
Simulation time 42873377 ps
CPU time 1.09 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 217664 kb
Host smart-e86d7879-d327-4d36-bfdc-e85404293e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388611778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3388611778
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3148204052
Short name T329
Test name
Test status
Simulation time 63873729 ps
CPU time 1.07 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 219904 kb
Host smart-59699d82-211d-4cbc-a69b-b7bf6c87a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148204052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3148204052
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3569530902
Short name T54
Test name
Test status
Simulation time 20251655 ps
CPU time 1.21 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 224264 kb
Host smart-e7f23376-a508-4415-a323-c4db32570b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569530902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3569530902
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2541906779
Short name T660
Test name
Test status
Simulation time 93062133 ps
CPU time 1.06 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 219280 kb
Host smart-4d00ff78-32c2-4308-ace5-a38a69016edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541906779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2541906779
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2770867995
Short name T457
Test name
Test status
Simulation time 25121219 ps
CPU time 1.13 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218840 kb
Host smart-1f1bcb1c-9ebf-4577-ae4d-56a14bf69410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770867995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2770867995
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1833769166
Short name T134
Test name
Test status
Simulation time 22989530 ps
CPU time 1.31 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 224264 kb
Host smart-0cb41571-b75f-4e8e-a261-c28984107371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833769166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1833769166
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.56840072
Short name T563
Test name
Test status
Simulation time 83972654 ps
CPU time 1.36 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 219124 kb
Host smart-a0c5d46f-be87-4104-a349-14c76eace1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56840072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.56840072
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3131572254
Short name T524
Test name
Test status
Simulation time 296373052 ps
CPU time 1.45 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 220888 kb
Host smart-e331c603-8c0d-4c2d-b7b8-7430db58b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131572254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3131572254
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.171020306
Short name T877
Test name
Test status
Simulation time 18895122 ps
CPU time 1 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 218564 kb
Host smart-b7c62c12-ed2f-4951-b0cb-101d078d3ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171020306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.171020306
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1176923437
Short name T396
Test name
Test status
Simulation time 54042265 ps
CPU time 1.71 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 219200 kb
Host smart-d09eeb14-96e4-4a13-9bdb-e2c12d786e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176923437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1176923437
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1584546198
Short name T671
Test name
Test status
Simulation time 52713218 ps
CPU time 1.22 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 216028 kb
Host smart-ddc4a4ad-6c8d-4836-a916-9c1ec5552bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584546198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1584546198
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.1426781318
Short name T984
Test name
Test status
Simulation time 228311389 ps
CPU time 1.24 seconds
Started Jul 04 06:26:35 PM PDT 24
Finished Jul 04 06:26:36 PM PDT 24
Peak memory 218728 kb
Host smart-ebbd8a16-4461-4e1e-8ea7-f610641db2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426781318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1426781318
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1627946934
Short name T324
Test name
Test status
Simulation time 48523523 ps
CPU time 1.16 seconds
Started Jul 04 06:25:58 PM PDT 24
Finished Jul 04 06:25:59 PM PDT 24
Peak memory 220180 kb
Host smart-e6b941e6-f6d1-44d9-b89b-2e83aca32227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627946934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1627946934
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2599201835
Short name T714
Test name
Test status
Simulation time 30285463 ps
CPU time 1.23 seconds
Started Jul 04 06:26:18 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 219948 kb
Host smart-0a922f8e-5a37-4859-be9e-462a36afd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599201835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2599201835
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3593160849
Short name T871
Test name
Test status
Simulation time 36065180 ps
CPU time 1.61 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 218732 kb
Host smart-fbb2294e-f1c6-4ab5-9bbe-e3ef5354dd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593160849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3593160849
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.4049932558
Short name T208
Test name
Test status
Simulation time 25147401 ps
CPU time 1.16 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 216036 kb
Host smart-14e7e8ac-955e-4a04-9005-a6de888d4ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049932558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.4049932558
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2525943868
Short name T413
Test name
Test status
Simulation time 28009541 ps
CPU time 0.96 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 232880 kb
Host smart-339e4af5-6c57-45e2-a16e-51866381bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525943868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2525943868
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.139214387
Short name T346
Test name
Test status
Simulation time 202130208 ps
CPU time 1.88 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 219588 kb
Host smart-f4021b92-9b00-4faa-9c49-e8510101e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139214387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.139214387
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3326446999
Short name T327
Test name
Test status
Simulation time 42540273 ps
CPU time 1.26 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 220132 kb
Host smart-785ddc15-9cba-4375-9d0b-8c695922428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326446999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3326446999
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2273374869
Short name T189
Test name
Test status
Simulation time 19137821 ps
CPU time 1.01 seconds
Started Jul 04 06:26:13 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 215772 kb
Host smart-31d0a6de-1eb2-412b-bc88-eca953d0037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273374869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2273374869
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2108286123
Short name T968
Test name
Test status
Simulation time 39136681 ps
CPU time 1.51 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 218024 kb
Host smart-55c652e1-2e6a-4a37-9a29-bb6891c7ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108286123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2108286123
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1613774227
Short name T83
Test name
Test status
Simulation time 47226612 ps
CPU time 1.11 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:11 PM PDT 24
Peak memory 221068 kb
Host smart-10d8c35c-70e5-42bf-9132-5d0c04ffeeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613774227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1613774227
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2647645545
Short name T973
Test name
Test status
Simulation time 61619443 ps
CPU time 0.9 seconds
Started Jul 04 06:25:01 PM PDT 24
Finished Jul 04 06:25:02 PM PDT 24
Peak memory 207020 kb
Host smart-c0c6cf27-3f36-4d87-9aa2-3859848701cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647645545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2647645545
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1418645724
Short name T150
Test name
Test status
Simulation time 13858990 ps
CPU time 0.92 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 215880 kb
Host smart-36d35b47-663a-4c99-ad82-33e616eeb815
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418645724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1418645724
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.565810365
Short name T694
Test name
Test status
Simulation time 314844185 ps
CPU time 1.14 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:24:59 PM PDT 24
Peak memory 217180 kb
Host smart-9e4b669b-2502-4302-802d-0e29202df692
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565810365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.565810365
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.16131510
Short name T619
Test name
Test status
Simulation time 18184837 ps
CPU time 1.17 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 218728 kb
Host smart-56b02c7b-7cb8-4cc8-81fd-5469dbb964df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16131510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.16131510
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.353235159
Short name T596
Test name
Test status
Simulation time 270920628 ps
CPU time 3.91 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:04 PM PDT 24
Peak memory 220452 kb
Host smart-eebbc9bd-7ef5-47db-a77c-fdd4571fdc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353235159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.353235159
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1359788418
Short name T27
Test name
Test status
Simulation time 28035584 ps
CPU time 0.96 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:01 PM PDT 24
Peak memory 216204 kb
Host smart-4351ec5f-95d0-4833-8b16-04719b7c7de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359788418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1359788418
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2180211642
Short name T323
Test name
Test status
Simulation time 29184947 ps
CPU time 0.99 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 207408 kb
Host smart-5fca444b-be56-4f33-a1d9-9b98b39cda0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180211642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2180211642
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2563450993
Short name T822
Test name
Test status
Simulation time 47036923 ps
CPU time 0.89 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 215624 kb
Host smart-5d872f5a-0b13-4a01-846c-f9c040ab64a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563450993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2563450993
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2702967511
Short name T401
Test name
Test status
Simulation time 721139673 ps
CPU time 4.73 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:17 PM PDT 24
Peak memory 220392 kb
Host smart-15d74cfd-ef25-4008-8745-acf0067e92ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702967511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2702967511
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1036054365
Short name T804
Test name
Test status
Simulation time 76822954115 ps
CPU time 1766.01 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:54:25 PM PDT 24
Peak memory 227996 kb
Host smart-eff93d80-5185-4bc8-bef9-6439ece5bf2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036054365 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1036054365
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.318487250
Short name T121
Test name
Test status
Simulation time 193561383 ps
CPU time 1.18 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218888 kb
Host smart-d16cb8ab-ac4e-4080-b450-7fade86cfc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318487250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.318487250
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2870377873
Short name T956
Test name
Test status
Simulation time 23633716 ps
CPU time 0.93 seconds
Started Jul 04 06:25:56 PM PDT 24
Finished Jul 04 06:25:57 PM PDT 24
Peak memory 218728 kb
Host smart-8c0f0f0b-7201-4fab-9c09-1e520dc46d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870377873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2870377873
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3520676459
Short name T311
Test name
Test status
Simulation time 30841984 ps
CPU time 1.33 seconds
Started Jul 04 06:26:26 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 215600 kb
Host smart-f060ee65-3030-4bcd-89a6-e435fff3f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520676459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3520676459
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.4036047392
Short name T236
Test name
Test status
Simulation time 44663497 ps
CPU time 1.19 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 219828 kb
Host smart-cbcd0f49-7105-4234-a908-a1a21ad37aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036047392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.4036047392
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.181517731
Short name T929
Test name
Test status
Simulation time 20505171 ps
CPU time 1.07 seconds
Started Jul 04 06:26:14 PM PDT 24
Finished Jul 04 06:26:16 PM PDT 24
Peak memory 219900 kb
Host smart-319a0518-0d56-471a-b3a6-0db707844b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181517731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.181517731
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3195713198
Short name T390
Test name
Test status
Simulation time 44180696 ps
CPU time 1.2 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 219028 kb
Host smart-7f78ae88-766e-45a8-a7e2-4b2278b45a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195713198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3195713198
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2181290425
Short name T465
Test name
Test status
Simulation time 49241208 ps
CPU time 1.2 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 219976 kb
Host smart-fd72c821-28dd-43b3-8ba1-4fcbbf341370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181290425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2181290425
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1782009759
Short name T197
Test name
Test status
Simulation time 33839461 ps
CPU time 1.22 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 219992 kb
Host smart-77b235f6-94d7-43b4-92cb-e034733ca165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782009759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1782009759
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3328437918
Short name T562
Test name
Test status
Simulation time 241357601 ps
CPU time 1.55 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 218924 kb
Host smart-6ff0e2a0-b42a-44f0-875f-d35a16978f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328437918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3328437918
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2371235021
Short name T796
Test name
Test status
Simulation time 38985861 ps
CPU time 1.14 seconds
Started Jul 04 06:26:30 PM PDT 24
Finished Jul 04 06:26:32 PM PDT 24
Peak memory 220956 kb
Host smart-4bbb7f56-d10c-4693-879e-cdbc4f610420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371235021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2371235021
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1963789500
Short name T781
Test name
Test status
Simulation time 19215874 ps
CPU time 1.16 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 224240 kb
Host smart-ef87d49f-6399-4b78-a306-081d3023f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963789500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1963789500
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2310634798
Short name T803
Test name
Test status
Simulation time 115419283 ps
CPU time 1.78 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 219212 kb
Host smart-62ce71c9-478c-495d-a702-9dca91a64f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310634798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2310634798
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2641193657
Short name T832
Test name
Test status
Simulation time 32556116 ps
CPU time 1.32 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 220188 kb
Host smart-f95553e2-5039-4b62-90cc-b3b7a4705f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641193657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2641193657
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2207826379
Short name T128
Test name
Test status
Simulation time 40391981 ps
CPU time 1.04 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 229916 kb
Host smart-c1c287b8-a4b2-48ef-a9dd-dc13d9725044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207826379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2207826379
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1147728771
Short name T840
Test name
Test status
Simulation time 249010816 ps
CPU time 2.96 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 220580 kb
Host smart-3ae84948-c94c-4ac2-a177-3b3eb853f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147728771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1147728771
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1761973855
Short name T734
Test name
Test status
Simulation time 42167474 ps
CPU time 1.19 seconds
Started Jul 04 06:26:17 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 221772 kb
Host smart-2e1851d0-8f6b-421d-abd6-47d136c70b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761973855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1761973855
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3218090693
Short name T124
Test name
Test status
Simulation time 90745158 ps
CPU time 0.87 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 219752 kb
Host smart-ba386e48-d62c-4bd1-95af-74dcbf2d74d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218090693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3218090693
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3154992956
Short name T662
Test name
Test status
Simulation time 20993778 ps
CPU time 1.12 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 215620 kb
Host smart-639bc2c9-0e69-4efd-ae6f-d74efcbab797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154992956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3154992956
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2879307546
Short name T173
Test name
Test status
Simulation time 39616415 ps
CPU time 1.13 seconds
Started Jul 04 06:26:41 PM PDT 24
Finished Jul 04 06:26:42 PM PDT 24
Peak memory 216028 kb
Host smart-f833e907-e69e-4bd0-bd68-812936ef5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879307546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2879307546
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3791283831
Short name T851
Test name
Test status
Simulation time 29603868 ps
CPU time 1.25 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 219964 kb
Host smart-5da57190-8f19-4a5a-a1bb-6cd9e5a6c680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791283831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3791283831
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1848814987
Short name T831
Test name
Test status
Simulation time 52791486 ps
CPU time 1.38 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 219108 kb
Host smart-b68da688-e87f-48a9-b2ea-8d824c5aac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848814987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1848814987
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3507652472
Short name T266
Test name
Test status
Simulation time 279673585 ps
CPU time 1.3 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218740 kb
Host smart-0f6db430-2eab-41ad-9dc7-c4f1bfa95f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507652472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3507652472
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3237217487
Short name T587
Test name
Test status
Simulation time 33915401 ps
CPU time 0.94 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 218708 kb
Host smart-6c84ee7f-61c8-4629-b805-597c9defcb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237217487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3237217487
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2682849862
Short name T557
Test name
Test status
Simulation time 40555557 ps
CPU time 1.44 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 218996 kb
Host smart-72fa678e-064e-42cc-b6fa-7af7e79761cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682849862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2682849862
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.178027884
Short name T673
Test name
Test status
Simulation time 24522499 ps
CPU time 1.16 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:02 PM PDT 24
Peak memory 219868 kb
Host smart-ee42df52-6bcc-46ee-95be-2a252b0dfda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178027884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.178027884
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3724071806
Short name T560
Test name
Test status
Simulation time 43857395 ps
CPU time 1.04 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 218696 kb
Host smart-8a35b986-15a7-4aaa-b3b4-9b198b357acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724071806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3724071806
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.130263490
Short name T603
Test name
Test status
Simulation time 71546811 ps
CPU time 1.12 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 217644 kb
Host smart-1b202dbd-d769-4c90-bbef-6bdaaec759f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130263490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.130263490
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2535313796
Short name T552
Test name
Test status
Simulation time 123657199 ps
CPU time 1.17 seconds
Started Jul 04 06:26:18 PM PDT 24
Finished Jul 04 06:26:19 PM PDT 24
Peak memory 219652 kb
Host smart-ad5d9645-b1d4-4be8-8c96-7234ca55f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535313796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2535313796
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1416977766
Short name T412
Test name
Test status
Simulation time 18721272 ps
CPU time 1.1 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 218836 kb
Host smart-410f7708-6096-4aae-8fcd-3c7cfa099a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416977766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1416977766
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.686674985
Short name T440
Test name
Test status
Simulation time 51691632 ps
CPU time 1.26 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 218980 kb
Host smart-b457037c-f88b-4445-ad2e-d9cf3a9c5926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686674985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.686674985
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2801099086
Short name T528
Test name
Test status
Simulation time 39686436 ps
CPU time 1.18 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 220080 kb
Host smart-17abbd48-2e07-485f-856d-4cba99e18a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801099086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2801099086
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2147556943
Short name T940
Test name
Test status
Simulation time 46197579 ps
CPU time 0.9 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:06 PM PDT 24
Peak memory 207032 kb
Host smart-ff7fb0f2-d384-4b4a-ba08-cc6d225297fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147556943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2147556943
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2822194899
Short name T191
Test name
Test status
Simulation time 25788404 ps
CPU time 0.94 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 216600 kb
Host smart-95c469ac-e1c7-4bc3-82dd-cb666aa37c4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822194899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2822194899
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1355322133
Short name T118
Test name
Test status
Simulation time 40330682 ps
CPU time 1.32 seconds
Started Jul 04 06:25:04 PM PDT 24
Finished Jul 04 06:25:05 PM PDT 24
Peak memory 217112 kb
Host smart-7e515348-f5a1-4fb5-8b49-7fc76cbdef23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355322133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1355322133
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1248947446
Short name T766
Test name
Test status
Simulation time 24156591 ps
CPU time 1.02 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:00 PM PDT 24
Peak memory 224316 kb
Host smart-b569109d-135c-4a4a-89fd-53d662a210a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248947446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1248947446
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.452175633
Short name T632
Test name
Test status
Simulation time 37509272 ps
CPU time 1.45 seconds
Started Jul 04 06:25:00 PM PDT 24
Finished Jul 04 06:25:02 PM PDT 24
Peak memory 220304 kb
Host smart-a2f7876a-58e4-4eab-a8b0-281a549db24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452175633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.452175633
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2961462400
Short name T904
Test name
Test status
Simulation time 25230151 ps
CPU time 1.02 seconds
Started Jul 04 06:25:06 PM PDT 24
Finished Jul 04 06:25:07 PM PDT 24
Peak memory 215752 kb
Host smart-1a26d239-2862-4445-addd-a5ab63cccf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961462400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2961462400
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4246977658
Short name T607
Test name
Test status
Simulation time 19487713 ps
CPU time 0.96 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:06 PM PDT 24
Peak memory 207452 kb
Host smart-6150f6be-e5d6-4a41-82c4-9642e87a7639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246977658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4246977658
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3613361618
Short name T574
Test name
Test status
Simulation time 16032181 ps
CPU time 1 seconds
Started Jul 04 06:25:05 PM PDT 24
Finished Jul 04 06:25:06 PM PDT 24
Peak memory 215528 kb
Host smart-a7618128-9d1a-4ab8-89d6-0565aa266af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613361618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3613361618
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1136465346
Short name T676
Test name
Test status
Simulation time 479787578 ps
CPU time 5.13 seconds
Started Jul 04 06:24:59 PM PDT 24
Finished Jul 04 06:25:04 PM PDT 24
Peak memory 220168 kb
Host smart-2a06dbb5-e166-49f7-8fd7-3cda57c50811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136465346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1136465346
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3030201812
Short name T577
Test name
Test status
Simulation time 388382701681 ps
CPU time 1907.04 seconds
Started Jul 04 06:24:56 PM PDT 24
Finished Jul 04 06:56:44 PM PDT 24
Peak memory 225588 kb
Host smart-b4806201-e4b7-4c59-afd3-92f80de21967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030201812 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3030201812
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.342556615
Short name T846
Test name
Test status
Simulation time 79079374 ps
CPU time 1.22 seconds
Started Jul 04 06:25:59 PM PDT 24
Finished Jul 04 06:26:00 PM PDT 24
Peak memory 220628 kb
Host smart-c5ca0972-734a-452e-8d5a-007fe6eea323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342556615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.342556615
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1892826675
Short name T73
Test name
Test status
Simulation time 30480097 ps
CPU time 1.28 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 219924 kb
Host smart-06ff121e-e4e5-43ce-8fb1-ef09b6311acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892826675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1892826675
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.567993937
Short name T764
Test name
Test status
Simulation time 57784157 ps
CPU time 1.19 seconds
Started Jul 04 06:26:20 PM PDT 24
Finished Jul 04 06:26:21 PM PDT 24
Peak memory 217684 kb
Host smart-c044a65b-fd85-4b37-97cd-ef595275c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567993937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.567993937
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.4236997933
Short name T983
Test name
Test status
Simulation time 35328966 ps
CPU time 1.18 seconds
Started Jul 04 06:26:41 PM PDT 24
Finished Jul 04 06:26:43 PM PDT 24
Peak memory 218908 kb
Host smart-93f22b7b-8b70-4662-8795-eef266db8640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236997933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.4236997933
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2854918839
Short name T954
Test name
Test status
Simulation time 20779321 ps
CPU time 1 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 224244 kb
Host smart-f05b4a26-d747-4d10-aa08-500fc79e7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854918839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2854918839
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.338850901
Short name T821
Test name
Test status
Simulation time 76142995 ps
CPU time 1.84 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 219212 kb
Host smart-9767bd9d-d9bc-47d1-90c1-99e3fdd0d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338850901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.338850901
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4063029667
Short name T431
Test name
Test status
Simulation time 45146928 ps
CPU time 1.11 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 218716 kb
Host smart-14abb998-069a-4dab-a8a3-02ef828844d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063029667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4063029667
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2201250325
Short name T202
Test name
Test status
Simulation time 56338097 ps
CPU time 1.09 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 220068 kb
Host smart-ac20ac87-668f-4cfc-81f0-c43535245d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201250325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2201250325
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3870337209
Short name T611
Test name
Test status
Simulation time 122227775 ps
CPU time 1.24 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 219180 kb
Host smart-3f76ae4d-fae4-4fda-b046-22cee315fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870337209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3870337209
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.291925538
Short name T858
Test name
Test status
Simulation time 92116794 ps
CPU time 1.17 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 221028 kb
Host smart-7cb0494b-0218-4237-9541-2b7873a89016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291925538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.291925538
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.959349457
Short name T788
Test name
Test status
Simulation time 21032285 ps
CPU time 0.98 seconds
Started Jul 04 06:26:07 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 219784 kb
Host smart-0a0f4bde-c12c-48c0-85ae-27a36e8df4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959349457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.959349457
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1435069242
Short name T824
Test name
Test status
Simulation time 252661627 ps
CPU time 2.83 seconds
Started Jul 04 06:26:22 PM PDT 24
Finished Jul 04 06:26:25 PM PDT 24
Peak memory 220280 kb
Host smart-61674ee7-4df0-4f1f-b47c-2dfd0e3d874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435069242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1435069242
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3315507268
Short name T261
Test name
Test status
Simulation time 26268199 ps
CPU time 1.2 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 220180 kb
Host smart-67bbef98-1cfd-4f89-88dc-3aa91d2a5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315507268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3315507268
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4137872657
Short name T201
Test name
Test status
Simulation time 22196672 ps
CPU time 0.94 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218804 kb
Host smart-0217c61b-5eb3-4d0a-9a3b-d8171b3dd27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137872657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4137872657
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.543962871
Short name T628
Test name
Test status
Simulation time 32013455 ps
CPU time 1.23 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 215684 kb
Host smart-36b5b086-7b39-407f-8d07-d2020e04a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543962871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.543962871
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1035856576
Short name T174
Test name
Test status
Simulation time 19023237 ps
CPU time 1.03 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218744 kb
Host smart-6f240683-309d-4c8f-a31a-0b6c52f84c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035856576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1035856576
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.899554507
Short name T424
Test name
Test status
Simulation time 40760045 ps
CPU time 1.45 seconds
Started Jul 04 06:26:32 PM PDT 24
Finished Jul 04 06:26:34 PM PDT 24
Peak memory 217488 kb
Host smart-05534b2e-a309-4525-8a22-c878ec7a332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899554507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.899554507
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1623483956
Short name T900
Test name
Test status
Simulation time 24144523 ps
CPU time 1.19 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 219912 kb
Host smart-46265b36-39e3-46e1-b21d-23c188877f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623483956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1623483956
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1642751106
Short name T159
Test name
Test status
Simulation time 45524156 ps
CPU time 0.8 seconds
Started Jul 04 06:26:09 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 218600 kb
Host smart-19b86d72-c6b9-440b-bcdb-1c637fb72db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642751106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1642751106
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3970809028
Short name T368
Test name
Test status
Simulation time 40678436 ps
CPU time 1.27 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 220232 kb
Host smart-f4b8ea2d-258a-41be-8e15-2c40d48a6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970809028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3970809028
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.589497962
Short name T870
Test name
Test status
Simulation time 22928158 ps
CPU time 1.19 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 221128 kb
Host smart-9e859310-0fd3-48a9-a6e0-81af13b53e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589497962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.589497962
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1448610686
Short name T423
Test name
Test status
Simulation time 26584017 ps
CPU time 0.92 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 224080 kb
Host smart-74399136-3e71-4d7e-a6bd-2aade2e6a370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448610686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1448610686
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3469847589
Short name T467
Test name
Test status
Simulation time 66061985 ps
CPU time 1.06 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:08 PM PDT 24
Peak memory 217716 kb
Host smart-803278db-39cd-4786-ad3e-6ef244899eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469847589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3469847589
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1415899002
Short name T708
Test name
Test status
Simulation time 76059895 ps
CPU time 1.14 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 219700 kb
Host smart-1c17e373-832b-41bf-acb7-b8f3894b4eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415899002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1415899002
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.490350738
Short name T488
Test name
Test status
Simulation time 24185746 ps
CPU time 1 seconds
Started Jul 04 06:26:24 PM PDT 24
Finished Jul 04 06:26:25 PM PDT 24
Peak memory 224244 kb
Host smart-acb54f84-2fa0-4e3d-a939-f05937d13901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490350738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.490350738
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3061041066
Short name T820
Test name
Test status
Simulation time 24356101 ps
CPU time 1.15 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 219200 kb
Host smart-9fcacdb8-2337-44ce-9329-570ab08a42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061041066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3061041066
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1894062139
Short name T273
Test name
Test status
Simulation time 71896859 ps
CPU time 1.09 seconds
Started Jul 04 06:26:05 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 219848 kb
Host smart-1c7cc2cd-b6d4-4582-b42e-06c52156211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894062139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1894062139
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.282335142
Short name T116
Test name
Test status
Simulation time 38715827 ps
CPU time 1.22 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 229972 kb
Host smart-a224d0a1-0dc4-4d9c-9a87-f945a9c41817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282335142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.282335142
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1011673923
Short name T433
Test name
Test status
Simulation time 110460350 ps
CPU time 1.31 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 218784 kb
Host smart-c162567e-6d18-472e-a70c-cf03c19fe5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011673923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1011673923
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.2357185161
Short name T747
Test name
Test status
Simulation time 20759188 ps
CPU time 0.85 seconds
Started Jul 04 06:25:09 PM PDT 24
Finished Jul 04 06:25:10 PM PDT 24
Peak memory 215220 kb
Host smart-0e7ef271-a467-4032-9361-c175567d8790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357185161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2357185161
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.757696950
Short name T558
Test name
Test status
Simulation time 72500067 ps
CPU time 0.88 seconds
Started Jul 04 06:25:12 PM PDT 24
Finished Jul 04 06:25:14 PM PDT 24
Peak memory 216276 kb
Host smart-37cdb74d-0a8f-451e-be9f-f40f1d303f69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757696950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.757696950
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1808492360
Short name T20
Test name
Test status
Simulation time 82208576 ps
CPU time 1.15 seconds
Started Jul 04 06:25:10 PM PDT 24
Finished Jul 04 06:25:12 PM PDT 24
Peak memory 217092 kb
Host smart-334d3133-f48e-4eee-a6d3-7f841354b796
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808492360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1808492360
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1037132012
Short name T122
Test name
Test status
Simulation time 34024156 ps
CPU time 0.95 seconds
Started Jul 04 06:25:37 PM PDT 24
Finished Jul 04 06:25:38 PM PDT 24
Peak memory 219912 kb
Host smart-24cf6a6f-cbea-4c9f-b8b3-8ec16cf0049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037132012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1037132012
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1512349964
Short name T316
Test name
Test status
Simulation time 105007209 ps
CPU time 2.25 seconds
Started Jul 04 06:24:56 PM PDT 24
Finished Jul 04 06:24:59 PM PDT 24
Peak memory 220520 kb
Host smart-95d56c85-fc3a-41c8-9388-a23a1364515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512349964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1512349964
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2745026814
Short name T71
Test name
Test status
Simulation time 30648821 ps
CPU time 0.9 seconds
Started Jul 04 06:25:11 PM PDT 24
Finished Jul 04 06:25:13 PM PDT 24
Peak memory 215700 kb
Host smart-edb8268e-7300-40bd-91b0-f24ee83209c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745026814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2745026814
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2135437178
Short name T576
Test name
Test status
Simulation time 28387108 ps
CPU time 0.95 seconds
Started Jul 04 06:25:08 PM PDT 24
Finished Jul 04 06:25:09 PM PDT 24
Peak memory 207428 kb
Host smart-c35c72cf-3f35-40f7-a0a7-73670ce2936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135437178 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2135437178
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3837204537
Short name T362
Test name
Test status
Simulation time 40889136 ps
CPU time 0.95 seconds
Started Jul 04 06:25:02 PM PDT 24
Finished Jul 04 06:25:03 PM PDT 24
Peak memory 215612 kb
Host smart-5141b144-78f8-4c2e-946e-fc6ce32f685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837204537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3837204537
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4202473046
Short name T98
Test name
Test status
Simulation time 487168725 ps
CPU time 5.61 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:25:04 PM PDT 24
Peak memory 217684 kb
Host smart-b3bd2694-ede7-4d41-bcee-5ca4bc57ee35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202473046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4202473046
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4053313292
Short name T216
Test name
Test status
Simulation time 166399203292 ps
CPU time 587.11 seconds
Started Jul 04 06:24:58 PM PDT 24
Finished Jul 04 06:34:45 PM PDT 24
Peak memory 224056 kb
Host smart-d49f1b38-1dd9-4654-aef5-7cd39ea522d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053313292 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4053313292
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.940774910
Short name T670
Test name
Test status
Simulation time 23752505 ps
CPU time 1.14 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 219908 kb
Host smart-80268f2d-d1c4-4357-87b8-8bc4f26802c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940774910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.940774910
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.661705775
Short name T711
Test name
Test status
Simulation time 35127976 ps
CPU time 1.18 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 215700 kb
Host smart-5b8ddf36-369e-467f-827e-24746b284b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661705775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.661705775
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3023152424
Short name T989
Test name
Test status
Simulation time 85778315 ps
CPU time 1.36 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 219368 kb
Host smart-1de2e8ae-5a8d-4c5d-9356-a5e6bb064bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023152424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3023152424
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1449698697
Short name T932
Test name
Test status
Simulation time 29255764 ps
CPU time 1.25 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 218836 kb
Host smart-83cb4e4b-2e43-415a-a823-87155df2e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449698697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1449698697
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1497487966
Short name T196
Test name
Test status
Simulation time 29130566 ps
CPU time 1.4 seconds
Started Jul 04 06:26:29 PM PDT 24
Finished Jul 04 06:26:30 PM PDT 24
Peak memory 226236 kb
Host smart-079fe01a-db1c-471c-9f29-2304d2fb502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497487966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1497487966
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3465113663
Short name T475
Test name
Test status
Simulation time 79180955 ps
CPU time 1.18 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:13 PM PDT 24
Peak memory 217512 kb
Host smart-5c54076b-9378-448f-9221-3642074c9318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465113663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3465113663
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2908109459
Short name T105
Test name
Test status
Simulation time 49706574 ps
CPU time 1.19 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 221144 kb
Host smart-9a37537e-0b42-42f1-9331-d258f9736690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908109459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2908109459
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3744276612
Short name T352
Test name
Test status
Simulation time 48646118 ps
CPU time 0.96 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 218936 kb
Host smart-9908a040-385d-4c89-bc8f-58cd6861ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744276612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3744276612
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1843527716
Short name T953
Test name
Test status
Simulation time 60771760 ps
CPU time 1.17 seconds
Started Jul 04 06:26:03 PM PDT 24
Finished Jul 04 06:26:05 PM PDT 24
Peak memory 217680 kb
Host smart-6810a299-9fa6-4278-819b-76a956213364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843527716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1843527716
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.464908231
Short name T761
Test name
Test status
Simulation time 22720985 ps
CPU time 1.14 seconds
Started Jul 04 06:26:47 PM PDT 24
Finished Jul 04 06:26:49 PM PDT 24
Peak memory 221116 kb
Host smart-62afeff7-d3fd-4446-85a5-b8b72467e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464908231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.464908231
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.4283269010
Short name T890
Test name
Test status
Simulation time 24141131 ps
CPU time 1.15 seconds
Started Jul 04 06:26:27 PM PDT 24
Finished Jul 04 06:26:29 PM PDT 24
Peak memory 220124 kb
Host smart-7f564d44-0e5f-4195-8f67-6552a6bfa2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283269010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4283269010
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3782024742
Short name T480
Test name
Test status
Simulation time 50342781 ps
CPU time 1.74 seconds
Started Jul 04 06:26:34 PM PDT 24
Finished Jul 04 06:26:36 PM PDT 24
Peak memory 217884 kb
Host smart-376aa29d-8d4b-4632-b96f-63a1fde7dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782024742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3782024742
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2318205796
Short name T675
Test name
Test status
Simulation time 25872986 ps
CPU time 1.22 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 221112 kb
Host smart-5684b654-986a-4a7e-95fa-bb30c8d913b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318205796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2318205796
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1676429722
Short name T398
Test name
Test status
Simulation time 27163311 ps
CPU time 0.97 seconds
Started Jul 04 06:26:08 PM PDT 24
Finished Jul 04 06:26:11 PM PDT 24
Peak memory 224084 kb
Host smart-fb976111-d29f-4dff-b896-4cc6dbf9a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676429722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1676429722
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1029212797
Short name T683
Test name
Test status
Simulation time 84233961 ps
CPU time 1.17 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 217524 kb
Host smart-05d8ce4b-e525-4842-8fa5-fd181b211e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029212797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1029212797
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.4113911409
Short name T908
Test name
Test status
Simulation time 40744112 ps
CPU time 1.19 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:06 PM PDT 24
Peak memory 219140 kb
Host smart-5352b7f2-d2fa-4d74-872b-99f3c2859eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113911409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.4113911409
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3092007568
Short name T472
Test name
Test status
Simulation time 20801131 ps
CPU time 1.06 seconds
Started Jul 04 06:26:29 PM PDT 24
Finished Jul 04 06:26:30 PM PDT 24
Peak memory 219652 kb
Host smart-9a39660f-b3ce-4bd9-8f35-b1cd6779608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092007568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3092007568
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1854747863
Short name T770
Test name
Test status
Simulation time 77043079 ps
CPU time 1.3 seconds
Started Jul 04 06:26:28 PM PDT 24
Finished Jul 04 06:26:35 PM PDT 24
Peak memory 219304 kb
Host smart-57669868-975c-445d-813e-e80ffc90fe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854747863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1854747863
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2623462977
Short name T141
Test name
Test status
Simulation time 85783338 ps
CPU time 1.17 seconds
Started Jul 04 06:26:06 PM PDT 24
Finished Jul 04 06:26:09 PM PDT 24
Peak memory 219220 kb
Host smart-6cddd88a-2ca0-48bc-b407-38e95f26941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623462977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2623462977
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.4003269904
Short name T775
Test name
Test status
Simulation time 20010997 ps
CPU time 0.99 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:12 PM PDT 24
Peak memory 218480 kb
Host smart-d5c7ae93-1554-4ac9-bdc3-5e44fc1db366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003269904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4003269904
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2729761241
Short name T447
Test name
Test status
Simulation time 46392028 ps
CPU time 2.08 seconds
Started Jul 04 06:26:10 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 218948 kb
Host smart-fcdfba9c-896e-4448-a7dd-2a690374ee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729761241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2729761241
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3726947383
Short name T624
Test name
Test status
Simulation time 42720384 ps
CPU time 1.14 seconds
Started Jul 04 06:26:16 PM PDT 24
Finished Jul 04 06:26:17 PM PDT 24
Peak memory 218936 kb
Host smart-311e800c-54d7-4a19-85a9-1bd728fc5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726947383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3726947383
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3494836707
Short name T993
Test name
Test status
Simulation time 18489005 ps
CPU time 1.15 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 224292 kb
Host smart-213fa5cc-4a90-43e5-9554-3ddeb8ae0d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494836707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3494836707
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2524399113
Short name T878
Test name
Test status
Simulation time 121395865 ps
CPU time 1.32 seconds
Started Jul 04 06:26:02 PM PDT 24
Finished Jul 04 06:26:04 PM PDT 24
Peak memory 217464 kb
Host smart-3b196cbe-50bc-4deb-9529-d71140273477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524399113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2524399113
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.4085325965
Short name T730
Test name
Test status
Simulation time 28228967 ps
CPU time 1.24 seconds
Started Jul 04 06:26:20 PM PDT 24
Finished Jul 04 06:26:21 PM PDT 24
Peak memory 219180 kb
Host smart-c629fd59-2536-4bf4-972a-b66a732659f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085325965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.4085325965
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.606444839
Short name T129
Test name
Test status
Simulation time 25751113 ps
CPU time 1.17 seconds
Started Jul 04 06:26:04 PM PDT 24
Finished Jul 04 06:26:07 PM PDT 24
Peak memory 220708 kb
Host smart-8d271e66-077a-41f0-a080-b8bd59653e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606444839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.606444839
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1215748400
Short name T452
Test name
Test status
Simulation time 112179995 ps
CPU time 1.33 seconds
Started Jul 04 06:26:01 PM PDT 24
Finished Jul 04 06:26:03 PM PDT 24
Peak memory 218868 kb
Host smart-78d6fa81-6790-47b7-b7d2-9d21cb63637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215748400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1215748400
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1391294179
Short name T514
Test name
Test status
Simulation time 40547366 ps
CPU time 1.19 seconds
Started Jul 04 06:26:27 PM PDT 24
Finished Jul 04 06:26:28 PM PDT 24
Peak memory 221728 kb
Host smart-8d6bce19-447a-483a-98b8-19fb913371a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391294179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1391294179
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3263659634
Short name T8
Test name
Test status
Simulation time 37935431 ps
CPU time 1.16 seconds
Started Jul 04 06:26:11 PM PDT 24
Finished Jul 04 06:26:14 PM PDT 24
Peak memory 221064 kb
Host smart-1787a921-8768-4a76-bf6b-91a4088bbb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263659634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3263659634
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1698026311
Short name T913
Test name
Test status
Simulation time 43178155 ps
CPU time 1.56 seconds
Started Jul 04 06:26:12 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 218912 kb
Host smart-d097ae7a-d13e-46d3-9ee2-8540a2e6d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698026311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1698026311
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%