Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.53 98.25 93.91 97.07 91.28 96.37 99.77 92.08


Total test records in report: 1130
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T1018 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1072987479 Jul 05 05:13:55 PM PDT 24 Jul 05 05:13:58 PM PDT 24 38783786 ps
T1019 /workspace/coverage/cover_reg_top/16.edn_intr_test.362625460 Jul 05 05:14:09 PM PDT 24 Jul 05 05:14:11 PM PDT 24 20450388 ps
T1020 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2884666620 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:02 PM PDT 24 89081178 ps
T1021 /workspace/coverage/cover_reg_top/17.edn_intr_test.2162223562 Jul 05 05:14:16 PM PDT 24 Jul 05 05:14:18 PM PDT 24 35176553 ps
T1022 /workspace/coverage/cover_reg_top/8.edn_intr_test.2155384289 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:06 PM PDT 24 20818795 ps
T253 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4051008534 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:00 PM PDT 24 22089432 ps
T235 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1516617166 Jul 05 05:14:02 PM PDT 24 Jul 05 05:14:03 PM PDT 24 12826799 ps
T1023 /workspace/coverage/cover_reg_top/18.edn_intr_test.1578057197 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:19 PM PDT 24 33914359 ps
T1024 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2195943524 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:06 PM PDT 24 30705730 ps
T254 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1360832981 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:15 PM PDT 24 190166962 ps
T1025 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2343406302 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:09 PM PDT 24 79477465 ps
T1026 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.248610152 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:14 PM PDT 24 43938735 ps
T1027 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1072646765 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:09 PM PDT 24 12873714 ps
T270 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2434949976 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:20 PM PDT 24 414230548 ps
T1028 /workspace/coverage/cover_reg_top/31.edn_intr_test.3782002012 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:27 PM PDT 24 20118563 ps
T1029 /workspace/coverage/cover_reg_top/7.edn_intr_test.1321404050 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:06 PM PDT 24 32327572 ps
T1030 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3444734082 Jul 05 05:14:08 PM PDT 24 Jul 05 05:14:10 PM PDT 24 60069636 ps
T236 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2215075484 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:14 PM PDT 24 14593325 ps
T1031 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1848991662 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:14 PM PDT 24 43302085 ps
T1032 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.601606869 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 20877397 ps
T1033 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2759351447 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 42383525 ps
T1034 /workspace/coverage/cover_reg_top/30.edn_intr_test.3472955181 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 41783733 ps
T1035 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1011261873 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:16 PM PDT 24 154104689 ps
T1036 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2839881402 Jul 05 05:14:10 PM PDT 24 Jul 05 05:14:13 PM PDT 24 169548692 ps
T1037 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2441825960 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:13 PM PDT 24 62036470 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.76046973 Jul 05 05:13:55 PM PDT 24 Jul 05 05:13:58 PM PDT 24 18334425 ps
T237 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.608691702 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:02 PM PDT 24 29145356 ps
T1039 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.896724493 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:09 PM PDT 24 72573533 ps
T1040 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2461043338 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:05 PM PDT 24 11399841 ps
T1041 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1426506748 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:10 PM PDT 24 115716647 ps
T1042 /workspace/coverage/cover_reg_top/1.edn_intr_test.791920842 Jul 05 05:13:52 PM PDT 24 Jul 05 05:13:54 PM PDT 24 16778241 ps
T1043 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1609241789 Jul 05 05:13:55 PM PDT 24 Jul 05 05:14:00 PM PDT 24 210940594 ps
T1044 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2986314884 Jul 05 05:14:14 PM PDT 24 Jul 05 05:14:16 PM PDT 24 69600342 ps
T238 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3313064867 Jul 05 05:14:19 PM PDT 24 Jul 05 05:14:21 PM PDT 24 15238171 ps
T1045 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2969526993 Jul 05 05:13:56 PM PDT 24 Jul 05 05:14:01 PM PDT 24 114462610 ps
T1046 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1564959934 Jul 05 05:14:08 PM PDT 24 Jul 05 05:14:11 PM PDT 24 161464351 ps
T1047 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2641793543 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:16 PM PDT 24 87299056 ps
T1048 /workspace/coverage/cover_reg_top/10.edn_intr_test.2304195123 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:08 PM PDT 24 25530245 ps
T239 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1925109038 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:01 PM PDT 24 16431057 ps
T240 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3082505906 Jul 05 05:14:06 PM PDT 24 Jul 05 05:14:09 PM PDT 24 21567368 ps
T241 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1176651373 Jul 05 05:13:51 PM PDT 24 Jul 05 05:13:54 PM PDT 24 42616264 ps
T1049 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1423759843 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:19 PM PDT 24 46674397 ps
T1050 /workspace/coverage/cover_reg_top/21.edn_intr_test.1478143328 Jul 05 05:14:20 PM PDT 24 Jul 05 05:14:22 PM PDT 24 15350986 ps
T1051 /workspace/coverage/cover_reg_top/46.edn_intr_test.1204130806 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:28 PM PDT 24 25875341 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_intr_test.3562545347 Jul 05 05:13:56 PM PDT 24 Jul 05 05:13:58 PM PDT 24 47318051 ps
T1053 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2703359681 Jul 05 05:14:09 PM PDT 24 Jul 05 05:14:12 PM PDT 24 40689730 ps
T1054 /workspace/coverage/cover_reg_top/15.edn_intr_test.2230772057 Jul 05 05:14:20 PM PDT 24 Jul 05 05:14:22 PM PDT 24 27372810 ps
T1055 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1655265986 Jul 05 05:13:55 PM PDT 24 Jul 05 05:13:58 PM PDT 24 51747152 ps
T1056 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1168833769 Jul 05 05:14:29 PM PDT 24 Jul 05 05:14:36 PM PDT 24 445399095 ps
T1057 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2668402727 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:03 PM PDT 24 287678482 ps
T1058 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3603338985 Jul 05 05:14:13 PM PDT 24 Jul 05 05:14:15 PM PDT 24 24016262 ps
T1059 /workspace/coverage/cover_reg_top/6.edn_intr_test.4036426666 Jul 05 05:14:01 PM PDT 24 Jul 05 05:14:03 PM PDT 24 12531372 ps
T1060 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1007731718 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:21 PM PDT 24 265132046 ps
T1061 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2730286892 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:20 PM PDT 24 45254074 ps
T1062 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3172261180 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:02 PM PDT 24 170530027 ps
T1063 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.7562288 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:08 PM PDT 24 23480870 ps
T1064 /workspace/coverage/cover_reg_top/23.edn_intr_test.2711386122 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:18 PM PDT 24 36808546 ps
T1065 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.992645247 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:14 PM PDT 24 34903063 ps
T1066 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1331187394 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:06 PM PDT 24 558210101 ps
T1067 /workspace/coverage/cover_reg_top/4.edn_tl_errors.237758444 Jul 05 05:13:59 PM PDT 24 Jul 05 05:14:04 PM PDT 24 386730124 ps
T266 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1147262637 Jul 05 05:14:10 PM PDT 24 Jul 05 05:14:12 PM PDT 24 86152439 ps
T1068 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1136843266 Jul 05 05:14:09 PM PDT 24 Jul 05 05:14:11 PM PDT 24 22305260 ps
T1069 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3323723767 Jul 05 05:14:20 PM PDT 24 Jul 05 05:14:22 PM PDT 24 44188193 ps
T1070 /workspace/coverage/cover_reg_top/12.edn_intr_test.54927880 Jul 05 05:14:12 PM PDT 24 Jul 05 05:14:14 PM PDT 24 70476492 ps
T1071 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1218677792 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:07 PM PDT 24 247980015 ps
T1072 /workspace/coverage/cover_reg_top/39.edn_intr_test.1518600455 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:27 PM PDT 24 21458383 ps
T1073 /workspace/coverage/cover_reg_top/14.edn_intr_test.308146391 Jul 05 05:14:14 PM PDT 24 Jul 05 05:14:16 PM PDT 24 51113550 ps
T1074 /workspace/coverage/cover_reg_top/9.edn_intr_test.2961324978 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:08 PM PDT 24 32318541 ps
T1075 /workspace/coverage/cover_reg_top/29.edn_intr_test.3080863588 Jul 05 05:14:22 PM PDT 24 Jul 05 05:14:23 PM PDT 24 15808703 ps
T1076 /workspace/coverage/cover_reg_top/13.edn_intr_test.1528458294 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:13 PM PDT 24 15379811 ps
T1077 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1393281024 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:15 PM PDT 24 42962307 ps
T1078 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3075824342 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:00 PM PDT 24 29099985 ps
T1079 /workspace/coverage/cover_reg_top/19.edn_intr_test.2919691065 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 15589741 ps
T1080 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3360530788 Jul 05 05:14:19 PM PDT 24 Jul 05 05:14:23 PM PDT 24 76837749 ps
T1081 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3883163741 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:11 PM PDT 24 853633392 ps
T1082 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.810680090 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:14 PM PDT 24 83355534 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4243472387 Jul 05 05:13:52 PM PDT 24 Jul 05 05:13:56 PM PDT 24 32831662 ps
T1084 /workspace/coverage/cover_reg_top/11.edn_intr_test.2997798698 Jul 05 05:14:20 PM PDT 24 Jul 05 05:14:22 PM PDT 24 11542583 ps
T1085 /workspace/coverage/cover_reg_top/35.edn_intr_test.3886670022 Jul 05 05:14:26 PM PDT 24 Jul 05 05:14:30 PM PDT 24 40228072 ps
T1086 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3389493236 Jul 05 05:14:29 PM PDT 24 Jul 05 05:14:33 PM PDT 24 65023041 ps
T242 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3135700813 Jul 05 05:14:08 PM PDT 24 Jul 05 05:14:10 PM PDT 24 42902091 ps
T1087 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2110645405 Jul 05 05:13:55 PM PDT 24 Jul 05 05:14:00 PM PDT 24 141161352 ps
T1088 /workspace/coverage/cover_reg_top/33.edn_intr_test.3206783616 Jul 05 05:14:24 PM PDT 24 Jul 05 05:14:26 PM PDT 24 24900159 ps
T1089 /workspace/coverage/cover_reg_top/20.edn_intr_test.2326995126 Jul 05 05:14:21 PM PDT 24 Jul 05 05:14:22 PM PDT 24 21405338 ps
T1090 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1637093255 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:06 PM PDT 24 44706118 ps
T1091 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2940028044 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:10 PM PDT 24 51065197 ps
T1092 /workspace/coverage/cover_reg_top/49.edn_intr_test.2660360721 Jul 05 05:14:27 PM PDT 24 Jul 05 05:14:31 PM PDT 24 18387546 ps
T1093 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1351983345 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 22869447 ps
T1094 /workspace/coverage/cover_reg_top/41.edn_intr_test.4167717145 Jul 05 05:14:27 PM PDT 24 Jul 05 05:14:31 PM PDT 24 32813287 ps
T1095 /workspace/coverage/cover_reg_top/2.edn_intr_test.4148821300 Jul 05 05:13:54 PM PDT 24 Jul 05 05:13:56 PM PDT 24 15181853 ps
T1096 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2015088736 Jul 05 05:14:22 PM PDT 24 Jul 05 05:14:24 PM PDT 24 57373908 ps
T1097 /workspace/coverage/cover_reg_top/45.edn_intr_test.1445397387 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:27 PM PDT 24 18189694 ps
T1098 /workspace/coverage/cover_reg_top/28.edn_intr_test.2261017282 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:18 PM PDT 24 112138678 ps
T1099 /workspace/coverage/cover_reg_top/25.edn_intr_test.1125316620 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:20 PM PDT 24 15433176 ps
T1100 /workspace/coverage/cover_reg_top/17.edn_csr_rw.267255901 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:19 PM PDT 24 13012088 ps
T1101 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4193021077 Jul 05 05:13:59 PM PDT 24 Jul 05 05:14:02 PM PDT 24 102390326 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2146716482 Jul 05 05:14:29 PM PDT 24 Jul 05 05:14:33 PM PDT 24 27003116 ps
T1103 /workspace/coverage/cover_reg_top/43.edn_intr_test.3877099818 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:29 PM PDT 24 13616325 ps
T1104 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1952604358 Jul 05 05:14:18 PM PDT 24 Jul 05 05:14:22 PM PDT 24 41474075 ps
T1105 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3257635645 Jul 05 05:14:04 PM PDT 24 Jul 05 05:14:06 PM PDT 24 40599491 ps
T1106 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3447437257 Jul 05 05:14:06 PM PDT 24 Jul 05 05:14:08 PM PDT 24 11823594 ps
T1107 /workspace/coverage/cover_reg_top/42.edn_intr_test.2825639292 Jul 05 05:14:25 PM PDT 24 Jul 05 05:14:27 PM PDT 24 14733041 ps
T1108 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3525855551 Jul 05 05:13:59 PM PDT 24 Jul 05 05:14:05 PM PDT 24 466334280 ps
T1109 /workspace/coverage/cover_reg_top/8.edn_tl_errors.772206150 Jul 05 05:14:05 PM PDT 24 Jul 05 05:14:10 PM PDT 24 212934256 ps
T1110 /workspace/coverage/cover_reg_top/22.edn_intr_test.3081140177 Jul 05 05:14:19 PM PDT 24 Jul 05 05:14:21 PM PDT 24 13149776 ps
T1111 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1470321926 Jul 05 05:14:11 PM PDT 24 Jul 05 05:14:14 PM PDT 24 38599805 ps
T1112 /workspace/coverage/cover_reg_top/5.edn_tl_errors.720173181 Jul 05 05:13:56 PM PDT 24 Jul 05 05:14:02 PM PDT 24 377121425 ps
T1113 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2738777858 Jul 05 05:14:15 PM PDT 24 Jul 05 05:14:18 PM PDT 24 683068582 ps
T243 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2389072436 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:09 PM PDT 24 13947952 ps
T1114 /workspace/coverage/cover_reg_top/37.edn_intr_test.1202807485 Jul 05 05:14:29 PM PDT 24 Jul 05 05:14:33 PM PDT 24 42012939 ps
T1115 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.355437327 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:01 PM PDT 24 59559332 ps
T1116 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4130647907 Jul 05 05:13:51 PM PDT 24 Jul 05 05:13:54 PM PDT 24 96268061 ps
T244 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2583196834 Jul 05 05:13:51 PM PDT 24 Jul 05 05:13:53 PM PDT 24 24975329 ps
T1117 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2226008492 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:09 PM PDT 24 66885341 ps
T1118 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.647832416 Jul 05 05:13:54 PM PDT 24 Jul 05 05:13:56 PM PDT 24 48394847 ps
T1119 /workspace/coverage/cover_reg_top/26.edn_intr_test.3868422920 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:18 PM PDT 24 26155756 ps
T1120 /workspace/coverage/cover_reg_top/44.edn_intr_test.678461377 Jul 05 05:14:24 PM PDT 24 Jul 05 05:14:27 PM PDT 24 38244203 ps
T1121 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.296969160 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:03 PM PDT 24 389597180 ps
T1122 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2871227942 Jul 05 05:13:57 PM PDT 24 Jul 05 05:14:00 PM PDT 24 21652337 ps
T1123 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4145478986 Jul 05 05:14:03 PM PDT 24 Jul 05 05:14:06 PM PDT 24 145353600 ps
T1124 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3355155000 Jul 05 05:13:51 PM PDT 24 Jul 05 05:13:54 PM PDT 24 34600097 ps
T1125 /workspace/coverage/cover_reg_top/14.edn_csr_rw.298121724 Jul 05 05:14:13 PM PDT 24 Jul 05 05:14:15 PM PDT 24 23898546 ps
T245 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3545432895 Jul 05 05:13:55 PM PDT 24 Jul 05 05:13:57 PM PDT 24 32073953 ps
T1126 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2882636351 Jul 05 05:13:58 PM PDT 24 Jul 05 05:14:01 PM PDT 24 44587887 ps
T1127 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3024026292 Jul 05 05:13:56 PM PDT 24 Jul 05 05:14:01 PM PDT 24 97158916 ps
T1128 /workspace/coverage/cover_reg_top/27.edn_intr_test.3193307337 Jul 05 05:14:17 PM PDT 24 Jul 05 05:14:20 PM PDT 24 29360319 ps
T267 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2476318348 Jul 05 05:14:06 PM PDT 24 Jul 05 05:14:10 PM PDT 24 119119528 ps
T246 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3286480774 Jul 05 05:14:07 PM PDT 24 Jul 05 05:14:12 PM PDT 24 195570652 ps
T1129 /workspace/coverage/cover_reg_top/0.edn_intr_test.1587379308 Jul 05 05:13:51 PM PDT 24 Jul 05 05:13:54 PM PDT 24 17336122 ps
T1130 /workspace/coverage/cover_reg_top/48.edn_intr_test.1563662826 Jul 05 05:14:26 PM PDT 24 Jul 05 05:14:30 PM PDT 24 24203455 ps

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4103620611
Short name T4
Test name
Test status
Simulation time 26176957902 ps
CPU time 600.6 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:58:32 PM PDT 24
Peak memory 224032 kb
Host smart-039377a4-adb7-4647-8cc8-2fc4e68e9096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103620611 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4103620611
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3938969308
Short name T8
Test name
Test status
Simulation time 43756579 ps
CPU time 1.5 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 219840 kb
Host smart-0e29d509-eeb2-4a6f-9010-f4ce1cc292cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938969308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3938969308
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.4161470031
Short name T11
Test name
Test status
Simulation time 77780356 ps
CPU time 1.16 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 225836 kb
Host smart-aa2c52da-b4ba-4f01-aa28-ba237d76e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161470031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4161470031
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2916752761
Short name T44
Test name
Test status
Simulation time 56301427 ps
CPU time 1.38 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:32 PM PDT 24
Peak memory 219024 kb
Host smart-a17d1f33-3540-4968-989b-d25fcc4a2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916752761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2916752761
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2559991872
Short name T15
Test name
Test status
Simulation time 513391512 ps
CPU time 8.21 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:48:02 PM PDT 24
Peak memory 236372 kb
Host smart-236d4140-00ae-4f50-88e0-1777a08c045d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559991872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2559991872
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/67.edn_alert.2116729846
Short name T7
Test name
Test status
Simulation time 26146909 ps
CPU time 1.2 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 219704 kb
Host smart-109bfcbd-5a2a-4871-9798-c03e905be1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116729846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2116729846
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1450039926
Short name T75
Test name
Test status
Simulation time 53431440 ps
CPU time 1.08 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 218840 kb
Host smart-3d9198c7-e9c1-4b1d-b020-b730d646b93e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450039926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1450039926
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/134.edn_alert.1758893388
Short name T88
Test name
Test status
Simulation time 41038542 ps
CPU time 1.11 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 220000 kb
Host smart-58b8552c-e1ac-47ca-93e1-b6f6066ca1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758893388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1758893388
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.3552535301
Short name T84
Test name
Test status
Simulation time 30465676 ps
CPU time 1.24 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 215976 kb
Host smart-2671cded-c7b8-4ac4-a034-f9520514d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552535301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3552535301
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3155216838
Short name T19
Test name
Test status
Simulation time 144515887 ps
CPU time 1 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 217264 kb
Host smart-84fd24c7-ce15-436c-b415-ebae4400e4e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155216838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3155216838
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_regwen.1593772052
Short name T26
Test name
Test status
Simulation time 51693426 ps
CPU time 0.99 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 207372 kb
Host smart-e5b83295-12b3-448f-a3f8-1097e3412315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593772052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1593772052
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/15.edn_disable.1938750444
Short name T94
Test name
Test status
Simulation time 14635205 ps
CPU time 0.95 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 216832 kb
Host smart-573da5aa-b5df-4dcc-8338-bbd7ec35b8b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938750444 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1938750444
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2149152818
Short name T261
Test name
Test status
Simulation time 301330964 ps
CPU time 2.33 seconds
Started Jul 05 05:14:10 PM PDT 24
Finished Jul 05 05:14:13 PM PDT 24
Peak memory 206796 kb
Host smart-5c7331c7-363e-4a14-9e1b-bbb8244dbde7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149152818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2149152818
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/117.edn_alert.864038886
Short name T101
Test name
Test status
Simulation time 31737438 ps
CPU time 1.37 seconds
Started Jul 05 05:50:01 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 216000 kb
Host smart-e12fa379-f2af-431a-a202-b588c57bd201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864038886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.864038886
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1287986147
Short name T78
Test name
Test status
Simulation time 97230056 ps
CPU time 1.07 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 220004 kb
Host smart-a4a32a01-7cd8-4c4c-a36c-544eadf8ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287986147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1287986147
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1516617166
Short name T235
Test name
Test status
Simulation time 12826799 ps
CPU time 0.87 seconds
Started Jul 05 05:14:02 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 206784 kb
Host smart-84649bfa-2e39-4fb8-a0c7-e30e75cfb284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516617166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1516617166
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/default/187.edn_alert.3959324350
Short name T143
Test name
Test status
Simulation time 24190478 ps
CPU time 1.25 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 219656 kb
Host smart-914ce667-84c6-4c65-b092-9d7fa005c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959324350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3959324350
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.670589309
Short name T202
Test name
Test status
Simulation time 30574589 ps
CPU time 0.82 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 216480 kb
Host smart-15395df3-1172-4572-9f81-c9f6fbb0a464
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670589309 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.670589309
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2662744475
Short name T195
Test name
Test status
Simulation time 203066326 ps
CPU time 1.33 seconds
Started Jul 05 05:47:39 PM PDT 24
Finished Jul 05 05:47:41 PM PDT 24
Peak memory 217284 kb
Host smart-1abdf25f-f876-432e-8097-f809f741a648
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662744475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2662744475
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/170.edn_alert.2997607862
Short name T66
Test name
Test status
Simulation time 44192161 ps
CPU time 1.18 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219020 kb
Host smart-c8ef7e58-4943-4cb7-89d3-743f21971cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997607862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2997607862
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4162850315
Short name T71
Test name
Test status
Simulation time 31213885107 ps
CPU time 687.01 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 06:00:48 PM PDT 24
Peak memory 218752 kb
Host smart-1bf5ea22-91de-46fc-ad6c-ffad26220620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162850315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4162850315
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.edn_alert.424580133
Short name T227
Test name
Test status
Simulation time 30448863 ps
CPU time 1.45 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 218928 kb
Host smart-d58042d2-7379-441e-9045-63457a483a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424580133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.424580133
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3458384674
Short name T13
Test name
Test status
Simulation time 463670804 ps
CPU time 4.05 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:46 PM PDT 24
Peak memory 235660 kb
Host smart-af5660f8-9d32-4980-b065-016daadcbd5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458384674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3458384674
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1283370190
Short name T47
Test name
Test status
Simulation time 114430838 ps
CPU time 1.19 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 220260 kb
Host smart-ba45688c-3555-4e68-8987-d8ee530e652f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283370190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1283370190
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/94.edn_alert.1956477584
Short name T492
Test name
Test status
Simulation time 48432938 ps
CPU time 1.25 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 215900 kb
Host smart-17bd54bf-16df-4936-8b0d-9858fbe202e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956477584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1956477584
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert.3271608999
Short name T256
Test name
Test status
Simulation time 113684465 ps
CPU time 1.2 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 218664 kb
Host smart-711e08e2-2252-4a60-ad78-8491e95fd6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271608999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3271608999
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.1612960322
Short name T731
Test name
Test status
Simulation time 26438743 ps
CPU time 1.29 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 219880 kb
Host smart-9d7b2df9-a4ea-464e-b4fe-d24aaea65639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612960322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1612960322
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/140.edn_alert.1594327228
Short name T503
Test name
Test status
Simulation time 77989032 ps
CPU time 1.11 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 218952 kb
Host smart-339a4064-4d57-4922-9978-23481e934b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594327228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1594327228
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.1138221035
Short name T153
Test name
Test status
Simulation time 55870105 ps
CPU time 1.14 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 220104 kb
Host smart-30638e4d-7715-43f7-a777-33731c7bab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138221035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1138221035
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.3092491725
Short name T948
Test name
Test status
Simulation time 26683369 ps
CPU time 1.19 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 218864 kb
Host smart-6adc0b9c-1f41-4dba-b3ca-d617eef09516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092491725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3092491725
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/16.edn_intr.674634549
Short name T100
Test name
Test status
Simulation time 27100039 ps
CPU time 1.05 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 216108 kb
Host smart-d0cb52c6-ddfe-486c-9c4b-21214b3e538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674634549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.674634549
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/67.edn_genbits.2744522769
Short name T285
Test name
Test status
Simulation time 72092307 ps
CPU time 1.11 seconds
Started Jul 05 05:49:37 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 217500 kb
Host smart-2650cad4-b1b1-40c0-a04f-6f5a55cd1dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744522769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2744522769
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_genbits.3855382449
Short name T320
Test name
Test status
Simulation time 55025086 ps
CPU time 1.73 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 220336 kb
Host smart-8241f925-a6c7-4677-a578-b7842f7f4fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855382449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3855382449
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_disable.1910218238
Short name T206
Test name
Test status
Simulation time 46531063 ps
CPU time 0.84 seconds
Started Jul 05 05:48:22 PM PDT 24
Finished Jul 05 05:48:24 PM PDT 24
Peak memory 215664 kb
Host smart-3b9a8ca7-210b-444c-a975-0fdcbe4bc9e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910218238 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1910218238
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/175.edn_alert.1939381091
Short name T607
Test name
Test status
Simulation time 45141878 ps
CPU time 1.13 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 220312 kb
Host smart-295598ff-fc2a-454a-9a55-c0d4a23431a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939381091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1939381091
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/36.edn_intr.2313320213
Short name T36
Test name
Test status
Simulation time 22759800 ps
CPU time 0.92 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 216204 kb
Host smart-e1e92d84-4f42-4f5e-b7ff-80a2995f7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313320213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2313320213
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.2325348794
Short name T192
Test name
Test status
Simulation time 12771984 ps
CPU time 0.93 seconds
Started Jul 05 05:47:40 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 216768 kb
Host smart-8c9d3b3a-1ab1-4f59-a33d-78388763bc54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325348794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2325348794
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3276194171
Short name T943
Test name
Test status
Simulation time 112140499 ps
CPU time 1.17 seconds
Started Jul 05 05:48:14 PM PDT 24
Finished Jul 05 05:48:15 PM PDT 24
Peak memory 217048 kb
Host smart-6eec31bf-081b-4573-99f3-404cf79812c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276194171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3276194171
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/118.edn_alert.1297930702
Short name T751
Test name
Test status
Simulation time 24027553 ps
CPU time 1.23 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 218952 kb
Host smart-260d1d94-43b8-417b-a788-56e239e38e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297930702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1297930702
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.9951082
Short name T983
Test name
Test status
Simulation time 26002588 ps
CPU time 1.25 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 219908 kb
Host smart-816095a5-db98-4f1f-9172-a5d82eb283f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9951082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.9951082
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1436550353
Short name T136
Test name
Test status
Simulation time 31443544 ps
CPU time 1.18 seconds
Started Jul 05 05:48:22 PM PDT 24
Finished Jul 05 05:48:23 PM PDT 24
Peak memory 218508 kb
Host smart-1654601a-439f-4404-a2a7-a8e75e697f29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436550353 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1436550353
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.818263508
Short name T112
Test name
Test status
Simulation time 44742861 ps
CPU time 1.2 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 217216 kb
Host smart-28abc528-f527-4de2-8aa7-0905e2700ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818263508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.818263508
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable.1191129700
Short name T194
Test name
Test status
Simulation time 20875116 ps
CPU time 0.91 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 216504 kb
Host smart-d0f8d87b-e6c6-471b-a18a-1c5487a293e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191129700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1191129700
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2323706122
Short name T140
Test name
Test status
Simulation time 70632230 ps
CPU time 1.12 seconds
Started Jul 05 05:48:33 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 217092 kb
Host smart-6af28e00-dab8-48c0-8629-be304f2ed6f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323706122 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2323706122
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.779634475
Short name T201
Test name
Test status
Simulation time 27532889 ps
CPU time 1.15 seconds
Started Jul 05 05:48:32 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 217348 kb
Host smart-d8536498-5f2d-459e-ba08-9eadd875a8f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779634475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.779634475
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable.2057860648
Short name T183
Test name
Test status
Simulation time 11870291 ps
CPU time 0.9 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:48 PM PDT 24
Peak memory 216832 kb
Host smart-ead892f1-1b3e-478c-801c-9a9328556561
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057860648 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2057860648
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.3383247789
Short name T191
Test name
Test status
Simulation time 18191393 ps
CPU time 0.96 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 216872 kb
Host smart-64c84056-97ab-4513-86a3-bd3833b310ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383247789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3383247789
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.182868364
Short name T174
Test name
Test status
Simulation time 19278325 ps
CPU time 1.1 seconds
Started Jul 05 05:48:55 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 218648 kb
Host smart-3f183d97-9a85-4f84-af0d-0de3ae3252ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182868364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.182868364
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/41.edn_err.2892880183
Short name T570
Test name
Test status
Simulation time 23671468 ps
CPU time 1.02 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 224260 kb
Host smart-2b4270bc-f228-4abe-9795-47345e566879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892880183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2892880183
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3892445670
Short name T89
Test name
Test status
Simulation time 51492764 ps
CPU time 1.82 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 220424 kb
Host smart-a703c578-4ac0-42a5-8016-9d2c0e0a20da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892445670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3892445670
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1040220809
Short name T292
Test name
Test status
Simulation time 105948049 ps
CPU time 2.32 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 220176 kb
Host smart-c1a58133-76e8-4ee9-a9b9-15d6377f315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040220809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1040220809
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.2628238553
Short name T72
Test name
Test status
Simulation time 71771240 ps
CPU time 0.9 seconds
Started Jul 05 05:47:39 PM PDT 24
Finished Jul 05 05:47:40 PM PDT 24
Peak memory 207060 kb
Host smart-f859097c-8561-4841-b6de-20a8b5800782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628238553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2628238553
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/77.edn_genbits.423874952
Short name T18
Test name
Test status
Simulation time 87149931 ps
CPU time 1.33 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 220412 kb
Host smart-2976c379-0947-4d23-85e4-f76759a140e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423874952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.423874952
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3291196553
Short name T690
Test name
Test status
Simulation time 129266814 ps
CPU time 1.4 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220260 kb
Host smart-267c0af7-8c91-4707-9004-0e59099411e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291196553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3291196553
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.640641266
Short name T835
Test name
Test status
Simulation time 29324280 ps
CPU time 1.23 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 220372 kb
Host smart-437ccc4a-a0f0-4d87-8918-34b8e7b1289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640641266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.640641266
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/47.edn_intr.3891633027
Short name T30
Test name
Test status
Simulation time 27302210 ps
CPU time 1.17 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 217000 kb
Host smart-a5ac66eb-3329-4023-98e0-b6c9ccfbca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891633027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3891633027
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2969526993
Short name T1045
Test name
Test status
Simulation time 114462610 ps
CPU time 2.8 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 215244 kb
Host smart-9a352e1e-e999-4249-bb46-8a86dd9815e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969526993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2969526993
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2757205414
Short name T861
Test name
Test status
Simulation time 61197057 ps
CPU time 1.2 seconds
Started Jul 05 05:47:40 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 217512 kb
Host smart-613e4c6a-1265-4e5f-92db-1130ddff263a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757205414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2757205414
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.476893717
Short name T211
Test name
Test status
Simulation time 79434348035 ps
CPU time 863.79 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 06:02:06 PM PDT 24
Peak memory 222052 kb
Host smart-66847e63-c7c1-4eb8-b696-0b2e7e9e12b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476893717 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.476893717
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3149258013
Short name T309
Test name
Test status
Simulation time 53615344 ps
CPU time 1.57 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 219096 kb
Host smart-26fd11da-1389-46c7-a1ea-f1b2c62d38f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149258013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3149258013
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1421059212
Short name T181
Test name
Test status
Simulation time 172990938 ps
CPU time 1.24 seconds
Started Jul 05 05:49:57 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 216048 kb
Host smart-870dde5b-258c-4ec8-808e-c602f893f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421059212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1421059212
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1638273155
Short name T929
Test name
Test status
Simulation time 56407117 ps
CPU time 1.74 seconds
Started Jul 05 05:49:59 PM PDT 24
Finished Jul 05 05:50:01 PM PDT 24
Peak memory 217708 kb
Host smart-e1e680a5-c2ff-493e-8327-de71f8ac0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638273155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1638273155
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1964421795
Short name T68
Test name
Test status
Simulation time 37232186 ps
CPU time 1.38 seconds
Started Jul 05 05:52:44 PM PDT 24
Finished Jul 05 05:52:47 PM PDT 24
Peak memory 218880 kb
Host smart-97d16978-87cb-4c42-8c92-5949dd995fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964421795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1964421795
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.114438722
Short name T569
Test name
Test status
Simulation time 6971386778 ps
CPU time 93.5 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220744 kb
Host smart-9d14f377-a17c-4840-a5c0-75a1a5e3b511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114438722 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.114438722
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_genbits.3166525165
Short name T290
Test name
Test status
Simulation time 95751907 ps
CPU time 1.29 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 219248 kb
Host smart-08e65f45-ef01-4b5b-bf6b-f6a57e13d54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166525165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3166525165
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_stress_all.3701370960
Short name T317
Test name
Test status
Simulation time 183658328 ps
CPU time 2.93 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:35 PM PDT 24
Peak memory 215656 kb
Host smart-97406913-01eb-4aff-b1c0-d55a9b0a6a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701370960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3701370960
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_genbits.152948855
Short name T301
Test name
Test status
Simulation time 29871046 ps
CPU time 1.38 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 217916 kb
Host smart-6612047e-a065-4320-8eed-cea79254a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152948855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.152948855
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_genbits.3727682730
Short name T312
Test name
Test status
Simulation time 77805996 ps
CPU time 1.44 seconds
Started Jul 05 05:48:43 PM PDT 24
Finished Jul 05 05:48:45 PM PDT 24
Peak memory 219300 kb
Host smart-b04f1ace-c875-415a-a085-20b43d35fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727682730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3727682730
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_genbits.182732529
Short name T297
Test name
Test status
Simulation time 56507650 ps
CPU time 2.14 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 217924 kb
Host smart-72bdd288-1885-4d14-bb22-e67598b154a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182732529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.182732529
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.851843440
Short name T35
Test name
Test status
Simulation time 23043230 ps
CPU time 0.97 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 216140 kb
Host smart-157e958d-43ec-4f05-820b-86c6f797fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851843440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.851843440
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/14.edn_err.4088376798
Short name T5
Test name
Test status
Simulation time 26447887 ps
CPU time 1 seconds
Started Jul 05 05:48:23 PM PDT 24
Finished Jul 05 05:48:25 PM PDT 24
Peak memory 220220 kb
Host smart-1f1bc505-0148-4272-b3ec-87a5d4d2102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088376798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4088376798
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/102.edn_genbits.2876503710
Short name T892
Test name
Test status
Simulation time 160788744 ps
CPU time 1.86 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 219500 kb
Host smart-c346abbe-98b2-476b-b9e8-2869fce7bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876503710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2876503710
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2743964783
Short name T910
Test name
Test status
Simulation time 107831156 ps
CPU time 1.45 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 219920 kb
Host smart-3c739a6e-3858-40d4-8c80-65bbcacb177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743964783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2743964783
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3355155000
Short name T1124
Test name
Test status
Simulation time 34600097 ps
CPU time 1.44 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206984 kb
Host smart-5a211b03-6ac0-47df-83fe-12725744e757
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355155000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3355155000
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.711194869
Short name T999
Test name
Test status
Simulation time 58941385 ps
CPU time 3.38 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 207028 kb
Host smart-0d9b7964-ef67-4364-81fd-8ef85a8bbe2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711194869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.711194869
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2583196834
Short name T244
Test name
Test status
Simulation time 24975329 ps
CPU time 0.97 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:53 PM PDT 24
Peak memory 206956 kb
Host smart-a196ecd9-fb82-402c-96e9-7dcb93c49f95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583196834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2583196834
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1072987479
Short name T1018
Test name
Test status
Simulation time 38783786 ps
CPU time 1.38 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 215232 kb
Host smart-ecb0e749-6d75-4dcb-9013-a6013abb1d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072987479 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1072987479
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3646989199
Short name T1000
Test name
Test status
Simulation time 48767176 ps
CPU time 0.94 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206916 kb
Host smart-18c99eec-7dee-4b3b-b94a-87df0152d3ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646989199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3646989199
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1587379308
Short name T1129
Test name
Test status
Simulation time 17336122 ps
CPU time 0.9 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206896 kb
Host smart-84e9587c-61ec-4290-a1dc-90a26c4b6985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587379308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1587379308
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4130647907
Short name T1116
Test name
Test status
Simulation time 96268061 ps
CPU time 1.04 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206852 kb
Host smart-020cc4c8-a68f-47c0-b7da-e2eebf01b93c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130647907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4130647907
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4243472387
Short name T1083
Test name
Test status
Simulation time 32831662 ps
CPU time 1.52 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 215272 kb
Host smart-665a152f-0c18-4923-8c33-07012d8c4e11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243472387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4243472387
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1176651373
Short name T241
Test name
Test status
Simulation time 42616264 ps
CPU time 1.14 seconds
Started Jul 05 05:13:51 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 207060 kb
Host smart-e4b87c29-075e-4caa-a30c-99e13e4006f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176651373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1176651373
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1609241789
Short name T1043
Test name
Test status
Simulation time 210940594 ps
CPU time 3.4 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 206948 kb
Host smart-9918badd-f313-4733-9ad5-06acf55356ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609241789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1609241789
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.647832416
Short name T1118
Test name
Test status
Simulation time 48394847 ps
CPU time 0.93 seconds
Started Jul 05 05:13:54 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 206964 kb
Host smart-b6ce04dc-ae66-443e-9b48-25e722e1ead4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647832416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.647832416
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2871227942
Short name T1122
Test name
Test status
Simulation time 21652337 ps
CPU time 1.08 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 206916 kb
Host smart-24d9be42-d0b8-4e80-ba86-f219a5156489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871227942 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2871227942
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.776387632
Short name T234
Test name
Test status
Simulation time 22052073 ps
CPU time 0.86 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206912 kb
Host smart-fa102a80-30e5-4a76-b343-010bf1144494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776387632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.776387632
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.791920842
Short name T1042
Test name
Test status
Simulation time 16778241 ps
CPU time 0.91 seconds
Started Jul 05 05:13:52 PM PDT 24
Finished Jul 05 05:13:54 PM PDT 24
Peak memory 206856 kb
Host smart-30b59767-fe7d-4136-adbf-f2883f2366bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791920842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.791920842
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.76046973
Short name T1038
Test name
Test status
Simulation time 18334425 ps
CPU time 1.25 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 207028 kb
Host smart-4d5c2bf4-d30f-4ded-9215-f4595223262c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76046973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outs
tanding.76046973
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.572061635
Short name T1017
Test name
Test status
Simulation time 235445681 ps
CPU time 2.36 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 215164 kb
Host smart-7f4e0342-4f5b-4909-8500-70b36d296852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572061635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.572061635
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2110645405
Short name T1087
Test name
Test status
Simulation time 141161352 ps
CPU time 3.08 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 206932 kb
Host smart-8146b0b7-c8f2-47de-b0b5-502984dcda9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110645405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2110645405
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.992645247
Short name T1065
Test name
Test status
Simulation time 34903063 ps
CPU time 1.22 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 217744 kb
Host smart-3d4b36c1-4d1c-4754-b4cc-3d55af0d57f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992645247 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.992645247
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3135700813
Short name T242
Test name
Test status
Simulation time 42902091 ps
CPU time 0.92 seconds
Started Jul 05 05:14:08 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 206932 kb
Host smart-f0c6c0bb-5b0d-4dd8-9cf5-9f4428a68316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135700813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3135700813
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2304195123
Short name T1048
Test name
Test status
Simulation time 25530245 ps
CPU time 0.96 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 206836 kb
Host smart-5ee1b909-84f7-47ee-921e-da9f717a4238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304195123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2304195123
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.51616483
Short name T248
Test name
Test status
Simulation time 52787619 ps
CPU time 0.96 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206884 kb
Host smart-b1d29d2d-6b83-41ec-8dfa-304728f30726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51616483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_out
standing.51616483
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2940028044
Short name T1091
Test name
Test status
Simulation time 51065197 ps
CPU time 3.46 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 215192 kb
Host smart-c461183e-bfe7-4400-ac81-76ecd0bcca35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940028044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2940028044
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1564959934
Short name T1046
Test name
Test status
Simulation time 161464351 ps
CPU time 2.36 seconds
Started Jul 05 05:14:08 PM PDT 24
Finished Jul 05 05:14:11 PM PDT 24
Peak memory 206932 kb
Host smart-ea440885-a23d-4a89-8602-561b952471cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564959934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1564959934
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2986314884
Short name T1044
Test name
Test status
Simulation time 69600342 ps
CPU time 1.06 seconds
Started Jul 05 05:14:14 PM PDT 24
Finished Jul 05 05:14:16 PM PDT 24
Peak memory 216920 kb
Host smart-cce9d50e-d20c-4719-bd6d-204950133e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986314884 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2986314884
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3603338985
Short name T1058
Test name
Test status
Simulation time 24016262 ps
CPU time 0.89 seconds
Started Jul 05 05:14:13 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 206928 kb
Host smart-327d1e22-09e2-4403-9b8d-a75cb9551af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603338985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3603338985
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2997798698
Short name T1084
Test name
Test status
Simulation time 11542583 ps
CPU time 0.77 seconds
Started Jul 05 05:14:20 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 206604 kb
Host smart-ba32df79-912d-44e6-b2cf-cf60239ad694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997798698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2997798698
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2730286892
Short name T1061
Test name
Test status
Simulation time 45254074 ps
CPU time 1.18 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206860 kb
Host smart-ca310d03-3974-4ef6-b2bf-4793197881bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730286892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2730286892
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2996209074
Short name T1006
Test name
Test status
Simulation time 189839474 ps
CPU time 3.41 seconds
Started Jul 05 05:14:13 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 215188 kb
Host smart-e1fec70a-b910-4154-a7c5-6a94694d09ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996209074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2996209074
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2839881402
Short name T1036
Test name
Test status
Simulation time 169548692 ps
CPU time 1.57 seconds
Started Jul 05 05:14:10 PM PDT 24
Finished Jul 05 05:14:13 PM PDT 24
Peak memory 207316 kb
Host smart-849338bf-1217-4629-b703-ed1b180d893d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839881402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2839881402
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.810680090
Short name T1082
Test name
Test status
Simulation time 83355534 ps
CPU time 1.55 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 215232 kb
Host smart-9fb07c52-c0d6-457b-b979-39795a0c1ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810680090 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.810680090
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1136843266
Short name T1068
Test name
Test status
Simulation time 22305260 ps
CPU time 0.86 seconds
Started Jul 05 05:14:09 PM PDT 24
Finished Jul 05 05:14:11 PM PDT 24
Peak memory 206820 kb
Host smart-826683c1-3e4b-492a-b5b4-2d220a2b82fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136843266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1136843266
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.54927880
Short name T1070
Test name
Test status
Simulation time 70476492 ps
CPU time 0.81 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 206632 kb
Host smart-964bc950-774f-4dcb-afe5-ff41bc0350e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54927880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.54927880
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.248610152
Short name T1026
Test name
Test status
Simulation time 43938735 ps
CPU time 0.95 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 207056 kb
Host smart-4ebaf875-5702-435c-9095-ebd412f697fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248610152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.248610152
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1393281024
Short name T1077
Test name
Test status
Simulation time 42962307 ps
CPU time 3.03 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 215156 kb
Host smart-9ecea644-219e-49c5-9124-59430106496b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393281024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1393281024
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1077038161
Short name T268
Test name
Test status
Simulation time 87290683 ps
CPU time 1.52 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 206932 kb
Host smart-ceb8cd57-68e8-4456-b0fe-c2e8ebb338c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077038161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1077038161
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1423759843
Short name T1049
Test name
Test status
Simulation time 46674397 ps
CPU time 1.27 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:19 PM PDT 24
Peak memory 215096 kb
Host smart-eeea80d3-167d-45f7-9ba3-b3105d8d7da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423759843 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1423759843
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2215075484
Short name T236
Test name
Test status
Simulation time 14593325 ps
CPU time 0.93 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 206868 kb
Host smart-a786c42c-4484-4ba9-8c8f-983d9fbcbce0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215075484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2215075484
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1528458294
Short name T1076
Test name
Test status
Simulation time 15379811 ps
CPU time 0.91 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:13 PM PDT 24
Peak memory 206808 kb
Host smart-7b0498eb-fe35-4974-ad1d-2d24e9dee5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528458294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1528458294
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1470321926
Short name T1111
Test name
Test status
Simulation time 38599805 ps
CPU time 1.09 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 206824 kb
Host smart-7ef922b0-6462-4f81-8727-ee2a4994d571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470321926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1470321926
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1466381712
Short name T1010
Test name
Test status
Simulation time 19749099 ps
CPU time 1.46 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 215200 kb
Host smart-10eb1082-52dc-4cbc-89c4-91bfa3b91748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466381712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1466381712
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.855531002
Short name T1009
Test name
Test status
Simulation time 42146383 ps
CPU time 2.21 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:21 PM PDT 24
Peak memory 215180 kb
Host smart-35263a22-27bf-4e3c-99b1-4330051fddc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855531002 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.855531002
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.298121724
Short name T1125
Test name
Test status
Simulation time 23898546 ps
CPU time 0.84 seconds
Started Jul 05 05:14:13 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 206752 kb
Host smart-c8d3b04a-82f6-4707-a2e7-11d6b3f771ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298121724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.298121724
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.308146391
Short name T1073
Test name
Test status
Simulation time 51113550 ps
CPU time 0.91 seconds
Started Jul 05 05:14:14 PM PDT 24
Finished Jul 05 05:14:16 PM PDT 24
Peak memory 206952 kb
Host smart-a5b6e994-9665-4c88-afe4-afe6b3da3a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308146391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.308146391
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1360832981
Short name T254
Test name
Test status
Simulation time 190166962 ps
CPU time 1.21 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:15 PM PDT 24
Peak memory 206896 kb
Host smart-f82fbe56-6383-4c07-99f8-8f23f4862005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360832981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1360832981
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2703359681
Short name T1053
Test name
Test status
Simulation time 40689730 ps
CPU time 2.7 seconds
Started Jul 05 05:14:09 PM PDT 24
Finished Jul 05 05:14:12 PM PDT 24
Peak memory 223464 kb
Host smart-27076f07-59ee-4c94-aa4f-38dfc8b644ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703359681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2703359681
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.771815647
Short name T259
Test name
Test status
Simulation time 173995634 ps
CPU time 1.68 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 215180 kb
Host smart-d10bbe0a-4ec3-4eaf-bc33-c03dda250bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771815647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.771815647
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1848991662
Short name T1031
Test name
Test status
Simulation time 43302085 ps
CPU time 1.55 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 219524 kb
Host smart-5a954178-fccb-4a54-abf2-c78387b7ac66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848991662 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1848991662
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.172469267
Short name T1016
Test name
Test status
Simulation time 20537608 ps
CPU time 0.94 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:14 PM PDT 24
Peak memory 206868 kb
Host smart-427c0e2c-2583-4152-956b-6e342694a1e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172469267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.172469267
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2230772057
Short name T1054
Test name
Test status
Simulation time 27372810 ps
CPU time 0.86 seconds
Started Jul 05 05:14:20 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 206776 kb
Host smart-db03e974-4e36-4bb3-bf2b-6988dd3b2e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230772057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2230772057
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2441825960
Short name T1037
Test name
Test status
Simulation time 62036470 ps
CPU time 1.29 seconds
Started Jul 05 05:14:11 PM PDT 24
Finished Jul 05 05:14:13 PM PDT 24
Peak memory 206964 kb
Host smart-ded57050-6423-4dee-a3c9-afbd9206a511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441825960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2441825960
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2641793543
Short name T1047
Test name
Test status
Simulation time 87299056 ps
CPU time 3.36 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:16 PM PDT 24
Peak memory 215192 kb
Host smart-817396d1-2b0d-4073-9828-895c01d9092e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641793543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2641793543
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1147262637
Short name T266
Test name
Test status
Simulation time 86152439 ps
CPU time 1.64 seconds
Started Jul 05 05:14:10 PM PDT 24
Finished Jul 05 05:14:12 PM PDT 24
Peak memory 207012 kb
Host smart-795d3cbe-3624-4cc7-97ba-2ae96095092e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147262637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1147262637
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1952604358
Short name T1104
Test name
Test status
Simulation time 41474075 ps
CPU time 2.13 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 215076 kb
Host smart-32c6aeef-bae0-4845-b8ac-139a02cb18ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952604358 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1952604358
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3323723767
Short name T1069
Test name
Test status
Simulation time 44188193 ps
CPU time 0.88 seconds
Started Jul 05 05:14:20 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 206920 kb
Host smart-a1323894-3c8a-45dd-a586-5614a5da5dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323723767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3323723767
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.362625460
Short name T1019
Test name
Test status
Simulation time 20450388 ps
CPU time 0.8 seconds
Started Jul 05 05:14:09 PM PDT 24
Finished Jul 05 05:14:11 PM PDT 24
Peak memory 206672 kb
Host smart-5a152b6d-7368-4c8c-90a9-6f9a945dd35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362625460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.362625460
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1351983345
Short name T1093
Test name
Test status
Simulation time 22869447 ps
CPU time 0.97 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206988 kb
Host smart-9f53aba7-7c03-4f43-88e9-c52c1b7b60f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351983345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1351983345
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1011261873
Short name T1035
Test name
Test status
Simulation time 154104689 ps
CPU time 2.8 seconds
Started Jul 05 05:14:12 PM PDT 24
Finished Jul 05 05:14:16 PM PDT 24
Peak memory 215192 kb
Host smart-cebae2eb-771e-4e6d-9f14-f15f96106862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011261873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1011261873
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2738777858
Short name T1113
Test name
Test status
Simulation time 683068582 ps
CPU time 2.3 seconds
Started Jul 05 05:14:15 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 206992 kb
Host smart-74d46e9f-77e7-4bcf-83fc-b89be4582869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738777858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2738777858
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.601606869
Short name T1032
Test name
Test status
Simulation time 20877397 ps
CPU time 1.17 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 215132 kb
Host smart-01c6b29c-6a9f-4367-83ee-ccfdbcab3740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601606869 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.601606869
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.267255901
Short name T1100
Test name
Test status
Simulation time 13012088 ps
CPU time 0.87 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:19 PM PDT 24
Peak memory 206948 kb
Host smart-597751fd-70ae-4f0a-b4e4-47327e6fdd02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267255901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.267255901
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2162223562
Short name T1021
Test name
Test status
Simulation time 35176553 ps
CPU time 0.82 seconds
Started Jul 05 05:14:16 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 206800 kb
Host smart-d47c89a8-64da-4bb0-a49e-be43cf047d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162223562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2162223562
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3389493236
Short name T1086
Test name
Test status
Simulation time 65023041 ps
CPU time 1.26 seconds
Started Jul 05 05:14:29 PM PDT 24
Finished Jul 05 05:14:33 PM PDT 24
Peak memory 206784 kb
Host smart-72b45f27-b680-4933-87b9-b14a4100d3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389493236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3389493236
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3552120185
Short name T1015
Test name
Test status
Simulation time 78634164 ps
CPU time 2.59 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 215200 kb
Host smart-8278f5a6-d381-452b-a085-e5c7625296c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552120185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3552120185
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1997092729
Short name T265
Test name
Test status
Simulation time 127161001 ps
CPU time 1.52 seconds
Started Jul 05 05:14:23 PM PDT 24
Finished Jul 05 05:14:25 PM PDT 24
Peak memory 206964 kb
Host smart-b9fc4abe-e115-4b75-ab25-a88225bc1819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997092729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1997092729
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2759351447
Short name T1033
Test name
Test status
Simulation time 42383525 ps
CPU time 1.21 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 215156 kb
Host smart-3b3c142a-624e-410d-8cd5-0621b8628c05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759351447 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2759351447
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3637519970
Short name T1008
Test name
Test status
Simulation time 19742977 ps
CPU time 1.01 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:21 PM PDT 24
Peak memory 206944 kb
Host smart-f67f33c8-d1fe-4985-b7f1-3eb635a6005f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637519970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3637519970
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1578057197
Short name T1023
Test name
Test status
Simulation time 33914359 ps
CPU time 0.82 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:19 PM PDT 24
Peak memory 206688 kb
Host smart-fdc3aaa1-1018-4fb9-898b-e5c5b7baaf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578057197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1578057197
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2146716482
Short name T1102
Test name
Test status
Simulation time 27003116 ps
CPU time 1.18 seconds
Started Jul 05 05:14:29 PM PDT 24
Finished Jul 05 05:14:33 PM PDT 24
Peak memory 206688 kb
Host smart-100b13a0-f0b3-4fac-a7de-7a641d3caf63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146716482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2146716482
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2015088736
Short name T1096
Test name
Test status
Simulation time 57373908 ps
CPU time 2.23 seconds
Started Jul 05 05:14:22 PM PDT 24
Finished Jul 05 05:14:24 PM PDT 24
Peak memory 215188 kb
Host smart-69408c8b-dbfd-4bcc-a620-d2d87f885c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015088736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2015088736
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3360530788
Short name T1080
Test name
Test status
Simulation time 76837749 ps
CPU time 2.12 seconds
Started Jul 05 05:14:19 PM PDT 24
Finished Jul 05 05:14:23 PM PDT 24
Peak memory 207004 kb
Host smart-f5a5203a-953f-41b4-a290-2b9bb7d9be31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360530788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3360530788
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2319693015
Short name T997
Test name
Test status
Simulation time 32582526 ps
CPU time 2.02 seconds
Started Jul 05 05:14:23 PM PDT 24
Finished Jul 05 05:14:25 PM PDT 24
Peak memory 215272 kb
Host smart-44ea0d98-3f95-4459-abf4-5fb76f4e14e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319693015 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2319693015
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3313064867
Short name T238
Test name
Test status
Simulation time 15238171 ps
CPU time 0.93 seconds
Started Jul 05 05:14:19 PM PDT 24
Finished Jul 05 05:14:21 PM PDT 24
Peak memory 206924 kb
Host smart-1d52d8a3-1786-486e-907a-aa1cb90b7a3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313064867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3313064867
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2919691065
Short name T1079
Test name
Test status
Simulation time 15589741 ps
CPU time 0.9 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206864 kb
Host smart-883fd318-49d9-43ed-b435-66e101ba2c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919691065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2919691065
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1007731718
Short name T1060
Test name
Test status
Simulation time 265132046 ps
CPU time 1.43 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:21 PM PDT 24
Peak memory 206932 kb
Host smart-497e4983-30ca-43a6-a28a-e6634a932fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007731718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1007731718
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1168833769
Short name T1056
Test name
Test status
Simulation time 445399095 ps
CPU time 4.4 seconds
Started Jul 05 05:14:29 PM PDT 24
Finished Jul 05 05:14:36 PM PDT 24
Peak memory 215184 kb
Host smart-0bc3389f-af65-4079-9df1-1209881362f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168833769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1168833769
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2434949976
Short name T270
Test name
Test status
Simulation time 414230548 ps
CPU time 2.82 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 207024 kb
Host smart-ea724af8-54d8-46f7-8ab1-7d655ec6e75c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434949976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2434949976
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.608691702
Short name T237
Test name
Test status
Simulation time 29145356 ps
CPU time 1.24 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 206948 kb
Host smart-4b1dc6ac-cd1f-4ca9-8f0d-6654fb569280
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608691702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.608691702
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3286480774
Short name T246
Test name
Test status
Simulation time 195570652 ps
CPU time 3.47 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:12 PM PDT 24
Peak memory 206852 kb
Host smart-0c72c884-0827-449d-90c2-7ec5cae021b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286480774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3286480774
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1072646765
Short name T1027
Test name
Test status
Simulation time 12873714 ps
CPU time 0.9 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206916 kb
Host smart-400396a5-1a30-444e-bf58-85f18abc12c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072646765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1072646765
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.822715403
Short name T1001
Test name
Test status
Simulation time 37036674 ps
CPU time 1.62 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 218720 kb
Host smart-bad4eb99-4aa7-4c93-aa57-c5a6c3149a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822715403 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.822715403
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1925109038
Short name T239
Test name
Test status
Simulation time 16431057 ps
CPU time 0.95 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 206912 kb
Host smart-93c4636e-fea5-4fbb-ac84-6785056bf255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925109038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1925109038
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4148821300
Short name T1095
Test name
Test status
Simulation time 15181853 ps
CPU time 0.87 seconds
Started Jul 05 05:13:54 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 206860 kb
Host smart-ab9d5c14-ec27-45a4-af58-61d8b4f7d965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148821300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4148821300
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1655265986
Short name T1055
Test name
Test status
Simulation time 51747152 ps
CPU time 1.1 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 206816 kb
Host smart-16902245-568e-447a-a44f-801be268eddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655265986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1655265986
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2668402727
Short name T1057
Test name
Test status
Simulation time 287678482 ps
CPU time 2.69 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 215188 kb
Host smart-85ffed03-90ef-4b36-992d-61b2baa8f4df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668402727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2668402727
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.265999972
Short name T260
Test name
Test status
Simulation time 560967289 ps
CPU time 1.67 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 206944 kb
Host smart-89eac68a-4e41-4e42-a4e5-2e308a2ca2b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265999972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.265999972
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2326995126
Short name T1089
Test name
Test status
Simulation time 21405338 ps
CPU time 0.8 seconds
Started Jul 05 05:14:21 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 206772 kb
Host smart-5aba3b84-fb73-4e42-93ce-5a7c6a2f7742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326995126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2326995126
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1478143328
Short name T1050
Test name
Test status
Simulation time 15350986 ps
CPU time 0.84 seconds
Started Jul 05 05:14:20 PM PDT 24
Finished Jul 05 05:14:22 PM PDT 24
Peak memory 206872 kb
Host smart-19ab6fcd-a9a2-4ad9-9c63-18eed9d1319b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478143328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1478143328
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3081140177
Short name T1110
Test name
Test status
Simulation time 13149776 ps
CPU time 0.89 seconds
Started Jul 05 05:14:19 PM PDT 24
Finished Jul 05 05:14:21 PM PDT 24
Peak memory 206796 kb
Host smart-f31de71c-9fc8-4350-85bb-d546027e1dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081140177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3081140177
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2711386122
Short name T1064
Test name
Test status
Simulation time 36808546 ps
CPU time 0.87 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 206636 kb
Host smart-9c929c7f-21c5-403a-9a58-f55751471087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711386122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2711386122
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3226541488
Short name T998
Test name
Test status
Simulation time 20048406 ps
CPU time 0.82 seconds
Started Jul 05 05:14:15 PM PDT 24
Finished Jul 05 05:14:17 PM PDT 24
Peak memory 206604 kb
Host smart-3fb55e1a-93e6-4f69-8813-8860d336948d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226541488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3226541488
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1125316620
Short name T1099
Test name
Test status
Simulation time 15433176 ps
CPU time 0.88 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206868 kb
Host smart-03b17e65-579f-4237-8a62-727ab6d7d945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125316620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1125316620
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3868422920
Short name T1119
Test name
Test status
Simulation time 26155756 ps
CPU time 0.88 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 206860 kb
Host smart-c9d5a5f2-7f61-4544-9bb3-a0e59504e62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868422920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3868422920
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3193307337
Short name T1128
Test name
Test status
Simulation time 29360319 ps
CPU time 0.94 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206880 kb
Host smart-6ba7aada-a697-4d83-aacb-8ca5687a15e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193307337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3193307337
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2261017282
Short name T1098
Test name
Test status
Simulation time 112138678 ps
CPU time 0.92 seconds
Started Jul 05 05:14:17 PM PDT 24
Finished Jul 05 05:14:18 PM PDT 24
Peak memory 206900 kb
Host smart-40800af2-ae2c-49ab-a209-4483a76dd5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261017282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2261017282
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3080863588
Short name T1075
Test name
Test status
Simulation time 15808703 ps
CPU time 0.91 seconds
Started Jul 05 05:14:22 PM PDT 24
Finished Jul 05 05:14:23 PM PDT 24
Peak memory 206776 kb
Host smart-ffbd1d88-7530-4f16-8051-186e97be1766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080863588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3080863588
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3082505906
Short name T240
Test name
Test status
Simulation time 21567368 ps
CPU time 1.28 seconds
Started Jul 05 05:14:06 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206980 kb
Host smart-092b96c7-d883-4262-8890-ae4b14939653
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082505906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3082505906
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1331187394
Short name T1066
Test name
Test status
Simulation time 558210101 ps
CPU time 6.52 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206928 kb
Host smart-8997cc21-8cea-458e-aee8-5042f70b690a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331187394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1331187394
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2389072436
Short name T243
Test name
Test status
Simulation time 13947952 ps
CPU time 0.92 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206808 kb
Host smart-6a291ed3-5fc4-4d9f-9a21-cc9b7470d5e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389072436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2389072436
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2226008492
Short name T1117
Test name
Test status
Simulation time 66885341 ps
CPU time 1.26 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 215252 kb
Host smart-0f24cb78-3f18-4c0b-a1b1-ece25b6d636c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226008492 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2226008492
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3545432895
Short name T245
Test name
Test status
Simulation time 32073953 ps
CPU time 0.79 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 206736 kb
Host smart-f7e543d6-a499-4b20-a7be-370d6fb15d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545432895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3545432895
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3562545347
Short name T1052
Test name
Test status
Simulation time 47318051 ps
CPU time 0.83 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:13:58 PM PDT 24
Peak memory 206644 kb
Host smart-e87a5640-f447-4dbb-9a17-0ecce3296c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562545347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3562545347
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1025538129
Short name T247
Test name
Test status
Simulation time 136447236 ps
CPU time 1.4 seconds
Started Jul 05 05:13:55 PM PDT 24
Finished Jul 05 05:13:57 PM PDT 24
Peak memory 206804 kb
Host smart-d1f0f7d7-87bb-4d59-94d8-f143b34fcf12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025538129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1025538129
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1426506748
Short name T1041
Test name
Test status
Simulation time 115716647 ps
CPU time 2.14 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 215024 kb
Host smart-063d2642-92ec-4dc8-8416-9129ac81f023
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426506748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1426506748
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.296969160
Short name T1121
Test name
Test status
Simulation time 389597180 ps
CPU time 2.33 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 206872 kb
Host smart-b185b665-6657-414c-af24-2c179277dc97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296969160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.296969160
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3472955181
Short name T1034
Test name
Test status
Simulation time 41783733 ps
CPU time 0.86 seconds
Started Jul 05 05:14:18 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 206688 kb
Host smart-7c7544d7-19de-4894-910e-8a7afde51ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472955181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3472955181
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3782002012
Short name T1028
Test name
Test status
Simulation time 20118563 ps
CPU time 0.84 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 206808 kb
Host smart-2ea69ad1-cd72-4656-99ec-a3dd24c5f9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782002012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3782002012
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3498956360
Short name T1014
Test name
Test status
Simulation time 43117090 ps
CPU time 0.87 seconds
Started Jul 05 05:14:27 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 206876 kb
Host smart-1fe22d92-4c5d-4231-b9af-6ee443edaafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498956360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3498956360
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3206783616
Short name T1088
Test name
Test status
Simulation time 24900159 ps
CPU time 0.84 seconds
Started Jul 05 05:14:24 PM PDT 24
Finished Jul 05 05:14:26 PM PDT 24
Peak memory 206860 kb
Host smart-c28925f4-ef97-4483-a78d-777f77f3362f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206783616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3206783616
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1168086807
Short name T996
Test name
Test status
Simulation time 16345554 ps
CPU time 0.92 seconds
Started Jul 05 05:14:27 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 206860 kb
Host smart-4a4c7201-3501-4c50-8b0b-55019ad86690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168086807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1168086807
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3886670022
Short name T1085
Test name
Test status
Simulation time 40228072 ps
CPU time 0.87 seconds
Started Jul 05 05:14:26 PM PDT 24
Finished Jul 05 05:14:30 PM PDT 24
Peak memory 206864 kb
Host smart-4c25690a-ab0b-4dc8-a59d-06732f9a9a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886670022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3886670022
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3424736985
Short name T1005
Test name
Test status
Simulation time 12613358 ps
CPU time 0.86 seconds
Started Jul 05 05:14:22 PM PDT 24
Finished Jul 05 05:14:24 PM PDT 24
Peak memory 206896 kb
Host smart-c8c45cd2-45bb-4041-a971-434aefc0ef93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424736985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3424736985
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1202807485
Short name T1114
Test name
Test status
Simulation time 42012939 ps
CPU time 0.85 seconds
Started Jul 05 05:14:29 PM PDT 24
Finished Jul 05 05:14:33 PM PDT 24
Peak memory 207004 kb
Host smart-506551a9-64a7-4ab4-90f2-e8c76dffbb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202807485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1202807485
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3100096595
Short name T1004
Test name
Test status
Simulation time 16604134 ps
CPU time 0.89 seconds
Started Jul 05 05:14:26 PM PDT 24
Finished Jul 05 05:14:30 PM PDT 24
Peak memory 206820 kb
Host smart-75e5f54a-120d-438a-9e94-b92d8a3c809e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100096595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3100096595
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1518600455
Short name T1072
Test name
Test status
Simulation time 21458383 ps
CPU time 0.86 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 206776 kb
Host smart-cfd6ccef-27df-44e9-8941-c5c0875f0cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518600455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1518600455
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4193021077
Short name T1101
Test name
Test status
Simulation time 102390326 ps
CPU time 1.29 seconds
Started Jul 05 05:13:59 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 206924 kb
Host smart-9b4ec4a6-09d8-42d7-9a84-b6d69b5c82be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193021077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4193021077
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3024026292
Short name T1127
Test name
Test status
Simulation time 97158916 ps
CPU time 3 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 206936 kb
Host smart-7a8deb49-1ee1-4758-ae9c-3385c002dcb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024026292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3024026292
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.934826898
Short name T1002
Test name
Test status
Simulation time 121424023 ps
CPU time 0.9 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206848 kb
Host smart-f7a50208-b02d-4a78-bf68-1d6be35785b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934826898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.934826898
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3075824342
Short name T1078
Test name
Test status
Simulation time 29099985 ps
CPU time 1.08 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 216468 kb
Host smart-ceac438c-bf6e-4795-ad89-83e73a150b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075824342 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3075824342
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.364218793
Short name T249
Test name
Test status
Simulation time 41319986 ps
CPU time 0.87 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206892 kb
Host smart-4ead4ae1-2d9f-4dd0-9e72-92a76cc95e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364218793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.364218793
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3079282364
Short name T1011
Test name
Test status
Simulation time 35873863 ps
CPU time 0.84 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:13:59 PM PDT 24
Peak memory 206832 kb
Host smart-f4f4cc4d-e9e1-45f9-84a5-de5e4cfc821b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079282364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3079282364
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4051008534
Short name T253
Test name
Test status
Simulation time 22089432 ps
CPU time 1.02 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 206904 kb
Host smart-b0b75a1a-24fe-4332-9db6-62c6ec2c6442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051008534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4051008534
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.237758444
Short name T1067
Test name
Test status
Simulation time 386730124 ps
CPU time 3.09 seconds
Started Jul 05 05:13:59 PM PDT 24
Finished Jul 05 05:14:04 PM PDT 24
Peak memory 215176 kb
Host smart-28cd4f48-485d-4f42-add6-3bfc4e4fa427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237758444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.237758444
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3172261180
Short name T1062
Test name
Test status
Simulation time 170530027 ps
CPU time 1.73 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 206996 kb
Host smart-90072244-4348-402a-be91-3e572f466ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172261180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3172261180
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.720245818
Short name T1007
Test name
Test status
Simulation time 47112014 ps
CPU time 0.87 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:28 PM PDT 24
Peak memory 206856 kb
Host smart-8e08fbd0-402e-48f0-addf-58470ead1d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720245818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.720245818
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4167717145
Short name T1094
Test name
Test status
Simulation time 32813287 ps
CPU time 0.81 seconds
Started Jul 05 05:14:27 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 206660 kb
Host smart-8b5f4f5e-f32e-4b67-9dfc-e5f63e9c9d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167717145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4167717145
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2825639292
Short name T1107
Test name
Test status
Simulation time 14733041 ps
CPU time 0.9 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 206868 kb
Host smart-9a2d4bb1-9b44-4616-b493-fa9e854562b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825639292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2825639292
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3877099818
Short name T1103
Test name
Test status
Simulation time 13616325 ps
CPU time 0.88 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:29 PM PDT 24
Peak memory 206860 kb
Host smart-329aa918-a6b3-448d-b9cf-f83009f61319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877099818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3877099818
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.678461377
Short name T1120
Test name
Test status
Simulation time 38244203 ps
CPU time 0.92 seconds
Started Jul 05 05:14:24 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 206632 kb
Host smart-f0be560f-3802-4ea4-be98-9696913df97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678461377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.678461377
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1445397387
Short name T1097
Test name
Test status
Simulation time 18189694 ps
CPU time 0.84 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 206784 kb
Host smart-3ae60ca6-c059-42f0-9131-c47d6fec4714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445397387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1445397387
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1204130806
Short name T1051
Test name
Test status
Simulation time 25875341 ps
CPU time 0.86 seconds
Started Jul 05 05:14:25 PM PDT 24
Finished Jul 05 05:14:28 PM PDT 24
Peak memory 206828 kb
Host smart-fa7c7cd7-239e-475a-b3ff-82aae4201265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204130806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1204130806
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1081506514
Short name T1012
Test name
Test status
Simulation time 135731301 ps
CPU time 0.83 seconds
Started Jul 05 05:14:26 PM PDT 24
Finished Jul 05 05:14:30 PM PDT 24
Peak memory 206936 kb
Host smart-661e54a8-f975-4b05-ae45-10f55dc5577a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081506514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1081506514
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1563662826
Short name T1130
Test name
Test status
Simulation time 24203455 ps
CPU time 0.87 seconds
Started Jul 05 05:14:26 PM PDT 24
Finished Jul 05 05:14:30 PM PDT 24
Peak memory 206908 kb
Host smart-0276a5ea-f453-477a-991f-e79c37e0c390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563662826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1563662826
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2660360721
Short name T1092
Test name
Test status
Simulation time 18387546 ps
CPU time 0.82 seconds
Started Jul 05 05:14:27 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 206688 kb
Host smart-f0a4e2f3-0480-4e33-8349-9887c3026a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660360721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2660360721
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2343406302
Short name T1025
Test name
Test status
Simulation time 79477465 ps
CPU time 1.22 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 215184 kb
Host smart-a8f4b86d-ae6c-41ee-8698-8805187886b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343406302 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2343406302
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2882636351
Short name T1126
Test name
Test status
Simulation time 44587887 ps
CPU time 0.89 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 206800 kb
Host smart-d032a4ba-502c-4327-8ed1-21d07956db28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882636351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2882636351
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.709688494
Short name T1003
Test name
Test status
Simulation time 60623361 ps
CPU time 0.86 seconds
Started Jul 05 05:13:54 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 206892 kb
Host smart-46492f98-8e19-4f2b-a65b-b0f00381acc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709688494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.709688494
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.355437327
Short name T1115
Test name
Test status
Simulation time 59559332 ps
CPU time 1.05 seconds
Started Jul 05 05:13:58 PM PDT 24
Finished Jul 05 05:14:01 PM PDT 24
Peak memory 206972 kb
Host smart-9df89aac-2fe1-4055-84ad-b1ad3c44bf85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355437327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.355437327
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.720173181
Short name T1112
Test name
Test status
Simulation time 377121425 ps
CPU time 3.32 seconds
Started Jul 05 05:13:56 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 215320 kb
Host smart-ffa524c9-2004-4889-948c-a7ee2effed40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720173181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.720173181
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2884666620
Short name T1020
Test name
Test status
Simulation time 89081178 ps
CPU time 2.78 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 207120 kb
Host smart-838d39c3-13c0-43e9-9d42-5faf0e10b9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884666620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2884666620
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.896724493
Short name T1039
Test name
Test status
Simulation time 72573533 ps
CPU time 1.46 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 215184 kb
Host smart-b2d2cf14-e82c-4a64-9a38-32d733e13c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896724493 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.896724493
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1870321021
Short name T252
Test name
Test status
Simulation time 14365458 ps
CPU time 0.96 seconds
Started Jul 05 05:13:57 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 206912 kb
Host smart-44367808-d3a6-4b4f-8fbd-ec43dc57a966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870321021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1870321021
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4036426666
Short name T1059
Test name
Test status
Simulation time 12531372 ps
CPU time 0.91 seconds
Started Jul 05 05:14:01 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 206868 kb
Host smart-ecacb2f6-96a3-4838-bcf4-7825e6ac35d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036426666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4036426666
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1065823128
Short name T250
Test name
Test status
Simulation time 68217133 ps
CPU time 1.05 seconds
Started Jul 05 05:14:07 PM PDT 24
Finished Jul 05 05:14:09 PM PDT 24
Peak memory 206832 kb
Host smart-d3b08d59-2765-4616-96a6-21d7291f2d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065823128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1065823128
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3525855551
Short name T1108
Test name
Test status
Simulation time 466334280 ps
CPU time 4.58 seconds
Started Jul 05 05:13:59 PM PDT 24
Finished Jul 05 05:14:05 PM PDT 24
Peak memory 215180 kb
Host smart-5f652c3c-936b-4cf5-a47e-f6c5f8a56b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525855551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3525855551
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3889950126
Short name T269
Test name
Test status
Simulation time 165828464 ps
CPU time 2.42 seconds
Started Jul 05 05:14:06 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 206944 kb
Host smart-4a13a8cd-1c9c-4658-8868-3929ed5bce0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889950126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3889950126
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1637093255
Short name T1090
Test name
Test status
Simulation time 44706118 ps
CPU time 1.67 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 215204 kb
Host smart-5ad7499d-164b-4ae5-9606-8a1dd2daf21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637093255 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1637093255
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1321404050
Short name T1029
Test name
Test status
Simulation time 32327572 ps
CPU time 0.87 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206684 kb
Host smart-1a7ab775-0fb5-48a5-ac04-d59849a746cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321404050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1321404050
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3257635645
Short name T1105
Test name
Test status
Simulation time 40599491 ps
CPU time 0.94 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206908 kb
Host smart-a9fde9da-479a-44a4-aa85-6ec1d463f1aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257635645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3257635645
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3073876807
Short name T1013
Test name
Test status
Simulation time 27741001 ps
CPU time 1.81 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 215120 kb
Host smart-4994349a-2d1f-413d-8f92-204ebaa186bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073876807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3073876807
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3444734082
Short name T1030
Test name
Test status
Simulation time 60069636 ps
CPU time 1.38 seconds
Started Jul 05 05:14:08 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 206952 kb
Host smart-02815540-d3ef-44e9-b6e9-4133b22b7aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444734082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3444734082
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2195943524
Short name T1024
Test name
Test status
Simulation time 30705730 ps
CPU time 2.01 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 215212 kb
Host smart-b0032aa0-6856-4619-8f9b-27be72579765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195943524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2195943524
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2461043338
Short name T1040
Test name
Test status
Simulation time 11399841 ps
CPU time 0.89 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:05 PM PDT 24
Peak memory 206916 kb
Host smart-11ec41f9-6fa1-45a4-b6d1-1ead80fe8966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461043338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2461043338
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2155384289
Short name T1022
Test name
Test status
Simulation time 20818795 ps
CPU time 0.83 seconds
Started Jul 05 05:14:04 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206816 kb
Host smart-432bbcf8-719d-4e7d-8a96-44f30068264d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155384289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2155384289
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1218677792
Short name T1071
Test name
Test status
Simulation time 247980015 ps
CPU time 1.33 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:07 PM PDT 24
Peak memory 206916 kb
Host smart-c4c15f23-74b1-4eff-bac7-3019e80a7674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218677792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1218677792
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.772206150
Short name T1109
Test name
Test status
Simulation time 212934256 ps
CPU time 3.72 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 215236 kb
Host smart-0b809d61-7f66-41c2-93d2-8583238b3b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772206150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.772206150
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2476318348
Short name T267
Test name
Test status
Simulation time 119119528 ps
CPU time 2.9 seconds
Started Jul 05 05:14:06 PM PDT 24
Finished Jul 05 05:14:10 PM PDT 24
Peak memory 206932 kb
Host smart-d5353ebe-4e01-4017-8a3a-7328a29bfcff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476318348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2476318348
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.7562288
Short name T1063
Test name
Test status
Simulation time 23480870 ps
CPU time 1.24 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 215200 kb
Host smart-3ba82542-4fd6-4e8e-bc99-bc84d92ba3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7562288 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.7562288
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3447437257
Short name T1106
Test name
Test status
Simulation time 11823594 ps
CPU time 0.84 seconds
Started Jul 05 05:14:06 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 206884 kb
Host smart-5d4e1c53-97c2-44ea-8da1-a994ddcb5709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447437257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3447437257
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2961324978
Short name T1074
Test name
Test status
Simulation time 32318541 ps
CPU time 0.88 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 206820 kb
Host smart-81cde81b-11eb-45a5-99b1-0d8f73677ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961324978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2961324978
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1772237754
Short name T251
Test name
Test status
Simulation time 14165820 ps
CPU time 0.96 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:07 PM PDT 24
Peak memory 206988 kb
Host smart-8cb88e1b-8848-4465-a473-f80c42128aa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772237754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1772237754
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3883163741
Short name T1081
Test name
Test status
Simulation time 853633392 ps
CPU time 5.05 seconds
Started Jul 05 05:14:05 PM PDT 24
Finished Jul 05 05:14:11 PM PDT 24
Peak memory 215280 kb
Host smart-2ef22ce7-ce95-41c1-809a-a10320b84ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883163741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3883163741
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4145478986
Short name T1123
Test name
Test status
Simulation time 145353600 ps
CPU time 1.53 seconds
Started Jul 05 05:14:03 PM PDT 24
Finished Jul 05 05:14:06 PM PDT 24
Peak memory 206984 kb
Host smart-4c20d943-d759-45d0-8f47-a1139c23b937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145478986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4145478986
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.1635761281
Short name T747
Test name
Test status
Simulation time 34012924 ps
CPU time 0.86 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 216592 kb
Host smart-fdeacfd0-77ff-4d12-9216-500c2b98a5c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635761281 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1635761281
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3897532031
Short name T445
Test name
Test status
Simulation time 39378836 ps
CPU time 1.05 seconds
Started Jul 05 05:47:40 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 220152 kb
Host smart-3ed51a60-0e1a-4289-84ae-24162ed05806
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897532031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3897532031
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3964750489
Short name T160
Test name
Test status
Simulation time 27899484 ps
CPU time 0.88 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 218428 kb
Host smart-103ca82e-5800-4449-b8d9-b06f068cac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964750489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3964750489
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1409078986
Short name T730
Test name
Test status
Simulation time 45531381 ps
CPU time 0.9 seconds
Started Jul 05 05:47:42 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 215836 kb
Host smart-8b56a54d-944d-455b-ab36-11bf2bba07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409078986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1409078986
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.468813373
Short name T594
Test name
Test status
Simulation time 14523143 ps
CPU time 1 seconds
Started Jul 05 05:47:42 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 207428 kb
Host smart-9caffe1f-bd60-4efd-874b-279a2fb3e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468813373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.468813373
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1773976349
Short name T705
Test name
Test status
Simulation time 15765462 ps
CPU time 0.97 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 215640 kb
Host smart-af50cbc4-06b4-47e1-9f52-6f8dba90c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773976349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1773976349
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1482487404
Short name T440
Test name
Test status
Simulation time 71991017 ps
CPU time 2.07 seconds
Started Jul 05 05:47:39 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 215688 kb
Host smart-acafc171-3755-4ee5-ad56-4bbd7a1fad1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482487404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1482487404
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.657657157
Short name T215
Test name
Test status
Simulation time 137136249531 ps
CPU time 812.41 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 06:01:16 PM PDT 24
Peak memory 224004 kb
Host smart-ada9febe-c73c-4461-9fc2-6e7cd92ae429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657657157 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.657657157
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2669382392
Short name T606
Test name
Test status
Simulation time 46613789 ps
CPU time 1.19 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 219940 kb
Host smart-c2d8adaf-acff-470c-a5b9-0b29b8895d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669382392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2669382392
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1316539883
Short name T708
Test name
Test status
Simulation time 53852729 ps
CPU time 0.83 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 206844 kb
Host smart-5d9e5d7b-1263-4054-962d-9716aec4137b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316539883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1316539883
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.1529569032
Short name T123
Test name
Test status
Simulation time 34025889 ps
CPU time 1.11 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 229936 kb
Host smart-8c52a152-d95a-4bd2-99e0-7df5d546471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529569032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1529569032
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.477545815
Short name T947
Test name
Test status
Simulation time 67190933 ps
CPU time 1.52 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:44 PM PDT 24
Peak memory 217708 kb
Host smart-174b7801-89f0-458e-aea4-dcac275770f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477545815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.477545815
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3664114028
Short name T740
Test name
Test status
Simulation time 23989176 ps
CPU time 1.03 seconds
Started Jul 05 05:47:42 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 215948 kb
Host smart-631eee16-00b7-4083-892e-430d8c525fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664114028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3664114028
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3275238433
Short name T916
Test name
Test status
Simulation time 24288913 ps
CPU time 0.9 seconds
Started Jul 05 05:47:42 PM PDT 24
Finished Jul 05 05:47:44 PM PDT 24
Peak memory 207524 kb
Host smart-988e59d2-25d2-49a7-9524-be1d4ca12a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275238433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3275238433
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3165890272
Short name T62
Test name
Test status
Simulation time 494205015 ps
CPU time 8.45 seconds
Started Jul 05 05:47:39 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 237628 kb
Host smart-20e979d1-95ae-4837-a685-09ba3a23aaff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165890272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3165890272
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1697230333
Short name T465
Test name
Test status
Simulation time 22863667 ps
CPU time 0.92 seconds
Started Jul 05 05:47:39 PM PDT 24
Finished Jul 05 05:47:41 PM PDT 24
Peak memory 215552 kb
Host smart-3dd84d64-ac2c-4897-a158-c74143773f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697230333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1697230333
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.775846458
Short name T575
Test name
Test status
Simulation time 247152030 ps
CPU time 1.92 seconds
Started Jul 05 05:47:40 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 217452 kb
Host smart-fadf4019-a8eb-430e-b085-68cd6f410cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775846458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.775846458
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.1169884484
Short name T556
Test name
Test status
Simulation time 225354950 ps
CPU time 1.28 seconds
Started Jul 05 05:48:08 PM PDT 24
Finished Jul 05 05:48:10 PM PDT 24
Peak memory 216016 kb
Host smart-20b29a8a-f7a2-456c-8254-64e12fc94d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169884484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1169884484
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2186085022
Short name T619
Test name
Test status
Simulation time 83949436 ps
CPU time 0.99 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 215484 kb
Host smart-9ef66f2c-19a7-414a-b294-4ff8ff9040f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186085022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2186085022
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1158628947
Short name T196
Test name
Test status
Simulation time 17005469 ps
CPU time 0.85 seconds
Started Jul 05 05:48:14 PM PDT 24
Finished Jul 05 05:48:15 PM PDT 24
Peak memory 216552 kb
Host smart-09609255-0414-4e9a-8b70-e634521a3c41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158628947 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1158628947
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1287330395
Short name T942
Test name
Test status
Simulation time 22130385 ps
CPU time 1.02 seconds
Started Jul 05 05:48:18 PM PDT 24
Finished Jul 05 05:48:19 PM PDT 24
Peak memory 218764 kb
Host smart-9a18238d-cb9b-4da1-a0ec-3fce41b5a4eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287330395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1287330395
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.4052240784
Short name T736
Test name
Test status
Simulation time 23776357 ps
CPU time 1.01 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 224104 kb
Host smart-0012a7b4-5899-48ea-a099-98383170c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052240784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4052240784
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.656155300
Short name T961
Test name
Test status
Simulation time 75818091 ps
CPU time 1.06 seconds
Started Jul 05 05:48:06 PM PDT 24
Finished Jul 05 05:48:08 PM PDT 24
Peak memory 217692 kb
Host smart-8a8c9844-373a-45da-b150-c9b43c410f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656155300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.656155300
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2241883957
Short name T700
Test name
Test status
Simulation time 21428910 ps
CPU time 0.92 seconds
Started Jul 05 05:48:14 PM PDT 24
Finished Jul 05 05:48:15 PM PDT 24
Peak memory 216084 kb
Host smart-6f603b7b-d1e9-49f2-be80-238eb0f73f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241883957 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2241883957
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3774126319
Short name T420
Test name
Test status
Simulation time 44777908 ps
CPU time 0.97 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:13 PM PDT 24
Peak memory 215616 kb
Host smart-906fefde-1a3b-4057-afd3-5bb769221759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774126319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3774126319
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2686849783
Short name T386
Test name
Test status
Simulation time 184771164 ps
CPU time 2.31 seconds
Started Jul 05 05:48:09 PM PDT 24
Finished Jul 05 05:48:11 PM PDT 24
Peak memory 215608 kb
Host smart-4c2b15fb-b6e4-45b6-9e17-2a59831bedc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686849783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2686849783
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.239104346
Short name T749
Test name
Test status
Simulation time 80246684685 ps
CPU time 1796.6 seconds
Started Jul 05 05:48:07 PM PDT 24
Finished Jul 05 06:18:05 PM PDT 24
Peak memory 226260 kb
Host smart-42c48d8f-b381-423c-8183-d73909c0d2e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239104346 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.239104346
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3821667908
Short name T573
Test name
Test status
Simulation time 70135377 ps
CPU time 1.13 seconds
Started Jul 05 05:49:53 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 218844 kb
Host smart-dfcc7faa-7529-45d4-8aae-ca3c876231dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821667908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3821667908
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.2213179594
Short name T168
Test name
Test status
Simulation time 21902909 ps
CPU time 1.21 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 219196 kb
Host smart-d66d582b-ca51-446b-9866-30b9863965de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213179594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2213179594
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.75812851
Short name T931
Test name
Test status
Simulation time 40615459 ps
CPU time 1.5 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 218676 kb
Host smart-86af9fb2-e7c2-4ec4-8d70-9c3b979835e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75812851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.75812851
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.4034286101
Short name T132
Test name
Test status
Simulation time 85220992 ps
CPU time 1.1 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 218932 kb
Host smart-8d4052b4-51ef-41a0-bdc4-c8aec78e25a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034286101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.4034286101
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.2122547441
Short name T645
Test name
Test status
Simulation time 23490182 ps
CPU time 1.16 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 220052 kb
Host smart-a381c4e1-d3c3-4bfb-a684-94aa3c307050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122547441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2122547441
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3582182250
Short name T799
Test name
Test status
Simulation time 49952045 ps
CPU time 1.3 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 219452 kb
Host smart-7b811689-0f39-4c06-953d-2b8b3e9d1696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582182250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3582182250
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3532894218
Short name T583
Test name
Test status
Simulation time 51512116 ps
CPU time 1.01 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:47 PM PDT 24
Peak memory 217764 kb
Host smart-b2a4a0e3-a540-4d74-a074-6059e38beda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532894218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3532894218
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1883342465
Short name T232
Test name
Test status
Simulation time 52318868 ps
CPU time 1.25 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 220496 kb
Host smart-d92865be-951a-48aa-8f0f-891578ec13da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883342465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1883342465
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3787102802
Short name T836
Test name
Test status
Simulation time 37175941 ps
CPU time 1.49 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 217712 kb
Host smart-1fd709d9-8a04-4617-b791-feff057febe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787102802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3787102802
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2539465815
Short name T82
Test name
Test status
Simulation time 107340126 ps
CPU time 1.14 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 219936 kb
Host smart-c3b17cc7-11c6-4c04-a075-27ebfded67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539465815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2539465815
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3373499435
Short name T511
Test name
Test status
Simulation time 67136464 ps
CPU time 1.07 seconds
Started Jul 05 05:49:47 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 217720 kb
Host smart-752a7fcd-ac4a-4661-a5af-bff0f227d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373499435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3373499435
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1614152886
Short name T233
Test name
Test status
Simulation time 29635146 ps
CPU time 1.47 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 219744 kb
Host smart-daa20070-4889-4c2f-a1c1-c58d0eac44f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614152886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1614152886
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.333399973
Short name T600
Test name
Test status
Simulation time 113349230 ps
CPU time 1.29 seconds
Started Jul 05 05:49:47 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 219244 kb
Host smart-b31e3242-0f1a-4180-ad3d-44beebb01cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333399973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.333399973
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.295445565
Short name T145
Test name
Test status
Simulation time 49051341 ps
CPU time 1.32 seconds
Started Jul 05 05:49:57 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 220132 kb
Host smart-90bea836-b366-4326-9671-72463b2ad784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295445565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.295445565
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.352181356
Short name T796
Test name
Test status
Simulation time 52494679 ps
CPU time 1.18 seconds
Started Jul 05 05:50:09 PM PDT 24
Finished Jul 05 05:50:11 PM PDT 24
Peak memory 219928 kb
Host smart-217e22f2-432c-4fb8-b8b2-39f9d21b9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352181356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.352181356
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4052774806
Short name T538
Test name
Test status
Simulation time 103924951 ps
CPU time 1.18 seconds
Started Jul 05 05:49:53 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 220784 kb
Host smart-9ce15fe2-54ce-4418-802c-20838a990fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052774806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4052774806
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.4183570238
Short name T427
Test name
Test status
Simulation time 143361997 ps
CPU time 3.29 seconds
Started Jul 05 05:49:59 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 220556 kb
Host smart-20dddf97-978a-4d3e-8307-a6b8ba880bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183570238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4183570238
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3393294845
Short name T623
Test name
Test status
Simulation time 53082575 ps
CPU time 1.26 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 219008 kb
Host smart-22986f64-7cc4-49a2-949d-df4a739ab871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393294845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3393294845
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.719572191
Short name T715
Test name
Test status
Simulation time 65760773 ps
CPU time 1 seconds
Started Jul 05 05:48:19 PM PDT 24
Finished Jul 05 05:48:21 PM PDT 24
Peak memory 207112 kb
Host smart-76616bfa-31a8-4c69-ad73-485b4fc541c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719572191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.719572191
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3445018134
Short name T147
Test name
Test status
Simulation time 19192990 ps
CPU time 0.88 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:48:19 PM PDT 24
Peak memory 215724 kb
Host smart-302e0718-918b-4b4f-b01a-dbcbbd7a47a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445018134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3445018134
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1918400052
Short name T521
Test name
Test status
Simulation time 24294323 ps
CPU time 1.06 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:17 PM PDT 24
Peak memory 224288 kb
Host smart-fb58ae25-2f90-4f42-915c-99245e2bcc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918400052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1918400052
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2437898478
Short name T706
Test name
Test status
Simulation time 53026077 ps
CPU time 1.38 seconds
Started Jul 05 05:48:12 PM PDT 24
Finished Jul 05 05:48:14 PM PDT 24
Peak memory 217660 kb
Host smart-80972e67-528c-492d-9239-1b491e5bbf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437898478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2437898478
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.990102399
Short name T455
Test name
Test status
Simulation time 28003017 ps
CPU time 0.86 seconds
Started Jul 05 05:48:18 PM PDT 24
Finished Jul 05 05:48:19 PM PDT 24
Peak memory 215932 kb
Host smart-9b9c44dd-07a0-4d08-8c77-5c6dfa3bcb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990102399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.990102399
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3649733528
Short name T397
Test name
Test status
Simulation time 16493087 ps
CPU time 0.97 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 215604 kb
Host smart-6cb5f693-5561-4fc8-b62f-276ba199b3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649733528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3649733528
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.385337591
Short name T955
Test name
Test status
Simulation time 1077407946 ps
CPU time 5.11 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:48:23 PM PDT 24
Peak memory 215612 kb
Host smart-4e9e889e-a4ad-407c-bdda-bb44d650bd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385337591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.385337591
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2445866870
Short name T448
Test name
Test status
Simulation time 137409274911 ps
CPU time 529.56 seconds
Started Jul 05 05:48:18 PM PDT 24
Finished Jul 05 05:57:08 PM PDT 24
Peak memory 224060 kb
Host smart-be745944-99bf-4c01-b46b-7ad5ff2bcb55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445866870 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2445866870
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.933935744
Short name T207
Test name
Test status
Simulation time 25969977 ps
CPU time 1.38 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 219212 kb
Host smart-3ca4821e-0845-4922-9ff6-a33e9f98652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933935744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.933935744
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2282713019
Short name T378
Test name
Test status
Simulation time 62166360 ps
CPU time 1.08 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 217576 kb
Host smart-032d0206-897d-45b6-91a0-b231b01458db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282713019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2282713019
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2882313497
Short name T159
Test name
Test status
Simulation time 34595356 ps
CPU time 1.15 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 219056 kb
Host smart-173264ba-2b7f-44a7-96c4-f95edcb64ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882313497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2882313497
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1325147688
Short name T886
Test name
Test status
Simulation time 122579135 ps
CPU time 1.35 seconds
Started Jul 05 05:49:52 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 217936 kb
Host smart-51d98a59-9cbf-4ff5-b884-6ff6b7a7a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325147688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1325147688
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1162400115
Short name T760
Test name
Test status
Simulation time 25619000 ps
CPU time 1.21 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 218928 kb
Host smart-4579abbe-3b95-4bfd-b5cc-43eb04af2568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162400115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1162400115
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3063805679
Short name T402
Test name
Test status
Simulation time 50165286 ps
CPU time 1.56 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 215712 kb
Host smart-1441306d-7069-4ddc-923d-da9f3f5209e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063805679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3063805679
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1719314116
Short name T61
Test name
Test status
Simulation time 38888522 ps
CPU time 1.34 seconds
Started Jul 05 05:49:55 PM PDT 24
Finished Jul 05 05:49:57 PM PDT 24
Peak memory 215968 kb
Host smart-76b1b006-93be-4a81-8600-9922c55d5fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719314116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1719314116
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3768710827
Short name T529
Test name
Test status
Simulation time 31291614 ps
CPU time 1.18 seconds
Started Jul 05 05:49:55 PM PDT 24
Finished Jul 05 05:49:57 PM PDT 24
Peak memory 220144 kb
Host smart-cd21f5bd-ec72-4e0d-ba81-52a80e334191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768710827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3768710827
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3119980180
Short name T639
Test name
Test status
Simulation time 32988317 ps
CPU time 1.06 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 218744 kb
Host smart-a5f7ac02-4ca4-4274-9bb8-900e8af0a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119980180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3119980180
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2224732273
Short name T381
Test name
Test status
Simulation time 83861001 ps
CPU time 1.52 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 219240 kb
Host smart-790139d8-1ea7-4947-a783-751a79ce6894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224732273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2224732273
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2539816714
Short name T461
Test name
Test status
Simulation time 24552733 ps
CPU time 1.15 seconds
Started Jul 05 05:49:57 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 219032 kb
Host smart-86bc1b85-d77c-4b9f-ae76-f148b641040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539816714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2539816714
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.386377869
Short name T901
Test name
Test status
Simulation time 49715689 ps
CPU time 1.27 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 219004 kb
Host smart-91082638-a344-42d0-8e56-fa12bc4a6f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386377869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.386377869
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.97116115
Short name T688
Test name
Test status
Simulation time 57700459 ps
CPU time 1.33 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 218812 kb
Host smart-fbffa7d4-f77e-4115-8b61-b519bf8d1cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97116115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.97116115
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1249236461
Short name T632
Test name
Test status
Simulation time 44260087 ps
CPU time 1.27 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 217664 kb
Host smart-a30283c2-79d8-4a2f-a285-879a7e6ba11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249236461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1249236461
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3908414941
Short name T535
Test name
Test status
Simulation time 30116355 ps
CPU time 1.56 seconds
Started Jul 05 05:49:55 PM PDT 24
Finished Jul 05 05:49:57 PM PDT 24
Peak memory 219128 kb
Host smart-a6d5a877-c424-4644-ac4c-160b6552b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908414941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3908414941
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3357059049
Short name T443
Test name
Test status
Simulation time 25168540 ps
CPU time 1.25 seconds
Started Jul 05 05:49:59 PM PDT 24
Finished Jul 05 05:50:01 PM PDT 24
Peak memory 220028 kb
Host smart-4ab4f7f3-ee68-4598-9a51-1856f382bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357059049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3357059049
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2504610177
Short name T926
Test name
Test status
Simulation time 66052290 ps
CPU time 1.34 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 218936 kb
Host smart-f4ccc06f-da5d-4c2d-bf41-f0578342f6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504610177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2504610177
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2670602748
Short name T928
Test name
Test status
Simulation time 40214972 ps
CPU time 1.21 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:48:19 PM PDT 24
Peak memory 220168 kb
Host smart-1b791429-61d0-4ffc-af65-81cb15b89592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670602748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2670602748
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3475388193
Short name T433
Test name
Test status
Simulation time 12777282 ps
CPU time 0.86 seconds
Started Jul 05 05:48:19 PM PDT 24
Finished Jul 05 05:48:21 PM PDT 24
Peak memory 207272 kb
Host smart-efb01b37-b737-4437-97e5-409bd7007a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475388193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3475388193
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2960726013
Short name T185
Test name
Test status
Simulation time 15710598 ps
CPU time 0.91 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 216588 kb
Host smart-c35ebe77-3065-490d-a884-c787d537c2ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960726013 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2960726013
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3434947277
Short name T989
Test name
Test status
Simulation time 34264079 ps
CPU time 1.33 seconds
Started Jul 05 05:48:15 PM PDT 24
Finished Jul 05 05:48:17 PM PDT 24
Peak memory 217220 kb
Host smart-80aba67e-1be3-48dc-a04f-a2dca1b179da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434947277 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3434947277
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.750746102
Short name T199
Test name
Test status
Simulation time 24462232 ps
CPU time 1.25 seconds
Started Jul 05 05:48:18 PM PDT 24
Finished Jul 05 05:48:20 PM PDT 24
Peak memory 220236 kb
Host smart-5b627f6b-e80f-40b9-a1fc-32d62d55d14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750746102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.750746102
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3502183407
Short name T463
Test name
Test status
Simulation time 128932176 ps
CPU time 1.46 seconds
Started Jul 05 05:48:20 PM PDT 24
Finished Jul 05 05:48:22 PM PDT 24
Peak memory 219232 kb
Host smart-c6219f5f-0368-4b1c-8e2c-00325ab724c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502183407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3502183407
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.387104295
Short name T176
Test name
Test status
Simulation time 22177378 ps
CPU time 0.96 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 216088 kb
Host smart-63fb4d39-29d6-4efc-932e-15e2b26ef33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387104295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.387104295
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1884365907
Short name T371
Test name
Test status
Simulation time 45765983 ps
CPU time 0.9 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:17 PM PDT 24
Peak memory 215504 kb
Host smart-b5c17611-a700-47d5-ac81-86d75e2121b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884365907 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1884365907
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1204241785
Short name T299
Test name
Test status
Simulation time 447437273 ps
CPU time 2.13 seconds
Started Jul 05 05:48:15 PM PDT 24
Finished Jul 05 05:48:18 PM PDT 24
Peak memory 217608 kb
Host smart-6afe7d40-09d3-4e6f-b90d-bd03f62204d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204241785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1204241785
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3893368770
Short name T216
Test name
Test status
Simulation time 54858663565 ps
CPU time 290.79 seconds
Started Jul 05 05:48:17 PM PDT 24
Finished Jul 05 05:53:09 PM PDT 24
Peak memory 224152 kb
Host smart-051c2967-fbdf-4325-af18-6d968193fb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893368770 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3893368770
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.293651553
Short name T108
Test name
Test status
Simulation time 124060636 ps
CPU time 1.33 seconds
Started Jul 05 05:50:01 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 218996 kb
Host smart-e907f64f-4f88-410b-82d5-5b000a4e4ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293651553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.293651553
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.3007117914
Short name T685
Test name
Test status
Simulation time 28129934 ps
CPU time 1.31 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220176 kb
Host smart-b4ad5f29-7d42-4b9e-a044-dbc81b349633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007117914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3007117914
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1258879606
Short name T351
Test name
Test status
Simulation time 50695904 ps
CPU time 1.22 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 219008 kb
Host smart-b0073f9d-8e94-4787-9871-df976aa73973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258879606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1258879606
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3429667361
Short name T121
Test name
Test status
Simulation time 75743305 ps
CPU time 1.16 seconds
Started Jul 05 05:50:09 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 218908 kb
Host smart-d9fbd63e-ebff-4443-91be-d621a1b0c072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429667361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3429667361
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3311607725
Short name T579
Test name
Test status
Simulation time 321591801 ps
CPU time 2.24 seconds
Started Jul 05 05:49:59 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 219152 kb
Host smart-5084ff50-3104-4a7a-864a-378d3cd89ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311607725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3311607725
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2664994684
Short name T745
Test name
Test status
Simulation time 25263182 ps
CPU time 1.21 seconds
Started Jul 05 05:49:57 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 219876 kb
Host smart-3fd48946-8d7c-491c-bec6-9dc6889c90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664994684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2664994684
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.3155100451
Short name T779
Test name
Test status
Simulation time 34991828 ps
CPU time 1.12 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220056 kb
Host smart-30262ce4-acb5-4098-9f5a-b88c60fe1353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155100451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3155100451
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3244948242
Short name T744
Test name
Test status
Simulation time 54290138 ps
CPU time 2.07 seconds
Started Jul 05 05:49:52 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 219884 kb
Host smart-40d3fa76-19c2-41a2-8cac-84cf0035031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244948242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3244948242
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1327139480
Short name T637
Test name
Test status
Simulation time 47629704 ps
CPU time 1.26 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 220100 kb
Host smart-587890ab-9f28-4cfe-b263-f075c131faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327139480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1327139480
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.801699588
Short name T721
Test name
Test status
Simulation time 69011377 ps
CPU time 1.12 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 217748 kb
Host smart-b07303c9-3c35-4d94-8c2e-07b814fda73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801699588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.801699588
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2119084859
Short name T349
Test name
Test status
Simulation time 89366938 ps
CPU time 1.06 seconds
Started Jul 05 05:49:55 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 219988 kb
Host smart-4aaad794-0baf-4e9b-9f25-2979f2128ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119084859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2119084859
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2301581341
Short name T421
Test name
Test status
Simulation time 100711769 ps
CPU time 1.22 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 217736 kb
Host smart-4ad64df7-56e8-40c5-aa2e-6d256d83e1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301581341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2301581341
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1611268968
Short name T911
Test name
Test status
Simulation time 112850637 ps
CPU time 1.08 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:57 PM PDT 24
Peak memory 219092 kb
Host smart-81cc10ef-6e08-4254-bc82-105acd4594bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611268968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1611268968
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.932688104
Short name T424
Test name
Test status
Simulation time 51584389 ps
CPU time 1.19 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 217788 kb
Host smart-a35923f0-0f22-475d-b0c2-76fbfa329ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932688104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.932688104
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.976240394
Short name T684
Test name
Test status
Simulation time 36558886 ps
CPU time 1.13 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 220004 kb
Host smart-fbf00a97-0a5e-42d6-9d5d-afd0b283d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976240394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.976240394
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4282412494
Short name T9
Test name
Test status
Simulation time 85665906 ps
CPU time 1.2 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 220276 kb
Host smart-f997f299-0568-4ec1-9c7f-ad6185066d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282412494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4282412494
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.910947683
Short name T897
Test name
Test status
Simulation time 337389366 ps
CPU time 1.1 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 218720 kb
Host smart-a0bc9ec6-0906-4bd0-9ff1-a450a9f21d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910947683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.910947683
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2992578361
Short name T333
Test name
Test status
Simulation time 59837674 ps
CPU time 1.01 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 215208 kb
Host smart-2aa9a2d8-5b2f-495c-8d82-0c15529c4ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992578361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2992578361
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1253063292
Short name T95
Test name
Test status
Simulation time 15743386 ps
CPU time 0.81 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 215688 kb
Host smart-a3fa8650-0501-4c9b-ada3-cb5aed6a3ab4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253063292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1253063292
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2460285074
Short name T150
Test name
Test status
Simulation time 22546528 ps
CPU time 0.99 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:26 PM PDT 24
Peak memory 218856 kb
Host smart-dff8ad60-a95d-46de-9f14-9cfd0a8084cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460285074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2460285074
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3812642235
Short name T323
Test name
Test status
Simulation time 194997276 ps
CPU time 3.26 seconds
Started Jul 05 05:48:16 PM PDT 24
Finished Jul 05 05:48:20 PM PDT 24
Peak memory 220604 kb
Host smart-1262ed25-3110-4fd8-9c32-d2d3d36c959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812642235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3812642235
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1767896179
Short name T994
Test name
Test status
Simulation time 27623796 ps
CPU time 1.09 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 224440 kb
Host smart-711b8ad2-32d1-4d7e-a421-7605d5a16501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767896179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1767896179
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3657402653
Short name T635
Test name
Test status
Simulation time 18393561 ps
CPU time 1.02 seconds
Started Jul 05 05:48:19 PM PDT 24
Finished Jul 05 05:48:21 PM PDT 24
Peak memory 215632 kb
Host smart-d4b6202b-ed71-4686-940f-3bffdc73d3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657402653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3657402653
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.651773347
Short name T369
Test name
Test status
Simulation time 73956864 ps
CPU time 1.21 seconds
Started Jul 05 05:48:20 PM PDT 24
Finished Jul 05 05:48:22 PM PDT 24
Peak memory 215604 kb
Host smart-1479fa40-0079-4913-a4e3-2c5136f6cd59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651773347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.651773347
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4139352013
Short name T880
Test name
Test status
Simulation time 59032592893 ps
CPU time 1450.5 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 06:12:36 PM PDT 24
Peak memory 225484 kb
Host smart-1de79dcd-d8b7-445c-9aeb-ec271467c923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139352013 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4139352013
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2418105674
Short name T590
Test name
Test status
Simulation time 28291626 ps
CPU time 1.21 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 218772 kb
Host smart-72b67dc2-d506-48f8-a6e1-b52345fdd29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418105674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2418105674
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2447622052
Short name T300
Test name
Test status
Simulation time 185802293 ps
CPU time 1.03 seconds
Started Jul 05 05:49:59 PM PDT 24
Finished Jul 05 05:50:01 PM PDT 24
Peak memory 215640 kb
Host smart-adfbd1d2-5cb1-4843-89ed-38f186f8926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447622052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2447622052
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.164269879
Short name T274
Test name
Test status
Simulation time 89398792 ps
CPU time 1.14 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220724 kb
Host smart-89e49977-c24f-4af3-8e7e-a4f8a38041fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164269879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.164269879
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.2479991656
Short name T963
Test name
Test status
Simulation time 79341813 ps
CPU time 1.13 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220608 kb
Host smart-3ad4737c-c5aa-4e25-80f9-81bb358a08c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479991656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2479991656
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3610419235
Short name T456
Test name
Test status
Simulation time 29207488 ps
CPU time 1.29 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 217776 kb
Host smart-673fa7ae-8d6c-424d-8b7c-2a4f50554908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610419235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3610419235
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2293747102
Short name T435
Test name
Test status
Simulation time 314398822 ps
CPU time 1.17 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 218728 kb
Host smart-10828c14-9d33-434f-98e1-027d81a81817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293747102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2293747102
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1572128273
Short name T394
Test name
Test status
Simulation time 62563324 ps
CPU time 1.41 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 218708 kb
Host smart-4ab327df-bb60-4a3d-b649-c571387ec5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572128273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1572128273
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1732817358
Short name T849
Test name
Test status
Simulation time 49720531 ps
CPU time 1.27 seconds
Started Jul 05 05:49:57 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 220540 kb
Host smart-70299211-518e-40ed-bba1-df41c7bd3844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732817358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1732817358
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2127633436
Short name T927
Test name
Test status
Simulation time 52948214 ps
CPU time 1.32 seconds
Started Jul 05 05:50:00 PM PDT 24
Finished Jul 05 05:50:02 PM PDT 24
Peak memory 219420 kb
Host smart-8d0622c3-89f7-4dbb-ab33-905cd1dd7b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127633436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2127633436
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1780459443
Short name T859
Test name
Test status
Simulation time 62812883 ps
CPU time 1.13 seconds
Started Jul 05 05:50:01 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 217656 kb
Host smart-e81db9bd-6335-4b01-a0e8-42878143bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780459443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1780459443
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1348222616
Short name T115
Test name
Test status
Simulation time 24920871 ps
CPU time 1.24 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 220820 kb
Host smart-8bfe5e5c-5aa9-46bb-a433-fa6592dfa57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348222616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1348222616
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3901781984
Short name T674
Test name
Test status
Simulation time 246595028 ps
CPU time 3.34 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 219184 kb
Host smart-18574554-0749-4d16-80ff-e67e3e9f001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901781984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3901781984
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2811706037
Short name T416
Test name
Test status
Simulation time 27295531 ps
CPU time 1.19 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:06 PM PDT 24
Peak memory 218964 kb
Host smart-e20e87b4-a9d4-4c2a-a017-f2320a1296d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811706037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2811706037
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.370207687
Short name T598
Test name
Test status
Simulation time 71344515 ps
CPU time 1.08 seconds
Started Jul 05 05:50:01 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 217724 kb
Host smart-d1946824-9ef3-4204-b201-db5de8b7ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370207687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.370207687
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2527289747
Short name T866
Test name
Test status
Simulation time 340231166 ps
CPU time 1.1 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 216260 kb
Host smart-80f6ed3b-5dbd-4a2d-b3bd-8719e07a21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527289747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2527289747
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1900356355
Short name T457
Test name
Test status
Simulation time 27302325 ps
CPU time 1.37 seconds
Started Jul 05 05:49:58 PM PDT 24
Finished Jul 05 05:50:00 PM PDT 24
Peak memory 218956 kb
Host smart-cb05a63b-2ed4-4ec4-a08d-733c0067567d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900356355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1900356355
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1043082762
Short name T640
Test name
Test status
Simulation time 28232717 ps
CPU time 1.19 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 220156 kb
Host smart-7f6815c7-1383-4f64-a037-23de1ae8f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043082762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1043082762
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.251063608
Short name T537
Test name
Test status
Simulation time 106379037 ps
CPU time 1.19 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 217648 kb
Host smart-8699d1e4-ac20-4621-b69e-1c6c0445653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251063608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.251063608
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3060492978
Short name T585
Test name
Test status
Simulation time 73564661 ps
CPU time 1.21 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 220472 kb
Host smart-7e229fb4-91ef-44b5-9082-a4e59908cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060492978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3060492978
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2612742513
Short name T564
Test name
Test status
Simulation time 16152166 ps
CPU time 0.94 seconds
Started Jul 05 05:48:27 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 215304 kb
Host smart-54d5ed2d-05f7-405e-9610-6c3960e7f967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612742513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2612742513
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2872489477
Short name T65
Test name
Test status
Simulation time 32630722 ps
CPU time 0.85 seconds
Started Jul 05 05:48:22 PM PDT 24
Finished Jul 05 05:48:24 PM PDT 24
Peak memory 216448 kb
Host smart-1c133d43-3cfa-4342-9db8-722d7cd52fe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872489477 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2872489477
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2892601632
Short name T124
Test name
Test status
Simulation time 33136035 ps
CPU time 1.26 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 220036 kb
Host smart-0dea0563-4a07-4898-baa5-2929f46bb48e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892601632 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2892601632
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.1591815689
Short name T850
Test name
Test status
Simulation time 142835867 ps
CPU time 2.17 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 220792 kb
Host smart-64904c66-515a-4a3b-80c6-82d149038437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591815689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1591815689
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2928596127
Short name T591
Test name
Test status
Simulation time 34139590 ps
CPU time 1.04 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 224292 kb
Host smart-20271c6d-189b-4c70-8524-202163645819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928596127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2928596127
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.49643828
Short name T526
Test name
Test status
Simulation time 26964295 ps
CPU time 0.99 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:26 PM PDT 24
Peak memory 215616 kb
Host smart-51ca3139-94a5-4181-af81-805c7d74ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49643828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.49643828
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.730884594
Short name T495
Test name
Test status
Simulation time 92964552 ps
CPU time 1.65 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 215652 kb
Host smart-bf594bce-be1a-4150-8ac4-3da8b871e5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730884594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.730884594
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1208336693
Short name T219
Test name
Test status
Simulation time 145683398345 ps
CPU time 1606.33 seconds
Started Jul 05 05:48:23 PM PDT 24
Finished Jul 05 06:15:10 PM PDT 24
Peak memory 225256 kb
Host smart-f4cbc5c6-a205-4a3f-8f02-e5d901569f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208336693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1208336693
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2109445344
Short name T960
Test name
Test status
Simulation time 42864770 ps
CPU time 1.65 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 220028 kb
Host smart-83dd3131-d5ae-4cf6-a8b4-e1c9335844bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109445344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2109445344
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3718162663
Short name T92
Test name
Test status
Simulation time 49649711 ps
CPU time 1.11 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219084 kb
Host smart-d5927e13-f415-4d97-bdfd-0054f3944e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718162663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3718162663
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.918266918
Short name T769
Test name
Test status
Simulation time 42171405 ps
CPU time 1.12 seconds
Started Jul 05 05:50:01 PM PDT 24
Finished Jul 05 05:50:03 PM PDT 24
Peak memory 217724 kb
Host smart-81142a27-3784-437e-868b-29f06263044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918266918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.918266918
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3790391493
Short name T877
Test name
Test status
Simulation time 43181888 ps
CPU time 1.15 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 218936 kb
Host smart-e2837290-2ef7-4b1a-b5d0-5ec1b8c91609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790391493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3790391493
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.531704634
Short name T621
Test name
Test status
Simulation time 40274661 ps
CPU time 1.12 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 217656 kb
Host smart-b2f3eefd-cafc-4642-aff6-b88886a74ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531704634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.531704634
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2725524577
Short name T655
Test name
Test status
Simulation time 71346506 ps
CPU time 1.17 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 219324 kb
Host smart-ef863da3-6a30-4ab4-9ba1-722773bdb311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725524577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2725524577
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.348647697
Short name T596
Test name
Test status
Simulation time 86478012 ps
CPU time 1.26 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 216012 kb
Host smart-dfa3a1e7-2463-4bd4-9290-941bfbf7b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348647697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.348647697
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2980256986
Short name T666
Test name
Test status
Simulation time 107296990 ps
CPU time 1.28 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 219172 kb
Host smart-e52e151e-5bbd-4967-abc7-40417d387a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980256986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2980256986
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3987599401
Short name T513
Test name
Test status
Simulation time 33010159 ps
CPU time 1.25 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 218884 kb
Host smart-f7315f85-ac20-42ee-b1c5-128eeb5770fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987599401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3987599401
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2358063204
Short name T675
Test name
Test status
Simulation time 48403532 ps
CPU time 1.28 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 217688 kb
Host smart-979a6b14-f7c3-40a5-b5fd-81080222daaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358063204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2358063204
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.766921818
Short name T131
Test name
Test status
Simulation time 76499778 ps
CPU time 1.18 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 221128 kb
Host smart-f55dd1ec-b81f-4628-9492-76180e6402b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766921818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.766921818
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2270518478
Short name T920
Test name
Test status
Simulation time 20978916 ps
CPU time 1.14 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 217564 kb
Host smart-ebc3a18b-c2e7-4d7c-a59e-ccf4b7a07f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270518478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2270518478
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1841688780
Short name T654
Test name
Test status
Simulation time 86382207 ps
CPU time 1.18 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 220116 kb
Host smart-9b9116df-9f95-4f40-9365-c0dd5d24f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841688780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1841688780
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2355468771
Short name T704
Test name
Test status
Simulation time 51944395 ps
CPU time 1.32 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 218856 kb
Host smart-31d4f0dc-21d3-422b-bbbf-b6e343ff4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355468771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2355468771
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1720311772
Short name T23
Test name
Test status
Simulation time 64863476 ps
CPU time 1.34 seconds
Started Jul 05 05:50:08 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 219484 kb
Host smart-66fed7a7-e96a-45f5-9ced-79a6a04e936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720311772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1720311772
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.714728682
Short name T661
Test name
Test status
Simulation time 48355348 ps
CPU time 1.3 seconds
Started Jul 05 05:50:06 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 219424 kb
Host smart-aabb76dd-61ac-460f-9a96-98a4863ef6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714728682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.714728682
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3030510669
Short name T727
Test name
Test status
Simulation time 34148809 ps
CPU time 1.35 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 217532 kb
Host smart-ddaff9e9-e127-4c67-8305-216da56c3f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030510669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3030510669
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3834570297
Short name T546
Test name
Test status
Simulation time 74614862 ps
CPU time 1.18 seconds
Started Jul 05 05:48:28 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 219940 kb
Host smart-461852d9-c2f4-4e06-9279-f2f9151c40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834570297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3834570297
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2285798263
Short name T864
Test name
Test status
Simulation time 15830859 ps
CPU time 0.97 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 207028 kb
Host smart-31926b5e-6371-4a04-89d1-60f1a6624d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285798263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2285798263
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.1039259252
Short name T12
Test name
Test status
Simulation time 22421162 ps
CPU time 1.06 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 224064 kb
Host smart-f6d12384-d3bf-4fbc-a944-bd33920e349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039259252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1039259252
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.864914660
Short name T924
Test name
Test status
Simulation time 21481179 ps
CPU time 1.2 seconds
Started Jul 05 05:48:21 PM PDT 24
Finished Jul 05 05:48:23 PM PDT 24
Peak memory 224340 kb
Host smart-c4740af0-936c-46f1-9d7e-d1ccf5d6b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864914660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.864914660
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.269866269
Short name T871
Test name
Test status
Simulation time 17703446 ps
CPU time 1.08 seconds
Started Jul 05 05:48:22 PM PDT 24
Finished Jul 05 05:48:24 PM PDT 24
Peak memory 215620 kb
Host smart-69eb9d11-1248-48e7-ad50-6c23ff37c570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269866269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.269866269
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2457525858
Short name T980
Test name
Test status
Simulation time 508261794 ps
CPU time 5.69 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 217516 kb
Host smart-a106edf4-4e81-47bf-8483-dcb4cfa1f691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457525858 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2457525858
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.291930627
Short name T255
Test name
Test status
Simulation time 39868834 ps
CPU time 1.22 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 219096 kb
Host smart-6322fce4-b2d3-4c86-98f5-7b6381cca5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291930627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.291930627
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.1259822412
Short name T713
Test name
Test status
Simulation time 86468282 ps
CPU time 1.12 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 220008 kb
Host smart-1718eaf0-c285-4ec4-b378-185b4886e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259822412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1259822412
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.750713380
Short name T660
Test name
Test status
Simulation time 172533934 ps
CPU time 1.24 seconds
Started Jul 05 05:50:07 PM PDT 24
Finished Jul 05 05:50:09 PM PDT 24
Peak memory 217844 kb
Host smart-0c1d2244-62b9-4648-b8bd-01c5a2753db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750713380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.750713380
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1083811440
Short name T775
Test name
Test status
Simulation time 48054703 ps
CPU time 1.13 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 218860 kb
Host smart-c89acada-5789-4263-8b2f-f3ef8753d221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083811440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1083811440
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4126130123
Short name T459
Test name
Test status
Simulation time 44559846 ps
CPU time 1.56 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:06 PM PDT 24
Peak memory 220264 kb
Host smart-9fe7e9e8-e9f1-42e6-a12b-ef1ac8b44f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126130123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4126130123
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.4174793599
Short name T746
Test name
Test status
Simulation time 30033412 ps
CPU time 1.32 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 220892 kb
Host smart-bfebc8f3-185f-4321-bff1-e516c5f29efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174793599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.4174793599
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3821909907
Short name T382
Test name
Test status
Simulation time 104196603 ps
CPU time 1.32 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 218780 kb
Host smart-39f7cf8e-9e13-45c6-adf4-7633e5856285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821909907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3821909907
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3243694907
Short name T454
Test name
Test status
Simulation time 29143177 ps
CPU time 1.29 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 216016 kb
Host smart-514d0025-a912-4dbf-a044-0f2fcc1cff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243694907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3243694907
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1053219975
Short name T968
Test name
Test status
Simulation time 12169087119 ps
CPU time 147.11 seconds
Started Jul 05 05:50:06 PM PDT 24
Finished Jul 05 05:52:34 PM PDT 24
Peak memory 220904 kb
Host smart-aa48902b-62a5-42a8-b191-1b065e7fe153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053219975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1053219975
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4004999028
Short name T278
Test name
Test status
Simulation time 355569733 ps
CPU time 1.38 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 220016 kb
Host smart-027229e3-ac91-4f05-96fa-ca240d0a45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004999028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4004999028
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1664325578
Short name T870
Test name
Test status
Simulation time 115921101 ps
CPU time 1.19 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 217576 kb
Host smart-336e8b1c-364f-40d6-ba80-acac44e38313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664325578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1664325578
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1109444025
Short name T127
Test name
Test status
Simulation time 26385706 ps
CPU time 1.27 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219936 kb
Host smart-ce917b8a-6e68-4b30-9f70-94eacd2cc8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109444025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1109444025
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2254920053
Short name T668
Test name
Test status
Simulation time 89552590 ps
CPU time 3.08 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 217884 kb
Host smart-3c7bb2dc-c65e-40db-a290-62e390f20882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254920053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2254920053
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1193638180
Short name T884
Test name
Test status
Simulation time 29614213 ps
CPU time 1.23 seconds
Started Jul 05 05:50:02 PM PDT 24
Finished Jul 05 05:50:04 PM PDT 24
Peak memory 218964 kb
Host smart-bd60710d-644d-4b85-9213-f0f77f17f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193638180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1193638180
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2916371452
Short name T318
Test name
Test status
Simulation time 62978915 ps
CPU time 1.55 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 219020 kb
Host smart-4801ec8f-4796-4776-b86b-a676d9623a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916371452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2916371452
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.951713465
Short name T557
Test name
Test status
Simulation time 87140992 ps
CPU time 1.34 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 221052 kb
Host smart-ee64a91c-026f-493e-80c0-5a9944fd9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951713465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.951713465
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.4031282570
Short name T873
Test name
Test status
Simulation time 212837688 ps
CPU time 1.5 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 219096 kb
Host smart-84d7d6dd-08da-4bdc-95f9-51f8a341ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031282570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.4031282570
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2945278676
Short name T967
Test name
Test status
Simulation time 343750488 ps
CPU time 1.26 seconds
Started Jul 05 05:50:07 PM PDT 24
Finished Jul 05 05:50:09 PM PDT 24
Peak memory 219664 kb
Host smart-47207ae4-22a7-4ee1-8c92-7084419b47c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945278676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2945278676
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1293005980
Short name T322
Test name
Test status
Simulation time 34420247 ps
CPU time 1.35 seconds
Started Jul 05 05:50:06 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 219820 kb
Host smart-de946fc1-b8de-44a1-9eae-cbee9b474a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293005980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1293005980
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3662555127
Short name T439
Test name
Test status
Simulation time 48758454 ps
CPU time 1.16 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 220124 kb
Host smart-343337a7-07fe-44ea-a531-d7e83e3d745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662555127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3662555127
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1223507234
Short name T602
Test name
Test status
Simulation time 31109896 ps
CPU time 0.97 seconds
Started Jul 05 05:48:23 PM PDT 24
Finished Jul 05 05:48:24 PM PDT 24
Peak memory 207008 kb
Host smart-d3104f20-4cbd-4c11-afc6-c89ec5fa8d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223507234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1223507234
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1610913545
Short name T764
Test name
Test status
Simulation time 88717632 ps
CPU time 1.2 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 217256 kb
Host smart-f7f91944-3538-458e-adc1-d2fca793d0ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610913545 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1610913545
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3159622674
Short name T527
Test name
Test status
Simulation time 24418898 ps
CPU time 1.18 seconds
Started Jul 05 05:48:26 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 218828 kb
Host smart-be020f57-1d81-4004-ad81-baae2482249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159622674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3159622674
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.886699010
Short name T422
Test name
Test status
Simulation time 41740343 ps
CPU time 1.28 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 217744 kb
Host smart-ecbd5672-877d-4a49-a6b0-209804e895c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886699010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.886699010
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.176499060
Short name T566
Test name
Test status
Simulation time 34185451 ps
CPU time 0.91 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 215660 kb
Host smart-5db1eeaa-0292-4617-af5b-8a993edbb2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176499060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.176499060
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3046568995
Short name T553
Test name
Test status
Simulation time 710341663 ps
CPU time 3.53 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 217504 kb
Host smart-2e0efa83-f8bf-431c-b941-7f846fefb575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046568995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3046568995
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3734639831
Short name T951
Test name
Test status
Simulation time 98779683931 ps
CPU time 985.06 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 06:04:52 PM PDT 24
Peak memory 222620 kb
Host smart-c473ff06-4a68-4be0-9123-d5acda6270de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734639831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3734639831
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3795308903
Short name T276
Test name
Test status
Simulation time 51891693 ps
CPU time 1.27 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:06 PM PDT 24
Peak memory 219208 kb
Host smart-af40f420-ac3b-483a-8edb-9bf60108792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795308903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3795308903
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1713966187
Short name T458
Test name
Test status
Simulation time 44457044 ps
CPU time 1.26 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 220368 kb
Host smart-a1c87c52-dfac-449e-a3a9-8e64b7f7670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713966187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1713966187
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.614266894
Short name T228
Test name
Test status
Simulation time 86789098 ps
CPU time 1.22 seconds
Started Jul 05 05:50:03 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 219384 kb
Host smart-3ba70156-8b7f-42d9-ba5a-590849871618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614266894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.614266894
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3235990828
Short name T295
Test name
Test status
Simulation time 75323943 ps
CPU time 1.53 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219412 kb
Host smart-9cac9c3c-9206-4309-92a1-e147979d7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235990828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3235990828
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3481964320
Short name T171
Test name
Test status
Simulation time 26953855 ps
CPU time 1.24 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 216012 kb
Host smart-b0daad1c-3d65-4736-bd41-f0a572ef9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481964320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3481964320
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.4006045806
Short name T282
Test name
Test status
Simulation time 50662714 ps
CPU time 1.25 seconds
Started Jul 05 05:50:04 PM PDT 24
Finished Jul 05 05:50:06 PM PDT 24
Peak memory 216004 kb
Host smart-af4eb205-95a6-40cd-9d7d-2f2187a47990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006045806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4006045806
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.517202248
Short name T828
Test name
Test status
Simulation time 84931497 ps
CPU time 1.28 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 219308 kb
Host smart-14c1d582-fd6a-420e-b9a8-a0e683ce6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517202248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.517202248
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2003565526
Short name T811
Test name
Test status
Simulation time 293003829 ps
CPU time 1.39 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 215888 kb
Host smart-88063baa-88fd-40ed-849c-ae8ee066e31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003565526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2003565526
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3332552191
Short name T982
Test name
Test status
Simulation time 39968402 ps
CPU time 1.47 seconds
Started Jul 05 05:50:05 PM PDT 24
Finished Jul 05 05:50:07 PM PDT 24
Peak memory 219460 kb
Host smart-517df015-f86d-4c0b-8e9d-c5f092827d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332552191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3332552191
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2655493317
Short name T810
Test name
Test status
Simulation time 88456693 ps
CPU time 1.17 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 219780 kb
Host smart-4a6e84b4-108d-46b1-aecf-792238263524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655493317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2655493317
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3869509274
Short name T39
Test name
Test status
Simulation time 54856297 ps
CPU time 1.67 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 217640 kb
Host smart-e3f16c8d-f65c-4f76-ae98-075073171d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869509274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3869509274
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1733485408
Short name T29
Test name
Test status
Simulation time 91357896 ps
CPU time 1.21 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 220972 kb
Host smart-7c455df5-a87f-42d3-a4a6-03b0d4ffa0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733485408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1733485408
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2241123706
Short name T364
Test name
Test status
Simulation time 77735977 ps
CPU time 1.19 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 217596 kb
Host smart-10e42279-cd02-4e5d-8db4-4cc621e10d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241123706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2241123706
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2215407612
Short name T842
Test name
Test status
Simulation time 26051435 ps
CPU time 1.25 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219076 kb
Host smart-1967c4d1-e050-4e3f-bd3c-1f8357cddc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215407612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2215407612
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3403448080
Short name T486
Test name
Test status
Simulation time 53446095 ps
CPU time 1.07 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 218836 kb
Host smart-ac0f64ac-03c3-4bb1-993f-dbfcef805a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403448080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3403448080
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.913710928
Short name T109
Test name
Test status
Simulation time 29623999 ps
CPU time 1.28 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 219700 kb
Host smart-c6c30525-cfa8-45b9-9c09-af8d2bb14a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913710928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.913710928
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3691763005
Short name T918
Test name
Test status
Simulation time 58732107 ps
CPU time 1.52 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 218736 kb
Host smart-d8e7c83a-61a7-4432-a1f1-dfe92370eded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691763005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3691763005
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1883512953
Short name T735
Test name
Test status
Simulation time 24408814 ps
CPU time 1.15 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 219948 kb
Host smart-65b3b2ee-d901-4f9c-8b43-3468d9bce0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883512953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1883512953
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3920429929
Short name T652
Test name
Test status
Simulation time 40068426 ps
CPU time 1.43 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:16 PM PDT 24
Peak memory 218860 kb
Host smart-897b7a9e-89c4-4d28-9dca-905a20157674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920429929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3920429929
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3548171949
Short name T180
Test name
Test status
Simulation time 47281438 ps
CPU time 0.98 seconds
Started Jul 05 05:48:22 PM PDT 24
Finished Jul 05 05:48:23 PM PDT 24
Peak memory 207032 kb
Host smart-4d0567ce-9498-4793-841b-66bcdb408b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548171949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3548171949
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2423702865
Short name T413
Test name
Test status
Simulation time 35852610 ps
CPU time 0.89 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 216280 kb
Host smart-41375c91-28ce-419b-8cb7-597b9d113f84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423702865 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2423702865
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.3481586208
Short name T753
Test name
Test status
Simulation time 24255428 ps
CPU time 1.11 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 218824 kb
Host smart-2ac52611-1818-447e-8565-d1de97840f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481586208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3481586208
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3387486826
Short name T506
Test name
Test status
Simulation time 49629259 ps
CPU time 1.35 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 217636 kb
Host smart-4238dd32-1e2b-4d55-ba4e-53b1a2ffa95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387486826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3387486826
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1888460878
Short name T57
Test name
Test status
Simulation time 24836175 ps
CPU time 1.1 seconds
Started Jul 05 05:48:25 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 224360 kb
Host smart-db4493c9-48d6-49f5-827a-295a1caf5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888460878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1888460878
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.120137470
Short name T605
Test name
Test status
Simulation time 145543684 ps
CPU time 0.91 seconds
Started Jul 05 05:48:23 PM PDT 24
Finished Jul 05 05:48:25 PM PDT 24
Peak memory 215528 kb
Host smart-c8f4b55f-4c6a-4a5c-9752-155198a78706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120137470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.120137470
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1708422962
Short name T417
Test name
Test status
Simulation time 105158287 ps
CPU time 1.67 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 218832 kb
Host smart-e6924ca3-4c9f-4e59-9528-116a1da8d30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708422962 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1708422962
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3664088729
Short name T379
Test name
Test status
Simulation time 115219731998 ps
CPU time 2351.94 seconds
Started Jul 05 05:48:24 PM PDT 24
Finished Jul 05 06:27:38 PM PDT 24
Peak memory 237672 kb
Host smart-f8aa265b-0f7e-4e48-bb26-56b5bb394b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664088729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3664088729
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4199941856
Short name T307
Test name
Test status
Simulation time 143274472 ps
CPU time 1.34 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 219212 kb
Host smart-5e45bfb6-77fa-49f4-b12d-698eba814085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199941856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4199941856
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1529297259
Short name T919
Test name
Test status
Simulation time 85315370 ps
CPU time 1.18 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219448 kb
Host smart-4ff7c4ae-cb69-478f-84d9-1ea0e87ab587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529297259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1529297259
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2226636057
Short name T882
Test name
Test status
Simulation time 94255504 ps
CPU time 1.38 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 219040 kb
Host smart-be21a753-917f-4c32-9a57-f2ba160c7582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226636057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2226636057
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.861675457
Short name T653
Test name
Test status
Simulation time 23009094 ps
CPU time 1.22 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 219856 kb
Host smart-900881ae-6331-44c6-909d-7477c15d0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861675457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.861675457
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3307059258
Short name T626
Test name
Test status
Simulation time 88667146 ps
CPU time 1.18 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219196 kb
Host smart-19dcda1e-4e32-42fc-996f-56c78a6acfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307059258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3307059258
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.781028369
Short name T616
Test name
Test status
Simulation time 40391627 ps
CPU time 1.13 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 218876 kb
Host smart-0c0551af-65e0-4de6-a518-3bf48840a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781028369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.781028369
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2066311044
Short name T536
Test name
Test status
Simulation time 67032983 ps
CPU time 1.35 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 217488 kb
Host smart-9ebcb47c-0a56-47ab-bdcd-7a1283271762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066311044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2066311044
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2475626218
Short name T692
Test name
Test status
Simulation time 36816083 ps
CPU time 1.09 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 218904 kb
Host smart-2a3d5c89-9152-4035-a02b-ddeb48e53ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475626218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2475626218
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1898004492
Short name T903
Test name
Test status
Simulation time 53381686 ps
CPU time 1.19 seconds
Started Jul 05 05:50:06 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 218808 kb
Host smart-bcd06494-2bdb-46f4-a95c-cc9d7130a05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898004492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1898004492
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.606096199
Short name T617
Test name
Test status
Simulation time 207475214 ps
CPU time 1.34 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 217660 kb
Host smart-069d135f-7f44-4156-8c9d-bb87b44e932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606096199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.606096199
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.787340176
Short name T283
Test name
Test status
Simulation time 111487906 ps
CPU time 1.1 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 219104 kb
Host smart-afad65b6-c20b-4c8c-a5a2-e757a27fce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787340176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.787340176
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.242297375
Short name T410
Test name
Test status
Simulation time 67571102 ps
CPU time 1.46 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 219000 kb
Host smart-702cf458-1833-46c7-8709-dba0cdb75074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242297375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.242297375
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1931161695
Short name T754
Test name
Test status
Simulation time 28431142 ps
CPU time 1.29 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 220276 kb
Host smart-8b0b022b-e612-497f-b08c-e8a0d2642d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931161695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1931161695
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2983214426
Short name T558
Test name
Test status
Simulation time 52158330 ps
CPU time 1.62 seconds
Started Jul 05 05:50:07 PM PDT 24
Finished Jul 05 05:50:09 PM PDT 24
Peak memory 218952 kb
Host smart-c82b70bb-0786-4dba-bb32-72eab673fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983214426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2983214426
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3864479022
Short name T624
Test name
Test status
Simulation time 49363159 ps
CPU time 1.31 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 220048 kb
Host smart-64637f96-9701-4242-a57e-f1a138b5d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864479022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3864479022
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1753635238
Short name T407
Test name
Test status
Simulation time 54684877 ps
CPU time 1.3 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 218416 kb
Host smart-2b1e043c-4e7b-4d7d-8975-b473ff5ea487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753635238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1753635238
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3632398679
Short name T125
Test name
Test status
Simulation time 24691423 ps
CPU time 1.23 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:16 PM PDT 24
Peak memory 218700 kb
Host smart-f2845cb1-e73e-491e-943e-b8ec1806473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632398679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3632398679
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1043408623
Short name T314
Test name
Test status
Simulation time 36812972 ps
CPU time 1.34 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:12 PM PDT 24
Peak memory 220128 kb
Host smart-427ef9f1-93e0-43af-8c43-edfc6d20a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043408623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1043408623
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.97045338
Short name T144
Test name
Test status
Simulation time 39625582 ps
CPU time 1.35 seconds
Started Jul 05 05:48:35 PM PDT 24
Finished Jul 05 05:48:37 PM PDT 24
Peak memory 216004 kb
Host smart-5b454688-9710-4bcd-ba3a-c1bb3cef1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97045338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.97045338
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1022558781
Short name T950
Test name
Test status
Simulation time 16281073 ps
CPU time 0.92 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 207056 kb
Host smart-d5a3263b-1c57-47af-92ef-04e9982a2139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022558781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1022558781
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.921236520
Short name T3
Test name
Test status
Simulation time 52624376 ps
CPU time 1.03 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 220256 kb
Host smart-6d5c68e8-1c9e-43c2-bd8b-10e0c3208524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921236520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.921236520
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.3337500699
Short name T974
Test name
Test status
Simulation time 21453836 ps
CPU time 1.1 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 215752 kb
Host smart-bcaa365f-fdfe-4eb1-8412-02b667f4d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337500699 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3337500699
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2936511767
Short name T387
Test name
Test status
Simulation time 20006045 ps
CPU time 1.01 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 215652 kb
Host smart-ac2fa55a-b255-408a-9c5f-d569b94b1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936511767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2936511767
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/180.edn_alert.725616043
Short name T716
Test name
Test status
Simulation time 23095638 ps
CPU time 1.18 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 220348 kb
Host smart-c40b43f4-3db9-4fb3-b0f3-0d7a4499857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725616043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.725616043
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.244405888
Short name T817
Test name
Test status
Simulation time 64160582 ps
CPU time 1.7 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 218928 kb
Host smart-96b0c95b-e992-4971-909b-d7794462070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244405888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.244405888
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1611024373
Short name T231
Test name
Test status
Simulation time 84575230 ps
CPU time 1.26 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 218888 kb
Host smart-7b41c7af-6ea0-4ad9-b516-b57dba26fafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611024373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1611024373
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.47723079
Short name T510
Test name
Test status
Simulation time 46666365 ps
CPU time 1.27 seconds
Started Jul 05 05:50:09 PM PDT 24
Finished Jul 05 05:50:11 PM PDT 24
Peak memory 220192 kb
Host smart-c183330a-e1f4-4888-8de0-cad5f285c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47723079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.47723079
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1329270246
Short name T969
Test name
Test status
Simulation time 45777680 ps
CPU time 1.2 seconds
Started Jul 05 05:50:09 PM PDT 24
Finished Jul 05 05:50:10 PM PDT 24
Peak memory 218880 kb
Host smart-3df9e1b7-e1f7-47e8-9fc5-979fcee38050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329270246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1329270246
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3815715379
Short name T703
Test name
Test status
Simulation time 47970991 ps
CPU time 1.3 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 219108 kb
Host smart-67dac25d-fc6d-424d-a942-ea2c2b9c3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815715379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3815715379
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1688974439
Short name T530
Test name
Test status
Simulation time 70406691 ps
CPU time 1.1 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 220796 kb
Host smart-3c0c39f2-0cd5-413e-94dc-a965e4d85412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688974439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1688974439
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2747634122
Short name T498
Test name
Test status
Simulation time 109950709 ps
CPU time 1.35 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 217668 kb
Host smart-069a8ceb-5572-4609-b7c7-30fd85c31517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747634122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2747634122
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.631668784
Short name T182
Test name
Test status
Simulation time 47992316 ps
CPU time 1.13 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:16 PM PDT 24
Peak memory 218848 kb
Host smart-11a969e8-4d59-4747-bbc8-2e41d6b6f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631668784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.631668784
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.4250843858
Short name T17
Test name
Test status
Simulation time 31303493 ps
CPU time 1.06 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 219156 kb
Host smart-250f92e2-8f56-41ae-a889-41a3c4bd49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250843858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4250843858
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.324964540
Short name T663
Test name
Test status
Simulation time 33418488 ps
CPU time 1.37 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:26 PM PDT 24
Peak memory 220188 kb
Host smart-cdb0b04a-babe-4ceb-aeb9-4408cfc92946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324964540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.324964540
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2974138482
Short name T638
Test name
Test status
Simulation time 144128001 ps
CPU time 1.14 seconds
Started Jul 05 05:50:11 PM PDT 24
Finished Jul 05 05:50:13 PM PDT 24
Peak memory 217792 kb
Host smart-b718de2e-7d2f-4d33-9eca-50e962d3d4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974138482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2974138482
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.798619167
Short name T50
Test name
Test status
Simulation time 123332271 ps
CPU time 1.27 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:16 PM PDT 24
Peak memory 220404 kb
Host smart-1d974909-e35d-4f1e-bd26-db524c1a63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798619167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.798619167
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1933944390
Short name T946
Test name
Test status
Simulation time 72827780 ps
CPU time 1.79 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 218948 kb
Host smart-bf109c4b-9faf-425b-a64e-d9e0d26498c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933944390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1933944390
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.585343181
Short name T41
Test name
Test status
Simulation time 30457190 ps
CPU time 1.24 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 218852 kb
Host smart-5c2d7908-4ced-4a6f-b057-f7cf07bed74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585343181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.585343181
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3109594704
Short name T392
Test name
Test status
Simulation time 98566204 ps
CPU time 1.51 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 219480 kb
Host smart-6a3cbb88-4ee3-41ec-ba69-153055bff92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109594704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3109594704
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.4200393223
Short name T821
Test name
Test status
Simulation time 22303940 ps
CPU time 1.16 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 220196 kb
Host smart-4fb2585d-65f2-41e9-8068-6dd460640cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200393223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.4200393223
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1765867615
Short name T99
Test name
Test status
Simulation time 56365279 ps
CPU time 1.48 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:26 PM PDT 24
Peak memory 218928 kb
Host smart-068ce453-7ef2-4e32-bde5-1d231710d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765867615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1765867615
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3863090560
Short name T854
Test name
Test status
Simulation time 75138886 ps
CPU time 1.12 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 220220 kb
Host smart-1655e55d-dfa6-4898-959d-ff1c3fc74a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863090560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3863090560
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2879913
Short name T786
Test name
Test status
Simulation time 27995259 ps
CPU time 0.89 seconds
Started Jul 05 05:48:32 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 207012 kb
Host smart-ee3f50b0-ec6e-4990-970d-8c242ffa0d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2879913
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.3088956213
Short name T399
Test name
Test status
Simulation time 60275916 ps
CPU time 1.05 seconds
Started Jul 05 05:48:35 PM PDT 24
Finished Jul 05 05:48:36 PM PDT 24
Peak memory 220844 kb
Host smart-de87e325-d76c-499e-825e-90a6205ea69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088956213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3088956213
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3483887213
Short name T925
Test name
Test status
Simulation time 222752680 ps
CPU time 1.91 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 219164 kb
Host smart-22c95875-8a6f-4599-8ad0-ddf7cce22d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483887213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3483887213
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3962019925
Short name T856
Test name
Test status
Simulation time 36687517 ps
CPU time 0.88 seconds
Started Jul 05 05:48:28 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 215596 kb
Host smart-b6dc8254-7215-41a3-9a6a-ce14fbb838ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962019925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3962019925
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4140703047
Short name T515
Test name
Test status
Simulation time 16642038 ps
CPU time 1.03 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 215548 kb
Host smart-817340b3-b8e2-4be9-a359-04823990a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140703047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4140703047
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2047852771
Short name T780
Test name
Test status
Simulation time 40646957 ps
CPU time 1.34 seconds
Started Jul 05 05:48:32 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 207376 kb
Host smart-7736f862-6453-4b79-8dcc-0a0c5e887cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047852771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2047852771
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1112618951
Short name T905
Test name
Test status
Simulation time 115327548006 ps
CPU time 883.93 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 06:03:24 PM PDT 24
Peak memory 224036 kb
Host smart-7567b1e1-ddd2-4ef6-ac36-0acea61b558e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112618951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1112618951
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1198088349
Short name T230
Test name
Test status
Simulation time 196429903 ps
CPU time 1.26 seconds
Started Jul 05 05:50:13 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 220004 kb
Host smart-67d0d22d-83be-4d38-bdb0-4de6e434028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198088349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1198088349
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3468768432
Short name T954
Test name
Test status
Simulation time 76149949 ps
CPU time 1.24 seconds
Started Jul 05 05:50:12 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 217644 kb
Host smart-0ca3c09c-ba48-4161-9a60-23fdedc4d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468768432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3468768432
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3216448030
Short name T90
Test name
Test status
Simulation time 26094705 ps
CPU time 1.24 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 219932 kb
Host smart-5fe9baa1-05ef-4d97-9748-045582002ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216448030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3216448030
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.4174418070
Short name T306
Test name
Test status
Simulation time 56551434 ps
CPU time 1.27 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217008 kb
Host smart-0d3a4921-dce0-45c7-9f4f-2e139bbc47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174418070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4174418070
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3983618165
Short name T155
Test name
Test status
Simulation time 21317499 ps
CPU time 1.12 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 218984 kb
Host smart-71842338-2ccf-4084-9b2e-77177320509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983618165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3983618165
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3509357578
Short name T561
Test name
Test status
Simulation time 40662336 ps
CPU time 1.8 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 218848 kb
Host smart-7358c67a-4399-48eb-ad25-f8caa7a1157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509357578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3509357578
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.386268848
Short name T902
Test name
Test status
Simulation time 43673562 ps
CPU time 1.21 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219732 kb
Host smart-392f34b2-a2dd-4a65-9550-da41882f4983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386268848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.386268848
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.519776417
Short name T620
Test name
Test status
Simulation time 40585002 ps
CPU time 1.27 seconds
Started Jul 05 05:50:25 PM PDT 24
Finished Jul 05 05:50:27 PM PDT 24
Peak memory 217668 kb
Host smart-f6e3b511-e439-41e0-bf2d-1df4a2816a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519776417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.519776417
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2010327190
Short name T883
Test name
Test status
Simulation time 28435963 ps
CPU time 1.27 seconds
Started Jul 05 05:50:19 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219136 kb
Host smart-c3ac17e3-5cd6-4d87-9726-8f223e6cb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010327190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2010327190
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3548077975
Short name T271
Test name
Test status
Simulation time 22728928 ps
CPU time 1.18 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219984 kb
Host smart-704fb942-34a4-47d8-817b-a98d8e9f26b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548077975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3548077975
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1887527357
Short name T406
Test name
Test status
Simulation time 69073933 ps
CPU time 1.04 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 217356 kb
Host smart-db48e79b-a1e9-49f7-866c-b5e6fd82a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887527357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1887527357
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.604901168
Short name T738
Test name
Test status
Simulation time 23831638 ps
CPU time 1.22 seconds
Started Jul 05 05:50:29 PM PDT 24
Finished Jul 05 05:50:31 PM PDT 24
Peak memory 220120 kb
Host smart-ad34f43a-8395-4d90-886f-d1af7b4c0b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604901168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.604901168
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.56723669
Short name T841
Test name
Test status
Simulation time 37365990 ps
CPU time 1.41 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 220152 kb
Host smart-6d6f216e-4316-4766-a473-fb0b9bccf5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56723669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.56723669
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3358683398
Short name T896
Test name
Test status
Simulation time 45550765 ps
CPU time 1.12 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 218904 kb
Host smart-2343ea59-474b-4a88-9740-a612cc2b4415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358683398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3358683398
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2366011540
Short name T633
Test name
Test status
Simulation time 78954150 ps
CPU time 1.28 seconds
Started Jul 05 05:50:23 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 219464 kb
Host smart-e4d6bb67-2606-4292-83a4-732d2dd8742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366011540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2366011540
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3958395503
Short name T826
Test name
Test status
Simulation time 64543258 ps
CPU time 1.09 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 219904 kb
Host smart-7f3a50cb-932f-4b64-be7b-3ca6540632c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958395503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3958395503
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3345865376
Short name T286
Test name
Test status
Simulation time 71223049 ps
CPU time 1.37 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 219184 kb
Host smart-815f8c09-343a-4bb4-9400-daa786bcaeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345865376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3345865376
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3671874349
Short name T93
Test name
Test status
Simulation time 22241141 ps
CPU time 1.18 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:26 PM PDT 24
Peak memory 221104 kb
Host smart-472cb0fa-8e3c-440b-97eb-b372b0fbacdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671874349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3671874349
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1799130398
Short name T958
Test name
Test status
Simulation time 44644404 ps
CPU time 1.56 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 220192 kb
Host smart-3f44eeee-1dc2-47e9-acbc-bdb9b24d1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799130398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1799130398
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.200917417
Short name T446
Test name
Test status
Simulation time 22548575 ps
CPU time 1.18 seconds
Started Jul 05 05:47:47 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 215960 kb
Host smart-05a5c268-5028-45d0-9988-90ec97177ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200917417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.200917417
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.252306963
Short name T808
Test name
Test status
Simulation time 14874817 ps
CPU time 0.95 seconds
Started Jul 05 05:47:46 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 215252 kb
Host smart-91c8dc09-034d-46c1-bd8c-b905e84e8d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252306963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.252306963
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2368739272
Short name T757
Test name
Test status
Simulation time 17058313 ps
CPU time 0.85 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 216288 kb
Host smart-3c640e5d-5f70-4836-b4e3-53f144898ca3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368739272 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2368739272
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3897682851
Short name T720
Test name
Test status
Simulation time 82111953 ps
CPU time 1.15 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:50 PM PDT 24
Peak memory 217156 kb
Host smart-aeff20ae-1e3b-4c60-b1a4-c1047a658b43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897682851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3897682851
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3069741930
Short name T664
Test name
Test status
Simulation time 54631263 ps
CPU time 1 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:50 PM PDT 24
Peak memory 218956 kb
Host smart-16024dc8-0bee-4956-ad35-42d3e1ac3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069741930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3069741930
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.123921861
Short name T580
Test name
Test status
Simulation time 83518581 ps
CPU time 1.48 seconds
Started Jul 05 05:47:47 PM PDT 24
Finished Jul 05 05:47:49 PM PDT 24
Peak memory 219216 kb
Host smart-a499c41c-c9c1-43e7-8cfe-34eb1b9501bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123921861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.123921861
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.722421753
Short name T577
Test name
Test status
Simulation time 20627882 ps
CPU time 1.12 seconds
Started Jul 05 05:47:46 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 215816 kb
Host smart-a8707d7a-8098-4782-a30a-cc363a556975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722421753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.722421753
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1090553802
Short name T16
Test name
Test status
Simulation time 990647474 ps
CPU time 8.59 seconds
Started Jul 05 05:47:46 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 238076 kb
Host smart-9028ac06-10d1-40c1-9225-e12ece96e9e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090553802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1090553802
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.535117674
Short name T618
Test name
Test status
Simulation time 17527536 ps
CPU time 1.02 seconds
Started Jul 05 05:47:41 PM PDT 24
Finished Jul 05 05:47:43 PM PDT 24
Peak memory 215612 kb
Host smart-e2ad182c-d8d4-40a9-80ee-b224d95d79b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535117674 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.535117674
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.593797450
Short name T956
Test name
Test status
Simulation time 349641791 ps
CPU time 4.3 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 215548 kb
Host smart-7234314b-0cc1-4bd5-a1e1-6a9f1658dc8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593797450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.593797450
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1933390533
Short name T507
Test name
Test status
Simulation time 136562957225 ps
CPU time 555.41 seconds
Started Jul 05 05:47:46 PM PDT 24
Finished Jul 05 05:57:02 PM PDT 24
Peak memory 224012 kb
Host smart-a08f0623-d65e-4bf1-91aa-591afc0e9418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933390533 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1933390533
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1727275579
Short name T157
Test name
Test status
Simulation time 46264421 ps
CPU time 1.19 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 215992 kb
Host smart-5d5018b9-e352-43de-86a2-7515f438933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727275579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1727275579
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3419462247
Short name T610
Test name
Test status
Simulation time 19436735 ps
CPU time 0.88 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 207036 kb
Host smart-12b547bd-c424-4d6f-ad5d-98e2d3b1359e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419462247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3419462247
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3666923306
Short name T777
Test name
Test status
Simulation time 13344581 ps
CPU time 0.91 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 216768 kb
Host smart-5b7f7429-b632-46ff-9acd-d503df24b660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666923306 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3666923306
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.630873144
Short name T367
Test name
Test status
Simulation time 117767481 ps
CPU time 1.21 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 217108 kb
Host smart-813cfdd7-b022-4f85-b272-99393d975ac8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630873144 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.630873144
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.4144065880
Short name T331
Test name
Test status
Simulation time 35964596 ps
CPU time 0.9 seconds
Started Jul 05 05:48:32 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 218724 kb
Host smart-def08ed3-ff4c-4eaa-bc7b-7ac3ddb91a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144065880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4144065880
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2536494139
Short name T889
Test name
Test status
Simulation time 121679598 ps
CPU time 1.24 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 217728 kb
Host smart-7093a9e0-56ee-442e-b1f7-3ac65485b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536494139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2536494139
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.663289215
Short name T829
Test name
Test status
Simulation time 33986740 ps
CPU time 0.95 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 215752 kb
Host smart-eed44614-12f9-4718-abeb-e7c3073f1d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663289215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.663289215
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.283660289
Short name T805
Test name
Test status
Simulation time 20543793 ps
CPU time 1.04 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 215612 kb
Host smart-ca0b7971-150c-4d54-bb84-f0eb62590889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283660289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.283660289
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3332521068
Short name T177
Test name
Test status
Simulation time 280312313 ps
CPU time 3.9 seconds
Started Jul 05 05:50:10 PM PDT 24
Finished Jul 05 05:50:15 PM PDT 24
Peak memory 215624 kb
Host smart-5fc16e0c-9cff-4432-8689-08282cd5f2ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332521068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3332521068
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.981830274
Short name T220
Test name
Test status
Simulation time 97059490053 ps
CPU time 1033.73 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 06:05:54 PM PDT 24
Peak memory 221684 kb
Host smart-6620dbaa-3aa5-40e2-a945-14ef5d660dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981830274 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.981830274
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2782262378
Short name T568
Test name
Test status
Simulation time 40730533 ps
CPU time 1.38 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 217732 kb
Host smart-462d886e-04d5-457e-b78c-e5273a102b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782262378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2782262378
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.530393073
Short name T319
Test name
Test status
Simulation time 127867795 ps
CPU time 1.22 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 220764 kb
Host smart-fe86dad4-8ba0-43ee-9c0a-4b52789e2e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530393073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.530393073
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3640041165
Short name T934
Test name
Test status
Simulation time 175117803 ps
CPU time 2.6 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:34 PM PDT 24
Peak memory 220736 kb
Host smart-aa3682cd-9a7d-42c8-8986-237f091afdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640041165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3640041165
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2294148866
Short name T522
Test name
Test status
Simulation time 56607225 ps
CPU time 1.32 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 219236 kb
Host smart-77825eec-4d08-40cd-8d25-0410eb5b5fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294148866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2294148866
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2511150496
Short name T565
Test name
Test status
Simulation time 113904979 ps
CPU time 1.26 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 217792 kb
Host smart-deb6e58d-67f9-47a0-8777-a6e7104c360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511150496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2511150496
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1784295200
Short name T310
Test name
Test status
Simulation time 101485548 ps
CPU time 1.51 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 219972 kb
Host smart-4d1973ad-599a-4fe2-8a33-556ad5ee5a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784295200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1784295200
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2737662253
Short name T603
Test name
Test status
Simulation time 38477216 ps
CPU time 1.41 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 218844 kb
Host smart-24becaa3-c777-4594-960b-b80f12c79c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737662253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2737662253
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3740354264
Short name T523
Test name
Test status
Simulation time 50970301 ps
CPU time 1.34 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 220272 kb
Host smart-8a5de1e5-11b8-4c4e-8ac4-9cef25ac2985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740354264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3740354264
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3576437325
Short name T365
Test name
Test status
Simulation time 28556716 ps
CPU time 1.23 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 220328 kb
Host smart-c30b4666-3f45-42cd-b29a-717df5a88e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576437325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3576437325
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3190456022
Short name T496
Test name
Test status
Simulation time 41170205 ps
CPU time 1.43 seconds
Started Jul 05 05:50:24 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 217632 kb
Host smart-81a210ac-eb80-48b0-b8bc-62e63dd78c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190456022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3190456022
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2839024589
Short name T576
Test name
Test status
Simulation time 38984819 ps
CPU time 1.08 seconds
Started Jul 05 05:48:36 PM PDT 24
Finished Jul 05 05:48:38 PM PDT 24
Peak memory 220120 kb
Host smart-6f512218-8c7a-45ba-8644-c6c2c8a2183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839024589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2839024589
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2739087099
Short name T995
Test name
Test status
Simulation time 22663116 ps
CPU time 0.97 seconds
Started Jul 05 05:48:37 PM PDT 24
Finished Jul 05 05:48:39 PM PDT 24
Peak memory 215196 kb
Host smart-b2954550-33be-40e7-981e-8c6bec996c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739087099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2739087099
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1107996248
Short name T539
Test name
Test status
Simulation time 33613295 ps
CPU time 0.88 seconds
Started Jul 05 05:48:37 PM PDT 24
Finished Jul 05 05:48:39 PM PDT 24
Peak memory 216360 kb
Host smart-ecbbc42e-b1d3-4edb-94fa-b80ce05df589
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107996248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1107996248
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2622546512
Short name T107
Test name
Test status
Simulation time 42054577 ps
CPU time 1.44 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 217196 kb
Host smart-35c641c5-446d-409f-91ab-4a7f793f3c8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622546512 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2622546512
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4182348431
Short name T483
Test name
Test status
Simulation time 19063813 ps
CPU time 1.11 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 218952 kb
Host smart-dc4b6aa2-6f10-474d-858c-c88aa9139019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182348431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4182348431
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.34604526
Short name T464
Test name
Test status
Simulation time 21490416 ps
CPU time 1.28 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 217964 kb
Host smart-347a756b-7dc4-4ebf-8f0a-219d5cac8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34604526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.34604526
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3181233830
Short name T472
Test name
Test status
Simulation time 22172007 ps
CPU time 1.13 seconds
Started Jul 05 05:48:33 PM PDT 24
Finished Jul 05 05:48:35 PM PDT 24
Peak memory 215948 kb
Host smart-96fec7ab-6fa6-4c5d-82ec-e1efd7e626e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181233830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3181233830
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.968240641
Short name T887
Test name
Test status
Simulation time 15719429 ps
CPU time 0.99 seconds
Started Jul 05 05:48:29 PM PDT 24
Finished Jul 05 05:48:31 PM PDT 24
Peak memory 215612 kb
Host smart-647d1254-3656-40b3-8e76-ba258e6f6c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968240641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.968240641
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1213369951
Short name T479
Test name
Test status
Simulation time 325135679 ps
CPU time 1.33 seconds
Started Jul 05 05:48:31 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 215520 kb
Host smart-42b231f0-f2d7-4e7a-9e61-c458973ed22c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213369951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1213369951
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4154608043
Short name T449
Test name
Test status
Simulation time 63826055340 ps
CPU time 1646.79 seconds
Started Jul 05 05:48:30 PM PDT 24
Finished Jul 05 06:15:58 PM PDT 24
Peak memory 226052 kb
Host smart-3d40b179-e45e-4100-8563-a21aaac3cde4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154608043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4154608043
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3263782757
Short name T411
Test name
Test status
Simulation time 54114631 ps
CPU time 1.97 seconds
Started Jul 05 05:50:32 PM PDT 24
Finished Jul 05 05:50:34 PM PDT 24
Peak memory 218916 kb
Host smart-c3c43ae2-8294-4347-abef-e37a23e4fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263782757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3263782757
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3174878975
Short name T978
Test name
Test status
Simulation time 128632526 ps
CPU time 2.31 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 217800 kb
Host smart-8a5d7b5a-d72a-4cf9-ad38-4dc3f0ea284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174878975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3174878975
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.313383813
Short name T70
Test name
Test status
Simulation time 36409293 ps
CPU time 1.46 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 218940 kb
Host smart-b114b57d-d9ab-468a-a189-de734e2b9343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313383813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.313383813
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2904360243
Short name T264
Test name
Test status
Simulation time 93548030 ps
CPU time 1.26 seconds
Started Jul 05 05:50:28 PM PDT 24
Finished Jul 05 05:50:29 PM PDT 24
Peak memory 220028 kb
Host smart-3b43dd8e-6dd8-47b1-8ae4-cb50b48d31b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904360243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2904360243
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2296104338
Short name T725
Test name
Test status
Simulation time 47366778 ps
CPU time 1.2 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 220204 kb
Host smart-c644002d-5cf1-42ff-bc62-a6f488bd9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296104338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2296104338
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.762623962
Short name T517
Test name
Test status
Simulation time 68296089 ps
CPU time 1.14 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 217612 kb
Host smart-20f0258e-42ec-4758-a53f-a67cdf677952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762623962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.762623962
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3234873826
Short name T534
Test name
Test status
Simulation time 62907373 ps
CPU time 2.14 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:22 PM PDT 24
Peak memory 218836 kb
Host smart-91b9477d-15dc-4c64-8f3e-56fddb44711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234873826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3234873826
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.885176924
Short name T761
Test name
Test status
Simulation time 53437247 ps
CPU time 2.17 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 218912 kb
Host smart-f83e7df6-ded4-4729-a025-33cc12f2b74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885176924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.885176924
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1724077081
Short name T898
Test name
Test status
Simulation time 36675916 ps
CPU time 1.31 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 217748 kb
Host smart-1828fa87-6a17-4bc0-a752-a6176ff680c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724077081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1724077081
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1119272367
Short name T398
Test name
Test status
Simulation time 64266951 ps
CPU time 1.07 seconds
Started Jul 05 05:48:35 PM PDT 24
Finished Jul 05 05:48:37 PM PDT 24
Peak memory 220092 kb
Host smart-9cd5c847-ecdc-43de-af65-04fcd8835af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119272367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1119272367
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.299178726
Short name T613
Test name
Test status
Simulation time 25853913 ps
CPU time 0.89 seconds
Started Jul 05 05:48:37 PM PDT 24
Finished Jul 05 05:48:38 PM PDT 24
Peak memory 215304 kb
Host smart-e2839a3c-32a1-4abb-b85f-19bbb860b0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299178726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.299178726
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2161490561
Short name T189
Test name
Test status
Simulation time 20685073 ps
CPU time 0.87 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 216576 kb
Host smart-513e9069-d384-4cc9-a929-4ebdbeadf03a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161490561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2161490561
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3073547791
Short name T134
Test name
Test status
Simulation time 24216571 ps
CPU time 1.17 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 217156 kb
Host smart-ac2fe929-9496-40a4-abcf-51f16b60e11f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073547791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3073547791
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3032922591
Short name T485
Test name
Test status
Simulation time 23756212 ps
CPU time 0.88 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 218748 kb
Host smart-f02fb9bd-0e3a-4bcb-b7b8-d2d29ebea7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032922591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3032922591
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2188923960
Short name T643
Test name
Test status
Simulation time 106150401 ps
CPU time 2.36 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 219924 kb
Host smart-e1e8793e-fe57-46cc-9a77-116510a571e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188923960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2188923960
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3033098923
Short name T357
Test name
Test status
Simulation time 38373243 ps
CPU time 0.89 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 215740 kb
Host smart-5a832568-7233-4c0c-b9e7-232e29c5eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033098923 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3033098923
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2614386740
Short name T560
Test name
Test status
Simulation time 105306378 ps
CPU time 0.94 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 215428 kb
Host smart-cf8578d2-8330-4ffe-8659-e013a95804fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614386740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2614386740
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.790695930
Short name T783
Test name
Test status
Simulation time 188304129 ps
CPU time 1.82 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 215624 kb
Host smart-164a9573-328d-4dbc-8fe0-776d81ecd3d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790695930 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.790695930
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1815484650
Short name T533
Test name
Test status
Simulation time 115440685223 ps
CPU time 642.81 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 220768 kb
Host smart-8cc39470-d3c6-4c89-b319-4769bac9af26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815484650 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1815484650
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1293383904
Short name T615
Test name
Test status
Simulation time 98168698 ps
CPU time 1.23 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219456 kb
Host smart-d73f75b4-7b99-4101-9a5a-fbe5cfa8503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293383904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1293383904
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4131887876
Short name T476
Test name
Test status
Simulation time 44558140 ps
CPU time 1.3 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 220284 kb
Host smart-847d59a7-ab03-463b-829d-75c74471c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131887876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4131887876
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.415519377
Short name T453
Test name
Test status
Simulation time 45698136 ps
CPU time 1.16 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 217560 kb
Host smart-1ae00282-9c07-4b71-b2d4-1eb9ed0d4f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415519377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.415519377
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.99499642
Short name T611
Test name
Test status
Simulation time 64557697 ps
CPU time 2.55 seconds
Started Jul 05 05:50:25 PM PDT 24
Finished Jul 05 05:50:33 PM PDT 24
Peak memory 219508 kb
Host smart-ac92f983-5c40-4f15-bde4-df6b9133c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99499642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.99499642
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.483269077
Short name T289
Test name
Test status
Simulation time 183575654 ps
CPU time 1.52 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 218976 kb
Host smart-4cff40da-fe79-4ef2-8068-ae665f27dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483269077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.483269077
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3558118577
Short name T815
Test name
Test status
Simulation time 52305648 ps
CPU time 0.99 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217876 kb
Host smart-f3508fae-c28a-41df-8397-ab9b0588f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558118577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3558118577
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3026306978
Short name T734
Test name
Test status
Simulation time 103209142 ps
CPU time 1.49 seconds
Started Jul 05 05:50:15 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 219232 kb
Host smart-ac3d5270-f5a1-4f61-8bc4-59cc4b04177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026306978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3026306978
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.835759476
Short name T514
Test name
Test status
Simulation time 27677180 ps
CPU time 1.19 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217152 kb
Host smart-c5241fa2-9f70-473d-b0e4-afc16d0722e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835759476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.835759476
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2488901144
Short name T797
Test name
Test status
Simulation time 63146148 ps
CPU time 1.06 seconds
Started Jul 05 05:50:30 PM PDT 24
Finished Jul 05 05:50:31 PM PDT 24
Peak memory 217632 kb
Host smart-bb0a5bf5-3361-4379-b7bc-d467c3b15da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488901144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2488901144
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3124675346
Short name T308
Test name
Test status
Simulation time 60577124 ps
CPU time 1.36 seconds
Started Jul 05 05:50:16 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 219136 kb
Host smart-ecd3e7f9-0407-48c6-b77c-c85cecf994f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124675346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3124675346
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2167117666
Short name T843
Test name
Test status
Simulation time 22711209 ps
CPU time 1.1 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 219212 kb
Host smart-cb5418ff-b13f-4dc5-be25-ce580cd4c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167117666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2167117666
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4282528114
Short name T508
Test name
Test status
Simulation time 48292896 ps
CPU time 0.87 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:39 PM PDT 24
Peak memory 207060 kb
Host smart-8f465df4-ed3d-4900-ba4a-1f1474cca2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282528114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4282528114
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1307881999
Short name T893
Test name
Test status
Simulation time 11720979 ps
CPU time 0.9 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 216644 kb
Host smart-803ae886-83f8-4d79-abc9-0641eaad7bd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307881999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1307881999
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1972098732
Short name T190
Test name
Test status
Simulation time 26339501 ps
CPU time 1.22 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 217148 kb
Host smart-7e79e480-1d8f-46ca-9a05-049fcb0b4c7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972098732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1972098732
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3928860284
Short name T542
Test name
Test status
Simulation time 98911526 ps
CPU time 1.17 seconds
Started Jul 05 05:48:41 PM PDT 24
Finished Jul 05 05:48:43 PM PDT 24
Peak memory 225936 kb
Host smart-5e419e1a-a837-4089-94da-c6b2cf0448ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928860284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3928860284
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.157466120
Short name T340
Test name
Test status
Simulation time 49990439 ps
CPU time 1.86 seconds
Started Jul 05 05:48:34 PM PDT 24
Finished Jul 05 05:48:37 PM PDT 24
Peak memory 218848 kb
Host smart-929cee17-8fd0-4063-9cec-f59b0085ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157466120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.157466120
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3858228429
Short name T370
Test name
Test status
Simulation time 28188609 ps
CPU time 1.01 seconds
Started Jul 05 05:48:42 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 215864 kb
Host smart-1b728009-82e9-4fe5-aba6-0a98999b1e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858228429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3858228429
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2968103764
Short name T834
Test name
Test status
Simulation time 21920155 ps
CPU time 0.93 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:39 PM PDT 24
Peak memory 215600 kb
Host smart-69537d6e-170c-4b20-9f7a-ab20cdfe3ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968103764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2968103764
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3605081698
Short name T187
Test name
Test status
Simulation time 154654433 ps
CPU time 3.51 seconds
Started Jul 05 05:48:36 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 217448 kb
Host smart-2a2d7f0c-1c93-4a0a-80cb-ad17ba657175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605081698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3605081698
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2691670410
Short name T788
Test name
Test status
Simulation time 44692394825 ps
CPU time 1014.79 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 06:05:35 PM PDT 24
Peak memory 224120 kb
Host smart-69c4c624-9e32-437b-8f6a-00fe76cbb821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691670410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2691670410
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2054310277
Short name T291
Test name
Test status
Simulation time 71880662 ps
CPU time 2.63 seconds
Started Jul 05 05:50:18 PM PDT 24
Finished Jul 05 05:50:22 PM PDT 24
Peak memory 220648 kb
Host smart-c62665ee-c153-4bbc-a22f-500cd3038917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054310277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2054310277
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.208667759
Short name T933
Test name
Test status
Simulation time 26962092 ps
CPU time 1.22 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217620 kb
Host smart-43e47ca3-3c69-49f2-a082-fd96f8db35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208667759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.208667759
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2218150604
Short name T941
Test name
Test status
Simulation time 72413701 ps
CPU time 1.13 seconds
Started Jul 05 05:50:26 PM PDT 24
Finished Jul 05 05:50:28 PM PDT 24
Peak memory 217564 kb
Host smart-2ee9eb28-6544-454c-9bf0-704b8fa78e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218150604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2218150604
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1230392458
Short name T489
Test name
Test status
Simulation time 44900624 ps
CPU time 1.16 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:36 PM PDT 24
Peak memory 218908 kb
Host smart-84aef77f-541d-42ac-9e23-5dab4e236891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230392458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1230392458
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3732214785
Short name T936
Test name
Test status
Simulation time 47853846 ps
CPU time 1.89 seconds
Started Jul 05 05:50:19 PM PDT 24
Finished Jul 05 05:50:22 PM PDT 24
Peak memory 220744 kb
Host smart-80f8bd03-2821-40ae-b848-d545da8063f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732214785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3732214785
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2875334894
Short name T262
Test name
Test status
Simulation time 58576611 ps
CPU time 1.25 seconds
Started Jul 05 05:50:17 PM PDT 24
Finished Jul 05 05:50:21 PM PDT 24
Peak memory 219080 kb
Host smart-08697533-95bb-44da-ae05-a618b2b9b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875334894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2875334894
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3906185074
Short name T689
Test name
Test status
Simulation time 118876354 ps
CPU time 1.44 seconds
Started Jul 05 05:50:22 PM PDT 24
Finished Jul 05 05:50:24 PM PDT 24
Peak memory 220496 kb
Host smart-66b55587-0b76-4b53-8092-cb29781c964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906185074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3906185074
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.121438067
Short name T921
Test name
Test status
Simulation time 73692074 ps
CPU time 2.32 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 219076 kb
Host smart-b5dcf1ae-bdc7-4a7b-b908-c7a05b32863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121438067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.121438067
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2259578398
Short name T763
Test name
Test status
Simulation time 59144781 ps
CPU time 1.22 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 218788 kb
Host smart-f306b201-87e5-4f57-8375-c1889d1995fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259578398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2259578398
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2744863537
Short name T915
Test name
Test status
Simulation time 43018381 ps
CPU time 1.1 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 215688 kb
Host smart-616e9306-dee3-40c6-a0b1-ce6035a05f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744863537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2744863537
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1707220050
Short name T277
Test name
Test status
Simulation time 70168608 ps
CPU time 1.1 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 220120 kb
Host smart-12be13d1-6745-464d-9585-0701122c28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707220050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1707220050
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.824435349
Short name T64
Test name
Test status
Simulation time 15237860 ps
CPU time 0.92 seconds
Started Jul 05 05:48:43 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 215192 kb
Host smart-b7d386d5-2676-4d45-801d-0da995180ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824435349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.824435349
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3888380943
Short name T571
Test name
Test status
Simulation time 21368057 ps
CPU time 0.9 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 216656 kb
Host smart-bba6aa7c-6745-466e-ab4f-98548394b25c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888380943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3888380943
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3381913162
Short name T772
Test name
Test status
Simulation time 28048645 ps
CPU time 1.1 seconds
Started Jul 05 05:48:41 PM PDT 24
Finished Jul 05 05:48:43 PM PDT 24
Peak memory 217288 kb
Host smart-477a4263-0d93-4143-947d-e559e086542f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381913162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3381913162
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.331307457
Short name T894
Test name
Test status
Simulation time 26880426 ps
CPU time 1.03 seconds
Started Jul 05 05:48:42 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 224272 kb
Host smart-24b1ef0e-0ff3-463f-ba68-85c79cee3ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331307457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.331307457
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.3558263324
Short name T792
Test name
Test status
Simulation time 33828379 ps
CPU time 0.87 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 215636 kb
Host smart-2e1118db-38ce-457d-b5a7-dee38c75534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558263324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3558263324
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.228446297
Short name T985
Test name
Test status
Simulation time 16881876 ps
CPU time 1.02 seconds
Started Jul 05 05:48:36 PM PDT 24
Finished Jul 05 05:48:38 PM PDT 24
Peak memory 215620 kb
Host smart-3a5016e6-be27-4cea-9e2a-f6086b014a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228446297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.228446297
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1349289588
Short name T504
Test name
Test status
Simulation time 149810235 ps
CPU time 2.31 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:43 PM PDT 24
Peak memory 220036 kb
Host smart-4afca48d-97a2-4aac-a06b-b4b9e35abcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349289588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1349289588
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2800181937
Short name T217
Test name
Test status
Simulation time 150866932970 ps
CPU time 1435.81 seconds
Started Jul 05 05:48:36 PM PDT 24
Finished Jul 05 06:12:32 PM PDT 24
Peak memory 224420 kb
Host smart-7adbf280-7d60-4d8b-8fdc-b2152b1f9fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800181937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2800181937
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4133371793
Short name T771
Test name
Test status
Simulation time 53984256 ps
CPU time 1.66 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 215628 kb
Host smart-9140065f-1af6-4da4-9e2f-fd9300e0e289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133371793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4133371793
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1445340644
Short name T359
Test name
Test status
Simulation time 57127057 ps
CPU time 1.51 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 217640 kb
Host smart-d6adac04-4194-4af9-b118-166670c99577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445340644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1445340644
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3371688387
Short name T467
Test name
Test status
Simulation time 203258162 ps
CPU time 2.8 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 219352 kb
Host smart-9a05aa84-1006-43c8-93d9-3e07f5c99258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371688387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3371688387
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3430668414
Short name T441
Test name
Test status
Simulation time 98214679 ps
CPU time 1.39 seconds
Started Jul 05 05:50:26 PM PDT 24
Finished Jul 05 05:50:28 PM PDT 24
Peak memory 219180 kb
Host smart-0949e60b-939c-432e-9ca4-af1d11cb4bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430668414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3430668414
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3851084060
Short name T699
Test name
Test status
Simulation time 43529378 ps
CPU time 1.41 seconds
Started Jul 05 05:50:29 PM PDT 24
Finished Jul 05 05:50:31 PM PDT 24
Peak memory 215708 kb
Host smart-19967713-d221-47b3-ae61-19a9875269be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851084060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3851084060
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4069608657
Short name T373
Test name
Test status
Simulation time 100187942 ps
CPU time 1.36 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 218896 kb
Host smart-4733175e-3bb3-4603-b226-4d0e27ed39f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069608657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4069608657
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4130101194
Short name T977
Test name
Test status
Simulation time 47837254 ps
CPU time 1.97 seconds
Started Jul 05 05:50:31 PM PDT 24
Finished Jul 05 05:50:34 PM PDT 24
Peak memory 219092 kb
Host smart-85f37db8-7861-4b92-b54b-607ba9f77565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130101194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4130101194
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2603834156
Short name T900
Test name
Test status
Simulation time 68924080 ps
CPU time 1.32 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 219140 kb
Host smart-f7de0c62-6ba4-4ae1-b16e-86cb8380ca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603834156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2603834156
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.113028822
Short name T809
Test name
Test status
Simulation time 70585695 ps
CPU time 1.19 seconds
Started Jul 05 05:50:29 PM PDT 24
Finished Jul 05 05:50:31 PM PDT 24
Peak memory 219896 kb
Host smart-ca02c64b-dfe8-4588-a6c4-40e17a6682e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113028822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.113028822
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1932330732
Short name T408
Test name
Test status
Simulation time 91562320 ps
CPU time 1.45 seconds
Started Jul 05 05:50:32 PM PDT 24
Finished Jul 05 05:50:34 PM PDT 24
Peak memory 219384 kb
Host smart-c4ef3a6d-9aae-43b3-bad2-75ed6d1602be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932330732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1932330732
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.212690920
Short name T116
Test name
Test status
Simulation time 37625608 ps
CPU time 1.17 seconds
Started Jul 05 05:48:42 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 218796 kb
Host smart-cf309147-1b90-40d4-905a-859c473bcd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212690920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.212690920
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.377506767
Short name T376
Test name
Test status
Simulation time 22574019 ps
CPU time 1.05 seconds
Started Jul 05 05:48:47 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 207100 kb
Host smart-581c11dd-fa56-4b68-a2f9-a0485a39fac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377506767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.377506767
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2888026395
Short name T733
Test name
Test status
Simulation time 16812639 ps
CPU time 0.9 seconds
Started Jul 05 05:48:39 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 215912 kb
Host smart-7f1d92df-babc-43b2-84f3-ea2753d0b074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888026395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2888026395
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3769583002
Short name T718
Test name
Test status
Simulation time 92776603 ps
CPU time 1.02 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 220168 kb
Host smart-abbe6f34-9f47-4cc7-969f-0a55612e892a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769583002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3769583002
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.864082482
Short name T79
Test name
Test status
Simulation time 19627593 ps
CPU time 1.09 seconds
Started Jul 05 05:48:40 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 218780 kb
Host smart-672e7973-2c7d-4e46-991f-68bb475d6268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864082482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.864082482
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3098759807
Short name T48
Test name
Test status
Simulation time 237974412 ps
CPU time 1.45 seconds
Started Jul 05 05:48:41 PM PDT 24
Finished Jul 05 05:48:43 PM PDT 24
Peak memory 217756 kb
Host smart-668774e0-8735-4071-8ad2-b97ab5f4e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098759807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3098759807
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3236242478
Short name T409
Test name
Test status
Simulation time 28005562 ps
CPU time 1.02 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 05:48:51 PM PDT 24
Peak memory 215700 kb
Host smart-41885b1f-f717-44d1-9a06-b9d7e21b526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236242478 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3236242478
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1848480902
Short name T959
Test name
Test status
Simulation time 18140175 ps
CPU time 0.99 seconds
Started Jul 05 05:48:38 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 215600 kb
Host smart-a3970a40-7f55-4d49-a4e0-fdaacb79e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848480902 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1848480902
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1940257359
Short name T917
Test name
Test status
Simulation time 47352037 ps
CPU time 1.55 seconds
Started Jul 05 05:48:41 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 217488 kb
Host smart-7e14f87b-5621-4551-9d00-49aafc6a1c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940257359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1940257359
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4126379395
Short name T38
Test name
Test status
Simulation time 31431644903 ps
CPU time 662.86 seconds
Started Jul 05 05:48:42 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 221164 kb
Host smart-959fd536-4b35-46d6-a974-48f9b9bb86a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126379395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4126379395
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1378520545
Short name T971
Test name
Test status
Simulation time 46712306 ps
CPU time 1.85 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 218872 kb
Host smart-a21efde3-02ae-4299-965c-ca010fdcaeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378520545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1378520545
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1960088157
Short name T487
Test name
Test status
Simulation time 177836308 ps
CPU time 1.2 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217452 kb
Host smart-cc17456a-253b-44e1-a6a6-8eacba8a426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960088157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1960088157
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3385588925
Short name T953
Test name
Test status
Simulation time 120266484 ps
CPU time 1.35 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:36 PM PDT 24
Peak memory 217700 kb
Host smart-9801b088-081f-48ac-9683-43d8b2298960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385588925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3385588925
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2402401431
Short name T830
Test name
Test status
Simulation time 207827451 ps
CPU time 1.16 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 217536 kb
Host smart-86dab4e0-8fc9-4402-8bc4-5ca32a46615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402401431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2402401431
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2059150936
Short name T418
Test name
Test status
Simulation time 80340071 ps
CPU time 1.83 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 218984 kb
Host smart-0b92dc4f-a5a8-4aa4-9a7d-9cfb246f3091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059150936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2059150936
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.803310735
Short name T988
Test name
Test status
Simulation time 37535240 ps
CPU time 1.3 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:35 PM PDT 24
Peak memory 217832 kb
Host smart-b4307b52-512b-46dd-bfe4-1e00fdedafb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803310735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.803310735
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.537428026
Short name T589
Test name
Test status
Simulation time 64249229 ps
CPU time 1.38 seconds
Started Jul 05 05:50:22 PM PDT 24
Finished Jul 05 05:50:24 PM PDT 24
Peak memory 219044 kb
Host smart-9aa8aafa-1850-48df-bb84-b620a3445d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537428026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.537428026
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4057528211
Short name T822
Test name
Test status
Simulation time 56444204 ps
CPU time 1.3 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 219084 kb
Host smart-3d8e377a-5c72-4b2b-b97d-692dbd40f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057528211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4057528211
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2020635437
Short name T412
Test name
Test status
Simulation time 37369480 ps
CPU time 1.34 seconds
Started Jul 05 05:50:26 PM PDT 24
Finished Jul 05 05:50:27 PM PDT 24
Peak memory 218796 kb
Host smart-fa5a5b86-ba51-4049-94c1-c18951815a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020635437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2020635437
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2400100600
Short name T698
Test name
Test status
Simulation time 68089926 ps
CPU time 1.25 seconds
Started Jul 05 05:50:23 PM PDT 24
Finished Jul 05 05:50:24 PM PDT 24
Peak memory 220160 kb
Host smart-de493f78-fe7b-4f3d-bb4c-a247fceeaeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400100600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2400100600
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.875413119
Short name T673
Test name
Test status
Simulation time 72182081 ps
CPU time 1.15 seconds
Started Jul 05 05:48:48 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 220132 kb
Host smart-5d9e5370-f04c-4831-9635-cfc9fc77e445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875413119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.875413119
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2681411857
Short name T474
Test name
Test status
Simulation time 16799239 ps
CPU time 0.96 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:47 PM PDT 24
Peak memory 207104 kb
Host smart-8e9e8bec-1b5d-4758-8ab2-af9a006574b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681411857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2681411857
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4204148884
Short name T932
Test name
Test status
Simulation time 12480823 ps
CPU time 0.93 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:48 PM PDT 24
Peak memory 216700 kb
Host smart-d9f3349f-003d-44a2-9fa9-aa26387e3be0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204148884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4204148884
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1673782254
Short name T490
Test name
Test status
Simulation time 23018890 ps
CPU time 1.04 seconds
Started Jul 05 05:48:43 PM PDT 24
Finished Jul 05 05:48:45 PM PDT 24
Peak memory 217128 kb
Host smart-63974d99-06ca-4848-bdc3-58a4284553c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673782254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1673782254
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.262658117
Short name T119
Test name
Test status
Simulation time 32914483 ps
CPU time 1.03 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:47 PM PDT 24
Peak memory 229880 kb
Host smart-4d19b458-1b8a-4061-91c2-aa1e1789d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262658117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.262658117
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.950193767
Short name T599
Test name
Test status
Simulation time 41970487 ps
CPU time 1.09 seconds
Started Jul 05 05:48:43 PM PDT 24
Finished Jul 05 05:48:44 PM PDT 24
Peak memory 224276 kb
Host smart-903bb42d-4c35-44cf-924a-e5a9398ea6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950193767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.950193767
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2093598260
Short name T547
Test name
Test status
Simulation time 32159994 ps
CPU time 0.93 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 215632 kb
Host smart-01bc0a11-2247-417a-b961-f73b2b5c46c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093598260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2093598260
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4023724922
Short name T224
Test name
Test status
Simulation time 2479492085 ps
CPU time 5.12 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 217612 kb
Host smart-3e6e250b-3311-46e7-a9a1-51019398f927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023724922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4023724922
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2677508884
Short name T178
Test name
Test status
Simulation time 330192989861 ps
CPU time 1908.15 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 06:20:38 PM PDT 24
Peak memory 226704 kb
Host smart-c10f6487-9f77-437e-8c54-eb86a2fddd9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677508884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2677508884
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4129285155
Short name T396
Test name
Test status
Simulation time 93124854 ps
CPU time 1.2 seconds
Started Jul 05 05:50:21 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 220372 kb
Host smart-d2fa8232-a5d6-4729-83e5-902148f239d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129285155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4129285155
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.923758867
Short name T339
Test name
Test status
Simulation time 66701757 ps
CPU time 0.97 seconds
Started Jul 05 05:50:22 PM PDT 24
Finished Jul 05 05:50:23 PM PDT 24
Peak memory 217760 kb
Host smart-79419ea1-f150-4c86-a905-20381ca009fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923758867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.923758867
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1088529881
Short name T353
Test name
Test status
Simulation time 291501789 ps
CPU time 1.13 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217516 kb
Host smart-838c3b15-c717-4f93-9d1e-9a9b0b49f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088529881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1088529881
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.752402444
Short name T717
Test name
Test status
Simulation time 32721923 ps
CPU time 1.41 seconds
Started Jul 05 05:50:19 PM PDT 24
Finished Jul 05 05:50:22 PM PDT 24
Peak memory 219100 kb
Host smart-f610a51c-68c1-4868-accc-940edbf11f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752402444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.752402444
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2618858950
Short name T572
Test name
Test status
Simulation time 65510953 ps
CPU time 1.03 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 217484 kb
Host smart-1046c17e-f3c6-49bf-b581-0c8d295a3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618858950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2618858950
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2531770628
Short name T469
Test name
Test status
Simulation time 123501364 ps
CPU time 2.92 seconds
Started Jul 05 05:50:22 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 220504 kb
Host smart-fee340c5-fb8e-49a3-b4d6-1c58b7630668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531770628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2531770628
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3856956124
Short name T358
Test name
Test status
Simulation time 54915439 ps
CPU time 2.03 seconds
Started Jul 05 05:50:26 PM PDT 24
Finished Jul 05 05:50:29 PM PDT 24
Peak memory 218908 kb
Host smart-c375416c-f1ac-467a-8364-262ec89872b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856956124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3856956124
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2649276803
Short name T315
Test name
Test status
Simulation time 60489402 ps
CPU time 2.12 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 220324 kb
Host smart-c7be3a78-c9dc-4cf3-807d-15567840068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649276803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2649276803
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2124621996
Short name T344
Test name
Test status
Simulation time 67803583 ps
CPU time 1.66 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 218920 kb
Host smart-7049e3da-496b-4fe8-9d10-0353bf7c37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124621996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2124621996
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3398033842
Short name T524
Test name
Test status
Simulation time 68894782 ps
CPU time 1.18 seconds
Started Jul 05 05:50:25 PM PDT 24
Finished Jul 05 05:50:27 PM PDT 24
Peak memory 218912 kb
Host smart-7b121a55-ff71-4c6d-866a-2226922367b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398033842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3398033842
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.439455481
Short name T52
Test name
Test status
Simulation time 78114224 ps
CPU time 1.21 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 220660 kb
Host smart-aeda14c0-305a-447c-9e1c-896e878d3f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439455481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.439455481
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1507451409
Short name T825
Test name
Test status
Simulation time 28779092 ps
CPU time 1.14 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 215208 kb
Host smart-c4af119e-d8f3-44b4-96de-7f10ffff98a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507451409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1507451409
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4044537127
Short name T563
Test name
Test status
Simulation time 40512925 ps
CPU time 0.93 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:47 PM PDT 24
Peak memory 215664 kb
Host smart-446e1119-79cf-4f32-aaf1-5401140da7d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044537127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4044537127
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3120442072
Short name T368
Test name
Test status
Simulation time 69537596 ps
CPU time 1.21 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 217068 kb
Host smart-49d3b512-10bb-41ce-b459-3fee02acb088
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120442072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3120442072
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2839058501
Short name T80
Test name
Test status
Simulation time 54658353 ps
CPU time 0.89 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:00 PM PDT 24
Peak memory 218624 kb
Host smart-b555240b-af7a-4a96-9aac-3e70a85ce656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839058501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2839058501
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2049759759
Short name T305
Test name
Test status
Simulation time 39088689 ps
CPU time 1.4 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 217432 kb
Host smart-3a400232-166a-49ce-b2e8-db31533bd891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049759759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2049759759
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2626799320
Short name T790
Test name
Test status
Simulation time 21176188 ps
CPU time 1.07 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:48 PM PDT 24
Peak memory 215760 kb
Host smart-24af77a4-bfb2-4924-af48-c8ac83bf1564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626799320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2626799320
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.85755888
Short name T346
Test name
Test status
Simulation time 47224982 ps
CPU time 0.89 seconds
Started Jul 05 05:48:47 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 215612 kb
Host smart-b9c194a9-3dc6-491c-ab01-e9eff4185f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85755888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.85755888
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.427767084
Short name T965
Test name
Test status
Simulation time 3648966652 ps
CPU time 4.43 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 215800 kb
Host smart-728258bc-39e7-42f3-8c12-d5356e442a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427767084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.427767084
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4041858540
Short name T743
Test name
Test status
Simulation time 232762116733 ps
CPU time 3031.67 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 06:39:19 PM PDT 24
Peak memory 235656 kb
Host smart-174aff7d-7381-47a4-98fd-4f0dfa4da17f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041858540 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4041858540
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2317140609
Short name T321
Test name
Test status
Simulation time 74405572 ps
CPU time 1.33 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 219692 kb
Host smart-6b91d388-9dd9-4c03-a6c7-aa360b76ef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317140609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2317140609
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2869858610
Short name T860
Test name
Test status
Simulation time 105683239 ps
CPU time 1.4 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 219216 kb
Host smart-e6cf9bd0-8a8d-44d9-bea7-a3f830ed02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869858610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2869858610
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2236245480
Short name T627
Test name
Test status
Simulation time 27905586 ps
CPU time 1.35 seconds
Started Jul 05 05:50:34 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 217672 kb
Host smart-7c531ba3-1c20-42e2-abdb-afc2c96fe304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236245480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2236245480
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3330485746
Short name T377
Test name
Test status
Simulation time 44761110 ps
CPU time 1.4 seconds
Started Jul 05 05:50:26 PM PDT 24
Finished Jul 05 05:50:28 PM PDT 24
Peak memory 218940 kb
Host smart-15c73d5f-a040-4f84-9963-41b15c0fb8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330485746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3330485746
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3978426575
Short name T857
Test name
Test status
Simulation time 61264825 ps
CPU time 1.36 seconds
Started Jul 05 05:50:41 PM PDT 24
Finished Jul 05 05:50:43 PM PDT 24
Peak memory 218840 kb
Host smart-4571f14c-01b2-4fef-8c18-eeff84086d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978426575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3978426575
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2874011824
Short name T667
Test name
Test status
Simulation time 132609379 ps
CPU time 2.82 seconds
Started Jul 05 05:50:38 PM PDT 24
Finished Jul 05 05:50:43 PM PDT 24
Peak memory 219648 kb
Host smart-c904f42d-ff73-42ec-8a02-509797c9b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874011824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2874011824
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4290973465
Short name T414
Test name
Test status
Simulation time 49808419 ps
CPU time 1.7 seconds
Started Jul 05 05:50:32 PM PDT 24
Finished Jul 05 05:50:34 PM PDT 24
Peak memory 218976 kb
Host smart-4d1192d1-fbd2-44a7-93a1-6f8e313d1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290973465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4290973465
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2716427146
Short name T49
Test name
Test status
Simulation time 42499456 ps
CPU time 1.52 seconds
Started Jul 05 05:50:54 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 218844 kb
Host smart-94e57516-9423-4cd3-a292-44ce1d68efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716427146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2716427146
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.196802025
Short name T296
Test name
Test status
Simulation time 36865181 ps
CPU time 1.15 seconds
Started Jul 05 05:50:51 PM PDT 24
Finished Jul 05 05:50:55 PM PDT 24
Peak memory 218776 kb
Host smart-9dbab84e-609e-4f04-94ce-291378d4103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196802025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.196802025
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.581719734
Short name T294
Test name
Test status
Simulation time 32188024 ps
CPU time 1.27 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 217672 kb
Host smart-3a70d7f9-ad44-4a3c-be4b-575b5c1d907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581719734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.581719734
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3588326808
Short name T126
Test name
Test status
Simulation time 30636529 ps
CPU time 1.4 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:48 PM PDT 24
Peak memory 220172 kb
Host smart-1d91065e-e641-424a-a7c8-b10e6a5fa77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588326808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3588326808
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3061039328
Short name T328
Test name
Test status
Simulation time 23400659 ps
CPU time 0.83 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:47 PM PDT 24
Peak memory 206848 kb
Host smart-f74305df-940e-4e6e-8466-c9d082b90c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061039328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3061039328
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.606452335
Short name T374
Test name
Test status
Simulation time 63362340 ps
CPU time 1.06 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 05:48:51 PM PDT 24
Peak memory 218524 kb
Host smart-b9fccd54-ab1c-4e67-a618-efa291fb5058
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606452335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.606452335
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.4060375321
Short name T122
Test name
Test status
Simulation time 72609784 ps
CPU time 1.05 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 220964 kb
Host smart-b416390e-abd8-4877-8013-15bc30c67760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060375321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.4060375321
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3582683154
Short name T555
Test name
Test status
Simulation time 44667303 ps
CPU time 1.29 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 05:48:51 PM PDT 24
Peak memory 219164 kb
Host smart-c67c9b18-3813-4fb3-b84e-639637ac6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582683154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3582683154
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2858524014
Short name T868
Test name
Test status
Simulation time 44474075 ps
CPU time 1.05 seconds
Started Jul 05 05:48:46 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 224332 kb
Host smart-d87145ed-6edf-4c47-ae3b-3f9cffaae28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858524014 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2858524014
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2537992824
Short name T326
Test name
Test status
Simulation time 18779256 ps
CPU time 0.97 seconds
Started Jul 05 05:48:47 PM PDT 24
Finished Jul 05 05:48:49 PM PDT 24
Peak memory 215632 kb
Host smart-60d38f93-3fc3-46a4-b583-4ef935653b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537992824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2537992824
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2731189565
Short name T337
Test name
Test status
Simulation time 797916982 ps
CPU time 4.96 seconds
Started Jul 05 05:48:47 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 217784 kb
Host smart-de379f46-cd92-43d1-ba21-c44255d4afa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731189565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2731189565
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.86926399
Short name T501
Test name
Test status
Simulation time 182184571919 ps
CPU time 1171.29 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 06:08:16 PM PDT 24
Peak memory 224096 kb
Host smart-c02ae0b3-49bc-47ae-9955-e3a089e020af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86926399 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.86926399
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2966717722
Short name T686
Test name
Test status
Simulation time 40333814 ps
CPU time 1.54 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 220328 kb
Host smart-42b40c96-ae2d-4fb1-976b-9d0fbf670c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966717722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2966717722
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2922398270
Short name T482
Test name
Test status
Simulation time 49879156 ps
CPU time 1.18 seconds
Started Jul 05 05:50:40 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 219772 kb
Host smart-62359cf6-6fd5-40ed-a8a3-e39ec31cd8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922398270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2922398270
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2282445044
Short name T937
Test name
Test status
Simulation time 58590670 ps
CPU time 1.08 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 217508 kb
Host smart-62aa26fe-4f18-47a5-a0f3-f284163058e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282445044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2282445044
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.859648227
Short name T701
Test name
Test status
Simulation time 70652501 ps
CPU time 1.05 seconds
Started Jul 05 05:50:44 PM PDT 24
Finished Jul 05 05:50:46 PM PDT 24
Peak memory 217572 kb
Host smart-cf012bc1-05e1-407f-8abf-d58868e80c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859648227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.859648227
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2409520085
Short name T42
Test name
Test status
Simulation time 89410818 ps
CPU time 1.12 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 217672 kb
Host smart-3554dce9-a9ed-42b7-8a6b-b40c4b5066d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409520085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2409520085
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1794846348
Short name T484
Test name
Test status
Simulation time 141751831 ps
CPU time 3.01 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 220472 kb
Host smart-db71eb86-39a9-4b70-9424-64343e4d74fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794846348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1794846348
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1914464474
Short name T46
Test name
Test status
Simulation time 662407429 ps
CPU time 5.05 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 220792 kb
Host smart-fa0b7cd4-8537-4673-ba09-418bdee4bb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914464474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1914464474
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4293437886
Short name T984
Test name
Test status
Simulation time 57846311 ps
CPU time 1.28 seconds
Started Jul 05 05:50:45 PM PDT 24
Finished Jul 05 05:50:47 PM PDT 24
Peak memory 217576 kb
Host smart-675e9004-837c-45ec-881d-affaac2cde60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293437886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4293437886
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.108308906
Short name T345
Test name
Test status
Simulation time 91388969 ps
CPU time 1.09 seconds
Started Jul 05 05:50:44 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 217780 kb
Host smart-6dd92c32-8a36-4a20-9a5d-97a3c33f0982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108308906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.108308906
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.33856079
Short name T634
Test name
Test status
Simulation time 96752777 ps
CPU time 1.27 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 219060 kb
Host smart-619c6e6d-cb3c-4dce-8ac4-2a65300f8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33856079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.33856079
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1135330652
Short name T208
Test name
Test status
Simulation time 24601147 ps
CPU time 1.22 seconds
Started Jul 05 05:48:44 PM PDT 24
Finished Jul 05 05:48:46 PM PDT 24
Peak memory 221472 kb
Host smart-20b1375d-b348-4d5d-94f7-6eedb9b64a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135330652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1135330652
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4095010331
Short name T781
Test name
Test status
Simulation time 83182206 ps
CPU time 0.88 seconds
Started Jul 05 05:48:50 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 207028 kb
Host smart-6b6d0a68-1ef8-4d82-b45c-b1882178068a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095010331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4095010331
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2018130283
Short name T770
Test name
Test status
Simulation time 27203168 ps
CPU time 0.91 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:54 PM PDT 24
Peak memory 216580 kb
Host smart-b62a94db-8014-417d-b5c2-0e4348047691
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018130283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2018130283
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3855624619
Short name T719
Test name
Test status
Simulation time 39431681 ps
CPU time 1.36 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 218668 kb
Host smart-840be60b-de98-42e0-88e2-649c27bf8089
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855624619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3855624619
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1994061683
Short name T151
Test name
Test status
Simulation time 24559922 ps
CPU time 0.96 seconds
Started Jul 05 05:48:49 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 219076 kb
Host smart-f365172d-79ed-42f6-975b-89ee6826b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994061683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1994061683
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2866652198
Short name T562
Test name
Test status
Simulation time 48561598 ps
CPU time 1.1 seconds
Started Jul 05 05:48:48 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 218956 kb
Host smart-dee5e33e-9c57-4106-a8dd-e04292839aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866652198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2866652198
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3140668078
Short name T741
Test name
Test status
Simulation time 31590347 ps
CPU time 0.87 seconds
Started Jul 05 05:48:48 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 215712 kb
Host smart-551c00f6-7ecb-431f-90d6-f3e2e3560c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140668078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3140668078
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.262804953
Short name T707
Test name
Test status
Simulation time 27191770 ps
CPU time 0.95 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:00 PM PDT 24
Peak memory 215612 kb
Host smart-1289bc58-8b0d-471e-9ea3-5d8d93d073e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262804953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.262804953
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1015914784
Short name T702
Test name
Test status
Simulation time 1441102771 ps
CPU time 4.06 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 215596 kb
Host smart-4c474594-3b22-4aee-a262-a0cca0baa356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015914784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1015914784
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.722772298
Short name T37
Test name
Test status
Simulation time 191528287288 ps
CPU time 2497.49 seconds
Started Jul 05 05:48:45 PM PDT 24
Finished Jul 05 06:30:23 PM PDT 24
Peak memory 232424 kb
Host smart-9c6d4b58-5ba2-476b-94f9-a5be33e788e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722772298 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.722772298
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1574932367
Short name T383
Test name
Test status
Simulation time 54470941 ps
CPU time 1.39 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 218948 kb
Host smart-775f6245-60ee-4b9e-bf89-547f77987b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574932367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1574932367
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2080869853
Short name T543
Test name
Test status
Simulation time 41286731 ps
CPU time 1.5 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 218960 kb
Host smart-cacec5f8-1f31-45f7-a803-e6673e8ad836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080869853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2080869853
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4163520446
Short name T970
Test name
Test status
Simulation time 56664264 ps
CPU time 1.15 seconds
Started Jul 05 05:50:47 PM PDT 24
Finished Jul 05 05:50:49 PM PDT 24
Peak memory 218800 kb
Host smart-1031bcb6-6319-4a80-b7f8-c122e2e7c83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163520446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4163520446
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1942282993
Short name T992
Test name
Test status
Simulation time 49567302 ps
CPU time 1.73 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 218788 kb
Host smart-7c9d87ab-4230-4833-90d9-83bfef40ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942282993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1942282993
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.919203926
Short name T40
Test name
Test status
Simulation time 71586423 ps
CPU time 1.41 seconds
Started Jul 05 05:50:42 PM PDT 24
Finished Jul 05 05:50:44 PM PDT 24
Peak memory 218684 kb
Host smart-f6cd75f3-24ec-42cf-950a-90bd93b47ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919203926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.919203926
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3406154405
Short name T531
Test name
Test status
Simulation time 54969169 ps
CPU time 1.26 seconds
Started Jul 05 05:50:35 PM PDT 24
Finished Jul 05 05:50:38 PM PDT 24
Peak memory 218908 kb
Host smart-adc31359-2b22-40b7-ae2d-bde0a2ccf99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406154405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3406154405
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2726015879
Short name T45
Test name
Test status
Simulation time 40229263 ps
CPU time 1.49 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 217464 kb
Host smart-6fb68808-e978-4e59-a5db-a2776cf9837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726015879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2726015879
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3681966970
Short name T304
Test name
Test status
Simulation time 86054463 ps
CPU time 1.24 seconds
Started Jul 05 05:50:33 PM PDT 24
Finished Jul 05 05:50:36 PM PDT 24
Peak memory 220268 kb
Host smart-4042187a-6c34-4be3-a4d0-175317f0f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681966970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3681966970
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.591753551
Short name T945
Test name
Test status
Simulation time 74414285 ps
CPU time 1.15 seconds
Started Jul 05 05:50:37 PM PDT 24
Finished Jul 05 05:50:41 PM PDT 24
Peak memory 217740 kb
Host smart-83435201-b1c0-4364-ad08-65a0739b492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591753551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.591753551
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.805097825
Short name T912
Test name
Test status
Simulation time 24076329 ps
CPU time 1.23 seconds
Started Jul 05 05:50:36 PM PDT 24
Finished Jul 05 05:50:40 PM PDT 24
Peak memory 217804 kb
Host smart-b2ad1aa6-041e-4f60-a6c1-334aeea79de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805097825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.805097825
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1712177881
Short name T14
Test name
Test status
Simulation time 404498686 ps
CPU time 1.5 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:50 PM PDT 24
Peak memory 220952 kb
Host smart-a926954e-0d38-48fb-aa2e-4fd1ffa1ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712177881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1712177881
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3891448737
Short name T630
Test name
Test status
Simulation time 43390750 ps
CPU time 0.86 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 215188 kb
Host smart-d21a8631-68af-41b5-8581-2042d26bf340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891448737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3891448737
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3954202442
Short name T184
Test name
Test status
Simulation time 18773865 ps
CPU time 0.83 seconds
Started Jul 05 05:47:44 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 216584 kb
Host smart-ccbd5b9f-baf6-4077-8ea2-39d9e2d311db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954202442 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3954202442
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1591624297
Short name T114
Test name
Test status
Simulation time 50251571 ps
CPU time 1.45 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 217152 kb
Host smart-d76d51fd-7c22-4dfb-9877-2d723d280c21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591624297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1591624297
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.866389852
Short name T891
Test name
Test status
Simulation time 29889752 ps
CPU time 1.21 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 219948 kb
Host smart-f244f302-7855-424c-8a71-255acf3904bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866389852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.866389852
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3948565803
Short name T831
Test name
Test status
Simulation time 98986018 ps
CPU time 1.21 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 217660 kb
Host smart-3ec702a4-224a-4283-bc59-14b0e9e1f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948565803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3948565803
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.952688557
Short name T612
Test name
Test status
Simulation time 25451547 ps
CPU time 0.97 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 215752 kb
Host smart-497d7d5f-57d3-48e3-b960-2929db0bbe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952688557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.952688557
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1629694667
Short name T711
Test name
Test status
Simulation time 59189935 ps
CPU time 0.95 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:49 PM PDT 24
Peak memory 207364 kb
Host smart-9bc5994c-0af9-4ab1-9fbc-195bca38c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629694667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1629694667
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3563668284
Short name T63
Test name
Test status
Simulation time 3615286792 ps
CPU time 5.54 seconds
Started Jul 05 05:47:46 PM PDT 24
Finished Jul 05 05:47:52 PM PDT 24
Peak memory 235908 kb
Host smart-91826a7f-730a-4207-b3f1-d3f45576948c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563668284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3563668284
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3474572395
Short name T762
Test name
Test status
Simulation time 15489452 ps
CPU time 0.99 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:50 PM PDT 24
Peak memory 215632 kb
Host smart-2c70b92e-4f1e-4b54-b80b-1936a3cbcdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474572395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3474572395
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1117979236
Short name T581
Test name
Test status
Simulation time 182358453 ps
CPU time 3.88 seconds
Started Jul 05 05:47:48 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 215708 kb
Host smart-8f14758b-3723-478d-bb18-4c4581bae207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117979236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1117979236
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3244932415
Short name T350
Test name
Test status
Simulation time 54949117609 ps
CPU time 1250.92 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 06:08:45 PM PDT 24
Peak memory 222192 kb
Host smart-e22b0ae6-615c-4670-8394-2bbb7817e67c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244932415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3244932415
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3796728275
Short name T275
Test name
Test status
Simulation time 29330280 ps
CPU time 1.33 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:54 PM PDT 24
Peak memory 219004 kb
Host smart-7e8018b9-5d87-465b-a675-446c31c22f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796728275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3796728275
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4233790382
Short name T360
Test name
Test status
Simulation time 21331979 ps
CPU time 1.06 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:48:56 PM PDT 24
Peak memory 207132 kb
Host smart-677902c8-1c67-4902-ad6a-8123aa121005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233790382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4233790382
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2909317513
Short name T366
Test name
Test status
Simulation time 26402820 ps
CPU time 0.85 seconds
Started Jul 05 05:48:51 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 216212 kb
Host smart-0c58d636-2d1e-4614-835c-1bcff6bba507
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909317513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2909317513
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.413635115
Short name T106
Test name
Test status
Simulation time 54093933 ps
CPU time 1.21 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 217248 kb
Host smart-f2262828-2394-4553-94a9-e7e422777933
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413635115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.413635115
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2492157689
Short name T139
Test name
Test status
Simulation time 33500885 ps
CPU time 1.03 seconds
Started Jul 05 05:48:56 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 220924 kb
Host smart-d490dcfe-9055-404e-901b-bfa4e2dc524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492157689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2492157689
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3265257650
Short name T552
Test name
Test status
Simulation time 588486867 ps
CPU time 4.79 seconds
Started Jul 05 05:48:53 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 219928 kb
Host smart-ab85e691-8e8b-4ef9-a089-f9d99d503c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265257650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3265257650
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.91130457
Short name T32
Test name
Test status
Simulation time 19798317 ps
CPU time 1.05 seconds
Started Jul 05 05:48:51 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 216100 kb
Host smart-46cb67d8-e5b1-498c-b3b3-1be6aefb047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91130457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.91130457
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1478201238
Short name T425
Test name
Test status
Simulation time 15935994 ps
CPU time 0.97 seconds
Started Jul 05 05:48:51 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 215580 kb
Host smart-dc8e6870-3010-4c14-a5ec-6484c67c0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478201238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1478201238
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1407953026
Short name T404
Test name
Test status
Simulation time 379971819 ps
CPU time 4.17 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 217652 kb
Host smart-7ccda0a8-e555-4ba9-8ba3-2fe0ed277ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407953026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1407953026
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.4121079756
Short name T69
Test name
Test status
Simulation time 81976476456 ps
CPU time 1206.46 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 06:09:07 PM PDT 24
Peak memory 222428 kb
Host smart-7e46e04e-02fb-4318-8f4f-bd2bd9dad45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121079756 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.4121079756
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.887692371
Short name T281
Test name
Test status
Simulation time 25596316 ps
CPU time 1.25 seconds
Started Jul 05 05:48:55 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 219100 kb
Host smart-3a985f8a-f4c7-4cb6-8879-21292319cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887692371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.887692371
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1579149902
Short name T444
Test name
Test status
Simulation time 18641786 ps
CPU time 0.84 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 207104 kb
Host smart-380cf2a5-2437-4392-b438-931ba6bf1e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579149902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1579149902
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3562332679
Short name T729
Test name
Test status
Simulation time 54337780 ps
CPU time 1.12 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 220084 kb
Host smart-da174ee8-c20b-4c23-a0e9-b86aa80901b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562332679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3562332679
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3339063572
Short name T512
Test name
Test status
Simulation time 26607019 ps
CPU time 0.98 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:54 PM PDT 24
Peak memory 219052 kb
Host smart-531940db-16b8-4014-bd68-f1da250a355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339063572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3339063572
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2377134718
Short name T336
Test name
Test status
Simulation time 164147470 ps
CPU time 1.02 seconds
Started Jul 05 05:48:50 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 217552 kb
Host smart-1e6ec117-8aee-45bc-92db-fa2bbab3497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377134718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2377134718
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4085493302
Short name T31
Test name
Test status
Simulation time 19848745 ps
CPU time 1.16 seconds
Started Jul 05 05:48:55 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 216100 kb
Host smart-d59f07ce-ad38-4b53-9f6e-20b92976f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085493302 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4085493302
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2763368499
Short name T863
Test name
Test status
Simulation time 20245642 ps
CPU time 1.07 seconds
Started Jul 05 05:48:52 PM PDT 24
Finished Jul 05 05:48:54 PM PDT 24
Peak memory 215576 kb
Host smart-23d34aa1-fcf0-458f-898f-12f1ef256868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763368499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2763368499
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1898732651
Short name T186
Test name
Test status
Simulation time 262472452 ps
CPU time 5.24 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:49:00 PM PDT 24
Peak memory 217672 kb
Host smart-f8be1b61-9e5c-4660-a639-880b9d025f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898732651 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1898732651
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.425450887
Short name T430
Test name
Test status
Simulation time 10068507776 ps
CPU time 266.92 seconds
Started Jul 05 05:48:51 PM PDT 24
Finished Jul 05 05:53:19 PM PDT 24
Peak memory 218268 kb
Host smart-4879fd83-1f61-4cfc-9c19-cc36a90c64bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425450887 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.425450887
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3976407391
Short name T149
Test name
Test status
Simulation time 25502017 ps
CPU time 1.19 seconds
Started Jul 05 05:48:51 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 220236 kb
Host smart-9471f8ad-a556-48ff-a076-c5c16683cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976407391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3976407391
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1497396704
Short name T74
Test name
Test status
Simulation time 24517788 ps
CPU time 0.92 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:04 PM PDT 24
Peak memory 207040 kb
Host smart-faba991a-1ef4-4872-a711-6f3d3a51d97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497396704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1497396704
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2419534101
Short name T2
Test name
Test status
Simulation time 22551174 ps
CPU time 0.94 seconds
Started Jul 05 05:48:53 PM PDT 24
Finished Jul 05 05:48:55 PM PDT 24
Peak memory 216580 kb
Host smart-2cc65b8c-354c-4ea2-8269-7dbd12709cac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419534101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2419534101
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.261613717
Short name T141
Test name
Test status
Simulation time 276952964 ps
CPU time 1.17 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:48:56 PM PDT 24
Peak memory 217104 kb
Host smart-af6715cd-4f6a-43fb-a71a-5de1936d348f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261613717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.261613717
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.2234668273
Short name T820
Test name
Test status
Simulation time 166983603 ps
CPU time 1.23 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:48:56 PM PDT 24
Peak memory 217500 kb
Host smart-fca24ce8-76b4-458c-88da-43e7117be332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234668273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2234668273
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2830937290
Short name T697
Test name
Test status
Simulation time 35796867 ps
CPU time 0.89 seconds
Started Jul 05 05:48:48 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 215580 kb
Host smart-0e63d218-6b3d-4713-8cba-cc28651c6fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830937290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2830937290
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3276040885
Short name T758
Test name
Test status
Simulation time 29080693 ps
CPU time 0.98 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:48:56 PM PDT 24
Peak memory 215616 kb
Host smart-4c7b4ccf-1e92-490d-af6c-501d35e054da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276040885 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3276040885
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3883824916
Short name T691
Test name
Test status
Simulation time 543927817 ps
CPU time 6.08 seconds
Started Jul 05 05:48:53 PM PDT 24
Finished Jul 05 05:49:00 PM PDT 24
Peak memory 215632 kb
Host smart-54eb2dac-f7b2-4eaa-afbd-c5f77c508bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883824916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3883824916
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3307888957
Short name T549
Test name
Test status
Simulation time 63799786777 ps
CPU time 457.12 seconds
Started Jul 05 05:48:54 PM PDT 24
Finished Jul 05 05:56:32 PM PDT 24
Peak memory 218036 kb
Host smart-a3e11dbd-a889-46b3-abb3-dd9caf3017b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307888957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3307888957
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1374505229
Short name T209
Test name
Test status
Simulation time 237004065 ps
CPU time 1.34 seconds
Started Jul 05 05:49:05 PM PDT 24
Finished Jul 05 05:49:07 PM PDT 24
Peak memory 215932 kb
Host smart-00cfa15f-fecf-4873-9f0a-8b7f10113f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374505229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1374505229
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1907877886
Short name T755
Test name
Test status
Simulation time 38918567 ps
CPU time 0.86 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:04 PM PDT 24
Peak memory 206844 kb
Host smart-b581c73c-4c57-4016-9554-aaaf186d5243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907877886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1907877886
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1304500650
Short name T434
Test name
Test status
Simulation time 13802797 ps
CPU time 0.95 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:03 PM PDT 24
Peak memory 216448 kb
Host smart-b321dd2f-fbfa-417a-9d8d-b629ffd79918
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304500650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1304500650
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.3411560435
Short name T806
Test name
Test status
Simulation time 30598218 ps
CPU time 1.33 seconds
Started Jul 05 05:49:00 PM PDT 24
Finished Jul 05 05:49:02 PM PDT 24
Peak memory 219828 kb
Host smart-da239da8-0280-4e04-a002-ffc39bcabc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411560435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3411560435
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.837634687
Short name T832
Test name
Test status
Simulation time 140875206 ps
CPU time 1.66 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:04 PM PDT 24
Peak memory 219420 kb
Host smart-51a25668-ea3d-4821-b2e7-966ae08b0d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837634687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.837634687
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4055426330
Short name T491
Test name
Test status
Simulation time 40464290 ps
CPU time 0.93 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:05 PM PDT 24
Peak memory 215780 kb
Host smart-441e8951-be44-4474-8fcd-8ef41150d729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055426330 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4055426330
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4025409441
Short name T342
Test name
Test status
Simulation time 48403289 ps
CPU time 0.9 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 215640 kb
Host smart-d0f8116f-5fa1-43a2-80da-a7a827e87091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025409441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4025409441
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.853131156
Short name T759
Test name
Test status
Simulation time 1249049118 ps
CPU time 4.41 seconds
Started Jul 05 05:49:04 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 215620 kb
Host smart-ee50a50e-619f-4e82-a355-b23c57fcd3e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853131156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.853131156
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3025598460
Short name T532
Test name
Test status
Simulation time 106013735009 ps
CPU time 1378.29 seconds
Started Jul 05 05:49:04 PM PDT 24
Finished Jul 05 06:12:04 PM PDT 24
Peak memory 226892 kb
Host smart-9106298a-ffd8-499f-bfb2-94f61741b09f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025598460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3025598460
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3159827764
Short name T991
Test name
Test status
Simulation time 25336237 ps
CPU time 1.26 seconds
Started Jul 05 05:49:03 PM PDT 24
Finished Jul 05 05:49:06 PM PDT 24
Peak memory 220124 kb
Host smart-ed03d91b-ea25-4cef-b1e4-a8a38938c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159827764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3159827764
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.117977340
Short name T957
Test name
Test status
Simulation time 31030672 ps
CPU time 0.86 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 207076 kb
Host smart-6857b365-a1a5-4874-9d37-dc0acd583c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117977340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.117977340
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3672541193
Short name T415
Test name
Test status
Simulation time 36807160 ps
CPU time 0.83 seconds
Started Jul 05 05:49:05 PM PDT 24
Finished Jul 05 05:49:07 PM PDT 24
Peak memory 216504 kb
Host smart-c213eecf-ba89-4a47-ab98-c3035291a90e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672541193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3672541193
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3093045014
Short name T488
Test name
Test status
Simulation time 32173287 ps
CPU time 1.24 seconds
Started Jul 05 05:48:58 PM PDT 24
Finished Jul 05 05:49:00 PM PDT 24
Peak memory 220284 kb
Host smart-ff6f7269-0f5e-49af-891b-5844534a432f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093045014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3093045014
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3691252447
Short name T77
Test name
Test status
Simulation time 19928221 ps
CPU time 1.08 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:04 PM PDT 24
Peak memory 218740 kb
Host smart-e27f1c09-7605-4ac7-ae86-2b15aaf5237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691252447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3691252447
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1734378161
Short name T76
Test name
Test status
Simulation time 89117928 ps
CPU time 1.06 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 217620 kb
Host smart-9282c664-a35e-44e9-ba89-930c3ad037a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734378161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1734378161
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.834208639
Short name T544
Test name
Test status
Simulation time 29981598 ps
CPU time 0.91 seconds
Started Jul 05 05:48:59 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 215848 kb
Host smart-6c112750-f11b-4bb8-ac07-392103cee016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834208639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.834208639
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3538120306
Short name T966
Test name
Test status
Simulation time 26974442 ps
CPU time 1.01 seconds
Started Jul 05 05:49:05 PM PDT 24
Finished Jul 05 05:49:07 PM PDT 24
Peak memory 215548 kb
Host smart-44ffbc12-c8e6-4fb8-abcf-783d5aab5082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538120306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3538120306
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1019793382
Short name T874
Test name
Test status
Simulation time 1802026579 ps
CPU time 4.12 seconds
Started Jul 05 05:49:03 PM PDT 24
Finished Jul 05 05:49:09 PM PDT 24
Peak memory 217628 kb
Host smart-5ab3f53d-e3eb-4c05-b88e-e8245176dde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019793382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1019793382
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2982205856
Short name T213
Test name
Test status
Simulation time 105070807058 ps
CPU time 664.49 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 06:00:07 PM PDT 24
Peak memory 220492 kb
Host smart-35d6bffd-024c-42e3-873c-7375a57ae65e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982205856 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2982205856
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2794021780
Short name T812
Test name
Test status
Simulation time 78358074 ps
CPU time 1.19 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:03 PM PDT 24
Peak memory 220052 kb
Host smart-98935a19-b056-4996-9dd7-9a172aba722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794021780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2794021780
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1320954899
Short name T644
Test name
Test status
Simulation time 189861580 ps
CPU time 0.86 seconds
Started Jul 05 05:49:00 PM PDT 24
Finished Jul 05 05:49:02 PM PDT 24
Peak memory 207040 kb
Host smart-6632a230-8e0d-4402-a11c-b8100da830a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320954899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1320954899
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.320336428
Short name T200
Test name
Test status
Simulation time 18072175 ps
CPU time 0.9 seconds
Started Jul 05 05:49:05 PM PDT 24
Finished Jul 05 05:49:07 PM PDT 24
Peak memory 216488 kb
Host smart-b95db115-bb0d-4aa2-8385-e751abb0778c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320336428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.320336428
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1557579684
Short name T876
Test name
Test status
Simulation time 62110571 ps
CPU time 1.12 seconds
Started Jul 05 05:49:04 PM PDT 24
Finished Jul 05 05:49:06 PM PDT 24
Peak memory 217168 kb
Host smart-90a95218-843b-4531-b3b2-81e60a38e955
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557579684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1557579684
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1903337781
Short name T658
Test name
Test status
Simulation time 31636976 ps
CPU time 0.91 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:03 PM PDT 24
Peak memory 218704 kb
Host smart-061a6406-6e64-4745-b954-9a70b98fce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903337781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1903337781
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1004716998
Short name T311
Test name
Test status
Simulation time 32392372 ps
CPU time 1.33 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:04 PM PDT 24
Peak memory 220324 kb
Host smart-e7f42bc8-3fbd-4569-b965-74ea6a120017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004716998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1004716998
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.376148365
Short name T722
Test name
Test status
Simulation time 20277625 ps
CPU time 1.08 seconds
Started Jul 05 05:49:01 PM PDT 24
Finished Jul 05 05:49:03 PM PDT 24
Peak memory 216052 kb
Host smart-bf4d8513-463d-4c5a-b929-dac13b8ab34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376148365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.376148365
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4044216721
Short name T548
Test name
Test status
Simulation time 14875875 ps
CPU time 0.97 seconds
Started Jul 05 05:48:57 PM PDT 24
Finished Jul 05 05:48:58 PM PDT 24
Peak memory 215636 kb
Host smart-adff62ed-5172-4a0c-a0f0-6f6931139aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044216721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4044216721
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1580737496
Short name T466
Test name
Test status
Simulation time 187231869 ps
CPU time 4.03 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:08 PM PDT 24
Peak memory 217648 kb
Host smart-ce860e59-11b0-467f-bb18-1400cdb69fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580737496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1580737496
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1113851064
Short name T338
Test name
Test status
Simulation time 264266649511 ps
CPU time 1471.44 seconds
Started Jul 05 05:49:00 PM PDT 24
Finished Jul 05 06:13:33 PM PDT 24
Peak memory 224300 kb
Host smart-63d0dd8e-3d6a-4f46-a016-5a8aec512da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113851064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1113851064
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1983851438
Short name T935
Test name
Test status
Simulation time 22865755 ps
CPU time 1.31 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:11 PM PDT 24
Peak memory 218784 kb
Host smart-a0a6cdf0-f70c-4d38-aa4a-9ac8e18cdc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983851438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1983851438
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.629187706
Short name T582
Test name
Test status
Simulation time 71330479 ps
CPU time 1.62 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 215284 kb
Host smart-6e492c70-10d4-4119-b7ee-5881fdd543b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629187706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.629187706
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4057176904
Short name T766
Test name
Test status
Simulation time 21715008 ps
CPU time 0.9 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 215724 kb
Host smart-87e27d40-6834-4390-8aba-bb673f2ea421
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057176904 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4057176904
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1157002243
Short name T447
Test name
Test status
Simulation time 32461755 ps
CPU time 1.24 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:11 PM PDT 24
Peak memory 217304 kb
Host smart-04485cf6-7410-4571-977d-2ad5f2444ad9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157002243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1157002243
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.297135741
Short name T56
Test name
Test status
Simulation time 71330392 ps
CPU time 1.01 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:09 PM PDT 24
Peak memory 229684 kb
Host smart-d2113d58-d3c2-4c30-8359-18f8c1835b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297135741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.297135741
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1856170769
Short name T499
Test name
Test status
Simulation time 30659766 ps
CPU time 1.52 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:05 PM PDT 24
Peak memory 217740 kb
Host smart-753fcb4a-7e3f-4d80-a549-c3cdf8a615f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856170769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1856170769
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.1603426094
Short name T641
Test name
Test status
Simulation time 18336523 ps
CPU time 1.05 seconds
Started Jul 05 05:49:07 PM PDT 24
Finished Jul 05 05:49:08 PM PDT 24
Peak memory 215660 kb
Host smart-e7fd621c-8067-41da-b4e4-1e77af6e4298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603426094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1603426094
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1087215054
Short name T428
Test name
Test status
Simulation time 26069740 ps
CPU time 1.12 seconds
Started Jul 05 05:49:02 PM PDT 24
Finished Jul 05 05:49:05 PM PDT 24
Peak memory 215600 kb
Host smart-7104c2eb-2009-4565-b813-efeed373f4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087215054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1087215054
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3891779301
Short name T214
Test name
Test status
Simulation time 123737346447 ps
CPU time 414.08 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:56:05 PM PDT 24
Peak memory 219296 kb
Host smart-def07a82-9249-44d5-9b82-35adbd6b33f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891779301 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3891779301
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.846669165
Short name T784
Test name
Test status
Simulation time 52045419 ps
CPU time 1.29 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 219016 kb
Host smart-3660e913-258c-4ff0-82e3-df2573aa86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846669165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.846669165
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.486905528
Short name T852
Test name
Test status
Simulation time 61883182 ps
CPU time 0.84 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:09 PM PDT 24
Peak memory 206836 kb
Host smart-66c8bf10-161b-476d-8043-979bf8f32629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486905528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.486905528
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3422229194
Short name T170
Test name
Test status
Simulation time 12957726 ps
CPU time 0.93 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 216816 kb
Host smart-b0f9067d-9c5a-4ba1-86dc-3d6756490e99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422229194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3422229194
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4247341161
Short name T480
Test name
Test status
Simulation time 80493859 ps
CPU time 1.23 seconds
Started Jul 05 05:49:05 PM PDT 24
Finished Jul 05 05:49:07 PM PDT 24
Peak memory 218712 kb
Host smart-5464f99c-ec10-40a8-af4d-c85a1656624b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247341161 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4247341161
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.591134979
Short name T133
Test name
Test status
Simulation time 36789216 ps
CPU time 1.27 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 220996 kb
Host smart-c956dab0-c0c7-4b16-a307-90b4c109bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591134979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.591134979
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.146026801
Short name T423
Test name
Test status
Simulation time 151334478 ps
CPU time 2.17 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 220464 kb
Host smart-26c55967-2443-42cf-900c-465d6a4ad1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146026801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.146026801
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.2842742728
Short name T803
Test name
Test status
Simulation time 43523287 ps
CPU time 0.93 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 215552 kb
Host smart-be8d0df9-e787-47fd-88e2-b2872654f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842742728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2842742728
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2163738635
Short name T724
Test name
Test status
Simulation time 875481533 ps
CPU time 4.53 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:17 PM PDT 24
Peak memory 215628 kb
Host smart-09316ecd-88ea-41cf-bb2e-161adb9cc280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163738635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2163738635
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2173433832
Short name T904
Test name
Test status
Simulation time 149459338718 ps
CPU time 1731.91 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 06:18:01 PM PDT 24
Peak memory 225824 kb
Host smart-177e8fe9-a87d-427e-9854-f808216d685d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173433832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2173433832
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.574148907
Short name T154
Test name
Test status
Simulation time 47168171 ps
CPU time 1.22 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 218916 kb
Host smart-1d4fe4d5-45e3-4c08-ae8f-eed37215a0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574148907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.574148907
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3565958325
Short name T481
Test name
Test status
Simulation time 28565689 ps
CPU time 0.92 seconds
Started Jul 05 05:49:07 PM PDT 24
Finished Jul 05 05:49:09 PM PDT 24
Peak memory 207024 kb
Host smart-13fb8d5e-3225-4c1d-9051-8c06e246c3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565958325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3565958325
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1974039553
Short name T203
Test name
Test status
Simulation time 17005600 ps
CPU time 0.91 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 215748 kb
Host smart-51cbb839-755d-4a8b-897a-b345db19488c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974039553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1974039553
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2237816381
Short name T128
Test name
Test status
Simulation time 61791289 ps
CPU time 1.02 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:17 PM PDT 24
Peak memory 218968 kb
Host smart-54d34bd8-a68c-4436-b8fa-600c5aad2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237816381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2237816381
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2033329878
Short name T293
Test name
Test status
Simulation time 71489824 ps
CPU time 1.15 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 220024 kb
Host smart-da40adbc-2842-4144-8efc-2d320abc292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033329878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2033329878
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2754682274
Short name T334
Test name
Test status
Simulation time 25323337 ps
CPU time 0.98 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 215768 kb
Host smart-a4f62b7f-1e7d-4278-94d0-f7ed9fdd517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754682274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2754682274
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1896995416
Short name T330
Test name
Test status
Simulation time 101447845 ps
CPU time 0.92 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 215408 kb
Host smart-87c3a84a-87aa-4f24-9175-cb3a18d93c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896995416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1896995416
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.530742321
Short name T335
Test name
Test status
Simulation time 2302675474 ps
CPU time 4.41 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 215708 kb
Host smart-e0377bae-c7da-4228-82ca-1450d3aabf8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530742321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.530742321
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.683992818
Short name T450
Test name
Test status
Simulation time 55587740921 ps
CPU time 1427.36 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 06:13:06 PM PDT 24
Peak memory 224716 kb
Host smart-c275d3c1-7e17-4736-9aaf-49e4c748b77e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683992818 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.683992818
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1912064569
Short name T778
Test name
Test status
Simulation time 41809773 ps
CPU time 1.18 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 218892 kb
Host smart-d2279055-3731-4cd5-ae0b-322ba5a5e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912064569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1912064569
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3648943884
Short name T879
Test name
Test status
Simulation time 20580885 ps
CPU time 0.87 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 207112 kb
Host smart-a2fc1209-c62c-4ec3-bc56-c02863b2ff73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648943884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3648943884
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2426164121
Short name T986
Test name
Test status
Simulation time 80752180 ps
CPU time 0.94 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 216352 kb
Host smart-a9a45eaf-6b15-472b-8260-d68c709c4d58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426164121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2426164121
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.997796104
Short name T847
Test name
Test status
Simulation time 425712835 ps
CPU time 1.25 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 217140 kb
Host smart-dd85b637-ce78-47a3-95fc-ba8c6e5c4e61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997796104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.997796104
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.726489708
Short name T222
Test name
Test status
Simulation time 81134143 ps
CPU time 0.94 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 224112 kb
Host smart-0dac7a98-76fb-4ea6-80da-eefb54617dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726489708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.726489708
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2484345246
Short name T432
Test name
Test status
Simulation time 32138674 ps
CPU time 1.36 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:11 PM PDT 24
Peak memory 220268 kb
Host smart-3f57285a-8a5d-4c37-889b-036381190afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484345246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2484345246
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.860848354
Short name T34
Test name
Test status
Simulation time 33464249 ps
CPU time 0.97 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:11 PM PDT 24
Peak memory 215940 kb
Host smart-25848645-5d61-4bf4-bab9-64b965212cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860848354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.860848354
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4282960219
Short name T678
Test name
Test status
Simulation time 31900352 ps
CPU time 0.92 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:17 PM PDT 24
Peak memory 215608 kb
Host smart-15b70442-6b69-47e9-8b64-1297b9f88125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282960219 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4282960219
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3054393741
Short name T662
Test name
Test status
Simulation time 452917957 ps
CPU time 5.03 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 217660 kb
Host smart-d75c9541-43d0-4d46-b2fd-cf08d7f661ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054393741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3054393741
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.974530689
Short name T218
Test name
Test status
Simulation time 45363811951 ps
CPU time 640.72 seconds
Started Jul 05 05:49:06 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 224032 kb
Host smart-97515d38-c881-4a58-95ea-b1973e8c2738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974530689 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.974530689
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3295731717
Short name T51
Test name
Test status
Simulation time 28028994 ps
CPU time 1.25 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 218836 kb
Host smart-846fbc54-d9d3-46ed-85d0-791f60d38d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295731717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3295731717
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3472365568
Short name T586
Test name
Test status
Simulation time 39335754 ps
CPU time 1.02 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 207084 kb
Host smart-1bed0e31-c9de-4215-aae2-5b7ed4f24500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472365568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3472365568
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3731836216
Short name T169
Test name
Test status
Simulation time 36135075 ps
CPU time 0.9 seconds
Started Jul 05 05:47:56 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 216552 kb
Host smart-25230bf0-9f5d-441a-9b37-ee7a561273b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731836216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3731836216
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.688329495
Short name T906
Test name
Test status
Simulation time 178966137 ps
CPU time 1.21 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 218672 kb
Host smart-abc80ada-3939-4a5d-bb5f-b31288331338
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688329495 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.688329495
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2770916933
Short name T567
Test name
Test status
Simulation time 62953855 ps
CPU time 0.86 seconds
Started Jul 05 05:47:56 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 218740 kb
Host smart-c091c576-b912-452a-bff6-b5c8a6a6f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770916933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2770916933
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1141700547
Short name T96
Test name
Test status
Simulation time 172455476 ps
CPU time 1.1 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 217648 kb
Host smart-f6a496a8-abf0-4e28-a69b-155e167c00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141700547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1141700547
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2989053422
Short name T651
Test name
Test status
Simulation time 31345086 ps
CPU time 1.01 seconds
Started Jul 05 05:47:58 PM PDT 24
Finished Jul 05 05:48:00 PM PDT 24
Peak memory 224412 kb
Host smart-5ee0358d-91e9-4f51-8061-2539bacb80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989053422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2989053422
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2093162445
Short name T976
Test name
Test status
Simulation time 99616493 ps
CPU time 0.9 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 207352 kb
Host smart-b5fb741a-8a77-4ef2-b4d2-3bd057fc24b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093162445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2093162445
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3833246339
Short name T669
Test name
Test status
Simulation time 34542905 ps
CPU time 0.96 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 215624 kb
Host smart-4ccd6651-eab4-4389-969b-c84d2ffb9376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833246339 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3833246339
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2594069401
Short name T316
Test name
Test status
Simulation time 241930526 ps
CPU time 5.1 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:48:01 PM PDT 24
Peak memory 217584 kb
Host smart-df69e097-e94a-48ad-a891-3fd959e4b11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594069401 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2594069401
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2602813315
Short name T505
Test name
Test status
Simulation time 90281465398 ps
CPU time 1576.99 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 06:14:13 PM PDT 24
Peak memory 225764 kb
Host smart-2ec0e32a-3b6e-467f-b1d6-382bbce31f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602813315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2602813315
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3790172717
Short name T518
Test name
Test status
Simulation time 22294473 ps
CPU time 1.15 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 220324 kb
Host smart-f3b18f8d-eedd-470b-bf72-9d057755c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790172717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3790172717
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2920794210
Short name T855
Test name
Test status
Simulation time 89210021 ps
CPU time 0.83 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 206344 kb
Host smart-5a9a3c81-e173-4954-90cd-7d8ca207f126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920794210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2920794210
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1787203989
Short name T405
Test name
Test status
Simulation time 39029558 ps
CPU time 0.86 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 215764 kb
Host smart-a1010d2b-bbf9-4382-b84d-b2fe9baa7425
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787203989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1787203989
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3682576929
Short name T205
Test name
Test status
Simulation time 71773757 ps
CPU time 1.1 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 219972 kb
Host smart-fee11d3a-cf02-4f9d-8c4f-08ee2caad85b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682576929 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3682576929
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.435873003
Short name T938
Test name
Test status
Simulation time 26813048 ps
CPU time 1 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:11 PM PDT 24
Peak memory 219924 kb
Host smart-87831cd5-61a6-4920-8f61-dd34efffde34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435873003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.435873003
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1688542488
Short name T844
Test name
Test status
Simulation time 78328364 ps
CPU time 1.46 seconds
Started Jul 05 05:49:11 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 219036 kb
Host smart-45b18d8b-d9e4-4efe-9976-3f034e64c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688542488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1688542488
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2718600433
Short name T742
Test name
Test status
Simulation time 36612139 ps
CPU time 0.92 seconds
Started Jul 05 05:49:14 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 224144 kb
Host smart-dccf8f32-62f8-4c61-bdd5-e523c9c0a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718600433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2718600433
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1447280009
Short name T923
Test name
Test status
Simulation time 28211985 ps
CPU time 0.95 seconds
Started Jul 05 05:49:09 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 207416 kb
Host smart-c07ddd18-5273-4f0b-b397-765ba62fe144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447280009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1447280009
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1983450265
Short name T865
Test name
Test status
Simulation time 68703436 ps
CPU time 1.24 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 217732 kb
Host smart-9633245a-7801-46d7-8587-699454725dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983450265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1983450265
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.3213508562
Short name T438
Test name
Test status
Simulation time 302445502 ps
CPU time 1.07 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 220168 kb
Host smart-7bb82e05-f93b-47f7-b48d-93d1485cfdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213508562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3213508562
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3930373158
Short name T802
Test name
Test status
Simulation time 46218147 ps
CPU time 0.89 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 215232 kb
Host smart-4712c0b5-54e1-40cc-85cc-668f1b0ac3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930373158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3930373158
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1505102398
Short name T728
Test name
Test status
Simulation time 33248751 ps
CPU time 1.01 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 216956 kb
Host smart-d324b31c-1fe3-4ccb-b026-bb6bc5ab1bef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505102398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1505102398
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3661131953
Short name T113
Test name
Test status
Simulation time 83666164 ps
CPU time 1.25 seconds
Started Jul 05 05:49:14 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 217360 kb
Host smart-dccc1a26-a93b-4397-b674-c680a6b09325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661131953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3661131953
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_genbits.3321630992
Short name T798
Test name
Test status
Simulation time 64028270 ps
CPU time 1.61 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 218916 kb
Host smart-8d7c9535-28ed-49e0-86be-062787341064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321630992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3321630992
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2854880682
Short name T696
Test name
Test status
Simulation time 20000436 ps
CPU time 1.07 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 216224 kb
Host smart-32d5082a-bbbe-4587-ab7e-8a6ee7afc366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854880682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2854880682
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3927237722
Short name T687
Test name
Test status
Simulation time 42121271 ps
CPU time 0.94 seconds
Started Jul 05 05:49:08 PM PDT 24
Finished Jul 05 05:49:10 PM PDT 24
Peak memory 215616 kb
Host smart-4f11ba5c-e144-403e-9627-c2886d453510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927237722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3927237722
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.521705000
Short name T872
Test name
Test status
Simulation time 2402223987 ps
CPU time 4.51 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 217620 kb
Host smart-87dc8976-b380-48e9-987f-37f16163afc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521705000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.521705000
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3079821210
Short name T595
Test name
Test status
Simulation time 36583167705 ps
CPU time 418.65 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:56:11 PM PDT 24
Peak memory 218976 kb
Host smart-8adad520-68c4-49d0-882a-c08eb6ed0cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079821210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3079821210
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2031424139
Short name T83
Test name
Test status
Simulation time 39869507 ps
CPU time 1.19 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 220172 kb
Host smart-4722e758-9c64-4be9-9d0e-3e72b44290e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031424139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2031424139
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3553776734
Short name T390
Test name
Test status
Simulation time 38735608 ps
CPU time 0.97 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 207324 kb
Host smart-8f2ba165-e136-43fe-9812-cfc8824afafc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553776734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3553776734
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1116184819
Short name T197
Test name
Test status
Simulation time 19336601 ps
CPU time 0.91 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 216740 kb
Host smart-85f4fa31-e981-49e1-96d9-da7d851ce9cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116184819 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1116184819
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.383087969
Short name T629
Test name
Test status
Simulation time 53351271 ps
CPU time 1.17 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 217260 kb
Host smart-d7bfbdd3-9628-4197-bc8a-58adb8273b97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383087969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.383087969
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1106460715
Short name T137
Test name
Test status
Simulation time 24595848 ps
CPU time 1.03 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 219804 kb
Host smart-6f88e73e-e381-4a19-a488-689172892172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106460715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1106460715
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1771286104
Short name T574
Test name
Test status
Simulation time 56049554 ps
CPU time 1.31 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 217668 kb
Host smart-0fabb8e4-1f41-488a-92e3-699e7a18d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771286104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1771286104
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.96406573
Short name T608
Test name
Test status
Simulation time 21086642 ps
CPU time 1.04 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 215860 kb
Host smart-fbadd351-d7cd-424a-9369-cf4584e985eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96406573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.96406573
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3010531565
Short name T656
Test name
Test status
Simulation time 67427284 ps
CPU time 0.92 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 215648 kb
Host smart-f8acedb3-5c0a-47db-92b5-a8c34e693470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010531565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3010531565
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.947817189
Short name T473
Test name
Test status
Simulation time 51479179 ps
CPU time 1.27 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 220420 kb
Host smart-dd5f962c-0b11-43c7-9482-2da3ae7271ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947817189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.947817189
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2531676222
Short name T451
Test name
Test status
Simulation time 106526176475 ps
CPU time 1390.1 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 06:12:24 PM PDT 24
Peak memory 226596 kb
Host smart-edc94c41-f5a9-4cda-abb1-158f1fa825bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531676222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2531676222
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.443327877
Short name T824
Test name
Test status
Simulation time 70407543 ps
CPU time 1.17 seconds
Started Jul 05 05:49:18 PM PDT 24
Finished Jul 05 05:49:20 PM PDT 24
Peak memory 219636 kb
Host smart-ab2191a4-5911-4a09-bfc4-7bedfcc81920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443327877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.443327877
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3273600508
Short name T767
Test name
Test status
Simulation time 79905983 ps
CPU time 0.98 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 206900 kb
Host smart-a7f1be42-536e-4002-8780-0759a9313989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273600508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3273600508
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2123809858
Short name T24
Test name
Test status
Simulation time 17473222 ps
CPU time 0.88 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 216580 kb
Host smart-9b1b81ea-e210-4f29-bd30-5ea622fd4fbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123809858 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2123809858
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3203291388
Short name T794
Test name
Test status
Simulation time 31756402 ps
CPU time 1.08 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 217252 kb
Host smart-51a1ff46-1f72-4837-804d-19d47ab05e17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203291388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3203291388
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1862791188
Short name T647
Test name
Test status
Simulation time 26910869 ps
CPU time 1.35 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 232492 kb
Host smart-d8ffdf13-1129-46bb-bfca-983399503dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862791188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1862791188
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.402571163
Short name T776
Test name
Test status
Simulation time 92635860 ps
CPU time 1.19 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 219812 kb
Host smart-7615409f-8f27-4884-b6f4-a43530090624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402571163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.402571163
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4026892059
Short name T592
Test name
Test status
Simulation time 25676559 ps
CPU time 0.98 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 215792 kb
Host smart-43078dbf-965a-4c37-8675-cafc38b908e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026892059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4026892059
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1829155932
Short name T324
Test name
Test status
Simulation time 20443800 ps
CPU time 0.99 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 215612 kb
Host smart-26a33988-ec30-4aac-96fa-6d22b606ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829155932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1829155932
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2204249585
Short name T601
Test name
Test status
Simulation time 145521960 ps
CPU time 2.11 seconds
Started Jul 05 05:49:10 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 218776 kb
Host smart-78961f0b-34ed-4de8-9d38-a6f1724cdd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204249585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2204249585
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.84898916
Short name T587
Test name
Test status
Simulation time 334621977877 ps
CPU time 1898.09 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 06:20:52 PM PDT 24
Peak memory 227432 kb
Host smart-e9a5d378-d5b4-418c-9042-eb37d896c027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84898916 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.84898916
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2563643726
Short name T646
Test name
Test status
Simulation time 113636961 ps
CPU time 1.21 seconds
Started Jul 05 05:49:14 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 220032 kb
Host smart-18432e54-5f5e-4ed8-be0d-df0c18bf582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563643726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2563643726
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2744115062
Short name T773
Test name
Test status
Simulation time 26099696 ps
CPU time 1.16 seconds
Started Jul 05 05:49:12 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 215284 kb
Host smart-73704496-e49a-40b4-bd37-a9093acfd7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744115062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2744115062
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1680157551
Short name T91
Test name
Test status
Simulation time 23025928 ps
CPU time 0.89 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:17 PM PDT 24
Peak memory 215768 kb
Host smart-da705b5e-81ff-4317-9b94-ef4418f4244d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680157551 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1680157551
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3238620923
Short name T768
Test name
Test status
Simulation time 67625871 ps
CPU time 1.06 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 218500 kb
Host smart-a7ba1b61-4a20-4ad7-b3a5-8d9a3e616831
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238620923 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3238620923
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2825630374
Short name T102
Test name
Test status
Simulation time 46950985 ps
CPU time 1.04 seconds
Started Jul 05 05:49:14 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 219864 kb
Host smart-56c02472-a107-4f51-8fc4-a3a55bd0d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825630374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2825630374
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4108026471
Short name T303
Test name
Test status
Simulation time 51281585 ps
CPU time 1.52 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 218936 kb
Host smart-6f56d4e9-5410-4fc5-93f5-c498e6ba58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108026471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4108026471
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1527658583
Short name T437
Test name
Test status
Simulation time 32601147 ps
CPU time 0.91 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 215812 kb
Host smart-ecd8b98f-573d-4a02-9a9b-64f4274c70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527658583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1527658583
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1964551046
Short name T676
Test name
Test status
Simulation time 35835399 ps
CPU time 0.94 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 215612 kb
Host smart-88c1bb12-e799-43f1-9e6b-023b890694d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964551046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1964551046
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3425155493
Short name T287
Test name
Test status
Simulation time 278545779 ps
CPU time 3.27 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 218836 kb
Host smart-0afa7d72-d9de-45f1-a9d0-dd1db8c7ddf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425155493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3425155493
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2882922876
Short name T494
Test name
Test status
Simulation time 49359561175 ps
CPU time 1209.08 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 06:09:27 PM PDT 24
Peak memory 223308 kb
Host smart-fa634287-89ba-40fa-a91b-355001a779ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882922876 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2882922876
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.251197274
Short name T559
Test name
Test status
Simulation time 28447054 ps
CPU time 1.22 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 220508 kb
Host smart-6377a568-aba1-4f06-804c-16c4a59fc406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251197274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.251197274
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2478796696
Short name T493
Test name
Test status
Simulation time 45885331 ps
CPU time 0.83 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 215248 kb
Host smart-dd3a9a3c-6e3c-4119-b510-9aaedd62d4de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478796696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2478796696
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3324272358
Short name T823
Test name
Test status
Simulation time 40773822 ps
CPU time 0.88 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 216304 kb
Host smart-d56aed7b-8103-4a9b-9d29-da528cccb337
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324272358 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3324272358
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1028502861
Short name T875
Test name
Test status
Simulation time 81340068 ps
CPU time 1.16 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 217332 kb
Host smart-a537436a-fda6-4713-8464-14162223264a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028502861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1028502861
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2246449556
Short name T471
Test name
Test status
Simulation time 20788972 ps
CPU time 1.16 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 220040 kb
Host smart-2e5a6f42-d5f6-4e7c-8958-d5b4338ad8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246449556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2246449556
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_intr.658186018
Short name T748
Test name
Test status
Simulation time 34099214 ps
CPU time 0.95 seconds
Started Jul 05 05:49:13 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 215764 kb
Host smart-0f5d4e93-a18b-4c9a-9fdf-131be9e130ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658186018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.658186018
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1017625542
Short name T325
Test name
Test status
Simulation time 29828371 ps
CPU time 0.91 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 215640 kb
Host smart-fdf8e59e-5305-4fed-b22d-67a22bea33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017625542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1017625542
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2293118122
Short name T500
Test name
Test status
Simulation time 153461075 ps
CPU time 1.53 seconds
Started Jul 05 05:49:17 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 220412 kb
Host smart-9e27fcec-93ab-463a-83ad-6199c483da53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293118122 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2293118122
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.42507694
Short name T541
Test name
Test status
Simulation time 50080933608 ps
CPU time 600.47 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:59:17 PM PDT 24
Peak memory 218416 kb
Host smart-a44bbd2c-c1cf-40ac-95e7-160caf9a2ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42507694 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.42507694
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3019269138
Short name T922
Test name
Test status
Simulation time 30823923 ps
CPU time 1.3 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 216012 kb
Host smart-83d3223d-e411-4521-a3ad-d0aad48bb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019269138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3019269138
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1872232359
Short name T622
Test name
Test status
Simulation time 20116921 ps
CPU time 0.9 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 207048 kb
Host smart-02a940df-d2dc-4d4f-939f-c48f995d6ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872232359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1872232359
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.396901679
Short name T858
Test name
Test status
Simulation time 84770018 ps
CPU time 0.86 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 215732 kb
Host smart-6ea6e4dc-08ff-488b-8afa-a3e8467baecb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396901679 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.396901679
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3202605533
Short name T135
Test name
Test status
Simulation time 46721271 ps
CPU time 1.52 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 217112 kb
Host smart-28ff85b1-168a-4ae0-ad2f-b1bd1a4fd7a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202605533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3202605533
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1606605465
Short name T682
Test name
Test status
Simulation time 42967873 ps
CPU time 1.08 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 219812 kb
Host smart-7169b566-88bc-46cb-ae4e-69a4c61ef9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606605465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1606605465
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1061584259
Short name T885
Test name
Test status
Simulation time 81338242 ps
CPU time 1.22 seconds
Started Jul 05 05:49:15 PM PDT 24
Finished Jul 05 05:49:17 PM PDT 24
Peak memory 220484 kb
Host smart-4e614031-5f3d-4403-8a51-5611218a6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061584259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1061584259
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3939993142
Short name T400
Test name
Test status
Simulation time 26370074 ps
CPU time 1.04 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 224360 kb
Host smart-bb24a3d2-71ad-4ce4-be7a-a0d239d777a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939993142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3939993142
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3968820427
Short name T839
Test name
Test status
Simulation time 16716202 ps
CPU time 1.03 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 215704 kb
Host smart-1b6a4ddb-1f5d-42a0-ae68-f03a15c1ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968820427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3968820427
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2511894785
Short name T60
Test name
Test status
Simulation time 181940456 ps
CPU time 3.72 seconds
Started Jul 05 05:49:14 PM PDT 24
Finished Jul 05 05:49:19 PM PDT 24
Peak memory 220148 kb
Host smart-ce0685f9-3a94-414c-94f4-7b38e353a1c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511894785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2511894785
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3056593374
Short name T765
Test name
Test status
Simulation time 166266042952 ps
CPU time 474.39 seconds
Started Jul 05 05:49:16 PM PDT 24
Finished Jul 05 05:57:11 PM PDT 24
Peak memory 219996 kb
Host smart-e3236a91-3b60-472b-b024-1193aad87602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056593374 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3056593374
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.243897735
Short name T944
Test name
Test status
Simulation time 91944588 ps
CPU time 1.18 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:26 PM PDT 24
Peak memory 219268 kb
Host smart-71da48d2-d917-414d-b052-490543d37016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243897735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.243897735
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3876421763
Short name T614
Test name
Test status
Simulation time 29930970 ps
CPU time 0.93 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 207008 kb
Host smart-5c2347f3-4ac5-4352-9f03-a793aa064fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876421763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3876421763
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1552905098
Short name T709
Test name
Test status
Simulation time 13636478 ps
CPU time 0.93 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:29 PM PDT 24
Peak memory 216836 kb
Host smart-177af653-0693-46b4-a2d5-a22a80129ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552905098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1552905098
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3118405150
Short name T987
Test name
Test status
Simulation time 176005840 ps
CPU time 1.12 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 217256 kb
Host smart-6bd92f05-13a4-4173-954f-e8514c1d2206
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118405150 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3118405150
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1996345024
Short name T867
Test name
Test status
Simulation time 37891753 ps
CPU time 1.15 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 221248 kb
Host smart-9810f8dc-5031-4e82-b341-66e8da6a250e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996345024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1996345024
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1650083290
Short name T665
Test name
Test status
Simulation time 41838813 ps
CPU time 1.58 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:26 PM PDT 24
Peak memory 219972 kb
Host smart-443dd398-2bf3-43fe-9a85-23e41844d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650083290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1650083290
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.2334697420
Short name T625
Test name
Test status
Simulation time 138449219 ps
CPU time 0.97 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:26 PM PDT 24
Peak memory 215592 kb
Host smart-aeba01bb-c9a4-46b6-97a6-1897e1fba10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334697420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2334697420
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1716513080
Short name T550
Test name
Test status
Simulation time 394348693 ps
CPU time 1.55 seconds
Started Jul 05 05:49:27 PM PDT 24
Finished Jul 05 05:49:29 PM PDT 24
Peak memory 217508 kb
Host smart-2a8708f6-162c-4c1d-8183-cce50e94876c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716513080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1716513080
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2329657373
Short name T930
Test name
Test status
Simulation time 98079173562 ps
CPU time 484.49 seconds
Started Jul 05 05:49:19 PM PDT 24
Finished Jul 05 05:57:25 PM PDT 24
Peak memory 219460 kb
Host smart-8ad41724-07b3-4376-b67c-2eac7b65abd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329657373 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2329657373
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.394336471
Short name T98
Test name
Test status
Simulation time 46717764 ps
CPU time 1.23 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 220112 kb
Host smart-55af3c56-e658-43ab-b85e-08e4151f408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394336471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.394336471
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.89172179
Short name T363
Test name
Test status
Simulation time 26297559 ps
CPU time 0.91 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 207044 kb
Host smart-3b6acef8-ffa5-4d13-9e71-e417cd70d8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89172179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.89172179
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.591313295
Short name T516
Test name
Test status
Simulation time 12918976 ps
CPU time 0.93 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 216704 kb
Host smart-573e4683-82cb-4728-bdf6-ec54e31be8ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591313295 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.591313295
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.657308160
Short name T800
Test name
Test status
Simulation time 107283755 ps
CPU time 1.07 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 217280 kb
Host smart-bef0a7e8-7764-4482-8bb5-c8afb72df6ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657308160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.657308160
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2584838047
Short name T59
Test name
Test status
Simulation time 18430831 ps
CPU time 1.14 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 224376 kb
Host smart-f5e19c9f-b506-4120-88c1-fd5efc4c46aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584838047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2584838047
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1489207501
Short name T694
Test name
Test status
Simulation time 39797650 ps
CPU time 1.36 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 217628 kb
Host smart-f4693d9b-18bb-4d80-90d9-4524ecb9f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489207501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1489207501
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3287280736
Short name T964
Test name
Test status
Simulation time 20547651 ps
CPU time 1.08 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 217056 kb
Host smart-58d1ea07-7244-451c-876c-9fb54ae95220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287280736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3287280736
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2393635794
Short name T332
Test name
Test status
Simulation time 40677451 ps
CPU time 0.94 seconds
Started Jul 05 05:49:21 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 215616 kb
Host smart-f56252a9-f924-4b38-8985-9266d33abbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393635794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2393635794
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3096754793
Short name T223
Test name
Test status
Simulation time 76935453 ps
CPU time 1.46 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 217688 kb
Host smart-a7a3a43f-9497-4258-980e-e3faa069bda2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096754793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3096754793
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1712234172
Short name T833
Test name
Test status
Simulation time 94376047626 ps
CPU time 540.39 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:58:24 PM PDT 24
Peak memory 219832 kb
Host smart-02e6e14c-a0ee-47ce-915f-d43525f3df84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712234172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1712234172
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.171874632
Short name T279
Test name
Test status
Simulation time 28786134 ps
CPU time 1.28 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 219804 kb
Host smart-4caba07d-7835-4297-b907-133233807dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171874632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.171874632
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3000788162
Short name T528
Test name
Test status
Simulation time 59797102 ps
CPU time 0.83 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 206764 kb
Host smart-8dbfdeb9-5684-444d-a586-947eec3ee89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000788162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3000788162
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3273148432
Short name T631
Test name
Test status
Simulation time 12229692 ps
CPU time 0.9 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 216792 kb
Host smart-270c1611-4df6-49f6-83c8-7a3d573f5e06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273148432 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3273148432
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3408593349
Short name T97
Test name
Test status
Simulation time 64354247 ps
CPU time 1.04 seconds
Started Jul 05 05:49:27 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 218948 kb
Host smart-11a3685d-2549-4a5d-93f8-e2f9b3fe2de8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408593349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3408593349
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2590732612
Short name T819
Test name
Test status
Simulation time 32273230 ps
CPU time 1.02 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 218792 kb
Host smart-6d854777-c08f-4fc8-a2c2-6d6c4e842486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590732612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2590732612
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.970578861
Short name T263
Test name
Test status
Simulation time 47377765 ps
CPU time 1.03 seconds
Started Jul 05 05:49:25 PM PDT 24
Finished Jul 05 05:49:27 PM PDT 24
Peak memory 217768 kb
Host smart-3ee5bf15-7178-4d2a-ad1e-58d66f0d4ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970578861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.970578861
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.691354380
Short name T782
Test name
Test status
Simulation time 21391403 ps
CPU time 1.25 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 224336 kb
Host smart-109569b1-c3ea-45a1-a3a7-17b9261e04ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691354380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.691354380
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2820693997
Short name T429
Test name
Test status
Simulation time 28237003 ps
CPU time 1.03 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 215640 kb
Host smart-7c3c7521-8840-4a87-9f42-b4ef41178c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820693997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2820693997
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.856015806
Short name T179
Test name
Test status
Simulation time 264611773 ps
CPU time 1.96 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:26 PM PDT 24
Peak memory 215672 kb
Host smart-9feb577e-cbaa-4fa1-810f-90b6c429140f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856015806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.856015806
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.485932409
Short name T952
Test name
Test status
Simulation time 26461229493 ps
CPU time 575 seconds
Started Jul 05 05:49:29 PM PDT 24
Finished Jul 05 05:59:05 PM PDT 24
Peak memory 218380 kb
Host smart-a02fd50e-1a02-4fd4-af04-dd2c9df7dae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485932409 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.485932409
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1405458789
Short name T20
Test name
Test status
Simulation time 87478065 ps
CPU time 1.27 seconds
Started Jul 05 05:47:54 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 218732 kb
Host smart-a0e1190d-7418-4793-9f77-bb3e41f12685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405458789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1405458789
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4015842363
Short name T462
Test name
Test status
Simulation time 24199165 ps
CPU time 0.96 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 215212 kb
Host smart-c61a8142-2aa4-42a3-939a-7c2694442fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015842363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4015842363
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4213488637
Short name T210
Test name
Test status
Simulation time 30491028 ps
CPU time 0.85 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 05:47:54 PM PDT 24
Peak memory 215704 kb
Host smart-ebbbc79e-6056-4528-b333-4c5671381cad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213488637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4213488637
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1076682543
Short name T509
Test name
Test status
Simulation time 41008985 ps
CPU time 1.29 seconds
Started Jul 05 05:47:57 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 217220 kb
Host smart-f4ed1c92-89d5-4c51-9e50-fd80973040c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076682543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1076682543
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4032609955
Short name T442
Test name
Test status
Simulation time 51171657 ps
CPU time 1.01 seconds
Started Jul 05 05:47:51 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 218996 kb
Host smart-bd481635-593e-4be0-bc96-ce47455bfb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032609955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4032609955
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.809327834
Short name T67
Test name
Test status
Simulation time 317484198 ps
CPU time 1.75 seconds
Started Jul 05 05:47:56 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 219088 kb
Host smart-447246ca-9655-40c5-8868-d296c2da1fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809327834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.809327834
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3968011977
Short name T385
Test name
Test status
Simulation time 28411425 ps
CPU time 0.96 seconds
Started Jul 05 05:47:53 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 215696 kb
Host smart-ba9f7fb6-bc0d-44ce-a929-ba851ae03868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968011977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3968011977
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2157052307
Short name T650
Test name
Test status
Simulation time 28040639 ps
CPU time 0.98 seconds
Started Jul 05 05:47:57 PM PDT 24
Finished Jul 05 05:47:59 PM PDT 24
Peak memory 207444 kb
Host smart-62c2063f-2f0f-4a0b-8885-281fcf0e036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157052307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2157052307
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.939426198
Short name T609
Test name
Test status
Simulation time 49291696 ps
CPU time 0.9 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 215612 kb
Host smart-40661f1c-fe1f-43ee-bdd7-9b10b108d8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939426198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.939426198
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2317689488
Short name T375
Test name
Test status
Simulation time 301410566 ps
CPU time 6.51 seconds
Started Jul 05 05:47:56 PM PDT 24
Finished Jul 05 05:48:03 PM PDT 24
Peak memory 217668 kb
Host smart-ec330212-52f4-46b5-8483-510dd90199d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317689488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2317689488
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.251509795
Short name T212
Test name
Test status
Simulation time 191551467668 ps
CPU time 1016.08 seconds
Started Jul 05 05:47:58 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 222768 kb
Host smart-284afa79-4a6e-4b3e-a499-15200f377575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251509795 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.251509795
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.4273197949
Short name T284
Test name
Test status
Simulation time 24990350 ps
CPU time 1.27 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 220072 kb
Host smart-a701fdb7-c2f1-4fb8-9030-252ed6c660f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273197949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.4273197949
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3465140402
Short name T118
Test name
Test status
Simulation time 98444416 ps
CPU time 1.06 seconds
Started Jul 05 05:49:23 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 220988 kb
Host smart-680f35bb-aa1d-4e9d-9004-c248b969699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465140402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3465140402
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3635334856
Short name T520
Test name
Test status
Simulation time 40232634 ps
CPU time 1.25 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:26 PM PDT 24
Peak memory 218976 kb
Host smart-7cc824e7-9398-4043-a567-6259fda24069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635334856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3635334856
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2507798600
Short name T352
Test name
Test status
Simulation time 270490471 ps
CPU time 1.14 seconds
Started Jul 05 05:49:20 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 218824 kb
Host smart-3be85d1e-8c81-437f-aee0-5ae8ad354fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507798600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2507798600
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.434499849
Short name T164
Test name
Test status
Simulation time 31825978 ps
CPU time 0.88 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:25 PM PDT 24
Peak memory 218632 kb
Host smart-2f7a3536-dac5-4041-b126-c0a5adb2f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434499849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.434499849
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.961210574
Short name T853
Test name
Test status
Simulation time 81999525 ps
CPU time 2.88 seconds
Started Jul 05 05:49:24 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 219008 kb
Host smart-1071857b-ebf4-42d4-aa16-8eb862b0665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961210574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.961210574
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.860822824
Short name T973
Test name
Test status
Simulation time 41184832 ps
CPU time 1.12 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:29 PM PDT 24
Peak memory 221032 kb
Host smart-68dd7605-af86-4c80-b6da-8459c77dabea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860822824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.860822824
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1399177842
Short name T103
Test name
Test status
Simulation time 19861668 ps
CPU time 1.37 seconds
Started Jul 05 05:49:26 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 229912 kb
Host smart-1ca36ce0-c4bb-4d72-a346-f646a5ff9c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399177842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1399177842
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2680735152
Short name T10
Test name
Test status
Simulation time 33760120 ps
CPU time 1.39 seconds
Started Jul 05 05:49:26 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 220244 kb
Host smart-300a7542-4d42-40af-9efc-d9914e84f7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680735152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2680735152
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1266079013
Short name T540
Test name
Test status
Simulation time 77908862 ps
CPU time 1.19 seconds
Started Jul 05 05:49:22 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 220656 kb
Host smart-b3237ebd-78f5-4200-968f-50931d8aa574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266079013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1266079013
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1962453544
Short name T53
Test name
Test status
Simulation time 21237307 ps
CPU time 1.12 seconds
Started Jul 05 05:49:29 PM PDT 24
Finished Jul 05 05:49:31 PM PDT 24
Peak memory 224232 kb
Host smart-38729d6f-8acd-4d3d-a232-ee8f7f120444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962453544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1962453544
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2965798698
Short name T225
Test name
Test status
Simulation time 75992196 ps
CPU time 1.32 seconds
Started Jul 05 05:49:26 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 219116 kb
Host smart-925946eb-3d58-42e3-acfd-f178afc20ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965798698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2965798698
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3915648569
Short name T172
Test name
Test status
Simulation time 64371665 ps
CPU time 1.14 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 219720 kb
Host smart-cc84a01b-4447-4fd7-9b37-11bec04d1c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915648569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3915648569
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.983448713
Short name T165
Test name
Test status
Simulation time 23054983 ps
CPU time 1.06 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:35 PM PDT 24
Peak memory 224296 kb
Host smart-b9b8e151-75f6-409a-9c00-8e9ce69906e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983448713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.983448713
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_alert.2316338977
Short name T117
Test name
Test status
Simulation time 75924337 ps
CPU time 1.27 seconds
Started Jul 05 05:49:32 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 218856 kb
Host smart-f43f1266-f6d9-441a-984c-5510bd15325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316338977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2316338977
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1371294226
Short name T913
Test name
Test status
Simulation time 22628837 ps
CPU time 1.07 seconds
Started Jul 05 05:49:27 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 224280 kb
Host smart-323cd0ef-f567-4d2b-ad91-5c7f0df0525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371294226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1371294226
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4158587642
Short name T343
Test name
Test status
Simulation time 40215415 ps
CPU time 1.39 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 218924 kb
Host smart-7ea543de-93c6-452f-aae3-5a7259444328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158587642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4158587642
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.4100865894
Short name T81
Test name
Test status
Simulation time 28664449 ps
CPU time 1.27 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 220044 kb
Host smart-7414831f-2bf1-4555-ade2-7a1b30d451f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100865894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.4100865894
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1925559101
Short name T55
Test name
Test status
Simulation time 22298162 ps
CPU time 1.03 seconds
Started Jul 05 05:49:31 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 224312 kb
Host smart-767efb8e-0f70-463f-ae35-b95ca50396cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925559101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1925559101
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1004308018
Short name T990
Test name
Test status
Simulation time 67849695 ps
CPU time 1.07 seconds
Started Jul 05 05:49:29 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 217652 kb
Host smart-eb1600e1-1666-4e5a-b7e2-04d0b6ca3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004308018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1004308018
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.4252808648
Short name T158
Test name
Test status
Simulation time 22478824 ps
CPU time 1.12 seconds
Started Jul 05 05:49:29 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 220104 kb
Host smart-815a7f39-3b1b-43c3-b55f-344614dca505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252808648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.4252808648
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2743042353
Short name T899
Test name
Test status
Simulation time 23895168 ps
CPU time 1.14 seconds
Started Jul 05 05:49:33 PM PDT 24
Finished Jul 05 05:49:35 PM PDT 24
Peak memory 218880 kb
Host smart-aec4665a-0d32-4071-bce6-5f886752a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743042353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2743042353
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3916794048
Short name T348
Test name
Test status
Simulation time 94448053 ps
CPU time 1.1 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 217568 kb
Host smart-64c2afa9-39fe-4bc7-9cc6-f3085138dd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916794048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3916794048
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1798235207
Short name T419
Test name
Test status
Simulation time 40197783 ps
CPU time 1.09 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 219264 kb
Host smart-2129ab32-70e9-43d0-9733-e1703b39e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798235207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1798235207
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.209427937
Short name T110
Test name
Test status
Simulation time 31911294 ps
CPU time 1.18 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 217568 kb
Host smart-440054f0-fbc6-4cee-bf60-f1e335f578e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209427937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.209427937
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3981907580
Short name T981
Test name
Test status
Simulation time 114851273 ps
CPU time 2.56 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 218872 kb
Host smart-08d52b92-87d9-4274-a381-da63f8e4ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981907580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3981907580
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.4055954904
Short name T648
Test name
Test status
Simulation time 76504839 ps
CPU time 1.27 seconds
Started Jul 05 05:49:28 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 220704 kb
Host smart-2c2842bd-d2ec-4d61-816f-978039cb37ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055954904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.4055954904
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2101300699
Short name T426
Test name
Test status
Simulation time 18034263 ps
CPU time 1.02 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:32 PM PDT 24
Peak memory 218840 kb
Host smart-76959e43-baea-4cf3-a74d-791d825d9bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101300699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2101300699
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3094342979
Short name T680
Test name
Test status
Simulation time 48841489 ps
CPU time 1.59 seconds
Started Jul 05 05:49:26 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 218640 kb
Host smart-c7b4ae72-b3a3-47b2-b3c3-f0e04d8780fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094342979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3094342979
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3026886281
Short name T258
Test name
Test status
Simulation time 45685422 ps
CPU time 1.24 seconds
Started Jul 05 05:48:02 PM PDT 24
Finished Jul 05 05:48:04 PM PDT 24
Peak memory 219076 kb
Host smart-88ca7740-6b34-4f5b-972a-fde48b354645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026886281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3026886281
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.757872160
Short name T895
Test name
Test status
Simulation time 86382203 ps
CPU time 0.82 seconds
Started Jul 05 05:48:04 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 207044 kb
Host smart-f34a1c94-2d92-43f6-95f0-313a31cabc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757872160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.757872160
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1468475217
Short name T597
Test name
Test status
Simulation time 10893922 ps
CPU time 0.9 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:05 PM PDT 24
Peak memory 216328 kb
Host smart-36fb108e-e5d0-4b7d-82d2-024144a5eff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468475217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1468475217
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1324592331
Short name T142
Test name
Test status
Simulation time 127784574 ps
CPU time 1.28 seconds
Started Jul 05 05:48:05 PM PDT 24
Finished Jul 05 05:48:07 PM PDT 24
Peak memory 217152 kb
Host smart-d629d908-093e-4298-a9de-4d9447529715
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324592331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1324592331
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3115564254
Short name T739
Test name
Test status
Simulation time 26830508 ps
CPU time 0.85 seconds
Started Jul 05 05:48:05 PM PDT 24
Finished Jul 05 05:48:07 PM PDT 24
Peak memory 218492 kb
Host smart-a41da848-7b2a-45c4-8ee8-250c5b7768b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115564254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3115564254
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3107482860
Short name T851
Test name
Test status
Simulation time 74865304 ps
CPU time 1.57 seconds
Started Jul 05 05:47:58 PM PDT 24
Finished Jul 05 05:48:00 PM PDT 24
Peak memory 220556 kb
Host smart-7072a6db-4ef0-4b5d-a513-12979a86cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107482860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3107482860
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.920334994
Short name T175
Test name
Test status
Simulation time 47399101 ps
CPU time 0.93 seconds
Started Jul 05 05:48:04 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 215740 kb
Host smart-94c8767b-7143-4034-8f93-4d1c74a52c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920334994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.920334994
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3518120385
Short name T272
Test name
Test status
Simulation time 17867504 ps
CPU time 1.06 seconds
Started Jul 05 05:47:55 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 207528 kb
Host smart-45e7789a-507c-4d7f-b9a1-7675ec9a40e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518120385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3518120385
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1730228304
Short name T327
Test name
Test status
Simulation time 89496149 ps
CPU time 0.88 seconds
Started Jul 05 05:47:57 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 215480 kb
Host smart-7819c7ac-4b4d-4f38-85a2-088916a39c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730228304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1730228304
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2756555924
Short name T391
Test name
Test status
Simulation time 211568027 ps
CPU time 4.4 seconds
Started Jul 05 05:48:02 PM PDT 24
Finished Jul 05 05:48:07 PM PDT 24
Peak memory 218656 kb
Host smart-1bc19900-aa3f-49fe-82bf-dea58ea9899b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756555924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2756555924
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3375064240
Short name T908
Test name
Test status
Simulation time 546577377816 ps
CPU time 1532.87 seconds
Started Jul 05 05:48:06 PM PDT 24
Finished Jul 05 06:13:39 PM PDT 24
Peak memory 227772 kb
Host smart-5e4ae7cc-74c7-4503-b057-0235b7b3db1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375064240 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3375064240
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1151379143
Short name T657
Test name
Test status
Simulation time 323003866 ps
CPU time 1.29 seconds
Started Jul 05 05:49:27 PM PDT 24
Finished Jul 05 05:49:29 PM PDT 24
Peak memory 221020 kb
Host smart-8ef24b63-1e4f-45e2-b866-282ecbe609be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151379143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1151379143
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.572903067
Short name T837
Test name
Test status
Simulation time 44245572 ps
CPU time 1.15 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:32 PM PDT 24
Peak memory 219932 kb
Host smart-f7579160-35df-4ed6-9d67-879fbe8d726d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572903067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.572903067
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2654289458
Short name T732
Test name
Test status
Simulation time 47257325 ps
CPU time 1.71 seconds
Started Jul 05 05:49:31 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 220476 kb
Host smart-3a0ce1c4-5132-4bac-8243-04d123d1def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654289458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2654289458
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1782432193
Short name T477
Test name
Test status
Simulation time 52798206 ps
CPU time 1.25 seconds
Started Jul 05 05:49:33 PM PDT 24
Finished Jul 05 05:49:35 PM PDT 24
Peak memory 216008 kb
Host smart-53fa6cfb-2acc-4298-92dc-01ee1879f828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782432193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1782432193
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2590212134
Short name T939
Test name
Test status
Simulation time 42448350 ps
CPU time 1.01 seconds
Started Jul 05 05:50:14 PM PDT 24
Finished Jul 05 05:50:17 PM PDT 24
Peak memory 219056 kb
Host smart-dd90db63-89fa-4ffb-a710-9c997452cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590212134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2590212134
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1837389129
Short name T737
Test name
Test status
Simulation time 112455832 ps
CPU time 1.34 seconds
Started Jul 05 05:49:32 PM PDT 24
Finished Jul 05 05:49:34 PM PDT 24
Peak memory 217548 kb
Host smart-4223ff72-42d9-4796-8747-0cf86ac83e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837389129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1837389129
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3537394958
Short name T257
Test name
Test status
Simulation time 284945112 ps
CPU time 1.23 seconds
Started Jul 05 05:49:32 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 220000 kb
Host smart-5ff1f31b-6099-45a6-bf87-f92ecd42e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537394958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3537394958
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.4108128625
Short name T525
Test name
Test status
Simulation time 32936040 ps
CPU time 1.04 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:31 PM PDT 24
Peak memory 220248 kb
Host smart-bfd37534-5d2e-40dc-9019-1a2f60abeeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108128625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.4108128625
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.602574234
Short name T642
Test name
Test status
Simulation time 40428826 ps
CPU time 1.58 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:32 PM PDT 24
Peak memory 218972 kb
Host smart-b1289c0a-12a1-4a32-938d-f183f502bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602574234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.602574234
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1600054307
Short name T578
Test name
Test status
Simulation time 77273240 ps
CPU time 1.17 seconds
Started Jul 05 05:49:26 PM PDT 24
Finished Jul 05 05:49:28 PM PDT 24
Peak memory 218960 kb
Host smart-f0672e37-5563-4cd3-9d5c-2aa939bc4be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600054307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1600054307
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.615682079
Short name T789
Test name
Test status
Simulation time 34877431 ps
CPU time 0.94 seconds
Started Jul 05 05:49:31 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 220028 kb
Host smart-45ee9727-f92d-42c3-874e-a77492911333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615682079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.615682079
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4153135423
Short name T22
Test name
Test status
Simulation time 29962174 ps
CPU time 1.2 seconds
Started Jul 05 05:49:30 PM PDT 24
Finished Jul 05 05:49:32 PM PDT 24
Peak memory 219064 kb
Host smart-97ffb6f6-012a-4aac-9b5c-10d1f1fd3d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153135423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4153135423
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1830418365
Short name T280
Test name
Test status
Simulation time 30030713 ps
CPU time 1.25 seconds
Started Jul 05 05:49:43 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 220092 kb
Host smart-a4f91781-af07-447d-ac8d-4d74a98482a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830418365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1830418365
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3799771571
Short name T395
Test name
Test status
Simulation time 22021869 ps
CPU time 0.9 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 218360 kb
Host smart-c4882c52-4763-4adc-b336-542bdd630c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799771571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3799771571
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4044393218
Short name T693
Test name
Test status
Simulation time 129347220 ps
CPU time 1.52 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 218832 kb
Host smart-24e00691-89ad-4016-ad63-2b9c41014df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044393218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4044393218
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2425480789
Short name T723
Test name
Test status
Simulation time 107259450 ps
CPU time 1.1 seconds
Started Jul 05 05:49:39 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 219696 kb
Host smart-50580049-3b1e-48c4-b97e-76f684880622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425480789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2425480789
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4060484321
Short name T795
Test name
Test status
Simulation time 34409665 ps
CPU time 0.84 seconds
Started Jul 05 05:49:39 PM PDT 24
Finished Jul 05 05:49:41 PM PDT 24
Peak memory 218620 kb
Host smart-133adff0-c493-458c-a719-d3141baeeb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060484321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4060484321
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.716639943
Short name T962
Test name
Test status
Simulation time 114443711 ps
CPU time 1.67 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 219136 kb
Host smart-95c81ecc-901f-4ac9-a63a-cbc2a729134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716639943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.716639943
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4149867910
Short name T475
Test name
Test status
Simulation time 231929349 ps
CPU time 1.39 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 222124 kb
Host smart-2367f891-8f93-4972-aa87-f8162844285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149867910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4149867910
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.1245726828
Short name T672
Test name
Test status
Simulation time 86100588 ps
CPU time 1.17 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 217640 kb
Host smart-a7f66bb2-79dc-4ada-a16f-8ac7dc7009ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245726828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1245726828
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1980960807
Short name T881
Test name
Test status
Simulation time 78892072 ps
CPU time 1.07 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 219988 kb
Host smart-17ce1f27-36e0-4860-b984-3d583c4a7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980960807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1980960807
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_alert.3946770258
Short name T551
Test name
Test status
Simulation time 78791184 ps
CPU time 1.21 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 218916 kb
Host smart-8a52be1c-61b9-4ef0-b3d9-2084729b936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946770258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3946770258
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1306103938
Short name T659
Test name
Test status
Simulation time 22064736 ps
CPU time 0.98 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 218176 kb
Host smart-0fa400e6-c229-4e6e-a42e-e5d38bc5725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306103938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1306103938
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4038084696
Short name T869
Test name
Test status
Simulation time 247721483 ps
CPU time 1.26 seconds
Started Jul 05 05:49:32 PM PDT 24
Finished Jul 05 05:49:34 PM PDT 24
Peak memory 219548 kb
Host smart-521a1e9b-9bb8-46b4-820e-fdc7a2f07e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038084696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4038084696
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3276265444
Short name T677
Test name
Test status
Simulation time 22980487 ps
CPU time 1.13 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:48 PM PDT 24
Peak memory 218752 kb
Host smart-0b2b1460-1286-4b92-9a7a-a4123d483dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276265444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3276265444
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3377278580
Short name T329
Test name
Test status
Simulation time 23498225 ps
CPU time 1.12 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 220184 kb
Host smart-5606f9e1-3f64-4e51-80fe-6fe866484651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377278580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3377278580
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1395268798
Short name T468
Test name
Test status
Simulation time 116861806 ps
CPU time 1.15 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 219248 kb
Host smart-6c414736-7db3-4a1b-8004-bd0f67629a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395268798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1395268798
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3346912337
Short name T545
Test name
Test status
Simulation time 42770005 ps
CPU time 1.2 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:05 PM PDT 24
Peak memory 218920 kb
Host smart-7e3e1a3d-13d6-44fc-b6ed-9f71614ff0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346912337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3346912337
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2631663964
Short name T681
Test name
Test status
Simulation time 71044807 ps
CPU time 1.8 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 207204 kb
Host smart-b3a8456d-6c1c-4ac2-9139-4acd081c837a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631663964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2631663964
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.754643797
Short name T193
Test name
Test status
Simulation time 12241867 ps
CPU time 0.87 seconds
Started Jul 05 05:48:02 PM PDT 24
Finished Jul 05 05:48:04 PM PDT 24
Peak memory 216672 kb
Host smart-9232a271-a0c0-4aff-86d8-88b0ef97fe7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754643797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.754643797
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3692037634
Short name T188
Test name
Test status
Simulation time 46054604 ps
CPU time 1.04 seconds
Started Jul 05 05:48:04 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 217200 kb
Host smart-133cfe3c-0c43-4d3f-82bb-4495f536b7f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692037634 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3692037634
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2059523518
Short name T848
Test name
Test status
Simulation time 23254849 ps
CPU time 0.96 seconds
Started Jul 05 05:48:02 PM PDT 24
Finished Jul 05 05:48:04 PM PDT 24
Peak memory 218532 kb
Host smart-01633a68-ee60-477d-9508-6c3cbcc406f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059523518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2059523518
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.286824884
Short name T818
Test name
Test status
Simulation time 131686256 ps
CPU time 1.04 seconds
Started Jul 05 05:48:00 PM PDT 24
Finished Jul 05 05:48:02 PM PDT 24
Peak memory 217608 kb
Host smart-bedb92ef-6efe-4c96-98c9-3e8d3299d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286824884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.286824884
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1304946653
Short name T636
Test name
Test status
Simulation time 24863276 ps
CPU time 0.95 seconds
Started Jul 05 05:48:04 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 215832 kb
Host smart-24cc14bf-fccf-4608-a3d6-380f906fb983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304946653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1304946653
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.291606369
Short name T27
Test name
Test status
Simulation time 20391935 ps
CPU time 1.03 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:05 PM PDT 24
Peak memory 207416 kb
Host smart-583e6a6e-4a21-450b-abbb-5925cb3ba3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291606369 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.291606369
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1099646922
Short name T452
Test name
Test status
Simulation time 16756715 ps
CPU time 0.99 seconds
Started Jul 05 05:48:02 PM PDT 24
Finished Jul 05 05:48:03 PM PDT 24
Peak memory 215572 kb
Host smart-33ce3e00-b491-4b86-994e-59c277c1ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099646922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1099646922
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1623765665
Short name T1
Test name
Test status
Simulation time 121069469 ps
CPU time 1.78 seconds
Started Jul 05 05:48:05 PM PDT 24
Finished Jul 05 05:48:08 PM PDT 24
Peak memory 217544 kb
Host smart-c593e87c-bbea-4116-925a-5a9a91ec941f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623765665 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1623765665
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1249729886
Short name T649
Test name
Test status
Simulation time 110743674220 ps
CPU time 401.53 seconds
Started Jul 05 05:48:05 PM PDT 24
Finished Jul 05 05:54:47 PM PDT 24
Peak memory 224120 kb
Host smart-e2c9a208-7ace-4297-bd41-4b083daf5c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249729886 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1249729886
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1438867765
Short name T679
Test name
Test status
Simulation time 23178842 ps
CPU time 1.21 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 220300 kb
Host smart-001d0dcd-9fe1-434b-acf5-315a0ff58834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438867765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1438867765
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3296560459
Short name T801
Test name
Test status
Simulation time 18481990 ps
CPU time 1.07 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 218456 kb
Host smart-b3dac8d4-1914-4650-98e4-9cf36f3f0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296560459 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3296560459
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1170321856
Short name T401
Test name
Test status
Simulation time 73504555 ps
CPU time 2.61 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:43 PM PDT 24
Peak memory 218972 kb
Host smart-4b4e8d1f-084d-4368-b75b-adf4a49107ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170321856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1170321856
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.448307373
Short name T670
Test name
Test status
Simulation time 46295511 ps
CPU time 1.23 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 218848 kb
Host smart-d2be7e3a-18e0-4971-a0d4-5b219bd3d593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448307373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.448307373
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2329125482
Short name T104
Test name
Test status
Simulation time 35685223 ps
CPU time 1.13 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 229992 kb
Host smart-a77c5990-e502-4ec1-bbe6-ae16de042813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329125482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2329125482
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2625706804
Short name T478
Test name
Test status
Simulation time 30591103 ps
CPU time 1.36 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 218736 kb
Host smart-8daf8809-d52f-43b4-95cb-9db5c9987b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625706804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2625706804
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2330280924
Short name T229
Test name
Test status
Simulation time 88206666 ps
CPU time 1.19 seconds
Started Jul 05 05:49:39 PM PDT 24
Finished Jul 05 05:49:41 PM PDT 24
Peak memory 219700 kb
Host smart-82f76039-22b4-4a93-899d-77434d552500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330280924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2330280924
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2417640376
Short name T198
Test name
Test status
Simulation time 18941961 ps
CPU time 1.15 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 220088 kb
Host smart-df43faf6-be55-4b38-8623-e95c58e3ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417640376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2417640376
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.583857947
Short name T683
Test name
Test status
Simulation time 76244581 ps
CPU time 1.32 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 217584 kb
Host smart-bb302adc-551f-4901-998e-859b37b8a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583857947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.583857947
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3037911321
Short name T204
Test name
Test status
Simulation time 26372287 ps
CPU time 1.2 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 215968 kb
Host smart-0153e0ee-ff98-4ac5-b494-c7da0b513a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037911321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3037911321
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2067275662
Short name T756
Test name
Test status
Simulation time 57929901 ps
CPU time 0.82 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:48 PM PDT 24
Peak memory 218668 kb
Host smart-8f0d34a1-8eda-4094-b73e-8895c9753761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067275662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2067275662
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1320889906
Short name T813
Test name
Test status
Simulation time 40250283 ps
CPU time 1.46 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 218864 kb
Host smart-d4b98435-a13d-4db7-a9c6-219f51d17a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320889906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1320889906
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.4167366963
Short name T979
Test name
Test status
Simulation time 24404106 ps
CPU time 1.31 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 219116 kb
Host smart-fdd0fa2d-0166-4c12-9d3f-ebb08c67efbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167366963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4167366963
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1670953943
Short name T460
Test name
Test status
Simulation time 72304448 ps
CPU time 0.95 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 218844 kb
Host smart-b78b5f19-3ba1-41b3-8251-2b94ce05c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670953943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1670953943
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2498514385
Short name T470
Test name
Test status
Simulation time 115999167 ps
CPU time 1.39 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 219456 kb
Host smart-443bdd02-ce30-497d-b9e9-c3feaa7f3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498514385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2498514385
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1618579652
Short name T814
Test name
Test status
Simulation time 95729674 ps
CPU time 1.2 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 219780 kb
Host smart-d5c46b6b-8d47-42a5-a322-fefdec70a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618579652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1618579652
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2798203774
Short name T993
Test name
Test status
Simulation time 22230065 ps
CPU time 1.16 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 218784 kb
Host smart-3471f88a-c459-4309-9722-12ba9e0b9797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798203774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2798203774
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1019968752
Short name T878
Test name
Test status
Simulation time 100856513 ps
CPU time 1.32 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 218872 kb
Host smart-0d936591-b28e-4813-84fc-26ff3ea5604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019968752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1019968752
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.600045648
Short name T85
Test name
Test status
Simulation time 72442819 ps
CPU time 1.16 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 219916 kb
Host smart-a31a6b96-efc3-4f4e-8fe4-0024ee144123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600045648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.600045648
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.643983982
Short name T138
Test name
Test status
Simulation time 28739324 ps
CPU time 0.96 seconds
Started Jul 05 05:49:35 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 219860 kb
Host smart-4d69b728-5316-49a4-9e79-f708fe3d6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643983982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.643983982
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.464770981
Short name T554
Test name
Test status
Simulation time 114369379 ps
CPU time 1.4 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 218716 kb
Host smart-a5b33002-cbf0-4ba0-adfb-9d604941c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464770981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.464770981
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2502737208
Short name T726
Test name
Test status
Simulation time 35817573 ps
CPU time 1.19 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 219736 kb
Host smart-5b54015b-c745-4578-80dd-d89598ab8bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502737208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2502737208
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.4183996127
Short name T120
Test name
Test status
Simulation time 23505884 ps
CPU time 0.98 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 219968 kb
Host smart-717cbc71-357c-4c01-ad48-e6c816201412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183996127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4183996127
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_alert.2568420005
Short name T161
Test name
Test status
Simulation time 50443816 ps
CPU time 1.14 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 219636 kb
Host smart-d421496f-5a4c-414a-afac-8de698e8aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568420005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2568420005
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1829562089
Short name T846
Test name
Test status
Simulation time 23968159 ps
CPU time 0.98 seconds
Started Jul 05 05:49:37 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 218744 kb
Host smart-a911cdac-1054-4256-997c-7875ce9e498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829562089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1829562089
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1985332874
Short name T888
Test name
Test status
Simulation time 51731545 ps
CPU time 1.29 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 219608 kb
Host smart-f4559e86-d6a7-4709-8fa1-899d1b1e34bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985332874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1985332874
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3309497882
Short name T750
Test name
Test status
Simulation time 43963002 ps
CPU time 1.15 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 219032 kb
Host smart-d7aae8ea-12bc-4f5b-bf15-3e366eb431e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309497882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3309497882
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1137157010
Short name T129
Test name
Test status
Simulation time 24267479 ps
CPU time 1.3 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:38 PM PDT 24
Peak memory 224308 kb
Host smart-3146539c-0628-4cf5-8e82-9352c596cbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137157010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1137157010
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3420909870
Short name T907
Test name
Test status
Simulation time 83027692 ps
CPU time 1.36 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 217720 kb
Host smart-8c9c12d7-2bb3-4128-b998-f059aa183ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420909870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3420909870
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2823455575
Short name T148
Test name
Test status
Simulation time 29833291 ps
CPU time 1.3 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 219968 kb
Host smart-181d7111-5a1e-4d38-9ed0-bdbd3255884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823455575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2823455575
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1822872775
Short name T497
Test name
Test status
Simulation time 81909493 ps
CPU time 1 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 207076 kb
Host smart-eaa4fac6-cac5-45cb-9cfe-ac2a638b9d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822872775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1822872775
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.151740817
Short name T862
Test name
Test status
Simulation time 13514462 ps
CPU time 0.9 seconds
Started Jul 05 05:48:08 PM PDT 24
Finished Jul 05 05:48:10 PM PDT 24
Peak memory 215928 kb
Host smart-47fc2184-43e2-48a6-ab27-06f9eb45aace
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151740817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.151740817
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3437154756
Short name T975
Test name
Test status
Simulation time 67214590 ps
CPU time 1.06 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:11 PM PDT 24
Peak memory 218648 kb
Host smart-ba8fcc5c-0b9b-4d6a-b546-114e0100e446
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437154756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3437154756
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2418054440
Short name T393
Test name
Test status
Simulation time 37676596 ps
CPU time 0.97 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:13 PM PDT 24
Peak memory 224084 kb
Host smart-db441aef-5d57-4c62-b38b-559d2bdd492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418054440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2418054440
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.4103228716
Short name T355
Test name
Test status
Simulation time 54235216 ps
CPU time 1.88 seconds
Started Jul 05 05:48:06 PM PDT 24
Finished Jul 05 05:48:09 PM PDT 24
Peak memory 217836 kb
Host smart-15a4262d-fa44-46ea-9d69-cc1da7f2a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103228716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4103228716
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3264761950
Short name T436
Test name
Test status
Simulation time 64560929 ps
CPU time 1.02 seconds
Started Jul 05 05:48:09 PM PDT 24
Finished Jul 05 05:48:11 PM PDT 24
Peak memory 224168 kb
Host smart-282b92ab-9930-4890-bbf4-a87cdfa6d0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264761950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3264761950
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3792086813
Short name T273
Test name
Test status
Simulation time 58250449 ps
CPU time 0.91 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:05 PM PDT 24
Peak memory 207224 kb
Host smart-2b6662ea-cccb-4e98-96af-da12d10acd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792086813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3792086813
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2953657716
Short name T774
Test name
Test status
Simulation time 29097547 ps
CPU time 1 seconds
Started Jul 05 05:48:04 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 215580 kb
Host smart-eff2dba0-fc4b-4019-8ed6-7a8020efb453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953657716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2953657716
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.276748148
Short name T25
Test name
Test status
Simulation time 375692913 ps
CPU time 4 seconds
Started Jul 05 05:48:03 PM PDT 24
Finished Jul 05 05:48:08 PM PDT 24
Peak memory 215544 kb
Host smart-e4a5fddb-5561-43e9-872a-45a7e8ecb81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276748148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.276748148
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1492571995
Short name T588
Test name
Test status
Simulation time 77620812379 ps
CPU time 938.13 seconds
Started Jul 05 05:48:05 PM PDT 24
Finished Jul 05 06:03:44 PM PDT 24
Peak memory 222180 kb
Host smart-8ce8246d-e7c7-480e-9e9e-805fb287e3e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492571995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1492571995
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1775740575
Short name T347
Test name
Test status
Simulation time 35298118 ps
CPU time 1.11 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 219584 kb
Host smart-e59cd450-426a-46a9-acbb-cc81d529528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775740575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1775740575
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2611075521
Short name T341
Test name
Test status
Simulation time 21530673 ps
CPU time 1.09 seconds
Started Jul 05 05:49:39 PM PDT 24
Finished Jul 05 05:49:41 PM PDT 24
Peak memory 220172 kb
Host smart-2ce40d62-b6d0-40b0-b1d4-b840fac80686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611075521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2611075521
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3966462093
Short name T43
Test name
Test status
Simulation time 44431566 ps
CPU time 1.24 seconds
Started Jul 05 05:49:34 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 217620 kb
Host smart-44b6e0e5-3fad-434c-9dc9-3cc1a13551ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966462093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3966462093
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1790119695
Short name T162
Test name
Test status
Simulation time 61381241 ps
CPU time 1.04 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 218656 kb
Host smart-23ce13a8-b8b4-4fa1-bef7-f5f1344c1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790119695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1790119695
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3528226129
Short name T914
Test name
Test status
Simulation time 31318856 ps
CPU time 1.23 seconds
Started Jul 05 05:49:40 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 220024 kb
Host smart-ccdeac80-45d5-4f61-a0ef-f26b63102d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528226129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3528226129
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.804507518
Short name T384
Test name
Test status
Simulation time 64255738 ps
CPU time 1.08 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 217664 kb
Host smart-77f7e177-7848-47c2-98ab-aacc4d7dfb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804507518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.804507518
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1006084867
Short name T785
Test name
Test status
Simulation time 68076112 ps
CPU time 1.16 seconds
Started Jul 05 05:49:47 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 218760 kb
Host smart-a9e8e46a-a01c-40ea-9c79-04ef765a6a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006084867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1006084867
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1543164717
Short name T6
Test name
Test status
Simulation time 56813546 ps
CPU time 1.24 seconds
Started Jul 05 05:49:41 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 219868 kb
Host smart-81a26d58-0b85-4b91-94ca-400d5ca8540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543164717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1543164717
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3696181169
Short name T226
Test name
Test status
Simulation time 44689815 ps
CPU time 1.56 seconds
Started Jul 05 05:49:47 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 219016 kb
Host smart-8229e304-6bcb-45d9-9b34-24b0d9f2b924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696181169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3696181169
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.530053199
Short name T787
Test name
Test status
Simulation time 170242131 ps
CPU time 1.22 seconds
Started Jul 05 05:49:45 PM PDT 24
Finished Jul 05 05:49:47 PM PDT 24
Peak memory 219116 kb
Host smart-790b97a3-10f9-42a3-accf-abc3085c3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530053199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.530053199
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.603961595
Short name T972
Test name
Test status
Simulation time 27574809 ps
CPU time 0.96 seconds
Started Jul 05 05:49:43 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 224072 kb
Host smart-00270c98-7941-4611-979a-98b916a16e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603961595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.603961595
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1978183474
Short name T388
Test name
Test status
Simulation time 80510253 ps
CPU time 1.11 seconds
Started Jul 05 05:49:44 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 217696 kb
Host smart-ef56d449-0b59-4f61-b4b4-e0d1cd553988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978183474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1978183474
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.830563881
Short name T710
Test name
Test status
Simulation time 30551852 ps
CPU time 1.32 seconds
Started Jul 05 05:49:38 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 216052 kb
Host smart-663aeb64-7816-4928-ba43-a5c360b28113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830563881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.830563881
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.836369819
Short name T111
Test name
Test status
Simulation time 38129931 ps
CPU time 1.04 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:47 PM PDT 24
Peak memory 229908 kb
Host smart-5166ef68-6e99-49d5-ac1f-d90e4c2b2f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836369819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.836369819
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1476631804
Short name T21
Test name
Test status
Simulation time 39923697 ps
CPU time 1.1 seconds
Started Jul 05 05:49:44 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 218688 kb
Host smart-54ee8593-9372-4750-8d95-f4f95676bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476631804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1476631804
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3315143900
Short name T431
Test name
Test status
Simulation time 43607001 ps
CPU time 1.16 seconds
Started Jul 05 05:49:41 PM PDT 24
Finished Jul 05 05:49:43 PM PDT 24
Peak memory 218948 kb
Host smart-ffa4c9a6-2b81-423d-bb93-e0256bc99c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315143900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3315143900
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.407876558
Short name T152
Test name
Test status
Simulation time 23509713 ps
CPU time 1.13 seconds
Started Jul 05 05:49:44 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 224244 kb
Host smart-c73a2151-ed3d-4b52-af7c-2bbd1ff02365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407876558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.407876558
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3664769933
Short name T909
Test name
Test status
Simulation time 42416990 ps
CPU time 1.11 seconds
Started Jul 05 05:49:41 PM PDT 24
Finished Jul 05 05:49:43 PM PDT 24
Peak memory 219080 kb
Host smart-bc2a502b-6ee8-4614-8d30-0570b1415c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664769933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3664769933
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1264333539
Short name T166
Test name
Test status
Simulation time 53252059 ps
CPU time 1.12 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 220704 kb
Host smart-13fc7518-b2b4-4109-8b85-87ee95f241c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264333539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1264333539
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3256137006
Short name T221
Test name
Test status
Simulation time 136220898 ps
CPU time 1.01 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 218852 kb
Host smart-72138512-96fa-41fd-bb10-fd3ae754533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256137006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3256137006
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3469935985
Short name T584
Test name
Test status
Simulation time 63461070 ps
CPU time 2.24 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 220528 kb
Host smart-32e4e411-ff30-46a7-8c64-db2f95578b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469935985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3469935985
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1865475020
Short name T372
Test name
Test status
Simulation time 48257122 ps
CPU time 1.16 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 218908 kb
Host smart-aee14dc2-7327-4165-a8d1-ceecdba4d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865475020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1865475020
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3870343727
Short name T628
Test name
Test status
Simulation time 58089070 ps
CPU time 1.04 seconds
Started Jul 05 05:49:52 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 218956 kb
Host smart-16be33bf-b9bf-4134-9be5-f095a6b8d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870343727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3870343727
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3393039687
Short name T671
Test name
Test status
Simulation time 77174205 ps
CPU time 1.13 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:53 PM PDT 24
Peak memory 217804 kb
Host smart-79436712-28e4-4a3f-a6d4-6a8d9b52043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393039687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3393039687
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3602049432
Short name T816
Test name
Test status
Simulation time 115224711 ps
CPU time 1.23 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 220568 kb
Host smart-9419565e-4c7f-4b14-8bdd-cde831c075f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602049432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3602049432
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1992015976
Short name T146
Test name
Test status
Simulation time 51295747 ps
CPU time 1.19 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 226112 kb
Host smart-f06d0e0b-d9a0-439b-8556-fbea4f7656ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992015976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1992015976
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2593356847
Short name T840
Test name
Test status
Simulation time 35933702 ps
CPU time 1.51 seconds
Started Jul 05 05:49:52 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 220112 kb
Host smart-a048385f-8ec9-4c25-800c-a941002ef72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593356847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2593356847
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2011137130
Short name T695
Test name
Test status
Simulation time 29413401 ps
CPU time 1.27 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 221172 kb
Host smart-24dc9678-47e1-46cc-9bf2-38a8a88d551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011137130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2011137130
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_genbits.2448933212
Short name T791
Test name
Test status
Simulation time 55197546 ps
CPU time 0.97 seconds
Started Jul 05 05:49:39 PM PDT 24
Finished Jul 05 05:49:41 PM PDT 24
Peak memory 217712 kb
Host smart-5da42d6f-ba8d-4595-93e2-4fdfd4f4ea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448933212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2448933212
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2065055197
Short name T86
Test name
Test status
Simulation time 96003502 ps
CPU time 1.21 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 219980 kb
Host smart-a73bd7c7-88f3-48b0-b329-32d861dd9bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065055197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2065055197
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2775260644
Short name T362
Test name
Test status
Simulation time 41851637 ps
CPU time 0.85 seconds
Started Jul 05 05:48:08 PM PDT 24
Finished Jul 05 05:48:09 PM PDT 24
Peak memory 207120 kb
Host smart-91771cd8-5caa-4a0d-896a-2b6689fc342f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775260644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2775260644
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3138111709
Short name T793
Test name
Test status
Simulation time 68506489 ps
CPU time 0.89 seconds
Started Jul 05 05:51:42 PM PDT 24
Finished Jul 05 05:51:43 PM PDT 24
Peak memory 216576 kb
Host smart-f5510053-4471-42ae-bc68-d2266aeba2f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138111709 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3138111709
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1042264239
Short name T73
Test name
Test status
Simulation time 18748626 ps
CPU time 0.95 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 217192 kb
Host smart-cf671e10-98cd-4694-bf0c-f435a3aac3d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042264239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1042264239
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1324879267
Short name T163
Test name
Test status
Simulation time 19789663 ps
CPU time 1.16 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:12 PM PDT 24
Peak memory 218924 kb
Host smart-ccf4184d-bfd1-4978-a0f6-db827ec0d841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324879267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1324879267
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1543365875
Short name T502
Test name
Test status
Simulation time 42840689 ps
CPU time 1.53 seconds
Started Jul 05 05:49:36 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 218808 kb
Host smart-0171b4ff-0202-4b9e-a4d5-1d20ea758c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543365875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1543365875
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.509208294
Short name T33
Test name
Test status
Simulation time 19943062 ps
CPU time 1.07 seconds
Started Jul 05 05:48:10 PM PDT 24
Finished Jul 05 05:48:11 PM PDT 24
Peak memory 216244 kb
Host smart-639a686e-7a55-4ceb-a04d-44c133cc10de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509208294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.509208294
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2132879403
Short name T28
Test name
Test status
Simulation time 44895772 ps
CPU time 0.91 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:13 PM PDT 24
Peak memory 207432 kb
Host smart-19d2cf9c-5d36-4507-a662-7d12044ac511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132879403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2132879403
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1726464538
Short name T356
Test name
Test status
Simulation time 86383251 ps
CPU time 0.91 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:13 PM PDT 24
Peak memory 215424 kb
Host smart-bf17f659-7bf1-44ce-85bc-71c0ca858566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726464538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1726464538
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3082327700
Short name T712
Test name
Test status
Simulation time 1116449285 ps
CPU time 3.71 seconds
Started Jul 05 05:48:11 PM PDT 24
Finished Jul 05 05:48:16 PM PDT 24
Peak memory 215652 kb
Host smart-87fe8e42-d260-4542-a120-53a18f8f57a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082327700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3082327700
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.932337315
Short name T593
Test name
Test status
Simulation time 14507409421 ps
CPU time 366.21 seconds
Started Jul 05 05:48:13 PM PDT 24
Finished Jul 05 05:54:19 PM PDT 24
Peak memory 219048 kb
Host smart-d1d2e899-11c4-4219-abea-0a4323bdd908
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932337315 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.932337315
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3669448043
Short name T380
Test name
Test status
Simulation time 35191754 ps
CPU time 1.11 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 221032 kb
Host smart-86950675-139f-42d2-aead-d78835f4617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669448043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3669448043
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3791197196
Short name T949
Test name
Test status
Simulation time 50212159 ps
CPU time 1.02 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:53 PM PDT 24
Peak memory 219040 kb
Host smart-179c8fb8-7b1b-4f57-baf7-092016300a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791197196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3791197196
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.471761822
Short name T361
Test name
Test status
Simulation time 244522408 ps
CPU time 1.21 seconds
Started Jul 05 05:49:46 PM PDT 24
Finished Jul 05 05:49:48 PM PDT 24
Peak memory 217620 kb
Host smart-264840e9-dea4-4d72-94ec-edc993c8c5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471761822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.471761822
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1462366087
Short name T130
Test name
Test status
Simulation time 26893460 ps
CPU time 1.22 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 218900 kb
Host smart-b987cda7-3ebc-4f6b-a95a-a7ef9ae71ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462366087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1462366087
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2951295853
Short name T156
Test name
Test status
Simulation time 35389079 ps
CPU time 0.94 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:44 PM PDT 24
Peak memory 218680 kb
Host smart-f1ad699a-d243-401f-9fe8-58ae14e8f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951295853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2951295853
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.303667870
Short name T827
Test name
Test status
Simulation time 48257621 ps
CPU time 1.76 seconds
Started Jul 05 05:49:41 PM PDT 24
Finished Jul 05 05:49:43 PM PDT 24
Peak memory 220732 kb
Host smart-d1c9f1e1-aa4f-4fef-935b-59953ccde662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303667870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.303667870
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.763095710
Short name T87
Test name
Test status
Simulation time 29794924 ps
CPU time 1.18 seconds
Started Jul 05 05:49:41 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 219128 kb
Host smart-0b878928-f724-412b-8e6b-291bebb0dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763095710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.763095710
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3871716304
Short name T54
Test name
Test status
Simulation time 83132989 ps
CPU time 1.29 seconds
Started Jul 05 05:49:56 PM PDT 24
Finished Jul 05 05:49:58 PM PDT 24
Peak memory 226080 kb
Host smart-b24ee51f-6a96-4a64-a7d4-3d80bb3154a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871716304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3871716304
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.401128664
Short name T389
Test name
Test status
Simulation time 121280951 ps
CPU time 2.84 seconds
Started Jul 05 05:49:42 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 218840 kb
Host smart-cc5ac08f-f0cc-4c42-87cc-9370f0f50d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401128664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.401128664
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.902150716
Short name T845
Test name
Test status
Simulation time 42257067 ps
CPU time 1.19 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 219304 kb
Host smart-9af6233c-a90d-461e-ad75-e00f5fc938da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902150716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.902150716
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1119749883
Short name T58
Test name
Test status
Simulation time 50436191 ps
CPU time 0.95 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:50 PM PDT 24
Peak memory 223976 kb
Host smart-6690d816-56a7-414d-b11a-1d0da9c071d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119749883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1119749883
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1339094508
Short name T354
Test name
Test status
Simulation time 35699476 ps
CPU time 1.4 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 217708 kb
Host smart-178b721b-1b14-4767-a75e-9a8dec77c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339094508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1339094508
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1539732157
Short name T714
Test name
Test status
Simulation time 47016930 ps
CPU time 0.94 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 224080 kb
Host smart-675b62c8-dd4c-4710-8dfe-d3797e15287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539732157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1539732157
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.978305688
Short name T804
Test name
Test status
Simulation time 66694570 ps
CPU time 1.73 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 218968 kb
Host smart-dd449467-f7c8-4631-83ff-55b81dacf48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978305688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.978305688
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2449727525
Short name T807
Test name
Test status
Simulation time 30220767 ps
CPU time 1.21 seconds
Started Jul 05 05:49:47 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 221232 kb
Host smart-9bf5f2cb-84ec-433e-9cee-f923ec195d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449727525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2449727525
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.630487080
Short name T173
Test name
Test status
Simulation time 120246990 ps
CPU time 0.92 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 218636 kb
Host smart-4529391f-bce7-49db-ad2a-42768bf6070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630487080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.630487080
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1476850108
Short name T298
Test name
Test status
Simulation time 88435309 ps
CPU time 1.88 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:54 PM PDT 24
Peak memory 220152 kb
Host smart-3933dad4-cd82-4602-84e4-e483caa6a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476850108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1476850108
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.494937730
Short name T167
Test name
Test status
Simulation time 82973932 ps
CPU time 1.19 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 219944 kb
Host smart-fbefe0b6-3414-48d3-9389-98e5bf5341da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494937730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.494937730
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.8888124
Short name T752
Test name
Test status
Simulation time 30282980 ps
CPU time 1.2 seconds
Started Jul 05 05:49:51 PM PDT 24
Finished Jul 05 05:49:53 PM PDT 24
Peak memory 220156 kb
Host smart-0e1a9052-c292-454b-ab44-2186d0157789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8888124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.8888124
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4035617642
Short name T288
Test name
Test status
Simulation time 65866260 ps
CPU time 1.28 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:53 PM PDT 24
Peak memory 219440 kb
Host smart-a009f643-e784-4297-9eed-46b052b0ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035617642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4035617642
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1170708289
Short name T403
Test name
Test status
Simulation time 115145085 ps
CPU time 1.31 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 220312 kb
Host smart-0aff8ab6-1351-4be5-a9c0-f134be523b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170708289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1170708289
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1018888605
Short name T604
Test name
Test status
Simulation time 38768838 ps
CPU time 1.15 seconds
Started Jul 05 05:49:49 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 217912 kb
Host smart-cf8fa4cc-17a6-423b-afa5-843d4be361cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018888605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1018888605
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3078891361
Short name T302
Test name
Test status
Simulation time 34145209 ps
CPU time 1.52 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 217748 kb
Host smart-7a8e4972-f8a6-449b-bca7-7eefa9b4c640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078891361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3078891361
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2290093140
Short name T519
Test name
Test status
Simulation time 49743658 ps
CPU time 1.19 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 218868 kb
Host smart-bd739098-6d20-4761-92c7-3f720738fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290093140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2290093140
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1619229520
Short name T105
Test name
Test status
Simulation time 20138573 ps
CPU time 1.13 seconds
Started Jul 05 05:49:50 PM PDT 24
Finished Jul 05 05:49:52 PM PDT 24
Peak memory 219920 kb
Host smart-5cb2ec51-57d8-4d26-aee7-ffa2a93e396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619229520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1619229520
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3023436010
Short name T940
Test name
Test status
Simulation time 52172638 ps
CPU time 1.72 seconds
Started Jul 05 05:49:53 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 218868 kb
Host smart-418fca66-9333-4ed2-b975-0870637d6a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023436010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3023436010
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1642422451
Short name T838
Test name
Test status
Simulation time 104838769 ps
CPU time 1.1 seconds
Started Jul 05 05:49:53 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 220060 kb
Host smart-32e8af22-0342-408d-a521-521210ba4ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642422451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1642422451
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1312979930
Short name T890
Test name
Test status
Simulation time 33203399 ps
CPU time 0.92 seconds
Started Jul 05 05:49:48 PM PDT 24
Finished Jul 05 05:49:50 PM PDT 24
Peak memory 220244 kb
Host smart-780ff720-006f-452e-9855-a81d6833e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312979930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1312979930
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3462320375
Short name T313
Test name
Test status
Simulation time 64222695 ps
CPU time 1.32 seconds
Started Jul 05 05:49:54 PM PDT 24
Finished Jul 05 05:49:56 PM PDT 24
Peak memory 219236 kb
Host smart-fb46e1e6-d228-4d06-9c82-a72c6173dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462320375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3462320375
Directory /workspace/99.edn_genbits/latest
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