Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.97 97.02 93.02 96.37 99.77 92.08


Total test records in report: 1129
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T1014 /workspace/coverage/cover_reg_top/15.edn_intr_test.4108033638 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:05 PM PDT 24 62308397 ps
T284 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2586002263 Jul 07 05:47:39 PM PDT 24 Jul 07 05:47:40 PM PDT 24 32772915 ps
T296 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1803102818 Jul 07 05:47:53 PM PDT 24 Jul 07 05:47:55 PM PDT 24 28295738 ps
T1015 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4057782967 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:48 PM PDT 24 28770080 ps
T1016 /workspace/coverage/cover_reg_top/49.edn_intr_test.692752637 Jul 07 05:48:13 PM PDT 24 Jul 07 05:48:14 PM PDT 24 51999015 ps
T1017 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1667257364 Jul 07 05:47:46 PM PDT 24 Jul 07 05:47:48 PM PDT 24 120414911 ps
T309 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3361451796 Jul 07 05:47:55 PM PDT 24 Jul 07 05:47:57 PM PDT 24 142958308 ps
T1018 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1252759218 Jul 07 05:47:56 PM PDT 24 Jul 07 05:47:58 PM PDT 24 44753264 ps
T1019 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1650311616 Jul 07 05:47:50 PM PDT 24 Jul 07 05:47:52 PM PDT 24 35227025 ps
T1020 /workspace/coverage/cover_reg_top/13.edn_intr_test.3193869201 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:05 PM PDT 24 42177408 ps
T1021 /workspace/coverage/cover_reg_top/19.edn_csr_rw.10664141 Jul 07 05:48:07 PM PDT 24 Jul 07 05:48:09 PM PDT 24 68081418 ps
T1022 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3048231488 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:04 PM PDT 24 13988962 ps
T1023 /workspace/coverage/cover_reg_top/8.edn_intr_test.2367865457 Jul 07 05:47:58 PM PDT 24 Jul 07 05:48:00 PM PDT 24 151219662 ps
T1024 /workspace/coverage/cover_reg_top/22.edn_intr_test.2133920876 Jul 07 05:48:08 PM PDT 24 Jul 07 05:48:09 PM PDT 24 30597831 ps
T1025 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4200080826 Jul 07 05:47:44 PM PDT 24 Jul 07 05:47:46 PM PDT 24 28227724 ps
T285 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3511074100 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:49 PM PDT 24 15426506 ps
T1026 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1496370376 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:08 PM PDT 24 106301263 ps
T307 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2045723229 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:04 PM PDT 24 314202380 ps
T1027 /workspace/coverage/cover_reg_top/10.edn_tl_errors.153672117 Jul 07 05:47:56 PM PDT 24 Jul 07 05:47:59 PM PDT 24 82419506 ps
T1028 /workspace/coverage/cover_reg_top/20.edn_intr_test.1382847873 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:05 PM PDT 24 201709009 ps
T1029 /workspace/coverage/cover_reg_top/37.edn_intr_test.2930982784 Jul 07 05:48:13 PM PDT 24 Jul 07 05:48:15 PM PDT 24 43234486 ps
T1030 /workspace/coverage/cover_reg_top/38.edn_intr_test.779979418 Jul 07 05:48:08 PM PDT 24 Jul 07 05:48:09 PM PDT 24 38031388 ps
T1031 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1228584542 Jul 07 05:47:58 PM PDT 24 Jul 07 05:48:02 PM PDT 24 65484254 ps
T1032 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1522484272 Jul 07 05:47:55 PM PDT 24 Jul 07 05:47:57 PM PDT 24 103300197 ps
T308 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3449857285 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:46 PM PDT 24 92926606 ps
T1033 /workspace/coverage/cover_reg_top/31.edn_intr_test.3947214540 Jul 07 05:48:09 PM PDT 24 Jul 07 05:48:10 PM PDT 24 41478796 ps
T1034 /workspace/coverage/cover_reg_top/35.edn_intr_test.1950493920 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 23832295 ps
T1035 /workspace/coverage/cover_reg_top/12.edn_intr_test.2244235553 Jul 07 05:47:56 PM PDT 24 Jul 07 05:47:58 PM PDT 24 17730230 ps
T1036 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2694379157 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:01 PM PDT 24 261257313 ps
T1037 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.187508446 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:03 PM PDT 24 276234381 ps
T1038 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2943964059 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:44 PM PDT 24 42670065 ps
T286 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1842474821 Jul 07 05:47:44 PM PDT 24 Jul 07 05:47:46 PM PDT 24 33029329 ps
T1039 /workspace/coverage/cover_reg_top/12.edn_tl_errors.851104525 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:06 PM PDT 24 136618762 ps
T1040 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2373327672 Jul 07 05:48:02 PM PDT 24 Jul 07 05:48:04 PM PDT 24 26857417 ps
T1041 /workspace/coverage/cover_reg_top/17.edn_intr_test.399202456 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:01 PM PDT 24 14781266 ps
T1042 /workspace/coverage/cover_reg_top/1.edn_intr_test.3790221922 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:39 PM PDT 24 27719206 ps
T1043 /workspace/coverage/cover_reg_top/42.edn_intr_test.2983553197 Jul 07 05:48:11 PM PDT 24 Jul 07 05:48:12 PM PDT 24 39267025 ps
T1044 /workspace/coverage/cover_reg_top/0.edn_intr_test.1090201161 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:38 PM PDT 24 11215946 ps
T1045 /workspace/coverage/cover_reg_top/39.edn_intr_test.515376372 Jul 07 05:48:14 PM PDT 24 Jul 07 05:48:15 PM PDT 24 39486647 ps
T1046 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4263929022 Jul 07 05:47:56 PM PDT 24 Jul 07 05:47:58 PM PDT 24 19944394 ps
T1047 /workspace/coverage/cover_reg_top/5.edn_csr_rw.989006644 Jul 07 05:47:50 PM PDT 24 Jul 07 05:47:51 PM PDT 24 15295236 ps
T1048 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3109405032 Jul 07 05:47:54 PM PDT 24 Jul 07 05:47:55 PM PDT 24 28478523 ps
T1049 /workspace/coverage/cover_reg_top/46.edn_intr_test.1760655290 Jul 07 05:48:10 PM PDT 24 Jul 07 05:48:12 PM PDT 24 12789603 ps
T1050 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2893087250 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:02 PM PDT 24 21306582 ps
T1051 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2651560269 Jul 07 05:47:46 PM PDT 24 Jul 07 05:47:53 PM PDT 24 874566146 ps
T310 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3665038367 Jul 07 05:48:08 PM PDT 24 Jul 07 05:48:11 PM PDT 24 257084326 ps
T287 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.624686965 Jul 07 05:47:39 PM PDT 24 Jul 07 05:47:40 PM PDT 24 53426661 ps
T1052 /workspace/coverage/cover_reg_top/5.edn_intr_test.3623152484 Jul 07 05:47:48 PM PDT 24 Jul 07 05:47:49 PM PDT 24 11833041 ps
T1053 /workspace/coverage/cover_reg_top/47.edn_intr_test.2770252688 Jul 07 05:48:10 PM PDT 24 Jul 07 05:48:11 PM PDT 24 26220326 ps
T1054 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1243174880 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:04 PM PDT 24 102279662 ps
T1055 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3225648153 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:01 PM PDT 24 26539040 ps
T1056 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1498742026 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:03 PM PDT 24 172923008 ps
T1057 /workspace/coverage/cover_reg_top/23.edn_intr_test.2170299604 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 16612464 ps
T1058 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1829805060 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:02 PM PDT 24 97310734 ps
T1059 /workspace/coverage/cover_reg_top/1.edn_tl_errors.684074437 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:46 PM PDT 24 123770057 ps
T1060 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1229008511 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:05 PM PDT 24 87404257 ps
T1061 /workspace/coverage/cover_reg_top/25.edn_intr_test.359821105 Jul 07 05:48:10 PM PDT 24 Jul 07 05:48:11 PM PDT 24 47629557 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2228085498 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:44 PM PDT 24 102819338 ps
T1063 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3633166496 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:49 PM PDT 24 87861368 ps
T1064 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2287989944 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:05 PM PDT 24 23717660 ps
T1065 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.12451963 Jul 07 05:47:52 PM PDT 24 Jul 07 05:47:53 PM PDT 24 18668988 ps
T311 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4234988184 Jul 07 05:47:59 PM PDT 24 Jul 07 05:48:02 PM PDT 24 633978959 ps
T1066 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1765758789 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:07 PM PDT 24 46893170 ps
T1067 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1042098463 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:49 PM PDT 24 106222065 ps
T1068 /workspace/coverage/cover_reg_top/0.edn_tl_errors.247270962 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:38 PM PDT 24 62697548 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4031459616 Jul 07 05:47:42 PM PDT 24 Jul 07 05:47:45 PM PDT 24 71939143 ps
T1070 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3387410823 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:04 PM PDT 24 18074534 ps
T1071 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2727166188 Jul 07 05:47:46 PM PDT 24 Jul 07 05:47:49 PM PDT 24 60878847 ps
T1072 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2947944787 Jul 07 05:47:44 PM PDT 24 Jul 07 05:47:48 PM PDT 24 119418851 ps
T1073 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3183941479 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:40 PM PDT 24 58136490 ps
T1074 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3192915932 Jul 07 05:47:51 PM PDT 24 Jul 07 05:47:54 PM PDT 24 160489314 ps
T1075 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2734477051 Jul 07 05:47:42 PM PDT 24 Jul 07 05:47:44 PM PDT 24 23407944 ps
T1076 /workspace/coverage/cover_reg_top/30.edn_intr_test.881311161 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 53711457 ps
T1077 /workspace/coverage/cover_reg_top/9.edn_intr_test.1551758481 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:59 PM PDT 24 33572631 ps
T288 /workspace/coverage/cover_reg_top/1.edn_csr_rw.293483040 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:40 PM PDT 24 33278088 ps
T1078 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2345602813 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:06 PM PDT 24 37462444 ps
T1079 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1155047386 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:58 PM PDT 24 61945917 ps
T1080 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3886851825 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:03 PM PDT 24 86847258 ps
T1081 /workspace/coverage/cover_reg_top/18.edn_intr_test.3930899378 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 42334786 ps
T1082 /workspace/coverage/cover_reg_top/44.edn_intr_test.2927117364 Jul 07 05:48:12 PM PDT 24 Jul 07 05:48:14 PM PDT 24 24999934 ps
T1083 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1704717503 Jul 07 05:48:12 PM PDT 24 Jul 07 05:48:14 PM PDT 24 90022500 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.93906545 Jul 07 05:47:58 PM PDT 24 Jul 07 05:48:00 PM PDT 24 30911687 ps
T1085 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2275277551 Jul 07 05:47:58 PM PDT 24 Jul 07 05:48:01 PM PDT 24 286802534 ps
T1086 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2696324661 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:02 PM PDT 24 15858010 ps
T1087 /workspace/coverage/cover_reg_top/14.edn_intr_test.1430703630 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:05 PM PDT 24 17642472 ps
T289 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1675947504 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:48 PM PDT 24 58909227 ps
T1088 /workspace/coverage/cover_reg_top/7.edn_intr_test.3966643548 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:58 PM PDT 24 19241077 ps
T1089 /workspace/coverage/cover_reg_top/40.edn_intr_test.2324057204 Jul 07 05:48:11 PM PDT 24 Jul 07 05:48:13 PM PDT 24 36135924 ps
T1090 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.82287499 Jul 07 05:47:56 PM PDT 24 Jul 07 05:47:59 PM PDT 24 77662720 ps
T1091 /workspace/coverage/cover_reg_top/10.edn_intr_test.1357835363 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:58 PM PDT 24 42037316 ps
T1092 /workspace/coverage/cover_reg_top/2.edn_intr_test.4128092736 Jul 07 05:47:49 PM PDT 24 Jul 07 05:47:50 PM PDT 24 36957640 ps
T1093 /workspace/coverage/cover_reg_top/33.edn_intr_test.3878143999 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:06 PM PDT 24 40714104 ps
T1094 /workspace/coverage/cover_reg_top/45.edn_intr_test.861931194 Jul 07 05:48:10 PM PDT 24 Jul 07 05:48:12 PM PDT 24 108625728 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4147657547 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:06 PM PDT 24 108867399 ps
T290 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2786461117 Jul 07 05:47:49 PM PDT 24 Jul 07 05:47:50 PM PDT 24 77247511 ps
T1096 /workspace/coverage/cover_reg_top/43.edn_intr_test.1530911004 Jul 07 05:48:11 PM PDT 24 Jul 07 05:48:12 PM PDT 24 24488092 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1012357494 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:46 PM PDT 24 81471043 ps
T1098 /workspace/coverage/cover_reg_top/24.edn_intr_test.2943309985 Jul 07 05:48:05 PM PDT 24 Jul 07 05:48:06 PM PDT 24 15949858 ps
T1099 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3048974107 Jul 07 05:47:53 PM PDT 24 Jul 07 05:47:56 PM PDT 24 117948705 ps
T1100 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.299454064 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:05 PM PDT 24 163833950 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1472772882 Jul 07 05:47:53 PM PDT 24 Jul 07 05:47:55 PM PDT 24 92032847 ps
T1102 /workspace/coverage/cover_reg_top/11.edn_intr_test.1128762955 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:58 PM PDT 24 27650842 ps
T1103 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3953233585 Jul 07 05:47:49 PM PDT 24 Jul 07 05:47:50 PM PDT 24 69510384 ps
T1104 /workspace/coverage/cover_reg_top/28.edn_intr_test.1538607364 Jul 07 05:48:11 PM PDT 24 Jul 07 05:48:12 PM PDT 24 27035985 ps
T1105 /workspace/coverage/cover_reg_top/32.edn_intr_test.951113924 Jul 07 05:48:12 PM PDT 24 Jul 07 05:48:13 PM PDT 24 71595527 ps
T1106 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.523356472 Jul 07 05:47:58 PM PDT 24 Jul 07 05:48:00 PM PDT 24 32559262 ps
T1107 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3958142964 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 62258532 ps
T1108 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1146679645 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 15060272 ps
T1109 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1263418955 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:03 PM PDT 24 29201369 ps
T1110 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3209145002 Jul 07 05:48:01 PM PDT 24 Jul 07 05:48:05 PM PDT 24 280911446 ps
T1111 /workspace/coverage/cover_reg_top/21.edn_intr_test.3522172724 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:04 PM PDT 24 117364696 ps
T1112 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1678818761 Jul 07 05:47:47 PM PDT 24 Jul 07 05:47:48 PM PDT 24 29153966 ps
T1113 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.396480474 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:46 PM PDT 24 35934358 ps
T1114 /workspace/coverage/cover_reg_top/29.edn_intr_test.1517961528 Jul 07 05:48:05 PM PDT 24 Jul 07 05:48:06 PM PDT 24 29649859 ps
T1115 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3047659567 Jul 07 05:47:57 PM PDT 24 Jul 07 05:47:59 PM PDT 24 57378540 ps
T1116 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1738920013 Jul 07 05:48:00 PM PDT 24 Jul 07 05:48:02 PM PDT 24 21412285 ps
T1117 /workspace/coverage/cover_reg_top/34.edn_intr_test.2689543996 Jul 07 05:48:06 PM PDT 24 Jul 07 05:48:07 PM PDT 24 25727573 ps
T1118 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1424507915 Jul 07 05:47:43 PM PDT 24 Jul 07 05:47:49 PM PDT 24 1380018322 ps
T1119 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2513358296 Jul 07 05:48:03 PM PDT 24 Jul 07 05:48:04 PM PDT 24 41711772 ps
T1120 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.59880886 Jul 07 05:47:44 PM PDT 24 Jul 07 05:47:47 PM PDT 24 521477805 ps
T1121 /workspace/coverage/cover_reg_top/5.edn_tl_errors.61519853 Jul 07 05:47:51 PM PDT 24 Jul 07 05:47:55 PM PDT 24 96520616 ps
T1122 /workspace/coverage/cover_reg_top/3.edn_intr_test.4081734930 Jul 07 05:47:44 PM PDT 24 Jul 07 05:47:45 PM PDT 24 15801515 ps
T1123 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3338867252 Jul 07 05:47:40 PM PDT 24 Jul 07 05:47:45 PM PDT 24 176466493 ps
T1124 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3233089269 Jul 07 05:48:02 PM PDT 24 Jul 07 05:48:03 PM PDT 24 15070652 ps
T1125 /workspace/coverage/cover_reg_top/7.edn_tl_errors.716206310 Jul 07 05:47:50 PM PDT 24 Jul 07 05:47:54 PM PDT 24 284715235 ps
T1126 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1602591134 Jul 07 05:48:04 PM PDT 24 Jul 07 05:48:06 PM PDT 24 58048965 ps
T1127 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3472943752 Jul 07 05:47:59 PM PDT 24 Jul 07 05:48:00 PM PDT 24 16387537 ps
T1128 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3154668161 Jul 07 05:48:05 PM PDT 24 Jul 07 05:48:08 PM PDT 24 102027357 ps
T1129 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2896070892 Jul 07 05:47:57 PM PDT 24 Jul 07 05:48:00 PM PDT 24 56964391 ps

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2954323505
Short name T4
Test name
Test status
Simulation time 221012408814 ps
CPU time 917.91 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 06:06:00 PM PDT 24
Peak memory 222468 kb
Host smart-3cbf3b1c-9348-4632-8bfc-9253a582b3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954323505 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2954323505
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_err.3697681724
Short name T5
Test name
Test status
Simulation time 33281242 ps
CPU time 0.98 seconds
Started Jul 07 05:50:10 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 219928 kb
Host smart-8f9c251c-61d5-459b-ad5f-f3d7874402e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697681724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3697681724
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/262.edn_genbits.2617435187
Short name T45
Test name
Test status
Simulation time 84959462 ps
CPU time 1.68 seconds
Started Jul 07 05:52:10 PM PDT 24
Finished Jul 07 05:52:12 PM PDT 24
Peak memory 219048 kb
Host smart-83752c4c-e83c-40b8-8ee8-ff22b1e64a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617435187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2617435187
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2352655968
Short name T57
Test name
Test status
Simulation time 79563947 ps
CPU time 1.83 seconds
Started Jul 07 05:52:11 PM PDT 24
Finished Jul 07 05:52:13 PM PDT 24
Peak memory 219116 kb
Host smart-6bae0810-a220-4294-a9c0-16687ed86e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352655968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2352655968
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1561839576
Short name T17
Test name
Test status
Simulation time 1269882206 ps
CPU time 9.54 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:37 PM PDT 24
Peak memory 237652 kb
Host smart-ed33e103-677a-47c2-abe2-80b07840ad78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561839576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1561839576
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/124.edn_alert.530030010
Short name T10
Test name
Test status
Simulation time 28673834 ps
CPU time 1.36 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 220280 kb
Host smart-3c77938f-639a-4df0-89ec-96105a24b603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530030010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.530030010
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.206631686
Short name T22
Test name
Test status
Simulation time 133269403 ps
CPU time 3.25 seconds
Started Jul 07 05:51:56 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 219924 kb
Host smart-620b1381-022e-494d-a864-1d89fd131b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206631686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.206631686
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_disable.2155426521
Short name T95
Test name
Test status
Simulation time 11491153 ps
CPU time 0.91 seconds
Started Jul 07 05:50:47 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 216592 kb
Host smart-5c620087-318f-4e7c-84ce-0d0fff863f3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155426521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2155426521
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/60.edn_alert.196030866
Short name T98
Test name
Test status
Simulation time 27653670 ps
CPU time 1.34 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:51:00 PM PDT 24
Peak memory 220188 kb
Host smart-bf228440-b55e-433f-af1b-9c49aabdb9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196030866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.196030866
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1829221339
Short name T240
Test name
Test status
Simulation time 53995772159 ps
CPU time 716.42 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 06:02:46 PM PDT 24
Peak memory 224024 kb
Host smart-cf219ab3-d551-44bf-8661-390c076c1bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829221339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1829221339
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.499869516
Short name T2
Test name
Test status
Simulation time 73996829 ps
CPU time 1.24 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 215924 kb
Host smart-cbcc4d9f-18af-49b1-af37-577ba5afbd13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499869516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.499869516
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_regwen.3417135040
Short name T259
Test name
Test status
Simulation time 19421565 ps
CPU time 1.03 seconds
Started Jul 07 05:49:26 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 207292 kb
Host smart-f3c195f0-8d72-4509-bd75-856a3006628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417135040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3417135040
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/44.edn_err.578365104
Short name T14
Test name
Test status
Simulation time 87926504 ps
CPU time 0.99 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 224056 kb
Host smart-845b69df-637b-4fd7-a3c2-afced1263118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578365104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.578365104
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/115.edn_alert.2561896970
Short name T94
Test name
Test status
Simulation time 21875018 ps
CPU time 1.16 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218920 kb
Host smart-8baa441a-15e6-4e66-9e31-479e05f9a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561896970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2561896970
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2140798728
Short name T77
Test name
Test status
Simulation time 29845546 ps
CPU time 1.26 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 217084 kb
Host smart-91d45dfe-ae72-4e59-9756-cfd6c531d73c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140798728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2140798728
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3449857285
Short name T308
Test name
Test status
Simulation time 92926606 ps
CPU time 2.61 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 215204 kb
Host smart-d7c6d54d-ca9f-4389-a75e-94bc8aaa2dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449857285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3449857285
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/28.edn_alert.2722535348
Short name T162
Test name
Test status
Simulation time 26977629 ps
CPU time 1.16 seconds
Started Jul 07 05:50:19 PM PDT 24
Finished Jul 07 05:50:20 PM PDT 24
Peak memory 219140 kb
Host smart-8e8aa434-d0dd-49e3-98c5-b2bf34a55290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722535348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2722535348
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2842629121
Short name T283
Test name
Test status
Simulation time 27540394 ps
CPU time 0.81 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206836 kb
Host smart-375a4e97-b4fc-4a84-9f20-8d3586830b40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842629121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2842629121
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/default/1.edn_alert.114716739
Short name T185
Test name
Test status
Simulation time 23828737 ps
CPU time 1.17 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:49:30 PM PDT 24
Peak memory 218756 kb
Host smart-4e8baa0c-e00c-494c-89c3-3de874a0bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114716739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.114716739
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.2531164899
Short name T92
Test name
Test status
Simulation time 12687348 ps
CPU time 0.91 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 216780 kb
Host smart-4fd161f3-f708-4a60-87be-deb809d7f9ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531164899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2531164899
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.2605203786
Short name T207
Test name
Test status
Simulation time 91004596 ps
CPU time 0.86 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:24 PM PDT 24
Peak memory 216540 kb
Host smart-56bc3d67-7928-4396-8738-925a088cb1c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605203786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2605203786
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable.3736714226
Short name T222
Test name
Test status
Simulation time 30436104 ps
CPU time 0.85 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:20 PM PDT 24
Peak memory 216656 kb
Host smart-de47bdf2-bc0c-4ca8-874e-488f06cd66f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736714226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3736714226
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2715879241
Short name T895
Test name
Test status
Simulation time 89853493 ps
CPU time 1.16 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 217164 kb
Host smart-30a5fbfa-389a-4806-9c09-d30a4e399a32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715879241 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2715879241
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_alert.1679947530
Short name T201
Test name
Test status
Simulation time 45050943 ps
CPU time 1.14 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 219048 kb
Host smart-345df0cb-c228-4dca-ab20-295c875034d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679947530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1679947530
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/159.edn_alert.296949584
Short name T275
Test name
Test status
Simulation time 48280895 ps
CPU time 1.23 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 219020 kb
Host smart-e10aa241-d20a-4aff-af21-1fee7ed91827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296949584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.296949584
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert.2877074118
Short name T32
Test name
Test status
Simulation time 24305699 ps
CPU time 1.26 seconds
Started Jul 07 05:49:39 PM PDT 24
Finished Jul 07 05:49:41 PM PDT 24
Peak memory 220912 kb
Host smart-f8c3ecc9-d215-47ae-a6b7-442863131ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877074118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2877074118
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/51.edn_alert.1595533445
Short name T33
Test name
Test status
Simulation time 45791159 ps
CPU time 1.27 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 220692 kb
Host smart-6fbaa599-6fd0-4124-b169-2edf1c0aaebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595533445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1595533445
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/66.edn_alert.2511569306
Short name T101
Test name
Test status
Simulation time 26637103 ps
CPU time 1.25 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 218732 kb
Host smart-225adf2c-3430-40b3-b069-9ba66341dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511569306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2511569306
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/253.edn_genbits.4157502625
Short name T46
Test name
Test status
Simulation time 41031109 ps
CPU time 1.3 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 218772 kb
Host smart-d13d6c60-c3f7-4731-af99-b4909b0bfc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157502625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4157502625
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3123685756
Short name T552
Test name
Test status
Simulation time 21441003 ps
CPU time 1.15 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 220140 kb
Host smart-e2fc3bd1-8119-448f-bdba-04c049b7f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123685756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3123685756
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/37.edn_disable.3071230103
Short name T58
Test name
Test status
Simulation time 25950984 ps
CPU time 0.83 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:35 PM PDT 24
Peak memory 215760 kb
Host smart-360f0033-1e84-4744-a37d-d754d1f7f323
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071230103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3071230103
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/170.edn_alert.3045303684
Short name T348
Test name
Test status
Simulation time 78902486 ps
CPU time 1.2 seconds
Started Jul 07 05:51:39 PM PDT 24
Finished Jul 07 05:51:41 PM PDT 24
Peak memory 220492 kb
Host smart-b70b5223-ca98-4b36-ab7b-cfcfd594460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045303684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3045303684
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert.2463320571
Short name T346
Test name
Test status
Simulation time 89542157 ps
CPU time 1.26 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 221164 kb
Host smart-fe3b51a8-1d86-4244-86bb-7b7caddfbab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463320571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2463320571
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/10.edn_intr.2089356970
Short name T40
Test name
Test status
Simulation time 20971116 ps
CPU time 1.15 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 216068 kb
Host smart-470b0785-975f-4f04-8026-5880d2594e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089356970 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2089356970
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/286.edn_genbits.2977389740
Short name T12
Test name
Test status
Simulation time 119646210 ps
CPU time 1.18 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 217664 kb
Host smart-72752cbc-3447-4bc0-8fdf-e6fe190cd0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977389740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2977389740
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1337758739
Short name T43
Test name
Test status
Simulation time 150225063284 ps
CPU time 984.98 seconds
Started Jul 07 05:50:35 PM PDT 24
Finished Jul 07 06:07:01 PM PDT 24
Peak memory 224004 kb
Host smart-d74010ce-47ee-44ae-a2b9-a7df5b279b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337758739 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1337758739
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.330584777
Short name T99
Test name
Test status
Simulation time 24871163 ps
CPU time 1.2 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 219044 kb
Host smart-43fe0b47-b551-4466-84fb-63de3fd1a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330584777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.330584777
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/15.edn_intr.2546451893
Short name T800
Test name
Test status
Simulation time 38408458 ps
CPU time 0.91 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 216116 kb
Host smart-ac86bfb5-63f1-4956-b4bf-366949392056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546451893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2546451893
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/30.edn_alert_test.1648821112
Short name T27
Test name
Test status
Simulation time 85062575 ps
CPU time 1.28 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:20 PM PDT 24
Peak memory 215240 kb
Host smart-3ecb6262-f0e0-4879-98d7-be2adbfba8c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648821112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1648821112
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3094314384
Short name T225
Test name
Test status
Simulation time 38053859 ps
CPU time 1.44 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:24 PM PDT 24
Peak memory 217672 kb
Host smart-82ccb460-c745-4d84-9eaf-2db028762e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094314384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3094314384
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.2786190507
Short name T59
Test name
Test status
Simulation time 39751113 ps
CPU time 1.18 seconds
Started Jul 07 05:49:41 PM PDT 24
Finished Jul 07 05:49:42 PM PDT 24
Peak memory 220140 kb
Host smart-554e8afd-e3d9-4825-b3f1-f34885115a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786190507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2786190507
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4286195972
Short name T848
Test name
Test status
Simulation time 62861877 ps
CPU time 1.16 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:47 PM PDT 24
Peak memory 216932 kb
Host smart-23fad679-7b07-4be8-8789-deac1ab23100
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286195972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4286195972
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.3905529728
Short name T741
Test name
Test status
Simulation time 24847235 ps
CPU time 1.23 seconds
Started Jul 07 05:49:47 PM PDT 24
Finished Jul 07 05:49:49 PM PDT 24
Peak memory 218852 kb
Host smart-78aa948e-b34b-4dfc-ba64-33b9b9614587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905529728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3905529728
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.674235520
Short name T916
Test name
Test status
Simulation time 27609015 ps
CPU time 1.39 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 219572 kb
Host smart-0b22ed0a-54c1-4239-bcbd-a1d7e84c79e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674235520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.674235520
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.2828680938
Short name T208
Test name
Test status
Simulation time 11174734 ps
CPU time 0.91 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:05 PM PDT 24
Peak memory 216688 kb
Host smart-619245ef-33d0-4d72-87b0-49b7cea4aace
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828680938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2828680938
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2320921011
Short name T137
Test name
Test status
Simulation time 25218315 ps
CPU time 1.04 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 217128 kb
Host smart-bb76232d-d2b3-4eac-bf3c-7525fc6d6ecd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320921011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2320921011
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable.2578364472
Short name T228
Test name
Test status
Simulation time 19314622 ps
CPU time 0.87 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 216536 kb
Host smart-49a42549-d19a-4276-b05a-2d265f987a63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578364472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2578364472
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.71987742
Short name T198
Test name
Test status
Simulation time 21651820 ps
CPU time 1.04 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 224304 kb
Host smart-8e2f2e0c-f9d9-4bba-90a6-c54262a6f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71987742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.71987742
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/3.edn_disable.3380409600
Short name T209
Test name
Test status
Simulation time 13173002 ps
CPU time 0.91 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:49:31 PM PDT 24
Peak memory 216676 kb
Host smart-6f9a9d0f-b64c-4034-b57d-c492d54ba6d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380409600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3380409600
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.905955558
Short name T217
Test name
Test status
Simulation time 39275859 ps
CPU time 1.26 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 217204 kb
Host smart-b8c374e7-a861-4c83-b4d0-94e88761554f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905955558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.905955558
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.172587276
Short name T203
Test name
Test status
Simulation time 20193632 ps
CPU time 1.2 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:37 PM PDT 24
Peak memory 229804 kb
Host smart-36f4d355-ce6f-4b9f-a3b0-5d369596c521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172587276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.172587276
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/234.edn_genbits.3937440200
Short name T109
Test name
Test status
Simulation time 62009970 ps
CPU time 1.08 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 217536 kb
Host smart-73030308-8aa6-42fa-88c8-afc8354da4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937440200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3937440200
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_genbits.3776657804
Short name T13
Test name
Test status
Simulation time 43797792 ps
CPU time 1.26 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 218856 kb
Host smart-3e92019c-bca0-4486-8409-367c31cf3680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776657804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3776657804
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.464193012
Short name T332
Test name
Test status
Simulation time 45494071 ps
CPU time 1.76 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 218840 kb
Host smart-d3c1c065-fdf6-4843-92cc-4ddeda533d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464193012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.464193012
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3889855193
Short name T945
Test name
Test status
Simulation time 101517324 ps
CPU time 1.32 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 215612 kb
Host smart-b5fce611-db28-4b8d-809d-70efe32c387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889855193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3889855193
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2325997757
Short name T115
Test name
Test status
Simulation time 29005970 ps
CPU time 0.96 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 216164 kb
Host smart-fe00a8e2-b932-41ee-90c0-695b1b40d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325997757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2325997757
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/182.edn_genbits.937733196
Short name T55
Test name
Test status
Simulation time 352496756 ps
CPU time 1.16 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 217752 kb
Host smart-d83c155e-f5fb-473f-ae46-1a2c3c66f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937733196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.937733196
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/50.edn_genbits.3056289206
Short name T324
Test name
Test status
Simulation time 36376581 ps
CPU time 1.66 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 220300 kb
Host smart-55c8ad22-045b-458b-b18f-a1c554188401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056289206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3056289206
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3361451796
Short name T309
Test name
Test status
Simulation time 142958308 ps
CPU time 2.19 seconds
Started Jul 07 05:47:55 PM PDT 24
Finished Jul 07 05:47:57 PM PDT 24
Peak memory 206916 kb
Host smart-c7df8288-b03a-430d-959e-8735655ea5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361451796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3361451796
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/116.edn_genbits.3941592282
Short name T318
Test name
Test status
Simulation time 46027124 ps
CPU time 1.47 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 217628 kb
Host smart-4bb227cc-2030-4af1-ba02-9faf82810c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941592282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3941592282
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.3202804789
Short name T256
Test name
Test status
Simulation time 57282201 ps
CPU time 1.08 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:52 PM PDT 24
Peak memory 217816 kb
Host smart-96988962-53de-40e9-9a55-59b1bd349038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202804789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3202804789
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1089997295
Short name T323
Test name
Test status
Simulation time 169960892 ps
CPU time 1.34 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 219076 kb
Host smart-664f17d0-c244-4c42-a6be-12f92817f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089997295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1089997295
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.4099287825
Short name T497
Test name
Test status
Simulation time 269975855 ps
CPU time 2.22 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 217780 kb
Host smart-6788e9be-a9e5-402c-8685-e8e593e10186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099287825 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4099287825
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_genbits.2523743323
Short name T319
Test name
Test status
Simulation time 77937567 ps
CPU time 1.48 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 219064 kb
Host smart-91b606be-f13a-444d-9fd8-92f81ae5cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523743323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2523743323
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_genbits.1886723948
Short name T853
Test name
Test status
Simulation time 95456783 ps
CPU time 1.28 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 219012 kb
Host smart-c1e14e81-6900-4c95-9ad8-e38b93328656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886723948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1886723948
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2476949876
Short name T38
Test name
Test status
Simulation time 62295195 ps
CPU time 0.87 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 215812 kb
Host smart-3677d0cb-29cd-48dc-9c6f-6b2c55188042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476949876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2476949876
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/106.edn_alert.3849875935
Short name T128
Test name
Test status
Simulation time 58368425 ps
CPU time 1.23 seconds
Started Jul 07 05:51:19 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 219880 kb
Host smart-a3c94fa1-7dd6-4533-98c8-8373ad58763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849875935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3849875935
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.2935499519
Short name T161
Test name
Test status
Simulation time 77568986 ps
CPU time 1.13 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219972 kb
Host smart-2efd951f-5ea7-4200-ad28-2005d39ace8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935499519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2935499519
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3491679070
Short name T906
Test name
Test status
Simulation time 34846003 ps
CPU time 1.62 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 219244 kb
Host smart-f8fbd216-2030-4dcb-b61f-8e17fb6d956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491679070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3491679070
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.624686965
Short name T287
Test name
Test status
Simulation time 53426661 ps
CPU time 1.03 seconds
Started Jul 07 05:47:39 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 206980 kb
Host smart-f1373ae7-0c54-4c36-922d-72d01b9d26ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624686965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.624686965
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3338867252
Short name T1123
Test name
Test status
Simulation time 176466493 ps
CPU time 4.93 seconds
Started Jul 07 05:47:40 PM PDT 24
Finished Jul 07 05:47:45 PM PDT 24
Peak memory 206920 kb
Host smart-80b996a9-2db0-4a7f-a2c8-b9e436c7326c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338867252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3338867252
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1146679645
Short name T1108
Test name
Test status
Simulation time 15060272 ps
CPU time 0.96 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 206848 kb
Host smart-97034a99-0d5a-4d4b-937d-b4b594808fab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146679645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1146679645
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.27186182
Short name T1010
Test name
Test status
Simulation time 26500550 ps
CPU time 1.79 seconds
Started Jul 07 05:47:41 PM PDT 24
Finished Jul 07 05:47:43 PM PDT 24
Peak memory 215248 kb
Host smart-75611c4b-64f1-4ddd-920d-2825b3af6bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186182 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.27186182
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2586002263
Short name T284
Test name
Test status
Simulation time 32772915 ps
CPU time 0.8 seconds
Started Jul 07 05:47:39 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 206744 kb
Host smart-258ad857-c506-4388-b729-ec5db89aa9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586002263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2586002263
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1090201161
Short name T1044
Test name
Test status
Simulation time 11215946 ps
CPU time 0.88 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 206840 kb
Host smart-d83b606d-bc52-488f-8ef1-85b644652edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090201161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1090201161
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2943964059
Short name T1038
Test name
Test status
Simulation time 42670065 ps
CPU time 1.15 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:44 PM PDT 24
Peak memory 207052 kb
Host smart-66e14aab-ffec-478a-81b8-55d57b252452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943964059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2943964059
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.247270962
Short name T1068
Test name
Test status
Simulation time 62697548 ps
CPU time 2.39 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 215316 kb
Host smart-0a14e9d6-13c8-4d5a-b392-f164379ac50e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247270962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.247270962
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3183941479
Short name T1073
Test name
Test status
Simulation time 58136490 ps
CPU time 1.82 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 206900 kb
Host smart-c4dc3419-957c-4e77-aa84-5a4aabd4b778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183941479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3183941479
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2316805011
Short name T1005
Test name
Test status
Simulation time 83196162 ps
CPU time 1.17 seconds
Started Jul 07 05:47:39 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 206896 kb
Host smart-56e1be27-6431-4b58-9dfb-4711ea814d54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316805011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2316805011
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1424507915
Short name T1118
Test name
Test status
Simulation time 1380018322 ps
CPU time 6.44 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 206968 kb
Host smart-3b35f41e-400c-4e4a-883c-024f5900bb47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424507915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1424507915
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3255645457
Short name T1011
Test name
Test status
Simulation time 19303758 ps
CPU time 0.95 seconds
Started Jul 07 05:47:42 PM PDT 24
Finished Jul 07 05:47:43 PM PDT 24
Peak memory 206744 kb
Host smart-f1a1c932-f0e7-4cc0-96ec-882c4db764f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255645457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3255645457
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2234390124
Short name T994
Test name
Test status
Simulation time 19378733 ps
CPU time 1.5 seconds
Started Jul 07 05:47:45 PM PDT 24
Finished Jul 07 05:47:47 PM PDT 24
Peak memory 215112 kb
Host smart-4477ad6b-15de-4584-9f85-edc12dbc4421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234390124 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2234390124
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.293483040
Short name T288
Test name
Test status
Simulation time 33278088 ps
CPU time 0.85 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 206920 kb
Host smart-51edf4af-70d4-4621-b935-9588cfbfa336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293483040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.293483040
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3790221922
Short name T1042
Test name
Test status
Simulation time 27719206 ps
CPU time 0.89 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 206820 kb
Host smart-e95feab1-91a1-48e0-b5dc-9ad6340d2d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790221922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3790221922
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.210988720
Short name T293
Test name
Test status
Simulation time 43577638 ps
CPU time 1.57 seconds
Started Jul 07 05:47:40 PM PDT 24
Finished Jul 07 05:47:42 PM PDT 24
Peak memory 206936 kb
Host smart-c9634230-1292-4063-96c7-fad9f11ba6c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210988720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.210988720
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.684074437
Short name T1059
Test name
Test status
Simulation time 123770057 ps
CPU time 2.74 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 215380 kb
Host smart-045edf54-4f7a-416b-9729-b5d29cec61b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684074437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.684074437
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1522484272
Short name T1032
Test name
Test status
Simulation time 103300197 ps
CPU time 1.3 seconds
Started Jul 07 05:47:55 PM PDT 24
Finished Jul 07 05:47:57 PM PDT 24
Peak memory 217008 kb
Host smart-f097ed90-d09e-439e-8a94-c331320b5488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522484272 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1522484272
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4167879474
Short name T999
Test name
Test status
Simulation time 36939017 ps
CPU time 0.95 seconds
Started Jul 07 05:47:54 PM PDT 24
Finished Jul 07 05:47:56 PM PDT 24
Peak memory 206792 kb
Host smart-0fbd1915-fa55-4533-9f2b-6b3c69acb0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167879474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4167879474
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1357835363
Short name T1091
Test name
Test status
Simulation time 42037316 ps
CPU time 0.89 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206828 kb
Host smart-99b0beff-6375-47a4-8579-1201e9a4d8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357835363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1357835363
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3472943752
Short name T1127
Test name
Test status
Simulation time 16387537 ps
CPU time 1.01 seconds
Started Jul 07 05:47:59 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 206936 kb
Host smart-b297b4c7-81d1-421e-a279-f9b90ea2eb0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472943752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3472943752
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.153672117
Short name T1027
Test name
Test status
Simulation time 82419506 ps
CPU time 3.12 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 215468 kb
Host smart-520c67da-57ad-4cd7-8884-5a9f8d044f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153672117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.153672117
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1725091084
Short name T1006
Test name
Test status
Simulation time 74294252 ps
CPU time 1.55 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:57 PM PDT 24
Peak memory 215168 kb
Host smart-a47e2d26-d21c-44ad-91bd-766652a96e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725091084 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1725091084
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1155047386
Short name T1079
Test name
Test status
Simulation time 61945917 ps
CPU time 0.87 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206976 kb
Host smart-30dbbe38-09e0-43e2-82c6-c11218a524c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155047386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1155047386
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1128762955
Short name T1102
Test name
Test status
Simulation time 27650842 ps
CPU time 0.88 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206916 kb
Host smart-935dc8e4-6cbd-47bd-bbef-42f4ed721e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128762955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1128762955
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3109405032
Short name T1048
Test name
Test status
Simulation time 28478523 ps
CPU time 1.02 seconds
Started Jul 07 05:47:54 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 206936 kb
Host smart-ba1c4b24-cbce-42f2-a6f7-a0206e0787ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109405032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3109405032
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1496370376
Short name T1026
Test name
Test status
Simulation time 106301263 ps
CPU time 4.01 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:08 PM PDT 24
Peak memory 215352 kb
Host smart-d7729477-5f2e-45cb-96f8-6c67eab9079e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496370376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1496370376
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4234988184
Short name T311
Test name
Test status
Simulation time 633978959 ps
CPU time 2.23 seconds
Started Jul 07 05:47:59 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 215164 kb
Host smart-b812f2e2-00c1-45e1-8984-e7ac449aeafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234988184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4234988184
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2694379157
Short name T1036
Test name
Test status
Simulation time 261257313 ps
CPU time 1.31 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:01 PM PDT 24
Peak memory 217180 kb
Host smart-b60b3fe6-a6d2-4c7f-b948-f820ea718d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694379157 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2694379157
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3990330280
Short name T991
Test name
Test status
Simulation time 12813855 ps
CPU time 0.92 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 206904 kb
Host smart-c566b847-1e4e-4d2e-81de-cbe419a8b4ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990330280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3990330280
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2244235553
Short name T1035
Test name
Test status
Simulation time 17730230 ps
CPU time 0.99 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206796 kb
Host smart-76c4963b-6015-48de-a3bc-e64c9b18c968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244235553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2244235553
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3225648153
Short name T1055
Test name
Test status
Simulation time 26539040 ps
CPU time 0.9 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:01 PM PDT 24
Peak memory 207004 kb
Host smart-c8d339c7-071f-45ea-8a82-1d6e81a54959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225648153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3225648153
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.851104525
Short name T1039
Test name
Test status
Simulation time 136618762 ps
CPU time 2.24 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 215204 kb
Host smart-cbf709d0-93c7-4025-adcb-c99ba17ad418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851104525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.851104525
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3874694264
Short name T301
Test name
Test status
Simulation time 463489041 ps
CPU time 2.86 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:48:01 PM PDT 24
Peak memory 215128 kb
Host smart-21d366ca-e49c-413a-a23a-9a67a14d942f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874694264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3874694264
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.782371949
Short name T990
Test name
Test status
Simulation time 82826648 ps
CPU time 1.61 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 215184 kb
Host smart-f2aaa71f-5778-44fe-a8b8-bbe04f3cc112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782371949 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.782371949
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.147679646
Short name T282
Test name
Test status
Simulation time 26295193 ps
CPU time 0.84 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 206972 kb
Host smart-acc38076-9f6d-44b3-97a8-85a11c02db6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147679646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.147679646
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3193869201
Short name T1020
Test name
Test status
Simulation time 42177408 ps
CPU time 0.81 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 206704 kb
Host smart-99521db1-e0c9-4d39-8ba8-6abac027eb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193869201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3193869201
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.187508446
Short name T1037
Test name
Test status
Simulation time 276234381 ps
CPU time 1.55 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 206888 kb
Host smart-64732333-f098-463d-8b9b-aad05c729a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187508446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.187508446
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1498742026
Short name T1056
Test name
Test status
Simulation time 172923008 ps
CPU time 3.19 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 215268 kb
Host smart-81d16fa6-dd08-41f4-a2a3-7f65bfb56110
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498742026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1498742026
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3154668161
Short name T1128
Test name
Test status
Simulation time 102027357 ps
CPU time 2.73 seconds
Started Jul 07 05:48:05 PM PDT 24
Finished Jul 07 05:48:08 PM PDT 24
Peak memory 215148 kb
Host smart-0fc810aa-9bda-4dfd-85cb-983a8336cdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154668161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3154668161
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2513358296
Short name T1119
Test name
Test status
Simulation time 41711772 ps
CPU time 1.31 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 215260 kb
Host smart-527fc691-9564-41e6-8d86-febd53bc092b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513358296 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2513358296
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1277998913
Short name T1007
Test name
Test status
Simulation time 59294501 ps
CPU time 0.88 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 206712 kb
Host smart-cd48fda4-0863-4db9-be76-e40f9e9a0e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277998913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1277998913
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1430703630
Short name T1087
Test name
Test status
Simulation time 17642472 ps
CPU time 0.79 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 206708 kb
Host smart-cbc6a6df-f13f-49fc-8210-10bd54c8c863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430703630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1430703630
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.523356472
Short name T1106
Test name
Test status
Simulation time 32559262 ps
CPU time 1.38 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 206884 kb
Host smart-6dfc6fb6-880f-4a9c-968b-05ad9988c155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523356472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.523356472
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1228584542
Short name T1031
Test name
Test status
Simulation time 65484254 ps
CPU time 3.1 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 215568 kb
Host smart-e425c8f3-a52b-40ad-8d24-8bf24cd5b74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228584542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1228584542
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1243174880
Short name T1054
Test name
Test status
Simulation time 102279662 ps
CPU time 2.8 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 207156 kb
Host smart-32d1b425-6874-4141-a4af-75dd291e1544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243174880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1243174880
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1829805060
Short name T1058
Test name
Test status
Simulation time 97310734 ps
CPU time 1.51 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 219752 kb
Host smart-4bd9f700-729d-4a63-bf4e-d7db2f5ccade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829805060 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1829805060
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3233089269
Short name T1124
Test name
Test status
Simulation time 15070652 ps
CPU time 1 seconds
Started Jul 07 05:48:02 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 206824 kb
Host smart-9aa453ed-1c64-46b4-955f-f1735931966f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233089269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3233089269
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4108033638
Short name T1014
Test name
Test status
Simulation time 62308397 ps
CPU time 0.76 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 206696 kb
Host smart-794343db-60f6-4b57-ac50-ba5aaf7cde08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108033638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4108033638
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2893087250
Short name T1050
Test name
Test status
Simulation time 21306582 ps
CPU time 1.07 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 206944 kb
Host smart-dae67acb-2f18-4b77-b7d9-792d1efcaed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893087250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2893087250
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3209145002
Short name T1110
Test name
Test status
Simulation time 280911446 ps
CPU time 3.7 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 219512 kb
Host smart-b28e5c67-0a9d-413e-8b37-2320eb24fbea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209145002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3209145002
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1602591134
Short name T1126
Test name
Test status
Simulation time 58048965 ps
CPU time 1.84 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 207112 kb
Host smart-9ee4bd89-4306-479e-8259-173021b0e0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602591134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1602591134
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1738920013
Short name T1116
Test name
Test status
Simulation time 21412285 ps
CPU time 1.17 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 215344 kb
Host smart-ac14123b-1cc1-4f4b-9357-fb2fb2df9ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738920013 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1738920013
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3387410823
Short name T1070
Test name
Test status
Simulation time 18074534 ps
CPU time 0.96 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 206932 kb
Host smart-7d97acb5-4b4f-4dbc-96d1-543bdfeb69a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387410823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3387410823
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3744162269
Short name T993
Test name
Test status
Simulation time 16625110 ps
CPU time 0.93 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206864 kb
Host smart-1d8a3a7b-c0bb-49a5-96a1-a7a1130b77fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744162269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3744162269
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1263418955
Short name T1109
Test name
Test status
Simulation time 29201369 ps
CPU time 1.39 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 206856 kb
Host smart-19009f12-3ad2-4c10-b96b-334de5a1af0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263418955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1263418955
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1765758789
Short name T1066
Test name
Test status
Simulation time 46893170 ps
CPU time 2.97 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 215244 kb
Host smart-7a6bc2e8-cb24-46aa-8945-f141c8b7cb58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765758789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1765758789
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.299454064
Short name T1100
Test name
Test status
Simulation time 163833950 ps
CPU time 1.68 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 215552 kb
Host smart-821716ed-6d3a-41d0-ae63-3e2fb972074d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299454064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.299454064
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3103245287
Short name T1003
Test name
Test status
Simulation time 83208475 ps
CPU time 1.19 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 217128 kb
Host smart-73dbe8c0-66d5-408c-a3fc-bbe57b98f3bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103245287 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3103245287
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2020776214
Short name T291
Test name
Test status
Simulation time 31105018 ps
CPU time 0.85 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 207032 kb
Host smart-ad8ff6e0-2843-43c0-81be-d71df42df9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020776214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2020776214
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.399202456
Short name T1041
Test name
Test status
Simulation time 14781266 ps
CPU time 0.79 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:01 PM PDT 24
Peak memory 206868 kb
Host smart-567bd86f-d0a2-44f8-9e2c-90ab21828f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399202456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.399202456
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3958142964
Short name T1107
Test name
Test status
Simulation time 62258532 ps
CPU time 1.11 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206968 kb
Host smart-5d33b06a-0df5-4c09-93bb-8ef749103102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958142964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3958142964
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3886851825
Short name T1080
Test name
Test status
Simulation time 86847258 ps
CPU time 3.08 seconds
Started Jul 07 05:48:00 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 215264 kb
Host smart-33750fef-5023-4c27-a93c-1c5f75b68975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886851825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3886851825
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4147657547
Short name T1095
Test name
Test status
Simulation time 108867399 ps
CPU time 1.76 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206956 kb
Host smart-f94ba09b-2eb0-4eb7-bc91-244621a5452e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147657547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4147657547
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2373327672
Short name T1040
Test name
Test status
Simulation time 26857417 ps
CPU time 1.68 seconds
Started Jul 07 05:48:02 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 215244 kb
Host smart-d4da4728-973e-4c29-86d3-b65c8f092c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373327672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2373327672
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.4177108328
Short name T280
Test name
Test status
Simulation time 54232548 ps
CPU time 0.95 seconds
Started Jul 07 05:48:05 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206900 kb
Host smart-0442288f-3c3d-4d04-b327-fb202e954baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177108328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4177108328
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3930899378
Short name T1081
Test name
Test status
Simulation time 42334786 ps
CPU time 0.78 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206672 kb
Host smart-3b1d3641-6306-4158-9f69-30869b7d355d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930899378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3930899378
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2696324661
Short name T1086
Test name
Test status
Simulation time 15858010 ps
CPU time 1.02 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:02 PM PDT 24
Peak memory 206920 kb
Host smart-5581ece6-eb1a-4f37-9595-91dc2661bca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696324661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2696324661
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3758724296
Short name T996
Test name
Test status
Simulation time 23608474 ps
CPU time 1.54 seconds
Started Jul 07 05:48:02 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 215200 kb
Host smart-79a11e06-50ab-42aa-bfad-30ee82328b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758724296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3758724296
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2045723229
Short name T307
Test name
Test status
Simulation time 314202380 ps
CPU time 2.41 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 215480 kb
Host smart-5e4fa0a9-3742-4aef-b860-2d6aa6af4232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045723229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2045723229
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2345602813
Short name T1078
Test name
Test status
Simulation time 37462444 ps
CPU time 1.08 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 215280 kb
Host smart-eaa67e24-a027-4736-976e-c34fa789bcec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345602813 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2345602813
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.10664141
Short name T1021
Test name
Test status
Simulation time 68081418 ps
CPU time 0.87 seconds
Started Jul 07 05:48:07 PM PDT 24
Finished Jul 07 05:48:09 PM PDT 24
Peak memory 206976 kb
Host smart-11d0a67f-7bc5-4b98-a602-f832fbf9c4e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10664141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.10664141
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1218742293
Short name T992
Test name
Test status
Simulation time 72132115 ps
CPU time 0.84 seconds
Started Jul 07 05:48:08 PM PDT 24
Finished Jul 07 05:48:09 PM PDT 24
Peak memory 206896 kb
Host smart-d6a0a1ef-7395-41d4-b2a7-e8ab1064ecb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218742293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1218742293
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1704717503
Short name T1083
Test name
Test status
Simulation time 90022500 ps
CPU time 1.53 seconds
Started Jul 07 05:48:12 PM PDT 24
Finished Jul 07 05:48:14 PM PDT 24
Peak memory 206920 kb
Host smart-9b9d962d-78e6-4a61-848b-fab53f5904e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704717503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1704717503
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1229008511
Short name T1060
Test name
Test status
Simulation time 87404257 ps
CPU time 3.28 seconds
Started Jul 07 05:48:01 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 215192 kb
Host smart-fd39dfd1-b11a-4e6f-967e-7bc7248bb88a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229008511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1229008511
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3665038367
Short name T310
Test name
Test status
Simulation time 257084326 ps
CPU time 1.72 seconds
Started Jul 07 05:48:08 PM PDT 24
Finished Jul 07 05:48:11 PM PDT 24
Peak memory 215128 kb
Host smart-d9527685-36b1-4c9b-b154-e74624b2c537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665038367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3665038367
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2297016850
Short name T1004
Test name
Test status
Simulation time 24997895 ps
CPU time 1.23 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 206952 kb
Host smart-0fa99461-2e07-4789-b026-8b032b7d5c5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297016850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2297016850
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.396480474
Short name T1113
Test name
Test status
Simulation time 35934358 ps
CPU time 2.07 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 207052 kb
Host smart-153bfaee-6e26-4068-a904-126a06b2d459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396480474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.396480474
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2734477051
Short name T1075
Test name
Test status
Simulation time 23407944 ps
CPU time 0.88 seconds
Started Jul 07 05:47:42 PM PDT 24
Finished Jul 07 05:47:44 PM PDT 24
Peak memory 206872 kb
Host smart-981a3351-bea2-4d05-a6f4-2ad4763c84d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734477051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2734477051
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4057782967
Short name T1015
Test name
Test status
Simulation time 28770080 ps
CPU time 0.99 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:48 PM PDT 24
Peak memory 216860 kb
Host smart-e12e1ee3-c362-441e-827b-e551f807eae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057782967 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4057782967
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3511074100
Short name T285
Test name
Test status
Simulation time 15426506 ps
CPU time 0.96 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 206924 kb
Host smart-f1a2a7bd-8256-4ffa-8b06-4a7d233e5acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511074100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3511074100
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4128092736
Short name T1092
Test name
Test status
Simulation time 36957640 ps
CPU time 0.78 seconds
Started Jul 07 05:47:49 PM PDT 24
Finished Jul 07 05:47:50 PM PDT 24
Peak memory 206684 kb
Host smart-3e23c1de-e63d-4339-a6b4-3d46418a385d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128092736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4128092736
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4200080826
Short name T1025
Test name
Test status
Simulation time 28227724 ps
CPU time 1.11 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 206952 kb
Host smart-66ee5fa9-ca21-41d6-baac-0f25fbca2eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200080826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4200080826
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4031459616
Short name T1069
Test name
Test status
Simulation time 71939143 ps
CPU time 2.78 seconds
Started Jul 07 05:47:42 PM PDT 24
Finished Jul 07 05:47:45 PM PDT 24
Peak memory 215252 kb
Host smart-aa1fe0dd-7634-44fa-a1b5-ed91802bf394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031459616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4031459616
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.59880886
Short name T1120
Test name
Test status
Simulation time 521477805 ps
CPU time 2.26 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:47 PM PDT 24
Peak memory 206740 kb
Host smart-3fcf4064-2b7c-4a03-89e8-113287d42077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59880886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.59880886
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1382847873
Short name T1028
Test name
Test status
Simulation time 201709009 ps
CPU time 0.95 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 206708 kb
Host smart-ef47c3f7-6d05-42eb-991f-c4e52c0450e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382847873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1382847873
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3522172724
Short name T1111
Test name
Test status
Simulation time 117364696 ps
CPU time 0.78 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 206676 kb
Host smart-8255f8dd-c352-4a96-9f0f-df85930a3c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522172724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3522172724
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2133920876
Short name T1024
Test name
Test status
Simulation time 30597831 ps
CPU time 0.79 seconds
Started Jul 07 05:48:08 PM PDT 24
Finished Jul 07 05:48:09 PM PDT 24
Peak memory 206720 kb
Host smart-d4098d53-faee-425c-94a5-51f2f8b89b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133920876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2133920876
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2170299604
Short name T1057
Test name
Test status
Simulation time 16612464 ps
CPU time 0.85 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206848 kb
Host smart-d67e1b74-2144-483f-9236-1af55a5e8806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170299604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2170299604
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2943309985
Short name T1098
Test name
Test status
Simulation time 15949858 ps
CPU time 0.93 seconds
Started Jul 07 05:48:05 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206696 kb
Host smart-51fc928e-8ce6-438f-aaee-e67e4664f09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943309985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2943309985
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.359821105
Short name T1061
Test name
Test status
Simulation time 47629557 ps
CPU time 0.83 seconds
Started Jul 07 05:48:10 PM PDT 24
Finished Jul 07 05:48:11 PM PDT 24
Peak memory 206684 kb
Host smart-8a5aecab-8e64-42db-988d-9bc053fefd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359821105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.359821105
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2629203339
Short name T1013
Test name
Test status
Simulation time 55129605 ps
CPU time 0.87 seconds
Started Jul 07 05:48:07 PM PDT 24
Finished Jul 07 05:48:08 PM PDT 24
Peak memory 206732 kb
Host smart-3d999d7a-7eb1-4d05-8099-4dbab1eb11a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629203339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2629203339
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1580032196
Short name T1012
Test name
Test status
Simulation time 48170815 ps
CPU time 0.91 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206832 kb
Host smart-75a32f98-11a9-4e9c-b96c-8879a7a2f709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580032196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1580032196
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1538607364
Short name T1104
Test name
Test status
Simulation time 27035985 ps
CPU time 0.85 seconds
Started Jul 07 05:48:11 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206696 kb
Host smart-d099e937-2e4c-4e26-99ae-7034038994af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538607364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1538607364
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1517961528
Short name T1114
Test name
Test status
Simulation time 29649859 ps
CPU time 0.91 seconds
Started Jul 07 05:48:05 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206872 kb
Host smart-689fe4e3-780b-4393-a6c6-8c9078ecb007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517961528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1517961528
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1769773778
Short name T281
Test name
Test status
Simulation time 26905128 ps
CPU time 1.04 seconds
Started Jul 07 05:47:48 PM PDT 24
Finished Jul 07 05:47:50 PM PDT 24
Peak memory 206916 kb
Host smart-e91d5d6d-ecd7-4d0a-87c9-cd6186b2a2cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769773778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1769773778
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2947944787
Short name T1072
Test name
Test status
Simulation time 119418851 ps
CPU time 3.1 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:48 PM PDT 24
Peak memory 206920 kb
Host smart-8fb81328-ddc7-4deb-85a8-0e885739a992
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947944787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2947944787
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1842474821
Short name T286
Test name
Test status
Simulation time 33029329 ps
CPU time 1.03 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 207208 kb
Host smart-6300bd60-ef12-49fc-91b9-5ee632b76034
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842474821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1842474821
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2228085498
Short name T1062
Test name
Test status
Simulation time 102819338 ps
CPU time 1.15 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:44 PM PDT 24
Peak memory 215196 kb
Host smart-8ffa776e-85dd-45b0-aafc-657df9b41833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228085498 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2228085498
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1956479632
Short name T1009
Test name
Test status
Simulation time 14010290 ps
CPU time 0.94 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:45 PM PDT 24
Peak memory 206880 kb
Host smart-3d47d87f-a2ca-4597-99e2-d170d06bc8bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956479632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1956479632
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4081734930
Short name T1122
Test name
Test status
Simulation time 15801515 ps
CPU time 0.91 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:45 PM PDT 24
Peak memory 206864 kb
Host smart-43b2bda7-d79b-4032-9b37-23126a6e57a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081734930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4081734930
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3953233585
Short name T1103
Test name
Test status
Simulation time 69510384 ps
CPU time 1.1 seconds
Started Jul 07 05:47:49 PM PDT 24
Finished Jul 07 05:47:50 PM PDT 24
Peak memory 206916 kb
Host smart-7517cda0-1007-4e89-89ec-6d3093225daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953233585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3953233585
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2727166188
Short name T1071
Test name
Test status
Simulation time 60878847 ps
CPU time 2.54 seconds
Started Jul 07 05:47:46 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 215184 kb
Host smart-e4f5bc89-5fe8-4db4-806a-5ce5a19e9776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727166188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2727166188
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1865204410
Short name T303
Test name
Test status
Simulation time 152939634 ps
CPU time 2.26 seconds
Started Jul 07 05:47:44 PM PDT 24
Finished Jul 07 05:47:47 PM PDT 24
Peak memory 206948 kb
Host smart-634e56c6-d094-4df2-8749-2e31cbe4ac77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865204410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1865204410
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.881311161
Short name T1076
Test name
Test status
Simulation time 53711457 ps
CPU time 0.93 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206840 kb
Host smart-2faba093-274a-4c03-b0e4-3a2ab429afac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881311161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.881311161
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3947214540
Short name T1033
Test name
Test status
Simulation time 41478796 ps
CPU time 0.83 seconds
Started Jul 07 05:48:09 PM PDT 24
Finished Jul 07 05:48:10 PM PDT 24
Peak memory 206936 kb
Host smart-3b0116da-aba9-4448-a907-b3df1732cc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947214540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3947214540
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.951113924
Short name T1105
Test name
Test status
Simulation time 71595527 ps
CPU time 0.78 seconds
Started Jul 07 05:48:12 PM PDT 24
Finished Jul 07 05:48:13 PM PDT 24
Peak memory 206700 kb
Host smart-73a3a11d-5aba-4e07-ad97-6e590fe84111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951113924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.951113924
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3878143999
Short name T1093
Test name
Test status
Simulation time 40714104 ps
CPU time 0.86 seconds
Started Jul 07 05:48:04 PM PDT 24
Finished Jul 07 05:48:06 PM PDT 24
Peak memory 206892 kb
Host smart-fd5cba75-9075-42eb-8fb9-070414efb63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878143999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3878143999
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2689543996
Short name T1117
Test name
Test status
Simulation time 25727573 ps
CPU time 0.91 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206800 kb
Host smart-db56a742-ba04-4b09-b120-152758719542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689543996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2689543996
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1950493920
Short name T1034
Test name
Test status
Simulation time 23832295 ps
CPU time 0.86 seconds
Started Jul 07 05:48:06 PM PDT 24
Finished Jul 07 05:48:07 PM PDT 24
Peak memory 206800 kb
Host smart-86cab27a-5c45-4cc6-ab9c-fe7a655423bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950493920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1950493920
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1833666797
Short name T1002
Test name
Test status
Simulation time 28106826 ps
CPU time 0.89 seconds
Started Jul 07 05:48:09 PM PDT 24
Finished Jul 07 05:48:10 PM PDT 24
Peak memory 206792 kb
Host smart-7c152417-e952-4ba6-99b8-d22ae81b1b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833666797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1833666797
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2930982784
Short name T1029
Test name
Test status
Simulation time 43234486 ps
CPU time 0.91 seconds
Started Jul 07 05:48:13 PM PDT 24
Finished Jul 07 05:48:15 PM PDT 24
Peak memory 206876 kb
Host smart-e3777ffe-0eff-40a2-b98f-8f07674a638d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930982784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2930982784
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.779979418
Short name T1030
Test name
Test status
Simulation time 38031388 ps
CPU time 0.85 seconds
Started Jul 07 05:48:08 PM PDT 24
Finished Jul 07 05:48:09 PM PDT 24
Peak memory 206728 kb
Host smart-72d6716d-41d8-4963-97b3-2c6092107580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779979418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.779979418
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.515376372
Short name T1045
Test name
Test status
Simulation time 39486647 ps
CPU time 0.82 seconds
Started Jul 07 05:48:14 PM PDT 24
Finished Jul 07 05:48:15 PM PDT 24
Peak memory 206720 kb
Host smart-aab19728-2623-4225-8837-a55cd056a959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515376372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.515376372
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2786461117
Short name T290
Test name
Test status
Simulation time 77247511 ps
CPU time 1.01 seconds
Started Jul 07 05:47:49 PM PDT 24
Finished Jul 07 05:47:50 PM PDT 24
Peak memory 207004 kb
Host smart-e688dc27-ece4-4ccc-96a1-3e2ed05e5918
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786461117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2786461117
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2651560269
Short name T1051
Test name
Test status
Simulation time 874566146 ps
CPU time 6.22 seconds
Started Jul 07 05:47:46 PM PDT 24
Finished Jul 07 05:47:53 PM PDT 24
Peak memory 206916 kb
Host smart-09d3e488-fc1b-4918-bd41-b88f0a1c22e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651560269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2651560269
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1042098463
Short name T1067
Test name
Test status
Simulation time 106222065 ps
CPU time 0.91 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 207036 kb
Host smart-70a9e7f3-ad96-442a-9173-94d8a1416031
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042098463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1042098463
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1667257364
Short name T1017
Test name
Test status
Simulation time 120414911 ps
CPU time 1.49 seconds
Started Jul 07 05:47:46 PM PDT 24
Finished Jul 07 05:47:48 PM PDT 24
Peak memory 215184 kb
Host smart-9b5a1d9e-e55e-4e1b-b557-62e4456a6aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667257364 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1667257364
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1675947504
Short name T289
Test name
Test status
Simulation time 58909227 ps
CPU time 1 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:48 PM PDT 24
Peak memory 206924 kb
Host smart-47a21f4f-f748-4a23-a59f-6bf22bc82f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675947504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1675947504
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1612663064
Short name T1000
Test name
Test status
Simulation time 32706616 ps
CPU time 0.94 seconds
Started Jul 07 05:47:51 PM PDT 24
Finished Jul 07 05:47:53 PM PDT 24
Peak memory 206904 kb
Host smart-866863c5-b658-481c-8b66-2ccb453d2129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612663064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1612663064
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1678818761
Short name T1112
Test name
Test status
Simulation time 29153966 ps
CPU time 1.07 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:48 PM PDT 24
Peak memory 206936 kb
Host smart-95fba484-0eef-44da-a52e-51f86f9e2501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678818761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1678818761
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1012357494
Short name T1097
Test name
Test status
Simulation time 81471043 ps
CPU time 3.05 seconds
Started Jul 07 05:47:43 PM PDT 24
Finished Jul 07 05:47:46 PM PDT 24
Peak memory 215260 kb
Host smart-261231db-4fd5-4be4-969c-5e631b15e49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012357494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1012357494
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3192915932
Short name T1074
Test name
Test status
Simulation time 160489314 ps
CPU time 2.5 seconds
Started Jul 07 05:47:51 PM PDT 24
Finished Jul 07 05:47:54 PM PDT 24
Peak memory 207024 kb
Host smart-1cf5ba48-5cb5-4c5f-98aa-83cb7b7077c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192915932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3192915932
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2324057204
Short name T1089
Test name
Test status
Simulation time 36135924 ps
CPU time 0.83 seconds
Started Jul 07 05:48:11 PM PDT 24
Finished Jul 07 05:48:13 PM PDT 24
Peak memory 206696 kb
Host smart-2c554722-c380-4f63-95cc-36804c8fe1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324057204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2324057204
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2714890426
Short name T997
Test name
Test status
Simulation time 13964932 ps
CPU time 0.88 seconds
Started Jul 07 05:48:09 PM PDT 24
Finished Jul 07 05:48:10 PM PDT 24
Peak memory 206820 kb
Host smart-d6de099f-a628-49f7-b503-e913d0a87096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714890426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2714890426
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2983553197
Short name T1043
Test name
Test status
Simulation time 39267025 ps
CPU time 0.81 seconds
Started Jul 07 05:48:11 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206736 kb
Host smart-d26303ee-872b-4956-aa58-4a07c1a297c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983553197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2983553197
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1530911004
Short name T1096
Test name
Test status
Simulation time 24488092 ps
CPU time 0.86 seconds
Started Jul 07 05:48:11 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206764 kb
Host smart-12dbb46b-c6bd-4252-8201-6d139b9a4688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530911004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1530911004
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2927117364
Short name T1082
Test name
Test status
Simulation time 24999934 ps
CPU time 0.89 seconds
Started Jul 07 05:48:12 PM PDT 24
Finished Jul 07 05:48:14 PM PDT 24
Peak memory 206800 kb
Host smart-0f4a36ba-e8f0-432d-be80-fbc41940311f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927117364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2927117364
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.861931194
Short name T1094
Test name
Test status
Simulation time 108625728 ps
CPU time 0.87 seconds
Started Jul 07 05:48:10 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206892 kb
Host smart-8b2356e7-9705-4138-87af-d5afc9838406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861931194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.861931194
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1760655290
Short name T1049
Test name
Test status
Simulation time 12789603 ps
CPU time 0.85 seconds
Started Jul 07 05:48:10 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206812 kb
Host smart-f1d0de7b-6745-46a0-9062-55792013a00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760655290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1760655290
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2770252688
Short name T1053
Test name
Test status
Simulation time 26220326 ps
CPU time 0.9 seconds
Started Jul 07 05:48:10 PM PDT 24
Finished Jul 07 05:48:11 PM PDT 24
Peak memory 206816 kb
Host smart-1e01740d-58d3-4cfa-8ab4-d49b85fd957c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770252688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2770252688
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1408591636
Short name T1001
Test name
Test status
Simulation time 26013588 ps
CPU time 0.92 seconds
Started Jul 07 05:48:11 PM PDT 24
Finished Jul 07 05:48:12 PM PDT 24
Peak memory 206844 kb
Host smart-e1a9d5a1-7e5c-40dd-9b32-36109baafb54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408591636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1408591636
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.692752637
Short name T1016
Test name
Test status
Simulation time 51999015 ps
CPU time 0.88 seconds
Started Jul 07 05:48:13 PM PDT 24
Finished Jul 07 05:48:14 PM PDT 24
Peak memory 206844 kb
Host smart-76974941-fd49-4a68-a9eb-4e837a683612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692752637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.692752637
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.12451963
Short name T1065
Test name
Test status
Simulation time 18668988 ps
CPU time 1.08 seconds
Started Jul 07 05:47:52 PM PDT 24
Finished Jul 07 05:47:53 PM PDT 24
Peak memory 215184 kb
Host smart-ab65819f-4ab3-4605-ba15-6418c6510f90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12451963 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.12451963
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.989006644
Short name T1047
Test name
Test status
Simulation time 15295236 ps
CPU time 0.87 seconds
Started Jul 07 05:47:50 PM PDT 24
Finished Jul 07 05:47:51 PM PDT 24
Peak memory 206744 kb
Host smart-5a17b2cd-d33f-4788-ac38-2142e197d841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989006644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.989006644
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3623152484
Short name T1052
Test name
Test status
Simulation time 11833041 ps
CPU time 0.95 seconds
Started Jul 07 05:47:48 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 206868 kb
Host smart-d216a7ba-6699-4d43-84c4-17d8be4b0be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623152484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3623152484
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1650311616
Short name T1019
Test name
Test status
Simulation time 35227025 ps
CPU time 1.47 seconds
Started Jul 07 05:47:50 PM PDT 24
Finished Jul 07 05:47:52 PM PDT 24
Peak memory 206880 kb
Host smart-3f5ae815-ca25-4ca8-aefe-a52b3c08b013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650311616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1650311616
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.61519853
Short name T1121
Test name
Test status
Simulation time 96520616 ps
CPU time 3.17 seconds
Started Jul 07 05:47:51 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 215180 kb
Host smart-9bf3c63d-0a70-41e7-9530-5c6b949cbf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61519853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.61519853
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3633166496
Short name T1063
Test name
Test status
Simulation time 87861368 ps
CPU time 1.64 seconds
Started Jul 07 05:47:47 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 215144 kb
Host smart-2fc8931e-5daa-45ef-910f-220a41234c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633166496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3633166496
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3047659567
Short name T1115
Test name
Test status
Simulation time 57378540 ps
CPU time 1.41 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 215100 kb
Host smart-4beed9bf-6e85-4908-ac01-d11f5b6f093e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047659567 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3047659567
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2561237190
Short name T294
Test name
Test status
Simulation time 47861750 ps
CPU time 0.89 seconds
Started Jul 07 05:47:52 PM PDT 24
Finished Jul 07 05:47:53 PM PDT 24
Peak memory 206924 kb
Host smart-2fafe550-70bd-4942-bd77-b05eb29d0232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561237190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2561237190
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3857945148
Short name T1008
Test name
Test status
Simulation time 31316099 ps
CPU time 0.82 seconds
Started Jul 07 05:47:54 PM PDT 24
Finished Jul 07 05:47:56 PM PDT 24
Peak memory 206696 kb
Host smart-a2285b16-1740-468a-90b4-9d60c2158482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857945148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3857945148
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1252759218
Short name T1018
Test name
Test status
Simulation time 44753264 ps
CPU time 1.09 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206860 kb
Host smart-98194c9e-c5ed-47ea-8660-099c9511d4c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252759218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1252759218
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3048974107
Short name T1099
Test name
Test status
Simulation time 117948705 ps
CPU time 2.24 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:56 PM PDT 24
Peak memory 215152 kb
Host smart-9a1ad38d-8453-4b1e-bc1d-8adc25850d21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048974107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3048974107
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3900562207
Short name T302
Test name
Test status
Simulation time 89003260 ps
CPU time 1.69 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:56 PM PDT 24
Peak memory 206968 kb
Host smart-a8c3e0e7-3b20-48c0-95f7-dd22b9332e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900562207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3900562207
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.93906545
Short name T1084
Test name
Test status
Simulation time 30911687 ps
CPU time 1.2 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 215160 kb
Host smart-fa7ac878-7f91-4c2a-91bb-e080c9f78dee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93906545 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.93906545
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3966643548
Short name T1088
Test name
Test status
Simulation time 19241077 ps
CPU time 0.79 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206604 kb
Host smart-3bfd26bb-5f6e-4ac3-83ea-d23fe656bc33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966643548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3966643548
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1803102818
Short name T296
Test name
Test status
Simulation time 28295738 ps
CPU time 1.03 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 206892 kb
Host smart-2608a972-597f-4070-9ef1-8f7791327320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803102818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1803102818
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.716206310
Short name T1125
Test name
Test status
Simulation time 284715235 ps
CPU time 3.59 seconds
Started Jul 07 05:47:50 PM PDT 24
Finished Jul 07 05:47:54 PM PDT 24
Peak memory 215204 kb
Host smart-86389a54-d4ad-4ecd-b10b-a61a18210ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716206310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.716206310
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2896070892
Short name T1129
Test name
Test status
Simulation time 56964391 ps
CPU time 1.97 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 215036 kb
Host smart-105a118c-27b0-4d77-b3fd-4264e249a933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896070892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2896070892
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1472772882
Short name T1101
Test name
Test status
Simulation time 92032847 ps
CPU time 1.31 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 215328 kb
Host smart-92ac4ef6-ce0c-4a75-a452-56de6da19ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472772882 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1472772882
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4263929022
Short name T1046
Test name
Test status
Simulation time 19944394 ps
CPU time 0.86 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206884 kb
Host smart-d51041f8-5dac-457c-bf68-7b1e1dffea10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263929022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4263929022
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2367865457
Short name T1023
Test name
Test status
Simulation time 151219662 ps
CPU time 0.83 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 206664 kb
Host smart-3333326c-097c-4d4c-bdd2-eb663ee5ee53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367865457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2367865457
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3423675023
Short name T295
Test name
Test status
Simulation time 65262852 ps
CPU time 1.46 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 206912 kb
Host smart-41e3a950-d813-4867-bb19-fcb70a75c782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423675023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3423675023
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.917483085
Short name T998
Test name
Test status
Simulation time 21848938 ps
CPU time 1.62 seconds
Started Jul 07 05:47:50 PM PDT 24
Finished Jul 07 05:47:52 PM PDT 24
Peak memory 215268 kb
Host smart-6c119022-0069-4feb-ab0b-c595f8a04535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917483085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.917483085
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2275277551
Short name T1085
Test name
Test status
Simulation time 286802534 ps
CPU time 2.06 seconds
Started Jul 07 05:47:58 PM PDT 24
Finished Jul 07 05:48:01 PM PDT 24
Peak memory 206960 kb
Host smart-78117809-dedc-4b79-a559-e56181207c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275277551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2275277551
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2287989944
Short name T1064
Test name
Test status
Simulation time 23717660 ps
CPU time 1.17 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:05 PM PDT 24
Peak memory 223344 kb
Host smart-eb5c780e-3ce5-4883-933a-c3151eea3a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287989944 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2287989944
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3048231488
Short name T1022
Test name
Test status
Simulation time 13988962 ps
CPU time 0.91 seconds
Started Jul 07 05:48:03 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 206936 kb
Host smart-8d5635a8-7134-43be-a33b-ba95852e0e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048231488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3048231488
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1551758481
Short name T1077
Test name
Test status
Simulation time 33572631 ps
CPU time 0.89 seconds
Started Jul 07 05:47:57 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 206848 kb
Host smart-1e31704d-bbf9-45a6-ab49-44743f67071a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551758481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1551758481
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1019875032
Short name T292
Test name
Test status
Simulation time 23244810 ps
CPU time 1.17 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 206968 kb
Host smart-c02a26f4-6c42-4b19-a773-410fd79e5859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019875032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1019875032
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.591973514
Short name T995
Test name
Test status
Simulation time 119313343 ps
CPU time 3.55 seconds
Started Jul 07 05:47:53 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 215148 kb
Host smart-f86281a9-f8de-4612-b519-aa66aa69d20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591973514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.591973514
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.82287499
Short name T1090
Test name
Test status
Simulation time 77662720 ps
CPU time 2.35 seconds
Started Jul 07 05:47:56 PM PDT 24
Finished Jul 07 05:47:59 PM PDT 24
Peak memory 207368 kb
Host smart-d204d25e-a918-4845-9e4c-4902e5410192
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82287499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.82287499
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3986457592
Short name T550
Test name
Test status
Simulation time 86720711 ps
CPU time 1.14 seconds
Started Jul 07 05:49:21 PM PDT 24
Finished Jul 07 05:49:22 PM PDT 24
Peak memory 219608 kb
Host smart-64d78703-2b61-4871-9288-c53093b368c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986457592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3986457592
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2908413178
Short name T962
Test name
Test status
Simulation time 84791015 ps
CPU time 0.88 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 05:49:25 PM PDT 24
Peak memory 207068 kb
Host smart-b5953cf2-47d1-4ad5-a10b-06c588a933a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908413178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2908413178
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.3820249214
Short name T152
Test name
Test status
Simulation time 37831471 ps
CPU time 1.23 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 05:49:25 PM PDT 24
Peak memory 230056 kb
Host smart-4569fd49-c8f6-4649-87f2-4cb2dd026a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820249214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3820249214
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1371132717
Short name T415
Test name
Test status
Simulation time 40617812 ps
CPU time 1.32 seconds
Started Jul 07 05:49:28 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 218840 kb
Host smart-9399e44b-5f2a-4713-9f33-f5a923c4abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371132717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1371132717
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2176216116
Short name T522
Test name
Test status
Simulation time 24722166 ps
CPU time 0.96 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 215940 kb
Host smart-c83b9b90-473a-4c2d-a18d-93804fbc0a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176216116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2176216116
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2084320533
Short name T781
Test name
Test status
Simulation time 39302427 ps
CPU time 0.95 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:24 PM PDT 24
Peak memory 207408 kb
Host smart-67e707fe-261c-4356-8d66-14884bb6ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084320533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2084320533
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2355121358
Short name T73
Test name
Test status
Simulation time 1697621014 ps
CPU time 7.43 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:30 PM PDT 24
Peak memory 236944 kb
Host smart-88ceef78-9917-4c00-a08d-0d40f0d0a9c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355121358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2355121358
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2742324457
Short name T515
Test name
Test status
Simulation time 43684396 ps
CPU time 0.92 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:23 PM PDT 24
Peak memory 215584 kb
Host smart-db3b313f-df4d-47ce-adee-38d0d791a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742324457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2742324457
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.495269496
Short name T83
Test name
Test status
Simulation time 129484939 ps
CPU time 3.02 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:26 PM PDT 24
Peak memory 215660 kb
Host smart-d6ce2bdc-a2e2-4e3f-8f6e-c7280167b928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495269496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.495269496
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1371862556
Short name T249
Test name
Test status
Simulation time 76759520816 ps
CPU time 854.71 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 06:03:38 PM PDT 24
Peak memory 221476 kb
Host smart-a50137b6-44d7-423c-8b50-34e5639c8c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371862556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1371862556
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2885858402
Short name T418
Test name
Test status
Simulation time 47811982 ps
CPU time 0.94 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 05:49:25 PM PDT 24
Peak memory 215192 kb
Host smart-60869db7-7f9c-4fda-a6f3-b86e14efbc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885858402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2885858402
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.807615212
Short name T155
Test name
Test status
Simulation time 63558039 ps
CPU time 1.22 seconds
Started Jul 07 05:49:28 PM PDT 24
Finished Jul 07 05:49:30 PM PDT 24
Peak memory 217068 kb
Host smart-0fbd4c98-d77e-4346-b4e2-d272f35c8b5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807615212 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.807615212
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.510436407
Short name T182
Test name
Test status
Simulation time 21899248 ps
CPU time 1.05 seconds
Started Jul 07 05:49:26 PM PDT 24
Finished Jul 07 05:49:28 PM PDT 24
Peak memory 224264 kb
Host smart-627fe895-023b-46d3-af2f-3721686f7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510436407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.510436407
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.525514769
Short name T664
Test name
Test status
Simulation time 213221697 ps
CPU time 1.49 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:49:24 PM PDT 24
Peak memory 220960 kb
Host smart-fa9ce100-716a-41ba-b8c7-520b8661a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525514769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.525514769
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3960343273
Short name T60
Test name
Test status
Simulation time 22219572 ps
CPU time 1.2 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 224296 kb
Host smart-87a9fcf1-63a2-4c9c-a51f-d7d26e77d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960343273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3960343273
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2452250460
Short name T31
Test name
Test status
Simulation time 36933204 ps
CPU time 0.91 seconds
Started Jul 07 05:49:21 PM PDT 24
Finished Jul 07 05:49:22 PM PDT 24
Peak memory 207380 kb
Host smart-2b71cc39-b6e7-498b-94f6-e7dec0a594e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452250460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2452250460
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.2142904288
Short name T647
Test name
Test status
Simulation time 44604224 ps
CPU time 0.91 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 05:49:24 PM PDT 24
Peak memory 215660 kb
Host smart-b02502c1-b1b2-4688-881f-bdb71de03746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142904288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2142904288
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2999009998
Short name T645
Test name
Test status
Simulation time 186594846 ps
CPU time 2.7 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 217572 kb
Host smart-ed1e274c-d68d-4fde-a1af-7e5e544b5fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999009998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2999009998
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2749198415
Short name T558
Test name
Test status
Simulation time 18431748129 ps
CPU time 452.36 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 05:56:55 PM PDT 24
Peak memory 224000 kb
Host smart-004ef4a4-6ccd-4f0a-8a89-41f60593ff2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749198415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2749198415
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.1688069880
Short name T924
Test name
Test status
Simulation time 11301742 ps
CPU time 0.91 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 207124 kb
Host smart-400357ee-6f19-4218-936d-107c36c5cd8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688069880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1688069880
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1199838453
Short name T837
Test name
Test status
Simulation time 21409774 ps
CPU time 0.92 seconds
Started Jul 07 05:49:43 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 216224 kb
Host smart-f641608c-507b-48a4-b9a9-62db0a019017
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199838453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1199838453
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.4274634322
Short name T776
Test name
Test status
Simulation time 38998367 ps
CPU time 1.03 seconds
Started Jul 07 05:49:43 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 224240 kb
Host smart-52a09171-f057-4628-b8ef-7d2a40050d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274634322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4274634322
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2738219720
Short name T53
Test name
Test status
Simulation time 66933881 ps
CPU time 1.04 seconds
Started Jul 07 05:49:48 PM PDT 24
Finished Jul 07 05:49:49 PM PDT 24
Peak memory 217780 kb
Host smart-08c0b1eb-169d-434b-adb1-c075aefd38a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738219720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2738219720
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.3636389997
Short name T363
Test name
Test status
Simulation time 15566195 ps
CPU time 1 seconds
Started Jul 07 05:49:48 PM PDT 24
Finished Jul 07 05:49:49 PM PDT 24
Peak memory 215648 kb
Host smart-d074f366-c362-4379-880e-c208c17072ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636389997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3636389997
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1005192791
Short name T263
Test name
Test status
Simulation time 143316983 ps
CPU time 2.01 seconds
Started Jul 07 05:49:43 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 215572 kb
Host smart-f0a8db6c-9519-431c-8d5e-8fc9dcdd5c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005192791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1005192791
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4279373400
Short name T399
Test name
Test status
Simulation time 18940026457 ps
CPU time 416.24 seconds
Started Jul 07 05:49:49 PM PDT 24
Finished Jul 07 05:56:45 PM PDT 24
Peak memory 218068 kb
Host smart-6547a679-cb32-4d21-89b8-3724421557cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279373400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4279373400
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.299867509
Short name T723
Test name
Test status
Simulation time 61570605 ps
CPU time 1.14 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 219436 kb
Host smart-e563a3b6-f2d4-41a5-ab47-860ed816d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299867509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.299867509
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3499493676
Short name T687
Test name
Test status
Simulation time 35460195 ps
CPU time 1.16 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 217660 kb
Host smart-c2fd24ec-c538-4a57-a810-859db3f656e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499493676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3499493676
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.334122253
Short name T586
Test name
Test status
Simulation time 90641410 ps
CPU time 1.1 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 218688 kb
Host smart-ed14f969-9625-436d-a988-1bbb38c51b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334122253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.334122253
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2587137112
Short name T577
Test name
Test status
Simulation time 178964692 ps
CPU time 1.3 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 217684 kb
Host smart-83761d23-b4a9-40de-90b5-83911918a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587137112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2587137112
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3177231208
Short name T929
Test name
Test status
Simulation time 22955018 ps
CPU time 1.19 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 219912 kb
Host smart-94fcaf14-bdb5-42d4-ac5a-3336afd28d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177231208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3177231208
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.1921616098
Short name T546
Test name
Test status
Simulation time 135549518 ps
CPU time 1.11 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 217500 kb
Host smart-2b74d815-ca6d-4ed4-91b2-f7c84381780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921616098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1921616098
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1406576114
Short name T683
Test name
Test status
Simulation time 21882675 ps
CPU time 1.12 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 220124 kb
Host smart-07d9bab7-cdf3-4622-a309-4b249c499e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406576114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1406576114
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.4228886167
Short name T766
Test name
Test status
Simulation time 84759085 ps
CPU time 1.18 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 217664 kb
Host smart-ee1d3bdb-3ef1-4b52-80f3-5d56ffe953e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228886167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4228886167
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3215342731
Short name T740
Test name
Test status
Simulation time 74514962 ps
CPU time 1.19 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 220236 kb
Host smart-2a0fecc9-dedb-4d4d-acc0-f0c868277a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215342731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3215342731
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.573318841
Short name T436
Test name
Test status
Simulation time 69815357 ps
CPU time 1.19 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 217660 kb
Host smart-64a9edb3-34e3-4304-aa4a-b59c9f05255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573318841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.573318841
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.460585731
Short name T825
Test name
Test status
Simulation time 76978393 ps
CPU time 1.23 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 220148 kb
Host smart-ad7020fc-73d0-42c2-a447-14b9d30c9c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460585731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.460585731
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.216342412
Short name T634
Test name
Test status
Simulation time 67226221 ps
CPU time 1.23 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 219012 kb
Host smart-28593e0d-070e-498b-a8a7-7057b2443849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216342412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.216342412
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1365743669
Short name T373
Test name
Test status
Simulation time 233254966 ps
CPU time 1.42 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 218976 kb
Host smart-38dfb4a4-0168-4622-8e0d-53fa5962f7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365743669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1365743669
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2432819798
Short name T576
Test name
Test status
Simulation time 88106808 ps
CPU time 1.2 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 218672 kb
Host smart-e4fa9994-37d9-4341-b0a6-209d1f3eb649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432819798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2432819798
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.746145974
Short name T854
Test name
Test status
Simulation time 37069941 ps
CPU time 1.22 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 220188 kb
Host smart-734da41f-8821-4296-b42c-a9ed22ca7000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746145974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.746145974
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1841014064
Short name T20
Test name
Test status
Simulation time 53801311 ps
CPU time 1.31 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 220580 kb
Host smart-0b4ea70e-35c0-48a6-86e6-fdec29afb027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841014064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1841014064
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1194739803
Short name T650
Test name
Test status
Simulation time 45782822 ps
CPU time 1.39 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 219596 kb
Host smart-e47c99e5-b4a6-4f47-abd4-307708672ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194739803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1194739803
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4197189360
Short name T861
Test name
Test status
Simulation time 93011294 ps
CPU time 1.17 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 218740 kb
Host smart-bd71d301-32eb-4b9d-bd74-c392b3eb328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197189360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4197189360
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.60905210
Short name T655
Test name
Test status
Simulation time 221758655 ps
CPU time 3.02 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 219148 kb
Host smart-295bde97-53b5-4398-b55d-1ff500099960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60905210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.60905210
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2608554352
Short name T511
Test name
Test status
Simulation time 40685388 ps
CPU time 1.08 seconds
Started Jul 07 05:49:50 PM PDT 24
Finished Jul 07 05:49:51 PM PDT 24
Peak memory 215300 kb
Host smart-d2a73663-13d7-4006-9563-0f4fd9390165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608554352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2608554352
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3661221556
Short name T223
Test name
Test status
Simulation time 39428158 ps
CPU time 0.86 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 216328 kb
Host smart-c98ebf32-132a-49e5-b838-ef0f81bd954e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661221556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3661221556
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2188636892
Short name T821
Test name
Test status
Simulation time 48264110 ps
CPU time 1.13 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 219032 kb
Host smart-a65c094d-167a-41e5-b4ae-4e3ae60f792d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188636892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2188636892
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1274049043
Short name T231
Test name
Test status
Simulation time 59168989 ps
CPU time 0.88 seconds
Started Jul 07 05:49:50 PM PDT 24
Finished Jul 07 05:49:51 PM PDT 24
Peak memory 218628 kb
Host smart-fd008e39-2418-4312-a6d8-84fdb4f6a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274049043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1274049043
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.366778494
Short name T491
Test name
Test status
Simulation time 64438158 ps
CPU time 1.3 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 218636 kb
Host smart-aad2d72e-2e26-4512-b072-80ab33a2c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366778494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.366778494
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1576341996
Short name T603
Test name
Test status
Simulation time 54520641 ps
CPU time 0.92 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:52 PM PDT 24
Peak memory 215524 kb
Host smart-1185f8f3-63a8-448d-82c7-d95c73796ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576341996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1576341996
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.44128025
Short name T901
Test name
Test status
Simulation time 83026510 ps
CPU time 1.03 seconds
Started Jul 07 05:49:48 PM PDT 24
Finished Jul 07 05:49:49 PM PDT 24
Peak memory 215644 kb
Host smart-976bffac-02c8-46a9-922d-78c576e22cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44128025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.44128025
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2575820462
Short name T681
Test name
Test status
Simulation time 965825634 ps
CPU time 2.43 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 217784 kb
Host smart-8e293380-fc1d-4bed-8272-f84c7f8f5c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575820462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2575820462
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2382508560
Short name T668
Test name
Test status
Simulation time 44639553255 ps
CPU time 884.47 seconds
Started Jul 07 05:49:49 PM PDT 24
Finished Jul 07 06:04:34 PM PDT 24
Peak memory 219640 kb
Host smart-d9fd3f95-f8c5-4492-9a03-670372376719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382508560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2382508560
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.589821007
Short name T233
Test name
Test status
Simulation time 87885637 ps
CPU time 1.21 seconds
Started Jul 07 05:51:29 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 219308 kb
Host smart-5be99436-783d-4ae4-b72d-ff599fc98aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589821007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.589821007
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1910983827
Short name T356
Test name
Test status
Simulation time 219916716 ps
CPU time 1.04 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 217588 kb
Host smart-37426265-a6b1-404b-a5cb-33370c2df5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910983827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1910983827
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4068096205
Short name T341
Test name
Test status
Simulation time 40933111 ps
CPU time 1.22 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 219836 kb
Host smart-885365c9-1c2a-49d2-9ba7-195c804ce946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068096205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4068096205
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3636097611
Short name T329
Test name
Test status
Simulation time 30513574 ps
CPU time 1.3 seconds
Started Jul 07 05:51:29 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 220348 kb
Host smart-ddfa0042-7af0-4e84-9c9f-7f1872fe330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636097611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3636097611
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1708105997
Short name T911
Test name
Test status
Simulation time 27836089 ps
CPU time 1.26 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219592 kb
Host smart-f5092269-0af7-4063-886a-3532cd9fb214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708105997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1708105997
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3797626581
Short name T982
Test name
Test status
Simulation time 34593317 ps
CPU time 1.3 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218612 kb
Host smart-863fb7fc-9b78-4d29-885a-115c8d14bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797626581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3797626581
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1408602237
Short name T779
Test name
Test status
Simulation time 30877628 ps
CPU time 1.27 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 215968 kb
Host smart-0f62e39a-45a9-428b-9780-de56469c186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408602237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1408602237
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.3606600731
Short name T797
Test name
Test status
Simulation time 24254670 ps
CPU time 1.16 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 220128 kb
Host smart-5b41c5c4-e3e9-4032-ac17-b6bff20d6f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606600731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3606600731
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.585078999
Short name T337
Test name
Test status
Simulation time 124926214 ps
CPU time 2.83 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 220484 kb
Host smart-501315c4-17c2-4a33-894a-b8c451858ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585078999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.585078999
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4240963510
Short name T501
Test name
Test status
Simulation time 29641616 ps
CPU time 1.34 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 219740 kb
Host smart-d3df67af-24f8-405d-9eca-f276fb9daafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240963510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4240963510
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.3710843657
Short name T850
Test name
Test status
Simulation time 28373156 ps
CPU time 1.19 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 218880 kb
Host smart-02fa9e43-5a7e-4e1b-a29b-41ed9778f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710843657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3710843657
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1696455378
Short name T937
Test name
Test status
Simulation time 185194513 ps
CPU time 1.77 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 218908 kb
Host smart-bd9a4a64-a9e1-432f-abe0-ab14b1e97ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696455378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1696455378
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2657937490
Short name T932
Test name
Test status
Simulation time 37143383 ps
CPU time 1.13 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218888 kb
Host smart-672b2460-17d6-40e5-9b80-65058c0b5d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657937490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2657937490
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1463477070
Short name T461
Test name
Test status
Simulation time 36885424 ps
CPU time 1.23 seconds
Started Jul 07 05:51:19 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 219176 kb
Host smart-12ffd30c-555c-49b7-8f22-17d3b5235763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463477070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1463477070
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3835632183
Short name T196
Test name
Test status
Simulation time 45293089 ps
CPU time 1.18 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 220420 kb
Host smart-95d394c4-a103-4dc4-87f1-b856bf826bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835632183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3835632183
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.924684684
Short name T582
Test name
Test status
Simulation time 131412769 ps
CPU time 1.72 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219312 kb
Host smart-4e74ba64-27a2-4c64-a402-7ccb6992bc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924684684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.924684684
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3927016462
Short name T166
Test name
Test status
Simulation time 37489589 ps
CPU time 1.21 seconds
Started Jul 07 05:49:47 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 220460 kb
Host smart-24914465-5801-4824-9c03-8023bb53a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927016462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3927016462
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1917592564
Short name T508
Test name
Test status
Simulation time 13688684 ps
CPU time 0.87 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 207036 kb
Host smart-7a993533-99c1-4930-b6b2-76532277a3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917592564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1917592564
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.987172846
Short name T761
Test name
Test status
Simulation time 24443491 ps
CPU time 0.88 seconds
Started Jul 07 05:49:45 PM PDT 24
Finished Jul 07 05:49:47 PM PDT 24
Peak memory 216260 kb
Host smart-a83acece-3e51-410a-85fc-84a9aa6fd6b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987172846 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.987172846
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.118940866
Short name T9
Test name
Test status
Simulation time 36246660 ps
CPU time 1.21 seconds
Started Jul 07 05:49:49 PM PDT 24
Finished Jul 07 05:49:51 PM PDT 24
Peak memory 217264 kb
Host smart-603e1dfd-a057-4290-a2b9-8eef2b3a4f0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118940866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.118940866
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.95500253
Short name T488
Test name
Test status
Simulation time 86058133 ps
CPU time 1.01 seconds
Started Jul 07 05:49:50 PM PDT 24
Finished Jul 07 05:49:51 PM PDT 24
Peak memory 218896 kb
Host smart-0e4a3969-3c1c-4b76-920d-24ce389d12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95500253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.95500253
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.2754325334
Short name T127
Test name
Test status
Simulation time 30794789 ps
CPU time 0.83 seconds
Started Jul 07 05:49:52 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 215900 kb
Host smart-8960b0ec-75cf-4cc9-8ffa-15ccbb1f4f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754325334 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2754325334
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3539867890
Short name T812
Test name
Test status
Simulation time 28287193 ps
CPU time 0.97 seconds
Started Jul 07 05:49:47 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 215640 kb
Host smart-79514031-5760-4bc9-beaa-7583567eb601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539867890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3539867890
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3795807305
Short name T361
Test name
Test status
Simulation time 249504010 ps
CPU time 2.91 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 217692 kb
Host smart-6b0f5f3e-5b61-4811-953f-82a057beb892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795807305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3795807305
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3981130992
Short name T241
Test name
Test status
Simulation time 56992219346 ps
CPU time 1354.77 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 06:12:29 PM PDT 24
Peak memory 221040 kb
Host smart-491868ab-6afd-40b6-8996-436d3b4f2b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981130992 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3981130992
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.29922859
Short name T884
Test name
Test status
Simulation time 99576503 ps
CPU time 1.2 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 217744 kb
Host smart-044a7c49-7afd-4047-bd3c-05da3ea47635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29922859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.29922859
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1965602331
Short name T629
Test name
Test status
Simulation time 184879239 ps
CPU time 1.08 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 218844 kb
Host smart-bb25d191-bad4-4055-bd06-9c1ee19ccc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965602331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1965602331
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3786801516
Short name T794
Test name
Test status
Simulation time 91877749 ps
CPU time 1.14 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 219200 kb
Host smart-35216cd5-a01d-4b9a-92c7-4273c44ceafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786801516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3786801516
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1108763345
Short name T71
Test name
Test status
Simulation time 132588844 ps
CPU time 1.2 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 218944 kb
Host smart-710a80fb-f1ba-4168-b795-d0041518b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108763345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1108763345
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2963963699
Short name T254
Test name
Test status
Simulation time 37905811 ps
CPU time 1.31 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 220024 kb
Host smart-94f2f851-ad2f-478e-8d14-fa31ec8ad82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963963699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2963963699
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2357449164
Short name T505
Test name
Test status
Simulation time 229163520 ps
CPU time 1.28 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 218708 kb
Host smart-75f5a66b-1253-4dff-90bb-eb2615d54e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357449164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2357449164
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3925915406
Short name T339
Test name
Test status
Simulation time 41133339 ps
CPU time 1.29 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 217784 kb
Host smart-67c9b91b-ba4c-44f3-a829-0ff00c65af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925915406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3925915406
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3218852457
Short name T268
Test name
Test status
Simulation time 110025083 ps
CPU time 2.46 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 220332 kb
Host smart-0814f661-cae0-4590-b4e9-e6db5b57fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218852457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3218852457
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.849587242
Short name T694
Test name
Test status
Simulation time 135815691 ps
CPU time 1.16 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 218856 kb
Host smart-de172582-9fff-4e63-885d-b936145008b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849587242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.849587242
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.65450285
Short name T784
Test name
Test status
Simulation time 65859107 ps
CPU time 1.3 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 220224 kb
Host smart-043c4878-11ed-4853-9c7a-ba9e54584185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65450285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.65450285
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1148037428
Short name T312
Test name
Test status
Simulation time 72160351 ps
CPU time 1.1 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 219044 kb
Host smart-3d93de43-5cc3-4f10-9411-45097d610593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148037428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1148037428
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.4225771049
Short name T492
Test name
Test status
Simulation time 57933467 ps
CPU time 1.32 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 217588 kb
Host smart-b7b070af-bac9-464d-82aa-39f6d3e1d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225771049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4225771049
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2075504673
Short name T907
Test name
Test status
Simulation time 65146453 ps
CPU time 1.19 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219824 kb
Host smart-ba9aad89-fdd4-4e89-90c4-5c147953b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075504673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2075504673
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.200116547
Short name T360
Test name
Test status
Simulation time 41628962 ps
CPU time 1.42 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 218940 kb
Host smart-27350529-f247-40ca-95d2-bf7f4753b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200116547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.200116547
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.4231173442
Short name T908
Test name
Test status
Simulation time 22543446 ps
CPU time 1.18 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 221172 kb
Host smart-107ae0cf-94c2-44f1-ac9c-5503f8542c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231173442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4231173442
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3870822005
Short name T238
Test name
Test status
Simulation time 48132652 ps
CPU time 1.75 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 220536 kb
Host smart-9b350ed4-24ef-4c89-824b-b96b0e5892be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870822005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3870822005
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.878768873
Short name T968
Test name
Test status
Simulation time 26620181 ps
CPU time 1.22 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 215992 kb
Host smart-e35d3d96-736b-4e69-9248-1b74f012313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878768873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.878768873
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1524198492
Short name T709
Test name
Test status
Simulation time 36426002 ps
CPU time 1.33 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219104 kb
Host smart-e74ea4db-1b91-4f29-90ca-c1c01be53f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524198492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1524198492
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1058475236
Short name T370
Test name
Test status
Simulation time 33856994 ps
CPU time 0.89 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 207072 kb
Host smart-3d5454d8-6534-4554-af3e-ba46fc574d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058475236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1058475236
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.93296103
Short name T74
Test name
Test status
Simulation time 10397730 ps
CPU time 0.9 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 216228 kb
Host smart-3273a469-dc85-4e8e-84fa-9868235424a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93296103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.93296103
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3784395767
Short name T112
Test name
Test status
Simulation time 87974582 ps
CPU time 1.07 seconds
Started Jul 07 05:49:47 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 217324 kb
Host smart-6485fe0e-f8af-47db-b28e-0fa1a32d4e09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784395767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3784395767
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3736093614
Short name T62
Test name
Test status
Simulation time 23281102 ps
CPU time 1.05 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 223732 kb
Host smart-b27dc3e2-a0c4-4576-a30b-fed0b50df1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736093614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3736093614
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.827943380
Short name T824
Test name
Test status
Simulation time 39100722 ps
CPU time 1.69 seconds
Started Jul 07 05:49:48 PM PDT 24
Finished Jul 07 05:49:50 PM PDT 24
Peak memory 219144 kb
Host smart-42ec8a5b-f33f-4481-a9e3-ce7d44363961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827943380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.827943380
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.298148438
Short name T614
Test name
Test status
Simulation time 25393333 ps
CPU time 0.96 seconds
Started Jul 07 05:49:49 PM PDT 24
Finished Jul 07 05:49:50 PM PDT 24
Peak memory 215724 kb
Host smart-862ad5b9-c5eb-4d13-bf23-96fb85a00cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298148438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.298148438
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3419768078
Short name T364
Test name
Test status
Simulation time 102844111 ps
CPU time 0.91 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 215596 kb
Host smart-fc8a87b4-6718-4345-9e2c-5d67d6f94e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419768078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3419768078
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3653336458
Short name T767
Test name
Test status
Simulation time 302711991 ps
CPU time 1.34 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 217720 kb
Host smart-0017164c-34bf-4d42-90a2-07e6bec081e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653336458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3653336458
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3025979831
Short name T523
Test name
Test status
Simulation time 382160178645 ps
CPU time 1741.56 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 06:18:55 PM PDT 24
Peak memory 226088 kb
Host smart-8ac8c9ed-99b0-4270-af05-602660f133b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025979831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3025979831
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.305059060
Short name T498
Test name
Test status
Simulation time 44771070 ps
CPU time 1.17 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 218860 kb
Host smart-f11fb5db-5e34-495e-ba61-bf9c284c90ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305059060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.305059060
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2771198085
Short name T755
Test name
Test status
Simulation time 76676554 ps
CPU time 1.32 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 219072 kb
Host smart-360cf881-1c13-4fe3-8810-4804225055ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771198085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2771198085
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1461724892
Short name T713
Test name
Test status
Simulation time 68425757 ps
CPU time 1.05 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219284 kb
Host smart-75f9a12f-5ac3-45cf-b52f-ba863df31744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461724892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1461724892
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.3196150808
Short name T737
Test name
Test status
Simulation time 106830092 ps
CPU time 1.19 seconds
Started Jul 07 05:51:30 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 219500 kb
Host smart-f00eb99d-c968-4a18-816a-959e43141ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196150808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3196150808
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1829804601
Short name T306
Test name
Test status
Simulation time 29209158 ps
CPU time 1.02 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 217468 kb
Host smart-3fe5c819-11a0-49c8-a987-39861d93002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829804601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1829804601
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.4293706828
Short name T276
Test name
Test status
Simulation time 103335222 ps
CPU time 1.19 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 221052 kb
Host smart-4eb57e60-7ab6-48cd-9309-d45f0e20b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293706828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.4293706828
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1063875169
Short name T483
Test name
Test status
Simulation time 25319260 ps
CPU time 1.15 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 218756 kb
Host smart-643f810e-601a-4e4e-a50a-68b89404bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063875169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1063875169
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1600078547
Short name T516
Test name
Test status
Simulation time 268245463 ps
CPU time 1.2 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 221088 kb
Host smart-a4f0c77e-f6c5-4c37-97aa-c3c46f5ebec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600078547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1600078547
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3574185682
Short name T732
Test name
Test status
Simulation time 80005512 ps
CPU time 1.18 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 217520 kb
Host smart-e4f55eaf-c147-4cfa-85ba-f104e7b28046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574185682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3574185682
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1691239957
Short name T279
Test name
Test status
Simulation time 224561274 ps
CPU time 1.04 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 220972 kb
Host smart-d9b27bec-3550-4d8c-9dc8-2c28ab44610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691239957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1691239957
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2580340319
Short name T663
Test name
Test status
Simulation time 29293625 ps
CPU time 1.27 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 220144 kb
Host smart-52ab0046-0956-41a2-be0c-78d580c9dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580340319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2580340319
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1963230113
Short name T783
Test name
Test status
Simulation time 83361757 ps
CPU time 1.17 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219148 kb
Host smart-ab7b8c78-14fb-444c-97a5-1e8841bf51ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963230113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1963230113
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3370017459
Short name T933
Test name
Test status
Simulation time 133476183 ps
CPU time 1.03 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 217716 kb
Host smart-64031d1f-db96-4055-ba13-dd4b06b46b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370017459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3370017459
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2532623084
Short name T180
Test name
Test status
Simulation time 39093974 ps
CPU time 1.16 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 219184 kb
Host smart-4089b73d-581a-4ba1-ac5f-ced2182ffd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532623084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2532623084
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2806289198
Short name T390
Test name
Test status
Simulation time 126976191 ps
CPU time 1.05 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 217692 kb
Host smart-f02e0528-6e89-4134-b2cd-ac740a7ec1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806289198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2806289198
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3156223559
Short name T914
Test name
Test status
Simulation time 107957529 ps
CPU time 1.31 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 215828 kb
Host smart-e45f0421-e99e-4526-93c6-262fabe1950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156223559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3156223559
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1497085097
Short name T520
Test name
Test status
Simulation time 26155003 ps
CPU time 1.27 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 218960 kb
Host smart-c2fae022-6f62-4cf6-bd08-b53e3d7d8689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497085097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1497085097
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1687492267
Short name T125
Test name
Test status
Simulation time 25359423 ps
CPU time 1.29 seconds
Started Jul 07 05:51:26 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 220796 kb
Host smart-eaefe117-5a5c-4c9d-ada8-4bfa445a4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687492267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1687492267
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2258401941
Short name T49
Test name
Test status
Simulation time 33368689 ps
CPU time 1.42 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 218900 kb
Host smart-21b986c7-8340-4017-a3d0-772bbe392de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258401941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2258401941
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.1258670903
Short name T489
Test name
Test status
Simulation time 22106362 ps
CPU time 1.03 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 207000 kb
Host smart-c8a7c5da-ae54-48d3-8b56-b2c349249046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258670903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1258670903
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.962460831
Short name T422
Test name
Test status
Simulation time 20139358 ps
CPU time 0.87 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 216272 kb
Host smart-889db689-5bf8-4f56-8b6a-eaa69b480895
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962460831 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.962460831
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1747495192
Short name T131
Test name
Test status
Simulation time 28627971 ps
CPU time 1.18 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 217348 kb
Host smart-07cd41b4-5009-48ca-91a8-50d9fa50bfa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747495192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1747495192
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.987798417
Short name T639
Test name
Test status
Simulation time 22826801 ps
CPU time 1 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 218948 kb
Host smart-12087283-75b8-4fb3-bdd2-2af4b3aa1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987798417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.987798417
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2713774939
Short name T673
Test name
Test status
Simulation time 75383534 ps
CPU time 1.13 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 217352 kb
Host smart-d94f2c8e-687f-4299-a93c-4c2f61d58e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713774939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2713774939
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.511567753
Short name T819
Test name
Test status
Simulation time 30966126 ps
CPU time 1.01 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 215884 kb
Host smart-e244cd5c-411a-4d3e-ac6b-7103e2d76e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511567753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.511567753
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.523332843
Short name T698
Test name
Test status
Simulation time 24339133 ps
CPU time 0.97 seconds
Started Jul 07 05:49:49 PM PDT 24
Finished Jul 07 05:49:50 PM PDT 24
Peak memory 215600 kb
Host smart-20a0aa01-6baf-46a7-960b-1675decfeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523332843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.523332843
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3165151388
Short name T691
Test name
Test status
Simulation time 66506198384 ps
CPU time 379.74 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 218384 kb
Host smart-50c6ba52-4f34-4491-a70e-402051ef930e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165151388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3165151388
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.4260434655
Short name T236
Test name
Test status
Simulation time 67059618 ps
CPU time 1.17 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 218840 kb
Host smart-edbd594c-175e-4781-94ef-d041a163659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260434655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4260434655
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1992139350
Short name T554
Test name
Test status
Simulation time 90999630 ps
CPU time 1.23 seconds
Started Jul 07 05:51:29 PM PDT 24
Finished Jul 07 05:51:31 PM PDT 24
Peak memory 219504 kb
Host smart-ee892b46-ffb9-45aa-afb5-fa362c210088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992139350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1992139350
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.489534703
Short name T525
Test name
Test status
Simulation time 84834795 ps
CPU time 1.17 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 220088 kb
Host smart-315ab944-3ef6-43a3-8351-73936ac7f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489534703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.489534703
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1697688929
Short name T28
Test name
Test status
Simulation time 42028376 ps
CPU time 1.54 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 218564 kb
Host smart-1f194c7e-a6d1-4413-a234-3b394ac012d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697688929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1697688929
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1474279067
Short name T619
Test name
Test status
Simulation time 248359060 ps
CPU time 1.13 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 217740 kb
Host smart-057e8de7-3651-486d-b9fd-070d2ee9b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474279067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1474279067
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1257482345
Short name T150
Test name
Test status
Simulation time 331972899 ps
CPU time 1.16 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 219980 kb
Host smart-35f10990-0e05-4b44-9dad-a326590214c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257482345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1257482345
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.974397866
Short name T782
Test name
Test status
Simulation time 52621611 ps
CPU time 1.5 seconds
Started Jul 07 05:51:30 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 218676 kb
Host smart-879a33e5-fdaa-4107-9b93-8f9cd3efa931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974397866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.974397866
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.851204551
Short name T972
Test name
Test status
Simulation time 23173506 ps
CPU time 1.14 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 218788 kb
Host smart-66064b5c-9503-4ed8-a926-44fca8df92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851204551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.851204551
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3717757752
Short name T979
Test name
Test status
Simulation time 28348958 ps
CPU time 1.26 seconds
Started Jul 07 05:51:34 PM PDT 24
Finished Jul 07 05:51:36 PM PDT 24
Peak memory 220080 kb
Host smart-6876fe63-ecf5-4de5-8797-3daccc0ac2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717757752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3717757752
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.834366730
Short name T666
Test name
Test status
Simulation time 41586580 ps
CPU time 1.17 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 221208 kb
Host smart-7170e1a1-191e-4977-bf83-d25e90db5210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834366730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.834366730
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.514747047
Short name T471
Test name
Test status
Simulation time 57402957 ps
CPU time 1.26 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:36 PM PDT 24
Peak memory 217796 kb
Host smart-c9b129a3-8bb9-42cc-bf86-70df17562901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514747047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.514747047
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.4068062298
Short name T93
Test name
Test status
Simulation time 56229621 ps
CPU time 1.29 seconds
Started Jul 07 05:51:29 PM PDT 24
Finished Jul 07 05:51:31 PM PDT 24
Peak memory 216012 kb
Host smart-790db7d0-4f0e-4311-9b80-4e42dfd8a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068062298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.4068062298
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1870194103
Short name T541
Test name
Test status
Simulation time 22262265 ps
CPU time 1.08 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:36 PM PDT 24
Peak memory 217708 kb
Host smart-429c3ae7-a6b0-4093-925d-b018ec4f01bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870194103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1870194103
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3763677873
Short name T944
Test name
Test status
Simulation time 79895115 ps
CPU time 1.16 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 220100 kb
Host smart-105f8e2e-cbcb-4e4f-bd9c-18d004c4131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763677873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3763677873
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3354069811
Short name T736
Test name
Test status
Simulation time 44958728 ps
CPU time 1.57 seconds
Started Jul 07 05:51:30 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 218696 kb
Host smart-fe37dba0-4459-4719-9f27-1f44e10ef1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354069811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3354069811
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.390990384
Short name T91
Test name
Test status
Simulation time 24780154 ps
CPU time 1.24 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:32 PM PDT 24
Peak memory 219644 kb
Host smart-0254fc5a-e314-453f-b6b2-e840cfa97ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390990384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.390990384
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.604627045
Short name T704
Test name
Test status
Simulation time 43471964 ps
CPU time 1.59 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 219280 kb
Host smart-e3df22a7-461e-4ec5-bf10-ec7bab04796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604627045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.604627045
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2630032773
Short name T807
Test name
Test status
Simulation time 26902744 ps
CPU time 1.18 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:40 PM PDT 24
Peak memory 219984 kb
Host smart-b8c54b98-2642-4a9c-a377-eacfdb70925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630032773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2630032773
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2348615217
Short name T725
Test name
Test status
Simulation time 24062077 ps
CPU time 1.35 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 219104 kb
Host smart-9f1f25c6-4efa-432d-8f6f-e3885885408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348615217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2348615217
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3469322179
Short name T315
Test name
Test status
Simulation time 50371244 ps
CPU time 1.23 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 215940 kb
Host smart-3cb73c5a-6989-4849-8945-d221041128e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469322179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3469322179
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3935296426
Short name T406
Test name
Test status
Simulation time 15926977 ps
CPU time 0.94 seconds
Started Jul 07 05:49:52 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 215128 kb
Host smart-028a0ae5-2bd9-4e60-a441-8eb658bfe79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935296426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3935296426
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4178769552
Short name T899
Test name
Test status
Simulation time 11540248 ps
CPU time 0.87 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:52 PM PDT 24
Peak memory 216208 kb
Host smart-b01ab1d3-aca9-4078-b8ef-0209bb8b93b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178769552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4178769552
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.3278967979
Short name T357
Test name
Test status
Simulation time 41519064 ps
CPU time 1.09 seconds
Started Jul 07 05:49:52 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 220120 kb
Host smart-7a36f755-4177-43d9-aefa-09ae2ea6b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278967979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3278967979
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.33110228
Short name T718
Test name
Test status
Simulation time 72728906 ps
CPU time 1.17 seconds
Started Jul 07 05:49:52 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 219088 kb
Host smart-6d31785a-44b7-416d-a899-29a4bed8e6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33110228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.33110228
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2380482173
Short name T799
Test name
Test status
Simulation time 31269389 ps
CPU time 0.98 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 05:49:54 PM PDT 24
Peak memory 215636 kb
Host smart-3e78a5d0-4e80-41bc-a86c-88cc27e25791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380482173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2380482173
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3255572941
Short name T746
Test name
Test status
Simulation time 141613419 ps
CPU time 2.07 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 217556 kb
Host smart-4747cded-be1f-4026-a3bc-68078b52a44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255572941 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3255572941
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3014857235
Short name T389
Test name
Test status
Simulation time 147592702694 ps
CPU time 931.73 seconds
Started Jul 07 05:49:57 PM PDT 24
Finished Jul 07 06:05:30 PM PDT 24
Peak memory 223896 kb
Host smart-fdc2d814-4413-40e7-930f-e8ee584ff232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014857235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3014857235
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2017257644
Short name T871
Test name
Test status
Simulation time 69093498 ps
CPU time 1.12 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 220644 kb
Host smart-deeddbe3-4019-4b68-af4b-0a6f751629ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017257644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2017257644
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3343423162
Short name T672
Test name
Test status
Simulation time 52839587 ps
CPU time 1.71 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 218952 kb
Host smart-a7355998-88c7-470b-bc1c-2ba8d7c1c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343423162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3343423162
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1358544189
Short name T707
Test name
Test status
Simulation time 28622774 ps
CPU time 1.24 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 220088 kb
Host smart-2eedd146-725b-4a16-bad0-743b69d820d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358544189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1358544189
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3286529172
Short name T472
Test name
Test status
Simulation time 51055102 ps
CPU time 1.46 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 218996 kb
Host smart-621f3ff4-c964-43f7-b020-ea19e99df314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286529172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3286529172
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1239052000
Short name T792
Test name
Test status
Simulation time 79193410 ps
CPU time 1.22 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 219656 kb
Host smart-06c1486c-6433-4190-b00a-a2cdf9098176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239052000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1239052000
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.795349636
Short name T889
Test name
Test status
Simulation time 64403069 ps
CPU time 1.04 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 217572 kb
Host smart-8876b9e9-0390-44e8-bef4-721e55f62082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795349636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.795349636
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3468589879
Short name T958
Test name
Test status
Simulation time 230627793 ps
CPU time 1.56 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 216028 kb
Host smart-e135d663-1181-4023-8040-da97c785e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468589879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3468589879
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.579558655
Short name T330
Test name
Test status
Simulation time 57579359 ps
CPU time 1.34 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 218008 kb
Host smart-72e207e1-c51e-4333-a5b9-e896f23b03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579558655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.579558655
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.593548518
Short name T870
Test name
Test status
Simulation time 23814175 ps
CPU time 1.21 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 220124 kb
Host smart-4f12f52f-891b-4fe5-88ab-17a4db840daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593548518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.593548518
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1033442383
Short name T325
Test name
Test status
Simulation time 117932565 ps
CPU time 1.2 seconds
Started Jul 07 05:51:34 PM PDT 24
Finished Jul 07 05:51:36 PM PDT 24
Peak memory 219984 kb
Host smart-55a75196-8bb3-483d-af89-853fd925ab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033442383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1033442383
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1635573111
Short name T758
Test name
Test status
Simulation time 44144556 ps
CPU time 1.22 seconds
Started Jul 07 05:51:31 PM PDT 24
Finished Jul 07 05:51:33 PM PDT 24
Peak memory 219068 kb
Host smart-c00270c3-2c29-443a-aa64-defe72bd4038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635573111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1635573111
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1306139679
Short name T839
Test name
Test status
Simulation time 53222191 ps
CPU time 1.44 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 218788 kb
Host smart-5e5640e0-179f-44af-b693-b71ff2189d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306139679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1306139679
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2373198093
Short name T232
Test name
Test status
Simulation time 25176626 ps
CPU time 1.29 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 220036 kb
Host smart-1745d8bb-4a13-493d-ae07-80cbbf79b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373198093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2373198093
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.748647462
Short name T532
Test name
Test status
Simulation time 49554143 ps
CPU time 1.53 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 218716 kb
Host smart-d9039743-9cc1-4a9e-ba62-2d82648458db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748647462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.748647462
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3435027978
Short name T842
Test name
Test status
Simulation time 138071713 ps
CPU time 1.42 seconds
Started Jul 07 05:51:32 PM PDT 24
Finished Jul 07 05:51:34 PM PDT 24
Peak memory 218956 kb
Host smart-e9e7f2d3-b8bf-4cad-8330-903616da0e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435027978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3435027978
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3718271468
Short name T909
Test name
Test status
Simulation time 85987254 ps
CPU time 3.33 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 218952 kb
Host smart-faf1398c-34a2-47a7-83d4-f1e2c42464b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718271468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3718271468
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.4284100928
Short name T809
Test name
Test status
Simulation time 22717388 ps
CPU time 1.14 seconds
Started Jul 07 05:51:33 PM PDT 24
Finished Jul 07 05:51:35 PM PDT 24
Peak memory 219100 kb
Host smart-1673e6fc-fcb7-4ad5-8ce4-2ac9fbc762ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284100928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.4284100928
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1488433005
Short name T795
Test name
Test status
Simulation time 61473374 ps
CPU time 2.18 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 220484 kb
Host smart-c3ca58d1-21d6-4306-9810-ad58bd1f74df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488433005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1488433005
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3979736512
Short name T852
Test name
Test status
Simulation time 148247526 ps
CPU time 0.97 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 217532 kb
Host smart-e905d9af-4d83-46be-a124-4bc1ae16fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979736512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3979736512
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.320274232
Short name T305
Test name
Test status
Simulation time 57654352 ps
CPU time 1.1 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 218872 kb
Host smart-268a4347-e2dc-4513-abea-ac89728ffcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320274232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.320274232
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3232245078
Short name T446
Test name
Test status
Simulation time 10559307 ps
CPU time 0.87 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 207104 kb
Host smart-daccba11-a221-4985-93b8-bcf06695f222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232245078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3232245078
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.820605950
Short name T171
Test name
Test status
Simulation time 35340845 ps
CPU time 0.86 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 216480 kb
Host smart-48fe2b3b-a3c0-47aa-ad40-c91f8c31f307
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820605950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.820605950
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.347000894
Short name T952
Test name
Test status
Simulation time 17975485 ps
CPU time 1.07 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 217024 kb
Host smart-718f63ea-bd56-48ae-a57d-d92511c66ad9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347000894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.347000894
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1424119310
Short name T16
Test name
Test status
Simulation time 19624705 ps
CPU time 1.14 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 224272 kb
Host smart-7413d380-d2c2-4dc2-83ef-6adf1e3b6269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424119310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1424119310
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3621555389
Short name T385
Test name
Test status
Simulation time 235239108 ps
CPU time 1.26 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 217744 kb
Host smart-5170700a-36f1-41f1-82bb-89beb4bfe8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621555389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3621555389
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2633028859
Short name T935
Test name
Test status
Simulation time 22109375 ps
CPU time 1.21 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 224292 kb
Host smart-eb80a44b-fc76-4ad2-984d-13fcbf026a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633028859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2633028859
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4146189943
Short name T649
Test name
Test status
Simulation time 37898208 ps
CPU time 0.95 seconds
Started Jul 07 05:49:51 PM PDT 24
Finished Jul 07 05:49:53 PM PDT 24
Peak memory 215620 kb
Host smart-53398e2f-edaa-405d-b225-4964d57a0533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146189943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4146189943
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1712720888
Short name T401
Test name
Test status
Simulation time 583723262 ps
CPU time 2.8 seconds
Started Jul 07 05:49:52 PM PDT 24
Finished Jul 07 05:49:55 PM PDT 24
Peak memory 217688 kb
Host smart-caaf1042-940f-4994-aada-74b922bf28e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712720888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1712720888
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1731491017
Short name T244
Test name
Test status
Simulation time 55645084614 ps
CPU time 1196.27 seconds
Started Jul 07 05:49:53 PM PDT 24
Finished Jul 07 06:09:50 PM PDT 24
Peak memory 221660 kb
Host smart-915f821b-6955-4f60-be28-8efb79b3f38e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731491017 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1731491017
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.314971443
Short name T138
Test name
Test status
Simulation time 75047220 ps
CPU time 1.31 seconds
Started Jul 07 05:51:41 PM PDT 24
Finished Jul 07 05:51:42 PM PDT 24
Peak memory 219860 kb
Host smart-64422e5b-cf2e-49f9-83d9-1bf7dd7b6e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314971443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.314971443
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.122364127
Short name T921
Test name
Test status
Simulation time 49741311 ps
CPU time 2.06 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 218948 kb
Host smart-5f063484-a743-464a-ae50-54d32058fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122364127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.122364127
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2234177817
Short name T313
Test name
Test status
Simulation time 130773858 ps
CPU time 1.18 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 220988 kb
Host smart-f52c0e3a-7f00-4da1-aa5f-cb11dd941c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234177817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2234177817
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.882881233
Short name T703
Test name
Test status
Simulation time 56318093 ps
CPU time 2.21 seconds
Started Jul 07 05:51:37 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 217892 kb
Host smart-91011321-a94b-4e33-8bd5-9a44f901bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882881233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.882881233
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2819069586
Short name T621
Test name
Test status
Simulation time 28450919 ps
CPU time 1.26 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:40 PM PDT 24
Peak memory 218668 kb
Host smart-d3e2e8ed-8302-4174-b240-b1e565fcbe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819069586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2819069586
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1622192226
Short name T985
Test name
Test status
Simulation time 64331239 ps
CPU time 1.18 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:39 PM PDT 24
Peak memory 219304 kb
Host smart-fe51e779-9b67-4333-a054-05cd1bae1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622192226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1622192226
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1509711402
Short name T965
Test name
Test status
Simulation time 36241885 ps
CPU time 1.31 seconds
Started Jul 07 05:51:39 PM PDT 24
Finished Jul 07 05:51:40 PM PDT 24
Peak memory 220240 kb
Host smart-083e16c5-787b-49df-b0a6-32989c9c396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509711402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1509711402
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1977174429
Short name T104
Test name
Test status
Simulation time 47414115 ps
CPU time 1.9 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:40 PM PDT 24
Peak memory 217588 kb
Host smart-0dfce5c4-8b10-4399-b58e-f7ff56b68a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977174429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1977174429
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2602196221
Short name T804
Test name
Test status
Simulation time 73252221 ps
CPU time 1.21 seconds
Started Jul 07 05:51:39 PM PDT 24
Finished Jul 07 05:51:41 PM PDT 24
Peak memory 218988 kb
Host smart-eb650060-6f3c-43ae-ae96-aaf54ee8fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602196221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2602196221
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3547538352
Short name T813
Test name
Test status
Simulation time 34835684 ps
CPU time 1.35 seconds
Started Jul 07 05:51:37 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 219084 kb
Host smart-378640ea-ee62-441a-a739-07061e02ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547538352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3547538352
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2051390865
Short name T788
Test name
Test status
Simulation time 80322616 ps
CPU time 1.12 seconds
Started Jul 07 05:51:35 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 220104 kb
Host smart-8c9332df-837b-4c25-972b-3fd701de4c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051390865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2051390865
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1368144193
Short name T100
Test name
Test status
Simulation time 62373283 ps
CPU time 1.33 seconds
Started Jul 07 05:51:37 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 217836 kb
Host smart-d2863285-217b-49ab-8a40-fcb1e83597ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368144193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1368144193
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1892986263
Short name T157
Test name
Test status
Simulation time 108065745 ps
CPU time 1.27 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:37 PM PDT 24
Peak memory 220232 kb
Host smart-5b95c249-2d33-44bd-aff1-05f1fe903485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892986263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1892986263
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.723996114
Short name T417
Test name
Test status
Simulation time 45293822 ps
CPU time 1.47 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 217732 kb
Host smart-c4783dc4-bcc7-4ef8-b125-be32c0bfec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723996114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.723996114
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1463826731
Short name T297
Test name
Test status
Simulation time 42306531 ps
CPU time 1.19 seconds
Started Jul 07 05:51:36 PM PDT 24
Finished Jul 07 05:51:38 PM PDT 24
Peak memory 219596 kb
Host smart-f9d26d24-0c62-47a5-bd9e-4094b0a10e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463826731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1463826731
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3883350738
Short name T85
Test name
Test status
Simulation time 92142537 ps
CPU time 1.39 seconds
Started Jul 07 05:51:39 PM PDT 24
Finished Jul 07 05:51:41 PM PDT 24
Peak memory 219220 kb
Host smart-7a52fdcf-e5d6-4dce-8b64-ddbb1f38ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883350738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3883350738
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1683696876
Short name T481
Test name
Test status
Simulation time 43629843 ps
CPU time 1.19 seconds
Started Jul 07 05:51:41 PM PDT 24
Finished Jul 07 05:51:42 PM PDT 24
Peak memory 218924 kb
Host smart-692637ff-d591-4f62-a66f-acac80bd7125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683696876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1683696876
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1774279320
Short name T473
Test name
Test status
Simulation time 72381745 ps
CPU time 1.39 seconds
Started Jul 07 05:51:42 PM PDT 24
Finished Jul 07 05:51:44 PM PDT 24
Peak memory 218940 kb
Host smart-d6836d6d-5a84-4c31-9fae-cc4ac046e53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774279320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1774279320
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.951633127
Short name T828
Test name
Test status
Simulation time 30836635 ps
CPU time 1.27 seconds
Started Jul 07 05:51:42 PM PDT 24
Finished Jul 07 05:51:44 PM PDT 24
Peak memory 219828 kb
Host smart-c2c0e49e-36a4-4452-9c0e-d7c2555db574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951633127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.951633127
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.558704617
Short name T457
Test name
Test status
Simulation time 35703971 ps
CPU time 1.25 seconds
Started Jul 07 05:51:41 PM PDT 24
Finished Jul 07 05:51:43 PM PDT 24
Peak memory 220132 kb
Host smart-0cfa5b29-0e40-4913-9faf-f8eaec21f706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558704617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.558704617
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3731486516
Short name T910
Test name
Test status
Simulation time 182822543 ps
CPU time 1.24 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 216036 kb
Host smart-aecfd397-9db8-45db-bc37-642019b6ceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731486516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3731486516
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1121265341
Short name T964
Test name
Test status
Simulation time 52187001 ps
CPU time 0.87 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:57 PM PDT 24
Peak memory 207020 kb
Host smart-798581c9-1aa7-4edd-9ac7-e1a96385e694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121265341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1121265341
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2636649318
Short name T686
Test name
Test status
Simulation time 10959951 ps
CPU time 0.9 seconds
Started Jul 07 05:49:59 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 215744 kb
Host smart-c9a62464-6a04-4af1-acf2-4041c3fdd304
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636649318 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2636649318
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1822144688
Short name T542
Test name
Test status
Simulation time 48929836 ps
CPU time 1.13 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 05:49:56 PM PDT 24
Peak memory 217276 kb
Host smart-b22f4fe9-1d16-4415-a091-8d84c32d6f6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822144688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1822144688
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.500279426
Short name T64
Test name
Test status
Simulation time 19120165 ps
CPU time 1.24 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:59 PM PDT 24
Peak memory 224260 kb
Host smart-87dd576a-6dd6-49dc-a528-0be35b29f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500279426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.500279426
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2894843615
Short name T526
Test name
Test status
Simulation time 73763680 ps
CPU time 1 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 217692 kb
Host smart-6d73162a-6a05-4355-a4c4-7188b6697a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894843615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2894843615
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.809211954
Short name T862
Test name
Test status
Simulation time 26345124 ps
CPU time 1.11 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 224380 kb
Host smart-b850217f-3bd1-4860-b0ea-e9c705f5fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809211954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.809211954
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3759671071
Short name T594
Test name
Test status
Simulation time 42692805 ps
CPU time 0.98 seconds
Started Jul 07 05:49:58 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 215668 kb
Host smart-59d67609-8e0a-4327-a01c-e97b77e6c358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759671071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3759671071
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.472952690
Short name T266
Test name
Test status
Simulation time 297797097 ps
CPU time 1.43 seconds
Started Jul 07 05:49:55 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 218628 kb
Host smart-3f3d7bf3-8f48-4023-9082-aef05bf4ae1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472952690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.472952690
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1041218122
Short name T700
Test name
Test status
Simulation time 55710968325 ps
CPU time 1409.3 seconds
Started Jul 07 05:49:54 PM PDT 24
Finished Jul 07 06:13:24 PM PDT 24
Peak memory 224784 kb
Host smart-bb602d3a-9cc5-4684-a566-4830d2070cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041218122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1041218122
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.160963627
Short name T612
Test name
Test status
Simulation time 36724201 ps
CPU time 1.54 seconds
Started Jul 07 05:51:40 PM PDT 24
Finished Jul 07 05:51:42 PM PDT 24
Peak memory 219136 kb
Host smart-ab4ce174-1ad8-413e-97bf-9ccb901b27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160963627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.160963627
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1867510879
Short name T429
Test name
Test status
Simulation time 43147315 ps
CPU time 1.07 seconds
Started Jul 07 05:51:42 PM PDT 24
Finished Jul 07 05:51:43 PM PDT 24
Peak memory 219932 kb
Host smart-e6cd00c3-828f-4895-b270-dc1ff6301446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867510879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1867510879
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1158489480
Short name T351
Test name
Test status
Simulation time 269024513 ps
CPU time 3.95 seconds
Started Jul 07 05:51:44 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 217808 kb
Host smart-e02ec59a-9018-4472-b6c3-d694f66ae306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158489480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1158489480
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.758737422
Short name T299
Test name
Test status
Simulation time 99743680 ps
CPU time 1.1 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 220572 kb
Host smart-eaa7b3d9-52eb-4084-9d08-175cbb547b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758737422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.758737422
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2108685211
Short name T679
Test name
Test status
Simulation time 58567884 ps
CPU time 1.39 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 218724 kb
Host smart-08559d04-6386-4207-aff7-37372fab1699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108685211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2108685211
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2875033102
Short name T277
Test name
Test status
Simulation time 49348020 ps
CPU time 1.27 seconds
Started Jul 07 05:51:40 PM PDT 24
Finished Jul 07 05:51:42 PM PDT 24
Peak memory 219404 kb
Host smart-192306fe-7872-4909-bed5-2073844aad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875033102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2875033102
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3506495401
Short name T369
Test name
Test status
Simulation time 43627678 ps
CPU time 1.6 seconds
Started Jul 07 05:51:43 PM PDT 24
Finished Jul 07 05:51:45 PM PDT 24
Peak memory 218960 kb
Host smart-3e39755f-2981-42f4-bed8-b80d264ac0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506495401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3506495401
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.172817387
Short name T298
Test name
Test status
Simulation time 78350087 ps
CPU time 1.11 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 218884 kb
Host smart-7312fe1d-8555-4a52-b1e3-1b0d048bdb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172817387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.172817387
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.718720745
Short name T24
Test name
Test status
Simulation time 55268400 ps
CPU time 1.91 seconds
Started Jul 07 05:51:38 PM PDT 24
Finished Jul 07 05:51:41 PM PDT 24
Peak memory 218876 kb
Host smart-11b3fd43-fcad-4f25-860a-2c3a6d03bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718720745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.718720745
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.4078772747
Short name T595
Test name
Test status
Simulation time 25724643 ps
CPU time 1.28 seconds
Started Jul 07 05:51:45 PM PDT 24
Finished Jul 07 05:51:47 PM PDT 24
Peak memory 220976 kb
Host smart-4f9c35c1-cc8c-4e97-b07e-d05f27ee9195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078772747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.4078772747
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3001878071
Short name T253
Test name
Test status
Simulation time 52915491 ps
CPU time 1.2 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 217704 kb
Host smart-745bf147-cd89-4b71-8381-4100d50d5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001878071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3001878071
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1382328815
Short name T751
Test name
Test status
Simulation time 46506876 ps
CPU time 1.17 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 219868 kb
Host smart-1a35f27f-077d-4e19-a161-c3cad7e5a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382328815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1382328815
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3715583967
Short name T459
Test name
Test status
Simulation time 163602062 ps
CPU time 1.17 seconds
Started Jul 07 05:51:44 PM PDT 24
Finished Jul 07 05:51:46 PM PDT 24
Peak memory 217544 kb
Host smart-d0804a2c-fc23-4c13-b682-06526db9abb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715583967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3715583967
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3834265132
Short name T590
Test name
Test status
Simulation time 46982675 ps
CPU time 1.25 seconds
Started Jul 07 05:51:45 PM PDT 24
Finished Jul 07 05:51:47 PM PDT 24
Peak memory 219104 kb
Host smart-f621f179-3d67-48da-bd10-a81ef839ea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834265132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3834265132
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1877671728
Short name T563
Test name
Test status
Simulation time 58454577 ps
CPU time 1.39 seconds
Started Jul 07 05:51:42 PM PDT 24
Finished Jul 07 05:51:44 PM PDT 24
Peak memory 218960 kb
Host smart-86d7749c-211e-4092-94cb-c05480c59ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877671728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1877671728
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.105830075
Short name T106
Test name
Test status
Simulation time 39541886 ps
CPU time 1.14 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 218928 kb
Host smart-18dfae18-73c1-435a-95d8-acedabf93bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105830075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.105830075
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.4263169255
Short name T444
Test name
Test status
Simulation time 68859398 ps
CPU time 1.34 seconds
Started Jul 07 05:51:49 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 219544 kb
Host smart-bf304868-d4e8-4885-84fe-9d60ecebc66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263169255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4263169255
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.279314069
Short name T133
Test name
Test status
Simulation time 268288720 ps
CPU time 1.36 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 218896 kb
Host smart-707b8770-3199-4ad4-bde8-af1eb51a7e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279314069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.279314069
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.938460688
Short name T553
Test name
Test status
Simulation time 81681000 ps
CPU time 1.11 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 217540 kb
Host smart-16b77647-05d7-4006-9887-ea51ca6fe61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938460688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.938460688
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2828678669
Short name T190
Test name
Test status
Simulation time 24150009 ps
CPU time 1.19 seconds
Started Jul 07 05:49:59 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 218996 kb
Host smart-2e0d8654-6b16-4660-af47-193467719a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828678669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2828678669
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3404491365
Short name T484
Test name
Test status
Simulation time 19177340 ps
CPU time 0.96 seconds
Started Jul 07 05:50:03 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 207068 kb
Host smart-6dcaaab2-afd0-4763-a767-ac7bae3608f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404491365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3404491365
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1990092440
Short name T235
Test name
Test status
Simulation time 10780657 ps
CPU time 0.88 seconds
Started Jul 07 05:49:58 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 215720 kb
Host smart-5dea4886-1f81-496f-85cc-0cf4fa57552a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990092440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1990092440
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3207003480
Short name T949
Test name
Test status
Simulation time 54287869 ps
CPU time 1.14 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:58 PM PDT 24
Peak memory 217328 kb
Host smart-f35d196b-b169-43ab-83f9-ef911e818280
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207003480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3207003480
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4276069830
Short name T730
Test name
Test status
Simulation time 41452001 ps
CPU time 1.13 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 219872 kb
Host smart-34040de4-7a29-40af-b06a-acb3526c2f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276069830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4276069830
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2864549980
Short name T439
Test name
Test status
Simulation time 57732816 ps
CPU time 1.92 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:59 PM PDT 24
Peak memory 220144 kb
Host smart-05739f8c-fb7d-4bf4-ad56-791eb4017b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864549980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2864549980
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.4170700930
Short name T955
Test name
Test status
Simulation time 23052034 ps
CPU time 1.1 seconds
Started Jul 07 05:49:58 PM PDT 24
Finished Jul 07 05:49:59 PM PDT 24
Peak memory 215680 kb
Host smart-bd821393-f4a5-447d-b069-84f259d1f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170700930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.4170700930
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3782378582
Short name T398
Test name
Test status
Simulation time 45700622 ps
CPU time 0.92 seconds
Started Jul 07 05:49:57 PM PDT 24
Finished Jul 07 05:49:59 PM PDT 24
Peak memory 215596 kb
Host smart-c33d04fa-389a-49c6-b063-b10ffa6cf39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782378582 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3782378582
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4068892061
Short name T866
Test name
Test status
Simulation time 121003320 ps
CPU time 1.97 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:49:59 PM PDT 24
Peak memory 217516 kb
Host smart-d1b2571e-db73-4d02-9da1-27a951ec7662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068892061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4068892061
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2525307780
Short name T514
Test name
Test status
Simulation time 31355548133 ps
CPU time 408.55 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 223996 kb
Host smart-219c3af5-f03d-4f89-a1be-e246c5852cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525307780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2525307780
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1669039872
Short name T172
Test name
Test status
Simulation time 143410330 ps
CPU time 1.25 seconds
Started Jul 07 05:51:45 PM PDT 24
Finished Jul 07 05:51:47 PM PDT 24
Peak memory 216012 kb
Host smart-0db9e615-201a-4eda-b26d-280d3a1ff284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669039872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1669039872
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3874377093
Short name T394
Test name
Test status
Simulation time 53976567 ps
CPU time 1.36 seconds
Started Jul 07 05:51:43 PM PDT 24
Finished Jul 07 05:51:45 PM PDT 24
Peak memory 218752 kb
Host smart-b0e3ab56-c2dc-4ef4-9fbd-54eb936eb7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874377093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3874377093
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1811345982
Short name T397
Test name
Test status
Simulation time 93388958 ps
CPU time 1.22 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 219832 kb
Host smart-80712072-f11b-4935-bfd3-9559c8004f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811345982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1811345982
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3326186739
Short name T326
Test name
Test status
Simulation time 55010236 ps
CPU time 1.48 seconds
Started Jul 07 05:51:48 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 218784 kb
Host smart-f9330ae7-1250-483d-bb00-5e4c7977f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326186739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3326186739
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2674257667
Short name T151
Test name
Test status
Simulation time 66410065 ps
CPU time 1.12 seconds
Started Jul 07 05:51:43 PM PDT 24
Finished Jul 07 05:51:45 PM PDT 24
Peak memory 218848 kb
Host smart-c2105c28-3ae0-4c26-8083-5ba87d023462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674257667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2674257667
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.1563907545
Short name T638
Test name
Test status
Simulation time 46414140 ps
CPU time 1.2 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 219260 kb
Host smart-e95f4e60-21ba-416b-8337-a21c6715775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563907545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1563907545
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.779530863
Short name T411
Test name
Test status
Simulation time 58641250 ps
CPU time 1.57 seconds
Started Jul 07 05:51:45 PM PDT 24
Finished Jul 07 05:51:47 PM PDT 24
Peak memory 218956 kb
Host smart-bda0f22f-6565-40c3-986d-6cac38625dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779530863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.779530863
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2591632843
Short name T96
Test name
Test status
Simulation time 100945885 ps
CPU time 1.27 seconds
Started Jul 07 05:51:48 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 219876 kb
Host smart-2ab95b2c-e956-4db3-b2ca-fcea76d9607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591632843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2591632843
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2811986458
Short name T831
Test name
Test status
Simulation time 40907962 ps
CPU time 1.68 seconds
Started Jul 07 05:51:44 PM PDT 24
Finished Jul 07 05:51:46 PM PDT 24
Peak memory 218744 kb
Host smart-c9166602-07f7-418d-9b99-643b0643b0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811986458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2811986458
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3750950360
Short name T143
Test name
Test status
Simulation time 25538271 ps
CPU time 1.28 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 220084 kb
Host smart-31125249-a13e-4b4b-8522-12e21d7491ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750950360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3750950360
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3477842227
Short name T983
Test name
Test status
Simulation time 63317827 ps
CPU time 1.4 seconds
Started Jul 07 05:51:48 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 215652 kb
Host smart-aa8892cc-a370-43c0-b80c-03491c3f9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477842227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3477842227
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3746029980
Short name T494
Test name
Test status
Simulation time 41509809 ps
CPU time 1.16 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:47 PM PDT 24
Peak memory 219052 kb
Host smart-9b7efb76-a9bb-4fc1-9e30-74043ef2cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746029980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3746029980
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2393015407
Short name T270
Test name
Test status
Simulation time 76627021 ps
CPU time 1.19 seconds
Started Jul 07 05:51:51 PM PDT 24
Finished Jul 07 05:51:52 PM PDT 24
Peak memory 217580 kb
Host smart-15435c40-8815-4d40-8b1d-32de634211c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393015407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2393015407
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2822091425
Short name T925
Test name
Test status
Simulation time 53086055 ps
CPU time 1.25 seconds
Started Jul 07 05:51:48 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 216008 kb
Host smart-0d549015-4e33-4a2d-a666-652dd777564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822091425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2822091425
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4049119285
Short name T387
Test name
Test status
Simulation time 42373430 ps
CPU time 1.52 seconds
Started Jul 07 05:51:47 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 218632 kb
Host smart-0c6c5513-af22-40ce-9022-1bdd3dbb73ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049119285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4049119285
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4241510912
Short name T186
Test name
Test status
Simulation time 114352776 ps
CPU time 1.09 seconds
Started Jul 07 05:51:49 PM PDT 24
Finished Jul 07 05:51:51 PM PDT 24
Peak memory 219836 kb
Host smart-7cffae2f-4be1-465d-a49c-5f2345866870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241510912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4241510912
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.4070106033
Short name T393
Test name
Test status
Simulation time 32632155 ps
CPU time 1.24 seconds
Started Jul 07 05:51:48 PM PDT 24
Finished Jul 07 05:51:50 PM PDT 24
Peak memory 217668 kb
Host smart-6ebf2062-96fd-4ddc-aceb-75ecf090a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070106033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.4070106033
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.469864675
Short name T656
Test name
Test status
Simulation time 94374192 ps
CPU time 1.32 seconds
Started Jul 07 05:51:52 PM PDT 24
Finished Jul 07 05:51:53 PM PDT 24
Peak memory 221776 kb
Host smart-10c73723-7333-4372-b9a8-58b076b0068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469864675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.469864675
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.201941188
Short name T507
Test name
Test status
Simulation time 58354177 ps
CPU time 1.29 seconds
Started Jul 07 05:51:51 PM PDT 24
Finished Jul 07 05:51:52 PM PDT 24
Peak memory 217488 kb
Host smart-436662ca-5ea8-4752-9c54-9b55b8b3b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201941188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.201941188
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3168779372
Short name T752
Test name
Test status
Simulation time 91775849 ps
CPU time 1.13 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 221316 kb
Host smart-86c2f8ab-4829-4917-b359-645ec2e55ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168779372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3168779372
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2793813143
Short name T749
Test name
Test status
Simulation time 19217483 ps
CPU time 0.97 seconds
Started Jul 07 05:49:58 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 207032 kb
Host smart-1fb937fd-3220-4e2f-8093-ad38c94067a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793813143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2793813143
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1230740058
Short name T230
Test name
Test status
Simulation time 25636452 ps
CPU time 0.86 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 216564 kb
Host smart-b5dff455-bd70-49aa-8164-35785b0b51b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230740058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1230740058
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2979535160
Short name T237
Test name
Test status
Simulation time 88322623 ps
CPU time 1.08 seconds
Started Jul 07 05:50:06 PM PDT 24
Finished Jul 07 05:50:07 PM PDT 24
Peak memory 219960 kb
Host smart-be97c2a8-fa06-405e-8738-220362e56e2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979535160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2979535160
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1714462699
Short name T917
Test name
Test status
Simulation time 31611467 ps
CPU time 1.21 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 220008 kb
Host smart-9abaf76c-ac69-445c-b94c-190c7e4247b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714462699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1714462699
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.2828683102
Short name T626
Test name
Test status
Simulation time 21162579 ps
CPU time 1.19 seconds
Started Jul 07 05:49:59 PM PDT 24
Finished Jul 07 05:50:01 PM PDT 24
Peak memory 224352 kb
Host smart-ea9dd440-404a-4390-a8c5-7dcc33e58564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828683102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2828683102
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2421014938
Short name T3
Test name
Test status
Simulation time 48563431 ps
CPU time 0.97 seconds
Started Jul 07 05:50:06 PM PDT 24
Finished Jul 07 05:50:07 PM PDT 24
Peak memory 215624 kb
Host smart-da815e27-493c-4274-9c02-9ef0f7ba1b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421014938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2421014938
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2712252323
Short name T643
Test name
Test status
Simulation time 327734739 ps
CPU time 4.1 seconds
Started Jul 07 05:49:56 PM PDT 24
Finished Jul 07 05:50:01 PM PDT 24
Peak memory 217540 kb
Host smart-df660cc2-f32d-4388-b8ba-401357e5d2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712252323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2712252323
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1304124521
Short name T84
Test name
Test status
Simulation time 252135090686 ps
CPU time 447.72 seconds
Started Jul 07 05:49:57 PM PDT 24
Finished Jul 07 05:57:25 PM PDT 24
Peak memory 224000 kb
Host smart-f2b2156e-4631-411d-bfc4-ab1fed0433fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304124521 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1304124521
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3915553469
Short name T573
Test name
Test status
Simulation time 21525104 ps
CPU time 1.18 seconds
Started Jul 07 05:51:52 PM PDT 24
Finished Jul 07 05:51:53 PM PDT 24
Peak memory 219068 kb
Host smart-0c02dd35-0d77-4245-9e68-6fbc35217ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915553469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3915553469
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.140740404
Short name T423
Test name
Test status
Simulation time 70334234 ps
CPU time 1.05 seconds
Started Jul 07 05:51:46 PM PDT 24
Finished Jul 07 05:51:48 PM PDT 24
Peak memory 217712 kb
Host smart-6384015b-1efa-457e-8b0c-e2b218766793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140740404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.140740404
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2375650592
Short name T580
Test name
Test status
Simulation time 29330778 ps
CPU time 1.29 seconds
Started Jul 07 05:51:51 PM PDT 24
Finished Jul 07 05:51:53 PM PDT 24
Peak memory 218928 kb
Host smart-0cc3befb-6972-4eca-a5fb-2fb2696910dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375650592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2375650592
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1732136914
Short name T412
Test name
Test status
Simulation time 39339501 ps
CPU time 1.47 seconds
Started Jul 07 05:51:53 PM PDT 24
Finished Jul 07 05:51:54 PM PDT 24
Peak memory 217296 kb
Host smart-4b7bc3c9-bb2e-43f8-afe7-13461afab34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732136914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1732136914
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3877502823
Short name T618
Test name
Test status
Simulation time 37188043 ps
CPU time 1.34 seconds
Started Jul 07 05:51:53 PM PDT 24
Finished Jul 07 05:51:55 PM PDT 24
Peak memory 216032 kb
Host smart-0d1a9ca9-cdfb-4151-ac6b-2b09b3cdced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877502823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3877502823
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2507773420
Short name T880
Test name
Test status
Simulation time 35120345 ps
CPU time 1.32 seconds
Started Jul 07 05:51:55 PM PDT 24
Finished Jul 07 05:51:57 PM PDT 24
Peak memory 218824 kb
Host smart-4b441896-34ef-409e-8212-3b70edabec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507773420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2507773420
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1008629499
Short name T110
Test name
Test status
Simulation time 45006777 ps
CPU time 1.25 seconds
Started Jul 07 05:51:50 PM PDT 24
Finished Jul 07 05:51:51 PM PDT 24
Peak memory 218928 kb
Host smart-bee7c864-46d4-4753-bf5e-79af2538d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008629499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1008629499
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1856145453
Short name T834
Test name
Test status
Simulation time 57459953 ps
CPU time 1.22 seconds
Started Jul 07 05:51:54 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 218812 kb
Host smart-12e6eced-3b6e-4923-8dc5-58cfb8a364c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856145453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1856145453
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1670721354
Short name T347
Test name
Test status
Simulation time 143719330 ps
CPU time 1.33 seconds
Started Jul 07 05:51:54 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 220232 kb
Host smart-8191cfe0-b040-4bbb-89ee-1ccb6a90de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670721354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1670721354
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1253197716
Short name T567
Test name
Test status
Simulation time 102259700 ps
CPU time 2.12 seconds
Started Jul 07 05:51:52 PM PDT 24
Finished Jul 07 05:51:55 PM PDT 24
Peak memory 217660 kb
Host smart-5013600f-a7f9-40fb-af54-ae4e81138857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253197716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1253197716
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2541582225
Short name T173
Test name
Test status
Simulation time 40582454 ps
CPU time 1.14 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 219008 kb
Host smart-21f957b2-d56f-4149-b756-305bd22de754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541582225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2541582225
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/196.edn_alert.3138357344
Short name T490
Test name
Test status
Simulation time 54501287 ps
CPU time 1.15 seconds
Started Jul 07 05:51:52 PM PDT 24
Finished Jul 07 05:51:54 PM PDT 24
Peak memory 219864 kb
Host smart-50a19f99-2634-481f-91cf-f59eebf962c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138357344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3138357344
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3948481164
Short name T591
Test name
Test status
Simulation time 32080455 ps
CPU time 1.21 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 217588 kb
Host smart-900874e3-9335-42eb-a116-42c19723a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948481164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3948481164
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.165965793
Short name T627
Test name
Test status
Simulation time 41780066 ps
CPU time 1.25 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:59 PM PDT 24
Peak memory 219696 kb
Host smart-4d34c8d4-e7fe-4324-a9f7-99a05de6caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165965793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.165965793
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3238293764
Short name T961
Test name
Test status
Simulation time 26951877 ps
CPU time 1.3 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 220340 kb
Host smart-9cf0ef50-e13d-492c-b846-30c7146b7065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238293764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3238293764
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2246474
Short name T304
Test name
Test status
Simulation time 26287308 ps
CPU time 1.33 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 219664 kb
Host smart-f4406b26-061c-4d8c-b727-5a533672dcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2246474
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.223217736
Short name T765
Test name
Test status
Simulation time 144565635 ps
CPU time 1.24 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 220340 kb
Host smart-c2ab5562-2b3c-4d68-8c31-f911f85edbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223217736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.223217736
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2585500962
Short name T923
Test name
Test status
Simulation time 30879539 ps
CPU time 1.31 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:59 PM PDT 24
Peak memory 215920 kb
Host smart-8642ca6c-4418-4c3f-91bc-b40da069acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585500962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2585500962
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2393458956
Short name T427
Test name
Test status
Simulation time 108784493 ps
CPU time 1.2 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 217764 kb
Host smart-d0149647-f760-4e4c-8d17-9febcf45c65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393458956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2393458956
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3946533126
Short name T179
Test name
Test status
Simulation time 20650036 ps
CPU time 1.07 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 219888 kb
Host smart-3e12f3f5-50d5-43cf-9ca2-6608c2ca73c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946533126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3946533126
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2187029388
Short name T124
Test name
Test status
Simulation time 33391741 ps
CPU time 0.81 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 206596 kb
Host smart-b56b1b39-ee3f-4a8c-b76e-91f47fc413d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187029388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2187029388
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2348108275
Short name T503
Test name
Test status
Simulation time 42199559 ps
CPU time 0.83 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 216512 kb
Host smart-73e3c5d8-14e4-409f-85f7-ee9e537f69b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348108275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2348108275
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1233110938
Short name T793
Test name
Test status
Simulation time 57851392 ps
CPU time 1.15 seconds
Started Jul 07 05:49:26 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 217352 kb
Host smart-04b9dc8b-efff-47f1-ac93-41a385128c59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233110938 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1233110938
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1597702749
Short name T145
Test name
Test status
Simulation time 24459550 ps
CPU time 1.23 seconds
Started Jul 07 05:49:26 PM PDT 24
Finished Jul 07 05:49:27 PM PDT 24
Peak memory 220744 kb
Host smart-add817ec-0f84-4245-9c21-19af5bcd3edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597702749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1597702749
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3304463638
Short name T881
Test name
Test status
Simulation time 78101799 ps
CPU time 1.26 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:49:31 PM PDT 24
Peak memory 220212 kb
Host smart-306564c2-e935-48ba-bef4-400423b037d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304463638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3304463638
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1290815645
Short name T441
Test name
Test status
Simulation time 35552288 ps
CPU time 1.03 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 05:49:26 PM PDT 24
Peak memory 224316 kb
Host smart-9e77d74d-5615-4e9b-9ccb-9f3ef7e8089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290815645 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1290815645
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1278256356
Short name T675
Test name
Test status
Simulation time 57111900 ps
CPU time 0.97 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 05:49:26 PM PDT 24
Peak memory 207424 kb
Host smart-912a7268-3c0d-42b9-9cab-b20519ca3dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278256356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1278256356
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3903024587
Short name T18
Test name
Test status
Simulation time 2333976110 ps
CPU time 8.05 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 238132 kb
Host smart-f198534e-3273-4063-be34-49a04fb4beca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903024587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3903024587
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1051776772
Short name T778
Test name
Test status
Simulation time 25824300 ps
CPU time 0.89 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:28 PM PDT 24
Peak memory 215572 kb
Host smart-29121378-5f72-4baa-806e-7f96bb2e2244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051776772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1051776772
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3899611731
Short name T868
Test name
Test status
Simulation time 97170449 ps
CPU time 2.42 seconds
Started Jul 07 05:49:26 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 217532 kb
Host smart-5643655e-7e2d-45d2-925c-97c938810b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899611731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3899611731
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2971476663
Short name T239
Test name
Test status
Simulation time 41973215213 ps
CPU time 573.79 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 218516 kb
Host smart-7939bdd4-6a04-45ae-af78-b6279b271e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971476663 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2971476663
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2529834677
Short name T538
Test name
Test status
Simulation time 51711927 ps
CPU time 1.29 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 219244 kb
Host smart-4672333a-4e30-4740-9fc5-ec4152290b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529834677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2529834677
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2499206783
Short name T413
Test name
Test status
Simulation time 44428049 ps
CPU time 0.99 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 207120 kb
Host smart-05a68812-347e-447c-93ae-91cf628bea20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499206783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2499206783
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1279716428
Short name T229
Test name
Test status
Simulation time 9953760 ps
CPU time 0.89 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 216496 kb
Host smart-035f823c-a4eb-40e1-82fa-39bea8f70dae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279716428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1279716428
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3637647417
Short name T934
Test name
Test status
Simulation time 218522502 ps
CPU time 1.13 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 217336 kb
Host smart-7e5a6792-7c75-489f-aa71-587ccaa6f484
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637647417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3637647417
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2610697503
Short name T731
Test name
Test status
Simulation time 44232221 ps
CPU time 1.15 seconds
Started Jul 07 05:50:00 PM PDT 24
Finished Jul 07 05:50:02 PM PDT 24
Peak memory 219920 kb
Host smart-935a4df8-db00-4237-a54f-1981435a1e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610697503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2610697503
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_smoke.2732247464
Short name T806
Test name
Test status
Simulation time 22231878 ps
CPU time 0.94 seconds
Started Jul 07 05:49:59 PM PDT 24
Finished Jul 07 05:50:00 PM PDT 24
Peak memory 215536 kb
Host smart-cf0efb70-e921-490f-8174-1d602f5ea2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732247464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2732247464
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2553834953
Short name T777
Test name
Test status
Simulation time 517078147 ps
CPU time 5.42 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 217600 kb
Host smart-6c70cd83-76dd-4dd1-9ff5-e5fc3567e2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553834953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2553834953
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3460415368
Short name T44
Test name
Test status
Simulation time 60407474566 ps
CPU time 473.14 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 218204 kb
Host smart-6fccb026-9a3d-4b46-97e5-3519b4e90165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460415368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3460415368
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2510335415
Short name T734
Test name
Test status
Simulation time 80319475 ps
CPU time 1.27 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 219056 kb
Host smart-1d909b04-5f1c-4a79-b4e6-d954fa73f42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510335415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2510335415
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4048406421
Short name T359
Test name
Test status
Simulation time 64156453 ps
CPU time 1.49 seconds
Started Jul 07 05:51:53 PM PDT 24
Finished Jul 07 05:51:55 PM PDT 24
Peak memory 218916 kb
Host smart-e87b0b5d-d606-4c66-b800-f9dae45c0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048406421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4048406421
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1238944645
Short name T26
Test name
Test status
Simulation time 30887108 ps
CPU time 1.37 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 218752 kb
Host smart-8e6df0cb-bd07-4e41-9f10-f53d1deff89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238944645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1238944645
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1702235611
Short name T942
Test name
Test status
Simulation time 63472739 ps
CPU time 2.39 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 220360 kb
Host smart-f61e564b-4c98-4a9d-b84b-727e9e81d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702235611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1702235611
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.816747048
Short name T802
Test name
Test status
Simulation time 77454502 ps
CPU time 1.56 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 219196 kb
Host smart-47c47da1-31de-4769-9d2c-509efbcfbfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816747048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.816747048
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2344835398
Short name T717
Test name
Test status
Simulation time 43258330 ps
CPU time 1.57 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 218828 kb
Host smart-3b6d9daa-a433-4109-b89a-6e1727af29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344835398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2344835398
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1248743913
Short name T938
Test name
Test status
Simulation time 88709390 ps
CPU time 3.08 seconds
Started Jul 07 05:51:55 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 220576 kb
Host smart-ddf3d2c3-2385-485b-a972-2d73de3f8718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248743913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1248743913
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4054617594
Short name T78
Test name
Test status
Simulation time 49991825 ps
CPU time 1.16 seconds
Started Jul 07 05:51:54 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 217628 kb
Host smart-8c9a2e8c-85a3-4bdf-9dac-8138acde5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054617594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4054617594
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2374474262
Short name T820
Test name
Test status
Simulation time 88963923 ps
CPU time 1.18 seconds
Started Jul 07 05:51:55 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 220360 kb
Host smart-e8f1294b-fe40-48f6-b6d9-aa0a10b36856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374474262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2374474262
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3123041631
Short name T142
Test name
Test status
Simulation time 140844286 ps
CPU time 1.2 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:03 PM PDT 24
Peak memory 218784 kb
Host smart-5d1a73ae-b000-4beb-9195-66ed7bc31539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123041631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3123041631
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2630127686
Short name T559
Test name
Test status
Simulation time 40905081 ps
CPU time 0.76 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 206712 kb
Host smart-7f5607e0-53a4-4d5a-a844-d1138817e24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630127686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2630127686
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1473251794
Short name T705
Test name
Test status
Simulation time 34251508 ps
CPU time 0.88 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:05 PM PDT 24
Peak memory 216576 kb
Host smart-1ed8dde5-1c25-4b8b-9509-728904d8e159
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473251794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1473251794
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3353487067
Short name T922
Test name
Test status
Simulation time 38246140 ps
CPU time 1.27 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 217176 kb
Host smart-eb5d6b87-9a7f-4385-9216-a21d67ab3ac1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353487067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3353487067
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.685384470
Short name T148
Test name
Test status
Simulation time 43553486 ps
CPU time 1.3 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:05 PM PDT 24
Peak memory 225940 kb
Host smart-45dba4b3-71d8-41c5-a312-895383708901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685384470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.685384470
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2500165793
Short name T487
Test name
Test status
Simulation time 78296012 ps
CPU time 1.26 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 217476 kb
Host smart-4748b6a4-4e6d-438e-bc5d-dcb4f0a95852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500165793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2500165793
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3772087372
Short name T510
Test name
Test status
Simulation time 26898798 ps
CPU time 0.96 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:05 PM PDT 24
Peak memory 215840 kb
Host smart-186ca7c1-20b3-455a-a944-6e8f11345314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772087372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3772087372
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1156234459
Short name T368
Test name
Test status
Simulation time 45860816 ps
CPU time 0.92 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 215608 kb
Host smart-b85115c3-83a8-4947-86db-0f9dfc2bbea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156234459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1156234459
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2357325166
Short name T391
Test name
Test status
Simulation time 1159559232 ps
CPU time 4.01 seconds
Started Jul 07 05:50:00 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 215612 kb
Host smart-c7f29ec5-3753-4093-912b-7e37295d7503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357325166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2357325166
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.1994407338
Short name T757
Test name
Test status
Simulation time 33583268 ps
CPU time 1.39 seconds
Started Jul 07 05:51:55 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 219908 kb
Host smart-cc3cbdd1-20ac-4787-bb4d-ed17f6130615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994407338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1994407338
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3817214849
Short name T975
Test name
Test status
Simulation time 56096873 ps
CPU time 1.42 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 217724 kb
Host smart-dc7bc7e7-6f19-40bd-80a7-bc853a899a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817214849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3817214849
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1897129563
Short name T771
Test name
Test status
Simulation time 78986599 ps
CPU time 1.15 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 218684 kb
Host smart-fcf64ea8-f276-47e3-8d94-38b26d9c02e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897129563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1897129563
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2891397031
Short name T338
Test name
Test status
Simulation time 29360939 ps
CPU time 1.34 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 218768 kb
Host smart-cc3c77e4-df69-4239-9efa-4c17fe64ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891397031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2891397031
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4044448412
Short name T395
Test name
Test status
Simulation time 59924001 ps
CPU time 1.24 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 217648 kb
Host smart-776c8961-4681-4bbe-b0d6-6e555a447a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044448412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4044448412
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.809922100
Short name T818
Test name
Test status
Simulation time 81131796 ps
CPU time 1.09 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 219216 kb
Host smart-3e74e567-edad-43bc-b12d-153ee438b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809922100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.809922100
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2506336376
Short name T25
Test name
Test status
Simulation time 69557151 ps
CPU time 1.43 seconds
Started Jul 07 05:51:55 PM PDT 24
Finished Jul 07 05:51:57 PM PDT 24
Peak memory 218948 kb
Host smart-893efec5-5139-417e-8cb8-959fa95560ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506336376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2506336376
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4186165526
Short name T336
Test name
Test status
Simulation time 56146608 ps
CPU time 1.48 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 218976 kb
Host smart-dd7518a5-1bb9-4dc0-8f7a-8e49380f3fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186165526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4186165526
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3480102840
Short name T54
Test name
Test status
Simulation time 52549902 ps
CPU time 1.34 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:59 PM PDT 24
Peak memory 219028 kb
Host smart-557fad5a-8a33-4c28-9bf0-ae75ece76637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480102840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3480102840
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1446937677
Short name T540
Test name
Test status
Simulation time 51424205 ps
CPU time 1.65 seconds
Started Jul 07 05:52:05 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 218932 kb
Host smart-9baf0736-7e64-4554-975c-a4228d23fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446937677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1446937677
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3597011383
Short name T202
Test name
Test status
Simulation time 25987481 ps
CPU time 1.27 seconds
Started Jul 07 05:50:04 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 220296 kb
Host smart-d2eb1450-6df3-4dcc-b15d-ce1a084b6a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597011383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3597011383
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3450447056
Short name T660
Test name
Test status
Simulation time 12900548 ps
CPU time 0.89 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 215188 kb
Host smart-a2868d98-54c0-4cda-a266-240a7d8bd072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450447056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3450447056
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.428784896
Short name T213
Test name
Test status
Simulation time 35420880 ps
CPU time 1.4 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 219788 kb
Host smart-53a9736b-5e23-4752-a26b-9231ae0d6c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428784896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.428784896
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.845033291
Short name T886
Test name
Test status
Simulation time 129739851 ps
CPU time 1.57 seconds
Started Jul 07 05:50:02 PM PDT 24
Finished Jul 07 05:50:04 PM PDT 24
Peak memory 219408 kb
Host smart-c716b488-8457-4674-90df-4c5b2a4f37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845033291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.845033291
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1532905649
Short name T951
Test name
Test status
Simulation time 41053215 ps
CPU time 0.88 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 215680 kb
Host smart-d2b78452-e460-4fa3-8b12-09cb61c04d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532905649 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1532905649
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1984264582
Short name T524
Test name
Test status
Simulation time 40253356 ps
CPU time 0.94 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 215616 kb
Host smart-4d41c47d-a12f-4c44-a963-1e9c3aed027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984264582 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1984264582
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2767104679
Short name T946
Test name
Test status
Simulation time 326040268 ps
CPU time 6.3 seconds
Started Jul 07 05:50:01 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 218760 kb
Host smart-f2e92109-6b1f-4ab7-a2f2-73fcc8de8c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767104679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2767104679
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3698874257
Short name T811
Test name
Test status
Simulation time 503871310704 ps
CPU time 1760 seconds
Started Jul 07 05:50:03 PM PDT 24
Finished Jul 07 06:19:24 PM PDT 24
Peak memory 233632 kb
Host smart-f25d1945-a90e-4a33-b6fd-4842b2317154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698874257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3698874257
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1415473513
Short name T748
Test name
Test status
Simulation time 228072641 ps
CPU time 3.25 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 220512 kb
Host smart-80d88e8d-b0e3-47ea-8697-94719d5350f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415473513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1415473513
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1665353543
Short name T322
Test name
Test status
Simulation time 75945470 ps
CPU time 1.35 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 218988 kb
Host smart-ed20d103-096d-409f-bdb7-3fa85119e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665353543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1665353543
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2121661064
Short name T984
Test name
Test status
Simulation time 29364363 ps
CPU time 1.3 seconds
Started Jul 07 05:51:54 PM PDT 24
Finished Jul 07 05:51:55 PM PDT 24
Peak memory 218940 kb
Host smart-893b4aa1-7151-45a4-b378-36902eef00a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121661064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2121661064
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1179590363
Short name T833
Test name
Test status
Simulation time 41203418 ps
CPU time 1.28 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 218892 kb
Host smart-c4092271-fb5e-461b-83f2-28fabe3675ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179590363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1179590363
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.354716863
Short name T693
Test name
Test status
Simulation time 51695319 ps
CPU time 1.51 seconds
Started Jul 07 05:51:54 PM PDT 24
Finished Jul 07 05:51:56 PM PDT 24
Peak memory 219156 kb
Host smart-7b174698-a47a-418e-a40f-7af900748abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354716863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.354716863
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4105959871
Short name T531
Test name
Test status
Simulation time 61924896 ps
CPU time 1.14 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 215600 kb
Host smart-25a293f4-da27-4e34-a428-0ac510233ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105959871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4105959871
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3436221316
Short name T801
Test name
Test status
Simulation time 32280882 ps
CPU time 1.18 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 218852 kb
Host smart-f4d93779-e7ab-4382-b5b8-ed519b605c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436221316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3436221316
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1973971271
Short name T519
Test name
Test status
Simulation time 40398769 ps
CPU time 1.26 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 217620 kb
Host smart-57c924d0-5e4a-484a-bf24-1ea0bbac435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973971271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1973971271
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3242634640
Short name T518
Test name
Test status
Simulation time 72709707 ps
CPU time 1.4 seconds
Started Jul 07 05:51:59 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 219392 kb
Host smart-5d434f9d-7612-4787-b0cc-b7089fa75364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242634640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3242634640
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1083581434
Short name T530
Test name
Test status
Simulation time 98124214 ps
CPU time 2.36 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 219236 kb
Host smart-335708e8-650c-4e97-b3dd-d6da6c948ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083581434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1083581434
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3367339414
Short name T875
Test name
Test status
Simulation time 40012530 ps
CPU time 1.21 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 219032 kb
Host smart-5b1fa8fe-fac6-4f78-bb0f-70366dcde228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367339414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3367339414
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.425793942
Short name T82
Test name
Test status
Simulation time 18590524 ps
CPU time 1.03 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:50:09 PM PDT 24
Peak memory 215452 kb
Host smart-c2648216-c2af-43c4-b3a9-07517eed362c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425793942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.425793942
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3131129685
Short name T102
Test name
Test status
Simulation time 43910358 ps
CPU time 1.11 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 217124 kb
Host smart-55221eaa-e05c-4746-aa71-d46f0a5a7404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131129685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3131129685
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3928412136
Short name T720
Test name
Test status
Simulation time 28926141 ps
CPU time 0.96 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 219756 kb
Host smart-63a45988-7af9-4dc5-ad36-87bc4443809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928412136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3928412136
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2497571795
Short name T316
Test name
Test status
Simulation time 52058658 ps
CPU time 1.52 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:07 PM PDT 24
Peak memory 219148 kb
Host smart-64f123cf-fb12-4b88-8b57-ddd8b13fff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497571795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2497571795
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1225092887
Short name T974
Test name
Test status
Simulation time 20745164 ps
CPU time 1.08 seconds
Started Jul 07 05:50:06 PM PDT 24
Finished Jul 07 05:50:07 PM PDT 24
Peak memory 216128 kb
Host smart-183c4c6f-04c1-4aee-8695-c1475cba976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225092887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1225092887
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3700622641
Short name T973
Test name
Test status
Simulation time 31131102 ps
CPU time 0.98 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:06 PM PDT 24
Peak memory 215884 kb
Host smart-d3c2c612-b2cd-4c35-aa41-7bef225d6887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700622641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3700622641
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.386238329
Short name T808
Test name
Test status
Simulation time 292609823 ps
CPU time 5.69 seconds
Started Jul 07 05:50:05 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 218960 kb
Host smart-77e88480-1014-4d4b-8c16-3f7c9da47916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386238329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.386238329
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4225088673
Short name T246
Test name
Test status
Simulation time 22439676094 ps
CPU time 488.02 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 218052 kb
Host smart-37c3cfd3-6f21-41ef-8dc3-3d1f699cfb3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225088673 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4225088673
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3967818347
Short name T437
Test name
Test status
Simulation time 82637709 ps
CPU time 1.13 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 217512 kb
Host smart-2dfe501a-be9e-4846-8c59-23d6b6d491f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967818347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3967818347
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1601716055
Short name T76
Test name
Test status
Simulation time 53770271 ps
CPU time 1.14 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 217596 kb
Host smart-fd9ba6be-8937-48e8-87c8-f7917bcc5890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601716055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1601716055
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3559802826
Short name T849
Test name
Test status
Simulation time 83977958 ps
CPU time 1.06 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 217712 kb
Host smart-75c1b2ba-c817-45e5-9b2c-e4834abc2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559802826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3559802826
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3009632356
Short name T371
Test name
Test status
Simulation time 227272071 ps
CPU time 1.86 seconds
Started Jul 07 05:51:59 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 219188 kb
Host smart-8fa7cdc2-2afa-4eb8-9dbe-cd8af6c0e16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009632356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3009632356
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1379775401
Short name T648
Test name
Test status
Simulation time 344799281 ps
CPU time 1.54 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 219468 kb
Host smart-3e6a8329-5880-477c-b9c8-17ecc9f34765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379775401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1379775401
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.98224140
Short name T454
Test name
Test status
Simulation time 80807984 ps
CPU time 1.11 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 217620 kb
Host smart-cfd799ff-73b4-44a0-8be6-07a4b2755870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98224140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.98224140
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.16165244
Short name T50
Test name
Test status
Simulation time 37890144 ps
CPU time 1.38 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 217720 kb
Host smart-32be64af-88fd-4feb-89c7-b4c33ef27e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16165244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.16165244
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3221155674
Short name T943
Test name
Test status
Simulation time 28215514 ps
CPU time 1.32 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 219912 kb
Host smart-1464aabb-cd19-4695-8e18-b56feda6b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221155674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3221155674
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1828528066
Short name T462
Test name
Test status
Simulation time 53580861 ps
CPU time 1.8 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 218844 kb
Host smart-554655d7-c163-4dcf-b779-dc1dacd152fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828528066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1828528066
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4035134116
Short name T632
Test name
Test status
Simulation time 128888182 ps
CPU time 1.3 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 219380 kb
Host smart-089af417-1cc1-4e54-9624-83abf8c9d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035134116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4035134116
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1919835463
Short name T829
Test name
Test status
Simulation time 19876607 ps
CPU time 1.04 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 207068 kb
Host smart-49676866-2d13-4fa6-a997-31b718fcb8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919835463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1919835463
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3367764508
Short name T226
Test name
Test status
Simulation time 33972922 ps
CPU time 0.88 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 216536 kb
Host smart-d365d95a-0185-4565-b739-86a9791c2da5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367764508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3367764508
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.435143955
Short name T625
Test name
Test status
Simulation time 79781171 ps
CPU time 1 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 217168 kb
Host smart-8ff02bcb-683f-4c2c-a9bc-b8c3877b71ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435143955 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.435143955
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.1803235218
Short name T602
Test name
Test status
Simulation time 29412175 ps
CPU time 1.25 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:09 PM PDT 24
Peak memory 217620 kb
Host smart-50351b3a-199d-4531-bd93-502287fcf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803235218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1803235218
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.529570918
Short name T712
Test name
Test status
Simulation time 25760353 ps
CPU time 0.98 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 05:50:14 PM PDT 24
Peak memory 215632 kb
Host smart-6c44cd78-43b9-40b2-8cdd-d407f5146d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529570918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.529570918
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3084260037
Short name T504
Test name
Test status
Simulation time 115482498 ps
CPU time 1.7 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 215484 kb
Host smart-668ca029-a514-41aa-a523-1c6588b7038a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084260037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3084260037
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.549352938
Short name T402
Test name
Test status
Simulation time 20362939498 ps
CPU time 450.94 seconds
Started Jul 07 05:50:11 PM PDT 24
Finished Jul 07 05:57:43 PM PDT 24
Peak memory 224044 kb
Host smart-21c22346-9034-4f8c-a053-350a5c820219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549352938 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.549352938
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3574811500
Short name T865
Test name
Test status
Simulation time 210565028 ps
CPU time 1.33 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 220392 kb
Host smart-f6fd2a91-8182-447e-b9ca-116d0112c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574811500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3574811500
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3907979328
Short name T787
Test name
Test status
Simulation time 283117406 ps
CPU time 3.78 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:05 PM PDT 24
Peak memory 220752 kb
Host smart-ff0c2631-f147-488a-8d5d-64da36a2e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907979328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3907979328
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.286910649
Short name T419
Test name
Test status
Simulation time 66196551 ps
CPU time 1.35 seconds
Started Jul 07 05:52:10 PM PDT 24
Finished Jul 07 05:52:12 PM PDT 24
Peak memory 217780 kb
Host smart-cf4ac569-be64-43d9-8baa-d6f17b5f3de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286910649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.286910649
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3961499406
Short name T431
Test name
Test status
Simulation time 72383300 ps
CPU time 1.18 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 220088 kb
Host smart-6e0ebc5f-b2a2-4db9-b63f-d455069fe7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961499406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3961499406
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1583270242
Short name T986
Test name
Test status
Simulation time 83422422 ps
CPU time 1.15 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 217472 kb
Host smart-e1a71476-c8b6-446f-856c-467b11640e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583270242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1583270242
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2139745369
Short name T888
Test name
Test status
Simulation time 172177564 ps
CPU time 3.54 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:10 PM PDT 24
Peak memory 219596 kb
Host smart-a21ed49f-d034-471c-8a46-34f61f65c58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139745369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2139745369
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.796770283
Short name T607
Test name
Test status
Simulation time 72822761 ps
CPU time 1.26 seconds
Started Jul 07 05:51:59 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 219128 kb
Host smart-4dd9a776-a53e-4972-83e0-713609ec896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796770283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.796770283
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1460499070
Short name T470
Test name
Test status
Simulation time 80075565 ps
CPU time 2.96 seconds
Started Jul 07 05:52:10 PM PDT 24
Finished Jul 07 05:52:14 PM PDT 24
Peak memory 220376 kb
Host smart-4a8c816c-7fbf-4fa8-a16d-4706aae64861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460499070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1460499070
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2768974530
Short name T780
Test name
Test status
Simulation time 192453858 ps
CPU time 2.98 seconds
Started Jul 07 05:52:12 PM PDT 24
Finished Jul 07 05:52:15 PM PDT 24
Peak memory 220492 kb
Host smart-1deb2dae-56c8-4bc2-a2c7-1fdc809179e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768974530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2768974530
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.793140783
Short name T107
Test name
Test status
Simulation time 49813214 ps
CPU time 1.39 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 219300 kb
Host smart-6104ace8-6c14-4bb0-a014-6a7b6d3e9f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793140783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.793140783
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3039357876
Short name T156
Test name
Test status
Simulation time 43153700 ps
CPU time 1.21 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 220404 kb
Host smart-5302f776-b195-46d4-b28a-7b592ec0fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039357876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3039357876
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3480802176
Short name T785
Test name
Test status
Simulation time 45777090 ps
CPU time 0.88 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 206824 kb
Host smart-8e4ce870-9146-4bbb-b359-4652a3a38ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480802176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3480802176
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.902167154
Short name T52
Test name
Test status
Simulation time 10433562 ps
CPU time 0.9 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 215720 kb
Host smart-f21e8c63-3e43-41ed-a7a9-b1ea7f29b3ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902167154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.902167154
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3266033030
Short name T774
Test name
Test status
Simulation time 130746009 ps
CPU time 1.31 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 217240 kb
Host smart-a6208269-fc0c-4cf5-ac0b-7ebf8da081fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266033030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3266033030
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.651955724
Short name T167
Test name
Test status
Simulation time 18465069 ps
CPU time 1.15 seconds
Started Jul 07 05:50:10 PM PDT 24
Finished Jul 07 05:50:12 PM PDT 24
Peak memory 218716 kb
Host smart-b49e9db4-cd17-46b2-a798-b56664e82b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651955724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.651955724
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.852977439
Short name T521
Test name
Test status
Simulation time 70566449 ps
CPU time 1.07 seconds
Started Jul 07 05:50:10 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 217548 kb
Host smart-e7db2cb3-63b6-493f-8178-bf76d9f0af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852977439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.852977439
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3715318185
Short name T556
Test name
Test status
Simulation time 25839736 ps
CPU time 1.11 seconds
Started Jul 07 05:50:12 PM PDT 24
Finished Jul 07 05:50:13 PM PDT 24
Peak memory 224328 kb
Host smart-49f04fc6-acc1-473a-b149-9402be3b08ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715318185 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3715318185
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1488662266
Short name T378
Test name
Test status
Simulation time 29520555 ps
CPU time 1.01 seconds
Started Jul 07 05:50:06 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 215576 kb
Host smart-53c7a245-aecc-4d41-8c66-919849b8b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488662266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1488662266
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2449296304
Short name T726
Test name
Test status
Simulation time 466742749 ps
CPU time 3.09 seconds
Started Jul 07 05:50:09 PM PDT 24
Finished Jul 07 05:50:12 PM PDT 24
Peak memory 215604 kb
Host smart-775bcc32-db82-46ab-ac0b-93a13360e116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449296304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2449296304
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1588098459
Short name T575
Test name
Test status
Simulation time 73418764650 ps
CPU time 1685.65 seconds
Started Jul 07 05:50:10 PM PDT 24
Finished Jul 07 06:18:16 PM PDT 24
Peak memory 224224 kb
Host smart-3251c452-c97f-465b-85b7-74b7f02db9c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588098459 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1588098459
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.4246619227
Short name T81
Test name
Test status
Simulation time 65379280 ps
CPU time 1.38 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 218976 kb
Host smart-6f077247-e3d1-4c88-bfff-5f6fff52b3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246619227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4246619227
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3903348150
Short name T355
Test name
Test status
Simulation time 48587053 ps
CPU time 1 seconds
Started Jul 07 05:51:57 PM PDT 24
Finished Jul 07 05:51:58 PM PDT 24
Peak memory 217700 kb
Host smart-d03bb2a1-f5b2-4838-8c58-213f58f4604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903348150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3903348150
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3708921582
Short name T572
Test name
Test status
Simulation time 27193102 ps
CPU time 1.31 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 218836 kb
Host smart-c91aad2e-8143-4289-8d46-5414aca57bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708921582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3708921582
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2610736913
Short name T860
Test name
Test status
Simulation time 30559813 ps
CPU time 1.36 seconds
Started Jul 07 05:52:11 PM PDT 24
Finished Jul 07 05:52:13 PM PDT 24
Peak memory 219212 kb
Host smart-0654e806-51f1-4545-a3f3-fe6b3c9084cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610736913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2610736913
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.464168121
Short name T874
Test name
Test status
Simulation time 60611737 ps
CPU time 1.88 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 220368 kb
Host smart-88ae9eb8-ab0c-4f5f-9f90-51e412a72f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464168121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.464168121
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3617230819
Short name T425
Test name
Test status
Simulation time 35734525 ps
CPU time 1.42 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 219080 kb
Host smart-25f61014-83ea-42b1-87cc-4b55b64d437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617230819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3617230819
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.177839544
Short name T613
Test name
Test status
Simulation time 42721684 ps
CPU time 1.51 seconds
Started Jul 07 05:51:59 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 215512 kb
Host smart-bd216d77-5190-4260-8a84-df30edb35393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177839544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.177839544
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4119415425
Short name T623
Test name
Test status
Simulation time 97153974 ps
CPU time 1.25 seconds
Started Jul 07 05:51:59 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 217932 kb
Host smart-165c6a33-3876-433a-9234-e4110463c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119415425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4119415425
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4200437871
Short name T981
Test name
Test status
Simulation time 24675534 ps
CPU time 1.17 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 221124 kb
Host smart-a1b7eade-e1b6-4080-9e10-963403c62fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200437871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4200437871
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.221199339
Short name T882
Test name
Test status
Simulation time 33811478 ps
CPU time 0.99 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 215468 kb
Host smart-a514bfe5-3efc-49a9-b05c-c5088f0e8567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221199339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.221199339
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.694212061
Short name T657
Test name
Test status
Simulation time 21381730 ps
CPU time 0.91 seconds
Started Jul 07 05:50:12 PM PDT 24
Finished Jul 07 05:50:14 PM PDT 24
Peak memory 216280 kb
Host smart-df1d5e19-6974-4113-8475-2921fb572605
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694212061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.694212061
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3349163043
Short name T103
Test name
Test status
Simulation time 101741852 ps
CPU time 1.16 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 217468 kb
Host smart-6db3fca2-a2c0-4026-b34a-9c6b3372795c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349163043 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3349163043
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.382944859
Short name T178
Test name
Test status
Simulation time 24500208 ps
CPU time 1.06 seconds
Started Jul 07 05:50:17 PM PDT 24
Finished Jul 07 05:50:18 PM PDT 24
Peak memory 224276 kb
Host smart-8678ade9-b6e5-4c1e-a2fb-4d544167b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382944859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.382944859
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.97059874
Short name T786
Test name
Test status
Simulation time 47703225 ps
CPU time 1.14 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 215728 kb
Host smart-de5e6571-9593-4ae0-b975-1f600eb2e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97059874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.97059874
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.798054757
Short name T579
Test name
Test status
Simulation time 37743804 ps
CPU time 0.88 seconds
Started Jul 07 05:50:07 PM PDT 24
Finished Jul 07 05:50:08 PM PDT 24
Peak memory 215940 kb
Host smart-3ce5f74e-f0e3-4171-8394-27d1b5ced998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798054757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.798054757
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3893744339
Short name T430
Test name
Test status
Simulation time 33908540 ps
CPU time 0.9 seconds
Started Jul 07 05:50:11 PM PDT 24
Finished Jul 07 05:50:13 PM PDT 24
Peak memory 215640 kb
Host smart-153c4162-e895-487e-a509-9f852fafcee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893744339 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3893744339
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.833241500
Short name T715
Test name
Test status
Simulation time 295448801 ps
CPU time 2.27 seconds
Started Jul 07 05:50:08 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 217520 kb
Host smart-f8387412-29dd-4323-8f63-ec7218e402ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833241500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.833241500
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1686394376
Short name T467
Test name
Test status
Simulation time 42563539589 ps
CPU time 945.24 seconds
Started Jul 07 05:50:10 PM PDT 24
Finished Jul 07 06:05:56 PM PDT 24
Peak memory 219024 kb
Host smart-21814a88-1969-4809-ad3c-fbb0016a5660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686394376 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1686394376
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.108078954
Short name T959
Test name
Test status
Simulation time 83890117 ps
CPU time 1.56 seconds
Started Jul 07 05:51:58 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 219012 kb
Host smart-447e36f8-8348-40ff-bd5b-092f92c956a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108078954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.108078954
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1380911692
Short name T682
Test name
Test status
Simulation time 46931701 ps
CPU time 1.53 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 218760 kb
Host smart-d10473ee-f6b8-4eb9-8a00-ebebe9cdf465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380911692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1380911692
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2791834450
Short name T690
Test name
Test status
Simulation time 23357233 ps
CPU time 1.2 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 218892 kb
Host smart-ca8172a2-cedd-4a5d-8b27-fec909859fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791834450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2791834450
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3451518736
Short name T335
Test name
Test status
Simulation time 68287708 ps
CPU time 1.58 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 218848 kb
Host smart-1bc97858-72d2-451e-af9b-1e4e85e7ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451518736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3451518736
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1149839866
Short name T11
Test name
Test status
Simulation time 34336314 ps
CPU time 1.33 seconds
Started Jul 07 05:52:11 PM PDT 24
Finished Jul 07 05:52:13 PM PDT 24
Peak memory 215616 kb
Host smart-229250cf-eac9-4464-b467-fe875713cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149839866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1149839866
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2500075986
Short name T987
Test name
Test status
Simulation time 43338178 ps
CPU time 1.24 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:01 PM PDT 24
Peak memory 217384 kb
Host smart-c0dbdd2d-26fe-425f-bf1a-31642201869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500075986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2500075986
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1961391269
Short name T685
Test name
Test status
Simulation time 105853125 ps
CPU time 1.19 seconds
Started Jul 07 05:52:11 PM PDT 24
Finished Jul 07 05:52:12 PM PDT 24
Peak memory 217532 kb
Host smart-9edf58ca-be6a-4983-a491-7c478c3ce785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961391269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1961391269
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2256074287
Short name T475
Test name
Test status
Simulation time 58327105 ps
CPU time 1.19 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 217680 kb
Host smart-10dfc01a-7548-4631-98e6-6a187a04cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256074287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2256074287
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.458053181
Short name T450
Test name
Test status
Simulation time 62385153 ps
CPU time 1.55 seconds
Started Jul 07 05:52:11 PM PDT 24
Finished Jul 07 05:52:13 PM PDT 24
Peak memory 220308 kb
Host smart-910d203e-c379-4d60-8cbb-e33b61d272f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458053181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.458053181
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2799672083
Short name T493
Test name
Test status
Simulation time 43327406 ps
CPU time 1.15 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 220648 kb
Host smart-0e36c381-96b4-4e3f-b031-c1c0d60a1dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799672083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2799672083
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4117987662
Short name T533
Test name
Test status
Simulation time 21353368 ps
CPU time 0.88 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 206780 kb
Host smart-8c7397a4-9485-47b5-bb82-8a33ea18f208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117987662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4117987662
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2629733823
Short name T836
Test name
Test status
Simulation time 30094641 ps
CPU time 0.84 seconds
Started Jul 07 05:50:12 PM PDT 24
Finished Jul 07 05:50:13 PM PDT 24
Peak memory 216588 kb
Host smart-e1bf5378-08d3-463f-b021-dfd2a005a527
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629733823 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2629733823
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.325278052
Short name T724
Test name
Test status
Simulation time 99560520 ps
CPU time 1.19 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 218844 kb
Host smart-3dce2fa2-afff-4faf-b48d-a0f4e2b4a421
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325278052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.325278052
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.3927021307
Short name T543
Test name
Test status
Simulation time 90330957 ps
CPU time 1.22 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 217792 kb
Host smart-edbeb125-ff0a-4e6d-b368-666bfd093915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927021307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3927021307
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.402394950
Short name T604
Test name
Test status
Simulation time 36772252 ps
CPU time 0.97 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 224116 kb
Host smart-c900b935-cab1-4c6c-a7c3-cd55b466f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402394950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.402394950
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3925648876
Short name T581
Test name
Test status
Simulation time 22249109 ps
CPU time 0.93 seconds
Started Jul 07 05:50:11 PM PDT 24
Finished Jul 07 05:50:13 PM PDT 24
Peak memory 215588 kb
Host smart-865de03c-a1ac-4736-8b04-8e7aac4cebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925648876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3925648876
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2419089277
Short name T729
Test name
Test status
Simulation time 428230299 ps
CPU time 2.63 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 215572 kb
Host smart-9f78a7c1-7cbf-492e-a4bc-50aeabaa5c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419089277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2419089277
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2618961266
Short name T242
Test name
Test status
Simulation time 334682016203 ps
CPU time 1465.93 seconds
Started Jul 07 05:50:13 PM PDT 24
Finished Jul 07 06:14:40 PM PDT 24
Peak memory 222988 kb
Host smart-48fea6ba-956a-4cb1-955a-43e210a56a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618961266 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2618961266
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1931525754
Short name T79
Test name
Test status
Simulation time 78436588 ps
CPU time 2.96 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 220620 kb
Host smart-18696fad-c697-427b-8c14-cf8d7fc95b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931525754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1931525754
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2480481628
Short name T714
Test name
Test status
Simulation time 47018518 ps
CPU time 1.5 seconds
Started Jul 07 05:52:01 PM PDT 24
Finished Jul 07 05:52:03 PM PDT 24
Peak memory 215632 kb
Host smart-c49f9113-ae14-45a7-9af8-b8ab9aacee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480481628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2480481628
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3126370554
Short name T380
Test name
Test status
Simulation time 78465684 ps
CPU time 1.25 seconds
Started Jul 07 05:52:00 PM PDT 24
Finished Jul 07 05:52:02 PM PDT 24
Peak memory 218964 kb
Host smart-861d61a9-4ab0-4625-b238-e5064b263803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126370554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3126370554
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.171373418
Short name T642
Test name
Test status
Simulation time 30343610 ps
CPU time 1.44 seconds
Started Jul 07 05:52:10 PM PDT 24
Finished Jul 07 05:52:12 PM PDT 24
Peak memory 217704 kb
Host smart-79e7b02d-1793-4c51-9044-5f5b4bfd7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171373418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.171373418
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.929889464
Short name T754
Test name
Test status
Simulation time 26904876 ps
CPU time 1.19 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 217592 kb
Host smart-87160fef-7cb1-4a46-9779-12a17974a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929889464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.929889464
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3132870989
Short name T455
Test name
Test status
Simulation time 57732164 ps
CPU time 1.9 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 218640 kb
Host smart-6e9cabfd-53fb-402d-ba0d-17a9f511e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132870989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3132870989
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2874836923
Short name T458
Test name
Test status
Simulation time 262951033 ps
CPU time 4.03 seconds
Started Jul 07 05:52:08 PM PDT 24
Finished Jul 07 05:52:13 PM PDT 24
Peak memory 217832 kb
Host smart-2daa7d42-b666-431a-8a81-23a7aab52b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874836923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2874836923
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2250881381
Short name T930
Test name
Test status
Simulation time 195333120 ps
CPU time 1.94 seconds
Started Jul 07 05:52:04 PM PDT 24
Finished Jul 07 05:52:06 PM PDT 24
Peak memory 220312 kb
Host smart-6ecbaa14-fbce-4f95-807d-b6c265c901fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250881381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2250881381
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3050987396
Short name T113
Test name
Test status
Simulation time 69550941 ps
CPU time 1.69 seconds
Started Jul 07 05:52:03 PM PDT 24
Finished Jul 07 05:52:05 PM PDT 24
Peak memory 219148 kb
Host smart-5c0c466c-09d8-47bc-9f2a-15b36cb70459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050987396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3050987396
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.994921291
Short name T915
Test name
Test status
Simulation time 115867400 ps
CPU time 1.07 seconds
Started Jul 07 05:52:08 PM PDT 24
Finished Jul 07 05:52:10 PM PDT 24
Peak memory 217488 kb
Host smart-e7320674-3d14-4e3c-a1e4-e86b5a8f0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994921291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.994921291
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.3413708478
Short name T123
Test name
Test status
Simulation time 16759159 ps
CPU time 0.9 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 207048 kb
Host smart-ef66d0f0-88f8-4cd1-8011-e20fa9274703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413708478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3413708478
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1509348244
Short name T97
Test name
Test status
Simulation time 54384575 ps
CPU time 0.89 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 207524 kb
Host smart-be2ac4f4-ea7a-451e-9bf4-9d3cb2c1f788
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509348244 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1509348244
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2045849143
Short name T537
Test name
Test status
Simulation time 98056076 ps
CPU time 1.23 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 217104 kb
Host smart-e5124930-7629-448d-bd69-fdc9447e00ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045849143 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2045849143
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3408695822
Short name T768
Test name
Test status
Simulation time 19584409 ps
CPU time 1.08 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 219036 kb
Host smart-f7925544-e8ff-4553-86c5-7d50bad0d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408695822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3408695822
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2178619783
Short name T513
Test name
Test status
Simulation time 51651108 ps
CPU time 1.2 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 215660 kb
Host smart-bafb9493-286a-4d4f-88c5-c1722245008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178619783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2178619783
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4016302946
Short name T502
Test name
Test status
Simulation time 29948032 ps
CPU time 0.92 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 215688 kb
Host smart-51b85fc4-8c1b-4e2e-a65b-bf2af85f114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016302946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4016302946
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2034789982
Short name T261
Test name
Test status
Simulation time 29779075 ps
CPU time 0.93 seconds
Started Jul 07 05:50:12 PM PDT 24
Finished Jul 07 05:50:13 PM PDT 24
Peak memory 215648 kb
Host smart-1f24a632-0d6b-45a0-9f78-f67bc77c4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034789982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2034789982
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.176908482
Short name T773
Test name
Test status
Simulation time 794321348 ps
CPU time 4.96 seconds
Started Jul 07 05:50:19 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 217604 kb
Host smart-1068ee28-4203-40e8-8cfb-8dbdb1fd64e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176908482 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.176908482
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3072990128
Short name T247
Test name
Test status
Simulation time 20142754127 ps
CPU time 398.18 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:57:01 PM PDT 24
Peak memory 220700 kb
Host smart-a735f5bc-db09-4ef2-bf42-cc1e9136851c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072990128 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3072990128
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3085322216
Short name T970
Test name
Test status
Simulation time 42953626 ps
CPU time 1.5 seconds
Started Jul 07 05:52:08 PM PDT 24
Finished Jul 07 05:52:10 PM PDT 24
Peak memory 218856 kb
Host smart-44ab57bc-e53e-41df-bea0-ec787f95b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085322216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3085322216
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4133583259
Short name T637
Test name
Test status
Simulation time 69973591 ps
CPU time 1.33 seconds
Started Jul 07 05:52:04 PM PDT 24
Finished Jul 07 05:52:06 PM PDT 24
Peak memory 218896 kb
Host smart-d5d6727a-94aa-431a-9009-a2714c5d8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133583259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4133583259
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3217267269
Short name T789
Test name
Test status
Simulation time 62595048 ps
CPU time 1.17 seconds
Started Jul 07 05:52:03 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 218872 kb
Host smart-df745293-26d9-4945-8e56-f52b1cff9461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217267269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3217267269
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.586133951
Short name T448
Test name
Test status
Simulation time 114818798 ps
CPU time 0.99 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 217584 kb
Host smart-d57cdf24-7644-4079-a2ae-7056245a74a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586133951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.586133951
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1373551147
Short name T80
Test name
Test status
Simulation time 198227983 ps
CPU time 1.57 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 219120 kb
Host smart-18ee446a-7a6c-40f6-b6de-46a4594359bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373551147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1373551147
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2023055323
Short name T334
Test name
Test status
Simulation time 30475586 ps
CPU time 1.39 seconds
Started Jul 07 05:52:05 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 218756 kb
Host smart-71080678-d01b-4b10-8f5c-f45e5bb2f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023055323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2023055323
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.96958509
Short name T823
Test name
Test status
Simulation time 68314233 ps
CPU time 2.99 seconds
Started Jul 07 05:52:05 PM PDT 24
Finished Jul 07 05:52:08 PM PDT 24
Peak memory 220428 kb
Host smart-628271f0-4524-4f4a-926b-b0656cf16fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96958509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.96958509
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.817282161
Short name T353
Test name
Test status
Simulation time 210372091 ps
CPU time 2.27 seconds
Started Jul 07 05:52:04 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 220576 kb
Host smart-aa49073d-4c3b-4b7a-8d81-3f4a7d613b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817282161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.817282161
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3700699975
Short name T114
Test name
Test status
Simulation time 133502834 ps
CPU time 1.36 seconds
Started Jul 07 05:52:02 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 217680 kb
Host smart-03a5d2d9-6bd9-4c40-9622-0bda91cd739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700699975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3700699975
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1123342929
Short name T859
Test name
Test status
Simulation time 45031529 ps
CPU time 1.18 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 221204 kb
Host smart-3b51c4d2-90f1-4a3f-af09-1225e80edcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123342929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1123342929
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2634462691
Short name T433
Test name
Test status
Simulation time 17610824 ps
CPU time 1.05 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 207068 kb
Host smart-1530e6a6-497e-409f-82b2-1faae0e7f837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634462691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2634462691
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3990849572
Short name T863
Test name
Test status
Simulation time 173689835 ps
CPU time 1.05 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 217188 kb
Host smart-6fc24ac2-074d-4d98-ad5f-f8654717ffa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990849572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3990849572
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1629493916
Short name T175
Test name
Test status
Simulation time 35751886 ps
CPU time 1.03 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 223656 kb
Host smart-4abea1dc-3db8-4af3-8a5a-dbc2bc4f6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629493916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1629493916
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3693905684
Short name T67
Test name
Test status
Simulation time 40129272 ps
CPU time 1.32 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 218652 kb
Host smart-5a7b84ee-a4f3-40c5-817c-d3cf4b4ed469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693905684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3693905684
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4061314529
Short name T476
Test name
Test status
Simulation time 21021473 ps
CPU time 1.03 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:15 PM PDT 24
Peak memory 216204 kb
Host smart-8d07a099-4be0-499e-8c11-26b41ab80e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061314529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4061314529
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3151211347
Short name T635
Test name
Test status
Simulation time 107637200 ps
CPU time 0.93 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 215608 kb
Host smart-3a489a40-0e2e-427d-b83a-43a8ad96c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151211347 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3151211347
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1786221221
Short name T451
Test name
Test status
Simulation time 69134050 ps
CPU time 1.97 seconds
Started Jul 07 05:50:14 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 215696 kb
Host smart-ddb3fac9-7fb3-44bc-b93a-4d1a30e62f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786221221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1786221221
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.875664389
Short name T706
Test name
Test status
Simulation time 115643734629 ps
CPU time 779.1 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 06:03:15 PM PDT 24
Peak memory 224160 kb
Host smart-998adc8a-2c01-4cc3-b56a-cca61d7657b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875664389 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.875664389
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1226948959
Short name T598
Test name
Test status
Simulation time 107857570 ps
CPU time 2.46 seconds
Started Jul 07 05:52:04 PM PDT 24
Finished Jul 07 05:52:06 PM PDT 24
Peak memory 218832 kb
Host smart-4d75b14e-e2db-48f0-b400-abcf72867e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226948959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1226948959
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1363781834
Short name T928
Test name
Test status
Simulation time 33296898 ps
CPU time 1.42 seconds
Started Jul 07 05:52:03 PM PDT 24
Finished Jul 07 05:52:05 PM PDT 24
Peak memory 220268 kb
Host smart-0d72ef42-042c-4cfe-bc64-efff570f1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363781834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1363781834
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4241057743
Short name T838
Test name
Test status
Simulation time 79087763 ps
CPU time 1.25 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 217636 kb
Host smart-bc11a7ea-fb27-44ce-b780-51514fd8895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241057743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4241057743
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1671274096
Short name T762
Test name
Test status
Simulation time 285768985 ps
CPU time 3.47 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:12 PM PDT 24
Peak memory 220292 kb
Host smart-ff10cd80-41d7-47ab-a918-f8721edbdfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671274096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1671274096
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1952465060
Short name T624
Test name
Test status
Simulation time 32385825 ps
CPU time 1.31 seconds
Started Jul 07 05:52:04 PM PDT 24
Finished Jul 07 05:52:06 PM PDT 24
Peak memory 218768 kb
Host smart-0cf99edd-cd45-4ddb-84a5-f0aa6f7fc4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952465060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1952465060
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2750445699
Short name T374
Test name
Test status
Simulation time 116558513 ps
CPU time 1.27 seconds
Started Jul 07 05:52:03 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 218988 kb
Host smart-1b8c8035-4107-4593-9483-beecf1b1ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750445699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2750445699
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3528471725
Short name T320
Test name
Test status
Simulation time 55536376 ps
CPU time 1.25 seconds
Started Jul 07 05:52:03 PM PDT 24
Finished Jul 07 05:52:04 PM PDT 24
Peak memory 219204 kb
Host smart-1f338b90-c821-440f-adf9-7dec0023e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528471725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3528471725
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.10068841
Short name T864
Test name
Test status
Simulation time 375512966 ps
CPU time 3.54 seconds
Started Jul 07 05:52:06 PM PDT 24
Finished Jul 07 05:52:10 PM PDT 24
Peak memory 220768 kb
Host smart-21e115b2-6413-402a-887d-5dae14e5603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10068841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.10068841
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1193815284
Short name T352
Test name
Test status
Simulation time 71262458 ps
CPU time 1.57 seconds
Started Jul 07 05:52:05 PM PDT 24
Finished Jul 07 05:52:07 PM PDT 24
Peak memory 220240 kb
Host smart-1688254f-1c33-4ea9-9c76-a304e0302b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193815284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1193815284
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3127059894
Short name T327
Test name
Test status
Simulation time 35316517 ps
CPU time 1.49 seconds
Started Jul 07 05:52:07 PM PDT 24
Finished Jul 07 05:52:09 PM PDT 24
Peak memory 218892 kb
Host smart-2061c36b-3844-4924-8fdb-dd7ecb89ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127059894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3127059894
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3969522764
Short name T200
Test name
Test status
Simulation time 98100070 ps
CPU time 1.28 seconds
Started Jul 07 05:49:30 PM PDT 24
Finished Jul 07 05:49:32 PM PDT 24
Peak memory 219988 kb
Host smart-ab942fc7-6e8f-4f52-9c7e-f85bf184199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969522764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3969522764
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3196389344
Short name T267
Test name
Test status
Simulation time 41418164 ps
CPU time 0.99 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 215192 kb
Host smart-01f351b9-4e1b-46a6-b8d5-664afcd53df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196389344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3196389344
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.605551107
Short name T136
Test name
Test status
Simulation time 68972548 ps
CPU time 1.2 seconds
Started Jul 07 05:49:28 PM PDT 24
Finished Jul 07 05:49:29 PM PDT 24
Peak memory 217156 kb
Host smart-8edee86d-569e-4d33-859a-74be7522c885
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605551107 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.605551107
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.300116168
Short name T710
Test name
Test status
Simulation time 20686007 ps
CPU time 1.15 seconds
Started Jul 07 05:49:33 PM PDT 24
Finished Jul 07 05:49:34 PM PDT 24
Peak memory 224316 kb
Host smart-26bea2f2-0d62-472c-8f51-94d9f37cf423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300116168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.300116168
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.162118309
Short name T897
Test name
Test status
Simulation time 44024650 ps
CPU time 1.24 seconds
Started Jul 07 05:49:30 PM PDT 24
Finished Jul 07 05:49:32 PM PDT 24
Peak memory 217680 kb
Host smart-ad1592d7-bec0-47fa-99a7-d3d636e4b429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162118309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.162118309
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3727807243
Short name T383
Test name
Test status
Simulation time 21902974 ps
CPU time 1.11 seconds
Started Jul 07 05:49:31 PM PDT 24
Finished Jul 07 05:49:33 PM PDT 24
Peak memory 215972 kb
Host smart-85e6dc45-41ae-4367-958f-7ff4d887c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727807243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3727807243
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.844110081
Short name T72
Test name
Test status
Simulation time 261383615 ps
CPU time 4.44 seconds
Started Jul 07 05:49:31 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 236900 kb
Host smart-fe1aebe1-3b41-4bc2-a607-22858795f3d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844110081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.844110081
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3545790835
Short name T432
Test name
Test status
Simulation time 37355471 ps
CPU time 0.91 seconds
Started Jul 07 05:49:27 PM PDT 24
Finished Jul 07 05:49:28 PM PDT 24
Peak memory 215436 kb
Host smart-304127ee-f8f9-4471-a912-479419e20a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545790835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3545790835
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3914995208
Short name T379
Test name
Test status
Simulation time 200538330 ps
CPU time 2.39 seconds
Started Jul 07 05:49:31 PM PDT 24
Finished Jul 07 05:49:34 PM PDT 24
Peak memory 215644 kb
Host smart-75f2d653-88a4-45ed-ae64-0ccafe68ce43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914995208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3914995208
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.288679617
Short name T120
Test name
Test status
Simulation time 999326405293 ps
CPU time 1598.63 seconds
Started Jul 07 05:49:31 PM PDT 24
Finished Jul 07 06:16:10 PM PDT 24
Peak memory 223788 kb
Host smart-ded24f77-652e-4117-804c-0599206a4693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288679617 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.288679617
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1760327325
Short name T271
Test name
Test status
Simulation time 55087077 ps
CPU time 1.23 seconds
Started Jul 07 05:50:15 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 219964 kb
Host smart-ffab0a5e-3dd5-4e90-be4b-3ac87856ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760327325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1760327325
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_disable.1837229828
Short name T194
Test name
Test status
Simulation time 16641562 ps
CPU time 0.89 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 216552 kb
Host smart-cd489382-a8b2-4124-bc90-21d3f84d7acc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837229828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1837229828
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2384108934
Short name T877
Test name
Test status
Simulation time 80070064 ps
CPU time 1.04 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 218744 kb
Host smart-78a96344-6d6c-429b-9f95-52f2b9823b6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384108934 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2384108934
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3995014295
Short name T617
Test name
Test status
Simulation time 44448335 ps
CPU time 1.28 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:18 PM PDT 24
Peak memory 226104 kb
Host smart-a1388ae6-5bb2-4c06-ac1c-e85dfa5ca6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995014295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3995014295
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1401914705
Short name T615
Test name
Test status
Simulation time 89811852 ps
CPU time 1.43 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 219332 kb
Host smart-7efc3db6-0250-45b1-a882-6a46369a4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401914705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1401914705
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.469178725
Short name T847
Test name
Test status
Simulation time 30479849 ps
CPU time 1 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 215540 kb
Host smart-5643b39c-0957-469e-8535-23e35377a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469178725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.469178725
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.239378936
Short name T545
Test name
Test status
Simulation time 16330188 ps
CPU time 0.98 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:18 PM PDT 24
Peak memory 215648 kb
Host smart-4dfcca11-5717-45c9-96b3-dc7f168fe0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239378936 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.239378936
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3001498690
Short name T377
Test name
Test status
Simulation time 52286749 ps
CPU time 1.58 seconds
Started Jul 07 05:50:16 PM PDT 24
Finished Jul 07 05:50:18 PM PDT 24
Peak memory 215604 kb
Host smart-c1f59534-f8dc-4cd1-b736-47376d5b58a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001498690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3001498690
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1937928302
Short name T920
Test name
Test status
Simulation time 256861267129 ps
CPU time 893.62 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 06:05:11 PM PDT 24
Peak memory 220976 kb
Host smart-ae12cfbb-c9cb-4842-bc23-48587b4414a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937928302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1937928302
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4219504207
Short name T428
Test name
Test status
Simulation time 22597982 ps
CPU time 1.2 seconds
Started Jul 07 05:50:26 PM PDT 24
Finished Jul 07 05:50:28 PM PDT 24
Peak memory 220072 kb
Host smart-d5ac1b53-c0d4-48b2-80c0-a6ac18659dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219504207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4219504207
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3791968293
Short name T547
Test name
Test status
Simulation time 117398582 ps
CPU time 0.85 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 206668 kb
Host smart-fc1c5db0-a31e-4360-a749-656954677408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791968293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3791968293
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.33905809
Short name T214
Test name
Test status
Simulation time 47459163 ps
CPU time 0.87 seconds
Started Jul 07 05:50:18 PM PDT 24
Finished Jul 07 05:50:19 PM PDT 24
Peak memory 216824 kb
Host smart-bb9be27d-00c7-4c59-a95d-e9a2e74bc3b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.33905809
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3071141300
Short name T65
Test name
Test status
Simulation time 27947862 ps
CPU time 1.45 seconds
Started Jul 07 05:50:19 PM PDT 24
Finished Jul 07 05:50:21 PM PDT 24
Peak memory 226028 kb
Host smart-3c2c0efd-76c5-4149-aade-60635c915c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071141300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3071141300
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2044176594
Short name T447
Test name
Test status
Simulation time 46258970 ps
CPU time 1.18 seconds
Started Jul 07 05:50:20 PM PDT 24
Finished Jul 07 05:50:21 PM PDT 24
Peak memory 217732 kb
Host smart-6d99592c-b09f-43d7-a11c-53f249e4d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044176594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2044176594
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2988888604
Short name T34
Test name
Test status
Simulation time 21590768 ps
CPU time 1.04 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 216076 kb
Host smart-11106dd0-5563-465f-812d-2df19bf51b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988888604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2988888604
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2939253317
Short name T384
Test name
Test status
Simulation time 110690815 ps
CPU time 0.91 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 215364 kb
Host smart-568a0e56-5a09-42d8-9e13-3660c7657916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939253317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2939253317
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2845029770
Short name T918
Test name
Test status
Simulation time 90998322 ps
CPU time 2.32 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:25 PM PDT 24
Peak memory 217492 kb
Host smart-655388be-fd52-43e9-97cf-bd6f2480c464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845029770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2845029770
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2467103850
Short name T719
Test name
Test status
Simulation time 116547782153 ps
CPU time 489.76 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 220108 kb
Host smart-2f456388-e5b9-4596-8257-3b3776061639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467103850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2467103850
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2517016753
Short name T126
Test name
Test status
Simulation time 51795935 ps
CPU time 1.13 seconds
Started Jul 07 05:50:17 PM PDT 24
Finished Jul 07 05:50:18 PM PDT 24
Peak memory 218696 kb
Host smart-c7ab55ae-ff69-4a91-89f3-20bf4bc2eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517016753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2517016753
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4155468616
Short name T676
Test name
Test status
Simulation time 38742445 ps
CPU time 0.97 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 207056 kb
Host smart-a2fefec3-4792-4991-9bff-e52bee8af6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155468616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4155468616
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2973297861
Short name T566
Test name
Test status
Simulation time 27407774 ps
CPU time 0.8 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:50:22 PM PDT 24
Peak memory 216180 kb
Host smart-b3eb6428-5f97-4ea2-8683-e7cdfaa72644
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973297861 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2973297861
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3427494191
Short name T562
Test name
Test status
Simulation time 30810355 ps
CPU time 1.13 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 218856 kb
Host smart-e76ade28-caf8-441b-bd2a-1edb52ee8765
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427494191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3427494191
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2106524781
Short name T878
Test name
Test status
Simulation time 50223817 ps
CPU time 1.14 seconds
Started Jul 07 05:50:20 PM PDT 24
Finished Jul 07 05:50:21 PM PDT 24
Peak memory 224340 kb
Host smart-c0e1b6f6-5be9-40b6-b66d-f2ca43ce52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106524781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2106524781
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.302635277
Short name T410
Test name
Test status
Simulation time 149221569 ps
CPU time 2.23 seconds
Started Jul 07 05:50:20 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 217868 kb
Host smart-573e4a9f-2ce7-4975-831c-c8c38691d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302635277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.302635277
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.689045796
Short name T442
Test name
Test status
Simulation time 26094433 ps
CPU time 0.96 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:50:22 PM PDT 24
Peak memory 216152 kb
Host smart-aa50d883-45f6-41b8-b82c-bef582edb77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689045796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.689045796
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.727491376
Short name T659
Test name
Test status
Simulation time 36188409 ps
CPU time 0.92 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:50:22 PM PDT 24
Peak memory 215628 kb
Host smart-b1e7f845-f5e4-4f93-b4ad-15c6e043b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727491376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.727491376
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4205433713
Short name T264
Test name
Test status
Simulation time 875330946 ps
CPU time 4.76 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:50:26 PM PDT 24
Peak memory 215648 kb
Host smart-565c31fc-19ea-49a8-bd4b-516fe35e337b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205433713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4205433713
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1921416631
Short name T388
Test name
Test status
Simulation time 80864760010 ps
CPU time 524.73 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:59:06 PM PDT 24
Peak memory 220336 kb
Host smart-1b4bcb78-dc9c-451e-bad4-6333c3fb9bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921416631 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1921416631
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1107236647
Short name T769
Test name
Test status
Simulation time 70172169 ps
CPU time 1.12 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:28 PM PDT 24
Peak memory 219076 kb
Host smart-db23db26-7ca9-4a3c-bcbb-cc310e2de01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107236647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1107236647
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1918686360
Short name T699
Test name
Test status
Simulation time 17252453 ps
CPU time 0.83 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 207100 kb
Host smart-63cd8da6-6952-40a8-8f5a-5eb913a53d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918686360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1918686360
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4178519849
Short name T212
Test name
Test status
Simulation time 37295906 ps
CPU time 0.88 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 216664 kb
Host smart-dfceebcc-8909-46ac-9486-0bda3a9fbba3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178519849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4178519849
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3092579483
Short name T760
Test name
Test status
Simulation time 47080537 ps
CPU time 1.41 seconds
Started Jul 07 05:50:25 PM PDT 24
Finished Jul 07 05:50:27 PM PDT 24
Peak memory 217236 kb
Host smart-1c9e7d5b-ea10-403a-a53e-a97c7f3a0fa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092579483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3092579483
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2589952755
Short name T544
Test name
Test status
Simulation time 32136998 ps
CPU time 0.89 seconds
Started Jul 07 05:50:25 PM PDT 24
Finished Jul 07 05:50:26 PM PDT 24
Peak memory 218340 kb
Host smart-48054b63-5ce3-41d4-b5ce-7bbdf9f49367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589952755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2589952755
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2284660326
Short name T840
Test name
Test status
Simulation time 65488025 ps
CPU time 1.62 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:25 PM PDT 24
Peak memory 219088 kb
Host smart-ab909c6c-2062-4444-91a6-a2e27fb4524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284660326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2284660326
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.405765289
Short name T601
Test name
Test status
Simulation time 33325734 ps
CPU time 0.94 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 215568 kb
Host smart-dd03447a-81ff-4147-b1ff-00aacc0fa80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405765289 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.405765289
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.913340894
Short name T68
Test name
Test status
Simulation time 16715465 ps
CPU time 0.99 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 215604 kb
Host smart-d10c2862-b0c4-4d4e-9b23-02632fc1dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913340894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.913340894
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3987663472
Short name T265
Test name
Test status
Simulation time 492784743 ps
CPU time 5.29 seconds
Started Jul 07 05:50:21 PM PDT 24
Finished Jul 07 05:50:27 PM PDT 24
Peak memory 217496 kb
Host smart-2c45cf36-febc-4a39-a4d4-f8d74ea1b9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987663472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3987663472
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3589826422
Short name T321
Test name
Test status
Simulation time 288164026544 ps
CPU time 3131.11 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 06:42:40 PM PDT 24
Peak memory 235644 kb
Host smart-6f6d0a1a-9d47-4cd2-b1ff-6632988f37b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589826422 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3589826422
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1653645192
Short name T164
Test name
Test status
Simulation time 26494436 ps
CPU time 1.29 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 220260 kb
Host smart-fb615bbb-4813-4969-a465-ffd1377ac9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653645192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1653645192
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4157523842
Short name T571
Test name
Test status
Simulation time 45565493 ps
CPU time 0.89 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 215096 kb
Host smart-51c1b6bc-fe86-4eca-8749-4df4b7ae8cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157523842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4157523842
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.211124650
Short name T47
Test name
Test status
Simulation time 14450187 ps
CPU time 1.02 seconds
Started Jul 07 05:50:24 PM PDT 24
Finished Jul 07 05:50:25 PM PDT 24
Peak memory 216472 kb
Host smart-e43c8ed4-7f0d-483a-8987-39ab1720aa65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211124650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.211124650
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2237018673
Short name T744
Test name
Test status
Simulation time 40317005 ps
CPU time 1.02 seconds
Started Jul 07 05:50:26 PM PDT 24
Finished Jul 07 05:50:28 PM PDT 24
Peak memory 217216 kb
Host smart-de8d603a-efb7-4912-897e-56476127754d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237018673 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2237018673
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2108711212
Short name T440
Test name
Test status
Simulation time 19729849 ps
CPU time 1.04 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 218812 kb
Host smart-9052cfcf-42fc-4c00-b5ef-bdfe6a8d3c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108711212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2108711212
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1449921235
Short name T950
Test name
Test status
Simulation time 489201642 ps
CPU time 5.35 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:33 PM PDT 24
Peak memory 219780 kb
Host smart-3ecc80dc-138c-4111-a485-38fc07e53ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449921235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1449921235
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1755598614
Short name T902
Test name
Test status
Simulation time 22927917 ps
CPU time 1.16 seconds
Started Jul 07 05:50:22 PM PDT 24
Finished Jul 07 05:50:23 PM PDT 24
Peak memory 224312 kb
Host smart-598bd71a-3201-4575-bf6e-cb34d870dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755598614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1755598614
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1786448954
Short name T661
Test name
Test status
Simulation time 21329714 ps
CPU time 0.96 seconds
Started Jul 07 05:50:23 PM PDT 24
Finished Jul 07 05:50:24 PM PDT 24
Peak memory 215588 kb
Host smart-af57047d-f8ef-4932-8632-abd6071b3870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786448954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1786448954
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1642793303
Short name T400
Test name
Test status
Simulation time 789171097 ps
CPU time 4.49 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 217440 kb
Host smart-6daebe96-485a-4d62-93d3-f4d0bc94390d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642793303 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1642793303
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1853167265
Short name T969
Test name
Test status
Simulation time 16502472535 ps
CPU time 377.99 seconds
Started Jul 07 05:50:24 PM PDT 24
Finished Jul 07 05:56:42 PM PDT 24
Peak memory 224084 kb
Host smart-31a4af8f-945b-4959-a162-e2f067676a6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853167265 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1853167265
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.372322855
Short name T272
Test name
Test status
Simulation time 27134725 ps
CPU time 1.26 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:28 PM PDT 24
Peak memory 219124 kb
Host smart-c736787f-b0f3-4a6d-926f-13abe4b8db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372322855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.372322855
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.737087291
Short name T255
Test name
Test status
Simulation time 13902193 ps
CPU time 0.95 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 207056 kb
Host smart-0529b359-e873-46ca-81bd-401f532b4472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737087291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.737087291
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2983563072
Short name T844
Test name
Test status
Simulation time 13258982 ps
CPU time 0.91 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 216408 kb
Host smart-bb7fb3d1-b3f1-4ae9-844d-319b99cd69a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983563072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2983563072
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2761799130
Short name T147
Test name
Test status
Simulation time 85258131 ps
CPU time 1.06 seconds
Started Jul 07 05:50:30 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 218888 kb
Host smart-bee23d9d-097f-4583-bd19-b565e2191587
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761799130 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2761799130
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3226974579
Short name T912
Test name
Test status
Simulation time 19137502 ps
CPU time 1.22 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 224268 kb
Host smart-6aac8e68-0034-4535-ba88-ead7c0174eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226974579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3226974579
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.195463276
Short name T333
Test name
Test status
Simulation time 82695697 ps
CPU time 1.11 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:28 PM PDT 24
Peak memory 217648 kb
Host smart-3db2ec34-fd9f-41ee-a58e-5660790a4174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195463276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.195463276
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3588588779
Short name T936
Test name
Test status
Simulation time 31698691 ps
CPU time 0.94 seconds
Started Jul 07 05:50:30 PM PDT 24
Finished Jul 07 05:50:31 PM PDT 24
Peak memory 223980 kb
Host smart-275637de-b757-411c-a0ea-373147356da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588588779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3588588779
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.286191168
Short name T620
Test name
Test status
Simulation time 25804699 ps
CPU time 0.95 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 215584 kb
Host smart-faa90f3d-2696-4b4c-98d2-ff04af444ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286191168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.286191168
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4129159938
Short name T640
Test name
Test status
Simulation time 724524033 ps
CPU time 5.72 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:33 PM PDT 24
Peak memory 217520 kb
Host smart-563760da-98f2-4a6e-8c7b-e495d78bee74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129159938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4129159938
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3399657077
Short name T742
Test name
Test status
Simulation time 243664054341 ps
CPU time 1434.91 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 06:14:32 PM PDT 24
Peak memory 223640 kb
Host smart-fc085207-ceed-467b-907d-e10c02a162e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399657077 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3399657077
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2089009362
Short name T191
Test name
Test status
Simulation time 91989721 ps
CPU time 1.26 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 221188 kb
Host smart-69446c8c-71a0-4c4b-8cf4-143814d94364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089009362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2089009362
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1238042916
Short name T631
Test name
Test status
Simulation time 15951613 ps
CPU time 0.88 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 207288 kb
Host smart-faa64c45-bff6-4640-9abb-fbe54ab4df4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238042916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1238042916
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1988050935
Short name T234
Test name
Test status
Simulation time 176508137 ps
CPU time 0.94 seconds
Started Jul 07 05:50:26 PM PDT 24
Finished Jul 07 05:50:27 PM PDT 24
Peak memory 215668 kb
Host smart-559531a9-a9ad-4397-a330-33b5272cc604
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988050935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1988050935
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2929190554
Short name T340
Test name
Test status
Simulation time 102338340 ps
CPU time 1.22 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 217344 kb
Host smart-3504f2fa-2e83-4292-adc0-7427e54337e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929190554 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2929190554
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1658717605
Short name T140
Test name
Test status
Simulation time 21458420 ps
CPU time 1.22 seconds
Started Jul 07 05:50:29 PM PDT 24
Finished Jul 07 05:50:30 PM PDT 24
Peak memory 229820 kb
Host smart-c1641144-6e2a-403a-acdf-3172d3b095b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658717605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1658717605
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2486768398
Short name T851
Test name
Test status
Simulation time 50706743 ps
CPU time 1.02 seconds
Started Jul 07 05:50:28 PM PDT 24
Finished Jul 07 05:50:29 PM PDT 24
Peak memory 217756 kb
Host smart-c8b47579-367f-41df-82c9-980db1fb1c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486768398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2486768398
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.567143813
Short name T36
Test name
Test status
Simulation time 25298656 ps
CPU time 0.98 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 216208 kb
Host smart-8e1d9e9e-86d5-4138-a006-3f5b2b7b57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567143813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.567143813
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4262811899
Short name T593
Test name
Test status
Simulation time 73829065 ps
CPU time 0.9 seconds
Started Jul 07 05:50:35 PM PDT 24
Finished Jul 07 05:50:36 PM PDT 24
Peak memory 215644 kb
Host smart-a854043a-d7f0-4f93-b9da-eb9f93e72bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262811899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4262811899
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.828720164
Short name T599
Test name
Test status
Simulation time 362742151 ps
CPU time 2.45 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:34 PM PDT 24
Peak memory 215548 kb
Host smart-2bd865cf-4c13-43c9-b143-a5185e02c0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828720164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.828720164
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3251046703
Short name T248
Test name
Test status
Simulation time 52031237777 ps
CPU time 1007.45 seconds
Started Jul 07 05:50:27 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 223976 kb
Host smart-97912fb2-6abe-4244-a654-a5fe9b613e36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251046703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3251046703
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3027527389
Short name T583
Test name
Test status
Simulation time 152519409 ps
CPU time 1.3 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:37 PM PDT 24
Peak memory 220464 kb
Host smart-faee3983-e968-4d84-9c43-52d204bf8c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027527389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3027527389
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1394129677
Short name T366
Test name
Test status
Simulation time 62546529 ps
CPU time 0.9 seconds
Started Jul 07 05:50:30 PM PDT 24
Finished Jul 07 05:50:31 PM PDT 24
Peak memory 206340 kb
Host smart-066d8eca-8cef-47f6-8926-f0e828267c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394129677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1394129677
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.781557033
Short name T738
Test name
Test status
Simulation time 266049494 ps
CPU time 1.26 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:36 PM PDT 24
Peak memory 215880 kb
Host smart-44a3d0da-0086-47fb-bb15-deacf80c7f59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781557033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.781557033
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1476567657
Short name T403
Test name
Test status
Simulation time 21413465 ps
CPU time 0.89 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:37 PM PDT 24
Peak memory 218604 kb
Host smart-c2cbc95b-ff92-49ab-b3ff-0d1db0f5fbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476567657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1476567657
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2383359088
Short name T438
Test name
Test status
Simulation time 38596492 ps
CPU time 1.06 seconds
Started Jul 07 05:50:35 PM PDT 24
Finished Jul 07 05:50:37 PM PDT 24
Peak memory 217596 kb
Host smart-487bd491-c851-40e3-924f-3e94d4738410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383359088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2383359088
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.530168611
Short name T118
Test name
Test status
Simulation time 38873673 ps
CPU time 0.87 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 215884 kb
Host smart-96f4d5a5-7464-4441-88f1-5f014d7b2bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530168611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.530168611
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3170181948
Short name T354
Test name
Test status
Simulation time 26793231 ps
CPU time 0.98 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 207440 kb
Host smart-1368f152-3bf0-4a5c-9146-d7f52c94fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170181948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3170181948
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2126395404
Short name T269
Test name
Test status
Simulation time 214199864 ps
CPU time 1.79 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:36 PM PDT 24
Peak memory 217428 kb
Host smart-c3fe3279-e682-42d2-ab63-8b62aac31404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126395404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2126395404
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3236794876
Short name T252
Test name
Test status
Simulation time 80031963235 ps
CPU time 591.58 seconds
Started Jul 07 05:50:32 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 220284 kb
Host smart-574d66e7-6c64-4e91-b064-deff3bea18ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236794876 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3236794876
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1741624241
Short name T739
Test name
Test status
Simulation time 43617980 ps
CPU time 1.12 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:36 PM PDT 24
Peak memory 218724 kb
Host smart-8b27715b-02f7-48b7-9194-ac4a9cea0b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741624241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1741624241
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1795173252
Short name T587
Test name
Test status
Simulation time 15238489 ps
CPU time 0.95 seconds
Started Jul 07 05:50:33 PM PDT 24
Finished Jul 07 05:50:34 PM PDT 24
Peak memory 215228 kb
Host smart-8ba8bc8a-386b-4efc-8c0a-381cf0c604cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795173252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1795173252
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.358607980
Short name T529
Test name
Test status
Simulation time 15307764 ps
CPU time 0.85 seconds
Started Jul 07 05:50:33 PM PDT 24
Finished Jul 07 05:50:34 PM PDT 24
Peak memory 215720 kb
Host smart-6477b1ba-8ec6-4740-ab22-e7c11bb9c203
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358607980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.358607980
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1019551280
Short name T300
Test name
Test status
Simulation time 277694773 ps
CPU time 1.09 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:35 PM PDT 24
Peak memory 218596 kb
Host smart-a9943491-28f8-498d-9668-999522736f96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019551280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1019551280
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4118956140
Short name T141
Test name
Test status
Simulation time 110027429 ps
CPU time 1.12 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 220708 kb
Host smart-68b0979f-d554-48bf-a9c4-d12aa74aff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118956140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4118956140
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2081316296
Short name T798
Test name
Test status
Simulation time 136261396 ps
CPU time 1.34 seconds
Started Jul 07 05:50:33 PM PDT 24
Finished Jul 07 05:50:35 PM PDT 24
Peak memory 218872 kb
Host smart-f92f2df8-e450-40fc-ae9a-ff604433f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081316296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2081316296
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2480490482
Short name T817
Test name
Test status
Simulation time 42906792 ps
CPU time 1.04 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 224248 kb
Host smart-dd897622-6cf0-4632-8969-8879b1a8038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480490482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2480490482
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.876502165
Short name T892
Test name
Test status
Simulation time 25926664 ps
CPU time 0.96 seconds
Started Jul 07 05:50:31 PM PDT 24
Finished Jul 07 05:50:32 PM PDT 24
Peak memory 215636 kb
Host smart-e232bc5f-f88a-4c27-9b6b-1149e782577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876502165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.876502165
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.893152103
Short name T260
Test name
Test status
Simulation time 981764188 ps
CPU time 5.18 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 215544 kb
Host smart-7c1d9665-2d24-4eb3-b784-dc8bb8679c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893152103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.893152103
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2783595153
Short name T245
Test name
Test status
Simulation time 65666925486 ps
CPU time 161.73 seconds
Started Jul 07 05:50:33 PM PDT 24
Finished Jul 07 05:53:15 PM PDT 24
Peak memory 218376 kb
Host smart-27c62e91-cba5-4a98-9a4a-53da1a20dc94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783595153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2783595153
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3367476135
Short name T585
Test name
Test status
Simulation time 22042211 ps
CPU time 1.21 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:35 PM PDT 24
Peak memory 220140 kb
Host smart-76be0946-654d-40ff-83d8-294ef82e750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367476135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3367476135
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2998795893
Short name T680
Test name
Test status
Simulation time 14304403 ps
CPU time 0.92 seconds
Started Jul 07 05:50:33 PM PDT 24
Finished Jul 07 05:50:34 PM PDT 24
Peak memory 215056 kb
Host smart-d74371b1-a315-4f88-b2a4-2d09f2b6778d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998795893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2998795893
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2860006230
Short name T51
Test name
Test status
Simulation time 21803398 ps
CPU time 0.87 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:35 PM PDT 24
Peak memory 216448 kb
Host smart-472ee68c-0376-4cda-b834-55ba23a1da63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860006230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2860006230
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2037852306
Short name T670
Test name
Test status
Simulation time 33305265 ps
CPU time 1.16 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:39 PM PDT 24
Peak memory 218376 kb
Host smart-e8117ab1-0072-49f1-a4aa-81696ad0f254
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037852306 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2037852306
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2550071914
Short name T375
Test name
Test status
Simulation time 22682285 ps
CPU time 0.99 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:39 PM PDT 24
Peak memory 219904 kb
Host smart-5b0ab72e-0953-4e6c-ac15-68d2dbc3752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550071914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2550071914
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.631027283
Short name T350
Test name
Test status
Simulation time 43063747 ps
CPU time 1.47 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 219800 kb
Host smart-3bef1f17-4a62-4a36-8d29-bcb10e5a256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631027283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.631027283
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3576568657
Short name T827
Test name
Test status
Simulation time 29888083 ps
CPU time 0.92 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 215868 kb
Host smart-5e43c306-648d-4c5e-b87d-6b0ae045c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576568657 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3576568657
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1259624893
Short name T527
Test name
Test status
Simulation time 48171466 ps
CPU time 0.93 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:39 PM PDT 24
Peak memory 215616 kb
Host smart-7a6aa64b-afd0-474e-a7c9-da3d865ae5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259624893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1259624893
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4082202077
Short name T641
Test name
Test status
Simulation time 704172683 ps
CPU time 4.02 seconds
Started Jul 07 05:50:35 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 217404 kb
Host smart-a4ac9369-f74d-4572-b9ee-6497d26a7a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082202077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4082202077
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2472259035
Short name T565
Test name
Test status
Simulation time 79061934594 ps
CPU time 1008.35 seconds
Started Jul 07 05:50:32 PM PDT 24
Finished Jul 07 06:07:20 PM PDT 24
Peak memory 223532 kb
Host smart-1120d6b7-ecd2-46af-8e3d-31b799916edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472259035 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2472259035
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3746479788
Short name T616
Test name
Test status
Simulation time 36496077 ps
CPU time 1.19 seconds
Started Jul 07 05:49:32 PM PDT 24
Finished Jul 07 05:49:34 PM PDT 24
Peak memory 218812 kb
Host smart-dc3275cb-57cf-4506-9ab9-2dd22e623cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746479788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3746479788
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.737750882
Short name T966
Test name
Test status
Simulation time 57145064 ps
CPU time 0.93 seconds
Started Jul 07 05:49:30 PM PDT 24
Finished Jul 07 05:49:32 PM PDT 24
Peak memory 215184 kb
Host smart-6bc3fda6-e809-4141-8130-4e7d448fb010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737750882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.737750882
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2337122236
Short name T654
Test name
Test status
Simulation time 19527734 ps
CPU time 0.83 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 215640 kb
Host smart-1f6f3a27-fa0b-4fc9-8b00-88d6e7956360
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337122236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2337122236
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1690723389
Short name T227
Test name
Test status
Simulation time 40750212 ps
CPU time 1.32 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 219764 kb
Host smart-581b0aeb-dcb6-480b-9444-1f731246361d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690723389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1690723389
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1236866214
Short name T87
Test name
Test status
Simulation time 18327817 ps
CPU time 1.1 seconds
Started Jul 07 05:49:31 PM PDT 24
Finished Jul 07 05:49:33 PM PDT 24
Peak memory 218724 kb
Host smart-61ad9d8b-b6ec-41ec-af15-be89d4d4f127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236866214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1236866214
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3224282603
Short name T105
Test name
Test status
Simulation time 164248038 ps
CPU time 1.86 seconds
Started Jul 07 05:49:28 PM PDT 24
Finished Jul 07 05:49:30 PM PDT 24
Peak memory 219540 kb
Host smart-73d41d25-a244-4845-a02f-c58602fec840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224282603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3224282603
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3573362991
Short name T956
Test name
Test status
Simulation time 32278463 ps
CPU time 0.91 seconds
Started Jul 07 05:49:30 PM PDT 24
Finished Jul 07 05:49:32 PM PDT 24
Peak memory 215728 kb
Host smart-3b03dab5-8ef4-4657-a28c-35b2d985fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573362991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3573362991
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3105187694
Short name T630
Test name
Test status
Simulation time 55617710 ps
CPU time 0.95 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:49:30 PM PDT 24
Peak memory 207328 kb
Host smart-ad270fc5-b552-4db8-a888-1f5931602b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105187694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3105187694
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3377097147
Short name T19
Test name
Test status
Simulation time 952176556 ps
CPU time 7.92 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:49:43 PM PDT 24
Peak memory 238152 kb
Host smart-f7f52b95-5258-4790-9319-1e9d7b21874c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377097147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3377097147
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3346503539
Short name T386
Test name
Test status
Simulation time 221284730 ps
CPU time 0.97 seconds
Started Jul 07 05:49:29 PM PDT 24
Finished Jul 07 05:49:31 PM PDT 24
Peak memory 215540 kb
Host smart-4e7ea2fe-e7ae-4140-98f5-469687c1aad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346503539 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3346503539
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3731403382
Short name T479
Test name
Test status
Simulation time 81359470 ps
CPU time 1.05 seconds
Started Jul 07 05:49:32 PM PDT 24
Finished Jul 07 05:49:33 PM PDT 24
Peak memory 206764 kb
Host smart-a76c39ca-cd9e-4715-bb44-437d8761c662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731403382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3731403382
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3553667912
Short name T727
Test name
Test status
Simulation time 41274932997 ps
CPU time 907.87 seconds
Started Jul 07 05:49:32 PM PDT 24
Finished Jul 07 06:04:40 PM PDT 24
Peak memory 224096 kb
Host smart-40fc4183-97e7-4c88-a433-a6048afc32bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553667912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3553667912
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.726789792
Short name T344
Test name
Test status
Simulation time 24657394 ps
CPU time 1.15 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 220088 kb
Host smart-aa3e2e98-0b1a-4834-88c2-607b5d942355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726789792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.726789792
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3361951650
Short name T883
Test name
Test status
Simulation time 21747188 ps
CPU time 0.87 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:37 PM PDT 24
Peak memory 206924 kb
Host smart-0c3ed191-246e-43d4-b121-79dd75adac3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361951650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3361951650
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2031802367
Short name T903
Test name
Test status
Simulation time 129584538 ps
CPU time 0.9 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 216276 kb
Host smart-28b395c4-c670-4e08-b00d-dea9f36c563f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031802367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2031802367
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1211000017
Short name T894
Test name
Test status
Simulation time 78563588 ps
CPU time 1.04 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 217140 kb
Host smart-bb6fa791-36b7-4aff-8fa4-7ea9d1541575
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211000017 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1211000017
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_genbits.3561550473
Short name T940
Test name
Test status
Simulation time 163301295 ps
CPU time 3.32 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 220396 kb
Host smart-834c3d82-9ba1-464f-af18-60d973730bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561550473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3561550473
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.987598752
Short name T117
Test name
Test status
Simulation time 21922219 ps
CPU time 1.14 seconds
Started Jul 07 05:50:34 PM PDT 24
Finished Jul 07 05:50:36 PM PDT 24
Peak memory 216072 kb
Host smart-3e92f9c7-da00-4e15-ae29-06b1392d9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987598752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.987598752
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3655277929
Short name T426
Test name
Test status
Simulation time 33843379 ps
CPU time 1.01 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:39 PM PDT 24
Peak memory 215640 kb
Host smart-79561371-d93f-447c-abd7-aa56449b4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655277929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3655277929
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.905953753
Short name T810
Test name
Test status
Simulation time 529452592 ps
CPU time 3.21 seconds
Started Jul 07 05:50:40 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 220828 kb
Host smart-9159aa51-1afa-4d8d-a20d-9b0380ad9e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905953753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.905953753
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.1752905279
Short name T885
Test name
Test status
Simulation time 62329282 ps
CPU time 1.15 seconds
Started Jul 07 05:50:40 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 220044 kb
Host smart-4f587f62-5cc7-4fb6-b2c8-54a3807bff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752905279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1752905279
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3021905512
Short name T873
Test name
Test status
Simulation time 67592148 ps
CPU time 1 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 207096 kb
Host smart-8916ee77-db34-44db-b5cf-75b72d0351f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021905512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3021905512
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1375739382
Short name T905
Test name
Test status
Simulation time 24339824 ps
CPU time 0.87 seconds
Started Jul 07 05:50:36 PM PDT 24
Finished Jul 07 05:50:38 PM PDT 24
Peak memory 207336 kb
Host smart-770e87fc-429f-4fab-824d-5e44cfaf8604
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375739382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1375739382
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3199434208
Short name T381
Test name
Test status
Simulation time 102392875 ps
CPU time 1.31 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 217264 kb
Host smart-4d450119-93b9-4140-800b-dbed7cff490b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199434208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3199434208
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3929069350
Short name T129
Test name
Test status
Simulation time 35356978 ps
CPU time 0.9 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:42 PM PDT 24
Peak memory 220032 kb
Host smart-5e5b5fec-a13e-437f-ab67-9d1c8df1fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929069350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3929069350
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.935688932
Short name T644
Test name
Test status
Simulation time 60190043 ps
CPU time 1.15 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 219992 kb
Host smart-af2d47d0-7a93-463f-be83-78cca7c774da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935688932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.935688932
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1571330579
Short name T116
Test name
Test status
Simulation time 21201991 ps
CPU time 1.07 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 216268 kb
Host smart-ee0bdb63-d7ef-48b9-b87b-015fe0670fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571330579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1571330579
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3360052519
Short name T841
Test name
Test status
Simulation time 25820150 ps
CPU time 1 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 215572 kb
Host smart-e9865065-a096-4c53-bd35-11f2b74a2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360052519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3360052519
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.408932591
Short name T119
Test name
Test status
Simulation time 95455665 ps
CPU time 2.35 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 217732 kb
Host smart-7ff7ba24-9ce9-40f8-a170-7303b5e03c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408932591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.408932591
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2534470655
Short name T900
Test name
Test status
Simulation time 117558112998 ps
CPU time 2733.95 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 06:36:14 PM PDT 24
Peak memory 230876 kb
Host smart-e46fa235-2588-4e81-a809-57afc995fc1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534470655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2534470655
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.776384601
Short name T574
Test name
Test status
Simulation time 39115243 ps
CPU time 1.09 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 219836 kb
Host smart-677a6927-242e-462d-90ef-24fa6bb7f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776384601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.776384601
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2081616609
Short name T560
Test name
Test status
Simulation time 67297435 ps
CPU time 0.82 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 206784 kb
Host smart-6332c975-37f0-4166-b402-644fcdf5cef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081616609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2081616609
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2045595637
Short name T184
Test name
Test status
Simulation time 68102158 ps
CPU time 0.86 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 216592 kb
Host smart-9a760455-273e-45e2-93cf-1819c0ee97b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045595637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2045595637
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1202973698
Short name T496
Test name
Test status
Simulation time 33978589 ps
CPU time 1.2 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 217168 kb
Host smart-23374000-2a01-4990-9e9b-95257b1a3c07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202973698 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1202973698
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4006223519
Short name T158
Test name
Test status
Simulation time 21409324 ps
CPU time 1.2 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 220776 kb
Host smart-6c9f28fc-0e41-4cc1-8829-53b9d88915b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006223519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4006223519
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.889771049
Short name T456
Test name
Test status
Simulation time 58199474 ps
CPU time 1.29 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 218688 kb
Host smart-607afa53-ecd1-4bff-ba1f-d5f25cff1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889771049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.889771049
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2100421828
Short name T763
Test name
Test status
Simulation time 23528383 ps
CPU time 1.1 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 215728 kb
Host smart-c009fbb4-ff32-4c99-ad84-4b21d480951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100421828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2100421828
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4108969401
Short name T421
Test name
Test status
Simulation time 16089529 ps
CPU time 1 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:39 PM PDT 24
Peak memory 215604 kb
Host smart-c9c69919-6b79-4880-8588-f5daec30a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108969401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4108969401
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2953291738
Short name T756
Test name
Test status
Simulation time 192827698 ps
CPU time 3.89 seconds
Started Jul 07 05:50:37 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 215716 kb
Host smart-b3fef7d3-ad63-4fb0-8582-b38e7dd78d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953291738 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2953291738
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.22568
Short name T480
Test name
Test status
Simulation time 215144925816 ps
CPU time 832.95 seconds
Started Jul 07 05:50:44 PM PDT 24
Finished Jul 07 06:04:38 PM PDT 24
Peak memory 224092 kb
Host smart-3755a831-2e67-48be-a03f-21a002bd9fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22568 -assert nopostproc +U
VM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.22568
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1627458687
Short name T549
Test name
Test status
Simulation time 36315280 ps
CPU time 1.09 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 219048 kb
Host smart-d0fdb325-7872-45ec-b0cf-e48809253e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627458687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1627458687
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2055654163
Short name T584
Test name
Test status
Simulation time 24782156 ps
CPU time 0.88 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 206844 kb
Host smart-831d00a5-044b-4d29-8641-7d3fcdc89157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055654163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2055654163
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2129333881
Short name T1
Test name
Test status
Simulation time 13399826 ps
CPU time 0.93 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 216704 kb
Host smart-5f7b9cd3-6831-4280-b0c4-55b095f37c1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129333881 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2129333881
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3165257084
Short name T135
Test name
Test status
Simulation time 93117431 ps
CPU time 1.05 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 05:50:41 PM PDT 24
Peak memory 217228 kb
Host smart-99e8a96f-9152-4e00-9e98-6965aa09f542
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165257084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3165257084
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1869712330
Short name T224
Test name
Test status
Simulation time 29050223 ps
CPU time 1.25 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 220072 kb
Host smart-a114e451-295a-41a0-863c-fd8139621f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869712330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1869712330
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2142364143
Short name T971
Test name
Test status
Simulation time 100769771 ps
CPU time 1.19 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 219152 kb
Host smart-d9c0b770-5b3a-4c1e-a5cb-9b39db7d0868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142364143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2142364143
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.753202892
Short name T636
Test name
Test status
Simulation time 20719381 ps
CPU time 1.14 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 224248 kb
Host smart-6d0408fc-3e7c-43aa-9f8f-0839ebefa4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753202892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.753202892
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1436914624
Short name T535
Test name
Test status
Simulation time 33521565 ps
CPU time 0.88 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 215608 kb
Host smart-c4643e55-9b26-4c34-a8e4-285598a0236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436914624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1436914624
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1556582099
Short name T805
Test name
Test status
Simulation time 569339070 ps
CPU time 3.45 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 217492 kb
Host smart-4041e415-6e39-450a-9b2f-9d97408ac199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556582099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1556582099
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2871284271
Short name T251
Test name
Test status
Simulation time 69753740055 ps
CPU time 711.21 seconds
Started Jul 07 05:50:39 PM PDT 24
Finished Jul 07 06:02:31 PM PDT 24
Peak memory 223984 kb
Host smart-2e3d88d4-d5ef-46ca-a886-17bc4e0c6eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871284271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2871284271
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.475091466
Short name T957
Test name
Test status
Simulation time 25663932 ps
CPU time 1.16 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 218996 kb
Host smart-952ac73d-5a4b-41d8-a635-3631929416e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475091466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.475091466
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3154530210
Short name T919
Test name
Test status
Simulation time 17572834 ps
CPU time 0.96 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 207108 kb
Host smart-7c43ef21-efff-4f14-9d09-58103ba83fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154530210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3154530210
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1452430768
Short name T111
Test name
Test status
Simulation time 17019035 ps
CPU time 0.89 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 216588 kb
Host smart-0fa456a3-16e6-4b29-b8de-2297cd612aa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452430768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1452430768
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_genbits.2026767077
Short name T652
Test name
Test status
Simulation time 127104045 ps
CPU time 1.13 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 217552 kb
Host smart-f426937a-c903-4f64-a180-7660b2339b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026767077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2026767077
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3682238089
Short name T622
Test name
Test status
Simulation time 38673738 ps
CPU time 0.91 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 215732 kb
Host smart-4b6a4697-bdcb-4780-a1e6-92ef07a8ac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682238089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3682238089
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3845070030
Short name T610
Test name
Test status
Simulation time 43520001 ps
CPU time 0.94 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 215572 kb
Host smart-6f372a51-acec-45a0-a46d-dbdee36598ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845070030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3845070030
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1114925518
Short name T528
Test name
Test status
Simulation time 2340778374 ps
CPU time 3.41 seconds
Started Jul 07 05:50:38 PM PDT 24
Finished Jul 07 05:50:42 PM PDT 24
Peak memory 217544 kb
Host smart-a4cbdb74-af62-4c80-be28-ce5b02b0cab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114925518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1114925518
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1506581796
Short name T931
Test name
Test status
Simulation time 304543886467 ps
CPU time 489.01 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:58:52 PM PDT 24
Peak memory 219568 kb
Host smart-86a8a0e1-e81f-4d29-ae18-4bde43253a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506581796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1506581796
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3746285660
Short name T273
Test name
Test status
Simulation time 101540737 ps
CPU time 1.28 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 219936 kb
Host smart-1a42b979-6949-4ed5-817f-6f515002167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746285660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3746285660
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1864405108
Short name T443
Test name
Test status
Simulation time 28757354 ps
CPU time 0.94 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:46 PM PDT 24
Peak memory 207032 kb
Host smart-0ee95bd1-7f58-4384-ae62-8ab90311a509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864405108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1864405108
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.600937315
Short name T216
Test name
Test status
Simulation time 11568273 ps
CPU time 0.87 seconds
Started Jul 07 05:50:44 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 216552 kb
Host smart-3a9bc607-a8b1-4878-90c5-b4255c4cf9ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600937315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.600937315
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.705560380
Short name T160
Test name
Test status
Simulation time 239925391 ps
CPU time 1.14 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 220020 kb
Host smart-f2615052-085c-44dd-b9ee-238e0606c47b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705560380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.705560380
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.781545717
Short name T189
Test name
Test status
Simulation time 21480028 ps
CPU time 1.1 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:45 PM PDT 24
Peak memory 224228 kb
Host smart-fe6cf1f1-03b4-4573-aa6e-8f86a872205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781545717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.781545717
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3789484739
Short name T845
Test name
Test status
Simulation time 110913295 ps
CPU time 1.63 seconds
Started Jul 07 05:50:47 PM PDT 24
Finished Jul 07 05:50:49 PM PDT 24
Peak memory 219376 kb
Host smart-bb9a4c51-1b19-4f90-948c-3ab9b2a183b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789484739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3789484739
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2734263085
Short name T37
Test name
Test status
Simulation time 34470877 ps
CPU time 0.94 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:44 PM PDT 24
Peak memory 215892 kb
Host smart-57c5827c-cbea-4fa4-bed6-09f06d86359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734263085 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2734263085
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1897785889
Short name T978
Test name
Test status
Simulation time 16273116 ps
CPU time 0.99 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 215556 kb
Host smart-9cdb57b5-402c-4903-bce1-56cf20357bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897785889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1897785889
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3222395426
Short name T210
Test name
Test status
Simulation time 159143868 ps
CPU time 3.44 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 217508 kb
Host smart-679f4da9-ae62-440e-a6a5-8a48c9669da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222395426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3222395426
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.2239154156
Short name T671
Test name
Test status
Simulation time 26435054 ps
CPU time 1.23 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 219940 kb
Host smart-50b16642-1c78-414b-93ec-ff1f71993c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239154156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2239154156
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4288648209
Short name T869
Test name
Test status
Simulation time 44140747 ps
CPU time 0.86 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 05:50:49 PM PDT 24
Peak memory 215524 kb
Host smart-0fd76a61-734e-4ef7-9f9b-c00417703a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288648209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4288648209
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.578525018
Short name T170
Test name
Test status
Simulation time 60675274 ps
CPU time 0.91 seconds
Started Jul 07 05:50:42 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 216000 kb
Host smart-56872d45-42cf-414b-987f-782e7691dbd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578525018 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.578525018
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2288320746
Short name T159
Test name
Test status
Simulation time 100950547 ps
CPU time 1.2 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 217144 kb
Host smart-3137df4f-e8b2-4445-8daf-8b2c1409a464
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288320746 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2288320746
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1831597899
Short name T478
Test name
Test status
Simulation time 24396275 ps
CPU time 1.19 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:42 PM PDT 24
Peak memory 218992 kb
Host smart-ae316524-ee0f-44e0-855e-68fe30633ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831597899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1831597899
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.655311500
Short name T960
Test name
Test status
Simulation time 60432940 ps
CPU time 1.55 seconds
Started Jul 07 05:50:41 PM PDT 24
Finished Jul 07 05:50:43 PM PDT 24
Peak memory 219172 kb
Host smart-f26150ba-95f9-4167-bde2-5219d321a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655311500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.655311500
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1798340240
Short name T485
Test name
Test status
Simulation time 33220466 ps
CPU time 1.03 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 224124 kb
Host smart-8a5219f6-e880-460d-86c2-f2ff6f54bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798340240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1798340240
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.912040262
Short name T539
Test name
Test status
Simulation time 62296677 ps
CPU time 0.97 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 215600 kb
Host smart-a3db7aae-b9a6-470c-9b9a-528a74cf5317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912040262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.912040262
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4013898511
Short name T362
Test name
Test status
Simulation time 681888853 ps
CPU time 3.47 seconds
Started Jul 07 05:50:43 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 217560 kb
Host smart-6ad1f40a-a32e-4d2e-b975-54b30dae6c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013898511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4013898511
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2295906656
Short name T243
Test name
Test status
Simulation time 140437991503 ps
CPU time 889.03 seconds
Started Jul 07 05:50:46 PM PDT 24
Finished Jul 07 06:05:36 PM PDT 24
Peak memory 224056 kb
Host smart-7e5fc066-c14c-495b-a4c0-333add0bb370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295906656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2295906656
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3351683880
Short name T195
Test name
Test status
Simulation time 31594902 ps
CPU time 1.4 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:51 PM PDT 24
Peak memory 215936 kb
Host smart-e7cb10c7-7476-4d0e-a363-a3b2de35adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351683880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3351683880
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3120920333
Short name T376
Test name
Test status
Simulation time 37997813 ps
CPU time 1.04 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:46 PM PDT 24
Peak memory 207184 kb
Host smart-b3e6a33a-caaf-4f97-963e-c0971265c69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120920333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3120920333
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1616477831
Short name T460
Test name
Test status
Simulation time 13180426 ps
CPU time 0.93 seconds
Started Jul 07 05:50:44 PM PDT 24
Finished Jul 07 05:50:46 PM PDT 24
Peak memory 215892 kb
Host smart-ab282783-ce56-42fc-b226-894a1b7ed5ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616477831 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1616477831
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.714774199
Short name T745
Test name
Test status
Simulation time 20473402 ps
CPU time 1.17 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:51 PM PDT 24
Peak memory 218836 kb
Host smart-7d5ba146-f6ee-4806-8cd7-4b8ffa7ba0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714774199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.714774199
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2556626458
Short name T407
Test name
Test status
Simulation time 302459013 ps
CPU time 1.36 seconds
Started Jul 07 05:50:44 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 219452 kb
Host smart-2e9f5194-564e-4dad-bfe3-b1a8c307aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556626458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2556626458
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1807435307
Short name T41
Test name
Test status
Simulation time 25978476 ps
CPU time 0.98 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 05:50:49 PM PDT 24
Peak memory 216184 kb
Host smart-a2ca0366-68a8-406e-ae4c-e1b97f518dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807435307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1807435307
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2565924353
Short name T409
Test name
Test status
Simulation time 41914108 ps
CPU time 0.93 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:46 PM PDT 24
Peak memory 215668 kb
Host smart-9e3ad39c-9423-47b4-a86e-b86ed1689259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565924353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2565924353
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.388921712
Short name T121
Test name
Test status
Simulation time 159598436 ps
CPU time 1.37 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 05:50:50 PM PDT 24
Peak memory 218000 kb
Host smart-4b920544-1333-4938-84cc-bbe14ceb7780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388921712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.388921712
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.1968455690
Short name T667
Test name
Test status
Simulation time 70124632 ps
CPU time 1.26 seconds
Started Jul 07 05:50:47 PM PDT 24
Finished Jul 07 05:50:49 PM PDT 24
Peak memory 221828 kb
Host smart-9be24f98-0478-41df-93b0-547202a8805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968455690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1968455690
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.602841283
Short name T646
Test name
Test status
Simulation time 20287689 ps
CPU time 0.83 seconds
Started Jul 07 05:50:47 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 206164 kb
Host smart-fc7f5517-4056-4f27-b152-36880b2f734d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602841283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.602841283
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.976735831
Short name T596
Test name
Test status
Simulation time 22291725 ps
CPU time 1.03 seconds
Started Jul 07 05:50:50 PM PDT 24
Finished Jul 07 05:50:51 PM PDT 24
Peak memory 217332 kb
Host smart-343ba50f-8989-4b57-a441-e05f271fa976
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976735831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.976735831
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1110692170
Short name T893
Test name
Test status
Simulation time 19656089 ps
CPU time 1.09 seconds
Started Jul 07 05:50:47 PM PDT 24
Finished Jul 07 05:50:48 PM PDT 24
Peak memory 218792 kb
Host smart-bd4b2433-6f03-41d8-b313-b499f038f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110692170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1110692170
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.48297988
Short name T791
Test name
Test status
Simulation time 106015646 ps
CPU time 1.53 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:47 PM PDT 24
Peak memory 219044 kb
Host smart-c8428cc5-b502-4acb-aaba-468ce2ae1fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48297988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.48297988
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3400616229
Short name T904
Test name
Test status
Simulation time 24217812 ps
CPU time 0.95 seconds
Started Jul 07 05:50:45 PM PDT 24
Finished Jul 07 05:50:46 PM PDT 24
Peak memory 216144 kb
Host smart-d46ddfa6-b5d4-4ee2-a08e-079aaa18276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400616229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3400616229
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1263153721
Short name T697
Test name
Test status
Simulation time 17630825 ps
CPU time 1.02 seconds
Started Jul 07 05:50:53 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 215596 kb
Host smart-a1881e72-fa3c-498a-a082-48ecee2d06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263153721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1263153721
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2264782145
Short name T464
Test name
Test status
Simulation time 372049600 ps
CPU time 4.19 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 217492 kb
Host smart-ca6ff36e-5e45-4410-b911-70cf7ba19da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264782145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2264782145
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1157293001
Short name T578
Test name
Test status
Simulation time 286913482143 ps
CPU time 2301.22 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 06:29:11 PM PDT 24
Peak memory 230944 kb
Host smart-249d840a-ea61-428d-8f91-6eed33eb469e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157293001 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1157293001
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4099445213
Short name T495
Test name
Test status
Simulation time 33173611 ps
CPU time 1.27 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:50 PM PDT 24
Peak memory 216000 kb
Host smart-a6124054-b44b-4ef3-9997-db9fb967b721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099445213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4099445213
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1621174110
Short name T669
Test name
Test status
Simulation time 24446425 ps
CPU time 0.89 seconds
Started Jul 07 05:50:51 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 215232 kb
Host smart-5b6c3ddc-0bb5-45eb-90c6-bcb740b77895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621174110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1621174110
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1577804698
Short name T988
Test name
Test status
Simulation time 91355815 ps
CPU time 0.9 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:50 PM PDT 24
Peak memory 216844 kb
Host smart-2284554b-94d0-46ab-9189-2fb928bbf379
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577804698 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1577804698
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.350303437
Short name T154
Test name
Test status
Simulation time 29915926 ps
CPU time 1.14 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 05:50:50 PM PDT 24
Peak memory 215908 kb
Host smart-0b59501e-7d9c-4883-a705-bed10be08520
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350303437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.350303437
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1177080761
Short name T204
Test name
Test status
Simulation time 22348304 ps
CPU time 1.03 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 229848 kb
Host smart-37fd2817-2aa5-43d3-a489-51dadcf761e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177080761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1177080761
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3829836937
Short name T695
Test name
Test status
Simulation time 43036514 ps
CPU time 1.21 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 218844 kb
Host smart-975f0140-42d1-43fd-bdf5-ba90d437fa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829836937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3829836937
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3813740254
Short name T35
Test name
Test status
Simulation time 19699479 ps
CPU time 1.07 seconds
Started Jul 07 05:50:50 PM PDT 24
Finished Jul 07 05:50:52 PM PDT 24
Peak memory 216200 kb
Host smart-2ab78598-a429-463d-9f7f-39f3e30ff2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813740254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3813740254
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.695101301
Short name T977
Test name
Test status
Simulation time 41540264 ps
CPU time 0.92 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 05:50:49 PM PDT 24
Peak memory 215572 kb
Host smart-a4458d40-7d3d-4fe3-b96b-a159eb2aa0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695101301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.695101301
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1465676631
Short name T750
Test name
Test status
Simulation time 369495195 ps
CPU time 2.4 seconds
Started Jul 07 05:50:51 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 215636 kb
Host smart-8a82d7d4-3d44-4036-b635-2a0a13dace42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465676631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1465676631
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3060825930
Short name T711
Test name
Test status
Simulation time 91011291282 ps
CPU time 1119.52 seconds
Started Jul 07 05:50:48 PM PDT 24
Finished Jul 07 06:09:28 PM PDT 24
Peak memory 225080 kb
Host smart-0fc67a14-2fcd-46bf-8942-38c15a4b65f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060825930 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3060825930
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.3342862980
Short name T509
Test name
Test status
Simulation time 34948895 ps
CPU time 0.81 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 207100 kb
Host smart-b880a256-fcfa-4d14-932b-4177530a1481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342862980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3342862980
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.559087633
Short name T947
Test name
Test status
Simulation time 12322932 ps
CPU time 0.87 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 216724 kb
Host smart-4402e71a-214c-4e48-ba5c-f7a2c7f3718e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559087633 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.559087633
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1433705278
Short name T218
Test name
Test status
Simulation time 55980361 ps
CPU time 1.15 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:49:43 PM PDT 24
Peak memory 217104 kb
Host smart-7780b0c7-fbe8-45c7-8258-6b648804fb77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433705278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1433705278
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2336947543
Short name T474
Test name
Test status
Simulation time 24311947 ps
CPU time 1.1 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 219956 kb
Host smart-ca10745e-9f48-42ee-9b6c-6932c1fed016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336947543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2336947543
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2434956796
Short name T953
Test name
Test status
Simulation time 39030173 ps
CPU time 1.47 seconds
Started Jul 07 05:49:34 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 215620 kb
Host smart-b2a903fe-e307-4e7c-9b09-03f8b1905862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434956796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2434956796
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4180224447
Short name T465
Test name
Test status
Simulation time 27456811 ps
CPU time 1.09 seconds
Started Jul 07 05:49:38 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 224320 kb
Host smart-d48cfd82-81f3-489b-8a62-60c25e289bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180224447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4180224447
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2348758496
Short name T30
Test name
Test status
Simulation time 27498478 ps
CPU time 0.94 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 207316 kb
Host smart-5b9e7c8f-da81-4f31-b0b9-dd80e7595a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348758496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2348758496
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1636873697
Short name T424
Test name
Test status
Simulation time 210002581 ps
CPU time 1 seconds
Started Jul 07 05:49:30 PM PDT 24
Finished Jul 07 05:49:32 PM PDT 24
Peak memory 207384 kb
Host smart-8d27c6de-7625-4147-b053-6fdd9abb89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636873697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1636873697
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.794840897
Short name T262
Test name
Test status
Simulation time 171213679 ps
CPU time 2.17 seconds
Started Jul 07 05:49:34 PM PDT 24
Finished Jul 07 05:49:36 PM PDT 24
Peak memory 217628 kb
Host smart-b44310ec-c324-4bb4-b04c-26e2bb095e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794840897 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.794840897
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3415962967
Short name T512
Test name
Test status
Simulation time 83616193933 ps
CPU time 538.89 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:58:34 PM PDT 24
Peak memory 220280 kb
Host smart-ddc60b70-c12c-4a62-9b31-50268c3b3ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415962967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3415962967
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2929569549
Short name T561
Test name
Test status
Simulation time 42346664 ps
CPU time 1.16 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 221488 kb
Host smart-0d1f4fa1-009e-42ba-a2b4-a734074bfdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929569549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2929569549
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.359508486
Short name T608
Test name
Test status
Simulation time 51561790 ps
CPU time 1.01 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 220248 kb
Host smart-af748768-21d1-4b3b-a63e-1bad69776601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359508486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.359508486
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.2361446578
Short name T753
Test name
Test status
Simulation time 38672967 ps
CPU time 1.09 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 217660 kb
Host smart-05bdeaa7-60a7-4fd6-bb42-e4e7935e9ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361446578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2361446578
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2886172043
Short name T258
Test name
Test status
Simulation time 215871447 ps
CPU time 1.23 seconds
Started Jul 07 05:50:51 PM PDT 24
Finished Jul 07 05:50:52 PM PDT 24
Peak memory 220388 kb
Host smart-e0ecb685-0fbb-4ae4-aa77-f913df741737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886172043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2886172043
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.4237753528
Short name T278
Test name
Test status
Simulation time 30318730 ps
CPU time 1.32 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 221056 kb
Host smart-41bd5432-19e1-4e10-abe1-3f6029d8bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237753528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.4237753528
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4032727156
Short name T722
Test name
Test status
Simulation time 23494475 ps
CPU time 1.18 seconds
Started Jul 07 05:50:51 PM PDT 24
Finished Jul 07 05:50:52 PM PDT 24
Peak memory 218984 kb
Host smart-dd182232-3deb-48b1-809e-b44a6be9f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032727156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4032727156
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2719944678
Short name T716
Test name
Test status
Simulation time 127795938 ps
CPU time 1.53 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 219672 kb
Host smart-99b41539-7843-4d93-ba65-87ef0f0ed97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719944678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2719944678
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3996146633
Short name T342
Test name
Test status
Simulation time 28650964 ps
CPU time 1.29 seconds
Started Jul 07 05:50:50 PM PDT 24
Finished Jul 07 05:50:52 PM PDT 24
Peak memory 219804 kb
Host smart-54bdb00f-52fa-43d7-a81d-3cedb77ec80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996146633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3996146633
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3196067264
Short name T168
Test name
Test status
Simulation time 18648362 ps
CPU time 1.23 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 224268 kb
Host smart-e73d0d16-ca42-4fce-9a43-9fbbc61e3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196067264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3196067264
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3513692164
Short name T445
Test name
Test status
Simulation time 97841492 ps
CPU time 1.6 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 220504 kb
Host smart-394dc57a-0b27-4df5-ac9f-a2b49a1c78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513692164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3513692164
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1455053287
Short name T482
Test name
Test status
Simulation time 46991621 ps
CPU time 1.16 seconds
Started Jul 07 05:50:53 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 220056 kb
Host smart-cb20e0ca-b709-48dc-a253-e6d79b670173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455053287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1455053287
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2886773097
Short name T735
Test name
Test status
Simulation time 21440522 ps
CPU time 1.17 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 224256 kb
Host smart-9ec188dd-62c9-4684-9326-c5fef1e4d4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886773097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2886773097
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4137192091
Short name T420
Test name
Test status
Simulation time 118318899 ps
CPU time 1.42 seconds
Started Jul 07 05:50:53 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 219060 kb
Host smart-36cf3d94-38d7-41bb-aa3d-a6cfe1824796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137192091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4137192091
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1685672857
Short name T75
Test name
Test status
Simulation time 30236641 ps
CPU time 1.21 seconds
Started Jul 07 05:50:49 PM PDT 24
Finished Jul 07 05:50:50 PM PDT 24
Peak memory 219960 kb
Host smart-f15d5f2d-27e9-4754-a7e6-3cb2c997138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685672857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1685672857
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2547812641
Short name T130
Test name
Test status
Simulation time 38275968 ps
CPU time 0.9 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:53 PM PDT 24
Peak memory 219992 kb
Host smart-cbfb7350-10ad-4e19-b912-b302eb11d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547812641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2547812641
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.173025123
Short name T331
Test name
Test status
Simulation time 82148786 ps
CPU time 1.35 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 219356 kb
Host smart-e01ff373-846f-421d-b544-2d533fa3b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173025123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.173025123
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1361016508
Short name T611
Test name
Test status
Simulation time 27933146 ps
CPU time 1.34 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 219088 kb
Host smart-8e82493d-de2e-4d25-91a2-0c7935e3e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361016508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1361016508
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3895659220
Short name T149
Test name
Test status
Simulation time 19749480 ps
CPU time 1.13 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 218740 kb
Host smart-c9243fb3-f3eb-4478-8699-aff2a5b1e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895659220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3895659220
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2397506662
Short name T896
Test name
Test status
Simulation time 64533279 ps
CPU time 1.08 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 217500 kb
Host smart-43e6e6c5-5dbc-4ced-b8dd-cd7e64a4c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397506662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2397506662
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1685951409
Short name T733
Test name
Test status
Simulation time 50122121 ps
CPU time 1.27 seconds
Started Jul 07 05:50:57 PM PDT 24
Finished Jul 07 05:50:58 PM PDT 24
Peak memory 216020 kb
Host smart-8356b94d-bf8d-4922-b6d2-2d239ba10b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685951409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1685951409
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.259840748
Short name T665
Test name
Test status
Simulation time 41059318 ps
CPU time 0.99 seconds
Started Jul 07 05:50:53 PM PDT 24
Finished Jul 07 05:50:55 PM PDT 24
Peak memory 219016 kb
Host smart-30e649ac-bec7-467e-a1da-89a7f9211b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259840748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.259840748
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2742423119
Short name T89
Test name
Test status
Simulation time 54608178 ps
CPU time 1.2 seconds
Started Jul 07 05:50:56 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 217628 kb
Host smart-cce38795-27d1-4f8a-9b56-081f74b51aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742423119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2742423119
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2396544932
Short name T592
Test name
Test status
Simulation time 28926739 ps
CPU time 1.34 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 220016 kb
Host smart-611bd1b3-e048-4464-9849-22c5e82166dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396544932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2396544932
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.823938159
Short name T181
Test name
Test status
Simulation time 19393824 ps
CPU time 1.27 seconds
Started Jul 07 05:50:56 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 224312 kb
Host smart-283c7c41-082f-4e0b-a6bb-5fa23d59832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823938159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.823938159
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2522196017
Short name T499
Test name
Test status
Simulation time 29240736 ps
CPU time 1.31 seconds
Started Jul 07 05:50:57 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 219744 kb
Host smart-161b784e-be1d-474a-ae8f-073353711bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522196017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2522196017
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1374529395
Short name T551
Test name
Test status
Simulation time 24850335 ps
CPU time 1.26 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 221532 kb
Host smart-9432ef5a-de4c-4f60-9cd2-9f22a7f43f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374529395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1374529395
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2873344600
Short name T188
Test name
Test status
Simulation time 20218253 ps
CPU time 1.08 seconds
Started Jul 07 05:50:52 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 218696 kb
Host smart-96b14b34-9c7b-4225-a55b-41cd2fc8d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873344600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2873344600
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2001126856
Short name T416
Test name
Test status
Simulation time 33495745 ps
CPU time 1.32 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 218708 kb
Host smart-e0770705-99d4-4f05-9985-f81d6364a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001126856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2001126856
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3669051925
Short name T980
Test name
Test status
Simulation time 74422667 ps
CPU time 1.19 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:37 PM PDT 24
Peak memory 220284 kb
Host smart-6c17a8d6-8ea2-462e-83b5-21866451b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669051925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3669051925
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1161490416
Short name T555
Test name
Test status
Simulation time 77554376 ps
CPU time 0.88 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 215196 kb
Host smart-defae6fb-ba21-47e2-b5f2-a5cc0a009fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161490416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1161490416
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4172445053
Short name T193
Test name
Test status
Simulation time 19756053 ps
CPU time 0.9 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 216640 kb
Host smart-f48365aa-fdd0-4c61-a426-88f6a1dc410e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172445053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4172445053
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3785191551
Short name T941
Test name
Test status
Simulation time 22519915 ps
CPU time 1.04 seconds
Started Jul 07 05:49:43 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 220012 kb
Host smart-b88007ea-fe9c-40bd-b1a6-038f172ec840
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785191551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3785191551
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.274036440
Short name T6
Test name
Test status
Simulation time 19571393 ps
CPU time 1.08 seconds
Started Jul 07 05:49:38 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 219920 kb
Host smart-39f981d1-9cb9-4a62-8866-b8ac2d3b6e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274036440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.274036440
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.368093564
Short name T651
Test name
Test status
Simulation time 72732819 ps
CPU time 1.38 seconds
Started Jul 07 05:49:38 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 218844 kb
Host smart-9ba9df95-ba31-4ae2-9ff8-701eb8665614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368093564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.368093564
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.508242024
Short name T42
Test name
Test status
Simulation time 49777971 ps
CPU time 0.86 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 215860 kb
Host smart-a862b178-f22f-4f2d-a36e-df3b7bfa00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508242024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.508242024
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4133636342
Short name T29
Test name
Test status
Simulation time 44878707 ps
CPU time 1 seconds
Started Jul 07 05:49:41 PM PDT 24
Finished Jul 07 05:49:42 PM PDT 24
Peak memory 207412 kb
Host smart-1f7d4a9e-8203-439e-ab38-a9d214b964b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133636342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4133636342
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1642704493
Short name T855
Test name
Test status
Simulation time 17085569 ps
CPU time 0.94 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 215632 kb
Host smart-d524faf5-ec7e-453a-bbed-3c830726d750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642704493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1642704493
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2604630465
Short name T790
Test name
Test status
Simulation time 882137117 ps
CPU time 4.71 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 217616 kb
Host smart-9bac2f6b-1cd6-4e7c-91e1-4bb99af3b49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604630465 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2604630465
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3408439942
Short name T589
Test name
Test status
Simulation time 44106953859 ps
CPU time 499.34 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 219196 kb
Host smart-faf7116f-8615-4295-b62e-dfa27186a6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408439942 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3408439942
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3899403618
Short name T176
Test name
Test status
Simulation time 22814239 ps
CPU time 0.97 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 218680 kb
Host smart-79867ce1-7523-4fc3-9a5a-edb5468d07ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899403618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3899403618
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1158591521
Short name T69
Test name
Test status
Simulation time 42564555 ps
CPU time 1.12 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 217552 kb
Host smart-919c4957-b582-4cda-b4bc-c19efb26e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158591521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1158591521
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3277428552
Short name T314
Test name
Test status
Simulation time 438444184 ps
CPU time 1.48 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 219772 kb
Host smart-97ab4732-c38f-4aa3-a4d4-8b97add3a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277428552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3277428552
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1654043875
Short name T8
Test name
Test status
Simulation time 29283786 ps
CPU time 1.27 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 221192 kb
Host smart-f42c5db0-37ab-45d3-b51b-2156576cd34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654043875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1654043875
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1994154846
Short name T721
Test name
Test status
Simulation time 104498557 ps
CPU time 1.14 seconds
Started Jul 07 05:50:53 PM PDT 24
Finished Jul 07 05:50:55 PM PDT 24
Peak memory 219048 kb
Host smart-ef89b0be-7ddb-4164-a007-f35db8fe7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994154846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1994154846
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.322590929
Short name T343
Test name
Test status
Simulation time 24762429 ps
CPU time 1.22 seconds
Started Jul 07 05:50:54 PM PDT 24
Finished Jul 07 05:50:56 PM PDT 24
Peak memory 218916 kb
Host smart-ccf9baf2-a04c-44a5-b9de-3c31ba6b091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322590929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.322590929
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1547576155
Short name T674
Test name
Test status
Simulation time 20643028 ps
CPU time 1.19 seconds
Started Jul 07 05:50:57 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 220016 kb
Host smart-2153e2c1-9b96-419f-b7bc-50f79fdd712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547576155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1547576155
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.116160936
Short name T728
Test name
Test status
Simulation time 145548219 ps
CPU time 1.19 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 217584 kb
Host smart-fa279231-a282-499e-86dc-83627006b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116160936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.116160936
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.262680610
Short name T856
Test name
Test status
Simulation time 41765674 ps
CPU time 1.19 seconds
Started Jul 07 05:51:00 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 220220 kb
Host smart-358774a3-0bf9-4218-995a-ab7dc1e2f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262680610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.262680610
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1727303509
Short name T163
Test name
Test status
Simulation time 25830072 ps
CPU time 1.01 seconds
Started Jul 07 05:50:55 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 218856 kb
Host smart-b7cdbde2-0ccb-44d3-a44f-eced32b0b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727303509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1727303509
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2927047230
Short name T477
Test name
Test status
Simulation time 100572894 ps
CPU time 1.23 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:51:00 PM PDT 24
Peak memory 217776 kb
Host smart-d17a3143-7e81-4240-a270-93c6caa086a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927047230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2927047230
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2521830156
Short name T879
Test name
Test status
Simulation time 27085567 ps
CPU time 1.25 seconds
Started Jul 07 05:51:03 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 219116 kb
Host smart-27aa3bd6-40b2-4e1a-83ad-f6da678da61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521830156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2521830156
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.384934030
Short name T70
Test name
Test status
Simulation time 47004355 ps
CPU time 0.88 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 218744 kb
Host smart-a85bc204-03c4-41c8-bf0f-fb1040506983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384934030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.384934030
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.23477143
Short name T570
Test name
Test status
Simulation time 43036883 ps
CPU time 1.43 seconds
Started Jul 07 05:50:56 PM PDT 24
Finished Jul 07 05:50:58 PM PDT 24
Peak memory 218796 kb
Host smart-ea8ef6a0-241e-4617-ac66-5028eaa7c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23477143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.23477143
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3503792291
Short name T122
Test name
Test status
Simulation time 51371805 ps
CPU time 1.18 seconds
Started Jul 07 05:50:59 PM PDT 24
Finished Jul 07 05:51:01 PM PDT 24
Peak memory 219964 kb
Host smart-3ffb9a19-a543-4821-b396-1f38c1fe36de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503792291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3503792291
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.66734823
Short name T205
Test name
Test status
Simulation time 21708986 ps
CPU time 0.96 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 218540 kb
Host smart-313df52f-7cb5-4f72-b4d7-50d1fc58a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66734823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.66734823
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.413337256
Short name T588
Test name
Test status
Simulation time 46090844 ps
CPU time 1.82 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 218872 kb
Host smart-e1834599-98f3-4d6c-9ed1-6a18396069e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413337256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.413337256
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.899382669
Short name T15
Test name
Test status
Simulation time 71823825 ps
CPU time 1.04 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 229712 kb
Host smart-a8f33f06-66d5-4474-910b-119dd1328451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899382669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.899382669
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3064550262
Short name T688
Test name
Test status
Simulation time 61382202 ps
CPU time 1.43 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:51:00 PM PDT 24
Peak memory 219068 kb
Host smart-2959f4c8-e784-4546-a180-46e86b687ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064550262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3064550262
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2367395771
Short name T469
Test name
Test status
Simulation time 35381818 ps
CPU time 1.14 seconds
Started Jul 07 05:50:59 PM PDT 24
Finished Jul 07 05:51:01 PM PDT 24
Peak memory 218908 kb
Host smart-cbb26afe-19d1-4081-be45-7236a68ee325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367395771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2367395771
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3473452772
Short name T606
Test name
Test status
Simulation time 19614195 ps
CPU time 1.19 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:51:00 PM PDT 24
Peak memory 224260 kb
Host smart-d1988fbc-007f-4d14-b9b7-fae18784cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473452772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3473452772
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1793944202
Short name T702
Test name
Test status
Simulation time 58241621 ps
CPU time 1.29 seconds
Started Jul 07 05:50:58 PM PDT 24
Finished Jul 07 05:50:59 PM PDT 24
Peak memory 217564 kb
Host smart-639dd399-5bf2-4da1-9bf3-d3598a551d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793944202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1793944202
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2605335065
Short name T536
Test name
Test status
Simulation time 225413570 ps
CPU time 1.28 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 219976 kb
Host smart-41a8eb15-8159-4aab-bf04-00d6a4253468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605335065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2605335065
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2845275735
Short name T689
Test name
Test status
Simulation time 30397834 ps
CPU time 0.88 seconds
Started Jul 07 05:51:05 PM PDT 24
Finished Jul 07 05:51:06 PM PDT 24
Peak memory 218644 kb
Host smart-34e82347-1cff-4faa-92d5-ef32796e0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845275735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2845275735
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.750230220
Short name T108
Test name
Test status
Simulation time 72636187 ps
CPU time 1.26 seconds
Started Jul 07 05:50:57 PM PDT 24
Finished Jul 07 05:50:58 PM PDT 24
Peak memory 217556 kb
Host smart-10e0b016-5134-48f3-965d-eb3aa0f2254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750230220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.750230220
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.30020350
Short name T414
Test name
Test status
Simulation time 25622617 ps
CPU time 1.24 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 219948 kb
Host smart-8c35250a-2222-4e44-a4c7-bd9ef44e6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30020350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.30020350
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1353284488
Short name T61
Test name
Test status
Simulation time 32208891 ps
CPU time 1.02 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 224072 kb
Host smart-f57b26fb-dc32-4368-823e-c17e9fe3b013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353284488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1353284488
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1353810786
Short name T743
Test name
Test status
Simulation time 106136639 ps
CPU time 1.07 seconds
Started Jul 07 05:51:00 PM PDT 24
Finished Jul 07 05:51:01 PM PDT 24
Peak memory 217556 kb
Host smart-82d8488b-6edd-47a2-b28f-7ab3c1446067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353810786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1353810786
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3223479195
Short name T830
Test name
Test status
Simulation time 87700230 ps
CPU time 1.2 seconds
Started Jul 07 05:49:35 PM PDT 24
Finished Jul 07 05:49:37 PM PDT 24
Peak memory 220580 kb
Host smart-3475530b-a7f8-4602-95b2-2cebea2d7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223479195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3223479195
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1729933870
Short name T358
Test name
Test status
Simulation time 22259088 ps
CPU time 0.89 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 207028 kb
Host smart-892abbbc-7046-4dec-b85d-c138994cc600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729933870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1729933870
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.377294724
Short name T211
Test name
Test status
Simulation time 41719760 ps
CPU time 0.91 seconds
Started Jul 07 05:49:39 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 216580 kb
Host smart-6c9bad39-8ee6-4b97-a2e2-9532f3e9761b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377294724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.377294724
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3945839101
Short name T153
Test name
Test status
Simulation time 32539131 ps
CPU time 1.03 seconds
Started Jul 07 05:49:41 PM PDT 24
Finished Jul 07 05:49:43 PM PDT 24
Peak memory 217236 kb
Host smart-de16b16b-b8fd-4b54-a87c-073fa45b8202
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945839101 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3945839101
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2002082451
Short name T169
Test name
Test status
Simulation time 36316865 ps
CPU time 0.87 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 218792 kb
Host smart-febfdae2-96e4-4c91-adf0-af6792b341ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002082451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2002082451
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2465877200
Short name T90
Test name
Test status
Simulation time 27433009 ps
CPU time 1.21 seconds
Started Jul 07 05:49:39 PM PDT 24
Finished Jul 07 05:49:41 PM PDT 24
Peak memory 218916 kb
Host smart-54f83738-9ee5-49e8-8754-ccd40a2690f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465877200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2465877200
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3184752644
Short name T835
Test name
Test status
Simulation time 23550179 ps
CPU time 1.01 seconds
Started Jul 07 05:49:38 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 216156 kb
Host smart-87121b53-2578-42d9-8511-435228c5199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184752644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3184752644
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1874239071
Short name T913
Test name
Test status
Simulation time 26662406 ps
CPU time 0.9 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:37 PM PDT 24
Peak memory 207412 kb
Host smart-06756753-1707-4ed3-8e82-b75cbc59c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874239071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1874239071
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3543763313
Short name T628
Test name
Test status
Simulation time 15066911 ps
CPU time 0.96 seconds
Started Jul 07 05:49:37 PM PDT 24
Finished Jul 07 05:49:39 PM PDT 24
Peak memory 215552 kb
Host smart-416912d2-27c1-4074-93dd-5d8de46710ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543763313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3543763313
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2262101973
Short name T365
Test name
Test status
Simulation time 68758446 ps
CPU time 2 seconds
Started Jul 07 05:49:36 PM PDT 24
Finished Jul 07 05:49:38 PM PDT 24
Peak memory 215628 kb
Host smart-771803b7-571e-459e-bc53-b0a9a40a7e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262101973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2262101973
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.660930812
Short name T898
Test name
Test status
Simulation time 82549485630 ps
CPU time 370.91 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:55:54 PM PDT 24
Peak memory 219040 kb
Host smart-6cd91c72-32d0-4091-8bcb-41efc3809eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660930812 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.660930812
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2651524959
Short name T132
Test name
Test status
Simulation time 125466530 ps
CPU time 1.3 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:02 PM PDT 24
Peak memory 219924 kb
Host smart-7f558cf1-2a7a-40a4-bccc-433387b5f91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651524959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2651524959
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1623853642
Short name T747
Test name
Test status
Simulation time 20558531 ps
CPU time 1.2 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 220180 kb
Host smart-a4f47313-efc5-47fa-9abd-9a94289ff8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623853642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1623853642
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.593252440
Short name T963
Test name
Test status
Simulation time 54172626 ps
CPU time 1.32 seconds
Started Jul 07 05:51:05 PM PDT 24
Finished Jul 07 05:51:06 PM PDT 24
Peak memory 217756 kb
Host smart-e7647608-8e45-4bc2-bf6d-e3fa3e3df1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593252440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.593252440
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1205636379
Short name T345
Test name
Test status
Simulation time 29925792 ps
CPU time 1.34 seconds
Started Jul 07 05:51:03 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 216132 kb
Host smart-286a31f8-fe79-4cce-947b-d490a89e9b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205636379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1205636379
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1346311868
Short name T486
Test name
Test status
Simulation time 22846383 ps
CPU time 1.25 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 224244 kb
Host smart-d36c6946-b638-4087-baef-b0d581f97a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346311868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1346311868
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.979289302
Short name T48
Test name
Test status
Simulation time 49450983 ps
CPU time 1.57 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:04 PM PDT 24
Peak memory 217568 kb
Host smart-28074407-b9ae-41e7-afb4-67eb5d025011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979289302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.979289302
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.204716219
Short name T770
Test name
Test status
Simulation time 196462963 ps
CPU time 1.24 seconds
Started Jul 07 05:51:00 PM PDT 24
Finished Jul 07 05:51:01 PM PDT 24
Peak memory 220680 kb
Host smart-48a73773-664c-4176-b7f6-7ad30c054abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204716219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.204716219
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3177169993
Short name T183
Test name
Test status
Simulation time 25336888 ps
CPU time 0.98 seconds
Started Jul 07 05:51:02 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 224008 kb
Host smart-84b6b9bb-ebd6-4d18-a381-ae266f15445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177169993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3177169993
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1364837565
Short name T396
Test name
Test status
Simulation time 49096358 ps
CPU time 1.1 seconds
Started Jul 07 05:51:01 PM PDT 24
Finished Jul 07 05:51:03 PM PDT 24
Peak memory 220164 kb
Host smart-0cffd9ec-d926-41e8-8ef8-a60e3af1114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364837565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1364837565
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3252642760
Short name T86
Test name
Test status
Simulation time 30644366 ps
CPU time 1.32 seconds
Started Jul 07 05:51:04 PM PDT 24
Finished Jul 07 05:51:06 PM PDT 24
Peak memory 220712 kb
Host smart-7e1b5325-0564-4f71-bf4b-248f1c9445fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252642760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3252642760
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1994880249
Short name T372
Test name
Test status
Simulation time 30100568 ps
CPU time 0.98 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 219984 kb
Host smart-c4b5288d-bafb-4b25-86bb-db09a1fb3837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994880249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1994880249
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1052000062
Short name T517
Test name
Test status
Simulation time 219031290 ps
CPU time 2.96 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:09 PM PDT 24
Peak memory 218164 kb
Host smart-fea0e05b-0da1-4060-a35b-392ab0ca3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052000062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1052000062
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.638723014
Short name T872
Test name
Test status
Simulation time 48242804 ps
CPU time 1.24 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 218848 kb
Host smart-cee86cb0-469a-41c2-a04c-ba95357af457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638723014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.638723014
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2117423189
Short name T39
Test name
Test status
Simulation time 28581968 ps
CPU time 0.93 seconds
Started Jul 07 05:51:04 PM PDT 24
Finished Jul 07 05:51:05 PM PDT 24
Peak memory 219016 kb
Host smart-80c6480b-2a61-4010-888c-319c4413c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117423189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2117423189
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2217910984
Short name T826
Test name
Test status
Simulation time 61252915 ps
CPU time 1.12 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 218896 kb
Host smart-ae2c4605-26b7-4b98-b38d-2d30e64b397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217910984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2217910984
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.572113840
Short name T775
Test name
Test status
Simulation time 88556453 ps
CPU time 1.24 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:09 PM PDT 24
Peak memory 219964 kb
Host smart-8844096c-ce69-4abb-9699-c82055878e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572113840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.572113840
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.312040943
Short name T658
Test name
Test status
Simulation time 32074908 ps
CPU time 0.96 seconds
Started Jul 07 05:51:13 PM PDT 24
Finished Jul 07 05:51:15 PM PDT 24
Peak memory 218624 kb
Host smart-04841f48-6ceb-4293-b681-0c61270df9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312040943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.312040943
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1752933034
Short name T392
Test name
Test status
Simulation time 48372968 ps
CPU time 1.54 seconds
Started Jul 07 05:51:04 PM PDT 24
Finished Jul 07 05:51:05 PM PDT 24
Peak memory 218724 kb
Host smart-a4fcf685-6884-4008-9a0f-71c54a124c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752933034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1752933034
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3442807131
Short name T66
Test name
Test status
Simulation time 100908637 ps
CPU time 1.25 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 221544 kb
Host smart-4184a178-c826-4b7d-a338-166e5ffe501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442807131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3442807131
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.951374614
Short name T134
Test name
Test status
Simulation time 37378518 ps
CPU time 1.2 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 220876 kb
Host smart-933019c2-afc9-4aac-8c16-ff6dd5b7162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951374614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.951374614
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1500894321
Short name T600
Test name
Test status
Simulation time 35972266 ps
CPU time 1.41 seconds
Started Jul 07 05:51:04 PM PDT 24
Finished Jul 07 05:51:06 PM PDT 24
Peak memory 220180 kb
Host smart-73868626-0e51-4bbd-b32b-d144ff97547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500894321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1500894321
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1372927946
Short name T597
Test name
Test status
Simulation time 27392866 ps
CPU time 1.25 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 219012 kb
Host smart-d0df4e9c-fd9f-4715-87a6-fbe97731ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372927946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1372927946
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1769033018
Short name T220
Test name
Test status
Simulation time 22653809 ps
CPU time 0.98 seconds
Started Jul 07 05:51:05 PM PDT 24
Finished Jul 07 05:51:06 PM PDT 24
Peak memory 218816 kb
Host smart-f5186209-c7d0-4947-a323-c81dcc77810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769033018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1769033018
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3614580209
Short name T890
Test name
Test status
Simulation time 80776106 ps
CPU time 1.15 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 217548 kb
Host smart-555fd837-3e6e-4b77-ae57-c19680b3e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614580209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3614580209
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2871226042
Short name T609
Test name
Test status
Simulation time 24814308 ps
CPU time 1.2 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 216020 kb
Host smart-c925660d-5e4e-4991-ba37-1db5af7c5e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871226042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2871226042
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2705918577
Short name T63
Test name
Test status
Simulation time 70638439 ps
CPU time 1.22 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:10 PM PDT 24
Peak memory 226072 kb
Host smart-97a6921f-81f2-4dd9-bfc7-51395e354c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705918577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2705918577
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3360943697
Short name T466
Test name
Test status
Simulation time 35141436 ps
CPU time 1.58 seconds
Started Jul 07 05:51:06 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 219028 kb
Host smart-ea59f1f9-d37c-45af-a72a-9cda657a1d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360943697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3360943697
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.555684178
Short name T967
Test name
Test status
Simulation time 194818442 ps
CPU time 1.13 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:10 PM PDT 24
Peak memory 220104 kb
Host smart-7487648f-f164-4bd6-adec-89ab59f1d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555684178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.555684178
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.4077252073
Short name T7
Test name
Test status
Simulation time 35685044 ps
CPU time 1 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:12 PM PDT 24
Peak memory 220188 kb
Host smart-a699905e-017d-4285-b8ff-a244abb3ba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077252073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4077252073
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3250648293
Short name T453
Test name
Test status
Simulation time 105984850 ps
CPU time 1.25 seconds
Started Jul 07 05:51:04 PM PDT 24
Finished Jul 07 05:51:05 PM PDT 24
Peak memory 217652 kb
Host smart-3995189b-996f-4f47-8538-86b4b8f665e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250648293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3250648293
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert_test.2439148183
Short name T452
Test name
Test status
Simulation time 32621840 ps
CPU time 0.8 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 206612 kb
Host smart-58cb4d9a-8a39-4a0c-956e-a1b925d56611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439148183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2439148183
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2131868169
Short name T759
Test name
Test status
Simulation time 51282481 ps
CPU time 0.84 seconds
Started Jul 07 05:49:42 PM PDT 24
Finished Jul 07 05:49:43 PM PDT 24
Peak memory 216236 kb
Host smart-8c97e7c3-aa16-4c2b-a901-0b4e10135404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131868169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2131868169
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1083765190
Short name T534
Test name
Test status
Simulation time 24735938 ps
CPU time 1.1 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 217232 kb
Host smart-fdc48ab1-47c9-4b69-a7c2-972e46fe56ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083765190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1083765190
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.612666544
Short name T815
Test name
Test status
Simulation time 31703488 ps
CPU time 0.88 seconds
Started Jul 07 05:49:40 PM PDT 24
Finished Jul 07 05:49:41 PM PDT 24
Peak memory 218720 kb
Host smart-30d0f836-8be7-40e5-b704-73934f067e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612666544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.612666544
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1348853176
Short name T506
Test name
Test status
Simulation time 79357444 ps
CPU time 1.28 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 217800 kb
Host smart-c0888075-212e-4cf2-b19e-b9a8d2a1dc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348853176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1348853176
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.810256372
Short name T814
Test name
Test status
Simulation time 23584999 ps
CPU time 1.11 seconds
Started Jul 07 05:49:39 PM PDT 24
Finished Jul 07 05:49:40 PM PDT 24
Peak memory 216152 kb
Host smart-ea574ae9-56f0-47e7-8905-4969f332fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810256372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.810256372
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3601719449
Short name T257
Test name
Test status
Simulation time 48503824 ps
CPU time 0.91 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:47 PM PDT 24
Peak memory 207376 kb
Host smart-46c534d9-8c83-4d30-b045-0fbca70c9db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601719449 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3601719449
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1018088086
Short name T976
Test name
Test status
Simulation time 71082154 ps
CPU time 0.93 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 215652 kb
Host smart-73beeca3-99ad-4a69-bd94-1d782ffd6e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018088086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1018088086
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.768793967
Short name T662
Test name
Test status
Simulation time 187501325 ps
CPU time 2.33 seconds
Started Jul 07 05:49:40 PM PDT 24
Finished Jul 07 05:49:43 PM PDT 24
Peak memory 218808 kb
Host smart-e3b1f2db-bf46-49af-80b6-c68c3cd4fb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768793967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.768793967
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.725010633
Short name T250
Test name
Test status
Simulation time 81107499416 ps
CPU time 906 seconds
Started Jul 07 05:49:45 PM PDT 24
Finished Jul 07 06:04:51 PM PDT 24
Peak memory 224096 kb
Host smart-9598a894-5a22-43a6-b856-6a68a0bd4e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725010633 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.725010633
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3801656590
Short name T684
Test name
Test status
Simulation time 22961861 ps
CPU time 1.18 seconds
Started Jul 07 05:51:14 PM PDT 24
Finished Jul 07 05:51:16 PM PDT 24
Peak memory 219136 kb
Host smart-e0ba32f0-0fe7-4459-a5cd-90a10a9c4a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801656590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3801656590
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.995252311
Short name T206
Test name
Test status
Simulation time 26913487 ps
CPU time 0.83 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:12 PM PDT 24
Peak memory 218584 kb
Host smart-1f2259c6-a602-486f-ad27-93bf5e86b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995252311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.995252311
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4076337332
Short name T843
Test name
Test status
Simulation time 54935662 ps
CPU time 1.25 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:10 PM PDT 24
Peak memory 217648 kb
Host smart-8bb47e0e-e5ce-4866-bbdf-2ebbeedbecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076337332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4076337332
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.653661294
Short name T954
Test name
Test status
Simulation time 99879294 ps
CPU time 1.4 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:08 PM PDT 24
Peak memory 220172 kb
Host smart-c46fbbd2-8101-43cd-9bfb-135e15e5593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653661294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.653661294
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2090748669
Short name T468
Test name
Test status
Simulation time 56737611 ps
CPU time 0.83 seconds
Started Jul 07 05:51:13 PM PDT 24
Finished Jul 07 05:51:14 PM PDT 24
Peak memory 218620 kb
Host smart-6b3df165-a7cb-4aff-af88-df5e28f193dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090748669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2090748669
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.619360760
Short name T349
Test name
Test status
Simulation time 73608529 ps
CPU time 2.73 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:14 PM PDT 24
Peak memory 220596 kb
Host smart-ea22d1dc-334f-4c90-a7a2-238d26650962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619360760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.619360760
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3338921343
Short name T557
Test name
Test status
Simulation time 35648998 ps
CPU time 1.27 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 219960 kb
Host smart-e3dd5c80-3ceb-4ab2-813f-7f7f72a01af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338921343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3338921343
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.822088317
Short name T88
Test name
Test status
Simulation time 29842191 ps
CPU time 1.24 seconds
Started Jul 07 05:51:07 PM PDT 24
Finished Jul 07 05:51:09 PM PDT 24
Peak memory 219992 kb
Host smart-a707560c-4ac3-4b74-a5c5-99bb6b595c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822088317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.822088317
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1850722138
Short name T500
Test name
Test status
Simulation time 88373519 ps
CPU time 1.66 seconds
Started Jul 07 05:51:12 PM PDT 24
Finished Jul 07 05:51:14 PM PDT 24
Peak memory 218872 kb
Host smart-42905595-a6ee-4b2a-abcb-7e5c76a2c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850722138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1850722138
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3593135776
Short name T891
Test name
Test status
Simulation time 108395269 ps
CPU time 1.22 seconds
Started Jul 07 05:51:12 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 219940 kb
Host smart-e96ecd97-c22a-4e26-b311-d533500d42ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593135776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3593135776
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.171926282
Short name T887
Test name
Test status
Simulation time 30911589 ps
CPU time 0.89 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:12 PM PDT 24
Peak memory 218556 kb
Host smart-4dac85b8-354e-4b7b-a282-a421ecb374b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171926282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.171926282
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3165886979
Short name T367
Test name
Test status
Simulation time 69381177 ps
CPU time 1.44 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 217588 kb
Host smart-7affb250-098c-4a74-86a6-f26085a7401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165886979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3165886979
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3087674094
Short name T939
Test name
Test status
Simulation time 29381510 ps
CPU time 1.39 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 220300 kb
Host smart-4ce82230-6326-4e46-aada-5897d8f2999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087674094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3087674094
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2039777873
Short name T701
Test name
Test status
Simulation time 38751061 ps
CPU time 1.18 seconds
Started Jul 07 05:51:14 PM PDT 24
Finished Jul 07 05:51:15 PM PDT 24
Peak memory 220980 kb
Host smart-b30acb74-b34f-4175-9fd0-48d2bbdd07cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039777873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2039777873
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2023764048
Short name T772
Test name
Test status
Simulation time 58223231 ps
CPU time 1.57 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 218916 kb
Host smart-cecea12a-4f92-4ba9-9ed4-6ef225a64f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023764048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2023764048
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.561182380
Short name T187
Test name
Test status
Simulation time 37369743 ps
CPU time 1.16 seconds
Started Jul 07 05:51:10 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 219052 kb
Host smart-057a13f6-9eac-48c7-9a74-e42a62428bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561182380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.561182380
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1940252979
Short name T146
Test name
Test status
Simulation time 36800040 ps
CPU time 0.95 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 220092 kb
Host smart-ed4a5f39-8bb1-44ac-b5bd-8d84cdd926e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940252979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1940252979
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3286238209
Short name T56
Test name
Test status
Simulation time 57190877 ps
CPU time 1.92 seconds
Started Jul 07 05:51:11 PM PDT 24
Finished Jul 07 05:51:13 PM PDT 24
Peak memory 218732 kb
Host smart-202d2937-ec1d-4243-9ec2-c6e033719804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286238209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3286238209
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1899664546
Short name T633
Test name
Test status
Simulation time 62263131 ps
CPU time 1.09 seconds
Started Jul 07 05:51:10 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 220168 kb
Host smart-28f70b39-1b8e-4210-982f-3ae14b086fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899664546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1899664546
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.67124622
Short name T857
Test name
Test status
Simulation time 32036728 ps
CPU time 1.15 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:11 PM PDT 24
Peak memory 224144 kb
Host smart-d4f20ab4-cf43-4291-b787-1b6b756c048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67124622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.67124622
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1302739229
Short name T435
Test name
Test status
Simulation time 39019640 ps
CPU time 1.1 seconds
Started Jul 07 05:51:09 PM PDT 24
Finished Jul 07 05:51:10 PM PDT 24
Peak memory 217760 kb
Host smart-64b018d4-6a9e-447f-8e4d-832674966497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302739229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1302739229
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3434482512
Short name T548
Test name
Test status
Simulation time 26154635 ps
CPU time 1.2 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 219736 kb
Host smart-d8a4b09f-07e8-4779-82d6-2af8d564a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434482512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3434482512
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1397278364
Short name T197
Test name
Test status
Simulation time 26741939 ps
CPU time 0.96 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 218840 kb
Host smart-86e97603-ccc7-44ac-9d26-9ee382c034f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397278364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1397278364
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2142327771
Short name T564
Test name
Test status
Simulation time 70684161 ps
CPU time 1.3 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 219012 kb
Host smart-354c6785-4abe-47c8-a2d4-108ffdf5b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142327771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2142327771
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3733806179
Short name T832
Test name
Test status
Simulation time 28554270 ps
CPU time 0.89 seconds
Started Jul 07 05:51:15 PM PDT 24
Finished Jul 07 05:51:16 PM PDT 24
Peak memory 218792 kb
Host smart-5437e9d6-6767-4225-832a-3297aa0da4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733806179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3733806179
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2890063194
Short name T822
Test name
Test status
Simulation time 52436815 ps
CPU time 1.12 seconds
Started Jul 07 05:51:13 PM PDT 24
Finished Jul 07 05:51:14 PM PDT 24
Peak memory 217564 kb
Host smart-1bac8187-8011-4c32-91da-c03c9cad8f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890063194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2890063194
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2807577497
Short name T678
Test name
Test status
Simulation time 66498195 ps
CPU time 1.18 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218900 kb
Host smart-ad5700b6-58b5-4dd8-8c5a-896ad186ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807577497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2807577497
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1694667892
Short name T926
Test name
Test status
Simulation time 22103862 ps
CPU time 0.97 seconds
Started Jul 07 05:51:14 PM PDT 24
Finished Jul 07 05:51:15 PM PDT 24
Peak memory 218780 kb
Host smart-dc7f9356-aa1f-412b-8ad8-2cf333894d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694667892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1694667892
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.362023646
Short name T21
Test name
Test status
Simulation time 109733999 ps
CPU time 2.33 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 219192 kb
Host smart-9105ccdf-cbbd-42ee-a1ed-55f6d0dc7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362023646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.362023646
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3620784263
Short name T174
Test name
Test status
Simulation time 23793129 ps
CPU time 1.14 seconds
Started Jul 07 05:49:43 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 220084 kb
Host smart-c063ad85-52c8-4087-b74e-34063e663e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620784263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3620784263
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2408249854
Short name T434
Test name
Test status
Simulation time 84196581 ps
CPU time 0.97 seconds
Started Jul 07 05:49:41 PM PDT 24
Finished Jul 07 05:49:42 PM PDT 24
Peak memory 207132 kb
Host smart-950db806-6cf2-41ef-80c2-9f07e50991b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408249854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2408249854
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4066837113
Short name T404
Test name
Test status
Simulation time 17223223 ps
CPU time 0.88 seconds
Started Jul 07 05:49:45 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 216408 kb
Host smart-027c74d9-88cd-403b-b9a8-f22cc3b7eccd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066837113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4066837113
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1691601069
Short name T23
Test name
Test status
Simulation time 37471838 ps
CPU time 1.39 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 217092 kb
Host smart-58784557-7bf7-42e1-beb3-e82439365617
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691601069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1691601069
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.737502291
Short name T177
Test name
Test status
Simulation time 21586423 ps
CPU time 0.98 seconds
Started Jul 07 05:49:44 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 218676 kb
Host smart-1337aede-d8e0-4a4e-9ab9-28e674bfa100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737502291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.737502291
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4059987739
Short name T569
Test name
Test status
Simulation time 41437477 ps
CPU time 1.47 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:48 PM PDT 24
Peak memory 218916 kb
Host smart-6861f552-3f6c-4e44-afaf-c8d8c3ef5172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059987739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4059987739
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3886269834
Short name T405
Test name
Test status
Simulation time 27546333 ps
CPU time 1.06 seconds
Started Jul 07 05:49:45 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 224320 kb
Host smart-1dc0f732-14d3-40af-937e-20e0bb56feb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886269834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3886269834
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.377599959
Short name T605
Test name
Test status
Simulation time 28537212 ps
CPU time 0.93 seconds
Started Jul 07 05:49:46 PM PDT 24
Finished Jul 07 05:49:47 PM PDT 24
Peak memory 207404 kb
Host smart-39176709-b2c6-4e38-8715-e28c84034b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377599959 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.377599959
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2517389823
Short name T816
Test name
Test status
Simulation time 31118560 ps
CPU time 1 seconds
Started Jul 07 05:49:40 PM PDT 24
Finished Jul 07 05:49:41 PM PDT 24
Peak memory 215636 kb
Host smart-62398288-ba7f-40e5-81c4-cdb532ed7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517389823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2517389823
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1241559437
Short name T382
Test name
Test status
Simulation time 419715902 ps
CPU time 3.03 seconds
Started Jul 07 05:49:41 PM PDT 24
Finished Jul 07 05:49:44 PM PDT 24
Peak memory 217628 kb
Host smart-80aa4fb3-f78f-4337-aa3c-828c12269129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241559437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1241559437
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1023603429
Short name T317
Test name
Test status
Simulation time 39353543388 ps
CPU time 237 seconds
Started Jul 07 05:49:47 PM PDT 24
Finished Jul 07 05:53:44 PM PDT 24
Peak memory 223808 kb
Host smart-8b7e0aba-9efd-4a98-b876-5aa7e1b8e306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023603429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1023603429
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3238900443
Short name T274
Test name
Test status
Simulation time 37345394 ps
CPU time 1.25 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 221144 kb
Host smart-e9bf2a8a-7974-4a6b-a93e-2d89d6f27721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238900443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3238900443
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3771398999
Short name T708
Test name
Test status
Simulation time 19275830 ps
CPU time 1.1 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 219840 kb
Host smart-8b48c9e5-3583-4054-ab3e-e4aede169589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771398999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3771398999
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3361004360
Short name T463
Test name
Test status
Simulation time 100941748 ps
CPU time 2.15 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 218908 kb
Host smart-7e8f392c-9cc0-4a31-9003-3b72e5ca1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361004360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3361004360
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1561122535
Short name T408
Test name
Test status
Simulation time 101676693 ps
CPU time 1.23 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 221868 kb
Host smart-0c373506-04fa-4483-9466-89b7888aa117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561122535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1561122535
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2898272307
Short name T199
Test name
Test status
Simulation time 32899845 ps
CPU time 0.99 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 224252 kb
Host smart-3824bb38-135d-44b8-8df5-be8118b57e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898272307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2898272307
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.739062578
Short name T677
Test name
Test status
Simulation time 96040563 ps
CPU time 1.62 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:31 PM PDT 24
Peak memory 219468 kb
Host smart-9ddebb0e-b475-419c-859c-8cbed3876e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739062578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.739062578
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.4176155234
Short name T165
Test name
Test status
Simulation time 24232522 ps
CPU time 1.3 seconds
Started Jul 07 05:51:25 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 220304 kb
Host smart-d33c7cc7-bdfd-4a93-9f77-ec65a54c9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176155234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.4176155234
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.4211312805
Short name T867
Test name
Test status
Simulation time 19724246 ps
CPU time 1.25 seconds
Started Jul 07 05:51:13 PM PDT 24
Finished Jul 07 05:51:14 PM PDT 24
Peak memory 224312 kb
Host smart-f33c2491-dcc1-47b6-afe6-c6d807d4a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211312805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4211312805
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3449778
Short name T653
Test name
Test status
Simulation time 39878570 ps
CPU time 1.5 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 218896 kb
Host smart-fa4971ae-fb04-482f-9ffb-9dd9b0e0e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3449778
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.507953759
Short name T948
Test name
Test status
Simulation time 117540720 ps
CPU time 1.31 seconds
Started Jul 07 05:51:14 PM PDT 24
Finished Jul 07 05:51:15 PM PDT 24
Peak memory 215928 kb
Host smart-6fbcf61f-b325-456d-bdc7-0c045046542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507953759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.507953759
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2726289288
Short name T221
Test name
Test status
Simulation time 44795793 ps
CPU time 1.17 seconds
Started Jul 07 05:51:27 PM PDT 24
Finished Jul 07 05:51:29 PM PDT 24
Peak memory 220008 kb
Host smart-fdfdbfbf-721d-4483-a50c-309ab6a3e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726289288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2726289288
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1618039832
Short name T803
Test name
Test status
Simulation time 42711029 ps
CPU time 1.54 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:31 PM PDT 24
Peak memory 218796 kb
Host smart-bb428357-f60f-42df-94c9-2c36a83e9563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618039832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1618039832
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1944387
Short name T692
Test name
Test status
Simulation time 62699761 ps
CPU time 1.2 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:23 PM PDT 24
Peak memory 218916 kb
Host smart-b14aa7bb-1f90-44df-b8af-0eb69b42837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1944387
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.194779257
Short name T219
Test name
Test status
Simulation time 25152373 ps
CPU time 0.91 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218908 kb
Host smart-7849b1c7-828e-4e92-a492-3f744c3f424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194779257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.194779257
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3003510710
Short name T328
Test name
Test status
Simulation time 69884330 ps
CPU time 2.42 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 219472 kb
Host smart-cb6a955d-8860-460b-b689-e167f48ab4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003510710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3003510710
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1269273683
Short name T876
Test name
Test status
Simulation time 31732769 ps
CPU time 1.35 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 215956 kb
Host smart-d3f6eee3-2b42-4804-9942-ca2137949617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269273683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1269273683
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2091284384
Short name T989
Test name
Test status
Simulation time 54363753 ps
CPU time 1.04 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 219040 kb
Host smart-7531e10b-beaf-41ff-96e8-bf486db2c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091284384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2091284384
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.4223703848
Short name T796
Test name
Test status
Simulation time 24689575 ps
CPU time 1.15 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 217648 kb
Host smart-e0cc01bf-00d3-4a01-a6c5-3aa4334a94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223703848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4223703848
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1396062056
Short name T858
Test name
Test status
Simulation time 42111898 ps
CPU time 1.1 seconds
Started Jul 07 05:51:19 PM PDT 24
Finished Jul 07 05:51:20 PM PDT 24
Peak memory 220044 kb
Host smart-7504c683-aa32-4e0b-a629-1dfaed124472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396062056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1396062056
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2037883916
Short name T192
Test name
Test status
Simulation time 20480994 ps
CPU time 1.15 seconds
Started Jul 07 05:51:21 PM PDT 24
Finished Jul 07 05:51:22 PM PDT 24
Peak memory 224272 kb
Host smart-5e6fc1ff-b73a-48d8-8a55-f5d347cd5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037883916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2037883916
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_alert.4090902803
Short name T139
Test name
Test status
Simulation time 29756751 ps
CPU time 1.33 seconds
Started Jul 07 05:51:28 PM PDT 24
Finished Jul 07 05:51:30 PM PDT 24
Peak memory 218936 kb
Host smart-70c8ac6b-bf34-440e-b0f5-2384f29a4a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090902803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.4090902803
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1825059393
Short name T215
Test name
Test status
Simulation time 28494843 ps
CPU time 0.85 seconds
Started Jul 07 05:51:19 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 218504 kb
Host smart-2e41eb98-4a67-42ce-93b3-a5c353f0516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825059393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1825059393
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2242396536
Short name T846
Test name
Test status
Simulation time 34599961 ps
CPU time 1.45 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:27 PM PDT 24
Peak memory 218792 kb
Host smart-45a8df62-dec8-4be1-8c26-66015d844805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242396536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2242396536
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3873277078
Short name T568
Test name
Test status
Simulation time 72237360 ps
CPU time 1.05 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 218980 kb
Host smart-2c928dcf-63cc-444e-82f2-900193e186b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873277078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3873277078
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.81962181
Short name T144
Test name
Test status
Simulation time 98366005 ps
CPU time 0.87 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:24 PM PDT 24
Peak memory 219964 kb
Host smart-9d3719b2-e713-456b-a426-959a766c0736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81962181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.81962181
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.485327840
Short name T696
Test name
Test status
Simulation time 94856781 ps
CPU time 1.37 seconds
Started Jul 07 05:51:20 PM PDT 24
Finished Jul 07 05:51:21 PM PDT 24
Peak memory 217792 kb
Host smart-7487fcac-4edb-425e-9ea3-16e2337ee843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485327840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.485327840
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.239901141
Short name T927
Test name
Test status
Simulation time 191207462 ps
CPU time 1.31 seconds
Started Jul 07 05:51:24 PM PDT 24
Finished Jul 07 05:51:26 PM PDT 24
Peak memory 221240 kb
Host smart-43d0c697-dc55-4e2e-8b38-e9360a0f5db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239901141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.239901141
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1717680998
Short name T764
Test name
Test status
Simulation time 22782048 ps
CPU time 0.91 seconds
Started Jul 07 05:51:23 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 218840 kb
Host smart-ee8c8eaa-54bf-4e02-a75f-f53fb4129f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717680998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1717680998
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.532095157
Short name T449
Test name
Test status
Simulation time 118112841 ps
CPU time 1.73 seconds
Started Jul 07 05:51:22 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 218956 kb
Host smart-b8e871f4-a36b-4e27-9d3d-02b399b0d035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532095157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.532095157
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%