Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08


Total test records in report: 1130
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T1016 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2681254597 Jul 09 05:44:03 PM PDT 24 Jul 09 05:44:07 PM PDT 24 63675443 ps
T1017 /workspace/coverage/cover_reg_top/33.edn_intr_test.2266456937 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:53 PM PDT 24 26494465 ps
T1018 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.172953598 Jul 09 05:43:56 PM PDT 24 Jul 09 05:43:58 PM PDT 24 39444173 ps
T265 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3454982010 Jul 09 05:43:52 PM PDT 24 Jul 09 05:43:54 PM PDT 24 54289180 ps
T288 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3067141657 Jul 09 05:44:02 PM PDT 24 Jul 09 05:44:05 PM PDT 24 41068815 ps
T1019 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2912415972 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:09 PM PDT 24 154744813 ps
T281 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.756052385 Jul 09 05:43:56 PM PDT 24 Jul 09 05:44:00 PM PDT 24 161463463 ps
T282 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.69622272 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:09 PM PDT 24 124656970 ps
T1020 /workspace/coverage/cover_reg_top/34.edn_intr_test.3515118063 Jul 09 05:44:11 PM PDT 24 Jul 09 05:44:15 PM PDT 24 44521057 ps
T266 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.117675456 Jul 09 05:43:48 PM PDT 24 Jul 09 05:43:49 PM PDT 24 135981416 ps
T283 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2795129998 Jul 09 05:43:57 PM PDT 24 Jul 09 05:44:01 PM PDT 24 174463178 ps
T1021 /workspace/coverage/cover_reg_top/14.edn_intr_test.530992590 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:53 PM PDT 24 18077979 ps
T1022 /workspace/coverage/cover_reg_top/17.edn_intr_test.1190691531 Jul 09 05:43:53 PM PDT 24 Jul 09 05:43:54 PM PDT 24 12561504 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1549179053 Jul 09 05:43:32 PM PDT 24 Jul 09 05:43:37 PM PDT 24 112390255 ps
T1024 /workspace/coverage/cover_reg_top/6.edn_csr_rw.339705516 Jul 09 05:43:46 PM PDT 24 Jul 09 05:43:48 PM PDT 24 38437829 ps
T267 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3528922035 Jul 09 05:43:55 PM PDT 24 Jul 09 05:43:58 PM PDT 24 24349689 ps
T1025 /workspace/coverage/cover_reg_top/38.edn_intr_test.879640894 Jul 09 05:44:06 PM PDT 24 Jul 09 05:44:09 PM PDT 24 25958447 ps
T1026 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.245393468 Jul 09 05:43:49 PM PDT 24 Jul 09 05:43:51 PM PDT 24 207513818 ps
T1027 /workspace/coverage/cover_reg_top/13.edn_csr_rw.4125136194 Jul 09 05:43:55 PM PDT 24 Jul 09 05:43:56 PM PDT 24 12073671 ps
T1028 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1840000897 Jul 09 05:43:32 PM PDT 24 Jul 09 05:43:35 PM PDT 24 49189507 ps
T1029 /workspace/coverage/cover_reg_top/16.edn_intr_test.3845996925 Jul 09 05:43:52 PM PDT 24 Jul 09 05:43:54 PM PDT 24 21134667 ps
T1030 /workspace/coverage/cover_reg_top/18.edn_csr_rw.129654951 Jul 09 05:43:57 PM PDT 24 Jul 09 05:44:00 PM PDT 24 40725320 ps
T1031 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2742696862 Jul 09 05:43:56 PM PDT 24 Jul 09 05:44:03 PM PDT 24 37059676 ps
T1032 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3081984346 Jul 09 05:43:57 PM PDT 24 Jul 09 05:43:59 PM PDT 24 26016901 ps
T284 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2442153817 Jul 09 05:43:56 PM PDT 24 Jul 09 05:43:58 PM PDT 24 271957195 ps
T1033 /workspace/coverage/cover_reg_top/25.edn_intr_test.3078613492 Jul 09 05:43:59 PM PDT 24 Jul 09 05:44:01 PM PDT 24 11156790 ps
T1034 /workspace/coverage/cover_reg_top/40.edn_intr_test.3457703226 Jul 09 05:44:14 PM PDT 24 Jul 09 05:44:18 PM PDT 24 37221997 ps
T1035 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1612318559 Jul 09 05:44:03 PM PDT 24 Jul 09 05:44:07 PM PDT 24 39293229 ps
T1036 /workspace/coverage/cover_reg_top/31.edn_intr_test.2494301541 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 51680900 ps
T1037 /workspace/coverage/cover_reg_top/5.edn_intr_test.3406383948 Jul 09 05:43:49 PM PDT 24 Jul 09 05:43:50 PM PDT 24 45050522 ps
T1038 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2252651847 Jul 09 05:44:14 PM PDT 24 Jul 09 05:44:18 PM PDT 24 24689413 ps
T1039 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1198532383 Jul 09 05:44:09 PM PDT 24 Jul 09 05:44:12 PM PDT 24 11501572 ps
T1040 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1662110090 Jul 09 05:44:07 PM PDT 24 Jul 09 05:44:11 PM PDT 24 71475758 ps
T1041 /workspace/coverage/cover_reg_top/43.edn_intr_test.3124521384 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 30642430 ps
T1042 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3026848280 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 23509286 ps
T285 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1273763996 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:43 PM PDT 24 88934222 ps
T1043 /workspace/coverage/cover_reg_top/11.edn_intr_test.3310840380 Jul 09 05:43:41 PM PDT 24 Jul 09 05:43:43 PM PDT 24 76873228 ps
T1044 /workspace/coverage/cover_reg_top/47.edn_intr_test.2852346485 Jul 09 05:44:02 PM PDT 24 Jul 09 05:44:05 PM PDT 24 25400630 ps
T1045 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3000137928 Jul 09 05:43:46 PM PDT 24 Jul 09 05:43:49 PM PDT 24 28543204 ps
T1046 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4080206426 Jul 09 05:43:36 PM PDT 24 Jul 09 05:43:42 PM PDT 24 169261800 ps
T1047 /workspace/coverage/cover_reg_top/48.edn_intr_test.2106742255 Jul 09 05:44:07 PM PDT 24 Jul 09 05:44:10 PM PDT 24 20083842 ps
T1048 /workspace/coverage/cover_reg_top/41.edn_intr_test.219520284 Jul 09 05:44:10 PM PDT 24 Jul 09 05:44:13 PM PDT 24 27910912 ps
T1049 /workspace/coverage/cover_reg_top/22.edn_intr_test.243313408 Jul 09 05:43:48 PM PDT 24 Jul 09 05:43:49 PM PDT 24 31669906 ps
T1050 /workspace/coverage/cover_reg_top/29.edn_intr_test.1466632500 Jul 09 05:44:02 PM PDT 24 Jul 09 05:44:06 PM PDT 24 29184113 ps
T1051 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1663544076 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:43 PM PDT 24 90378644 ps
T1052 /workspace/coverage/cover_reg_top/39.edn_intr_test.276856668 Jul 09 05:44:08 PM PDT 24 Jul 09 05:44:11 PM PDT 24 41558786 ps
T1053 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3863164077 Jul 09 05:44:02 PM PDT 24 Jul 09 05:44:05 PM PDT 24 15987944 ps
T1054 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.424318521 Jul 09 05:43:33 PM PDT 24 Jul 09 05:43:35 PM PDT 24 48925135 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.5716522 Jul 09 05:43:34 PM PDT 24 Jul 09 05:43:37 PM PDT 24 21872177 ps
T1056 /workspace/coverage/cover_reg_top/27.edn_intr_test.3597135730 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 23616228 ps
T1057 /workspace/coverage/cover_reg_top/28.edn_intr_test.558816484 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:04 PM PDT 24 11342011 ps
T1058 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2913257816 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:04 PM PDT 24 12626068 ps
T1059 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3975009605 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:09 PM PDT 24 42057811 ps
T1060 /workspace/coverage/cover_reg_top/24.edn_intr_test.507329641 Jul 09 05:43:43 PM PDT 24 Jul 09 05:43:44 PM PDT 24 87366430 ps
T1061 /workspace/coverage/cover_reg_top/36.edn_intr_test.400419025 Jul 09 05:44:16 PM PDT 24 Jul 09 05:44:20 PM PDT 24 32562823 ps
T1062 /workspace/coverage/cover_reg_top/37.edn_intr_test.2849466323 Jul 09 05:44:10 PM PDT 24 Jul 09 05:44:13 PM PDT 24 26497467 ps
T1063 /workspace/coverage/cover_reg_top/45.edn_intr_test.1401816134 Jul 09 05:43:59 PM PDT 24 Jul 09 05:44:01 PM PDT 24 22939758 ps
T1064 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1247490127 Jul 09 05:43:44 PM PDT 24 Jul 09 05:43:45 PM PDT 24 28626918 ps
T1065 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3148614245 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:08 PM PDT 24 17867177 ps
T1066 /workspace/coverage/cover_reg_top/11.edn_tl_errors.320306208 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:44 PM PDT 24 111862198 ps
T1067 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1303807194 Jul 09 05:43:31 PM PDT 24 Jul 09 05:43:33 PM PDT 24 44448448 ps
T1068 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3085201968 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:09 PM PDT 24 17732977 ps
T1069 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1983615180 Jul 09 05:43:33 PM PDT 24 Jul 09 05:43:37 PM PDT 24 162383094 ps
T1070 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3058780750 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:43 PM PDT 24 163197129 ps
T1071 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1627926294 Jul 09 05:43:44 PM PDT 24 Jul 09 05:43:46 PM PDT 24 38805958 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_intr_test.1386086045 Jul 09 05:43:33 PM PDT 24 Jul 09 05:43:35 PM PDT 24 114634817 ps
T255 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.964930413 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:42 PM PDT 24 106562098 ps
T1073 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2117297808 Jul 09 05:44:00 PM PDT 24 Jul 09 05:44:03 PM PDT 24 24259257 ps
T1074 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4020345433 Jul 09 05:43:59 PM PDT 24 Jul 09 05:44:02 PM PDT 24 27240939 ps
T1075 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.603687644 Jul 09 05:43:55 PM PDT 24 Jul 09 05:43:59 PM PDT 24 235728146 ps
T1076 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2830726534 Jul 09 05:43:36 PM PDT 24 Jul 09 05:43:40 PM PDT 24 89438564 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1336854126 Jul 09 05:44:07 PM PDT 24 Jul 09 05:44:10 PM PDT 24 80390759 ps
T1078 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2917037374 Jul 09 05:43:49 PM PDT 24 Jul 09 05:43:51 PM PDT 24 119066016 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2811870434 Jul 09 05:43:47 PM PDT 24 Jul 09 05:43:50 PM PDT 24 384584077 ps
T1080 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.540073445 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:04 PM PDT 24 60029457 ps
T1081 /workspace/coverage/cover_reg_top/13.edn_intr_test.2672507667 Jul 09 05:43:50 PM PDT 24 Jul 09 05:43:51 PM PDT 24 55308929 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2710197930 Jul 09 05:43:53 PM PDT 24 Jul 09 05:43:54 PM PDT 24 13712916 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_intr_test.1119423896 Jul 09 05:43:36 PM PDT 24 Jul 09 05:43:39 PM PDT 24 14961173 ps
T1084 /workspace/coverage/cover_reg_top/44.edn_intr_test.1789228018 Jul 09 05:44:09 PM PDT 24 Jul 09 05:44:12 PM PDT 24 41687512 ps
T1085 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4068909524 Jul 09 05:44:00 PM PDT 24 Jul 09 05:44:02 PM PDT 24 14487212 ps
T1086 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2915133284 Jul 09 05:44:05 PM PDT 24 Jul 09 05:44:09 PM PDT 24 47781318 ps
T1087 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2674966845 Jul 09 05:43:47 PM PDT 24 Jul 09 05:43:51 PM PDT 24 121607861 ps
T1088 /workspace/coverage/cover_reg_top/9.edn_intr_test.4294367306 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 14748739 ps
T1089 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1947139057 Jul 09 05:43:42 PM PDT 24 Jul 09 05:43:48 PM PDT 24 133442551 ps
T1090 /workspace/coverage/cover_reg_top/30.edn_intr_test.3019354040 Jul 09 05:44:02 PM PDT 24 Jul 09 05:44:05 PM PDT 24 21807668 ps
T1091 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2507951247 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:42 PM PDT 24 174224989 ps
T1092 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.608600665 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:52 PM PDT 24 44267087 ps
T1093 /workspace/coverage/cover_reg_top/12.edn_intr_test.2518756563 Jul 09 05:43:40 PM PDT 24 Jul 09 05:43:43 PM PDT 24 12185769 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1174987804 Jul 09 05:43:58 PM PDT 24 Jul 09 05:44:01 PM PDT 24 100899463 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.429772531 Jul 09 05:44:00 PM PDT 24 Jul 09 05:44:14 PM PDT 24 202275958 ps
T286 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.767286158 Jul 09 05:44:00 PM PDT 24 Jul 09 05:44:04 PM PDT 24 114857795 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3569125645 Jul 09 05:43:33 PM PDT 24 Jul 09 05:43:39 PM PDT 24 117678543 ps
T1097 /workspace/coverage/cover_reg_top/3.edn_intr_test.896861939 Jul 09 05:43:32 PM PDT 24 Jul 09 05:43:35 PM PDT 24 35908163 ps
T1098 /workspace/coverage/cover_reg_top/15.edn_intr_test.3313413667 Jul 09 05:44:06 PM PDT 24 Jul 09 05:44:10 PM PDT 24 22176626 ps
T1099 /workspace/coverage/cover_reg_top/10.edn_intr_test.2919286099 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:44 PM PDT 24 24618978 ps
T1100 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.324221650 Jul 09 05:43:47 PM PDT 24 Jul 09 05:43:49 PM PDT 24 64298538 ps
T1101 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3977932044 Jul 09 05:44:04 PM PDT 24 Jul 09 05:44:07 PM PDT 24 36907641 ps
T1102 /workspace/coverage/cover_reg_top/42.edn_intr_test.925827007 Jul 09 05:44:07 PM PDT 24 Jul 09 05:44:10 PM PDT 24 29340093 ps
T1103 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1387906076 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:52 PM PDT 24 33291590 ps
T1104 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2807736931 Jul 09 05:43:48 PM PDT 24 Jul 09 05:43:51 PM PDT 24 160460974 ps
T256 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1901462506 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:52 PM PDT 24 72964673 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2259435187 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:42 PM PDT 24 150677216 ps
T1106 /workspace/coverage/cover_reg_top/8.edn_intr_test.948372779 Jul 09 05:43:56 PM PDT 24 Jul 09 05:43:58 PM PDT 24 13383155 ps
T1107 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.73552270 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:09 PM PDT 24 51409415 ps
T1108 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1965061303 Jul 09 05:44:06 PM PDT 24 Jul 09 05:44:11 PM PDT 24 152133422 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3392150734 Jul 09 05:43:54 PM PDT 24 Jul 09 05:43:55 PM PDT 24 47488694 ps
T257 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.594411332 Jul 09 05:43:34 PM PDT 24 Jul 09 05:43:38 PM PDT 24 114684777 ps
T1110 /workspace/coverage/cover_reg_top/49.edn_intr_test.3141179473 Jul 09 05:44:06 PM PDT 24 Jul 09 05:44:10 PM PDT 24 21145278 ps
T1111 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3205455138 Jul 09 05:43:46 PM PDT 24 Jul 09 05:43:50 PM PDT 24 393210816 ps
T1112 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3963830693 Jul 09 05:43:47 PM PDT 24 Jul 09 05:43:50 PM PDT 24 252904799 ps
T1113 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1696339087 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:53 PM PDT 24 50706648 ps
T1114 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3870072452 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:46 PM PDT 24 306109221 ps
T1115 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3522407059 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:42 PM PDT 24 38136077 ps
T1116 /workspace/coverage/cover_reg_top/20.edn_intr_test.2940247516 Jul 09 05:44:00 PM PDT 24 Jul 09 05:44:02 PM PDT 24 15723314 ps
T1117 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3244209674 Jul 09 05:43:50 PM PDT 24 Jul 09 05:43:52 PM PDT 24 59569923 ps
T1118 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2172057515 Jul 09 05:43:48 PM PDT 24 Jul 09 05:43:55 PM PDT 24 78988306 ps
T1119 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1155384107 Jul 09 05:43:33 PM PDT 24 Jul 09 05:43:35 PM PDT 24 44065335 ps
T258 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2553175452 Jul 09 05:43:49 PM PDT 24 Jul 09 05:43:51 PM PDT 24 40387285 ps
T1120 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2035790393 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:53 PM PDT 24 113703411 ps
T1121 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1216485465 Jul 09 05:43:39 PM PDT 24 Jul 09 05:43:42 PM PDT 24 15572649 ps
T1122 /workspace/coverage/cover_reg_top/18.edn_intr_test.3059187340 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:03 PM PDT 24 21265640 ps
T1123 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3485979581 Jul 09 05:43:37 PM PDT 24 Jul 09 05:43:43 PM PDT 24 43777874 ps
T1124 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1319996174 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:04 PM PDT 24 121517668 ps
T259 /workspace/coverage/cover_reg_top/5.edn_csr_rw.952204672 Jul 09 05:43:54 PM PDT 24 Jul 09 05:43:56 PM PDT 24 58399152 ps
T1125 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1997306142 Jul 09 05:43:42 PM PDT 24 Jul 09 05:43:44 PM PDT 24 161838520 ps
T1126 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2206014085 Jul 09 05:43:59 PM PDT 24 Jul 09 05:44:02 PM PDT 24 140486042 ps
T1127 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2159613295 Jul 09 05:43:51 PM PDT 24 Jul 09 05:43:53 PM PDT 24 13375943 ps
T1128 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2113266258 Jul 09 05:43:56 PM PDT 24 Jul 09 05:43:58 PM PDT 24 44182567 ps
T1129 /workspace/coverage/cover_reg_top/23.edn_intr_test.2700146420 Jul 09 05:44:01 PM PDT 24 Jul 09 05:44:04 PM PDT 24 13437333 ps
T1130 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3295118935 Jul 09 05:43:38 PM PDT 24 Jul 09 05:43:42 PM PDT 24 25282984 ps

Test location /workspace/coverage/default/41.edn_stress_all.2041293315
Short name T1
Test name
Test status
Simulation time 471755145 ps
CPU time 5.18 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 217636 kb
Host smart-b016c82d-b5c9-45c2-a010-31f2b0d0f4d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041293315 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2041293315
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/205.edn_genbits.3885649399
Short name T15
Test name
Test status
Simulation time 46727728 ps
CPU time 1.3 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 217884 kb
Host smart-e970c429-4ff9-4c10-927e-236e433fe447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885649399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3885649399
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3958834242
Short name T40
Test name
Test status
Simulation time 352160728617 ps
CPU time 896.27 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 06:00:12 PM PDT 24
Peak memory 222168 kb
Host smart-781ba82d-bd94-4c94-88a2-5f0f9cfe6241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958834242 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3958834242
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_err.1152168382
Short name T16
Test name
Test status
Simulation time 76719100 ps
CPU time 1.22 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 225864 kb
Host smart-9f25a694-fa91-4364-b89a-947435bcb41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152168382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1152168382
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/173.edn_alert.2590303159
Short name T46
Test name
Test status
Simulation time 58559476 ps
CPU time 1.03 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 218944 kb
Host smart-f1d6a24b-9905-4858-a7f9-9086953e487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590303159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2590303159
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3868908461
Short name T19
Test name
Test status
Simulation time 372234872 ps
CPU time 5.55 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:39 PM PDT 24
Peak memory 243124 kb
Host smart-ad661f33-4b2e-4426-a735-5fe469ec725e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868908461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3868908461
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/78.edn_err.1640449013
Short name T4
Test name
Test status
Simulation time 24261109 ps
CPU time 1.18 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 218600 kb
Host smart-8f436daa-0b16-42ce-8582-354036409464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640449013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1640449013
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/11.edn_stress_all.2845029601
Short name T202
Test name
Test status
Simulation time 339122499 ps
CPU time 3.72 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 217632 kb
Host smart-f6460361-4e7c-4f05-b71f-b7d3035a7efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845029601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2845029601
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3125641315
Short name T13
Test name
Test status
Simulation time 32554423 ps
CPU time 1.36 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 220588 kb
Host smart-1ca1e6e6-74e9-42be-9096-0ae95d05a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125641315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3125641315
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.1166038182
Short name T45
Test name
Test status
Simulation time 79153555 ps
CPU time 1.13 seconds
Started Jul 09 05:46:24 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 220268 kb
Host smart-18015e0b-1897-4e10-b291-96ecb57b80ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166038182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1166038182
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/226.edn_genbits.3687806138
Short name T10
Test name
Test status
Simulation time 147626705 ps
CPU time 1.51 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 220448 kb
Host smart-10207e91-5103-46e1-aeb5-61f44f959488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687806138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3687806138
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3214087293
Short name T14
Test name
Test status
Simulation time 82812378 ps
CPU time 1.04 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:51 PM PDT 24
Peak memory 219788 kb
Host smart-e93264c7-c999-4bb5-b6b9-de9a154aa17e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214087293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3214087293
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_regwen.2926230407
Short name T29
Test name
Test status
Simulation time 21273296 ps
CPU time 1.09 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 207400 kb
Host smart-d9148a43-776a-497d-8bbe-7bab3380c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926230407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2926230407
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2442153817
Short name T284
Test name
Test status
Simulation time 271957195 ps
CPU time 1.44 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 215204 kb
Host smart-7ad57b57-2237-47a2-bae2-28b6d57163c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442153817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2442153817
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1490194576
Short name T119
Test name
Test status
Simulation time 88681390 ps
CPU time 1.06 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 217180 kb
Host smart-9fc7b05e-2eb8-4f14-b90a-04ff97ef762b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490194576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1490194576
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/155.edn_alert.663726621
Short name T49
Test name
Test status
Simulation time 37657393 ps
CPU time 1.07 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220208 kb
Host smart-00637fac-aa7a-4b68-ac78-f11b38a53c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663726621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.663726621
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2709869562
Short name T252
Test name
Test status
Simulation time 509344693 ps
CPU time 6.43 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:06 PM PDT 24
Peak memory 206916 kb
Host smart-0699f0c2-32cc-4ac0-87a4-b1c54c67959c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709869562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2709869562
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/1.edn_disable.205117351
Short name T186
Test name
Test status
Simulation time 16911228 ps
CPU time 0.84 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 216660 kb
Host smart-6bf947b1-de88-460f-98d2-b5e3db927cc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205117351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.205117351
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/183.edn_alert.2606182735
Short name T116
Test name
Test status
Simulation time 27377085 ps
CPU time 1.22 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 221204 kb
Host smart-caca2ee6-2c99-4121-b504-795bd75ed0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606182735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2606182735
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.547847758
Short name T170
Test name
Test status
Simulation time 27148588 ps
CPU time 0.85 seconds
Started Jul 09 05:44:31 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 216520 kb
Host smart-f144a60e-a503-46a6-b00d-ba1888ff834e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547847758 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.547847758
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.3740392981
Short name T638
Test name
Test status
Simulation time 44074843 ps
CPU time 0.88 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 216656 kb
Host smart-1c5647cd-4d54-4271-b517-720fba44f441
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740392981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3740392981
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2679855304
Short name T661
Test name
Test status
Simulation time 73893041 ps
CPU time 1.12 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 217312 kb
Host smart-507a9425-5a25-4152-9376-11c3513596d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679855304 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2679855304
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_intr.1291922748
Short name T37
Test name
Test status
Simulation time 35482776 ps
CPU time 0.94 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 215740 kb
Host smart-2469bc52-0d54-4777-983f-1518c55af4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291922748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1291922748
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/12.edn_genbits.1304065323
Short name T304
Test name
Test status
Simulation time 284714155 ps
CPU time 3.8 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 218896 kb
Host smart-5725cb51-1aef-4a75-a47c-92acd87d352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304065323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1304065323
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1909783697
Short name T128
Test name
Test status
Simulation time 35017596 ps
CPU time 1.14 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 219468 kb
Host smart-2f9c5b34-ee29-4188-9587-65e6a480898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909783697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1909783697
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.2506508038
Short name T141
Test name
Test status
Simulation time 310347977 ps
CPU time 1.2 seconds
Started Jul 09 05:46:22 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 221008 kb
Host smart-03b952fd-5cf8-4c81-a515-8348023c5047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506508038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2506508038
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.3196537252
Short name T552
Test name
Test status
Simulation time 40644650 ps
CPU time 1.24 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 220092 kb
Host smart-84bd70ae-f8b1-49ca-af59-7df5af9c888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196537252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3196537252
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert.2500542036
Short name T277
Test name
Test status
Simulation time 45345390 ps
CPU time 1.16 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 220248 kb
Host smart-fb14b7d0-630e-4916-acc8-cf2ae4d6fb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500542036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2500542036
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/33.edn_intr.3337131481
Short name T33
Test name
Test status
Simulation time 25411938 ps
CPU time 0.91 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 216196 kb
Host smart-54894d32-889b-43f2-942d-dfb874de0d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337131481 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3337131481
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/119.edn_genbits.1760719638
Short name T44
Test name
Test status
Simulation time 50743813 ps
CPU time 1.08 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 219324 kb
Host smart-b8866dfc-3539-45cc-b818-0e18b6cf7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760719638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1760719638
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2116052708
Short name T114
Test name
Test status
Simulation time 28733256 ps
CPU time 1.24 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:45:59 PM PDT 24
Peak memory 220000 kb
Host smart-8e5fc003-4feb-4a59-b8e7-7030bf9b038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116052708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2116052708
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.1529326680
Short name T860
Test name
Test status
Simulation time 26357679 ps
CPU time 1.19 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 220032 kb
Host smart-c669bcfe-e08e-47fb-9fe3-a05e5c33ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529326680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1529326680
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.2646634436
Short name T656
Test name
Test status
Simulation time 24250397 ps
CPU time 1.24 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 220684 kb
Host smart-08809f0e-06a4-4acf-9245-59db5d6dd4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646634436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2646634436
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.457127485
Short name T915
Test name
Test status
Simulation time 82494574 ps
CPU time 1.13 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:25 PM PDT 24
Peak memory 220280 kb
Host smart-c594e910-a847-4539-b540-d9363ceb6443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457127485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.457127485
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.388343090
Short name T648
Test name
Test status
Simulation time 11288398 ps
CPU time 0.85 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 215688 kb
Host smart-0601ed81-d4a0-41be-ba1e-98dd01d5d472
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388343090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.388343090
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/0.edn_intr.2068991148
Short name T104
Test name
Test status
Simulation time 30535767 ps
CPU time 0.84 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 215872 kb
Host smart-489aff1a-691e-4dcc-a645-54b837e65a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068991148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2068991148
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.1000242732
Short name T205
Test name
Test status
Simulation time 13941050 ps
CPU time 0.92 seconds
Started Jul 09 05:44:38 PM PDT 24
Finished Jul 09 05:44:39 PM PDT 24
Peak memory 216752 kb
Host smart-e4146e68-3566-40c7-8973-668a42f2fd27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000242732 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1000242732
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.271060894
Short name T617
Test name
Test status
Simulation time 22519223 ps
CPU time 1 seconds
Started Jul 09 05:44:48 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 229828 kb
Host smart-88810e95-132a-464d-949f-ee29cf87a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271060894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.271060894
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/115.edn_alert.1820033751
Short name T77
Test name
Test status
Simulation time 118882775 ps
CPU time 1.17 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 221196 kb
Host smart-6e42d145-c1e9-40ae-9c97-852667c0192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820033751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1820033751
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.3212452917
Short name T680
Test name
Test status
Simulation time 23864041 ps
CPU time 1.16 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 221216 kb
Host smart-46168fb2-0ac0-473d-9528-5bca1020eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212452917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3212452917
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.1519775625
Short name T218
Test name
Test status
Simulation time 12599381 ps
CPU time 0.93 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 216828 kb
Host smart-fa15095e-24d1-46eb-b489-ed8d11db7ac6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519775625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1519775625
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/166.edn_alert.3713568373
Short name T179
Test name
Test status
Simulation time 26994105 ps
CPU time 1.19 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 215988 kb
Host smart-bc149573-4ad1-40a0-a6d3-9a134afc1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713568373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3713568373
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2364705358
Short name T124
Test name
Test status
Simulation time 32367737 ps
CPU time 1.16 seconds
Started Jul 09 05:44:51 PM PDT 24
Finished Jul 09 05:44:53 PM PDT 24
Peak memory 217160 kb
Host smart-255fe483-07b6-488f-b94f-f99f3292b14e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364705358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2364705358
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2019190054
Short name T151
Test name
Test status
Simulation time 80018863 ps
CPU time 1.1 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 217172 kb
Host smart-e3480551-1a49-40bf-a493-d23aa608db41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019190054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2019190054
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable.986033511
Short name T161
Test name
Test status
Simulation time 12788446 ps
CPU time 0.91 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 216748 kb
Host smart-995a5391-d292-45cd-8c20-2b51e30b7d9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986033511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.986033511
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.4113038157
Short name T181
Test name
Test status
Simulation time 20312359 ps
CPU time 1.16 seconds
Started Jul 09 05:45:40 PM PDT 24
Finished Jul 09 05:45:42 PM PDT 24
Peak memory 224384 kb
Host smart-4e0cef17-aa06-432d-9ef8-a842684cf54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113038157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4113038157
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/33.edn_disable.217433581
Short name T177
Test name
Test status
Simulation time 17891651 ps
CPU time 0.8 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 216488 kb
Host smart-a697041a-4f37-4e91-8258-05b7a27ef034
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217433581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.217433581
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2774806292
Short name T143
Test name
Test status
Simulation time 96470750 ps
CPU time 1.47 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:15 PM PDT 24
Peak memory 217252 kb
Host smart-0934e2bf-d97d-4c07-abd8-29c6e7d0a0c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774806292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2774806292
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_disable.847236860
Short name T198
Test name
Test status
Simulation time 106938063 ps
CPU time 0.86 seconds
Started Jul 09 05:45:36 PM PDT 24
Finished Jul 09 05:45:37 PM PDT 24
Peak memory 216556 kb
Host smart-0e2e89b9-b105-44f1-8b4c-42fcf63fba1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847236860 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.847236860
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/50.edn_err.3164128823
Short name T192
Test name
Test status
Simulation time 23847590 ps
CPU time 0.93 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 218812 kb
Host smart-f13591c0-52b3-4886-9012-f03261018bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164128823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3164128823
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/16.edn_alert_test.1311567107
Short name T349
Test name
Test status
Simulation time 19682098 ps
CPU time 0.98 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 207064 kb
Host smart-8e15f53c-1f1b-4ff2-a6eb-9f3f7e9f95c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311567107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1311567107
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/289.edn_genbits.2815818440
Short name T310
Test name
Test status
Simulation time 29495747 ps
CPU time 1.22 seconds
Started Jul 09 05:46:48 PM PDT 24
Finished Jul 09 05:46:50 PM PDT 24
Peak memory 218692 kb
Host smart-14678ad3-666f-4f7e-97e7-9794aaed99b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815818440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2815818440
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1614719966
Short name T96
Test name
Test status
Simulation time 62633164 ps
CPU time 1.66 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 219124 kb
Host smart-357175f6-268e-4ab2-a05a-c083ed58ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614719966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1614719966
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2615778564
Short name T289
Test name
Test status
Simulation time 79461551 ps
CPU time 1.19 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 221136 kb
Host smart-9c0f78d9-a271-4a70-a8ed-bbbd58e82362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615778564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2615778564
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/40.edn_intr.4174327808
Short name T38
Test name
Test status
Simulation time 23401815 ps
CPU time 1.02 seconds
Started Jul 09 05:45:41 PM PDT 24
Finished Jul 09 05:45:43 PM PDT 24
Peak memory 216068 kb
Host smart-127f18a1-5a4c-4a45-b583-a613d6f91214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174327808 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4174327808
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.232225544
Short name T263
Test name
Test status
Simulation time 24563764 ps
CPU time 0.91 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:36 PM PDT 24
Peak memory 206936 kb
Host smart-60479459-63eb-4553-a261-cbe7e81b01f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232225544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.232225544
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/11.edn_err.3216928118
Short name T209
Test name
Test status
Simulation time 35013107 ps
CPU time 0.91 seconds
Started Jul 09 05:44:53 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 219824 kb
Host smart-e4f76031-12c4-4cc3-87da-d70e87fc79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216928118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3216928118
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.1348009330
Short name T535
Test name
Test status
Simulation time 22526365 ps
CPU time 0.95 seconds
Started Jul 09 05:44:31 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 207304 kb
Host smart-eb468b6f-9d20-4564-9148-1469de00848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348009330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1348009330
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_stress_all.445680659
Short name T557
Test name
Test status
Simulation time 953777669 ps
CPU time 4.64 seconds
Started Jul 09 05:44:51 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 217656 kb
Host smart-9b5d2ae5-aaeb-4061-a0c2-dec6e3ed5947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445680659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.445680659
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/104.edn_genbits.3716811775
Short name T313
Test name
Test status
Simulation time 489130436 ps
CPU time 3.09 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 217724 kb
Host smart-5064363a-a07a-419a-97f8-ec81abf39534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716811775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3716811775
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.4140235448
Short name T316
Test name
Test status
Simulation time 29712410 ps
CPU time 1.3 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 219148 kb
Host smart-77acf3cb-2a09-4ea9-aafe-a13125b44e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140235448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4140235448
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2388452581
Short name T879
Test name
Test status
Simulation time 24370694 ps
CPU time 1.08 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220220 kb
Host smart-a7d1535d-b4e3-4b0b-b109-89bfcc723588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388452581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2388452581
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3547219957
Short name T319
Test name
Test status
Simulation time 25999571487 ps
CPU time 615.21 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:55:11 PM PDT 24
Peak memory 224136 kb
Host smart-7a0073b9-10f2-48cb-bef4-1e51c9f2f8fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547219957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3547219957
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.edn_genbits.1722457604
Short name T323
Test name
Test status
Simulation time 87835251 ps
CPU time 1.24 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 217544 kb
Host smart-c5a6d9db-836d-4f20-820a-46a4a74b4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722457604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1722457604
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3104902134
Short name T327
Test name
Test status
Simulation time 49224918 ps
CPU time 1.17 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 220324 kb
Host smart-4169a5a2-ff66-4dfe-b629-fa265f4b0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104902134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3104902134
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3933778226
Short name T25
Test name
Test status
Simulation time 67013077 ps
CPU time 1.37 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 219004 kb
Host smart-2b76042a-31ad-4be3-b36d-3beb9d4f7654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933778226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3933778226
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.259818849
Short name T332
Test name
Test status
Simulation time 83780735 ps
CPU time 1.08 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 217592 kb
Host smart-5ac10e92-a424-4915-8ca7-78fd43ac963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259818849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.259818849
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1819388922
Short name T101
Test name
Test status
Simulation time 55463911 ps
CPU time 1.12 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 219656 kb
Host smart-e8f3545d-3d6a-453c-9ad5-78f1307e1a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819388922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1819388922
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3930150265
Short name T325
Test name
Test status
Simulation time 29928870 ps
CPU time 1.52 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 218884 kb
Host smart-1f8d5966-f1cc-4ca3-bf44-3adb409fe911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930150265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3930150265
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_genbits.2691103681
Short name T308
Test name
Test status
Simulation time 59802782 ps
CPU time 1.47 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 218992 kb
Host smart-d94f3fd9-444c-4c78-b2e4-827b5f399646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691103681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2691103681
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.854936994
Short name T39
Test name
Test status
Simulation time 20461261 ps
CPU time 1.13 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 216136 kb
Host smart-f9210e3e-5de1-44c4-a1fb-0ba65b091ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854936994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.854936994
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.172953598
Short name T1018
Test name
Test status
Simulation time 39444173 ps
CPU time 1.43 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 206952 kb
Host smart-7cebe3f1-6d2d-404d-b845-46b27fb69603
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172953598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.172953598
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2640359120
Short name T1008
Test name
Test status
Simulation time 61690073 ps
CPU time 2.02 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 206920 kb
Host smart-a150fd4c-35de-41d6-aa72-690181bddb1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640359120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2640359120
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.424318521
Short name T1054
Test name
Test status
Simulation time 48925135 ps
CPU time 0.89 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 206888 kb
Host smart-a5b424dd-9d37-45ca-a4f0-b34988895c84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424318521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.424318521
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2830726534
Short name T1076
Test name
Test status
Simulation time 89438564 ps
CPU time 1.61 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 215208 kb
Host smart-209fbdd5-709d-45d9-88f1-46d4c8fed38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830726534 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2830726534
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1119423896
Short name T1083
Test name
Test status
Simulation time 14961173 ps
CPU time 0.86 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 206884 kb
Host smart-990ce8aa-8b7b-4f37-ae71-472087b6731f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119423896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1119423896
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2113266258
Short name T1128
Test name
Test status
Simulation time 44182567 ps
CPU time 1.05 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 206888 kb
Host smart-09ab32a2-416a-4a5a-a3b2-58568b744077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113266258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2113266258
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3870072452
Short name T1114
Test name
Test status
Simulation time 306109221 ps
CPU time 5.2 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 219508 kb
Host smart-8de77fe0-1162-469d-aa3a-028f7d051b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870072452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3870072452
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.158333070
Short name T273
Test name
Test status
Simulation time 66337018 ps
CPU time 1.87 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 206940 kb
Host smart-bbd8fd3c-5e1c-4d09-b4e0-0de33f206da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158333070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.158333070
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1840000897
Short name T1028
Test name
Test status
Simulation time 49189507 ps
CPU time 1.27 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 206932 kb
Host smart-1f2ed09c-3174-4101-be93-7b41664c1337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840000897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1840000897
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3522407059
Short name T1115
Test name
Test status
Simulation time 38136077 ps
CPU time 2.03 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 206988 kb
Host smart-80cfcceb-7d81-486b-88a2-dd92dbead04a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522407059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3522407059
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1303807194
Short name T1067
Test name
Test status
Simulation time 44448448 ps
CPU time 0.84 seconds
Started Jul 09 05:43:31 PM PDT 24
Finished Jul 09 05:43:33 PM PDT 24
Peak memory 206896 kb
Host smart-34e578fb-f2df-478d-b069-8e7e7e85aeac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303807194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1303807194
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3000137928
Short name T1045
Test name
Test status
Simulation time 28543204 ps
CPU time 1.86 seconds
Started Jul 09 05:43:46 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 215176 kb
Host smart-77cdfe10-57f1-4755-816a-0f81004728a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000137928 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3000137928
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1155384107
Short name T1119
Test name
Test status
Simulation time 44065335 ps
CPU time 0.88 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 206912 kb
Host smart-66ba742c-ab96-49b2-a5a1-7970efe2c607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155384107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1155384107
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2120183869
Short name T995
Test name
Test status
Simulation time 26703858 ps
CPU time 0.85 seconds
Started Jul 09 05:43:40 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206852 kb
Host smart-ca5ee816-e90a-420d-bcf6-13f058f9c775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120183869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2120183869
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2805478664
Short name T251
Test name
Test status
Simulation time 19759840 ps
CPU time 1.18 seconds
Started Jul 09 05:43:58 PM PDT 24
Finished Jul 09 05:44:00 PM PDT 24
Peak memory 207000 kb
Host smart-97aedb52-94d3-405a-84cd-3f8b7cd10903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805478664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2805478664
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.847271015
Short name T1005
Test name
Test status
Simulation time 259341312 ps
CPU time 4.41 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:40 PM PDT 24
Peak memory 215184 kb
Host smart-254697ed-e0a0-4ad9-af22-8e331306d787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847271015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.847271015
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2507951247
Short name T1091
Test name
Test status
Simulation time 174224989 ps
CPU time 2.43 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 207428 kb
Host smart-9ccb7a47-15a6-4d2d-bdef-dd44701fb195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507951247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2507951247
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1696339087
Short name T1113
Test name
Test status
Simulation time 50706648 ps
CPU time 1.28 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 217992 kb
Host smart-64532808-784a-4a16-8656-5d207e901e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696339087 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1696339087
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1247490127
Short name T1064
Test name
Test status
Simulation time 28626918 ps
CPU time 0.78 seconds
Started Jul 09 05:43:44 PM PDT 24
Finished Jul 09 05:43:45 PM PDT 24
Peak memory 206740 kb
Host smart-3d43b116-cf5e-4975-9764-c5b011744b8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247490127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1247490127
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2919286099
Short name T1099
Test name
Test status
Simulation time 24618978 ps
CPU time 0.84 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 206880 kb
Host smart-18b77bea-2166-42de-a207-fd724925dfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919286099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2919286099
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.73552270
Short name T1107
Test name
Test status
Simulation time 51409415 ps
CPU time 1.07 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 206952 kb
Host smart-82f1738d-af4c-4cd2-85c2-b0c0f1d1ea03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73552270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_out
standing.73552270
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3205455138
Short name T1111
Test name
Test status
Simulation time 393210816 ps
CPU time 3.11 seconds
Started Jul 09 05:43:46 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 215140 kb
Host smart-4dacc336-0f06-4442-b312-404fe5563e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205455138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3205455138
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3067141657
Short name T288
Test name
Test status
Simulation time 41068815 ps
CPU time 1.59 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:05 PM PDT 24
Peak memory 215468 kb
Host smart-315f895c-6cac-49ff-b25b-cbfc323004b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067141657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3067141657
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2681254597
Short name T1016
Test name
Test status
Simulation time 63675443 ps
CPU time 1.24 seconds
Started Jul 09 05:44:03 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 215192 kb
Host smart-c9beb5a0-f2c7-47c4-b3e2-d41da9b80feb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681254597 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2681254597
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1901462506
Short name T256
Test name
Test status
Simulation time 72964673 ps
CPU time 0.85 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:52 PM PDT 24
Peak memory 206760 kb
Host smart-325d14ba-8120-4de1-a918-9ae89be274c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901462506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1901462506
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3310840380
Short name T1043
Test name
Test status
Simulation time 76873228 ps
CPU time 0.77 seconds
Started Jul 09 05:43:41 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206700 kb
Host smart-cd85a9c6-ef98-40cc-a89b-ac18f172783a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310840380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3310840380
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2035790393
Short name T1120
Test name
Test status
Simulation time 113703411 ps
CPU time 1.52 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206892 kb
Host smart-de24834e-4796-4855-b0ce-1286bcc49dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035790393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2035790393
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.320306208
Short name T1066
Test name
Test status
Simulation time 111862198 ps
CPU time 4.04 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 215288 kb
Host smart-357c066a-8bb4-4d99-9883-bb73383aa54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320306208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.320306208
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2674966845
Short name T1087
Test name
Test status
Simulation time 121607861 ps
CPU time 2.94 seconds
Started Jul 09 05:43:47 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 207012 kb
Host smart-be006531-6930-4dbd-9675-ebd3af30edca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674966845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2674966845
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4068909524
Short name T1085
Test name
Test status
Simulation time 14487212 ps
CPU time 1.02 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:02 PM PDT 24
Peak memory 215176 kb
Host smart-30e8d745-ab91-467b-a299-009665ee3364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068909524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4068909524
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3526739795
Short name T253
Test name
Test status
Simulation time 35942240 ps
CPU time 0.82 seconds
Started Jul 09 05:43:41 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206932 kb
Host smart-00f3aa29-1ecd-44cf-8e23-0cea7b70b8f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526739795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3526739795
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2518756563
Short name T1093
Test name
Test status
Simulation time 12185769 ps
CPU time 0.85 seconds
Started Jul 09 05:43:40 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206868 kb
Host smart-de9dbc21-8afc-43fb-a8f9-68f9c6226a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518756563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2518756563
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2206014085
Short name T1126
Test name
Test status
Simulation time 140486042 ps
CPU time 1.41 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:02 PM PDT 24
Peak memory 206984 kb
Host smart-3386ecdf-12f3-4b22-a268-1c1100b3f152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206014085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2206014085
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3485979581
Short name T1123
Test name
Test status
Simulation time 43777874 ps
CPU time 2.45 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 215268 kb
Host smart-25a0dd8a-bb28-4f2a-8c6c-9c85dd396dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485979581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3485979581
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2795129998
Short name T283
Test name
Test status
Simulation time 174463178 ps
CPU time 2.45 seconds
Started Jul 09 05:43:57 PM PDT 24
Finished Jul 09 05:44:01 PM PDT 24
Peak memory 215140 kb
Host smart-0dfaa59f-c29c-4a0e-916c-28b786ec1403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795129998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2795129998
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3148614245
Short name T1065
Test name
Test status
Simulation time 17867177 ps
CPU time 1.16 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:08 PM PDT 24
Peak memory 218480 kb
Host smart-c87467c8-75a5-44b0-b73a-9aede625e7a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148614245 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3148614245
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4125136194
Short name T1027
Test name
Test status
Simulation time 12073671 ps
CPU time 0.84 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:56 PM PDT 24
Peak memory 206868 kb
Host smart-d9dead5f-1897-4f86-babd-ffa02ec1b2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125136194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4125136194
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2672507667
Short name T1081
Test name
Test status
Simulation time 55308929 ps
CPU time 0.9 seconds
Started Jul 09 05:43:50 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 206888 kb
Host smart-f7ee9e70-efa0-473e-8e3a-1e381bb93d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672507667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2672507667
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.245393468
Short name T1026
Test name
Test status
Simulation time 207513818 ps
CPU time 1.4 seconds
Started Jul 09 05:43:49 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 206932 kb
Host smart-518ae560-41b3-4d3c-aa68-2af1266eb131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245393468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.245393468
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2020438115
Short name T1010
Test name
Test status
Simulation time 281266726 ps
CPU time 4.77 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:13 PM PDT 24
Peak memory 215268 kb
Host smart-5909b2d7-2bb8-44b5-998d-9662d6b55ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020438115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2020438115
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1965061303
Short name T1108
Test name
Test status
Simulation time 152133422 ps
CPU time 2.44 seconds
Started Jul 09 05:44:06 PM PDT 24
Finished Jul 09 05:44:11 PM PDT 24
Peak memory 215132 kb
Host smart-862a7427-dbbe-418a-a9f2-9412e93ddde7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965061303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1965061303
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1336854126
Short name T1077
Test name
Test status
Simulation time 80390759 ps
CPU time 1 seconds
Started Jul 09 05:44:07 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 215264 kb
Host smart-00d1237d-49bf-4d52-9b12-939c0578ae5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336854126 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1336854126
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2159613295
Short name T1127
Test name
Test status
Simulation time 13375943 ps
CPU time 0.91 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206924 kb
Host smart-3f14a9ff-fccf-491c-b17c-5e7d9b4f01a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159613295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2159613295
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.530992590
Short name T1021
Test name
Test status
Simulation time 18077979 ps
CPU time 1.01 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206880 kb
Host smart-336dd264-441e-4988-9d02-66c31188e177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530992590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.530992590
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3026848280
Short name T1042
Test name
Test status
Simulation time 23509286 ps
CPU time 1.09 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206920 kb
Host smart-ac9640f3-c6dd-441a-827a-852276d44aa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026848280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3026848280
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1406498382
Short name T1012
Test name
Test status
Simulation time 241138082 ps
CPU time 2.82 seconds
Started Jul 09 05:43:54 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 215196 kb
Host smart-4b1b4242-5018-4879-8678-64fb0ca3604d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406498382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1406498382
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.756052385
Short name T281
Test name
Test status
Simulation time 161463463 ps
CPU time 2.38 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:44:00 PM PDT 24
Peak memory 206956 kb
Host smart-d19c7d02-695c-4bc4-9870-005a6d40eb89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756052385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.756052385
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4020345433
Short name T1074
Test name
Test status
Simulation time 27240939 ps
CPU time 1.67 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:02 PM PDT 24
Peak memory 215196 kb
Host smart-cb6e2b06-65a4-4718-a3f5-f41cbe52cf3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020345433 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4020345433
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1897417195
Short name T254
Test name
Test status
Simulation time 23855228 ps
CPU time 0.88 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206912 kb
Host smart-b6f3cb9e-e5c8-408a-b38d-7a6e98a59e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897417195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1897417195
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3313413667
Short name T1098
Test name
Test status
Simulation time 22176626 ps
CPU time 0.95 seconds
Started Jul 09 05:44:06 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 206804 kb
Host smart-2a167289-4977-4c49-88f6-bcc188a73677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313413667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3313413667
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.117675456
Short name T266
Test name
Test status
Simulation time 135981416 ps
CPU time 1.07 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 206920 kb
Host smart-fa2d862f-0cd5-435b-b6fa-4bb66393dcce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117675456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.117675456
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1638659161
Short name T1015
Test name
Test status
Simulation time 50960515 ps
CPU time 1.89 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 215124 kb
Host smart-2a5fcffa-87a2-4dd6-bad9-2aa437b807b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638659161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1638659161
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.767286158
Short name T286
Test name
Test status
Simulation time 114857795 ps
CPU time 2.88 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206988 kb
Host smart-5289a1b8-6bd0-40d4-aab1-cc37d621be8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767286158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.767286158
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2915133284
Short name T1086
Test name
Test status
Simulation time 47781318 ps
CPU time 1.51 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 215268 kb
Host smart-32802670-eaf7-4b75-8d60-a2bc434568e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915133284 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2915133284
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2553175452
Short name T258
Test name
Test status
Simulation time 40387285 ps
CPU time 0.85 seconds
Started Jul 09 05:43:49 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 206948 kb
Host smart-aec31249-6d80-4995-99cc-6de8658b6c32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553175452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2553175452
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3845996925
Short name T1029
Test name
Test status
Simulation time 21134667 ps
CPU time 0.82 seconds
Started Jul 09 05:43:52 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 206860 kb
Host smart-16b82140-4fbd-4bf1-9300-d5a76a977905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845996925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3845996925
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3975009605
Short name T1059
Test name
Test status
Simulation time 42057811 ps
CPU time 1.32 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 206944 kb
Host smart-e1284e9c-398b-47a4-a5bf-0dc161083f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975009605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3975009605
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4187365852
Short name T1002
Test name
Test status
Simulation time 127211597 ps
CPU time 2.75 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 215208 kb
Host smart-cd619e75-0d19-41af-a551-f64b5a747fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187365852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4187365852
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.69622272
Short name T282
Test name
Test status
Simulation time 124656970 ps
CPU time 1.77 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 206924 kb
Host smart-7c1bf041-781b-4005-aa13-3354d026a06f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69622272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.69622272
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3536447783
Short name T1001
Test name
Test status
Simulation time 39290281 ps
CPU time 1.57 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:05 PM PDT 24
Peak memory 215116 kb
Host smart-57ac94ab-98ab-4f9c-9560-28f71b83d64a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536447783 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3536447783
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2913257816
Short name T1058
Test name
Test status
Simulation time 12626068 ps
CPU time 0.87 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206856 kb
Host smart-819b3cbc-3c89-4ca5-ad96-4417c23a450c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913257816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2913257816
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1190691531
Short name T1022
Test name
Test status
Simulation time 12561504 ps
CPU time 0.9 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 206832 kb
Host smart-36384c0d-1d6c-4bb5-8368-a1e85d2f0caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190691531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1190691531
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1149315329
Short name T262
Test name
Test status
Simulation time 55175352 ps
CPU time 1.12 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206976 kb
Host smart-96e39430-bb81-4709-bde1-520073404240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149315329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1149315329
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1612318559
Short name T1035
Test name
Test status
Simulation time 39293229 ps
CPU time 1.65 seconds
Started Jul 09 05:44:03 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 215352 kb
Host smart-743eb6c4-0278-4821-9dad-c3d2f26e4ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612318559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1612318559
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.429772531
Short name T1095
Test name
Test status
Simulation time 202275958 ps
CPU time 2.39 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:14 PM PDT 24
Peak memory 206936 kb
Host smart-6d878bf2-7443-4259-9e9a-eb881c106477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429772531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.429772531
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.324221650
Short name T1100
Test name
Test status
Simulation time 64298538 ps
CPU time 1.24 seconds
Started Jul 09 05:43:47 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 215136 kb
Host smart-1865eb32-9143-4927-8760-6c7a397decd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324221650 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.324221650
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.129654951
Short name T1030
Test name
Test status
Simulation time 40725320 ps
CPU time 0.82 seconds
Started Jul 09 05:43:57 PM PDT 24
Finished Jul 09 05:44:00 PM PDT 24
Peak memory 206764 kb
Host smart-bcb55a8c-05aa-4495-9396-fa115cbfd9be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129654951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.129654951
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3059187340
Short name T1122
Test name
Test status
Simulation time 21265640 ps
CPU time 0.85 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:03 PM PDT 24
Peak memory 206684 kb
Host smart-55ae63a1-6f75-4ce4-9891-fae322fc121f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059187340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3059187340
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1319996174
Short name T1124
Test name
Test status
Simulation time 121517668 ps
CPU time 1.45 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 207084 kb
Host smart-e95c437a-be41-46fd-aef5-ee2b93354249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319996174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1319996174
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3882431642
Short name T1013
Test name
Test status
Simulation time 460637046 ps
CPU time 2.78 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:06 PM PDT 24
Peak memory 215212 kb
Host smart-c371686a-d5c6-4fdb-b392-5b01292fc111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882431642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3882431642
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3085201968
Short name T1068
Test name
Test status
Simulation time 17732977 ps
CPU time 1.01 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 207008 kb
Host smart-7f7be74f-dc07-4ecf-884b-4a3925d815bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085201968 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3085201968
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1198532383
Short name T1039
Test name
Test status
Simulation time 11501572 ps
CPU time 0.87 seconds
Started Jul 09 05:44:09 PM PDT 24
Finished Jul 09 05:44:12 PM PDT 24
Peak memory 206924 kb
Host smart-84eaad66-176e-4b65-afda-e56e8ab02c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198532383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1198532383
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1458416528
Short name T997
Test name
Test status
Simulation time 29377951 ps
CPU time 0.94 seconds
Started Jul 09 05:43:46 PM PDT 24
Finished Jul 09 05:43:48 PM PDT 24
Peak memory 206876 kb
Host smart-c9c2a1de-9b9c-484f-bc39-1ce3b31b23d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458416528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1458416528
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1997306142
Short name T1125
Test name
Test status
Simulation time 161838520 ps
CPU time 1.11 seconds
Started Jul 09 05:43:42 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 206948 kb
Host smart-80296b27-f72b-4a69-bba8-c4dfc9b86bde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997306142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1997306142
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1174987804
Short name T1094
Test name
Test status
Simulation time 100899463 ps
CPU time 1.91 seconds
Started Jul 09 05:43:58 PM PDT 24
Finished Jul 09 05:44:01 PM PDT 24
Peak memory 215272 kb
Host smart-106023f4-6d4e-4a25-b97e-9706efc18fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174987804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1174987804
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1505522274
Short name T272
Test name
Test status
Simulation time 200302765 ps
CPU time 2.7 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 215060 kb
Host smart-6ea7d341-9a22-40b3-a6fc-2004d8e60829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505522274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1505522274
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.608600665
Short name T1092
Test name
Test status
Simulation time 44267087 ps
CPU time 1.15 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:52 PM PDT 24
Peak memory 206940 kb
Host smart-12e28eac-1a93-4060-a271-0879301ed09d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608600665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.608600665
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2811870434
Short name T1079
Test name
Test status
Simulation time 384584077 ps
CPU time 2.12 seconds
Started Jul 09 05:43:47 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 206988 kb
Host smart-b375f55c-27d3-4cc7-a7b6-97fc767c27c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811870434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2811870434
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3863164077
Short name T1053
Test name
Test status
Simulation time 15987944 ps
CPU time 0.9 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:05 PM PDT 24
Peak memory 206932 kb
Host smart-c25c09c1-704f-4320-9569-5b1c2ec82618
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863164077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3863164077
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2252651847
Short name T1038
Test name
Test status
Simulation time 24689413 ps
CPU time 1.56 seconds
Started Jul 09 05:44:14 PM PDT 24
Finished Jul 09 05:44:18 PM PDT 24
Peak memory 215184 kb
Host smart-36eb9975-1be6-4f20-ace8-f256d4b6bd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252651847 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2252651847
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3551061105
Short name T996
Test name
Test status
Simulation time 20478853 ps
CPU time 0.83 seconds
Started Jul 09 05:43:57 PM PDT 24
Finished Jul 09 05:43:59 PM PDT 24
Peak memory 206920 kb
Host smart-5dc74cd7-b051-4f57-a2e9-9bdc5a286b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551061105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3551061105
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1386086045
Short name T1072
Test name
Test status
Simulation time 114634817 ps
CPU time 0.82 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 206708 kb
Host smart-9accf749-9bc4-41a9-9aff-9decb0ff5c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386086045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1386086045
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.38983989
Short name T264
Test name
Test status
Simulation time 14213298 ps
CPU time 1.07 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206808 kb
Host smart-f49029bd-e4c0-4e75-bf3b-02284a801383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38983989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outs
tanding.38983989
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4080206426
Short name T1046
Test name
Test status
Simulation time 169261800 ps
CPU time 2.93 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 223424 kb
Host smart-a391639c-632c-4b98-aa3a-337ca3f71d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080206426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4080206426
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1273763996
Short name T285
Test name
Test status
Simulation time 88934222 ps
CPU time 2.44 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206940 kb
Host smart-16ccd5a2-b3eb-4e57-b76b-ca7ebbbbe98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273763996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1273763996
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2940247516
Short name T1116
Test name
Test status
Simulation time 15723314 ps
CPU time 0.91 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:02 PM PDT 24
Peak memory 206884 kb
Host smart-c887107f-de87-48cb-aa06-73e7b892613f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940247516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2940247516
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.346417086
Short name T1009
Test name
Test status
Simulation time 22413845 ps
CPU time 1 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 206884 kb
Host smart-d6080d8b-dd82-4431-9555-8d3fe780469a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346417086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.346417086
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.243313408
Short name T1049
Test name
Test status
Simulation time 31669906 ps
CPU time 0.77 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:49 PM PDT 24
Peak memory 206704 kb
Host smart-c0bcbae7-f16f-437e-8502-9c2583607f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243313408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.243313408
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2700146420
Short name T1129
Test name
Test status
Simulation time 13437333 ps
CPU time 0.85 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206760 kb
Host smart-5c2b75c7-b92c-470f-a0c0-dae038535d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700146420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2700146420
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.507329641
Short name T1060
Test name
Test status
Simulation time 87366430 ps
CPU time 0.78 seconds
Started Jul 09 05:43:43 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 206708 kb
Host smart-b0a380af-c473-4583-99af-63a19c504e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507329641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.507329641
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3078613492
Short name T1033
Test name
Test status
Simulation time 11156790 ps
CPU time 0.84 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:01 PM PDT 24
Peak memory 206848 kb
Host smart-8c796759-91df-48d7-aca4-cf8c7c4d8a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078613492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3078613492
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3668226376
Short name T1007
Test name
Test status
Simulation time 35274452 ps
CPU time 0.81 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206664 kb
Host smart-aa6c5cb5-eab6-4667-a79a-8752d769c1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668226376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3668226376
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3597135730
Short name T1056
Test name
Test status
Simulation time 23616228 ps
CPU time 0.85 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206856 kb
Host smart-6f38a929-6299-47ac-8a66-58bb2025c53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597135730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3597135730
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.558816484
Short name T1057
Test name
Test status
Simulation time 11342011 ps
CPU time 0.9 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206868 kb
Host smart-ad236d5e-5e48-4dba-8ebd-b1fca1a17009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558816484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.558816484
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1466632500
Short name T1050
Test name
Test status
Simulation time 29184113 ps
CPU time 0.78 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:06 PM PDT 24
Peak memory 206696 kb
Host smart-4be3931b-1f04-4bd8-9827-966908883e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466632500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1466632500
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.594411332
Short name T257
Test name
Test status
Simulation time 114684777 ps
CPU time 1.5 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 206952 kb
Host smart-15f48d15-1772-488e-bb66-a8bba5419905
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594411332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.594411332
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1549179053
Short name T1023
Test name
Test status
Simulation time 112390255 ps
CPU time 3.22 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 206976 kb
Host smart-e0b18644-33c2-452c-aee2-3442c3141ae8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549179053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1549179053
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3392150734
Short name T1109
Test name
Test status
Simulation time 47488694 ps
CPU time 0.87 seconds
Started Jul 09 05:43:54 PM PDT 24
Finished Jul 09 05:43:55 PM PDT 24
Peak memory 206908 kb
Host smart-0f84d6b9-d86a-47fd-9304-e1cf3fc099aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392150734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3392150734
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2917037374
Short name T1078
Test name
Test status
Simulation time 119066016 ps
CPU time 1.31 seconds
Started Jul 09 05:43:49 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 215164 kb
Host smart-8b3f8808-2a14-4687-9fa6-6c4554ed1206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917037374 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2917037374
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3295118935
Short name T1130
Test name
Test status
Simulation time 25282984 ps
CPU time 0.87 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 206856 kb
Host smart-7874d631-b445-42a6-85d9-72aa3396c275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295118935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3295118935
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.896861939
Short name T1097
Test name
Test status
Simulation time 35908163 ps
CPU time 0.84 seconds
Started Jul 09 05:43:32 PM PDT 24
Finished Jul 09 05:43:35 PM PDT 24
Peak memory 206808 kb
Host smart-35612010-b867-455a-8d52-889250c1795c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896861939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.896861939
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3528922035
Short name T267
Test name
Test status
Simulation time 24349689 ps
CPU time 1.2 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 207004 kb
Host smart-a651b6ef-278c-4cc0-b2c9-696a65cf3254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528922035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3528922035
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3569125645
Short name T1096
Test name
Test status
Simulation time 117678543 ps
CPU time 4.01 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 215204 kb
Host smart-a42cf754-b402-4983-9b17-380b054cec62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569125645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3569125645
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3058780750
Short name T1070
Test name
Test status
Simulation time 163197129 ps
CPU time 2.23 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 206916 kb
Host smart-592ce714-74ec-4b17-bc24-b96364d20a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058780750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3058780750
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3019354040
Short name T1090
Test name
Test status
Simulation time 21807668 ps
CPU time 0.82 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:05 PM PDT 24
Peak memory 206876 kb
Host smart-8c61aaaf-ee21-4c01-ad71-100d875f74a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019354040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3019354040
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2494301541
Short name T1036
Test name
Test status
Simulation time 51680900 ps
CPU time 0.92 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206868 kb
Host smart-2f60d180-8d69-435b-8dce-75404f9c4422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494301541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2494301541
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2353673520
Short name T1006
Test name
Test status
Simulation time 40507766 ps
CPU time 0.87 seconds
Started Jul 09 05:44:15 PM PDT 24
Finished Jul 09 05:44:18 PM PDT 24
Peak memory 206760 kb
Host smart-541f7d0e-d808-404c-8afa-c59ec4cf9261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353673520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2353673520
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2266456937
Short name T1017
Test name
Test status
Simulation time 26494465 ps
CPU time 0.9 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:53 PM PDT 24
Peak memory 206884 kb
Host smart-d162d5b2-cf67-4b42-a2a9-2485ed5248dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266456937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2266456937
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3515118063
Short name T1020
Test name
Test status
Simulation time 44521057 ps
CPU time 0.83 seconds
Started Jul 09 05:44:11 PM PDT 24
Finished Jul 09 05:44:15 PM PDT 24
Peak memory 206828 kb
Host smart-55d2de2b-09e3-4eae-a495-e76c8f3768af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515118063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3515118063
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.293878934
Short name T999
Test name
Test status
Simulation time 13705329 ps
CPU time 0.89 seconds
Started Jul 09 05:44:10 PM PDT 24
Finished Jul 09 05:44:13 PM PDT 24
Peak memory 206856 kb
Host smart-4d73473b-393c-4374-904d-1376da346eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293878934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.293878934
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.400419025
Short name T1061
Test name
Test status
Simulation time 32562823 ps
CPU time 0.96 seconds
Started Jul 09 05:44:16 PM PDT 24
Finished Jul 09 05:44:20 PM PDT 24
Peak memory 206840 kb
Host smart-289b6a94-441b-4d57-af84-69662b442b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400419025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.400419025
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2849466323
Short name T1062
Test name
Test status
Simulation time 26497467 ps
CPU time 0.87 seconds
Started Jul 09 05:44:10 PM PDT 24
Finished Jul 09 05:44:13 PM PDT 24
Peak memory 206668 kb
Host smart-68044427-bb66-4f4c-a508-6afc3acd7bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849466323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2849466323
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.879640894
Short name T1025
Test name
Test status
Simulation time 25958447 ps
CPU time 0.82 seconds
Started Jul 09 05:44:06 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 206840 kb
Host smart-d5696d97-c9b5-4b50-ab5c-130c606e9e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879640894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.879640894
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.276856668
Short name T1052
Test name
Test status
Simulation time 41558786 ps
CPU time 0.88 seconds
Started Jul 09 05:44:08 PM PDT 24
Finished Jul 09 05:44:11 PM PDT 24
Peak memory 206872 kb
Host smart-1cf28f6b-5558-4840-846b-f892ae9e9311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276856668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.276856668
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.964930413
Short name T255
Test name
Test status
Simulation time 106562098 ps
CPU time 1.56 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 206928 kb
Host smart-75afee7a-cead-41c0-951c-e483425e0856
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964930413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.964930413
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.5716522
Short name T1055
Test name
Test status
Simulation time 21872177 ps
CPU time 0.93 seconds
Started Jul 09 05:43:34 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 206920 kb
Host smart-2c5b9cba-7ac7-4bdc-963a-cd93a50a1721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5716522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.5716522
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2710197930
Short name T1082
Test name
Test status
Simulation time 13712916 ps
CPU time 0.94 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 206988 kb
Host smart-5c110ddf-6fb3-4928-a8b0-f407961e3310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710197930 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2710197930
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1346522075
Short name T1000
Test name
Test status
Simulation time 32420703 ps
CPU time 0.8 seconds
Started Jul 09 05:43:35 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 206764 kb
Host smart-812ee857-879c-4c61-b3b2-d44fa6017222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346522075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1346522075
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3832650816
Short name T1003
Test name
Test status
Simulation time 67018375 ps
CPU time 0.79 seconds
Started Jul 09 05:43:42 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 206684 kb
Host smart-b60766c3-e144-43cc-aced-a2a88f59c219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832650816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3832650816
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4285741704
Short name T260
Test name
Test status
Simulation time 40751237 ps
CPU time 1.21 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 207144 kb
Host smart-3df0b110-bf8e-4964-87fb-6c91dbd63c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285741704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4285741704
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2807736931
Short name T1104
Test name
Test status
Simulation time 160460974 ps
CPU time 1.69 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:51 PM PDT 24
Peak memory 215208 kb
Host smart-feb49f79-5c85-446d-830c-797fa2fadad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807736931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2807736931
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2172057515
Short name T1118
Test name
Test status
Simulation time 78988306 ps
CPU time 1.51 seconds
Started Jul 09 05:43:48 PM PDT 24
Finished Jul 09 05:43:55 PM PDT 24
Peak memory 215132 kb
Host smart-b09f4159-0e40-4cf4-a61d-64bbdfce8e59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172057515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2172057515
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3457703226
Short name T1034
Test name
Test status
Simulation time 37221997 ps
CPU time 0.85 seconds
Started Jul 09 05:44:14 PM PDT 24
Finished Jul 09 05:44:18 PM PDT 24
Peak memory 206900 kb
Host smart-41dedb5d-7b34-4938-8cd8-938179536ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457703226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3457703226
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.219520284
Short name T1048
Test name
Test status
Simulation time 27910912 ps
CPU time 0.78 seconds
Started Jul 09 05:44:10 PM PDT 24
Finished Jul 09 05:44:13 PM PDT 24
Peak memory 206716 kb
Host smart-6b997899-ae78-478b-b5c1-e42b92c24c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219520284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.219520284
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.925827007
Short name T1102
Test name
Test status
Simulation time 29340093 ps
CPU time 0.86 seconds
Started Jul 09 05:44:07 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 206876 kb
Host smart-f6d6890a-d682-4311-9579-008dd0f57cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925827007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.925827007
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3124521384
Short name T1041
Test name
Test status
Simulation time 30642430 ps
CPU time 0.85 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206888 kb
Host smart-f04f4775-eeca-4fe8-9dad-2f6c6edbfb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124521384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3124521384
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1789228018
Short name T1084
Test name
Test status
Simulation time 41687512 ps
CPU time 0.87 seconds
Started Jul 09 05:44:09 PM PDT 24
Finished Jul 09 05:44:12 PM PDT 24
Peak memory 206920 kb
Host smart-a07b2285-8f17-4fde-9bda-20cc2a0ad087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789228018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1789228018
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1401816134
Short name T1063
Test name
Test status
Simulation time 22939758 ps
CPU time 0.84 seconds
Started Jul 09 05:43:59 PM PDT 24
Finished Jul 09 05:44:01 PM PDT 24
Peak memory 206852 kb
Host smart-e956049f-dc06-44a2-9502-f1a939263d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401816134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1401816134
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3625755802
Short name T1014
Test name
Test status
Simulation time 136642336 ps
CPU time 0.81 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:57 PM PDT 24
Peak memory 206684 kb
Host smart-0e9cd7f2-3916-4329-928a-da70076f033f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625755802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3625755802
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2852346485
Short name T1044
Test name
Test status
Simulation time 25400630 ps
CPU time 0.87 seconds
Started Jul 09 05:44:02 PM PDT 24
Finished Jul 09 05:44:05 PM PDT 24
Peak memory 206860 kb
Host smart-479c1c75-30d6-41ad-8877-2e935cad8fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852346485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2852346485
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2106742255
Short name T1047
Test name
Test status
Simulation time 20083842 ps
CPU time 0.85 seconds
Started Jul 09 05:44:07 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 206844 kb
Host smart-2da3215a-232e-45ee-843d-494e199d991c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106742255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2106742255
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3141179473
Short name T1110
Test name
Test status
Simulation time 21145278 ps
CPU time 0.83 seconds
Started Jul 09 05:44:06 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 206844 kb
Host smart-555adfbf-c03d-4959-94ce-dfdc086f98cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141179473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3141179473
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2742696862
Short name T1031
Test name
Test status
Simulation time 37059676 ps
CPU time 0.95 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:44:03 PM PDT 24
Peak memory 206988 kb
Host smart-bca3ebc7-7d13-4cfd-b99c-4f70cf654803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742696862 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2742696862
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.952204672
Short name T259
Test name
Test status
Simulation time 58399152 ps
CPU time 0.95 seconds
Started Jul 09 05:43:54 PM PDT 24
Finished Jul 09 05:43:56 PM PDT 24
Peak memory 206820 kb
Host smart-04902854-2d96-4e17-991c-ac947157888a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952204672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.952204672
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3406383948
Short name T1037
Test name
Test status
Simulation time 45050522 ps
CPU time 0.79 seconds
Started Jul 09 05:43:49 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 206852 kb
Host smart-b7e074af-9c71-4167-936b-4361533223ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406383948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3406383948
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.540073445
Short name T1080
Test name
Test status
Simulation time 60029457 ps
CPU time 1.31 seconds
Started Jul 09 05:44:01 PM PDT 24
Finished Jul 09 05:44:04 PM PDT 24
Peak memory 206924 kb
Host smart-9f10eed5-1bde-4a44-8090-a4ab44803e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540073445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.540073445
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1947139057
Short name T1089
Test name
Test status
Simulation time 133442551 ps
CPU time 4.2 seconds
Started Jul 09 05:43:42 PM PDT 24
Finished Jul 09 05:43:48 PM PDT 24
Peak memory 223348 kb
Host smart-e5c6bb88-78ef-4d16-af1c-d5b5afb6e1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947139057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1947139057
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1983615180
Short name T1069
Test name
Test status
Simulation time 162383094 ps
CPU time 2.39 seconds
Started Jul 09 05:43:33 PM PDT 24
Finished Jul 09 05:43:37 PM PDT 24
Peak memory 215088 kb
Host smart-781021cf-69bc-48f0-b6fa-acd81e22ebc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983615180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1983615180
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1627926294
Short name T1071
Test name
Test status
Simulation time 38805958 ps
CPU time 1.35 seconds
Started Jul 09 05:43:44 PM PDT 24
Finished Jul 09 05:43:46 PM PDT 24
Peak memory 215320 kb
Host smart-b1ca0446-ad81-43fe-a499-f7c2040d22b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627926294 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1627926294
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.339705516
Short name T1024
Test name
Test status
Simulation time 38437829 ps
CPU time 0.86 seconds
Started Jul 09 05:43:46 PM PDT 24
Finished Jul 09 05:43:48 PM PDT 24
Peak memory 206768 kb
Host smart-087be30c-4290-46ab-8345-0d8457b5395c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339705516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.339705516
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2320853727
Short name T994
Test name
Test status
Simulation time 24437632 ps
CPU time 0.85 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:39 PM PDT 24
Peak memory 206668 kb
Host smart-a50f29f7-be0a-495d-8283-8d318240b2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320853727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2320853727
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3454982010
Short name T265
Test name
Test status
Simulation time 54289180 ps
CPU time 1.01 seconds
Started Jul 09 05:43:52 PM PDT 24
Finished Jul 09 05:43:54 PM PDT 24
Peak memory 206932 kb
Host smart-2bcfc318-0beb-4668-a383-b8ae92881f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454982010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3454982010
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3963830693
Short name T1112
Test name
Test status
Simulation time 252904799 ps
CPU time 2.08 seconds
Started Jul 09 05:43:47 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 215148 kb
Host smart-b49a7be9-8b14-4e00-9d26-391c4f7f04cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963830693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3963830693
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.591839998
Short name T274
Test name
Test status
Simulation time 792858774 ps
CPU time 1.69 seconds
Started Jul 09 05:43:42 PM PDT 24
Finished Jul 09 05:43:45 PM PDT 24
Peak memory 207096 kb
Host smart-b251595a-95bd-4849-84a5-ebe5f2071b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591839998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.591839998
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3244209674
Short name T1117
Test name
Test status
Simulation time 59569923 ps
CPU time 1.17 seconds
Started Jul 09 05:43:50 PM PDT 24
Finished Jul 09 05:43:52 PM PDT 24
Peak memory 215180 kb
Host smart-6e6cb555-d4b7-48dd-9996-4023ba2518cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244209674 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3244209674
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2117297808
Short name T1073
Test name
Test status
Simulation time 24259257 ps
CPU time 0.87 seconds
Started Jul 09 05:44:00 PM PDT 24
Finished Jul 09 05:44:03 PM PDT 24
Peak memory 206736 kb
Host smart-a69de9eb-c6a7-4582-b1ba-f43dac5167b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117297808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2117297808
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3822117311
Short name T1004
Test name
Test status
Simulation time 16271524 ps
CPU time 0.9 seconds
Started Jul 09 05:44:06 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 206840 kb
Host smart-892e67f3-00b4-4148-ac68-4333ac90a30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822117311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3822117311
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2080621774
Short name T261
Test name
Test status
Simulation time 41479691 ps
CPU time 0.93 seconds
Started Jul 09 05:43:53 PM PDT 24
Finished Jul 09 05:43:55 PM PDT 24
Peak memory 206964 kb
Host smart-662c6f85-d0b0-4164-9b5a-036227641b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080621774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2080621774
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1896826288
Short name T1011
Test name
Test status
Simulation time 54103125 ps
CPU time 2.24 seconds
Started Jul 09 05:43:45 PM PDT 24
Finished Jul 09 05:43:48 PM PDT 24
Peak memory 215248 kb
Host smart-d43fe3c5-1493-4a39-8735-b896de7ab7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896826288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1896826288
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3008238480
Short name T287
Test name
Test status
Simulation time 44118557 ps
CPU time 1.5 seconds
Started Jul 09 05:43:37 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 215184 kb
Host smart-f3343bbf-247f-4888-bb47-96e62a71027f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008238480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3008238480
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3081984346
Short name T1032
Test name
Test status
Simulation time 26016901 ps
CPU time 1 seconds
Started Jul 09 05:43:57 PM PDT 24
Finished Jul 09 05:43:59 PM PDT 24
Peak memory 215200 kb
Host smart-b10f763c-effd-47bd-a454-dc167d4a6ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081984346 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3081984346
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1216485465
Short name T1121
Test name
Test status
Simulation time 15572649 ps
CPU time 0.88 seconds
Started Jul 09 05:43:39 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 206900 kb
Host smart-765d7b3f-b901-420c-bf22-b81300172e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216485465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1216485465
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.948372779
Short name T1106
Test name
Test status
Simulation time 13383155 ps
CPU time 0.88 seconds
Started Jul 09 05:43:56 PM PDT 24
Finished Jul 09 05:43:58 PM PDT 24
Peak memory 206860 kb
Host smart-39035a83-5d4e-40ac-b67d-d2bad219b41d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948372779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.948372779
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1662110090
Short name T1040
Test name
Test status
Simulation time 71475758 ps
CPU time 1.39 seconds
Started Jul 09 05:44:07 PM PDT 24
Finished Jul 09 05:44:11 PM PDT 24
Peak memory 207020 kb
Host smart-3c6f9164-1437-4e9b-a556-519e7f023b8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662110090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1662110090
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.166414350
Short name T998
Test name
Test status
Simulation time 151517203 ps
CPU time 2.66 seconds
Started Jul 09 05:43:36 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 215196 kb
Host smart-42650f0a-443e-498b-8995-81b8d6d22fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166414350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.166414350
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.603687644
Short name T1075
Test name
Test status
Simulation time 235728146 ps
CPU time 2.19 seconds
Started Jul 09 05:43:55 PM PDT 24
Finished Jul 09 05:43:59 PM PDT 24
Peak memory 206972 kb
Host smart-94445787-9a50-4a22-917b-e68782bfb77d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603687644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.603687644
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2912415972
Short name T1019
Test name
Test status
Simulation time 154744813 ps
CPU time 0.92 seconds
Started Jul 09 05:44:05 PM PDT 24
Finished Jul 09 05:44:09 PM PDT 24
Peak memory 206964 kb
Host smart-6bccca55-7b38-477b-9632-8d9c5fe7fab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912415972 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2912415972
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1387906076
Short name T1103
Test name
Test status
Simulation time 33291590 ps
CPU time 0.93 seconds
Started Jul 09 05:43:51 PM PDT 24
Finished Jul 09 05:43:52 PM PDT 24
Peak memory 206924 kb
Host smart-ca4c1325-0849-44fb-a53f-6b3c884dbc52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387906076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1387906076
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4294367306
Short name T1088
Test name
Test status
Simulation time 14748739 ps
CPU time 0.89 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206804 kb
Host smart-253f6175-5a96-45e9-80e2-3469406770ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294367306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4294367306
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3977932044
Short name T1101
Test name
Test status
Simulation time 36907641 ps
CPU time 1.09 seconds
Started Jul 09 05:44:04 PM PDT 24
Finished Jul 09 05:44:07 PM PDT 24
Peak memory 206908 kb
Host smart-be7e54af-442f-4e94-988c-f42e2b4af4cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977932044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3977932044
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1663544076
Short name T1051
Test name
Test status
Simulation time 90378644 ps
CPU time 1.88 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:43 PM PDT 24
Peak memory 215212 kb
Host smart-ef574c2f-977d-49f7-92ef-7f243aa3a5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663544076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1663544076
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2259435187
Short name T1105
Test name
Test status
Simulation time 150677216 ps
CPU time 1.52 seconds
Started Jul 09 05:43:38 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 206820 kb
Host smart-9bc4ee1e-d975-4c1a-aa55-b52522ce49c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259435187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2259435187
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3629142399
Short name T247
Test name
Test status
Simulation time 99267649 ps
CPU time 1.23 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 220380 kb
Host smart-4521452d-423e-4f12-9784-73ba23b128cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629142399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3629142399
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1017932393
Short name T937
Test name
Test status
Simulation time 70657563 ps
CPU time 0.84 seconds
Started Jul 09 05:44:19 PM PDT 24
Finished Jul 09 05:44:22 PM PDT 24
Peak memory 207012 kb
Host smart-4e6c8e28-5b3a-4934-87b6-c90c33443ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017932393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1017932393
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3263965642
Short name T388
Test name
Test status
Simulation time 114496555 ps
CPU time 1.01 seconds
Started Jul 09 05:44:17 PM PDT 24
Finished Jul 09 05:44:21 PM PDT 24
Peak memory 217124 kb
Host smart-7b690c84-e3dc-4d23-b05a-4212a6488915
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263965642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3263965642
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2685635869
Short name T138
Test name
Test status
Simulation time 27588298 ps
CPU time 0.99 seconds
Started Jul 09 05:44:25 PM PDT 24
Finished Jul 09 05:44:29 PM PDT 24
Peak memory 224216 kb
Host smart-f597709e-0177-4e9f-bcf2-0c0e72c50c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685635869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2685635869
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.768836596
Short name T548
Test name
Test status
Simulation time 176326645 ps
CPU time 3.04 seconds
Started Jul 09 05:44:45 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 220312 kb
Host smart-42797985-b64f-4e8b-a7a0-c755c1c864f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768836596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.768836596
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3153280626
Short name T69
Test name
Test status
Simulation time 897255814 ps
CPU time 5.93 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 235580 kb
Host smart-b0f3f5f4-9ea1-4b8b-9577-c6392924bc59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153280626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3153280626
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2244898406
Short name T660
Test name
Test status
Simulation time 22105098 ps
CPU time 0.91 seconds
Started Jul 09 05:44:45 PM PDT 24
Finished Jul 09 05:44:47 PM PDT 24
Peak memory 215516 kb
Host smart-9ce0814c-48d0-4a77-b9b5-06e75952d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244898406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2244898406
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2844351242
Short name T590
Test name
Test status
Simulation time 77521932 ps
CPU time 1.93 seconds
Started Jul 09 05:44:25 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 215460 kb
Host smart-18ca49c2-281b-4b7a-9012-aaf59eb2a6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844351242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2844351242
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2376034272
Short name T588
Test name
Test status
Simulation time 192351439289 ps
CPU time 2053.45 seconds
Started Jul 09 05:44:43 PM PDT 24
Finished Jul 09 06:18:57 PM PDT 24
Peak memory 227032 kb
Host smart-44828fc9-975e-4e7e-8458-047aec7d84f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376034272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2376034272
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1695070955
Short name T670
Test name
Test status
Simulation time 37215770 ps
CPU time 1.16 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 218576 kb
Host smart-d7fefc42-d50c-4703-a588-cef51505e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695070955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1695070955
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4279886677
Short name T593
Test name
Test status
Simulation time 18293356 ps
CPU time 0.94 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 207020 kb
Host smart-b1db8988-248d-4a13-bd53-fcb291609a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279886677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4279886677
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2862193936
Short name T798
Test name
Test status
Simulation time 35206766 ps
CPU time 1.23 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:30 PM PDT 24
Peak memory 218904 kb
Host smart-ee50f687-f23b-4102-82ea-a515c2a1c137
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862193936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2862193936
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.392644262
Short name T839
Test name
Test status
Simulation time 33296407 ps
CPU time 0.83 seconds
Started Jul 09 05:44:22 PM PDT 24
Finished Jul 09 05:44:25 PM PDT 24
Peak memory 218724 kb
Host smart-b3879eb4-63db-423d-81d8-49cfaed9f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392644262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.392644262
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2045779112
Short name T516
Test name
Test status
Simulation time 57255560 ps
CPU time 1.32 seconds
Started Jul 09 05:44:22 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 219056 kb
Host smart-ea320989-713f-464e-8a02-68028c1f7d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045779112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2045779112
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2579957798
Short name T608
Test name
Test status
Simulation time 16782003 ps
CPU time 0.97 seconds
Started Jul 09 05:44:23 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 207392 kb
Host smart-6971fa87-59cf-4900-8267-e4f8305c6075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579957798 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2579957798
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.823910429
Short name T21
Test name
Test status
Simulation time 860925866 ps
CPU time 6.79 seconds
Started Jul 09 05:44:42 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 238032 kb
Host smart-3f7949af-5e52-4d01-8f8c-34a6da4f8507
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823910429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.823910429
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2674920010
Short name T372
Test name
Test status
Simulation time 37227460 ps
CPU time 0.92 seconds
Started Jul 09 05:44:24 PM PDT 24
Finished Jul 09 05:44:27 PM PDT 24
Peak memory 215808 kb
Host smart-70f98e3c-59a5-462e-bf8f-6f68f3ba019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674920010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2674920010
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3251118493
Short name T417
Test name
Test status
Simulation time 651879914 ps
CPU time 4.62 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:36 PM PDT 24
Peak memory 217636 kb
Host smart-1979f40b-f3ce-4365-84e2-9183fbcfa2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251118493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3251118493
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1155384522
Short name T108
Test name
Test status
Simulation time 585973288447 ps
CPU time 895.39 seconds
Started Jul 09 05:44:23 PM PDT 24
Finished Jul 09 05:59:22 PM PDT 24
Peak memory 220648 kb
Host smart-3b984556-8480-41e0-8be2-0ff6905b06be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155384522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1155384522
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3502450540
Short name T485
Test name
Test status
Simulation time 31571152 ps
CPU time 0.96 seconds
Started Jul 09 05:44:40 PM PDT 24
Finished Jul 09 05:44:41 PM PDT 24
Peak memory 215468 kb
Host smart-f50be04b-72f6-49bf-9281-4b6b6c13d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502450540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3502450540
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3290474956
Short name T567
Test name
Test status
Simulation time 43394156 ps
CPU time 1.44 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 217220 kb
Host smart-8df5d543-d0ca-4d24-bacf-c0731a0c29c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290474956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3290474956
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.3676294496
Short name T542
Test name
Test status
Simulation time 37363759 ps
CPU time 1.66 seconds
Started Jul 09 05:45:00 PM PDT 24
Finished Jul 09 05:45:02 PM PDT 24
Peak memory 220516 kb
Host smart-22dac4a6-c1ab-4637-a915-5adfc649f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676294496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3676294496
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3518809638
Short name T885
Test name
Test status
Simulation time 102112482 ps
CPU time 0.84 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 215620 kb
Host smart-b8aa5473-4e34-4acb-bba9-9de0b1be6aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518809638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3518809638
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1091343856
Short name T889
Test name
Test status
Simulation time 29474429 ps
CPU time 0.97 seconds
Started Jul 09 05:44:47 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 215624 kb
Host smart-0252c808-2196-48a1-825f-9eaeab20b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091343856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1091343856
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3535609491
Short name T229
Test name
Test status
Simulation time 61284869049 ps
CPU time 1525.82 seconds
Started Jul 09 05:44:37 PM PDT 24
Finished Jul 09 06:10:03 PM PDT 24
Peak memory 225640 kb
Host smart-2bcbecef-61db-4282-bad0-76f97e804f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535609491 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3535609491
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.890432686
Short name T190
Test name
Test status
Simulation time 33833827 ps
CPU time 1.12 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 220328 kb
Host smart-60679e35-ecdb-4293-9f2e-04f3521a53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890432686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.890432686
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.896787007
Short name T11
Test name
Test status
Simulation time 56327451 ps
CPU time 1.44 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 219080 kb
Host smart-c755bb0e-b566-41c1-94eb-3da8c2ac4df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896787007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.896787007
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3267120452
Short name T817
Test name
Test status
Simulation time 56591913 ps
CPU time 1.28 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 219348 kb
Host smart-6dd06e06-20bf-475a-980c-a7f3eac552da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267120452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3267120452
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2389426633
Short name T474
Test name
Test status
Simulation time 305268825 ps
CPU time 1.69 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 219260 kb
Host smart-9652000a-daea-482f-b33e-a2d02355b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389426633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2389426633
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1127229809
Short name T444
Test name
Test status
Simulation time 45819002 ps
CPU time 1.18 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 218928 kb
Host smart-b3f2b6c1-bd71-4050-a7fa-e7be5ea182f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127229809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1127229809
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3085835831
Short name T453
Test name
Test status
Simulation time 24520749 ps
CPU time 1.26 seconds
Started Jul 09 05:45:55 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 218896 kb
Host smart-70b36b99-8023-4638-ab1f-1dfc40edba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085835831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3085835831
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.941577765
Short name T43
Test name
Test status
Simulation time 42301262 ps
CPU time 1.64 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 217884 kb
Host smart-361e1891-0300-40cf-a1cd-d1658ae70bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941577765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.941577765
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2439622304
Short name T163
Test name
Test status
Simulation time 55415078 ps
CPU time 1.11 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 219764 kb
Host smart-6c3f6af8-3282-4a31-bbfd-729e271b38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439622304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2439622304
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.3540823085
Short name T668
Test name
Test status
Simulation time 23889309 ps
CPU time 1.19 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 220188 kb
Host smart-916c04e8-46b4-4a94-bb6d-bb85fd01fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540823085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3540823085
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.595592630
Short name T576
Test name
Test status
Simulation time 45929738 ps
CPU time 1.1 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 219916 kb
Host smart-ee16ff90-14f1-4c81-b156-cd7465cdb438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595592630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.595592630
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2988386594
Short name T443
Test name
Test status
Simulation time 41442061 ps
CPU time 1.09 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 218816 kb
Host smart-ecaeb910-d9bf-42da-a282-df14d0f68549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988386594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2988386594
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3417492281
Short name T172
Test name
Test status
Simulation time 68815276 ps
CPU time 1.06 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 221428 kb
Host smart-9dd06e51-9934-4992-bb86-94aff92d869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417492281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3417492281
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1476252797
Short name T881
Test name
Test status
Simulation time 45595908 ps
CPU time 1.7 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 218960 kb
Host smart-c33c494f-e038-4e32-a6e8-c5c73c769bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476252797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1476252797
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1811463439
Short name T939
Test name
Test status
Simulation time 22456847 ps
CPU time 1.18 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 219912 kb
Host smart-fba7773a-8dc2-4507-8a99-221b0fe8376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811463439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1811463439
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1659825654
Short name T756
Test name
Test status
Simulation time 35816821 ps
CPU time 1.19 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 217692 kb
Host smart-457b4d63-9989-4849-9920-7017be95cbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659825654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1659825654
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.281308235
Short name T938
Test name
Test status
Simulation time 43003159 ps
CPU time 1.11 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 219008 kb
Host smart-611e9d0f-b596-4f9c-8b04-02e3e6124541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281308235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.281308235
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2757251354
Short name T773
Test name
Test status
Simulation time 47021869 ps
CPU time 1.41 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 217472 kb
Host smart-28e2f7f1-00d4-45f7-9f59-85cbde85dc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757251354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2757251354
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2805162939
Short name T678
Test name
Test status
Simulation time 70252675 ps
CPU time 1.11 seconds
Started Jul 09 05:44:41 PM PDT 24
Finished Jul 09 05:44:42 PM PDT 24
Peak memory 218916 kb
Host smart-4f4c5c91-eae8-4d74-90b4-aeb66aff81a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805162939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2805162939
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.473807205
Short name T872
Test name
Test status
Simulation time 43126343 ps
CPU time 0.88 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:53 PM PDT 24
Peak memory 207024 kb
Host smart-5325a509-b109-403d-825a-97a1c8ee83f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473807205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.473807205
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2179405799
Short name T808
Test name
Test status
Simulation time 21915449 ps
CPU time 0.9 seconds
Started Jul 09 05:44:41 PM PDT 24
Finished Jul 09 05:44:42 PM PDT 24
Peak memory 215700 kb
Host smart-7f03bd5f-e94c-4a57-ad0e-c73e5a8652fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179405799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2179405799
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2599842085
Short name T681
Test name
Test status
Simulation time 116934604 ps
CPU time 1.27 seconds
Started Jul 09 05:44:43 PM PDT 24
Finished Jul 09 05:44:45 PM PDT 24
Peak memory 220168 kb
Host smart-abcc577b-e2d4-4679-a9a5-214f41416c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599842085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2599842085
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2720563251
Short name T458
Test name
Test status
Simulation time 110364571 ps
CPU time 1.53 seconds
Started Jul 09 05:44:43 PM PDT 24
Finished Jul 09 05:44:45 PM PDT 24
Peak memory 219012 kb
Host smart-71825c42-e102-45b7-b0b0-894c4afb687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720563251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2720563251
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4203206259
Short name T701
Test name
Test status
Simulation time 20515767 ps
CPU time 1.08 seconds
Started Jul 09 05:44:43 PM PDT 24
Finished Jul 09 05:44:44 PM PDT 24
Peak memory 216188 kb
Host smart-c80b50c3-a14c-45ad-b651-f12ed4048e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203206259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4203206259
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1264030708
Short name T896
Test name
Test status
Simulation time 54446037 ps
CPU time 0.96 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 215588 kb
Host smart-5c0288f3-1bc2-4d3a-a65f-ed9710c176ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264030708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1264030708
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2300296587
Short name T981
Test name
Test status
Simulation time 1796880195977 ps
CPU time 2347.87 seconds
Started Jul 09 05:44:41 PM PDT 24
Finished Jul 09 06:23:50 PM PDT 24
Peak memory 228012 kb
Host smart-22702f27-72ba-4dcd-971b-9e8fcfabf294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300296587 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2300296587
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2583578109
Short name T959
Test name
Test status
Simulation time 24892251 ps
CPU time 1.26 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 218868 kb
Host smart-1472dff3-f01d-47e3-8ccc-5b8a1090144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583578109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2583578109
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3821012048
Short name T880
Test name
Test status
Simulation time 59062776 ps
CPU time 2 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 217828 kb
Host smart-d2736d5a-24ff-41e3-8dbb-c6fce4398d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821012048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3821012048
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4112484036
Short name T95
Test name
Test status
Simulation time 72071625 ps
CPU time 1.09 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 219456 kb
Host smart-40157d57-a5f2-43f0-b45b-3463c9201c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112484036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4112484036
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2285851829
Short name T847
Test name
Test status
Simulation time 41826418 ps
CPU time 1.37 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 217524 kb
Host smart-6d21f47a-e3f5-4611-87d2-932ed9741f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285851829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2285851829
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3905598192
Short name T884
Test name
Test status
Simulation time 53795730 ps
CPU time 1.17 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 216024 kb
Host smart-3e907845-1f96-43d3-828f-0d2d44bc6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905598192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3905598192
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.692217561
Short name T790
Test name
Test status
Simulation time 90019088 ps
CPU time 1.37 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:59 PM PDT 24
Peak memory 219348 kb
Host smart-38e0e4f7-16c9-4d23-bc42-8c4764c7ed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692217561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.692217561
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4230435844
Short name T890
Test name
Test status
Simulation time 72840744 ps
CPU time 1.74 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 220192 kb
Host smart-f512c50d-2d9e-495a-87d1-3f4091593631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230435844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4230435844
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.913555344
Short name T921
Test name
Test status
Simulation time 111910632 ps
CPU time 1.13 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 221704 kb
Host smart-853c6a34-6367-46c3-858f-528432f398eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913555344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.913555344
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.116553421
Short name T909
Test name
Test status
Simulation time 176116890 ps
CPU time 1.93 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 220516 kb
Host smart-08e55b69-9896-4ba7-a5dc-1447861324da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116553421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.116553421
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.144508389
Short name T630
Test name
Test status
Simulation time 42520726 ps
CPU time 1.78 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 218884 kb
Host smart-c6a6b03f-6090-428e-9ecc-2aa30f3f20b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144508389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.144508389
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3132026142
Short name T744
Test name
Test status
Simulation time 77179011 ps
CPU time 1.28 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 218768 kb
Host smart-b4c2d3d9-e731-476a-a3a9-54fdc23adf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132026142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3132026142
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1098105648
Short name T330
Test name
Test status
Simulation time 155356164 ps
CPU time 1.22 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 220404 kb
Host smart-8cfa2a5b-dfd8-4228-88f8-f00260905ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098105648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1098105648
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.4014751478
Short name T275
Test name
Test status
Simulation time 45233704 ps
CPU time 1.35 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 216088 kb
Host smart-6852a381-6f24-4810-a2ec-75c9c0a7a302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014751478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.4014751478
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1859748291
Short name T848
Test name
Test status
Simulation time 44326086 ps
CPU time 1.13 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 220240 kb
Host smart-55afc016-b70f-4e0a-a26c-f632aca8a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859748291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1859748291
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.853086645
Short name T278
Test name
Test status
Simulation time 28046002 ps
CPU time 1.29 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:12 PM PDT 24
Peak memory 218820 kb
Host smart-1d368e45-3b1c-4f9e-bbed-6352654eed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853086645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.853086645
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.3020370109
Short name T295
Test name
Test status
Simulation time 89009294 ps
CPU time 1.15 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 218864 kb
Host smart-a7a2ac1f-5efc-458d-ab5b-a259c67a0d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020370109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3020370109
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.284055656
Short name T675
Test name
Test status
Simulation time 45067291 ps
CPU time 1.14 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 221152 kb
Host smart-4472e9a9-5fcc-4e9a-9ac5-d45e68c160b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284055656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.284055656
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.120096279
Short name T456
Test name
Test status
Simulation time 177522245 ps
CPU time 0.93 seconds
Started Jul 09 05:44:44 PM PDT 24
Finished Jul 09 05:44:45 PM PDT 24
Peak memory 207072 kb
Host smart-1177326d-66fb-4448-b482-f557bf7c3b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120096279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.120096279
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3968070975
Short name T206
Test name
Test status
Simulation time 29429148 ps
CPU time 0.81 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 216644 kb
Host smart-ac7eb852-1a6e-4484-ad3f-88d98f2258af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968070975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3968070975
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2997820162
Short name T441
Test name
Test status
Simulation time 188191356 ps
CPU time 1.02 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 217208 kb
Host smart-448b610b-77f1-4db0-bfbf-d0ac0aea52ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997820162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2997820162
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.985488851
Short name T643
Test name
Test status
Simulation time 30425372 ps
CPU time 0.88 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 218552 kb
Host smart-e76751f1-a3e3-49c3-bf07-f6fd259712ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985488851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.985488851
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.1606115896
Short name T679
Test name
Test status
Simulation time 27705747 ps
CPU time 1.05 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:50 PM PDT 24
Peak memory 224404 kb
Host smart-60a43695-9662-465c-b578-560d3a4cdb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606115896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1606115896
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2918120909
Short name T521
Test name
Test status
Simulation time 92157649 ps
CPU time 0.9 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 215640 kb
Host smart-bc9f5fe1-0d84-4c3a-81f6-e2ff01a569e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918120909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2918120909
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.975035360
Short name T578
Test name
Test status
Simulation time 510055126 ps
CPU time 1.8 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 217796 kb
Host smart-e7457ebe-2c59-4990-a2a9-e3095cdb817f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975035360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.975035360
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3753985340
Short name T236
Test name
Test status
Simulation time 114766792985 ps
CPU time 1025.67 seconds
Started Jul 09 05:44:51 PM PDT 24
Finished Jul 09 06:01:57 PM PDT 24
Peak memory 223024 kb
Host smart-fc5494df-3725-4e09-83aa-934e33b54ec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753985340 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3753985340
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2654226091
Short name T98
Test name
Test status
Simulation time 75621134 ps
CPU time 1.28 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 219296 kb
Host smart-13531969-f430-4003-b8df-4b9b577fc5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654226091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2654226091
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1262128760
Short name T665
Test name
Test status
Simulation time 36544605 ps
CPU time 1.01 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 217532 kb
Host smart-a8c8459a-9992-43ff-883d-dfc111f885e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262128760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1262128760
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.737466622
Short name T852
Test name
Test status
Simulation time 195181058 ps
CPU time 1.06 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 221168 kb
Host smart-741fc9c6-aaef-4bb8-a1bc-09608ba29ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737466622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.737466622
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.4012059942
Short name T312
Test name
Test status
Simulation time 42821865 ps
CPU time 1.48 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217792 kb
Host smart-6274f2be-19f5-4eeb-8f57-bb6e18be98ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012059942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4012059942
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3186005471
Short name T171
Test name
Test status
Simulation time 49520257 ps
CPU time 1.04 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 218760 kb
Host smart-005a5abb-9896-4046-877e-3abcc22a3554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186005471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3186005471
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1764639769
Short name T855
Test name
Test status
Simulation time 57509928 ps
CPU time 1.64 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 219352 kb
Host smart-55bc9b35-d91d-4872-99ad-270cf13e33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764639769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1764639769
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1721565837
Short name T727
Test name
Test status
Simulation time 126049534 ps
CPU time 1.17 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 218916 kb
Host smart-2a2b691a-5ed7-451a-a735-010d234970dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721565837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1721565837
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2730168185
Short name T566
Test name
Test status
Simulation time 406120302 ps
CPU time 3.78 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 220496 kb
Host smart-f546cfe5-eb53-4b58-b170-001ba3c7e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730168185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2730168185
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.4224662968
Short name T845
Test name
Test status
Simulation time 75728013 ps
CPU time 1.08 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 218868 kb
Host smart-b4de1e21-f2f0-4ecc-aa07-369739134c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224662968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.4224662968
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2791249060
Short name T569
Test name
Test status
Simulation time 48850194 ps
CPU time 1.85 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 218924 kb
Host smart-fa247e64-08da-4dd5-aef5-9f8522c7e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791249060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2791249060
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3143374567
Short name T434
Test name
Test status
Simulation time 92355357 ps
CPU time 1.2 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 216016 kb
Host smart-453ded26-09c7-4077-b2d2-2ef5be19d586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143374567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3143374567
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3089941030
Short name T629
Test name
Test status
Simulation time 33875303 ps
CPU time 1.34 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 217580 kb
Host smart-d03cd9db-e317-49fb-b0be-eaf2a8899ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089941030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3089941030
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1501168002
Short name T826
Test name
Test status
Simulation time 96511180 ps
CPU time 1.15 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 215972 kb
Host smart-e4f39c86-3954-4a89-a473-2d50be17a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501168002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1501168002
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1202931476
Short name T676
Test name
Test status
Simulation time 80930290 ps
CPU time 1.34 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 220436 kb
Host smart-fab33598-edaf-488c-a4ab-c25492d2484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202931476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1202931476
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.584713250
Short name T152
Test name
Test status
Simulation time 31291810 ps
CPU time 1.12 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 218868 kb
Host smart-65b0d074-7115-4303-9719-5f6ae9370b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584713250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.584713250
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1023826765
Short name T94
Test name
Test status
Simulation time 104190908 ps
CPU time 1.08 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 217512 kb
Host smart-d3f809ff-fb11-486a-a30e-5fd770dd10c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023826765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1023826765
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1568117471
Short name T140
Test name
Test status
Simulation time 85744135 ps
CPU time 1.14 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 221184 kb
Host smart-f42f44c7-a718-43e8-aa5f-12c342e6fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568117471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1568117471
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3123266306
Short name T531
Test name
Test status
Simulation time 35882051 ps
CPU time 1.63 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 219296 kb
Host smart-0e6c7933-1438-4957-aba1-d5123dd5eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123266306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3123266306
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1712564931
Short name T803
Test name
Test status
Simulation time 92198982 ps
CPU time 1.3 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 219276 kb
Host smart-98ea6a20-d9bf-4b3c-bda2-8b3f713247fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712564931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1712564931
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.359284313
Short name T693
Test name
Test status
Simulation time 38603310 ps
CPU time 1.17 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:51 PM PDT 24
Peak memory 220096 kb
Host smart-87af7a1e-2542-4d06-acf1-12c41d126d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359284313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.359284313
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1271780517
Short name T742
Test name
Test status
Simulation time 85169364 ps
CPU time 0.87 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 215200 kb
Host smart-f0d6fbba-b0a0-46c2-8078-adb50d6b6258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271780517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1271780517
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2168130929
Short name T187
Test name
Test status
Simulation time 39098127 ps
CPU time 0.88 seconds
Started Jul 09 05:44:47 PM PDT 24
Finished Jul 09 05:44:48 PM PDT 24
Peak memory 216560 kb
Host smart-dbac62f7-949c-4563-962e-cbe08d8e17d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168130929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2168130929
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3604064561
Short name T71
Test name
Test status
Simulation time 93810677 ps
CPU time 1.14 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:02 PM PDT 24
Peak memory 217084 kb
Host smart-acc42ffe-817e-4747-840f-327e1c2a42ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604064561 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3604064561
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1021504887
Short name T530
Test name
Test status
Simulation time 62923555 ps
CPU time 0.99 seconds
Started Jul 09 05:44:48 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 219068 kb
Host smart-64dd7fdd-f8ca-43fd-a19b-d3d6dd210c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021504887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1021504887
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2357596234
Short name T891
Test name
Test status
Simulation time 49869937 ps
CPU time 1.12 seconds
Started Jul 09 05:44:53 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 219208 kb
Host smart-fdd63085-9c07-400c-a4e7-6c228de597dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357596234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2357596234
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2500781442
Short name T107
Test name
Test status
Simulation time 25873746 ps
CPU time 0.94 seconds
Started Jul 09 05:44:42 PM PDT 24
Finished Jul 09 05:44:43 PM PDT 24
Peak memory 216156 kb
Host smart-7c2aad45-c3ec-4c47-90df-f29232e395a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500781442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2500781442
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2209617503
Short name T245
Test name
Test status
Simulation time 93214807 ps
CPU time 0.82 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 215344 kb
Host smart-7c80ca5c-ee2a-4a7b-9b8f-2244a7a5e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209617503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2209617503
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3434286390
Short name T823
Test name
Test status
Simulation time 145573606 ps
CPU time 3.39 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 215692 kb
Host smart-7f858a40-d1b9-4ef3-9683-d6971431b860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434286390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3434286390
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.2404800321
Short name T628
Test name
Test status
Simulation time 23672390 ps
CPU time 1.22 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 219628 kb
Host smart-3133c3da-0e63-450d-8bf2-7404382bd5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404800321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2404800321
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3432451226
Short name T849
Test name
Test status
Simulation time 29495611 ps
CPU time 1.3 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 218660 kb
Host smart-e82ee397-ed07-4788-bf9c-00a12967b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432451226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3432451226
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.680698178
Short name T435
Test name
Test status
Simulation time 59058745 ps
CPU time 1.41 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 219044 kb
Host smart-7d301736-f230-431e-8045-ae5ed63b0e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680698178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.680698178
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1908322044
Short name T184
Test name
Test status
Simulation time 24409876 ps
CPU time 1.18 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 219048 kb
Host smart-fd7c63b6-4449-4e3a-972a-4cbd20fa5bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908322044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1908322044
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2192499189
Short name T376
Test name
Test status
Simulation time 89998855 ps
CPU time 1.08 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:45:59 PM PDT 24
Peak memory 217440 kb
Host smart-a400947c-783a-4e30-bc5d-371744777b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192499189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2192499189
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1813348524
Short name T783
Test name
Test status
Simulation time 28141153 ps
CPU time 1.21 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 218872 kb
Host smart-3083f866-f3af-4d5e-b05d-b9bda8061d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813348524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1813348524
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.29672421
Short name T836
Test name
Test status
Simulation time 49838012 ps
CPU time 1.2 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 220444 kb
Host smart-69505362-d222-49ce-b2b3-8d25e6380eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29672421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.29672421
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1504816637
Short name T544
Test name
Test status
Simulation time 96286490 ps
CPU time 1.15 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 218804 kb
Host smart-9abc4f61-a5fb-465b-a045-d446cd36ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504816637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1504816637
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1498733035
Short name T409
Test name
Test status
Simulation time 88652249 ps
CPU time 1.15 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 220388 kb
Host smart-b9825688-aced-4f7c-8101-d6b28a5e24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498733035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1498733035
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1439766050
Short name T653
Test name
Test status
Simulation time 50400834 ps
CPU time 1.25 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:12 PM PDT 24
Peak memory 218824 kb
Host smart-8613c781-0242-46cf-bc1a-30b0ede9a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439766050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1439766050
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1008604957
Short name T159
Test name
Test status
Simulation time 30035128 ps
CPU time 1.22 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:12 PM PDT 24
Peak memory 215964 kb
Host smart-004fc07e-9a72-4edf-8c1c-08075bde1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008604957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1008604957
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2749145523
Short name T745
Test name
Test status
Simulation time 102934776 ps
CPU time 1.34 seconds
Started Jul 09 05:46:39 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 219336 kb
Host smart-0a624bc4-dadf-449a-bb23-552aba1fa783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749145523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2749145523
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2209285448
Short name T76
Test name
Test status
Simulation time 132975493 ps
CPU time 1.1 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 218820 kb
Host smart-8999b55b-bf4f-4947-97bd-648189bae70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209285448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2209285448
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3872792455
Short name T370
Test name
Test status
Simulation time 119077678 ps
CPU time 1.26 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 219092 kb
Host smart-fb326c19-e303-4165-ab39-08a686d1a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872792455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3872792455
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.307956291
Short name T951
Test name
Test status
Simulation time 109525418 ps
CPU time 1.55 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 219052 kb
Host smart-40ef5b79-3c86-4cb6-90ed-c5bf5d9cd933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307956291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.307956291
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2960685836
Short name T85
Test name
Test status
Simulation time 39642439 ps
CPU time 1.16 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 219040 kb
Host smart-d0773765-697e-4e94-801a-57e7dc7b2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960685836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2960685836
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1516632083
Short name T375
Test name
Test status
Simulation time 41138196 ps
CPU time 1.11 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 220224 kb
Host smart-719b83a1-0fb8-47a5-b88d-de7a8ac44d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516632083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1516632083
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2373153290
Short name T473
Test name
Test status
Simulation time 92287078 ps
CPU time 1.2 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 221136 kb
Host smart-1369d110-d179-4c4f-a842-8b5951949b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373153290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2373153290
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.210335080
Short name T658
Test name
Test status
Simulation time 13442663 ps
CPU time 0.88 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:51 PM PDT 24
Peak memory 207000 kb
Host smart-09ba6152-60b0-4976-adb1-176250d83a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210335080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.210335080
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.4185105998
Short name T991
Test name
Test status
Simulation time 30141855 ps
CPU time 1.22 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 220064 kb
Host smart-6ab7f062-1c4b-4a41-a76e-0d40dcf7fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185105998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4185105998
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1261431847
Short name T947
Test name
Test status
Simulation time 29994827 ps
CPU time 1.24 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:51 PM PDT 24
Peak memory 217708 kb
Host smart-437c3374-faa2-4cb0-9704-7b1a0a4e3e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261431847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1261431847
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1065788093
Short name T888
Test name
Test status
Simulation time 60494668 ps
CPU time 0.93 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 215540 kb
Host smart-7224f266-4ba8-4ecc-b595-478e1699de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065788093 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1065788093
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.4109042699
Short name T985
Test name
Test status
Simulation time 20699420 ps
CPU time 0.97 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 215620 kb
Host smart-653a7bd9-6780-4875-9e52-c954f367f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109042699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4109042699
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1499772638
Short name T772
Test name
Test status
Simulation time 250391490 ps
CPU time 4.88 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 215612 kb
Host smart-3bda6e6b-3640-40c5-9337-349e0f6d58bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499772638 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1499772638
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3985733969
Short name T760
Test name
Test status
Simulation time 95667736034 ps
CPU time 1036.18 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 06:02:12 PM PDT 24
Peak memory 224016 kb
Host smart-f6e61c01-7204-431d-8fe0-1a735284d090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985733969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3985733969
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3931379451
Short name T194
Test name
Test status
Simulation time 21340748 ps
CPU time 1.13 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 215980 kb
Host smart-12e691ab-3730-464c-9bc9-0a2f9951df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931379451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3931379451
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.4262998200
Short name T953
Test name
Test status
Simulation time 98415088 ps
CPU time 1.12 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 217552 kb
Host smart-14cceea8-16b2-4325-aba6-2bbf1ab1a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262998200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4262998200
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.70470131
Short name T714
Test name
Test status
Simulation time 60455184 ps
CPU time 1.1 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 220228 kb
Host smart-13fda66a-a483-4c61-862b-87140892b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70470131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.70470131
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.4017440532
Short name T294
Test name
Test status
Simulation time 43297424 ps
CPU time 1.27 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 219316 kb
Host smart-045ee29f-1aa5-4ad3-8d89-ab268ead4154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017440532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4017440532
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.4124494861
Short name T746
Test name
Test status
Simulation time 53447238 ps
CPU time 1.34 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 219204 kb
Host smart-f88865ee-69b7-48b9-ad3e-338db2136e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124494861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4124494861
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3174924688
Short name T131
Test name
Test status
Simulation time 26667039 ps
CPU time 1.19 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 218880 kb
Host smart-dedded57-1a93-491a-bc47-83c9d388856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174924688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3174924688
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1483099128
Short name T621
Test name
Test status
Simulation time 112077278 ps
CPU time 1.01 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 217612 kb
Host smart-d3b87f94-8b88-4f5c-9256-a16d78e2b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483099128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1483099128
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.290253926
Short name T963
Test name
Test status
Simulation time 51835884 ps
CPU time 1.14 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219824 kb
Host smart-dc2d5b95-4930-4605-aa18-c1a498b7939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290253926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.290253926
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2588040343
Short name T464
Test name
Test status
Simulation time 28129526 ps
CPU time 1.18 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 218668 kb
Host smart-1e1167e2-1e08-40d3-a753-a99aabd43144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588040343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2588040343
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1116743008
Short name T121
Test name
Test status
Simulation time 64920568 ps
CPU time 1.19 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219208 kb
Host smart-7bef92a1-2901-46ad-a4f2-d6e757ef3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116743008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1116743008
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2356046512
Short name T93
Test name
Test status
Simulation time 39632068 ps
CPU time 1.14 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 217500 kb
Host smart-8c2b96b7-aae6-4ff8-937c-d98782c46d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356046512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2356046512
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2266844737
Short name T865
Test name
Test status
Simulation time 87842218 ps
CPU time 1.14 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 220100 kb
Host smart-fd8485e7-6a99-4ed3-b8f1-d7862ac85356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266844737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2266844737
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.750348967
Short name T243
Test name
Test status
Simulation time 55992102 ps
CPU time 1.27 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 218860 kb
Host smart-2c9f6c0e-502a-4317-a3c1-0763fcb37795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750348967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.750348967
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1232431750
Short name T664
Test name
Test status
Simulation time 22775205 ps
CPU time 1.17 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219836 kb
Host smart-f6396770-17f5-4eaa-bd77-31e371246391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232431750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1232431750
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.2909688254
Short name T191
Test name
Test status
Simulation time 145910988 ps
CPU time 1.11 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219256 kb
Host smart-12177b8a-da51-467e-ae28-ff7a5e6b750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909688254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2909688254
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.1432496107
Short name T146
Test name
Test status
Simulation time 79527278 ps
CPU time 1.15 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 218932 kb
Host smart-eeff2e65-6c28-43b1-b723-55bcd3b00eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432496107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1432496107
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.707762319
Short name T807
Test name
Test status
Simulation time 138789320 ps
CPU time 1.95 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 219984 kb
Host smart-0ac955fd-23e4-4728-84b7-c98662f7842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707762319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.707762319
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3487490441
Short name T127
Test name
Test status
Simulation time 50212780 ps
CPU time 1.24 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 218828 kb
Host smart-11b40d69-d436-4788-89e3-9a2b2cb9b017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487490441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3487490441
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4234042878
Short name T554
Test name
Test status
Simulation time 47400316 ps
CPU time 0.9 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 215368 kb
Host smart-35ccd91b-29ab-4ba6-adfa-9245b5ea764a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234042878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4234042878
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3495333852
Short name T968
Test name
Test status
Simulation time 106012820 ps
CPU time 1.09 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 220268 kb
Host smart-31164e0b-4bc2-4426-86f3-defdf3faa39e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495333852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3495333852
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2599691672
Short name T60
Test name
Test status
Simulation time 20133949 ps
CPU time 1.17 seconds
Started Jul 09 05:44:48 PM PDT 24
Finished Jul 09 05:44:50 PM PDT 24
Peak memory 224248 kb
Host smart-c783ab08-b0bd-42c9-82d4-2d1fa47dec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599691672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2599691672
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1225299433
Short name T429
Test name
Test status
Simulation time 48058245 ps
CPU time 1.54 seconds
Started Jul 09 05:45:08 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 218756 kb
Host smart-f6d54a51-8afb-4818-8770-9765e3787f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225299433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1225299433
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1805926207
Short name T36
Test name
Test status
Simulation time 39962690 ps
CPU time 0.81 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:50 PM PDT 24
Peak memory 215904 kb
Host smart-019719f8-a3ac-4ed6-973d-ae834655e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805926207 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1805926207
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3025790469
Short name T835
Test name
Test status
Simulation time 40733291 ps
CPU time 0.85 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 215616 kb
Host smart-b066a384-2965-4060-8479-bd6402fc5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025790469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3025790469
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.341610390
Short name T964
Test name
Test status
Simulation time 1196236952 ps
CPU time 2.97 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 215572 kb
Host smart-daea1fbc-5416-480c-ba1b-c77792c4abd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341610390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.341610390
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4037016917
Short name T657
Test name
Test status
Simulation time 147584098551 ps
CPU time 933.83 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 06:00:27 PM PDT 24
Peak memory 222236 kb
Host smart-7d2e2c39-6cd0-4d0d-a954-e716bca3c64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037016917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4037016917
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2857781118
Short name T775
Test name
Test status
Simulation time 27757660 ps
CPU time 1.18 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 219772 kb
Host smart-2d8be128-ed10-44f4-8b6b-b70b140e96ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857781118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2857781118
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2988651191
Short name T674
Test name
Test status
Simulation time 54230208 ps
CPU time 1.11 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217520 kb
Host smart-4b583378-43ae-4064-ac3d-eae6bf37a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988651191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2988651191
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.672267091
Short name T173
Test name
Test status
Simulation time 91225907 ps
CPU time 1.19 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 221060 kb
Host smart-7dc41977-ac3a-4993-b573-356a95fa516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672267091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.672267091
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2930914240
Short name T477
Test name
Test status
Simulation time 101345999 ps
CPU time 2.28 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220516 kb
Host smart-16e80191-b1f8-4866-a249-2f582ef3e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930914240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2930914240
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3034100549
Short name T523
Test name
Test status
Simulation time 76524986 ps
CPU time 1.21 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 218888 kb
Host smart-c18aff1c-7d96-4a3e-a5a6-39345eee3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034100549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3034100549
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3143072202
Short name T573
Test name
Test status
Simulation time 82225457 ps
CPU time 0.99 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 217660 kb
Host smart-63108abe-4160-4068-99fe-027551bc5e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143072202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3143072202
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2564994452
Short name T491
Test name
Test status
Simulation time 409440845 ps
CPU time 1.46 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 220384 kb
Host smart-3ae66265-8f2a-4d54-81ca-fd9772aa3a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564994452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2564994452
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.527402244
Short name T493
Test name
Test status
Simulation time 206309430 ps
CPU time 2.77 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:12 PM PDT 24
Peak memory 220476 kb
Host smart-f61401a2-7f64-4d05-bc3e-d2664caf686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527402244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.527402244
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2418173048
Short name T311
Test name
Test status
Simulation time 64687755 ps
CPU time 1.67 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218844 kb
Host smart-3872bfa6-02c7-4018-9ede-41c946d77107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418173048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2418173048
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3807049696
Short name T401
Test name
Test status
Simulation time 134457510 ps
CPU time 1.12 seconds
Started Jul 09 05:46:29 PM PDT 24
Finished Jul 09 05:46:31 PM PDT 24
Peak memory 217356 kb
Host smart-0d0e2044-df71-4c20-8b9f-4efafe0d53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807049696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3807049696
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1462575077
Short name T136
Test name
Test status
Simulation time 42194730 ps
CPU time 1.17 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 219904 kb
Host smart-250f592b-5fde-44c3-bb6f-c9698f37050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462575077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1462575077
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.797978707
Short name T800
Test name
Test status
Simulation time 26853216 ps
CPU time 1.23 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 220088 kb
Host smart-5b060d0a-b04e-4546-bdaf-4e0c88cd2f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797978707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.797978707
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3682850340
Short name T48
Test name
Test status
Simulation time 30158721 ps
CPU time 1.29 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220196 kb
Host smart-9f308e1a-73ef-4885-960e-593283fde6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682850340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3682850340
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3696719928
Short name T955
Test name
Test status
Simulation time 24373711 ps
CPU time 1.19 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 220224 kb
Host smart-0186f46d-eda7-46f9-b329-f3891e192182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696719928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3696719928
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2119611380
Short name T539
Test name
Test status
Simulation time 40457607 ps
CPU time 1.15 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 218844 kb
Host smart-f2940c9d-a3c7-4fab-acff-c0b31e906561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119611380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2119611380
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4211329941
Short name T844
Test name
Test status
Simulation time 32286006 ps
CPU time 1.2 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 219064 kb
Host smart-667c505e-9a27-4eee-b2a8-fa4897b0b10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211329941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4211329941
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.862836659
Short name T326
Test name
Test status
Simulation time 49578117 ps
CPU time 1.22 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 219724 kb
Host smart-4fe031b0-5070-48e5-9224-0fb781e86a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862836659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.862836659
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4230482285
Short name T412
Test name
Test status
Simulation time 59571533 ps
CPU time 1.28 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 220524 kb
Host smart-e30b03a0-694d-4f46-bac1-780a1a943e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230482285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4230482285
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.786603172
Short name T510
Test name
Test status
Simulation time 55430336 ps
CPU time 1.04 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 217184 kb
Host smart-0624fafd-3fda-4ded-8ea0-e9d4ee6a83c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786603172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.786603172
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2054049725
Short name T501
Test name
Test status
Simulation time 22474563 ps
CPU time 0.94 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 218924 kb
Host smart-36da86b5-5115-4b62-8669-b8f72a70238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054049725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2054049725
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.44624542
Short name T334
Test name
Test status
Simulation time 141418897 ps
CPU time 3.22 seconds
Started Jul 09 05:44:53 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 220500 kb
Host smart-7ca4c198-6918-41e1-99dc-0d4501197e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44624542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.44624542
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1150139547
Short name T840
Test name
Test status
Simulation time 25619543 ps
CPU time 0.93 seconds
Started Jul 09 05:44:48 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 216204 kb
Host smart-54194e99-c1fe-4b47-88de-c46e875a7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150139547 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1150139547
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.996812796
Short name T543
Test name
Test status
Simulation time 16824787 ps
CPU time 0.93 seconds
Started Jul 09 05:44:53 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 215584 kb
Host smart-0cb25bae-dfbf-4fd8-81f9-3a66daeb081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996812796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.996812796
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3136985822
Short name T652
Test name
Test status
Simulation time 182110915 ps
CPU time 2.32 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 217464 kb
Host smart-8e4b0689-686a-4404-b0a9-5b0cca246977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136985822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3136985822
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2639501925
Short name T228
Test name
Test status
Simulation time 89865906601 ps
CPU time 1112.23 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 06:03:28 PM PDT 24
Peak memory 224752 kb
Host smart-9036dfdf-615f-42c7-9f06-669286195ec7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639501925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2639501925
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.106384182
Short name T706
Test name
Test status
Simulation time 21314323 ps
CPU time 1.1 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 220984 kb
Host smart-2f938053-aad6-475c-97d6-500b231b3be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106384182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.106384182
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1231899897
Short name T361
Test name
Test status
Simulation time 68254893 ps
CPU time 1.62 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 219084 kb
Host smart-576b2da4-664f-41b8-91c7-6ff84cd2846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231899897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1231899897
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2948652461
Short name T300
Test name
Test status
Simulation time 176039248 ps
CPU time 1.22 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 220108 kb
Host smart-92a17e2d-b371-4d54-93a4-68a508e91058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948652461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2948652461
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3227858925
Short name T586
Test name
Test status
Simulation time 37858699 ps
CPU time 1.01 seconds
Started Jul 09 05:47:48 PM PDT 24
Finished Jul 09 05:47:50 PM PDT 24
Peak memory 217616 kb
Host smart-fe95ea8e-d0d6-4301-9c0a-59de8bf400f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227858925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3227858925
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1507916922
Short name T182
Test name
Test status
Simulation time 307855936 ps
CPU time 1.47 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 221072 kb
Host smart-b21a251a-254a-4813-abde-1a4f4cc13d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507916922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1507916922
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2119052553
Short name T537
Test name
Test status
Simulation time 149599581 ps
CPU time 1.08 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 217624 kb
Host smart-b40bb439-1ac5-40e4-8dff-a886bf75926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119052553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2119052553
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.900871056
Short name T705
Test name
Test status
Simulation time 109836182 ps
CPU time 1 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 218708 kb
Host smart-939ad586-ca2b-471f-b750-3dc0a31edc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900871056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.900871056
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.798916237
Short name T356
Test name
Test status
Simulation time 38295816 ps
CPU time 1.05 seconds
Started Jul 09 05:46:21 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 220424 kb
Host smart-ca85184d-881b-4e71-bd43-a9631b38611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798916237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.798916237
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2464607568
Short name T8
Test name
Test status
Simulation time 29040123 ps
CPU time 1.26 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219920 kb
Host smart-18bbb5e0-cc2c-43fc-9d98-56cc8a80df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464607568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2464607568
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.446157761
Short name T669
Test name
Test status
Simulation time 88328153 ps
CPU time 1.23 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 217600 kb
Host smart-7b96cb0c-6ce7-4da6-95b9-2e6d74e57736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446157761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.446157761
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.4232783173
Short name T575
Test name
Test status
Simulation time 45906122 ps
CPU time 1.18 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 219044 kb
Host smart-e8b67ad1-598d-4a4d-a646-96876389f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232783173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.4232783173
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3909042055
Short name T378
Test name
Test status
Simulation time 254099035 ps
CPU time 1.36 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 217572 kb
Host smart-39e08590-e766-4db8-8345-084a54899357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909042055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3909042055
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.610800315
Short name T970
Test name
Test status
Simulation time 196914323 ps
CPU time 1.06 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 220084 kb
Host smart-23635836-eba3-4219-b2fc-f63b1610d77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610800315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.610800315
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3363846483
Short name T91
Test name
Test status
Simulation time 36094729 ps
CPU time 1.13 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 218888 kb
Host smart-891fef09-b3f5-4e7c-83ff-3b3cc40d58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363846483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3363846483
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3265126698
Short name T72
Test name
Test status
Simulation time 69528812 ps
CPU time 1.21 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 217784 kb
Host smart-8890cb1e-fc6e-4678-87de-2b84a83c3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265126698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3265126698
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.176793313
Short name T297
Test name
Test status
Simulation time 84681821 ps
CPU time 1.13 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218768 kb
Host smart-8f5c12d8-0b87-40ba-aba0-55fbec1ce4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176793313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.176793313
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3708929644
Short name T961
Test name
Test status
Simulation time 37575018 ps
CPU time 1.28 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 218820 kb
Host smart-2851c35c-4eb2-48b4-ac92-f36691b33525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708929644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3708929644
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3689261707
Short name T607
Test name
Test status
Simulation time 47339335 ps
CPU time 1.1 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 220252 kb
Host smart-6ef31ff2-9024-4f7d-ab61-0a44d7831277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689261707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3689261707
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3904482309
Short name T459
Test name
Test status
Simulation time 51919709 ps
CPU time 1.7 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 215552 kb
Host smart-5da1efcf-4032-4600-a450-c031c86de26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904482309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3904482309
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1272898303
Short name T377
Test name
Test status
Simulation time 28644261 ps
CPU time 1.24 seconds
Started Jul 09 05:45:08 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 218980 kb
Host smart-10f39080-e4c6-4759-b9e3-216c766d1db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272898303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1272898303
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3501786474
Short name T743
Test name
Test status
Simulation time 85372796 ps
CPU time 0.82 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 206792 kb
Host smart-0991973b-6192-4c53-aeed-a52b1b36b2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501786474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3501786474
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2152025654
Short name T215
Test name
Test status
Simulation time 12153787 ps
CPU time 0.95 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 216748 kb
Host smart-9d4105da-ccf2-43dc-a9af-d1b5c65e614c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152025654 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2152025654
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.112997365
Short name T207
Test name
Test status
Simulation time 111761932 ps
CPU time 1.18 seconds
Started Jul 09 05:45:07 PM PDT 24
Finished Jul 09 05:45:09 PM PDT 24
Peak memory 217144 kb
Host smart-80d1d3f9-2918-4c9d-8f4c-4820898c247e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112997365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.112997365
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2427281388
Short name T133
Test name
Test status
Simulation time 53928145 ps
CPU time 0.86 seconds
Started Jul 09 05:45:00 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 219676 kb
Host smart-072bc806-dc1a-41b6-ae1e-42c73089e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427281388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2427281388
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.4094955222
Short name T582
Test name
Test status
Simulation time 93683050 ps
CPU time 1.38 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 219180 kb
Host smart-b9482c20-254b-4a96-8eae-5330b78004ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094955222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4094955222
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1367634482
Short name T449
Test name
Test status
Simulation time 21107549 ps
CPU time 1.07 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 215752 kb
Host smart-106f7443-41c5-43a9-a5ef-5ea690b01c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367634482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1367634482
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1818276255
Short name T432
Test name
Test status
Simulation time 19854535 ps
CPU time 1.1 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 215620 kb
Host smart-ea249ac8-338d-4c81-997f-4475acd0043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818276255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1818276255
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3419143517
Short name T111
Test name
Test status
Simulation time 109612563 ps
CPU time 2.65 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 215620 kb
Host smart-63b86b62-ac8a-44fe-9443-94ed943867bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419143517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3419143517
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.398090975
Short name T42
Test name
Test status
Simulation time 78127815257 ps
CPU time 919.12 seconds
Started Jul 09 05:45:08 PM PDT 24
Finished Jul 09 06:00:28 PM PDT 24
Peak memory 222984 kb
Host smart-d2824fae-cfcb-49a6-9081-38a4c2e01e4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398090975 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.398090975
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2860231799
Short name T178
Test name
Test status
Simulation time 78054017 ps
CPU time 1.04 seconds
Started Jul 09 05:46:20 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 219820 kb
Host smart-8bdec20d-23f5-4a49-a303-f15c44a30491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860231799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2860231799
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3040259586
Short name T974
Test name
Test status
Simulation time 49314808 ps
CPU time 1.34 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 217764 kb
Host smart-507ea626-03ed-49eb-b4c0-217b9cba752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040259586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3040259586
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3023729667
Short name T54
Test name
Test status
Simulation time 98875242 ps
CPU time 1.24 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 218832 kb
Host smart-40605a6b-beb5-44d7-bb81-9104796e2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023729667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3023729667
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2441614529
Short name T929
Test name
Test status
Simulation time 41525248 ps
CPU time 1.39 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 218772 kb
Host smart-5eccc5bf-1369-4d2f-a5c8-f5ab791ded76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441614529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2441614529
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2059856407
Short name T944
Test name
Test status
Simulation time 32483031 ps
CPU time 1.06 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 219956 kb
Host smart-12349eb6-1917-459d-aa0e-abb2440feb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059856407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2059856407
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.174681763
Short name T563
Test name
Test status
Simulation time 65028089 ps
CPU time 1.11 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 217600 kb
Host smart-12373e57-f3fc-43ec-ab4e-f80619026e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174681763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.174681763
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3413308776
Short name T819
Test name
Test status
Simulation time 38519229 ps
CPU time 1.25 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 218808 kb
Host smart-bf6e243e-ee81-447e-8eaa-2ec613d9ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413308776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3413308776
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1053611533
Short name T597
Test name
Test status
Simulation time 140754203 ps
CPU time 1.16 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 220680 kb
Host smart-28cc3ad7-4e89-407d-a8bb-a301144fe707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053611533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1053611533
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.614596977
Short name T780
Test name
Test status
Simulation time 60211318 ps
CPU time 1.03 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 217644 kb
Host smart-a91dd9f7-280c-4ee0-8b2d-97057a59d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614596977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.614596977
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3969847450
Short name T729
Test name
Test status
Simulation time 48284386 ps
CPU time 1.18 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 220104 kb
Host smart-7259cbf5-7311-4dd9-b955-d383a1ba040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969847450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3969847450
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3723543707
Short name T610
Test name
Test status
Simulation time 45731625 ps
CPU time 1.73 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 219028 kb
Host smart-f202238f-0e95-4eb3-8622-04d5e604b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723543707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3723543707
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.376298594
Short name T226
Test name
Test status
Simulation time 26490097 ps
CPU time 1.23 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219480 kb
Host smart-91dda604-2223-4196-8ce8-9bd443698779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376298594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.376298594
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1511423458
Short name T954
Test name
Test status
Simulation time 34971246 ps
CPU time 1.51 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 218956 kb
Host smart-8e00e30a-fe52-430e-88a2-03ea8a2a5e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511423458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1511423458
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1388379793
Short name T547
Test name
Test status
Simulation time 46774178 ps
CPU time 1.29 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 220104 kb
Host smart-f64213db-afaf-4b9f-af50-930b9e30a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388379793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1388379793
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.3667622590
Short name T298
Test name
Test status
Simulation time 25764066 ps
CPU time 1.21 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 220112 kb
Host smart-cc745bb5-2aa0-4d13-a3f9-15f7f436e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667622590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3667622590
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3192873842
Short name T492
Test name
Test status
Simulation time 65976041 ps
CPU time 1.22 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 217768 kb
Host smart-3075c0b3-6d60-4eaa-a916-19314939b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192873842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3192873842
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3201613688
Short name T728
Test name
Test status
Simulation time 184836062 ps
CPU time 1.26 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 219788 kb
Host smart-b14a1b28-2d17-4cb1-a6f6-435d3422e669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201613688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3201613688
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2340539484
Short name T315
Test name
Test status
Simulation time 73862551 ps
CPU time 1.16 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219260 kb
Host smart-4a6dd4d1-2c61-468d-8f7d-356fbb3ee973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340539484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2340539484
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3236917949
Short name T971
Test name
Test status
Simulation time 28024951 ps
CPU time 1.26 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 219472 kb
Host smart-8f5ae7eb-e239-43bf-9683-1bb91c370dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236917949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3236917949
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3400224231
Short name T979
Test name
Test status
Simulation time 20082423 ps
CPU time 0.98 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 207048 kb
Host smart-36594d91-60ba-42ce-ad6c-e19fea55d319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400224231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3400224231
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2077435473
Short name T895
Test name
Test status
Simulation time 34756391 ps
CPU time 0.85 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 216636 kb
Host smart-3aaf2cd5-d34e-439f-9e7d-04603fa9aff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077435473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2077435473
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3494960115
Short name T415
Test name
Test status
Simulation time 27618759 ps
CPU time 0.86 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 218704 kb
Host smart-29390422-a2a8-41b7-b236-311979cf4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494960115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3494960115
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1666404483
Short name T379
Test name
Test status
Simulation time 87721352 ps
CPU time 1.21 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 220224 kb
Host smart-89a2a9b9-b9ff-41c6-b825-3c726d3c256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666404483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1666404483
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3280538739
Short name T735
Test name
Test status
Simulation time 23436777 ps
CPU time 1.08 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 215748 kb
Host smart-dea7ed28-95ee-40b5-93b1-77415cd64c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280538739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3280538739
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3388591279
Short name T560
Test name
Test status
Simulation time 49284715 ps
CPU time 0.93 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 215608 kb
Host smart-78e6435f-4eba-4c32-bfc6-4bd6d8068f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388591279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3388591279
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3431892964
Short name T559
Test name
Test status
Simulation time 434377454 ps
CPU time 1.3 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:09 PM PDT 24
Peak memory 217596 kb
Host smart-d4218ed4-e135-4f95-809f-bbabb18be3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431892964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3431892964
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2521235684
Short name T934
Test name
Test status
Simulation time 54482790647 ps
CPU time 617 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:55:24 PM PDT 24
Peak memory 217920 kb
Host smart-d3246a15-34b3-4306-94e6-5d9757986709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521235684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2521235684
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.260403565
Short name T902
Test name
Test status
Simulation time 29668934 ps
CPU time 1.27 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 220196 kb
Host smart-1e1ce0a3-668c-4457-adc2-a040c9c7f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260403565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.260403565
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2995693488
Short name T619
Test name
Test status
Simulation time 33907862 ps
CPU time 1.25 seconds
Started Jul 09 05:46:20 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 217596 kb
Host smart-0c1f5265-b3b3-4674-ae21-310b5a685556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995693488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2995693488
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2122363583
Short name T601
Test name
Test status
Simulation time 104500858 ps
CPU time 1.28 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 220936 kb
Host smart-532e27ac-0cf2-442e-ae06-7b96caabb375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122363583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2122363583
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2582705004
Short name T481
Test name
Test status
Simulation time 78483154 ps
CPU time 1.3 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 217480 kb
Host smart-47a1afe7-e6e5-460c-908c-346ded96fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582705004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2582705004
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1191809631
Short name T751
Test name
Test status
Simulation time 24860160 ps
CPU time 1.23 seconds
Started Jul 09 05:46:33 PM PDT 24
Finished Jul 09 05:46:35 PM PDT 24
Peak memory 220536 kb
Host smart-01c71a69-cda4-4bc6-8b24-3bdadf16a6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191809631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1191809631
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1051330807
Short name T3
Test name
Test status
Simulation time 244496040 ps
CPU time 1.19 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217684 kb
Host smart-e71a409e-da22-4b8d-bd9a-d4efb43273b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051330807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1051330807
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2262289423
Short name T886
Test name
Test status
Simulation time 93123123 ps
CPU time 1.03 seconds
Started Jul 09 05:46:33 PM PDT 24
Finished Jul 09 05:46:34 PM PDT 24
Peak memory 217652 kb
Host smart-59eca5bb-c389-4081-ad47-db39331bf714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262289423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2262289423
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3774815004
Short name T870
Test name
Test status
Simulation time 101187057 ps
CPU time 1.13 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 221188 kb
Host smart-17b90727-d8cf-4fa8-874f-8369fc038d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774815004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3774815004
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2998342127
Short name T802
Test name
Test status
Simulation time 84988218 ps
CPU time 1.07 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 215560 kb
Host smart-a854a49e-8ef4-431b-b355-6e7924e2cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998342127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2998342127
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3589754252
Short name T654
Test name
Test status
Simulation time 90440435 ps
CPU time 1.17 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 216016 kb
Host smart-9ef84064-eec9-44ba-b28b-81885de9ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589754252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3589754252
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1076322879
Short name T416
Test name
Test status
Simulation time 42156320 ps
CPU time 1.21 seconds
Started Jul 09 05:46:27 PM PDT 24
Finished Jul 09 05:46:29 PM PDT 24
Peak memory 219136 kb
Host smart-870164f3-8396-4ef3-a5a8-d7a7bbb39b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076322879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1076322879
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2685551385
Short name T509
Test name
Test status
Simulation time 29554323 ps
CPU time 1.3 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:12 PM PDT 24
Peak memory 215976 kb
Host smart-4d3eb878-f218-482e-b9fe-ea6c15964e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685551385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2685551385
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3664944599
Short name T594
Test name
Test status
Simulation time 192939177 ps
CPU time 2.4 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 220396 kb
Host smart-caa384f9-5ea2-4620-8d18-0c9aa20b0d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664944599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3664944599
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.176544482
Short name T239
Test name
Test status
Simulation time 29645438 ps
CPU time 1.2 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 216012 kb
Host smart-a0b371a7-8977-4ad7-9957-c5c2c90cc7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176544482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.176544482
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.867506913
Short name T631
Test name
Test status
Simulation time 102374596 ps
CPU time 1.17 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 219672 kb
Host smart-af8ac9cb-b9be-42d3-9dcc-39151e7f6e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867506913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.867506913
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3419432874
Short name T180
Test name
Test status
Simulation time 41526105 ps
CPU time 1.15 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220048 kb
Host smart-cfc15c29-d93e-4df8-98e5-8d3d87724fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419432874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3419432874
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1512326740
Short name T853
Test name
Test status
Simulation time 72324708 ps
CPU time 1.18 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 217808 kb
Host smart-0a9ff2f3-81b9-43b6-b1dc-3480b965b4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512326740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1512326740
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1684168864
Short name T577
Test name
Test status
Simulation time 36380449 ps
CPU time 1.11 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 219848 kb
Host smart-14fd9064-0852-4eb1-8fa2-229a288489be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684168864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1684168864
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3712778940
Short name T410
Test name
Test status
Simulation time 58214171 ps
CPU time 0.95 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 207116 kb
Host smart-f2bc2e70-8805-4706-bdbe-f68062b0cfdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712778940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3712778940
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3801352753
Short name T927
Test name
Test status
Simulation time 21433913 ps
CPU time 0.87 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 215708 kb
Host smart-45966bce-a958-46eb-9124-679dd6c0f033
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801352753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3801352753
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.2612256155
Short name T465
Test name
Test status
Simulation time 22304232 ps
CPU time 0.96 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 218928 kb
Host smart-e354aa4b-d747-4271-a98b-5c3ea581b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612256155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2612256155
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.663341074
Short name T707
Test name
Test status
Simulation time 249151510 ps
CPU time 2.89 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 220280 kb
Host smart-4b9b102e-15a9-42f5-bdd7-6e53cdd75513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663341074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.663341074
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1057032129
Short name T354
Test name
Test status
Simulation time 33079550 ps
CPU time 0.97 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 215952 kb
Host smart-4ce2e14d-cada-4548-9614-95e356390925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057032129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1057032129
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.320027626
Short name T403
Test name
Test status
Simulation time 16384514 ps
CPU time 0.98 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 215588 kb
Host smart-aff09082-4a70-4974-8562-b8e5eba607f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320027626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.320027626
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.202067777
Short name T203
Test name
Test status
Simulation time 1361738430 ps
CPU time 3.28 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 217628 kb
Host smart-23506eba-a57b-4955-a1f8-e9883fd29d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202067777 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.202067777
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.703568979
Short name T232
Test name
Test status
Simulation time 106853067510 ps
CPU time 585.98 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:54:43 PM PDT 24
Peak memory 219800 kb
Host smart-34f37038-d33f-4249-9a5b-10b0569f34ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703568979 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.703568979
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3440127738
Short name T246
Test name
Test status
Simulation time 236222408 ps
CPU time 1.32 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 219012 kb
Host smart-08394d49-17a8-46c2-abf3-4921ffde5390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440127738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3440127738
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3930535447
Short name T484
Test name
Test status
Simulation time 248938512 ps
CPU time 1.09 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 217676 kb
Host smart-a1316bf9-950b-4cf5-8765-55fbc340547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930535447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3930535447
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1742803238
Short name T992
Test name
Test status
Simulation time 37781850 ps
CPU time 1.05 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 220216 kb
Host smart-7dbaa5b2-fa92-4e47-9da2-cad51b7513f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742803238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1742803238
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3376732967
Short name T423
Test name
Test status
Simulation time 48759040 ps
CPU time 1.19 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217596 kb
Host smart-14f28f89-5795-479a-9d8d-0f357328e336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376732967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3376732967
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2996649308
Short name T524
Test name
Test status
Simulation time 42962781 ps
CPU time 1.42 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 219056 kb
Host smart-c6739fec-7788-4f3a-809e-5e03f06f8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996649308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2996649308
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2973682060
Short name T145
Test name
Test status
Simulation time 48418935 ps
CPU time 1.18 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 219520 kb
Host smart-c35e8ac7-e7a7-4fe8-bce6-491dcdda5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973682060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2973682060
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3509851821
Short name T499
Test name
Test status
Simulation time 35447521 ps
CPU time 1.31 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 217612 kb
Host smart-58468b50-82f2-4d80-ad00-b1e0894adb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509851821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3509851821
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1919822475
Short name T857
Test name
Test status
Simulation time 38999870 ps
CPU time 1.15 seconds
Started Jul 09 05:46:21 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 221036 kb
Host smart-87e33904-c0b6-4e46-be83-023e2b1e3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919822475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1919822475
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3289128215
Short name T328
Test name
Test status
Simulation time 36849746 ps
CPU time 1.05 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 217480 kb
Host smart-3e188e26-036d-4962-b06e-0308d5103cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289128215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3289128215
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4197614738
Short name T153
Test name
Test status
Simulation time 46932712 ps
CPU time 1.16 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 220072 kb
Host smart-ed03a415-ed7e-47dd-91e9-047055792614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197614738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4197614738
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1883369808
Short name T22
Test name
Test status
Simulation time 325455510 ps
CPU time 3.01 seconds
Started Jul 09 05:46:54 PM PDT 24
Finished Jul 09 05:46:58 PM PDT 24
Peak memory 217964 kb
Host smart-bf1fca47-8338-4414-a906-820843a15f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883369808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1883369808
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3568947512
Short name T393
Test name
Test status
Simulation time 43865742 ps
CPU time 1.14 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 220164 kb
Host smart-87378a4a-3869-4a50-89e0-3c94168676c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568947512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3568947512
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3752478088
Short name T471
Test name
Test status
Simulation time 21957127 ps
CPU time 1.18 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 217940 kb
Host smart-e74b3833-5192-4e67-9d68-c17fa57da7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752478088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3752478088
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3215628475
Short name T462
Test name
Test status
Simulation time 28353395 ps
CPU time 1.16 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 215804 kb
Host smart-bacb1286-7081-45ab-9238-53ef64bea21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215628475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3215628475
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.807976980
Short name T398
Test name
Test status
Simulation time 75475971 ps
CPU time 1.12 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 218892 kb
Host smart-f3588331-519a-4359-976c-25ade4899ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807976980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.807976980
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1205741926
Short name T112
Test name
Test status
Simulation time 26013011 ps
CPU time 1.25 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 219880 kb
Host smart-6048d43d-2e4b-4de0-9be4-8ceda8b5ace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205741926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1205741926
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1318870468
Short name T404
Test name
Test status
Simulation time 128927025 ps
CPU time 1.1 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 217536 kb
Host smart-7e69c6aa-6ab0-4c0c-9b77-5e412a7b6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318870468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1318870468
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3931043704
Short name T863
Test name
Test status
Simulation time 34217075 ps
CPU time 1.28 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 221560 kb
Host smart-4ba066f0-dcb8-4680-834b-223e833d7e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931043704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3931043704
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3681723192
Short name T892
Test name
Test status
Simulation time 36433444 ps
CPU time 1.35 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218848 kb
Host smart-e267ff8b-b7a0-43ac-8893-b38fef86466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681723192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3681723192
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.508426582
Short name T528
Test name
Test status
Simulation time 84403680 ps
CPU time 1.16 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 219944 kb
Host smart-971adbf7-2893-4745-ba3e-086b4c48832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508426582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.508426582
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.218117428
Short name T440
Test name
Test status
Simulation time 14855190 ps
CPU time 0.91 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 207032 kb
Host smart-a53c7401-b2c0-4e61-a414-1d34ad6db8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218117428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.218117428
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1020488446
Short name T914
Test name
Test status
Simulation time 38874453 ps
CPU time 0.81 seconds
Started Jul 09 05:44:25 PM PDT 24
Finished Jul 09 05:44:28 PM PDT 24
Peak memory 216260 kb
Host smart-d38bff0a-5359-4890-bb0e-5b5936adb332
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020488446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1020488446
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.895793117
Short name T500
Test name
Test status
Simulation time 144362958 ps
CPU time 1.14 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 218932 kb
Host smart-9077f2a1-a35e-4386-937b-a62ed61c3b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895793117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.895793117
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4057822190
Short name T785
Test name
Test status
Simulation time 20303008 ps
CPU time 1.06 seconds
Started Jul 09 05:44:20 PM PDT 24
Finished Jul 09 05:44:23 PM PDT 24
Peak memory 220056 kb
Host smart-21c6399e-5501-47de-bd52-cc162d8a9d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057822190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4057822190
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.329449802
Short name T784
Test name
Test status
Simulation time 44178064 ps
CPU time 1.5 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 217248 kb
Host smart-71a1054a-30b4-4315-b7dd-0ed9a26e75b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329449802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.329449802
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2356747396
Short name T958
Test name
Test status
Simulation time 23388879 ps
CPU time 0.9 seconds
Started Jul 09 05:44:22 PM PDT 24
Finished Jul 09 05:44:25 PM PDT 24
Peak memory 216108 kb
Host smart-579aa036-642d-4ae7-a48a-c1c5dcc3c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356747396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2356747396
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2771952059
Short name T70
Test name
Test status
Simulation time 907372835 ps
CPU time 4 seconds
Started Jul 09 05:44:23 PM PDT 24
Finished Jul 09 05:44:30 PM PDT 24
Peak memory 235736 kb
Host smart-b244d78b-93e7-45a7-adeb-dd564c906571
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771952059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2771952059
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.833174172
Short name T389
Test name
Test status
Simulation time 101633690 ps
CPU time 0.92 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 215572 kb
Host smart-ee52bc69-60ed-43bb-bfa7-6d0be4caf530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833174172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.833174172
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4049643866
Short name T667
Test name
Test status
Simulation time 768914415 ps
CPU time 3.33 seconds
Started Jul 09 05:44:23 PM PDT 24
Finished Jul 09 05:44:29 PM PDT 24
Peak memory 215704 kb
Host smart-b5ddfea3-5f6c-40a9-a482-2449613abe4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049643866 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4049643866
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2011947097
Short name T931
Test name
Test status
Simulation time 58634429351 ps
CPU time 275.86 seconds
Started Jul 09 05:44:24 PM PDT 24
Finished Jul 09 05:49:03 PM PDT 24
Peak memory 219284 kb
Host smart-28edbc51-92d9-4edf-9ec5-d0171beebaa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011947097 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2011947097
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.905843766
Short name T806
Test name
Test status
Simulation time 28692073 ps
CPU time 1.26 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 219040 kb
Host smart-2ae28c42-0891-4632-835b-d621abfb9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905843766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.905843766
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2490441157
Short name T829
Test name
Test status
Simulation time 17414392 ps
CPU time 0.94 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:13 PM PDT 24
Peak memory 206980 kb
Host smart-d076af67-2ada-4312-8a09-46feb0b28a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490441157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2490441157
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4028627502
Short name T900
Test name
Test status
Simulation time 18997703 ps
CPU time 0.85 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 215712 kb
Host smart-0cb45a8f-8ef0-488b-9141-118a363b1351
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028627502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4028627502
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1085197449
Short name T216
Test name
Test status
Simulation time 19890885 ps
CPU time 1.06 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:12 PM PDT 24
Peak memory 218772 kb
Host smart-96c567ba-4ea8-45db-9098-fdd83c12844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085197449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1085197449
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3105509076
Short name T875
Test name
Test status
Simulation time 42640171 ps
CPU time 1.53 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 220316 kb
Host smart-e7d327c3-0977-4bc0-8a29-aeb3999a5d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105509076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3105509076
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2435531995
Short name T100
Test name
Test status
Simulation time 22427613 ps
CPU time 1.03 seconds
Started Jul 09 05:44:57 PM PDT 24
Finished Jul 09 05:44:59 PM PDT 24
Peak memory 216164 kb
Host smart-581132b9-bf6e-489f-b6d9-5d760f443754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435531995 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2435531995
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2414493264
Short name T984
Test name
Test status
Simulation time 17906358 ps
CPU time 0.98 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 215600 kb
Host smart-b963de89-ba56-4170-bd45-06bbf765f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414493264 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2414493264
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3630859164
Short name T672
Test name
Test status
Simulation time 138759120 ps
CPU time 1.49 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 217524 kb
Host smart-fc9ef8b8-dada-48a0-9c5f-528e9e2239d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630859164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3630859164
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2148191756
Short name T595
Test name
Test status
Simulation time 16341769264 ps
CPU time 355.69 seconds
Started Jul 09 05:45:07 PM PDT 24
Finished Jul 09 05:51:04 PM PDT 24
Peak memory 217440 kb
Host smart-c4971bd8-fd79-45ea-81eb-e39fc402195e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148191756 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2148191756
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2590250736
Short name T572
Test name
Test status
Simulation time 39095595 ps
CPU time 1.27 seconds
Started Jul 09 05:46:24 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 220192 kb
Host smart-7d52794c-e3bc-4c3f-b650-f8472850024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590250736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2590250736
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.411089216
Short name T482
Test name
Test status
Simulation time 52602766 ps
CPU time 1.08 seconds
Started Jul 09 05:46:25 PM PDT 24
Finished Jul 09 05:46:27 PM PDT 24
Peak memory 220112 kb
Host smart-e9c6a706-b1fc-41d2-9e94-28082c7b3a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411089216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.411089216
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1439668220
Short name T68
Test name
Test status
Simulation time 38315909 ps
CPU time 1.08 seconds
Started Jul 09 05:46:26 PM PDT 24
Finished Jul 09 05:46:27 PM PDT 24
Peak memory 217584 kb
Host smart-3ccd9067-ee3e-4b84-9d72-c30b4c1c339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439668220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1439668220
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1549201086
Short name T380
Test name
Test status
Simulation time 57693130 ps
CPU time 1.76 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 218992 kb
Host smart-7ce85d5b-bbd6-43a3-a80a-a81a37e3f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549201086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1549201086
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3683229744
Short name T50
Test name
Test status
Simulation time 47172915 ps
CPU time 1.45 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:34 PM PDT 24
Peak memory 218796 kb
Host smart-cafc242e-88a3-436c-930b-0278e6850ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683229744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3683229744
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.11130981
Short name T382
Test name
Test status
Simulation time 45092995 ps
CPU time 1.2 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 220188 kb
Host smart-ad75da36-fc90-40db-9398-f13cffbea147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11130981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.11130981
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3566137238
Short name T347
Test name
Test status
Simulation time 58052635 ps
CPU time 1.17 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 218852 kb
Host smart-c857f169-2cde-41e6-8bf1-669c6f8bd5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566137238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3566137238
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2730329963
Short name T969
Test name
Test status
Simulation time 38910889 ps
CPU time 1.28 seconds
Started Jul 09 05:46:22 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 217764 kb
Host smart-8d369a4a-d1d4-4316-af58-ec6f5a2a887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730329963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2730329963
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1304985638
Short name T496
Test name
Test status
Simulation time 34800646 ps
CPU time 1.19 seconds
Started Jul 09 05:46:29 PM PDT 24
Finished Jul 09 05:46:31 PM PDT 24
Peak memory 219828 kb
Host smart-70ac4a03-9f5a-456c-9908-e378ee89055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304985638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1304985638
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2128855247
Short name T698
Test name
Test status
Simulation time 106402522 ps
CPU time 1.05 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 219228 kb
Host smart-1d1bc430-693c-40f6-bff3-264c2b150e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128855247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2128855247
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2741524413
Short name T385
Test name
Test status
Simulation time 19379663 ps
CPU time 0.94 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 215408 kb
Host smart-93621632-d3c6-4bdf-82bc-0bee37618c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741524413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2741524413
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1513297284
Short name T565
Test name
Test status
Simulation time 30910573 ps
CPU time 0.8 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 216512 kb
Host smart-dad4720d-2042-426c-8e12-067287425a0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513297284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1513297284
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2725912860
Short name T882
Test name
Test status
Simulation time 45921439 ps
CPU time 1.42 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 217252 kb
Host smart-14706798-c4a7-4ff5-8117-4de5e82adb25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725912860 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2725912860
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.737352791
Short name T585
Test name
Test status
Simulation time 45991102 ps
CPU time 0.84 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 218472 kb
Host smart-315175cc-7040-4fef-9ccf-a284b2db6268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737352791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.737352791
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.956595255
Short name T624
Test name
Test status
Simulation time 353294421 ps
CPU time 2.91 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:13 PM PDT 24
Peak memory 220608 kb
Host smart-fcd1f9de-6193-4adf-a4cc-a755d057946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956595255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.956595255
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1465550249
Short name T642
Test name
Test status
Simulation time 28094642 ps
CPU time 0.96 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 215852 kb
Host smart-baedf9e3-2ab2-420e-ba65-d226fac43196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465550249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1465550249
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2407521716
Short name T461
Test name
Test status
Simulation time 19509315 ps
CPU time 1.04 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 215604 kb
Host smart-d0d1aa47-0351-49f8-804c-77721df41b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407521716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2407521716
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3636796813
Short name T66
Test name
Test status
Simulation time 3088467892 ps
CPU time 3.81 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 217892 kb
Host smart-55f8438f-835f-46f0-bc58-10169c24ade9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636796813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3636796813
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1574485473
Short name T237
Test name
Test status
Simulation time 57017300464 ps
CPU time 1216.48 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 06:05:26 PM PDT 24
Peak memory 221632 kb
Host smart-d27c7a96-b060-4f32-b798-5991f26d4e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574485473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1574485473
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2248395279
Short name T322
Test name
Test status
Simulation time 38877055 ps
CPU time 1.37 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 219996 kb
Host smart-171bfc74-38a7-4f72-a27a-ec11742b20c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248395279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2248395279
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4049435577
Short name T980
Test name
Test status
Simulation time 190569818 ps
CPU time 1.08 seconds
Started Jul 09 05:46:20 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 217636 kb
Host smart-675d3506-b07e-4ebf-91c7-3cd62e922709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049435577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4049435577
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3260028361
Short name T494
Test name
Test status
Simulation time 122851603 ps
CPU time 1.08 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 217768 kb
Host smart-631c9a07-c56b-4fa1-bf90-176ef433169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260028361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3260028361
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3965424213
Short name T600
Test name
Test status
Simulation time 196234377 ps
CPU time 2.2 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 220640 kb
Host smart-374373e9-c482-46bc-b2c1-cbf5295c14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965424213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3965424213
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2427273052
Short name T320
Test name
Test status
Simulation time 49465653 ps
CPU time 1.74 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218704 kb
Host smart-feedd8d5-9fb0-4c8a-9a2e-b54dc41616ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427273052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2427273052
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3598445446
Short name T626
Test name
Test status
Simulation time 52577783 ps
CPU time 1.69 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 218884 kb
Host smart-09f55584-9d9f-415b-88f6-3ce8a8dcc5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598445446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3598445446
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.530611070
Short name T605
Test name
Test status
Simulation time 159123505 ps
CPU time 1.17 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 220316 kb
Host smart-2664d5ae-7dce-45ee-8562-edde8ecdbba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530611070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.530611070
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.250669383
Short name T338
Test name
Test status
Simulation time 68998523 ps
CPU time 1.01 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 217624 kb
Host smart-4f0f3d99-a995-4eaa-969a-903a597e69ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250669383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.250669383
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1293754466
Short name T371
Test name
Test status
Simulation time 41344252 ps
CPU time 1.33 seconds
Started Jul 09 05:46:26 PM PDT 24
Finished Jul 09 05:46:28 PM PDT 24
Peak memory 217284 kb
Host smart-fbfe6917-658b-4815-9ad3-c5049a06ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293754466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1293754466
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.777996232
Short name T339
Test name
Test status
Simulation time 25570162 ps
CPU time 1.16 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 218996 kb
Host smart-2c3ca979-4207-474d-9f44-78644c19392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777996232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.777996232
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1826166582
Short name T126
Test name
Test status
Simulation time 38696939 ps
CPU time 1.13 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 219520 kb
Host smart-18176547-89cb-4a46-bfca-a34852e3f7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826166582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1826166582
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3755154943
Short name T82
Test name
Test status
Simulation time 53750831 ps
CPU time 0.88 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:15 PM PDT 24
Peak memory 207028 kb
Host smart-51ae293e-f114-4154-9a04-c4945fbac4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755154943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3755154943
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.663744149
Short name T169
Test name
Test status
Simulation time 13799862 ps
CPU time 0.91 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 216768 kb
Host smart-38dd09fd-262f-41d6-bdcc-f5585c7cd56c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663744149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.663744149
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2742358649
Short name T786
Test name
Test status
Simulation time 53621076 ps
CPU time 1.13 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 219852 kb
Host smart-edb45189-7a81-41c4-bd8b-be93a4c5707f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742358649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2742358649
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1215940042
Short name T164
Test name
Test status
Simulation time 31808349 ps
CPU time 0.84 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 218560 kb
Host smart-51cb860b-048c-474f-afe6-efa021865f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215940042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1215940042
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1950532105
Short name T793
Test name
Test status
Simulation time 97744095 ps
CPU time 3.22 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 217852 kb
Host smart-e1b9e80b-fbff-4abd-8799-23bb1c43fa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950532105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1950532105
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.54955562
Short name T555
Test name
Test status
Simulation time 61351507 ps
CPU time 0.85 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 215520 kb
Host smart-32a71083-01ec-49e1-a506-1b226af3f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54955562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.54955562
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2558350802
Short name T395
Test name
Test status
Simulation time 16492985 ps
CPU time 1.01 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 215600 kb
Host smart-52226dd5-8761-4a9d-bf57-d8d078d1ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558350802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2558350802
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2720685429
Short name T930
Test name
Test status
Simulation time 96440074 ps
CPU time 2.48 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 217456 kb
Host smart-53d6de93-7098-4222-9429-38a4d8bc90b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720685429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2720685429
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.806085422
Short name T762
Test name
Test status
Simulation time 113196451488 ps
CPU time 2037.89 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 06:19:19 PM PDT 24
Peak memory 226604 kb
Host smart-0537ba7d-32b2-41b6-bb70-9f3fd3b530ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806085422 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.806085422
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2474368456
Short name T324
Test name
Test status
Simulation time 34874275 ps
CPU time 1.34 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218580 kb
Host smart-9319a1df-fc76-4ab3-953b-0260457ecdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474368456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2474368456
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4017588940
Short name T369
Test name
Test status
Simulation time 166997417 ps
CPU time 2.32 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 220472 kb
Host smart-df0c3536-aca9-4e18-913a-abcdc5acd590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017588940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4017588940
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.313342946
Short name T355
Test name
Test status
Simulation time 185752171 ps
CPU time 1.85 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 218088 kb
Host smart-fea664df-45e4-4c8c-a159-58772544c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313342946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.313342946
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3667818074
Short name T331
Test name
Test status
Simulation time 67001963 ps
CPU time 1.49 seconds
Started Jul 09 05:46:22 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 218800 kb
Host smart-6df7dd1d-7d38-4a47-a583-074440ff7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667818074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3667818074
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1458785197
Short name T309
Test name
Test status
Simulation time 59384778 ps
CPU time 1.11 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:15 PM PDT 24
Peak memory 217752 kb
Host smart-a713caa0-9a7d-402e-9250-aa0db12b9332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458785197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1458785197
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3167291558
Short name T922
Test name
Test status
Simulation time 79651097 ps
CPU time 1.16 seconds
Started Jul 09 05:46:13 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 219580 kb
Host smart-e118dea8-e20a-4648-a64c-5bdb73bdfa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167291558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3167291558
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1873026919
Short name T303
Test name
Test status
Simulation time 55646192 ps
CPU time 1.32 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:25 PM PDT 24
Peak memory 220480 kb
Host smart-c0caecb8-c823-4aa4-85d5-bf2b3067f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873026919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1873026919
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.955358333
Short name T864
Test name
Test status
Simulation time 56498337 ps
CPU time 1.22 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 217536 kb
Host smart-92d95f3a-4029-418e-8f0a-b64374481239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955358333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.955358333
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3309521392
Short name T280
Test name
Test status
Simulation time 41014156 ps
CPU time 1.68 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 218864 kb
Host smart-8bdc33e6-d45c-44a8-9903-6d2eb1e7cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309521392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3309521392
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2298603423
Short name T777
Test name
Test status
Simulation time 86232860 ps
CPU time 1.22 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 219220 kb
Host smart-3ff75715-79f4-4489-a5e3-66b009d5ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298603423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2298603423
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3986848629
Short name T374
Test name
Test status
Simulation time 53402382 ps
CPU time 0.9 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 207060 kb
Host smart-a97d7734-f5b0-4791-88af-e84815985d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986848629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3986848629
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2169862751
Short name T719
Test name
Test status
Simulation time 55787114 ps
CPU time 1.14 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 217136 kb
Host smart-389e9b05-28ae-45c1-b652-021c26f2ca40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169862751 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2169862751
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1589544250
Short name T730
Test name
Test status
Simulation time 20483974 ps
CPU time 1.2 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 229796 kb
Host smart-f8eba740-888d-4b41-a14d-5f45a1235fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589544250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1589544250
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.190198627
Short name T993
Test name
Test status
Simulation time 37180200 ps
CPU time 1.42 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 215584 kb
Host smart-7ba825fe-d29b-4a35-b8b1-85b00b6e3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190198627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.190198627
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3939448686
Short name T34
Test name
Test status
Simulation time 30531155 ps
CPU time 0.85 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 215904 kb
Host smart-ce46a592-beea-46dd-b0ca-a03ecc5ec3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939448686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3939448686
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3150298517
Short name T694
Test name
Test status
Simulation time 73843875 ps
CPU time 0.94 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 215620 kb
Host smart-533bd7df-3b20-450a-8f05-2bbb6a0dd9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150298517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3150298517
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2447580301
Short name T276
Test name
Test status
Simulation time 192423973 ps
CPU time 3.95 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 215616 kb
Host smart-45969fad-802e-4f3c-b6fa-7135fa247777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447580301 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2447580301
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1827578066
Short name T233
Test name
Test status
Simulation time 303068468189 ps
CPU time 1668.57 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 06:12:56 PM PDT 24
Peak memory 224196 kb
Host smart-944344f6-2bed-4244-8b02-4b4ad54a2629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827578066 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1827578066
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.431131831
Short name T24
Test name
Test status
Simulation time 43766415 ps
CPU time 1.15 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 220412 kb
Host smart-2f79d4af-fec0-40d4-ad6e-b9c490b2d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431131831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.431131831
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2869865002
Short name T318
Test name
Test status
Simulation time 94229790 ps
CPU time 1.13 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 217492 kb
Host smart-139ec7d9-03a4-4fef-80a5-7867d0649adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869865002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2869865002
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.660642866
Short name T622
Test name
Test status
Simulation time 45252029 ps
CPU time 1.39 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 218768 kb
Host smart-cc477c7e-3be6-48ca-a287-1e58579db03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660642866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.660642866
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.601645600
Short name T478
Test name
Test status
Simulation time 41042507 ps
CPU time 1.28 seconds
Started Jul 09 05:46:21 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 219072 kb
Host smart-51f88b8b-e56c-455c-a9bb-073c137aae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601645600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.601645600
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2040101502
Short name T533
Test name
Test status
Simulation time 45706017 ps
CPU time 1.13 seconds
Started Jul 09 05:46:29 PM PDT 24
Finished Jul 09 05:46:31 PM PDT 24
Peak memory 217612 kb
Host smart-49d55ef2-87f6-454c-bda8-2559f8761bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040101502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2040101502
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3797571047
Short name T414
Test name
Test status
Simulation time 23040425 ps
CPU time 1.08 seconds
Started Jul 09 05:46:28 PM PDT 24
Finished Jul 09 05:46:30 PM PDT 24
Peak memory 215892 kb
Host smart-ff228f0f-77bb-40a7-9ef4-3798e07e4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797571047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3797571047
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1178363217
Short name T832
Test name
Test status
Simulation time 102198566 ps
CPU time 0.96 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 217532 kb
Host smart-41ad0c68-7f58-4172-a907-ea4b4cb6a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178363217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1178363217
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.417032497
Short name T89
Test name
Test status
Simulation time 50181239 ps
CPU time 1.55 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 218852 kb
Host smart-7da5c033-aa0d-4b07-ac4f-59ec71af9404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417032497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.417032497
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3993230607
Short name T747
Test name
Test status
Simulation time 134944445 ps
CPU time 1.34 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 220424 kb
Host smart-eb1c3ab5-faed-4c88-97f5-f329ab8450d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993230607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3993230607
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3820059218
Short name T856
Test name
Test status
Simulation time 36777330 ps
CPU time 1.34 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 219684 kb
Host smart-1197f2ff-3023-4b88-8cab-e4d62f22fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820059218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3820059218
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3556868828
Short name T290
Test name
Test status
Simulation time 212399384 ps
CPU time 1.1 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:12 PM PDT 24
Peak memory 219364 kb
Host smart-60fb7e23-0761-4718-98a9-39b2db174549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556868828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3556868828
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4103407465
Short name T677
Test name
Test status
Simulation time 64305561 ps
CPU time 0.9 seconds
Started Jul 09 05:45:00 PM PDT 24
Finished Jul 09 05:45:01 PM PDT 24
Peak memory 215476 kb
Host smart-463bdb4e-180f-4b1d-87df-c930a5557360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103407465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4103407465
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.950925846
Short name T225
Test name
Test status
Simulation time 14135338 ps
CPU time 0.88 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 215904 kb
Host smart-cd976fab-ba0d-47a8-9ec2-bfaeb8233cca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950925846 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.950925846
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.819516728
Short name T418
Test name
Test status
Simulation time 261602071 ps
CPU time 1.14 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 217240 kb
Host smart-123827b5-a460-423d-81c1-aa5168fa6d34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819516728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.819516728
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3327953237
Short name T176
Test name
Test status
Simulation time 18515813 ps
CPU time 1.08 seconds
Started Jul 09 05:45:01 PM PDT 24
Finished Jul 09 05:45:03 PM PDT 24
Peak memory 218628 kb
Host smart-cd2d21f3-6f69-4c12-a554-012b2b0533f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327953237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3327953237
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.924824202
Short name T883
Test name
Test status
Simulation time 66189818 ps
CPU time 2.22 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 220308 kb
Host smart-82c07806-76eb-4fa8-9490-e95c4d2a7730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924824202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.924824202
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1078161853
Short name T579
Test name
Test status
Simulation time 28224549 ps
CPU time 1.04 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 224360 kb
Host smart-6a098bde-c78a-4a0a-9c7c-300f1cd06635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078161853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1078161853
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1249606335
Short name T801
Test name
Test status
Simulation time 54212628 ps
CPU time 0.94 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 215608 kb
Host smart-686402c0-ed01-4fdb-9143-3e1c84b3a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249606335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1249606335
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.27932252
Short name T825
Test name
Test status
Simulation time 950596552 ps
CPU time 4.5 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:12 PM PDT 24
Peak memory 215600 kb
Host smart-8a124548-e183-40f6-a6cb-e88b0d3ebebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27932252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.27932252
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3567215968
Short name T41
Test name
Test status
Simulation time 87820749457 ps
CPU time 489.71 seconds
Started Jul 09 05:45:07 PM PDT 24
Finished Jul 09 05:53:18 PM PDT 24
Peak memory 223980 kb
Host smart-ff21c2f3-818d-42ae-86d1-7d77c2f351d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567215968 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3567215968
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1171278921
Short name T952
Test name
Test status
Simulation time 61745902 ps
CPU time 1 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217596 kb
Host smart-af020fa2-9e21-4836-b977-5b84ef4f2191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171278921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1171278921
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.4215902854
Short name T644
Test name
Test status
Simulation time 128665346 ps
CPU time 1.33 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 219016 kb
Host smart-28123b8d-878b-43b8-b867-cd71a985f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215902854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.4215902854
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1806099310
Short name T420
Test name
Test status
Simulation time 94736825 ps
CPU time 1.19 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 217508 kb
Host smart-5e87429c-95f7-49d7-bea5-a0f90701ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806099310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1806099310
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1704762099
Short name T520
Test name
Test status
Simulation time 32262957 ps
CPU time 1.23 seconds
Started Jul 09 05:46:27 PM PDT 24
Finished Jul 09 05:46:29 PM PDT 24
Peak memory 217616 kb
Host smart-f025786d-1448-4131-a1ca-5c8e0c3e0eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704762099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1704762099
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2073477403
Short name T470
Test name
Test status
Simulation time 52270015 ps
CPU time 1.33 seconds
Started Jul 09 05:46:19 PM PDT 24
Finished Jul 09 05:46:23 PM PDT 24
Peak memory 219104 kb
Host smart-615f6d95-f63b-4a32-a7b4-1a9d2324cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073477403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2073477403
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.630250708
Short name T779
Test name
Test status
Simulation time 55910003 ps
CPU time 1.86 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:19 PM PDT 24
Peak memory 218844 kb
Host smart-839ad61e-d280-4449-9878-6a0cba56f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630250708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.630250708
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2445502292
Short name T718
Test name
Test status
Simulation time 223486632 ps
CPU time 3.44 seconds
Started Jul 09 05:46:18 PM PDT 24
Finished Jul 09 05:46:25 PM PDT 24
Peak memory 219284 kb
Host smart-a57dbedb-c03b-4350-b716-64e1215eec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445502292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2445502292
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3118075592
Short name T67
Test name
Test status
Simulation time 44754083 ps
CPU time 1.57 seconds
Started Jul 09 05:46:40 PM PDT 24
Finished Jul 09 05:46:42 PM PDT 24
Peak memory 218880 kb
Host smart-e7719732-9609-41cd-b5d2-8aea25789702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118075592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3118075592
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3608025953
Short name T505
Test name
Test status
Simulation time 546554879 ps
CPU time 4.82 seconds
Started Jul 09 05:46:15 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 220576 kb
Host smart-9130a987-0eca-42ac-bf6d-8b1ab1d729f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608025953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3608025953
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1459742569
Short name T812
Test name
Test status
Simulation time 95952784 ps
CPU time 1.26 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 217560 kb
Host smart-7ce1d2e8-c4df-41e8-8b28-3ccc8cec49b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459742569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1459742569
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3368477418
Short name T795
Test name
Test status
Simulation time 48316994 ps
CPU time 1.13 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 216024 kb
Host smart-040c2f16-14c0-4fdd-9545-fc1bb0be6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368477418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3368477418
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2174822458
Short name T546
Test name
Test status
Simulation time 92248829 ps
CPU time 1 seconds
Started Jul 09 05:45:07 PM PDT 24
Finished Jul 09 05:45:09 PM PDT 24
Peak memory 207040 kb
Host smart-0f4d2576-f3fd-489d-804f-e763325e716b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174822458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2174822458
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2380176949
Short name T221
Test name
Test status
Simulation time 15404875 ps
CPU time 0.85 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 216560 kb
Host smart-6e29da91-0b62-4a6e-ab67-9e2d21765267
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380176949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2380176949
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.3240130647
Short name T123
Test name
Test status
Simulation time 26773125 ps
CPU time 1.31 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 229840 kb
Host smart-eb187d3f-bc32-4473-9c82-644b7e896a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240130647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3240130647
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3307291372
Short name T350
Test name
Test status
Simulation time 33729171 ps
CPU time 1.11 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 217740 kb
Host smart-3b22af23-2794-4db2-8e2b-fed6d63d7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307291372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3307291372
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.203328986
Short name T517
Test name
Test status
Simulation time 21934698 ps
CPU time 1 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 215664 kb
Host smart-5bb37f10-7607-48fd-afb1-3848928af06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203328986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.203328986
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2670038672
Short name T912
Test name
Test status
Simulation time 135773990 ps
CPU time 0.97 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:07 PM PDT 24
Peak memory 215620 kb
Host smart-2bf890ac-58ce-4fcb-912c-be4cec58bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670038672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2670038672
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3866772192
Short name T739
Test name
Test status
Simulation time 339343000 ps
CPU time 6.75 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 217504 kb
Host smart-bc19b7d7-2500-4172-ab19-2fc2e14e00c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866772192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3866772192
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3627525010
Short name T234
Test name
Test status
Simulation time 141930969972 ps
CPU time 1597.9 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 06:11:54 PM PDT 24
Peak memory 225432 kb
Host smart-7ed88bd1-f72a-4932-add2-e177e7d219b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627525010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3627525010
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1248600371
Short name T655
Test name
Test status
Simulation time 170282849 ps
CPU time 1.79 seconds
Started Jul 09 05:46:35 PM PDT 24
Finished Jul 09 05:46:38 PM PDT 24
Peak memory 219644 kb
Host smart-672c8dbc-50c4-47af-9907-ea2c8eebb051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248600371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1248600371
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2661341726
Short name T671
Test name
Test status
Simulation time 39546384 ps
CPU time 1.43 seconds
Started Jul 09 05:46:46 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 218632 kb
Host smart-3d9aabae-b962-41aa-84a8-40d910b6534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661341726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2661341726
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2365849763
Short name T341
Test name
Test status
Simulation time 86556222 ps
CPU time 1.34 seconds
Started Jul 09 05:46:30 PM PDT 24
Finished Jul 09 05:46:32 PM PDT 24
Peak memory 218908 kb
Host smart-41bd4e55-8973-4c43-951a-457f9ff6d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365849763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2365849763
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2464173141
Short name T400
Test name
Test status
Simulation time 35026143 ps
CPU time 1.35 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 218972 kb
Host smart-5024182a-05b6-48ca-8337-bd840c9832a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464173141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2464173141
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3823079570
Short name T467
Test name
Test status
Simulation time 27552886 ps
CPU time 1.3 seconds
Started Jul 09 05:46:37 PM PDT 24
Finished Jul 09 05:46:39 PM PDT 24
Peak memory 218640 kb
Host smart-c89c2311-8517-4f1d-9f7f-8143364157a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823079570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3823079570
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2547452888
Short name T738
Test name
Test status
Simulation time 46103953 ps
CPU time 1.34 seconds
Started Jul 09 05:46:24 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 218816 kb
Host smart-c219f824-09ec-4728-aecb-8aa7d3a8b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547452888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2547452888
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1285526382
Short name T364
Test name
Test status
Simulation time 428684104 ps
CPU time 4.42 seconds
Started Jul 09 05:46:17 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 220512 kb
Host smart-397afdce-5c82-4e2c-a2a6-d96b25468545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285526382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1285526382
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2472669639
Short name T73
Test name
Test status
Simulation time 50324355 ps
CPU time 1.18 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:17 PM PDT 24
Peak memory 217660 kb
Host smart-d31b205e-f0f0-42b9-b06c-7af3aea0ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472669639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2472669639
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3288529444
Short name T541
Test name
Test status
Simulation time 29770360 ps
CPU time 1.28 seconds
Started Jul 09 05:46:23 PM PDT 24
Finished Jul 09 05:46:25 PM PDT 24
Peak memory 220208 kb
Host smart-804dc354-bfe8-4033-bcad-a64689b2e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288529444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3288529444
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.833915115
Short name T504
Test name
Test status
Simulation time 824907001 ps
CPU time 5.55 seconds
Started Jul 09 05:46:38 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 219884 kb
Host smart-497f8529-1759-478c-b462-b686ea4900f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833915115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.833915115
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2252828307
Short name T904
Test name
Test status
Simulation time 54428256 ps
CPU time 1.1 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 218932 kb
Host smart-2219d606-6349-481e-af71-4da338aecff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252828307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2252828307
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.132710248
Short name T455
Test name
Test status
Simulation time 13121474 ps
CPU time 0.88 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 207256 kb
Host smart-42f712ec-fc72-441c-a8b4-8b49790a7b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132710248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.132710248
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1703567404
Short name T741
Test name
Test status
Simulation time 14112484 ps
CPU time 1.1 seconds
Started Jul 09 05:45:08 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 216396 kb
Host smart-4c5d3492-c048-4692-96c6-16f34bd46f2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703567404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1703567404
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1126141823
Short name T814
Test name
Test status
Simulation time 24418541 ps
CPU time 1.17 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 217104 kb
Host smart-be7f731f-b274-4e9b-815b-085dc50cad84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126141823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1126141823
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3455477793
Short name T185
Test name
Test status
Simulation time 19707409 ps
CPU time 1.08 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 218716 kb
Host smart-e68ea46e-b26d-48f8-b2a2-f3bec7bc6595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455477793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3455477793
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2486513509
Short name T862
Test name
Test status
Simulation time 64614172 ps
CPU time 1.14 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 219220 kb
Host smart-763676e3-e44f-4789-b036-cea1b676395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486513509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2486513509
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3499252974
Short name T757
Test name
Test status
Simulation time 28432475 ps
CPU time 0.93 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 216256 kb
Host smart-1a4bc048-02b5-4706-8467-dfa903443c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499252974 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3499252974
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2871183848
Short name T352
Test name
Test status
Simulation time 17505127 ps
CPU time 0.99 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 215580 kb
Host smart-12341420-84f8-4414-8e26-10ed05f6d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871183848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2871183848
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2056269729
Short name T941
Test name
Test status
Simulation time 407695979 ps
CPU time 4.49 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:09 PM PDT 24
Peak memory 217648 kb
Host smart-08241dee-8663-4705-a21d-7ecfb115e863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056269729 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2056269729
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2794051857
Short name T722
Test name
Test status
Simulation time 21232013766 ps
CPU time 490.9 seconds
Started Jul 09 05:44:59 PM PDT 24
Finished Jul 09 05:53:11 PM PDT 24
Peak memory 224112 kb
Host smart-6d4a33c0-3e7e-4f96-a66e-4994715ca146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794051857 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2794051857
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3837135872
Short name T351
Test name
Test status
Simulation time 44629265 ps
CPU time 1.79 seconds
Started Jul 09 05:46:27 PM PDT 24
Finished Jul 09 05:46:29 PM PDT 24
Peak memory 217616 kb
Host smart-98f87e54-4fa9-4c6a-84f2-fa53e7ba4c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837135872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3837135872
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1564634355
Short name T837
Test name
Test status
Simulation time 46782526 ps
CPU time 1.74 seconds
Started Jul 09 05:46:33 PM PDT 24
Finished Jul 09 05:46:36 PM PDT 24
Peak memory 218824 kb
Host smart-1f909efd-ddfc-4fd9-8543-b864ec3fb616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564634355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1564634355
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2410708565
Short name T51
Test name
Test status
Simulation time 86808121 ps
CPU time 1.43 seconds
Started Jul 09 05:46:41 PM PDT 24
Finished Jul 09 05:46:43 PM PDT 24
Peak memory 218792 kb
Host smart-0c63cabd-6be0-4bd3-9c39-6c91f52d6b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410708565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2410708565
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4262202497
Short name T366
Test name
Test status
Simulation time 125519620 ps
CPU time 1.46 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:21 PM PDT 24
Peak memory 218936 kb
Host smart-2e874348-6dcf-4920-889b-019ca37c0060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262202497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4262202497
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2529744176
Short name T402
Test name
Test status
Simulation time 86010839 ps
CPU time 1.06 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 215616 kb
Host smart-6664d71d-00e8-4870-aef7-391fd4b8a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529744176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2529744176
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1134074052
Short name T490
Test name
Test status
Simulation time 115165484 ps
CPU time 1.22 seconds
Started Jul 09 05:46:40 PM PDT 24
Finished Jul 09 05:46:42 PM PDT 24
Peak memory 218648 kb
Host smart-619555e1-7d09-47b5-a409-c0312302190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134074052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1134074052
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2997379679
Short name T27
Test name
Test status
Simulation time 34878940 ps
CPU time 1.46 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 218740 kb
Host smart-11e1bd57-179c-4b21-a334-e6b3d873408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997379679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2997379679
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2914959236
Short name T242
Test name
Test status
Simulation time 35836620 ps
CPU time 1.33 seconds
Started Jul 09 05:46:36 PM PDT 24
Finished Jul 09 05:46:38 PM PDT 24
Peak memory 218740 kb
Host smart-49c1130a-7a8d-4019-86c5-88e0e64313cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914959236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2914959236
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1412417397
Short name T52
Test name
Test status
Simulation time 40102858 ps
CPU time 1.33 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:43 PM PDT 24
Peak memory 219932 kb
Host smart-0e9acf71-edc2-4ed1-a06e-2606e95b42f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412417397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1412417397
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1419476744
Short name T421
Test name
Test status
Simulation time 287441039 ps
CPU time 1.33 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 220372 kb
Host smart-b2ed9d14-ff84-477a-bf90-b6abfa5bf61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419476744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1419476744
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3129549361
Short name T897
Test name
Test status
Simulation time 26763771 ps
CPU time 0.92 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 207060 kb
Host smart-12736bca-61ef-415e-a79d-63a32e50ce2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129549361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3129549361
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.759053232
Short name T451
Test name
Test status
Simulation time 11007614 ps
CPU time 0.89 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 216220 kb
Host smart-569bf5cc-87ce-4c59-9611-461be5a5261e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759053232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.759053232
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3576017955
Short name T134
Test name
Test status
Simulation time 22949645 ps
CPU time 0.98 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 217112 kb
Host smart-d6d1e201-2df9-4dc1-8ae0-86043f501b81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576017955 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3576017955
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2121148190
Short name T105
Test name
Test status
Simulation time 22216738 ps
CPU time 0.89 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 218836 kb
Host smart-9cc2a165-00b9-444e-9d23-ec7b98288511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121148190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2121148190
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.300491409
Short name T809
Test name
Test status
Simulation time 123709044 ps
CPU time 1.72 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 219708 kb
Host smart-7f0ec350-458c-4575-8167-481fec630ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300491409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.300491409
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.138978081
Short name T917
Test name
Test status
Simulation time 20605944 ps
CPU time 1.07 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:15 PM PDT 24
Peak memory 215756 kb
Host smart-0a34ddd5-27de-4317-aae4-1614d2a09340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138978081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.138978081
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.163658527
Short name T390
Test name
Test status
Simulation time 42935659 ps
CPU time 0.9 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 215516 kb
Host smart-fecbd1d5-4937-4c65-8d12-6f05b72a5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163658527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.163658527
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1167325791
Short name T480
Test name
Test status
Simulation time 994342090 ps
CPU time 5.23 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 217724 kb
Host smart-935de8f5-66e1-4ffd-81ce-e7130756df9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167325791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1167325791
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3578390996
Short name T639
Test name
Test status
Simulation time 41658482507 ps
CPU time 865.91 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:59:47 PM PDT 24
Peak memory 223992 kb
Host smart-b06e94ed-2b1f-4973-aed8-a157ceedc26f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578390996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3578390996
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4070626782
Short name T335
Test name
Test status
Simulation time 284912203 ps
CPU time 3.89 seconds
Started Jul 09 05:46:51 PM PDT 24
Finished Jul 09 05:46:57 PM PDT 24
Peak memory 220376 kb
Host smart-0f90f1d0-e9c7-47d4-973d-bcc00271913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070626782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4070626782
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.980491489
Short name T487
Test name
Test status
Simulation time 41368363 ps
CPU time 1.74 seconds
Started Jul 09 05:46:12 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 218840 kb
Host smart-2f2bc44b-2591-4c30-b6a6-95777ed2350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980491489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.980491489
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3192309795
Short name T942
Test name
Test status
Simulation time 48948389 ps
CPU time 1.48 seconds
Started Jul 09 05:46:30 PM PDT 24
Finished Jul 09 05:46:32 PM PDT 24
Peak memory 218668 kb
Host smart-2a75deef-b75d-43de-b00e-891a08ed3f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192309795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3192309795
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1784676365
Short name T279
Test name
Test status
Simulation time 30438669 ps
CPU time 1.3 seconds
Started Jul 09 05:46:33 PM PDT 24
Finished Jul 09 05:46:35 PM PDT 24
Peak memory 218752 kb
Host smart-e9b4c8b6-3984-418e-a07d-7558e6f16ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784676365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1784676365
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1085107929
Short name T858
Test name
Test status
Simulation time 491936574 ps
CPU time 4.46 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:24 PM PDT 24
Peak memory 219348 kb
Host smart-6574b8e6-c71d-4a59-a90f-62556bc51537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085107929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1085107929
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3308629377
Short name T765
Test name
Test status
Simulation time 60545846 ps
CPU time 1.17 seconds
Started Jul 09 05:46:24 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 215532 kb
Host smart-551c6395-2721-436c-bbfa-f8e1e5dd1ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308629377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3308629377
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.357726270
Short name T556
Test name
Test status
Simulation time 45199073 ps
CPU time 1.22 seconds
Started Jul 09 05:46:30 PM PDT 24
Finished Jul 09 05:46:32 PM PDT 24
Peak memory 217680 kb
Host smart-5a176f7d-f369-433f-a61b-655371288b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357726270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.357726270
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3992009044
Short name T457
Test name
Test status
Simulation time 163208594 ps
CPU time 1.04 seconds
Started Jul 09 05:46:34 PM PDT 24
Finished Jul 09 05:46:35 PM PDT 24
Peak memory 217716 kb
Host smart-e248151c-105f-46e1-9e93-adcec11e70e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992009044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3992009044
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2207797278
Short name T978
Test name
Test status
Simulation time 37794470 ps
CPU time 1.32 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 219172 kb
Host smart-ccdad9df-be76-4425-84c3-4e225c8591b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207797278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2207797278
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2865885927
Short name T776
Test name
Test status
Simulation time 26799142 ps
CPU time 1.27 seconds
Started Jul 09 05:46:35 PM PDT 24
Finished Jul 09 05:46:37 PM PDT 24
Peak memory 218720 kb
Host smart-7c9094fc-186e-47cf-a50f-3e4226412f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865885927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2865885927
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3542410858
Short name T908
Test name
Test status
Simulation time 26060677 ps
CPU time 1.17 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 218740 kb
Host smart-7f2b58ec-6fd7-46fb-af19-bd7f4f05ba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542410858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3542410858
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1246229791
Short name T815
Test name
Test status
Simulation time 32307799 ps
CPU time 0.96 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 215428 kb
Host smart-e227a20d-2578-4e3f-ac48-a61a132cd627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246229791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1246229791
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2349773731
Short name T754
Test name
Test status
Simulation time 40765656 ps
CPU time 0.87 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 215708 kb
Host smart-3910061f-85cf-4978-8ec8-36f8ffc5ed1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349773731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2349773731
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1714902552
Short name T149
Test name
Test status
Simulation time 44308953 ps
CPU time 1.38 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 217284 kb
Host smart-3db13c15-b4a6-400d-930b-e49fcc062964
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714902552 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1714902552
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.104454100
Short name T602
Test name
Test status
Simulation time 28995651 ps
CPU time 0.89 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 218408 kb
Host smart-15091f17-45cb-4340-ba1d-a15f3b23c348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104454100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.104454100
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.523496664
Short name T691
Test name
Test status
Simulation time 39862734 ps
CPU time 1.49 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 218768 kb
Host smart-3148b167-957f-4635-84b5-e0ed015482f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523496664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.523496664
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.387656099
Short name T966
Test name
Test status
Simulation time 22395157 ps
CPU time 1.18 seconds
Started Jul 09 05:45:00 PM PDT 24
Finished Jul 09 05:45:02 PM PDT 24
Peak memory 224208 kb
Host smart-d12a12f6-1910-4507-8254-7fb1140fb6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387656099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.387656099
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.516298523
Short name T553
Test name
Test status
Simulation time 48322072 ps
CPU time 0.89 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 215568 kb
Host smart-1e42eea9-8e8c-4263-a783-7b78a9daafd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516298523 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.516298523
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3568000397
Short name T513
Test name
Test status
Simulation time 507111224 ps
CPU time 3 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 217532 kb
Host smart-7385e7f8-a475-4759-8e91-41744b1eb9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568000397 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3568000397
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3250851061
Short name T589
Test name
Test status
Simulation time 96512666170 ps
CPU time 517 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:53:36 PM PDT 24
Peak memory 224092 kb
Host smart-173fa6ef-7204-4620-8735-d8613a7996f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250851061 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3250851061
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1959964417
Short name T788
Test name
Test status
Simulation time 93482963 ps
CPU time 1.13 seconds
Started Jul 09 05:46:28 PM PDT 24
Finished Jul 09 05:46:30 PM PDT 24
Peak memory 218816 kb
Host smart-3f368229-0e15-46fd-b14e-48a07fa901b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959964417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1959964417
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.692447961
Short name T439
Test name
Test status
Simulation time 102426922 ps
CPU time 3.5 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:46 PM PDT 24
Peak memory 219256 kb
Host smart-c4ce868c-0fe2-45ba-b379-c24e59bc2f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692447961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.692447961
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2963171631
Short name T447
Test name
Test status
Simulation time 70672528 ps
CPU time 1.21 seconds
Started Jul 09 05:46:37 PM PDT 24
Finished Jul 09 05:46:39 PM PDT 24
Peak memory 220428 kb
Host smart-c04b6872-3d1e-40f1-bf00-c87780e5d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963171631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2963171631
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2078946267
Short name T26
Test name
Test status
Simulation time 104804884 ps
CPU time 0.99 seconds
Started Jul 09 05:46:24 PM PDT 24
Finished Jul 09 05:46:26 PM PDT 24
Peak memory 215688 kb
Host smart-3cc54503-0438-4d71-8dc0-37bcc8d70837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078946267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2078946267
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1649720845
Short name T797
Test name
Test status
Simulation time 40582337 ps
CPU time 1.15 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:51 PM PDT 24
Peak memory 218792 kb
Host smart-794c2967-cdfd-4edc-a0ab-7a644dd773d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649720845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1649720845
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1832732347
Short name T972
Test name
Test status
Simulation time 79143227 ps
CPU time 1.09 seconds
Started Jul 09 05:46:29 PM PDT 24
Finished Jul 09 05:46:31 PM PDT 24
Peak memory 217600 kb
Host smart-5d28938d-35ae-4c6d-98f1-4ca7cd4a19f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832732347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1832732347
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.349742059
Short name T768
Test name
Test status
Simulation time 56210946 ps
CPU time 1.43 seconds
Started Jul 09 05:46:28 PM PDT 24
Finished Jul 09 05:46:31 PM PDT 24
Peak memory 219336 kb
Host smart-4c46e243-1cf6-4038-bc0a-a7b1ec1cfa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349742059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.349742059
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2449079440
Short name T427
Test name
Test status
Simulation time 159396296 ps
CPU time 3.26 seconds
Started Jul 09 05:46:43 PM PDT 24
Finished Jul 09 05:46:47 PM PDT 24
Peak memory 215616 kb
Host smart-d0200487-d2aa-4264-9a21-31d9b0b07c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449079440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2449079440
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1080463519
Short name T452
Test name
Test status
Simulation time 80708963 ps
CPU time 1.11 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 218916 kb
Host smart-b6531f6e-4efc-44aa-830b-9dd3652e50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080463519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1080463519
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1753637477
Short name T139
Test name
Test status
Simulation time 45684316 ps
CPU time 1.14 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 221088 kb
Host smart-ce60aff8-153a-4f2b-95a5-2254c741ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753637477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1753637477
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.482916578
Short name T634
Test name
Test status
Simulation time 38995448 ps
CPU time 0.86 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 206852 kb
Host smart-0ea39c86-9db1-4ca7-9fb3-36f90f4aabc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482916578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.482916578
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.929076000
Short name T903
Test name
Test status
Simulation time 78151683 ps
CPU time 0.83 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 216160 kb
Host smart-d06ea4aa-e7c0-41ad-8434-48d425e8a1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929076000 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.929076000
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1138372115
Short name T962
Test name
Test status
Simulation time 60639244 ps
CPU time 1.13 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:12 PM PDT 24
Peak memory 218960 kb
Host smart-b5953756-6b27-4867-a63f-ff7a1ec0ed1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138372115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1138372115
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3657023964
Short name T599
Test name
Test status
Simulation time 31678566 ps
CPU time 1.16 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 221156 kb
Host smart-189d3a8b-8609-4e2a-b219-9bb1f2ddfc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657023964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3657023964
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3921539772
Short name T387
Test name
Test status
Simulation time 32549279 ps
CPU time 1.34 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 217760 kb
Host smart-ef0c753b-5d67-4b7f-b5cc-55e2945a8c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921539772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3921539772
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2633240109
Short name T861
Test name
Test status
Simulation time 27885808 ps
CPU time 0.86 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 215964 kb
Host smart-ca676f8a-16ef-4b46-840a-7955e5368ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633240109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2633240109
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2199993738
Short name T957
Test name
Test status
Simulation time 44841671 ps
CPU time 0.93 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:15 PM PDT 24
Peak memory 215572 kb
Host smart-1499fa47-dc34-4deb-ba9a-89044ddfd6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199993738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2199993738
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2805880804
Short name T360
Test name
Test status
Simulation time 323999937 ps
CPU time 3.68 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 217500 kb
Host smart-2147b790-9784-438e-96be-14710d31c8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805880804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2805880804
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2761766434
Short name T306
Test name
Test status
Simulation time 47447695859 ps
CPU time 1230.06 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 06:05:46 PM PDT 24
Peak memory 221812 kb
Host smart-4825a33a-83ba-4a23-adc5-a4d7c6b92f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761766434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2761766434
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4173651717
Short name T363
Test name
Test status
Simulation time 36381716 ps
CPU time 1.54 seconds
Started Jul 09 05:46:49 PM PDT 24
Finished Jul 09 05:46:52 PM PDT 24
Peak memory 218692 kb
Host smart-c5d6e8a3-2ee0-4c1c-800f-f2df4452a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173651717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4173651717
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2605598750
Short name T911
Test name
Test status
Simulation time 46157054 ps
CPU time 1.23 seconds
Started Jul 09 05:46:32 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 218908 kb
Host smart-534cc180-ad20-4304-82e1-12fbcbbbb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605598750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2605598750
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3502699212
Short name T702
Test name
Test status
Simulation time 45040063 ps
CPU time 1.57 seconds
Started Jul 09 05:46:45 PM PDT 24
Finished Jul 09 05:46:48 PM PDT 24
Peak memory 218856 kb
Host smart-51254336-8f3d-4570-8e79-59441af38e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502699212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3502699212
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2430238456
Short name T75
Test name
Test status
Simulation time 79473254 ps
CPU time 1.21 seconds
Started Jul 09 05:46:33 PM PDT 24
Finished Jul 09 05:46:35 PM PDT 24
Peak memory 217616 kb
Host smart-d46ac72d-0339-4674-81d2-74867cfa5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430238456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2430238456
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.799032883
Short name T791
Test name
Test status
Simulation time 58402395 ps
CPU time 1.3 seconds
Started Jul 09 05:46:47 PM PDT 24
Finished Jul 09 05:46:49 PM PDT 24
Peak memory 219132 kb
Host smart-a9a647a8-bb10-4ab3-8bd6-44951a65ea43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799032883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.799032883
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.567436345
Short name T317
Test name
Test status
Simulation time 60794650 ps
CPU time 1.08 seconds
Started Jul 09 05:46:42 PM PDT 24
Finished Jul 09 05:46:44 PM PDT 24
Peak memory 220268 kb
Host smart-6c3103bf-a123-450e-a66d-d271b079f3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567436345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.567436345
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1338063547
Short name T90
Test name
Test status
Simulation time 85363502 ps
CPU time 1.21 seconds
Started Jul 09 05:46:41 PM PDT 24
Finished Jul 09 05:46:43 PM PDT 24
Peak memory 219092 kb
Host smart-14917344-fd49-44e9-b2f7-8ceae6d1ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338063547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1338063547
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4230708095
Short name T497
Test name
Test status
Simulation time 46374262 ps
CPU time 1.31 seconds
Started Jul 09 05:46:31 PM PDT 24
Finished Jul 09 05:46:33 PM PDT 24
Peak memory 219720 kb
Host smart-deeae3b8-290e-48b2-affc-fed04c453354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230708095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4230708095
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2220928353
Short name T333
Test name
Test status
Simulation time 65166586 ps
CPU time 1.24 seconds
Started Jul 09 05:46:37 PM PDT 24
Finished Jul 09 05:46:38 PM PDT 24
Peak memory 219288 kb
Host smart-ef50feec-96d5-4fa4-9853-8dbb5f9e438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220928353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2220928353
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2849070522
Short name T424
Test name
Test status
Simulation time 69302996 ps
CPU time 2.47 seconds
Started Jul 09 05:46:38 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 220572 kb
Host smart-0fa5c30e-6b6d-42da-a33f-536f63174ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849070522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2849070522
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4060358008
Short name T268
Test name
Test status
Simulation time 70054159 ps
CPU time 1.02 seconds
Started Jul 09 05:44:24 PM PDT 24
Finished Jul 09 05:44:28 PM PDT 24
Peak memory 221028 kb
Host smart-58db695b-2dc0-4cd7-ad32-6ebcc9bde188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060358008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4060358008
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4182573699
Short name T55
Test name
Test status
Simulation time 30441305 ps
CPU time 0.96 seconds
Started Jul 09 05:44:36 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 215172 kb
Host smart-bd8e18f7-e66c-4570-8e84-997e0d701dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182573699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4182573699
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.560765195
Short name T157
Test name
Test status
Simulation time 14497483 ps
CPU time 0.97 seconds
Started Jul 09 05:44:31 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 215796 kb
Host smart-3a4014bb-ad15-4649-a225-fdb5ebe037e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560765195 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.560765195
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.324665836
Short name T503
Test name
Test status
Simulation time 38882631 ps
CPU time 1.33 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 217180 kb
Host smart-d355eb76-8e29-482b-93bf-3b30f132c168
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324665836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.324665836
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.133166258
Short name T147
Test name
Test status
Simulation time 51267945 ps
CPU time 1.01 seconds
Started Jul 09 05:44:31 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 220928 kb
Host smart-116117c5-2384-4ddc-a4cf-b1178c585881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133166258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.133166258
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.11478335
Short name T683
Test name
Test status
Simulation time 109684584 ps
CPU time 1.68 seconds
Started Jul 09 05:44:34 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 218976 kb
Host smart-1f5fb024-df14-474a-a48f-d6fe51b05943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11478335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.11478335
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2296853058
Short name T103
Test name
Test status
Simulation time 24822981 ps
CPU time 0.98 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 216148 kb
Host smart-0570e0d7-2031-44f5-8dff-f9561de66d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296853058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2296853058
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1288787243
Short name T869
Test name
Test status
Simulation time 36193828 ps
CPU time 0.93 seconds
Started Jul 09 05:44:22 PM PDT 24
Finished Jul 09 05:44:25 PM PDT 24
Peak memory 207420 kb
Host smart-519b5f46-ce7c-45cc-abf3-58b8978c033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288787243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1288787243
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1449614002
Short name T529
Test name
Test status
Simulation time 32768878 ps
CPU time 0.99 seconds
Started Jul 09 05:44:18 PM PDT 24
Finished Jul 09 05:44:22 PM PDT 24
Peak memory 215628 kb
Host smart-1b188491-471a-4744-8c92-da5abecbc3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449614002 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1449614002
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3767713986
Short name T468
Test name
Test status
Simulation time 246738240 ps
CPU time 2.87 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 215720 kb
Host smart-e1b0ab92-0542-410c-8e24-d1c35b88a6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767713986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3767713986
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2467671460
Short name T230
Test name
Test status
Simulation time 21312556282 ps
CPU time 476.92 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:52:27 PM PDT 24
Peak memory 218180 kb
Host smart-28596d89-8b3a-4bdf-9565-f0c5c2cff107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467671460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2467671460
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3465380954
Short name T627
Test name
Test status
Simulation time 86682997 ps
CPU time 1.24 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 218940 kb
Host smart-e8072555-ec18-4495-8b52-076dcc1a98a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465380954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3465380954
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3865611238
Short name T448
Test name
Test status
Simulation time 27318851 ps
CPU time 0.97 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 215188 kb
Host smart-6c64de24-1971-46f3-b2f6-7ba08ec2375d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865611238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3865611238
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2463566503
Short name T188
Test name
Test status
Simulation time 20217928 ps
CPU time 0.85 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 216764 kb
Host smart-41cf4097-8ed7-4211-8a29-6fe947a9ec25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463566503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2463566503
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1707842225
Short name T695
Test name
Test status
Simulation time 59026274 ps
CPU time 0.99 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 219984 kb
Host smart-6a80dc11-9f73-4d96-9141-c7420c62a0bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707842225 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1707842225
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.3808803016
Short name T650
Test name
Test status
Simulation time 45217356 ps
CPU time 1.25 seconds
Started Jul 09 05:45:33 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 218936 kb
Host smart-6b4292a9-11f4-43c6-ad1d-48c5d09eb303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808803016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3808803016
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.2279203634
Short name T526
Test name
Test status
Simulation time 15969012 ps
CPU time 0.93 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 215640 kb
Host smart-7113aa8c-4635-4b5f-9eea-b6884a703c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279203634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2279203634
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1679909450
Short name T506
Test name
Test status
Simulation time 775957688 ps
CPU time 4.6 seconds
Started Jul 09 05:45:07 PM PDT 24
Finished Jul 09 05:45:13 PM PDT 24
Peak memory 217488 kb
Host smart-9a6184df-9be2-4549-b3a7-54cd26977f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679909450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1679909450
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.475409407
Short name T536
Test name
Test status
Simulation time 226126138394 ps
CPU time 1512.88 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 06:10:27 PM PDT 24
Peak memory 225372 kb
Host smart-34912198-8033-4727-8c1f-b529967d09d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475409407 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.475409407
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3577006250
Short name T842
Test name
Test status
Simulation time 26106047 ps
CPU time 1.23 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 219976 kb
Host smart-b568bf56-99d6-43c7-b42d-ecbb603e80ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577006250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3577006250
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2795196384
Short name T81
Test name
Test status
Simulation time 19874804 ps
CPU time 0.82 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:13 PM PDT 24
Peak memory 207108 kb
Host smart-f9e764a0-44db-4d6a-90c7-cb59554bc413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795196384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2795196384
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3923691970
Short name T199
Test name
Test status
Simulation time 23536679 ps
CPU time 0.89 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 216556 kb
Host smart-a7b43966-35d3-47b4-8e20-154a1789cfbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923691970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3923691970
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3308042170
Short name T125
Test name
Test status
Simulation time 76918500 ps
CPU time 1.1 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 217280 kb
Host smart-0f2c2b92-0c46-4c26-9969-aaddbbf3defc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308042170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3308042170
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.501893094
Short name T5
Test name
Test status
Simulation time 18966583 ps
CPU time 1.05 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 218696 kb
Host smart-2fcba38b-0386-425d-a018-c27165e4ee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501893094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.501893094
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1592092669
Short name T620
Test name
Test status
Simulation time 26128998 ps
CPU time 1.29 seconds
Started Jul 09 05:45:10 PM PDT 24
Finished Jul 09 05:45:12 PM PDT 24
Peak memory 218868 kb
Host smart-4b659197-637c-4921-aa50-f6b2d81ed9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592092669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1592092669
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.357703978
Short name T766
Test name
Test status
Simulation time 33877494 ps
CPU time 0.86 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 215732 kb
Host smart-4b412449-8ce7-4b35-a9f4-f44b508c9e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357703978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.357703978
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1520428512
Short name T928
Test name
Test status
Simulation time 16665461 ps
CPU time 0.99 seconds
Started Jul 09 05:45:04 PM PDT 24
Finished Jul 09 05:45:06 PM PDT 24
Peak memory 215504 kb
Host smart-33c4f8fa-9727-4383-9f69-85abdda25c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520428512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1520428512
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1660686138
Short name T833
Test name
Test status
Simulation time 162465662 ps
CPU time 2.17 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 218716 kb
Host smart-99cb3567-0719-4547-b32e-8f82806bbee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660686138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1660686138
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1129876269
Short name T933
Test name
Test status
Simulation time 40606467433 ps
CPU time 472.76 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:53:05 PM PDT 24
Peak memory 224004 kb
Host smart-a8015feb-ab08-4a65-b62f-36896ee81989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129876269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1129876269
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2901036269
Short name T122
Test name
Test status
Simulation time 66064791 ps
CPU time 1.06 seconds
Started Jul 09 05:45:40 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 220116 kb
Host smart-5250f87a-03d4-40e2-94e9-9746e0bafd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901036269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2901036269
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1386489163
Short name T345
Test name
Test status
Simulation time 190281957 ps
CPU time 1.1 seconds
Started Jul 09 05:45:05 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 207060 kb
Host smart-53c1f8d2-b2c1-4d9c-8312-6beb2c62ff6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386489163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1386489163
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2852162192
Short name T219
Test name
Test status
Simulation time 38525957 ps
CPU time 0.82 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 216472 kb
Host smart-374fc230-2e99-43e2-b7cc-dc4ebda1c843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852162192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2852162192
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3717039815
Short name T764
Test name
Test status
Simulation time 42301191 ps
CPU time 1.33 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 219756 kb
Host smart-34ce969e-d74b-46d4-9d46-d0a157ad100c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717039815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3717039815
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1895285285
Short name T132
Test name
Test status
Simulation time 24483622 ps
CPU time 1.13 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:45:11 PM PDT 24
Peak memory 220868 kb
Host smart-f8ce4dfb-aeb1-4523-bca4-10a825164590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895285285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1895285285
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3624913544
Short name T828
Test name
Test status
Simulation time 41581592 ps
CPU time 1.25 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 217720 kb
Host smart-98928163-e824-4ecb-a88d-615b9d9c95ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624913544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3624913544
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1737940267
Short name T488
Test name
Test status
Simulation time 22937474 ps
CPU time 0.98 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 215664 kb
Host smart-7f70a9cd-9b98-4fce-92aa-5b44160b00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737940267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1737940267
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3459975962
Short name T512
Test name
Test status
Simulation time 42932834 ps
CPU time 0.88 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 215564 kb
Host smart-3fdb789c-4c71-4a09-98ba-eb130db5f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459975962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3459975962
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1355725766
Short name T615
Test name
Test status
Simulation time 810773965 ps
CPU time 5.15 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 217676 kb
Host smart-52402f83-b763-4caa-899a-4119f97a21c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355725766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1355725766
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1901520867
Short name T430
Test name
Test status
Simulation time 29652307949 ps
CPU time 752.79 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:57:45 PM PDT 24
Peak memory 224112 kb
Host smart-dc1f0744-ca68-472b-964a-5413dddff4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901520867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1901520867
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4140969253
Short name T867
Test name
Test status
Simulation time 36281613 ps
CPU time 1.24 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 220032 kb
Host smart-7e1dc1ae-b221-4804-8eea-6ffd67d90dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140969253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4140969253
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4037238755
Short name T781
Test name
Test status
Simulation time 13328353 ps
CPU time 0.9 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 206984 kb
Host smart-3f4ef2ae-7906-4f2f-81d7-8e9f13a5f64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037238755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4037238755
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.2114805656
Short name T709
Test name
Test status
Simulation time 25510865 ps
CPU time 1.13 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 224164 kb
Host smart-8ad5f8c3-b35b-46d5-a123-bb9df96ebdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114805656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2114805656
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1930810174
Short name T384
Test name
Test status
Simulation time 29910725 ps
CPU time 1.04 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 217540 kb
Host smart-5418fa28-6c5e-4158-ac21-ad1f82841731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930810174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1930810174
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_smoke.382757010
Short name T437
Test name
Test status
Simulation time 17576145 ps
CPU time 0.94 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 215616 kb
Host smart-919ee514-fed1-47b5-af3f-e1b44ceeeffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382757010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.382757010
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.358480634
Short name T240
Test name
Test status
Simulation time 1522551571 ps
CPU time 2.46 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 217736 kb
Host smart-365b16cd-563f-4363-82a7-73b5a444e744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358480634 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.358480634
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.589168220
Short name T413
Test name
Test status
Simulation time 139098741615 ps
CPU time 817.02 seconds
Started Jul 09 05:45:09 PM PDT 24
Finished Jul 09 05:58:46 PM PDT 24
Peak memory 221228 kb
Host smart-2ffbee57-6d12-41ac-9f9d-a9762f33313b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589168220 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.589168220
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.104349195
Short name T299
Test name
Test status
Simulation time 55501499 ps
CPU time 1.13 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 218972 kb
Host smart-8d1dbfc3-c30b-4731-a8d5-a4988c534371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104349195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.104349195
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3172275985
Short name T811
Test name
Test status
Simulation time 237147737 ps
CPU time 0.9 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 215220 kb
Host smart-1b3dc931-bb51-426d-9f98-99f2ed33b9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172275985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3172275985
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3674756944
Short name T989
Test name
Test status
Simulation time 28246901 ps
CPU time 0.82 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 216432 kb
Host smart-2ef152c6-7f05-4618-aa8a-4af83363f3e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674756944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3674756944
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3622873768
Short name T636
Test name
Test status
Simulation time 105419013 ps
CPU time 1.1 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 217216 kb
Host smart-4bf5c60e-bacc-4e08-b06b-248076ad4e1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622873768 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3622873768
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.127071826
Short name T129
Test name
Test status
Simulation time 28872112 ps
CPU time 0.99 seconds
Started Jul 09 05:45:12 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 219804 kb
Host smart-2a722de2-10a4-4a4a-aa46-ee58e37d0df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127071826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.127071826
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1965924711
Short name T532
Test name
Test status
Simulation time 32681638 ps
CPU time 1.36 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 218964 kb
Host smart-69f5ac07-cb1a-4689-b430-f3dec6e2c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965924711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1965924711
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3343902875
Short name T102
Test name
Test status
Simulation time 43788110 ps
CPU time 0.81 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 215824 kb
Host smart-e70d4d45-3004-496d-b7f8-227861c34c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343902875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3343902875
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1846096385
Short name T723
Test name
Test status
Simulation time 19751674 ps
CPU time 0.99 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 215596 kb
Host smart-dfd352f9-dfd0-467e-b8ee-4c132bce6abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846096385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1846096385
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4017880360
Short name T367
Test name
Test status
Simulation time 72002048 ps
CPU time 1.87 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 215540 kb
Host smart-1b2e5d37-13fd-4195-8755-b439fce5067c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017880360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4017880360
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1061640911
Short name T235
Test name
Test status
Simulation time 393257261083 ps
CPU time 560.76 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 05:54:50 PM PDT 24
Peak memory 219644 kb
Host smart-2cc4d2ec-925c-4e19-a4a4-c6fca9a6c873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061640911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1061640911
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3488328275
Short name T752
Test name
Test status
Simulation time 24521156 ps
CPU time 1.12 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 218632 kb
Host smart-8e224c0c-a6d7-4f05-96c2-94582a7909dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488328275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3488328275
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3202223571
Short name T712
Test name
Test status
Simulation time 22138529 ps
CPU time 0.86 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 215172 kb
Host smart-6948aba0-3d8f-4aa9-956e-b95fe6589d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202223571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3202223571
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2007681527
Short name T97
Test name
Test status
Simulation time 23033393 ps
CPU time 0.91 seconds
Started Jul 09 05:45:08 PM PDT 24
Finished Jul 09 05:45:10 PM PDT 24
Peak memory 216848 kb
Host smart-a849a1ab-3893-4047-830b-e52f1505893f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007681527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2007681527
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1488435841
Short name T460
Test name
Test status
Simulation time 30505620 ps
CPU time 1.01 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 217280 kb
Host smart-e6b6360f-7269-4dda-b07f-2c20a502a038
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488435841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1488435841
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.429039114
Short name T196
Test name
Test status
Simulation time 20116835 ps
CPU time 1.04 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 219744 kb
Host smart-5774ce21-d83d-4010-8fb0-6bd00efcf9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429039114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.429039114
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2461306939
Short name T538
Test name
Test status
Simulation time 47715387 ps
CPU time 1.49 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 218908 kb
Host smart-9447aa50-9e19-4e25-af8c-a229c5826119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461306939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2461306939
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2524013864
Short name T31
Test name
Test status
Simulation time 27380156 ps
CPU time 0.87 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 215884 kb
Host smart-b823e035-d6da-4c0c-980f-6b55f5c3dfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524013864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2524013864
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3024597651
Short name T688
Test name
Test status
Simulation time 94419130 ps
CPU time 0.84 seconds
Started Jul 09 05:45:06 PM PDT 24
Finished Jul 09 05:45:08 PM PDT 24
Peak memory 215608 kb
Host smart-c496e643-6424-4b78-b911-fc03c781942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024597651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3024597651
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1227559746
Short name T450
Test name
Test status
Simulation time 259475594 ps
CPU time 5.07 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 221052 kb
Host smart-e7393aad-e696-424b-9f5b-f6148c4cdf73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227559746 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1227559746
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1832820641
Short name T789
Test name
Test status
Simulation time 78513952623 ps
CPU time 1965.26 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 06:18:10 PM PDT 24
Peak memory 229080 kb
Host smart-7d91e0db-f1f3-4d52-8eb5-36c22277f693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832820641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1832820641
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2977342454
Short name T641
Test name
Test status
Simulation time 23128972 ps
CPU time 1.19 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 219656 kb
Host smart-07e55dbe-9358-4919-a7a7-c2f076b4b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977342454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2977342454
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3573662860
Short name T945
Test name
Test status
Simulation time 12368147 ps
CPU time 0.86 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 207064 kb
Host smart-47e16252-637a-43aa-8eec-45fe54698b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573662860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3573662860
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2177620950
Short name T635
Test name
Test status
Simulation time 69810354 ps
CPU time 0.86 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 216680 kb
Host smart-fcb1c96a-dd1b-49cc-8cc6-a1cc2e95c2a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177620950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2177620950
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.649575366
Short name T135
Test name
Test status
Simulation time 35586466 ps
CPU time 1.2 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 217280 kb
Host smart-458668bd-c60f-44fd-ae4a-1a3506ab063c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649575366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.649575366
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3909676516
Short name T86
Test name
Test status
Simulation time 20685532 ps
CPU time 0.91 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 218884 kb
Host smart-f70ed211-1038-47f3-ac24-fbb62e532c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909676516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3909676516
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.964903202
Short name T329
Test name
Test status
Simulation time 39406000 ps
CPU time 1.48 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 219772 kb
Host smart-a16cf276-b675-403f-bdc5-863eca8f680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964903202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.964903202
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3798230025
Short name T408
Test name
Test status
Simulation time 38593336 ps
CPU time 0.92 seconds
Started Jul 09 05:45:35 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 215728 kb
Host smart-0cc5242a-b3be-4346-82b0-45a24b8b253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798230025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3798230025
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.311610307
Short name T753
Test name
Test status
Simulation time 42467416 ps
CPU time 1.04 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 215596 kb
Host smart-6bb52cc1-4e9b-4726-ab64-ba75dc6e584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311610307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.311610307
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1726778867
Short name T687
Test name
Test status
Simulation time 405899974 ps
CPU time 6.75 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 217612 kb
Host smart-a0d7193b-6242-4804-a26a-a9dba8b4feed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726778867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1726778867
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2063375887
Short name T913
Test name
Test status
Simulation time 83660450394 ps
CPU time 459.26 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 05:53:08 PM PDT 24
Peak memory 222704 kb
Host smart-d179450e-62bd-4e4f-9a45-25a90809d453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063375887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2063375887
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1127022618
Short name T249
Test name
Test status
Simulation time 59214238 ps
CPU time 1.23 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 215784 kb
Host smart-c2c2717f-66a7-40f4-b478-2725375cd7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127022618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1127022618
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3214115842
Short name T699
Test name
Test status
Simulation time 25478518 ps
CPU time 0.96 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 207044 kb
Host smart-d053d95f-afe3-4ac3-b561-ec822d28755e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214115842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3214115842
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1630434121
Short name T834
Test name
Test status
Simulation time 32402446 ps
CPU time 0.84 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 216364 kb
Host smart-881d90bb-2b0e-4b9b-bf10-6d695835b49f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630434121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1630434121
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1318248256
Short name T907
Test name
Test status
Simulation time 34020735 ps
CPU time 1.19 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 217112 kb
Host smart-afe624ec-3bb9-4aac-b065-038a088fa687
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318248256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1318248256
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2151673011
Short name T794
Test name
Test status
Simulation time 45821703 ps
CPU time 1.09 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 220016 kb
Host smart-614ac641-2caf-4ab4-849c-15e8e21b1c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151673011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2151673011
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3400983542
Short name T659
Test name
Test status
Simulation time 105638036 ps
CPU time 1.2 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 217700 kb
Host smart-f4a0bf04-9513-41b1-ac8f-6ff2a98c1f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400983542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3400983542
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2646723562
Short name T62
Test name
Test status
Simulation time 37401833 ps
CPU time 1.01 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 224312 kb
Host smart-41aa265c-89c6-4994-a146-8f0ce7c7756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646723562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2646723562
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1235439615
Short name T342
Test name
Test status
Simulation time 15429179 ps
CPU time 0.92 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 215620 kb
Host smart-298c3f5c-8ea1-4b0d-b7fe-fabea1b1742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235439615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1235439615
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2691190807
Short name T774
Test name
Test status
Simulation time 51288089 ps
CPU time 0.98 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 206764 kb
Host smart-dce2fab7-866c-45a6-8427-907699c44b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691190807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2691190807
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1486586823
Short name T737
Test name
Test status
Simulation time 454094704784 ps
CPU time 1205.44 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 06:05:34 PM PDT 24
Peak memory 222548 kb
Host smart-28fefc9c-dedc-4fc0-a785-3c5b2a13fa2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486586823 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1486586823
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4050641395
Short name T130
Test name
Test status
Simulation time 36057360 ps
CPU time 1.23 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 220096 kb
Host smart-d5e0d23f-2b8c-4380-a82e-37ba2688ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050641395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4050641395
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2433253665
Short name T851
Test name
Test status
Simulation time 22966133 ps
CPU time 1.12 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 215252 kb
Host smart-ae83136e-7c72-4ce7-8488-3f1ce8307cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433253665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2433253665
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.311905958
Short name T158
Test name
Test status
Simulation time 30288493 ps
CPU time 0.77 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 215512 kb
Host smart-cdb3bc68-6c7f-4d1c-ab64-0c556583e054
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311905958 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.311905958
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4181190421
Short name T924
Test name
Test status
Simulation time 27903814 ps
CPU time 1.14 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:22 PM PDT 24
Peak memory 217076 kb
Host smart-500706dc-cf2a-4ea8-8b3d-180e700d415f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181190421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4181190421
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3686037624
Short name T117
Test name
Test status
Simulation time 33872230 ps
CPU time 1.02 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 220020 kb
Host smart-21a90c1a-7540-4978-b2c8-8b2b5845394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686037624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3686037624
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2148340338
Short name T792
Test name
Test status
Simulation time 46835114 ps
CPU time 1.91 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 220372 kb
Host smart-7ce8f545-fbcd-4311-b002-b7b3e240c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148340338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2148340338
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3470388730
Short name T35
Test name
Test status
Simulation time 21318533 ps
CPU time 1.03 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 216100 kb
Host smart-75e0e416-eb1c-4ccb-9916-8e640a55074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470388730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3470388730
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1902110771
Short name T346
Test name
Test status
Simulation time 75773058 ps
CPU time 0.85 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 215412 kb
Host smart-05cce6cd-c635-4fe5-af15-7ee1c511c313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902110771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1902110771
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.605580418
Short name T56
Test name
Test status
Simulation time 258863278 ps
CPU time 5.17 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 217608 kb
Host smart-760209b1-601e-4237-bb93-9da239c371ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605580418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.605580418
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3238839415
Short name T425
Test name
Test status
Simulation time 41574755711 ps
CPU time 873.5 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:59:54 PM PDT 24
Peak memory 220284 kb
Host smart-b9389a1f-f235-4315-aec5-cf62eab0f134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238839415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3238839415
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1493790327
Short name T898
Test name
Test status
Simulation time 76436896 ps
CPU time 1.17 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 220804 kb
Host smart-62b3ca10-c33e-43ec-a587-7cbe64558f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493790327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1493790327
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.115701238
Short name T949
Test name
Test status
Simulation time 17609576 ps
CPU time 0.92 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 206988 kb
Host smart-0a1bc34d-467e-4039-a830-1fa5f4060bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115701238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.115701238
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2473291623
Short name T224
Test name
Test status
Simulation time 19686242 ps
CPU time 0.87 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 216536 kb
Host smart-3cd367f0-f359-4fc1-811b-9b1d9fd63320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473291623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2473291623
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1806836020
Short name T697
Test name
Test status
Simulation time 26112009 ps
CPU time 1.03 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 216908 kb
Host smart-5cf41ea2-fe45-4919-bd1d-303e6d87bc26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806836020 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1806836020
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_genbits.3138682270
Short name T426
Test name
Test status
Simulation time 36026028 ps
CPU time 1.3 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 220256 kb
Host smart-2a84f848-2a9a-4b4b-9ce8-0df923015af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138682270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3138682270
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2878106661
Short name T918
Test name
Test status
Simulation time 22067148 ps
CPU time 1.06 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 215744 kb
Host smart-a1b2e348-ad7d-4b5f-bce2-eac676a60d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878106661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2878106661
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1935082767
Short name T392
Test name
Test status
Simulation time 39527398 ps
CPU time 0.87 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 215412 kb
Host smart-02fd6e5c-805e-49f9-979d-84ce1069d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935082767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1935082767
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.54062058
Short name T574
Test name
Test status
Simulation time 409624993 ps
CPU time 4.8 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 217636 kb
Host smart-4e7a2986-9b41-4e58-af6f-82752d134afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54062058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.54062058
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3395845465
Short name T227
Test name
Test status
Simulation time 64717736793 ps
CPU time 633.63 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 05:56:12 PM PDT 24
Peak memory 224008 kb
Host smart-a530299f-619d-4922-a6f5-22f418384291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395845465 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3395845465
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2543646162
Short name T632
Test name
Test status
Simulation time 111108126 ps
CPU time 1.12 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 220836 kb
Host smart-809fe7a3-b087-4bdb-9df4-37e363c782c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543646162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2543646162
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2816786220
Short name T923
Test name
Test status
Simulation time 13013234 ps
CPU time 0.87 seconds
Started Jul 09 05:44:33 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 207236 kb
Host smart-e66c26db-6e65-4a0e-8760-f4ffdd0d3b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816786220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2816786220
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.256552878
Short name T168
Test name
Test status
Simulation time 21393563 ps
CPU time 0.94 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 216560 kb
Host smart-c69efd93-8110-4392-8ccc-7f3931abe82b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256552878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.256552878
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3042478652
Short name T721
Test name
Test status
Simulation time 22849453 ps
CPU time 1.09 seconds
Started Jul 09 05:45:02 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 217216 kb
Host smart-5a9aa232-0d6d-4277-ab71-6f1e9e205f52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042478652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3042478652
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.451923411
Short name T220
Test name
Test status
Simulation time 29087489 ps
CPU time 1.23 seconds
Started Jul 09 05:44:22 PM PDT 24
Finished Jul 09 05:44:26 PM PDT 24
Peak memory 225960 kb
Host smart-d9f55f31-78b3-42e2-8b15-602d5e377c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451923411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.451923411
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2997591309
Short name T292
Test name
Test status
Simulation time 60683634 ps
CPU time 1.43 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 220376 kb
Host smart-a708645f-0fab-41ab-a8ad-3bbbb748df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997591309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2997591309
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.694511595
Short name T88
Test name
Test status
Simulation time 22210574 ps
CPU time 1.09 seconds
Started Jul 09 05:44:37 PM PDT 24
Finished Jul 09 05:44:39 PM PDT 24
Peak memory 215828 kb
Host smart-dd4f6178-fe83-4a49-971d-8c4216fbc425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694511595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.694511595
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3565414571
Short name T30
Test name
Test status
Simulation time 25853354 ps
CPU time 0.95 seconds
Started Jul 09 05:44:45 PM PDT 24
Finished Jul 09 05:44:46 PM PDT 24
Peak memory 207432 kb
Host smart-f7921b39-deaa-4c5f-8211-f720739f6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565414571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3565414571
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.390609893
Short name T20
Test name
Test status
Simulation time 664195800 ps
CPU time 9.64 seconds
Started Jul 09 05:44:36 PM PDT 24
Finished Jul 09 05:44:46 PM PDT 24
Peak memory 236964 kb
Host smart-500ec64c-b117-4e8f-8c7c-7b78cd9f19f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390609893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.390609893
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3742293779
Short name T662
Test name
Test status
Simulation time 24840313 ps
CPU time 0.88 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:30 PM PDT 24
Peak memory 215620 kb
Host smart-4f7282b1-ee78-43fe-8f43-125bab37cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742293779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3742293779
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2235798463
Short name T241
Test name
Test status
Simulation time 228091651 ps
CPU time 4.8 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 217668 kb
Host smart-c3c1bfa7-7f35-4d08-8289-8e44dfb3d654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235798463 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2235798463
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2446476437
Short name T758
Test name
Test status
Simulation time 348647004962 ps
CPU time 2146.62 seconds
Started Jul 09 05:44:26 PM PDT 24
Finished Jul 09 06:20:16 PM PDT 24
Peak memory 226412 kb
Host smart-cd985717-193c-4b75-ba3a-efe789017a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446476437 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2446476437
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2203767438
Short name T193
Test name
Test status
Simulation time 247561293 ps
CPU time 1.31 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 219888 kb
Host smart-a4c7fac6-6196-41f1-bfbf-ab745a704eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203767438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2203767438
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.407904689
Short name T935
Test name
Test status
Simulation time 44882177 ps
CPU time 0.92 seconds
Started Jul 09 05:45:37 PM PDT 24
Finished Jul 09 05:45:38 PM PDT 24
Peak memory 215176 kb
Host smart-fc890512-feae-494d-b6d1-b91f740fd470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407904689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.407904689
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.238372377
Short name T761
Test name
Test status
Simulation time 18768747 ps
CPU time 0.79 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:15 PM PDT 24
Peak memory 216448 kb
Host smart-42d8aa3c-19bd-4ed0-add4-881351ee1afe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238372377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.238372377
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1410636059
Short name T514
Test name
Test status
Simulation time 50650469 ps
CPU time 0.93 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:09 PM PDT 24
Peak memory 220104 kb
Host smart-f48cd1bb-2406-4a47-ac12-3ad75e81ee8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410636059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1410636059
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3730136501
Short name T769
Test name
Test status
Simulation time 56322658 ps
CPU time 1.11 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 232444 kb
Host smart-207be931-d6da-42dd-be7a-57c8aee5c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730136501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3730136501
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.141548130
Short name T901
Test name
Test status
Simulation time 61243781 ps
CPU time 1.35 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 218824 kb
Host smart-d6b374d6-679b-4334-90d3-ec52117e45ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141548130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.141548130
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.321738664
Short name T637
Test name
Test status
Simulation time 17051797 ps
CPU time 0.98 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 215588 kb
Host smart-8b2359aa-69d8-4e4a-9285-9c918ed8ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321738664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.321738664
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3556872522
Short name T110
Test name
Test status
Simulation time 659374430 ps
CPU time 3.58 seconds
Started Jul 09 05:45:30 PM PDT 24
Finished Jul 09 05:45:34 PM PDT 24
Peak memory 217704 kb
Host smart-7611cb5f-4b95-456a-8b59-d947f3442537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556872522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3556872522
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1435731485
Short name T767
Test name
Test status
Simulation time 13997301955 ps
CPU time 200.78 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:48:47 PM PDT 24
Peak memory 218052 kb
Host smart-a22eac15-d1da-43fe-9a89-5bce8794dfdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435731485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1435731485
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3060610049
Short name T740
Test name
Test status
Simulation time 62647101 ps
CPU time 1.02 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 218960 kb
Host smart-c487a481-7797-4588-93a6-06f94abeb042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060610049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3060610049
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2832481826
Short name T916
Test name
Test status
Simulation time 22537633 ps
CPU time 0.82 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 206996 kb
Host smart-c14553a3-1e5c-4245-80a6-3b0bd7e9e4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832481826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2832481826
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.518799172
Short name T47
Test name
Test status
Simulation time 18327582 ps
CPU time 0.83 seconds
Started Jul 09 05:45:35 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 216540 kb
Host smart-be3acbdb-35aa-4d2f-a30b-1cab5cf39ede
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518799172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.518799172
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.370885551
Short name T871
Test name
Test status
Simulation time 44127333 ps
CPU time 1.08 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 220240 kb
Host smart-1b786dcd-c7ca-4adb-9548-c2197addee3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370885551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.370885551
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1633598923
Short name T810
Test name
Test status
Simulation time 18047143 ps
CPU time 1.08 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 218968 kb
Host smart-95082500-3ae8-4cae-a522-f06f25c62351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633598923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1633598923
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.999218354
Short name T717
Test name
Test status
Simulation time 38425886 ps
CPU time 1.32 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 218720 kb
Host smart-363913ff-50fe-452c-9dfc-a7f281a145e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999218354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.999218354
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3712495371
Short name T613
Test name
Test status
Simulation time 37095698 ps
CPU time 0.86 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 215840 kb
Host smart-8379b4ff-2673-4174-b310-b7cc7a013d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712495371 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3712495371
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1925794117
Short name T787
Test name
Test status
Simulation time 23628282 ps
CPU time 0.87 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 215536 kb
Host smart-3febfe6d-3039-4295-9e77-c69cafdf9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925794117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1925794117
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1903976969
Short name T846
Test name
Test status
Simulation time 127482322245 ps
CPU time 1616.32 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 06:12:35 PM PDT 24
Peak memory 228140 kb
Host smart-56de72ad-4f30-4a09-99c8-9012bdd7dc15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903976969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1903976969
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.4235264597
Short name T540
Test name
Test status
Simulation time 39016622 ps
CPU time 1.22 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 219092 kb
Host smart-c1a9f2ea-6faf-4fe0-b26d-306245d42c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235264597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4235264597
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3182891290
Short name T483
Test name
Test status
Simulation time 17931536 ps
CPU time 0.96 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 207064 kb
Host smart-84ff4125-d35f-43ca-9e59-c093390bc155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182891290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3182891290
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2717004973
Short name T700
Test name
Test status
Simulation time 35022003 ps
CPU time 1.14 seconds
Started Jul 09 05:45:33 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 218460 kb
Host smart-6372d421-1c4d-4465-876f-17f88b2cc9cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717004973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2717004973
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.977538396
Short name T174
Test name
Test status
Simulation time 28648838 ps
CPU time 0.96 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 05:45:40 PM PDT 24
Peak memory 224044 kb
Host smart-e6825a54-d4da-4c75-b325-eeca3acda541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977538396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.977538396
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.378825989
Short name T736
Test name
Test status
Simulation time 63592695 ps
CPU time 1.27 seconds
Started Jul 09 05:45:11 PM PDT 24
Finished Jul 09 05:45:14 PM PDT 24
Peak memory 218784 kb
Host smart-b49dd1fc-149e-440d-9015-17740ba57193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378825989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.378825989
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.415393829
Short name T74
Test name
Test status
Simulation time 33549487 ps
CPU time 0.83 seconds
Started Jul 09 05:45:17 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 215784 kb
Host smart-6f40cbd2-27ed-4966-89e6-f1f013ba0f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415393829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.415393829
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3361858938
Short name T731
Test name
Test status
Simulation time 26260143 ps
CPU time 0.95 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 215596 kb
Host smart-85d1a0d6-f397-415c-b947-28b5a7b76480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361858938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3361858938
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2128153943
Short name T822
Test name
Test status
Simulation time 972878167 ps
CPU time 4.15 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:31 PM PDT 24
Peak memory 215616 kb
Host smart-078d26f4-53a5-4c21-b17d-019b91b350db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128153943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2128153943
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2281960813
Short name T932
Test name
Test status
Simulation time 75083428127 ps
CPU time 835.75 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:59:12 PM PDT 24
Peak memory 223972 kb
Host smart-900344fa-7e9d-4f57-b727-00189f869cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281960813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2281960813
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2310131614
Short name T183
Test name
Test status
Simulation time 61284548 ps
CPU time 1.08 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 219812 kb
Host smart-346c8fc8-98bb-4916-afa9-66dcc5a92bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310131614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2310131614
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2240228891
Short name T365
Test name
Test status
Simulation time 13174598 ps
CPU time 0.86 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 207032 kb
Host smart-abaaae48-c04d-4c16-a93c-942bede96236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240228891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2240228891
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.519093448
Short name T201
Test name
Test status
Simulation time 12230809 ps
CPU time 0.89 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 216732 kb
Host smart-d8a38167-8ac1-4827-a1b1-47da658c046e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519093448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.519093448
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1820284453
Short name T144
Test name
Test status
Simulation time 105562392 ps
CPU time 1.09 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 217324 kb
Host smart-9c7f40a0-e84d-4dd2-966e-016af9acc709
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820284453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1820284453
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.199660408
Short name T696
Test name
Test status
Simulation time 54643863 ps
CPU time 0.82 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 218648 kb
Host smart-494fcc8b-1ccb-4a28-b75a-a0f5d08ca2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199660408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.199660408
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3652323462
Short name T640
Test name
Test status
Simulation time 73036087 ps
CPU time 1.6 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 219140 kb
Host smart-8baf9be8-ab3e-4c8f-8a03-c100512aa7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652323462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3652323462
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.129359461
Short name T946
Test name
Test status
Simulation time 34192527 ps
CPU time 0.9 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 224120 kb
Host smart-f8c811e1-53f4-4b51-acc7-d454a7d42585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129359461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.129359461
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3262449460
Short name T422
Test name
Test status
Simulation time 16652782 ps
CPU time 0.97 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 215588 kb
Host smart-0962a44c-5d07-49ee-9b9b-3652e4c72604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262449460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3262449460
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1908307770
Short name T549
Test name
Test status
Simulation time 171105062 ps
CPU time 2.13 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 215712 kb
Host smart-85007cb3-1399-4902-9d1b-6b00539f380a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908307770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1908307770
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4251364600
Short name T231
Test name
Test status
Simulation time 212158044140 ps
CPU time 2572.57 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 06:28:40 PM PDT 24
Peak memory 233980 kb
Host smart-9ddcf47c-ccf4-49d3-8322-fde0196bdc1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251364600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4251364600
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3773582588
Short name T442
Test name
Test status
Simulation time 68025578 ps
CPU time 1.09 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 219756 kb
Host smart-331ee085-4d1e-46f2-bf59-d76a462fb551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773582588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3773582588
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3373965989
Short name T960
Test name
Test status
Simulation time 45267269 ps
CPU time 0.77 seconds
Started Jul 09 05:45:31 PM PDT 24
Finished Jul 09 05:45:32 PM PDT 24
Peak memory 206648 kb
Host smart-b7cdc72b-1f66-4d8d-b49e-89d0474f7125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373965989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3373965989
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.405309033
Short name T977
Test name
Test status
Simulation time 20929692 ps
CPU time 0.84 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 216240 kb
Host smart-d2011085-40f0-447c-8169-c00014bd1d95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405309033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.405309033
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1482435939
Short name T23
Test name
Test status
Simulation time 67237117 ps
CPU time 1.18 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 217040 kb
Host smart-fd4c496a-ae8f-4b04-913e-40a104d7b2e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482435939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1482435939
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2228776672
Short name T213
Test name
Test status
Simulation time 20758311 ps
CPU time 1.04 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:18 PM PDT 24
Peak memory 219912 kb
Host smart-45e4766c-9640-4c67-a0be-8246b8a417f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228776672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2228776672
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.140191713
Short name T561
Test name
Test status
Simulation time 78284686 ps
CPU time 1.63 seconds
Started Jul 09 05:45:29 PM PDT 24
Finished Jul 09 05:45:32 PM PDT 24
Peak memory 220468 kb
Host smart-896e9fba-3332-4b3f-b80e-29f0630053a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140191713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.140191713
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.511224288
Short name T976
Test name
Test status
Simulation time 22731965 ps
CPU time 1.08 seconds
Started Jul 09 05:45:37 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 215844 kb
Host smart-d409e437-2db7-40db-a515-f0b9f751872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511224288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.511224288
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3460408804
Short name T498
Test name
Test status
Simulation time 17692166 ps
CPU time 0.99 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 215596 kb
Host smart-ed8109ca-1cc3-43b2-b927-f6b2b9a12760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460408804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3460408804
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1869780950
Short name T805
Test name
Test status
Simulation time 463316554 ps
CPU time 1.7 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 217452 kb
Host smart-bd64cbaa-2801-4f5d-a3c0-84190ac7317c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869780950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1869780950
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.834859735
Short name T633
Test name
Test status
Simulation time 504425105278 ps
CPU time 1440.28 seconds
Started Jul 09 05:45:32 PM PDT 24
Finished Jul 09 06:09:33 PM PDT 24
Peak memory 224344 kb
Host smart-626fb256-c591-4eb3-a7c4-a4df30cf6e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834859735 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.834859735
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.173797006
Short name T296
Test name
Test status
Simulation time 27111726 ps
CPU time 1.19 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 218668 kb
Host smart-db8c52f1-6605-491c-a222-bb080d9a94f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173797006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.173797006
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.491353400
Short name T362
Test name
Test status
Simulation time 109635312 ps
CPU time 1.05 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 207064 kb
Host smart-619dd382-7edc-4b32-9eaa-0f564ea5372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491353400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.491353400
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3101469056
Short name T92
Test name
Test status
Simulation time 36302156 ps
CPU time 0.84 seconds
Started Jul 09 05:45:20 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 216644 kb
Host smart-537b2c00-ef11-4a37-a747-d040230b3763
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101469056 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3101469056
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2615464586
Short name T78
Test name
Test status
Simulation time 38306800 ps
CPU time 1.43 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 217300 kb
Host smart-8c1dd8df-3844-4327-98ff-c7d3db3fbe6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615464586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2615464586
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2346231437
Short name T214
Test name
Test status
Simulation time 52004909 ps
CPU time 0.87 seconds
Started Jul 09 05:45:22 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 215604 kb
Host smart-12ed2d90-58bd-4115-9ab5-5cfff84ef320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346231437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2346231437
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1486272842
Short name T816
Test name
Test status
Simulation time 90123606 ps
CPU time 1.68 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 220132 kb
Host smart-81fa47a4-d2b0-41cd-b062-667e36fc5541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486272842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1486272842
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3879115210
Short name T18
Test name
Test status
Simulation time 21832244 ps
CPU time 1.14 seconds
Started Jul 09 05:45:31 PM PDT 24
Finished Jul 09 05:45:32 PM PDT 24
Peak memory 224312 kb
Host smart-8518cd17-3506-423a-bd3b-10f3e9424846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879115210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3879115210
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4293140256
Short name T391
Test name
Test status
Simulation time 23624129 ps
CPU time 0.89 seconds
Started Jul 09 05:45:47 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 215592 kb
Host smart-830d025f-8a5b-4d5a-b0c4-60b12027f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293140256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4293140256
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1523199689
Short name T623
Test name
Test status
Simulation time 250856088 ps
CPU time 5.27 seconds
Started Jul 09 05:45:35 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 220536 kb
Host smart-127edbb7-f4e6-463d-98f0-4eb02dab61c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523199689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1523199689
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.3015511687
Short name T113
Test name
Test status
Simulation time 191143924 ps
CPU time 1.25 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 216016 kb
Host smart-5d54e365-8903-4cd3-acbb-02a7b946668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015511687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3015511687
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2111720330
Short name T778
Test name
Test status
Simulation time 76706380 ps
CPU time 0.85 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 215216 kb
Host smart-2e882d8d-ace5-471b-a7ea-ed1e4988512b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111720330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2111720330
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3176222367
Short name T850
Test name
Test status
Simulation time 17978207 ps
CPU time 0.81 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:27 PM PDT 24
Peak memory 216564 kb
Host smart-cac018ee-6315-4724-bb38-1dd7f19f8cee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176222367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3176222367
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3576009187
Short name T859
Test name
Test status
Simulation time 49468246 ps
CPU time 1.06 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:17 PM PDT 24
Peak memory 217140 kb
Host smart-906783aa-6df9-488a-b7e7-fe26cd2c831c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576009187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3576009187
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.25558920
Short name T137
Test name
Test status
Simulation time 26730448 ps
CPU time 0.93 seconds
Started Jul 09 05:45:30 PM PDT 24
Finished Jul 09 05:45:31 PM PDT 24
Peak memory 218788 kb
Host smart-1f1c8bd0-b126-4e40-bc41-803b59110855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25558920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.25558920
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1177606878
Short name T359
Test name
Test status
Simulation time 45963374 ps
CPU time 1.12 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 217504 kb
Host smart-7bf61de0-9d4a-4671-9d07-d8871e400c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177606878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1177606878
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3357722337
Short name T796
Test name
Test status
Simulation time 22872690 ps
CPU time 1.13 seconds
Started Jul 09 05:45:29 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 216092 kb
Host smart-572dbfcf-c014-4cd2-b6a7-2ee9025bf7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357722337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3357722337
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1193846196
Short name T581
Test name
Test status
Simulation time 62564258 ps
CPU time 0.89 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 215516 kb
Host smart-9ea106de-2c92-41bf-8dfd-78f94481b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193846196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1193846196
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1675329825
Short name T663
Test name
Test status
Simulation time 914176384 ps
CPU time 2.92 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 217572 kb
Host smart-925ab227-5eda-4b07-b994-e9501d5ea3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675329825 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1675329825
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2794982769
Short name T431
Test name
Test status
Simulation time 30274104604 ps
CPU time 715.69 seconds
Started Jul 09 05:45:31 PM PDT 24
Finished Jul 09 05:57:28 PM PDT 24
Peak memory 218052 kb
Host smart-2107397b-4ad8-4567-84cc-161643c14849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794982769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2794982769
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.487793092
Short name T750
Test name
Test status
Simulation time 38474112 ps
CPU time 1.28 seconds
Started Jul 09 05:45:24 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 218732 kb
Host smart-56a233d1-e2fa-410e-9a29-40fb0f743976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487793092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.487793092
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1239934822
Short name T649
Test name
Test status
Simulation time 47179646 ps
CPU time 0.83 seconds
Started Jul 09 05:45:36 PM PDT 24
Finished Jul 09 05:45:37 PM PDT 24
Peak memory 207032 kb
Host smart-64858c9c-caf7-4685-985e-965bf4f5663d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239934822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1239934822
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3375489919
Short name T988
Test name
Test status
Simulation time 36976055 ps
CPU time 0.85 seconds
Started Jul 09 05:45:15 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 215728 kb
Host smart-5d7245a9-beff-4483-b696-2b12b6c7f5fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375489919 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3375489919
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3730935197
Short name T212
Test name
Test status
Simulation time 90243836 ps
CPU time 1.01 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 219948 kb
Host smart-3984fff8-6584-4e1d-bd3e-22746324569f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730935197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3730935197
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1201257348
Short name T148
Test name
Test status
Simulation time 27487571 ps
CPU time 1.2 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 217652 kb
Host smart-76c56ad7-87f9-4ea9-8935-ef6f09883eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201257348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1201257348
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3624151175
Short name T583
Test name
Test status
Simulation time 92349257 ps
CPU time 1.18 seconds
Started Jul 09 05:45:13 PM PDT 24
Finished Jul 09 05:45:16 PM PDT 24
Peak memory 215552 kb
Host smart-ff1417d6-33cc-4156-9f7b-c5275edce017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624151175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3624151175
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4048954791
Short name T436
Test name
Test status
Simulation time 25606969 ps
CPU time 0.9 seconds
Started Jul 09 05:45:18 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 215808 kb
Host smart-bd8e2ea8-fe3d-4983-a6e8-409d02cbe50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048954791 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4048954791
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3556151826
Short name T84
Test name
Test status
Simulation time 17356852 ps
CPU time 0.97 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 215580 kb
Host smart-66ef6e3c-9c8b-48b2-b0fb-9ca24ae357f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556151826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3556151826
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.209366788
Short name T682
Test name
Test status
Simulation time 249784935 ps
CPU time 4.75 seconds
Started Jul 09 05:45:32 PM PDT 24
Finished Jul 09 05:45:38 PM PDT 24
Peak memory 218740 kb
Host smart-5f960cd8-6463-4088-b495-fee25931281f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209366788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.209366788
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1560468349
Short name T568
Test name
Test status
Simulation time 137505370670 ps
CPU time 1770.5 seconds
Started Jul 09 05:45:14 PM PDT 24
Finished Jul 09 06:14:46 PM PDT 24
Peak memory 228512 kb
Host smart-c59c8aee-aa2f-47d9-b512-2ecb5be38cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560468349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1560468349
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2545477838
Short name T763
Test name
Test status
Simulation time 90839019 ps
CPU time 1.22 seconds
Started Jul 09 05:45:19 PM PDT 24
Finished Jul 09 05:45:23 PM PDT 24
Peak memory 216016 kb
Host smart-74f971aa-846a-4659-8f37-7a3395df32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545477838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2545477838
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1098200357
Short name T80
Test name
Test status
Simulation time 127084738 ps
CPU time 0.92 seconds
Started Jul 09 05:45:32 PM PDT 24
Finished Jul 09 05:45:34 PM PDT 24
Peak memory 215204 kb
Host smart-1c4107fb-89e5-40e3-ae91-2ae59d361b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098200357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1098200357
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1524765321
Short name T647
Test name
Test status
Simulation time 29556255 ps
CPU time 0.83 seconds
Started Jul 09 05:45:30 PM PDT 24
Finished Jul 09 05:45:32 PM PDT 24
Peak memory 216204 kb
Host smart-3f9313ea-80a1-4397-b095-8086cf89a0ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524765321 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1524765321
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2704131525
Short name T293
Test name
Test status
Simulation time 35653656 ps
CPU time 1.17 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 219008 kb
Host smart-46dd7658-f66c-45b4-a89f-c2463aa4cb4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704131525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2704131525
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3904845614
Short name T813
Test name
Test status
Simulation time 20490515 ps
CPU time 0.96 seconds
Started Jul 09 05:45:28 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 220040 kb
Host smart-6324e61f-310f-4d9e-8800-c154f04bffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904845614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3904845614
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3956371737
Short name T692
Test name
Test status
Simulation time 115860113 ps
CPU time 1.32 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 220348 kb
Host smart-13997a95-a9f8-4576-91c6-fc759ad80d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956371737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3956371737
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3855476327
Short name T32
Test name
Test status
Simulation time 27826556 ps
CPU time 0.92 seconds
Started Jul 09 05:45:16 PM PDT 24
Finished Jul 09 05:45:19 PM PDT 24
Peak memory 216260 kb
Host smart-adbabe06-7e91-4c2d-ba3d-c7bc1897c18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855476327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3855476327
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1987739885
Short name T340
Test name
Test status
Simulation time 25270832 ps
CPU time 0.95 seconds
Started Jul 09 05:45:27 PM PDT 24
Finished Jul 09 05:45:30 PM PDT 24
Peak memory 215608 kb
Host smart-2d48375e-e53d-40a0-b21d-461576edf756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987739885 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1987739885
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.861542254
Short name T614
Test name
Test status
Simulation time 459577694 ps
CPU time 5.35 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:45 PM PDT 24
Peak memory 215596 kb
Host smart-24046477-93c5-4d0a-a54e-0fb3fcf24c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861542254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.861542254
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3166466784
Short name T983
Test name
Test status
Simulation time 5081008628 ps
CPU time 112.32 seconds
Started Jul 09 05:45:43 PM PDT 24
Finished Jul 09 05:47:35 PM PDT 24
Peak memory 218600 kb
Host smart-fa87b1eb-d464-420a-84ea-2047f0ed5284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166466784 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3166466784
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.570534335
Short name T165
Test name
Test status
Simulation time 79431921 ps
CPU time 1.11 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:26 PM PDT 24
Peak memory 219916 kb
Host smart-38710714-dc29-480c-b873-f44023971a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570534335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.570534335
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.611331551
Short name T472
Test name
Test status
Simulation time 44383736 ps
CPU time 0.89 seconds
Started Jul 09 05:45:38 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 214904 kb
Host smart-73557aea-d8ee-4917-91a7-f53a052ab22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611331551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.611331551
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.648248854
Short name T200
Test name
Test status
Simulation time 32596965 ps
CPU time 0.83 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:45 PM PDT 24
Peak memory 216564 kb
Host smart-b19ad736-cd5f-4c35-9ca8-9d3581137256
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648248854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.648248854
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3444561159
Short name T211
Test name
Test status
Simulation time 128132303 ps
CPU time 1.14 seconds
Started Jul 09 05:45:35 PM PDT 24
Finished Jul 09 05:45:37 PM PDT 24
Peak memory 217144 kb
Host smart-2b53a078-305e-4c6a-a419-ed6108cc409b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444561159 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3444561159
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2611421502
Short name T689
Test name
Test status
Simulation time 56302818 ps
CPU time 0.92 seconds
Started Jul 09 05:45:41 PM PDT 24
Finished Jul 09 05:45:43 PM PDT 24
Peak memory 218908 kb
Host smart-79b3f189-5734-451a-bbec-42d750cfc9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611421502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2611421502
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.840808563
Short name T463
Test name
Test status
Simulation time 70134754 ps
CPU time 1.11 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 220344 kb
Host smart-1925842d-ca5e-4308-a1e1-a80b263aee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840808563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.840808563
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2478867463
Short name T558
Test name
Test status
Simulation time 26903154 ps
CPU time 1.08 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 224312 kb
Host smart-caec4386-e800-498f-85ba-2a4a859f1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478867463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2478867463
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2287143272
Short name T604
Test name
Test status
Simulation time 26331929 ps
CPU time 0.88 seconds
Started Jul 09 05:45:30 PM PDT 24
Finished Jul 09 05:45:31 PM PDT 24
Peak memory 215612 kb
Host smart-c74c4562-bf33-49c1-919d-574696c95a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287143272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2287143272
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1032204081
Short name T109
Test name
Test status
Simulation time 180210070 ps
CPU time 2.36 seconds
Started Jul 09 05:45:23 PM PDT 24
Finished Jul 09 05:45:28 PM PDT 24
Peak memory 215612 kb
Host smart-dceea42a-f175-41f4-a5c0-52be369a2f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032204081 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1032204081
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2687075203
Short name T936
Test name
Test status
Simulation time 83767669760 ps
CPU time 756 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:58:16 PM PDT 24
Peak memory 220224 kb
Host smart-aca7ade4-8f0e-4eca-9e14-1bee266adc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687075203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2687075203
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3968623872
Short name T720
Test name
Test status
Simulation time 52899771 ps
CPU time 1.27 seconds
Started Jul 09 05:44:29 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 220176 kb
Host smart-085efb93-8c45-4b60-a5fb-e09043e7ec2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968623872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3968623872
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3053115253
Short name T724
Test name
Test status
Simulation time 39702469 ps
CPU time 0.83 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 207012 kb
Host smart-af68ac26-5a1b-459f-a06a-edbc49418f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053115253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3053115253
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.946446816
Short name T804
Test name
Test status
Simulation time 40035480 ps
CPU time 0.89 seconds
Started Jul 09 05:44:24 PM PDT 24
Finished Jul 09 05:44:27 PM PDT 24
Peak memory 216736 kb
Host smart-a53ef350-c65f-419a-abdb-842d9da78a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946446816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.946446816
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.925068319
Short name T920
Test name
Test status
Simulation time 136452101 ps
CPU time 1.13 seconds
Started Jul 09 05:44:32 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 220208 kb
Host smart-5b7de81a-976d-4d9b-add0-a017ca83ed59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925068319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.925068319
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1768234202
Short name T79
Test name
Test status
Simulation time 59996457 ps
CPU time 1.03 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 219984 kb
Host smart-4f6da233-5b14-49f1-9c4f-3499c27ffe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768234202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1768234202
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3169792220
Short name T305
Test name
Test status
Simulation time 93405952 ps
CPU time 1.2 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 219136 kb
Host smart-eb0a4988-c5e0-41e0-88d3-aad65dff6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169792220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3169792220
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3301311776
Short name T419
Test name
Test status
Simulation time 21989103 ps
CPU time 1.11 seconds
Started Jul 09 05:44:46 PM PDT 24
Finished Jul 09 05:44:48 PM PDT 24
Peak memory 215732 kb
Host smart-d7d8dc68-b801-4524-afa7-0fd41537f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301311776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3301311776
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.4006012297
Short name T711
Test name
Test status
Simulation time 17380012 ps
CPU time 1 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:38 PM PDT 24
Peak memory 207332 kb
Host smart-79387dfc-0bdb-411b-80d3-87917a7d897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006012297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4006012297
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1118496924
Short name T830
Test name
Test status
Simulation time 55108730 ps
CPU time 0.92 seconds
Started Jul 09 05:44:45 PM PDT 24
Finished Jul 09 05:44:47 PM PDT 24
Peak memory 215568 kb
Host smart-bd4f9a84-7223-4388-aa22-34cfe247e839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118496924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1118496924
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.4211838067
Short name T982
Test name
Test status
Simulation time 786722309 ps
CPU time 4.75 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:38 PM PDT 24
Peak memory 217648 kb
Host smart-f041759c-6311-4745-9261-f637f7c528d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211838067 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.4211838067
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3916777508
Short name T965
Test name
Test status
Simulation time 58447891100 ps
CPU time 1002.51 seconds
Started Jul 09 05:44:34 PM PDT 24
Finished Jul 09 06:01:18 PM PDT 24
Peak memory 220480 kb
Host smart-459d755c-63c5-489a-9917-c51dfa1b3720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916777508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3916777508
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1484013411
Short name T301
Test name
Test status
Simulation time 68480756 ps
CPU time 1.04 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:46 PM PDT 24
Peak memory 218924 kb
Host smart-8e39adc9-e406-45c3-a0c6-20aed32b18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484013411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1484013411
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_genbits.1463279723
Short name T584
Test name
Test status
Simulation time 48038130 ps
CPU time 1.27 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 218876 kb
Host smart-0ce9e618-b5ed-4cab-9b38-c40581ee846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463279723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1463279723
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1212110692
Short name T716
Test name
Test status
Simulation time 41852688 ps
CPU time 1.15 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:35 PM PDT 24
Peak memory 221152 kb
Host smart-782fe626-1ffc-4ef7-aee1-2a939fe20ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212110692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1212110692
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2979945001
Short name T820
Test name
Test status
Simulation time 29347933 ps
CPU time 0.92 seconds
Started Jul 09 05:45:45 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 218532 kb
Host smart-0302c671-be6d-4497-8989-79562a77b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979945001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2979945001
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2551356440
Short name T476
Test name
Test status
Simulation time 46901946 ps
CPU time 1.83 seconds
Started Jul 09 05:45:47 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 219124 kb
Host smart-4ffc4930-b98f-4155-ad25-41ecc05ab4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551356440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2551356440
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.705456423
Short name T713
Test name
Test status
Simulation time 91443499 ps
CPU time 1.19 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 215892 kb
Host smart-15812421-ef0c-4203-945a-ecd163ead816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705456423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.705456423
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3988665893
Short name T154
Test name
Test status
Simulation time 23870235 ps
CPU time 1 seconds
Started Jul 09 05:45:21 PM PDT 24
Finished Jul 09 05:45:25 PM PDT 24
Peak memory 224268 kb
Host smart-3a8b261a-50d5-40db-923b-86f8412e8e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988665893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3988665893
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_alert.271964518
Short name T990
Test name
Test status
Simulation time 40049367 ps
CPU time 1.18 seconds
Started Jul 09 05:45:30 PM PDT 24
Finished Jul 09 05:45:31 PM PDT 24
Peak memory 220716 kb
Host smart-a7304057-6156-46aa-9d77-752c8ca9129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271964518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.271964518
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2226464569
Short name T7
Test name
Test status
Simulation time 47126047 ps
CPU time 0.9 seconds
Started Jul 09 05:45:26 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 220188 kb
Host smart-687b96a0-5786-4d83-9730-d88f18bbad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226464569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2226464569
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1942589626
Short name T527
Test name
Test status
Simulation time 120545397 ps
CPU time 1.69 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 219040 kb
Host smart-9186a344-1fdb-4eea-96bf-564ba9988bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942589626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1942589626
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.322976561
Short name T269
Test name
Test status
Simulation time 27166614 ps
CPU time 1.19 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:46 PM PDT 24
Peak memory 218908 kb
Host smart-233a0ad6-a94e-4ead-be8e-96f3557707ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322976561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.322976561
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3862798372
Short name T507
Test name
Test status
Simulation time 18654585 ps
CPU time 1.06 seconds
Started Jul 09 05:45:32 PM PDT 24
Finished Jul 09 05:45:39 PM PDT 24
Peak memory 218596 kb
Host smart-70c91fdf-f401-43c0-b280-39d81a860524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862798372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3862798372
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2846232229
Short name T321
Test name
Test status
Simulation time 37488937 ps
CPU time 1.4 seconds
Started Jul 09 05:45:43 PM PDT 24
Finished Jul 09 05:45:45 PM PDT 24
Peak memory 219156 kb
Host smart-e2dec593-35df-488c-8f4c-caa00219bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846232229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2846232229
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1077496751
Short name T515
Test name
Test status
Simulation time 27859986 ps
CPU time 1.44 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 220836 kb
Host smart-c673d138-c286-4f33-9df0-ace61e545dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077496751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1077496751
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2776398657
Short name T210
Test name
Test status
Simulation time 24346074 ps
CPU time 0.86 seconds
Started Jul 09 05:45:32 PM PDT 24
Finished Jul 09 05:45:33 PM PDT 24
Peak memory 218372 kb
Host smart-3a479bdf-646f-4fe2-80b8-ab910772c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776398657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2776398657
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3123614457
Short name T511
Test name
Test status
Simulation time 64039153 ps
CPU time 1.16 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:46 PM PDT 24
Peak memory 219156 kb
Host smart-1936556a-83d0-4d09-9168-fb8c42d3d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123614457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3123614457
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.761247440
Short name T271
Test name
Test status
Simulation time 72055282 ps
CPU time 1.11 seconds
Started Jul 09 05:45:41 PM PDT 24
Finished Jul 09 05:45:43 PM PDT 24
Peak memory 218924 kb
Host smart-1d22630d-0932-47a1-a03e-e78ba95ede3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761247440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.761247440
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2093938080
Short name T580
Test name
Test status
Simulation time 28024280 ps
CPU time 1.15 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 221036 kb
Host smart-9cc68817-850e-4390-8187-3bcaba49f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093938080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2093938080
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1279461848
Short name T368
Test name
Test status
Simulation time 92904511 ps
CPU time 2.89 seconds
Started Jul 09 05:45:41 PM PDT 24
Finished Jul 09 05:45:44 PM PDT 24
Peak memory 219776 kb
Host smart-a2214be7-c9e4-4186-b446-8763fef76627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279461848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1279461848
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3696328674
Short name T302
Test name
Test status
Simulation time 45328876 ps
CPU time 1.09 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:46 PM PDT 24
Peak memory 220004 kb
Host smart-3d49e59b-a1b7-48cc-aa95-8005e956997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696328674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3696328674
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1832410081
Short name T651
Test name
Test status
Simulation time 21577372 ps
CPU time 1 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 224248 kb
Host smart-21754da5-a87d-4b96-b567-c75d89a3e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832410081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1832410081
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3223405372
Short name T53
Test name
Test status
Simulation time 35442801 ps
CPU time 1.45 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 218720 kb
Host smart-b98c2bfe-940e-4abd-8158-a0a48a16d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223405372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3223405372
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1511651895
Short name T571
Test name
Test status
Simulation time 25423175 ps
CPU time 1.23 seconds
Started Jul 09 05:45:43 PM PDT 24
Finished Jul 09 05:45:45 PM PDT 24
Peak memory 219028 kb
Host smart-dc73e591-4698-4adc-b108-9fc822262eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511651895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1511651895
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2279881696
Short name T899
Test name
Test status
Simulation time 42818604 ps
CPU time 1.25 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 226004 kb
Host smart-f45acbd4-002b-46c5-a2b6-26fda04c0715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279881696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2279881696
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.252941780
Short name T486
Test name
Test status
Simulation time 95942457 ps
CPU time 1.11 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 217564 kb
Host smart-6e4a282e-cfd4-4112-92eb-4383b6a5bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252941780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.252941780
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.4158786198
Short name T818
Test name
Test status
Simulation time 48809228 ps
CPU time 1.17 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 220972 kb
Host smart-ca80c02e-df72-4e4a-9694-c8b5a7785713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158786198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.4158786198
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1715447216
Short name T17
Test name
Test status
Simulation time 21324817 ps
CPU time 0.99 seconds
Started Jul 09 05:45:35 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 224260 kb
Host smart-35eff5b9-cac2-487c-8eaf-d7824fbf1411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715447216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1715447216
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3723661274
Short name T732
Test name
Test status
Simulation time 109333717 ps
CPU time 2.47 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:47 PM PDT 24
Peak memory 220128 kb
Host smart-28305f92-c216-476f-9819-e37ff88402cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723661274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3723661274
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.918490431
Short name T759
Test name
Test status
Simulation time 92355879 ps
CPU time 1.17 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 218824 kb
Host smart-375a00dd-234f-4b79-9b22-b0e249fbea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918490431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.918490431
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.496453489
Short name T454
Test name
Test status
Simulation time 49569809 ps
CPU time 0.86 seconds
Started Jul 09 05:44:47 PM PDT 24
Finished Jul 09 05:44:49 PM PDT 24
Peak memory 215216 kb
Host smart-3a8131b1-3992-483b-8576-1679d4c5073a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496453489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.496453489
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.794645308
Short name T373
Test name
Test status
Simulation time 10350273 ps
CPU time 0.83 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 216276 kb
Host smart-7deebc8c-bdde-4bf5-bbce-4bc4a0f5bafd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794645308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.794645308
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1891334511
Short name T150
Test name
Test status
Simulation time 41091431 ps
CPU time 1.07 seconds
Started Jul 09 05:44:29 PM PDT 24
Finished Jul 09 05:44:33 PM PDT 24
Peak memory 217088 kb
Host smart-df84db47-e431-429c-a8ab-e6b2e76ada4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891334511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1891334511
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1763450110
Short name T87
Test name
Test status
Simulation time 19461497 ps
CPU time 0.99 seconds
Started Jul 09 05:44:38 PM PDT 24
Finished Jul 09 05:44:40 PM PDT 24
Peak memory 218712 kb
Host smart-8db65729-4678-4c85-9ce4-2a65cbdede47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763450110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1763450110
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.585815134
Short name T551
Test name
Test status
Simulation time 52881072 ps
CPU time 0.95 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 215740 kb
Host smart-03a87341-dc42-403e-85f7-9a3af9944dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585815134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.585815134
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4275158483
Short name T684
Test name
Test status
Simulation time 26767174 ps
CPU time 0.94 seconds
Started Jul 09 05:44:45 PM PDT 24
Finished Jul 09 05:44:47 PM PDT 24
Peak memory 215860 kb
Host smart-868eb9a9-176a-44fb-a902-3ceccef93aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275158483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4275158483
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.205861812
Short name T291
Test name
Test status
Simulation time 25948566 ps
CPU time 0.9 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 207404 kb
Host smart-ca718137-7713-418c-ac30-7b07627049d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205861812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.205861812
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1231789066
Short name T508
Test name
Test status
Simulation time 18848718 ps
CPU time 0.98 seconds
Started Jul 09 05:44:35 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 215616 kb
Host smart-9909a878-79fd-48cd-9e37-5b4dfd6645d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231789066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1231789066
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.632599752
Short name T57
Test name
Test status
Simulation time 131845294 ps
CPU time 2.88 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 217588 kb
Host smart-199f9901-2ead-4943-8148-8263db2149bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632599752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.632599752
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3326050518
Short name T749
Test name
Test status
Simulation time 289570007469 ps
CPU time 1559.75 seconds
Started Jul 09 05:44:28 PM PDT 24
Finished Jul 09 06:10:32 PM PDT 24
Peak memory 224940 kb
Host smart-66e8e484-75e6-415e-8311-2d3619201e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326050518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3326050518
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3473068630
Short name T618
Test name
Test status
Simulation time 172300151 ps
CPU time 1.34 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:46 PM PDT 24
Peak memory 220056 kb
Host smart-44c16d38-0719-404e-9bec-36fdc08ca830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473068630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3473068630
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1654383690
Short name T782
Test name
Test status
Simulation time 31952490 ps
CPU time 0.85 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 218896 kb
Host smart-2b42a83d-4928-4550-bf3f-6ec3eb1e4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654383690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1654383690
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1970636347
Short name T407
Test name
Test status
Simulation time 55968126 ps
CPU time 1.36 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 219048 kb
Host smart-2f808f57-e46d-4ffc-99f5-d1bff078f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970636347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1970636347
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1385077325
Short name T950
Test name
Test status
Simulation time 25924405 ps
CPU time 1.27 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 219872 kb
Host smart-6a9d2340-e0c7-4340-97b8-903314a46840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385077325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1385077325
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.399721133
Short name T887
Test name
Test status
Simulation time 32993304 ps
CPU time 0.85 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 215524 kb
Host smart-61c66f22-f13e-41bf-b72e-cee8196f24bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399721133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.399721133
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.640512698
Short name T469
Test name
Test status
Simulation time 38347241 ps
CPU time 1.13 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 218740 kb
Host smart-48dd1299-afb4-43da-8b16-a1bcd93d600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640512698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.640512698
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3464910359
Short name T843
Test name
Test status
Simulation time 144491872 ps
CPU time 1.19 seconds
Started Jul 09 05:45:39 PM PDT 24
Finished Jul 09 05:45:41 PM PDT 24
Peak memory 218860 kb
Host smart-fba54704-66ed-4cb7-a4d7-a21b59b46b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464910359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3464910359
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.4062450439
Short name T197
Test name
Test status
Simulation time 19346097 ps
CPU time 1.09 seconds
Started Jul 09 05:45:47 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 219972 kb
Host smart-9705e9bc-7954-49d3-ad29-75b10694717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062450439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.4062450439
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1252701265
Short name T841
Test name
Test status
Simulation time 63710547 ps
CPU time 1.3 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 217600 kb
Host smart-f0c0bc6a-3d5d-4178-926a-76c5306eb848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252701265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1252701265
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3482264880
Short name T386
Test name
Test status
Simulation time 20198397 ps
CPU time 0.96 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 218804 kb
Host smart-890d6ddd-3290-49d4-82b6-f76a7c56f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482264880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3482264880
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1949101119
Short name T592
Test name
Test status
Simulation time 149159430 ps
CPU time 1.33 seconds
Started Jul 09 05:45:34 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 219052 kb
Host smart-3fcdc615-b76e-4591-9c47-a69930951a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949101119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1949101119
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1494256093
Short name T625
Test name
Test status
Simulation time 27982770 ps
CPU time 1.32 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 219916 kb
Host smart-cf8386bf-9fe0-4f66-a9de-d041d88f93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494256093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1494256093
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3181047148
Short name T611
Test name
Test status
Simulation time 60213453 ps
CPU time 1.08 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 219916 kb
Host smart-50424ed7-ed4b-4568-aa25-3c0948a9e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181047148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3181047148
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1263454322
Short name T710
Test name
Test status
Simulation time 83534377 ps
CPU time 1.51 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 219144 kb
Host smart-fb278b8a-132b-4876-9d41-773717acbb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263454322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1263454322
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.946013046
Short name T733
Test name
Test status
Simulation time 86047281 ps
CPU time 1.12 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 220024 kb
Host smart-b15d7e96-dab3-44f4-884a-26914572bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946013046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.946013046
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3450488780
Short name T748
Test name
Test status
Simulation time 21248409 ps
CPU time 1.03 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 224260 kb
Host smart-d44574eb-8201-4a95-ae6f-a3ba95425415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450488780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3450488780
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.302441621
Short name T596
Test name
Test status
Simulation time 58134020 ps
CPU time 1.05 seconds
Started Jul 09 05:45:41 PM PDT 24
Finished Jul 09 05:45:43 PM PDT 24
Peak memory 218864 kb
Host smart-2226c25b-3669-41b8-b5b6-c7804314a726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302441621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.302441621
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2155666236
Short name T250
Test name
Test status
Simulation time 104317175 ps
CPU time 1.37 seconds
Started Jul 09 05:45:40 PM PDT 24
Finished Jul 09 05:45:42 PM PDT 24
Peak memory 216016 kb
Host smart-03d8e44b-7ee5-4ea4-9de4-93e93fef5fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155666236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2155666236
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1430202735
Short name T160
Test name
Test status
Simulation time 20294311 ps
CPU time 1.08 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 218844 kb
Host smart-5ce4fdc7-40fb-40a8-8e06-7f8bac03ba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430202735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1430202735
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4084407080
Short name T519
Test name
Test status
Simulation time 222980678 ps
CPU time 1.18 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 215652 kb
Host smart-d1d3224b-6185-4df6-8898-d833ff4cb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084407080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4084407080
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1179327878
Short name T115
Test name
Test status
Simulation time 27447026 ps
CPU time 1.17 seconds
Started Jul 09 05:45:44 PM PDT 24
Finished Jul 09 05:45:45 PM PDT 24
Peak memory 220560 kb
Host smart-e3018e58-e2db-4cc1-9bfa-a6bc64de2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179327878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1179327878
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3835991399
Short name T142
Test name
Test status
Simulation time 27690755 ps
CPU time 1.32 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 229888 kb
Host smart-e0e3d712-cc76-46df-a37a-6d5943e7ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835991399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3835991399
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3944941972
Short name T940
Test name
Test status
Simulation time 79548489 ps
CPU time 2.94 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 220528 kb
Host smart-4466131b-c5ff-4290-892a-3c65aaf537d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944941972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3944941972
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.786751639
Short name T9
Test name
Test status
Simulation time 118015471 ps
CPU time 1.25 seconds
Started Jul 09 05:45:42 PM PDT 24
Finished Jul 09 05:45:44 PM PDT 24
Peak memory 218876 kb
Host smart-b13296c5-686b-47cc-a383-eb38f3eb6527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786751639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.786751639
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3023627839
Short name T59
Test name
Test status
Simulation time 43767898 ps
CPU time 1.23 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 229924 kb
Host smart-0dada12d-4bbe-4f66-b06e-cf8941233798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023627839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3023627839
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.778074669
Short name T967
Test name
Test status
Simulation time 85242751 ps
CPU time 1.27 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 219288 kb
Host smart-122e6c77-4e49-424b-8d87-a2672f1d299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778074669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.778074669
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2061741068
Short name T673
Test name
Test status
Simulation time 27233931 ps
CPU time 1.21 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 220016 kb
Host smart-05a7a58c-8007-47be-82b1-4ff5736385b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061741068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2061741068
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3526502636
Short name T118
Test name
Test status
Simulation time 27570646 ps
CPU time 0.95 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 219820 kb
Host smart-1fc5cd84-6308-45b4-89cd-66da1e5e1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526502636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3526502636
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3941409802
Short name T466
Test name
Test status
Simulation time 633811160 ps
CPU time 4.45 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 217872 kb
Host smart-e203cd13-4a03-4723-bec8-e6e6aab3d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941409802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3941409802
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.518656880
Short name T244
Test name
Test status
Simulation time 34424279 ps
CPU time 1.24 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 219124 kb
Host smart-e849f2e3-2ac5-4c3b-8eb8-64733bb31249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518656880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.518656880
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1560982093
Short name T396
Test name
Test status
Simulation time 42849589 ps
CPU time 0.83 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:53 PM PDT 24
Peak memory 207040 kb
Host smart-b07928ff-f593-40b6-affc-0117136f9e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560982093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1560982093
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2274440254
Short name T612
Test name
Test status
Simulation time 14106448 ps
CPU time 0.97 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 216732 kb
Host smart-a5777d85-f703-4b65-b3fb-c41b3afcae43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274440254 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2274440254
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2646483993
Short name T686
Test name
Test status
Simulation time 27472948 ps
CPU time 1.03 seconds
Started Jul 09 05:44:54 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 217160 kb
Host smart-f4aab9a6-f4d1-4a28-915a-7dc5367de274
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646483993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2646483993
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1730763943
Short name T973
Test name
Test status
Simulation time 28186647 ps
CPU time 0.91 seconds
Started Jul 09 05:44:55 PM PDT 24
Finished Jul 09 05:44:56 PM PDT 24
Peak memory 218696 kb
Host smart-62f03222-2ef7-418a-8586-ffeaeefb2e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730763943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1730763943
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.920901423
Short name T12
Test name
Test status
Simulation time 59911625 ps
CPU time 1.36 seconds
Started Jul 09 05:44:27 PM PDT 24
Finished Jul 09 05:44:32 PM PDT 24
Peak memory 219852 kb
Host smart-9ab439a8-7b47-47e7-9035-aa9fd60db493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920901423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.920901423
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.311738513
Short name T564
Test name
Test status
Simulation time 28427803 ps
CPU time 0.97 seconds
Started Jul 09 05:44:29 PM PDT 24
Finished Jul 09 05:44:34 PM PDT 24
Peak memory 215744 kb
Host smart-fff5a8fc-279f-42ba-88b9-c329e5669b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311738513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.311738513
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.370712340
Short name T28
Test name
Test status
Simulation time 20322082 ps
CPU time 1.01 seconds
Started Jul 09 05:44:50 PM PDT 24
Finished Jul 09 05:44:52 PM PDT 24
Peak memory 207392 kb
Host smart-75122b38-fcf9-4e23-8133-f939102ac483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370712340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.370712340
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.238640672
Short name T570
Test name
Test status
Simulation time 25446640 ps
CPU time 0.91 seconds
Started Jul 09 05:44:39 PM PDT 24
Finished Jul 09 05:44:40 PM PDT 24
Peak memory 215584 kb
Host smart-964e39f6-5a98-4e27-8ef9-23a867a414c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238640672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.238640672
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.233816414
Short name T948
Test name
Test status
Simulation time 1389254212 ps
CPU time 4.77 seconds
Started Jul 09 05:44:30 PM PDT 24
Finished Jul 09 05:44:38 PM PDT 24
Peak memory 220664 kb
Host smart-81b2cd5e-aeed-401b-b36b-19676d588733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233816414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.233816414
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2758561394
Short name T893
Test name
Test status
Simulation time 10052919466 ps
CPU time 222.42 seconds
Started Jul 09 05:44:41 PM PDT 24
Finished Jul 09 05:48:24 PM PDT 24
Peak memory 218528 kb
Host smart-46fcde9a-174b-42d7-a629-c1203ce73a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758561394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2758561394
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1566615548
Short name T986
Test name
Test status
Simulation time 23776227 ps
CPU time 1.15 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 221188 kb
Host smart-9b715cfa-7c1e-497a-9e03-e7d660722d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566615548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1566615548
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2536403933
Short name T204
Test name
Test status
Simulation time 22864937 ps
CPU time 0.91 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 218776 kb
Host smart-993ad540-40ed-4ef2-bafc-cfc86ddb57db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536403933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2536403933
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1678509187
Short name T433
Test name
Test status
Simulation time 83739580 ps
CPU time 1.12 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 218632 kb
Host smart-2ea8669f-ed88-46b4-a788-4b985188638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678509187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1678509187
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3815951769
Short name T587
Test name
Test status
Simulation time 160319448 ps
CPU time 1.29 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 218612 kb
Host smart-16fdfbfe-f597-46e0-b2eb-bdda9e503560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815951769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3815951769
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2898371455
Short name T956
Test name
Test status
Simulation time 20705138 ps
CPU time 1.12 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 219816 kb
Host smart-25db2cc5-e75f-43e2-bf3d-03d362093e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898371455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2898371455
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.969256347
Short name T522
Test name
Test status
Simulation time 47111392 ps
CPU time 0.96 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 217684 kb
Host smart-4d93caeb-e1d1-4546-8075-a3cb49f359cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969256347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.969256347
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3628972926
Short name T495
Test name
Test status
Simulation time 24370022 ps
CPU time 1.14 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 220044 kb
Host smart-2f969957-2ee1-4bdc-bebb-3ff6bbf2416b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628972926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3628972926
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.104504003
Short name T824
Test name
Test status
Simulation time 22618151 ps
CPU time 1.03 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 224268 kb
Host smart-67275671-0470-489a-a6df-60b866f53fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104504003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.104504003
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.510383867
Short name T734
Test name
Test status
Simulation time 33909572 ps
CPU time 1.47 seconds
Started Jul 09 05:45:45 PM PDT 24
Finished Jul 09 05:45:47 PM PDT 24
Peak memory 217668 kb
Host smart-3860e888-2b6e-4886-89a3-eae00ebd0184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510383867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.510383867
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2169144514
Short name T866
Test name
Test status
Simulation time 23617776 ps
CPU time 1.23 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 220140 kb
Host smart-06d0f8e2-3cd1-4642-8bad-f745facc660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169144514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2169144514
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1907126927
Short name T878
Test name
Test status
Simulation time 23860232 ps
CPU time 0.91 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 218916 kb
Host smart-c85207f4-7d52-46c2-a3ed-7d3c3d0514a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907126927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1907126927
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.634083400
Short name T821
Test name
Test status
Simulation time 75400527 ps
CPU time 2.74 seconds
Started Jul 09 05:45:49 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 215664 kb
Host smart-7f186ceb-6414-4fcf-87e4-761f6f77a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634083400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.634083400
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1662454715
Short name T645
Test name
Test status
Simulation time 101020689 ps
CPU time 1.22 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 221440 kb
Host smart-cd4673a1-a7fa-4bc8-b444-fd550518ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662454715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1662454715
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1929564536
Short name T61
Test name
Test status
Simulation time 20308138 ps
CPU time 1 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 224236 kb
Host smart-d2a6ad5b-e53c-4794-ac95-93688775d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929564536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1929564536
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.86906129
Short name T344
Test name
Test status
Simulation time 40931512 ps
CPU time 0.94 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 217728 kb
Host smart-c4d076ca-9242-438e-81a7-411e315702b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86906129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.86906129
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.91809450
Short name T598
Test name
Test status
Simulation time 26802943 ps
CPU time 1.2 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 220164 kb
Host smart-142d2f1b-c279-47ef-87f5-a9dd77ce9669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91809450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.91809450
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.4018306681
Short name T831
Test name
Test status
Simulation time 20580503 ps
CPU time 1.05 seconds
Started Jul 09 05:48:18 PM PDT 24
Finished Jul 09 05:48:19 PM PDT 24
Peak memory 220172 kb
Host smart-41b74d5e-1a96-4339-9055-ca5a0128e61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018306681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4018306681
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2164022092
Short name T314
Test name
Test status
Simulation time 34346787 ps
CPU time 1.39 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 218900 kb
Host smart-a1a82d74-b08d-4fa8-852d-7596a7a23038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164022092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2164022092
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1365772965
Short name T479
Test name
Test status
Simulation time 30364804 ps
CPU time 1.18 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 216004 kb
Host smart-9e2a49ca-0d46-4946-a15a-9bc639cbd513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365772965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1365772965
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1060449846
Short name T156
Test name
Test status
Simulation time 43327407 ps
CPU time 1.18 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 220128 kb
Host smart-baa69528-afa5-4928-8e8e-0ba2416f6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060449846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1060449846
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.616680452
Short name T343
Test name
Test status
Simulation time 250648463 ps
CPU time 2.61 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 220060 kb
Host smart-53ae41e7-97ec-4f85-a8d0-d28ea7f2d9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616680452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.616680452
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1190941208
Short name T189
Test name
Test status
Simulation time 81790716 ps
CPU time 1.18 seconds
Started Jul 09 05:46:03 PM PDT 24
Finished Jul 09 05:46:06 PM PDT 24
Peak memory 219424 kb
Host smart-1c83f516-a216-4aad-bdc4-67afdee42a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190941208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1190941208
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1658104965
Short name T58
Test name
Test status
Simulation time 23274633 ps
CPU time 1.05 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 224284 kb
Host smart-781687d3-80cb-4729-a420-9c0ae55d3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658104965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1658104965
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1738382880
Short name T99
Test name
Test status
Simulation time 48605047 ps
CPU time 1.11 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 218696 kb
Host smart-6b38b17e-c0fe-41c3-87af-86a0f14bec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738382880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1738382880
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2017123499
Short name T874
Test name
Test status
Simulation time 147599406 ps
CPU time 1.1 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 218804 kb
Host smart-e14d69ac-52e2-470d-81ce-d61e4ba1fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017123499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2017123499
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_genbits.575206881
Short name T550
Test name
Test status
Simulation time 30533006 ps
CPU time 1.23 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 220220 kb
Host smart-1612355b-1417-4cf3-8084-53ee6b7333df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575206881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.575206881
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.4269234552
Short name T987
Test name
Test status
Simulation time 42987653 ps
CPU time 1.09 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 218916 kb
Host smart-948f3d12-a64b-4bbf-a9eb-6dedbe7e301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269234552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.4269234552
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1001971316
Short name T208
Test name
Test status
Simulation time 27071810 ps
CPU time 1.02 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 219872 kb
Host smart-1227b93c-e4d7-4829-ba5f-6bd879eeb442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001971316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1001971316
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3264338344
Short name T348
Test name
Test status
Simulation time 61455137 ps
CPU time 1.01 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 217528 kb
Host smart-9f8562e7-6f36-412b-9ba8-ef50900b52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264338344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3264338344
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4241642555
Short name T397
Test name
Test status
Simulation time 53889149 ps
CPU time 1.32 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 220224 kb
Host smart-011f0621-e03d-4b6b-8a7f-d60fa81e51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241642555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4241642555
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.658723078
Short name T445
Test name
Test status
Simulation time 55490228 ps
CPU time 0.9 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:57 PM PDT 24
Peak memory 215148 kb
Host smart-7af70235-b639-4e13-a77b-eee0029528cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658723078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.658723078
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.412599373
Short name T222
Test name
Test status
Simulation time 12119917 ps
CPU time 0.85 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 216580 kb
Host smart-db9002bd-b47c-46b1-a859-7e05eb536b07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412599373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.412599373
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2456004985
Short name T120
Test name
Test status
Simulation time 76060513 ps
CPU time 1.12 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 217140 kb
Host smart-dd173f28-1424-44d7-8d45-62f8e62d0a12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456004985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2456004985
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4247649215
Short name T854
Test name
Test status
Simulation time 19538515 ps
CPU time 1.12 seconds
Started Jul 09 05:44:48 PM PDT 24
Finished Jul 09 05:44:50 PM PDT 24
Peak memory 218956 kb
Host smart-73a6fad4-8693-4ad0-9013-de8fd642d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247649215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4247649215
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3607532474
Short name T357
Test name
Test status
Simulation time 61781159 ps
CPU time 1.14 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 217644 kb
Host smart-9fe3351c-46cb-4979-88dc-fbc2e3ff09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607532474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3607532474
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2782040196
Short name T106
Test name
Test status
Simulation time 30085843 ps
CPU time 0.88 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:44:58 PM PDT 24
Peak memory 216076 kb
Host smart-0e2cda0d-9fdb-4c82-a523-18e27eed20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782040196 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2782040196
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3960374686
Short name T475
Test name
Test status
Simulation time 17941125 ps
CPU time 1.01 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 05:45:05 PM PDT 24
Peak memory 207384 kb
Host smart-08e57b30-1625-4d61-90a0-7a2aa1bfcf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960374686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3960374686
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1705878450
Short name T353
Test name
Test status
Simulation time 30795542 ps
CPU time 0.94 seconds
Started Jul 09 05:44:44 PM PDT 24
Finished Jul 09 05:44:46 PM PDT 24
Peak memory 215616 kb
Host smart-865725e4-5a33-4a38-b05b-c0f0938a87b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705878450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1705878450
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2810920642
Short name T646
Test name
Test status
Simulation time 683859216 ps
CPU time 5.6 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:04 PM PDT 24
Peak memory 218692 kb
Host smart-a6dd0254-d291-4d01-8e8c-32c6d39526ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810920642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2810920642
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.441983929
Short name T446
Test name
Test status
Simulation time 52860255521 ps
CPU time 1219.89 seconds
Started Jul 09 05:44:46 PM PDT 24
Finished Jul 09 06:05:06 PM PDT 24
Peak memory 224072 kb
Host smart-48ce6163-a7dd-4673-869a-dda4d7f31691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441983929 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.441983929
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.977207349
Short name T406
Test name
Test status
Simulation time 26017686 ps
CPU time 1.24 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 219980 kb
Host smart-24fdb79c-0d8c-4817-b453-fb9f3475c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977207349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.977207349
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2908537736
Short name T868
Test name
Test status
Simulation time 23103195 ps
CPU time 0.97 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 219912 kb
Host smart-98ac39ed-8ff3-4a38-a0ff-7cab8df3b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908537736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2908537736
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3711836437
Short name T873
Test name
Test status
Simulation time 86812446 ps
CPU time 2.14 seconds
Started Jul 09 05:46:11 PM PDT 24
Finished Jul 09 05:46:18 PM PDT 24
Peak memory 220428 kb
Host smart-a59ebc12-cd23-4eab-b385-bc1af93342c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711836437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3711836437
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1037423537
Short name T905
Test name
Test status
Simulation time 83587473 ps
CPU time 1.2 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 220024 kb
Host smart-b40ddcc2-9fe4-415c-9f89-181b1847e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037423537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1037423537
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.663553408
Short name T725
Test name
Test status
Simulation time 19143364 ps
CPU time 1.05 seconds
Started Jul 09 05:45:48 PM PDT 24
Finished Jul 09 05:45:50 PM PDT 24
Peak memory 218744 kb
Host smart-7a949e02-de4d-4a3e-bcf5-1cf2889dc4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663553408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.663553408
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3915671564
Short name T518
Test name
Test status
Simulation time 78676396 ps
CPU time 1.33 seconds
Started Jul 09 05:45:55 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 217660 kb
Host smart-e9626127-500b-49b5-92b7-3c579bdc4e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915671564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3915671564
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2117627920
Short name T799
Test name
Test status
Simulation time 24078933 ps
CPU time 1.18 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 221132 kb
Host smart-b0442bd6-2610-497b-bc4e-965a6a9f61b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117627920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2117627920
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1452215534
Short name T726
Test name
Test status
Simulation time 31575530 ps
CPU time 0.93 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:52 PM PDT 24
Peak memory 219856 kb
Host smart-b5dc5ec3-9b80-45b5-959c-68ccfdd8c21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452215534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1452215534
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3400399224
Short name T894
Test name
Test status
Simulation time 86275039 ps
CPU time 1.99 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:49 PM PDT 24
Peak memory 220528 kb
Host smart-31bb34f1-d371-4fb1-b675-8be46f964c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400399224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3400399224
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2277168999
Short name T827
Test name
Test status
Simulation time 173045352 ps
CPU time 1.39 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 220280 kb
Host smart-b9dbcb2d-4876-4670-99e1-059d35f950b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277168999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2277168999
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2486401517
Short name T155
Test name
Test status
Simulation time 42033407 ps
CPU time 1.24 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 225908 kb
Host smart-5bb3f457-263f-4c31-8259-2bdbaff2866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486401517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2486401517
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3580364459
Short name T394
Test name
Test status
Simulation time 32335017 ps
CPU time 1.51 seconds
Started Jul 09 05:46:06 PM PDT 24
Finished Jul 09 05:46:10 PM PDT 24
Peak memory 218672 kb
Host smart-a08c26fd-ade0-48bb-bb8b-efcbd833b91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580364459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3580364459
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1447784066
Short name T690
Test name
Test status
Simulation time 45706205 ps
CPU time 1.17 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 219136 kb
Host smart-3326ae99-1c26-4faa-b202-fce8a6cf4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447784066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1447784066
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.435969071
Short name T438
Test name
Test status
Simulation time 24173043 ps
CPU time 0.91 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 218724 kb
Host smart-33d6354b-5de3-4400-ac2d-08b051a78143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435969071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.435969071
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2450526181
Short name T910
Test name
Test status
Simulation time 98761779 ps
CPU time 1.41 seconds
Started Jul 09 05:45:50 PM PDT 24
Finished Jul 09 05:45:53 PM PDT 24
Peak memory 220744 kb
Host smart-4e169df9-a49a-469d-9f65-25b8a9d7c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450526181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2450526181
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1166078137
Short name T616
Test name
Test status
Simulation time 47011785 ps
CPU time 1.11 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 220220 kb
Host smart-75ae5472-5d3d-4bcb-b397-0beac79eda6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166078137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1166078137
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2271492970
Short name T685
Test name
Test status
Simulation time 28559738 ps
CPU time 0.86 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 218788 kb
Host smart-532d37ab-5aa5-4871-bd5d-0e35b0df5511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271492970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2271492970
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1628831341
Short name T337
Test name
Test status
Simulation time 59300867 ps
CPU time 1.12 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 217592 kb
Host smart-f676eee2-4777-4d60-a04f-fe5e28289a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628831341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1628831341
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.3394326161
Short name T906
Test name
Test status
Simulation time 25556661 ps
CPU time 1.19 seconds
Started Jul 09 05:45:53 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 221248 kb
Host smart-7637233f-09b3-40cb-80de-db10e3ed1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394326161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3394326161
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1622692826
Short name T771
Test name
Test status
Simulation time 19452429 ps
CPU time 1.16 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 229820 kb
Host smart-43479632-7312-4942-bab1-6233ce41df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622692826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1622692826
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3932554374
Short name T926
Test name
Test status
Simulation time 163409345 ps
CPU time 1.05 seconds
Started Jul 09 05:45:45 PM PDT 24
Finished Jul 09 05:45:47 PM PDT 24
Peak memory 217692 kb
Host smart-03ee2ef4-d539-4a98-8398-9b153ed18fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932554374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3932554374
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3147438974
Short name T428
Test name
Test status
Simulation time 18593111 ps
CPU time 1.04 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 218828 kb
Host smart-742b737d-b183-4f3a-8922-f650fb0d7cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147438974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3147438974
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3644361826
Short name T358
Test name
Test status
Simulation time 59888457 ps
CPU time 1.26 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 217684 kb
Host smart-147f7fc3-550a-49b2-a5e7-86ab6f04d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644361826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3644361826
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3566212130
Short name T2
Test name
Test status
Simulation time 36575039 ps
CPU time 1.09 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 220076 kb
Host smart-0a50078f-4de1-4508-8001-14e285878f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566212130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3566212130
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3729452532
Short name T666
Test name
Test status
Simulation time 46217034 ps
CPU time 0.8 seconds
Started Jul 09 05:45:46 PM PDT 24
Finished Jul 09 05:45:48 PM PDT 24
Peak memory 218620 kb
Host smart-6f9642e1-98a3-4391-ad11-7a5e49164c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729452532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3729452532
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.411665728
Short name T919
Test name
Test status
Simulation time 46502492 ps
CPU time 1.15 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 217680 kb
Host smart-5a708c94-360e-426e-94f5-46ba8e412be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411665728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.411665728
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.887085354
Short name T489
Test name
Test status
Simulation time 51105058 ps
CPU time 1.27 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 221572 kb
Host smart-721cba4a-abff-4f38-bfbb-5a3178ee877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887085354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.887085354
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.241482526
Short name T195
Test name
Test status
Simulation time 19151090 ps
CPU time 1.16 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 219916 kb
Host smart-10a77125-9dfc-497b-a136-0a06aacdda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241482526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.241482526
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.143052495
Short name T383
Test name
Test status
Simulation time 37906751 ps
CPU time 1.43 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 217840 kb
Host smart-8b995023-b1cf-49a1-a318-4d9f4100d9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143052495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.143052495
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2924951598
Short name T562
Test name
Test status
Simulation time 82911007 ps
CPU time 1.37 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:54 PM PDT 24
Peak memory 220416 kb
Host smart-b1bc8c1d-2e8c-4438-9416-9a6ce4006973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924951598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2924951598
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.229017199
Short name T405
Test name
Test status
Simulation time 19751148 ps
CPU time 0.81 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:51 PM PDT 24
Peak memory 207060 kb
Host smart-6dabb42c-1bdf-46b5-b068-63517950aca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229017199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.229017199
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1628339445
Short name T502
Test name
Test status
Simulation time 28437227 ps
CPU time 0.84 seconds
Started Jul 09 05:44:36 PM PDT 24
Finished Jul 09 05:44:37 PM PDT 24
Peak memory 216220 kb
Host smart-738dcd78-d5b3-45a0-a08c-5406ea836f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628339445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1628339445
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1647630626
Short name T83
Test name
Test status
Simulation time 42180578 ps
CPU time 1.34 seconds
Started Jul 09 05:44:43 PM PDT 24
Finished Jul 09 05:44:45 PM PDT 24
Peak memory 219584 kb
Host smart-de8a425a-ca17-4d1c-a7a8-7af65f151f5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647630626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1647630626
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1190548524
Short name T63
Test name
Test status
Simulation time 52097430 ps
CPU time 1.1 seconds
Started Jul 09 05:44:58 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 229948 kb
Host smart-b6bfff95-5c38-456b-8c0f-aa93e4ee8134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190548524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1190548524
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1341931120
Short name T876
Test name
Test status
Simulation time 207596324 ps
CPU time 3.15 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:53 PM PDT 24
Peak memory 220428 kb
Host smart-414651e8-ab97-4836-8bf3-7c63fb8f8ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341931120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1341931120
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3080517558
Short name T609
Test name
Test status
Simulation time 33492474 ps
CPU time 0.99 seconds
Started Jul 09 05:44:49 PM PDT 24
Finished Jul 09 05:44:50 PM PDT 24
Peak memory 224272 kb
Host smart-2a9c6775-4b5f-46d3-a447-eba3a8364d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080517558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3080517558
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1934888835
Short name T925
Test name
Test status
Simulation time 29605443 ps
CPU time 0.88 seconds
Started Jul 09 05:44:52 PM PDT 24
Finished Jul 09 05:44:53 PM PDT 24
Peak memory 207416 kb
Host smart-aafd7b19-ce3f-4356-8aa0-4896ea8a4950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934888835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1934888835
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1997959940
Short name T606
Test name
Test status
Simulation time 64141667 ps
CPU time 0.89 seconds
Started Jul 09 05:44:33 PM PDT 24
Finished Jul 09 05:44:36 PM PDT 24
Peak memory 215628 kb
Host smart-8b99a59e-324e-4d12-bac8-adce34ba6b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997959940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1997959940
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3621790766
Short name T703
Test name
Test status
Simulation time 290599465 ps
CPU time 3.45 seconds
Started Jul 09 05:44:56 PM PDT 24
Finished Jul 09 05:45:00 PM PDT 24
Peak memory 217468 kb
Host smart-09234e3e-d3c6-459a-a4d9-607be45f6ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621790766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3621790766
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2564553838
Short name T238
Test name
Test status
Simulation time 124394529872 ps
CPU time 1342.9 seconds
Started Jul 09 05:44:46 PM PDT 24
Finished Jul 09 06:07:10 PM PDT 24
Peak memory 224340 kb
Host smart-6e521eca-3ff5-46cb-b7a2-f9bf01f811a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564553838 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2564553838
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.440797149
Short name T715
Test name
Test status
Simulation time 41198455 ps
CPU time 1.15 seconds
Started Jul 09 05:46:08 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 219148 kb
Host smart-0de630f2-0fc8-412b-880e-40aceef33600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440797149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.440797149
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3146497517
Short name T708
Test name
Test status
Simulation time 49802509 ps
CPU time 1.02 seconds
Started Jul 09 05:45:54 PM PDT 24
Finished Jul 09 05:45:56 PM PDT 24
Peak memory 218860 kb
Host smart-6321c7dd-27f4-47e8-8a39-2a8a6db9d02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146497517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3146497517
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1147940301
Short name T307
Test name
Test status
Simulation time 69204544 ps
CPU time 1.17 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 217732 kb
Host smart-76f976dc-a696-4228-89e5-cdb15ba80153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147940301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1147940301
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3949267870
Short name T838
Test name
Test status
Simulation time 40862443 ps
CPU time 1.3 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 220532 kb
Host smart-ae3865b9-ab33-4c77-aa49-c6fb3b1c4b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949267870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3949267870
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.619362991
Short name T175
Test name
Test status
Simulation time 31506469 ps
CPU time 0.89 seconds
Started Jul 09 05:45:55 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 218648 kb
Host smart-c5376e91-4849-4ec9-842c-0612427e998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619362991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.619362991
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4206792825
Short name T877
Test name
Test status
Simulation time 48115994 ps
CPU time 1.56 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 218848 kb
Host smart-c6a263b4-5f09-4152-ae0f-1c3689d3da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206792825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4206792825
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3922970952
Short name T770
Test name
Test status
Simulation time 130004535 ps
CPU time 1.25 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 216004 kb
Host smart-fb13f989-7b0a-42d0-8114-6510e799486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922970952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3922970952
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.915881229
Short name T167
Test name
Test status
Simulation time 81060459 ps
CPU time 0.97 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 224080 kb
Host smart-a7a2778b-21d6-4d05-bce3-1d2ca089a5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915881229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.915881229
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3659145436
Short name T975
Test name
Test status
Simulation time 124391539 ps
CPU time 0.96 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 217644 kb
Host smart-cffd5f0a-5dc9-419c-9c36-2638a53ffb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659145436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3659145436
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.592942985
Short name T248
Test name
Test status
Simulation time 325796027 ps
CPU time 1.37 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 218732 kb
Host smart-c570d709-0767-4bd7-8bc7-daf27951b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592942985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.592942985
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3916706069
Short name T603
Test name
Test status
Simulation time 50602636 ps
CPU time 0.88 seconds
Started Jul 09 05:45:51 PM PDT 24
Finished Jul 09 05:45:54 PM PDT 24
Peak memory 218596 kb
Host smart-2e24e022-2875-4252-be87-4457b32fc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916706069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3916706069
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1864396675
Short name T336
Test name
Test status
Simulation time 84289120 ps
CPU time 3.05 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:04 PM PDT 24
Peak memory 220452 kb
Host smart-a5169d42-2b80-4858-992c-b8e617a6fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864396675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1864396675
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3350866487
Short name T525
Test name
Test status
Simulation time 107402159 ps
CPU time 1.07 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 220040 kb
Host smart-9295a313-84c7-4422-89ee-f00b763f583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350866487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3350866487
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1819729268
Short name T217
Test name
Test status
Simulation time 25309002 ps
CPU time 1.1 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:00 PM PDT 24
Peak memory 229824 kb
Host smart-2dc38785-e0cf-458a-9683-f3fb122d2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819729268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1819729268
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.64797703
Short name T534
Test name
Test status
Simulation time 84977702 ps
CPU time 1.51 seconds
Started Jul 09 05:46:05 PM PDT 24
Finished Jul 09 05:46:14 PM PDT 24
Peak memory 219316 kb
Host smart-5f5c9847-dffe-4580-a155-a8fa8b90d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64797703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.64797703
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2695496601
Short name T943
Test name
Test status
Simulation time 24622167 ps
CPU time 1.18 seconds
Started Jul 09 05:45:55 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 219592 kb
Host smart-ae0d733e-0499-440b-ba88-815efe889020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695496601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2695496601
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2038990080
Short name T162
Test name
Test status
Simulation time 24871383 ps
CPU time 0.89 seconds
Started Jul 09 05:45:55 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 218944 kb
Host smart-1ea0ac17-1505-431b-a4b4-9030b9f03e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038990080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2038990080
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.479223873
Short name T755
Test name
Test status
Simulation time 102086236 ps
CPU time 1.55 seconds
Started Jul 09 05:46:00 PM PDT 24
Finished Jul 09 05:46:02 PM PDT 24
Peak memory 219388 kb
Host smart-4932d806-a489-4006-90f0-20280b189dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479223873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.479223873
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3426301867
Short name T270
Test name
Test status
Simulation time 403745368 ps
CPU time 1.21 seconds
Started Jul 09 05:45:52 PM PDT 24
Finished Jul 09 05:45:55 PM PDT 24
Peak memory 218780 kb
Host smart-7b2c7dce-6fc9-4109-9256-440f9cbc63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426301867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3426301867
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1814200770
Short name T6
Test name
Test status
Simulation time 28080379 ps
CPU time 1.23 seconds
Started Jul 09 05:46:02 PM PDT 24
Finished Jul 09 05:46:05 PM PDT 24
Peak memory 220836 kb
Host smart-b1a0c738-0b88-4835-a6da-2b3068321250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814200770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1814200770
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.184294059
Short name T545
Test name
Test status
Simulation time 23410315 ps
CPU time 1.15 seconds
Started Jul 09 05:46:10 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 218948 kb
Host smart-7c646a1f-acc2-4d77-b70b-18e2daa330cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184294059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.184294059
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1757194823
Short name T704
Test name
Test status
Simulation time 40283540 ps
CPU time 1.18 seconds
Started Jul 09 05:46:16 PM PDT 24
Finished Jul 09 05:46:22 PM PDT 24
Peak memory 219268 kb
Host smart-04ef6f6a-963f-42b8-bf41-7d991117e9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757194823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1757194823
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1951836281
Short name T411
Test name
Test status
Simulation time 27077851 ps
CPU time 0.9 seconds
Started Jul 09 05:46:04 PM PDT 24
Finished Jul 09 05:46:07 PM PDT 24
Peak memory 218744 kb
Host smart-90288036-ea72-4e1c-a364-25ada870cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951836281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1951836281
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3178208679
Short name T65
Test name
Test status
Simulation time 52280690 ps
CPU time 1.07 seconds
Started Jul 09 05:46:07 PM PDT 24
Finished Jul 09 05:46:11 PM PDT 24
Peak memory 219132 kb
Host smart-35022899-0740-4992-bcec-2058e66e6ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178208679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3178208679
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2570118988
Short name T166
Test name
Test status
Simulation time 28221950 ps
CPU time 1.17 seconds
Started Jul 09 05:46:09 PM PDT 24
Finished Jul 09 05:46:13 PM PDT 24
Peak memory 220076 kb
Host smart-2346a7f2-a6e9-4bb7-9fc5-f6b85fb673cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570118988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2570118988
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3467124074
Short name T64
Test name
Test status
Simulation time 30099825 ps
CPU time 0.96 seconds
Started Jul 09 05:45:59 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 224108 kb
Host smart-1100e3c2-9521-4b25-b996-57f170af3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467124074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3467124074
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.89293775
Short name T399
Test name
Test status
Simulation time 109814223 ps
CPU time 1.26 seconds
Started Jul 09 05:45:58 PM PDT 24
Finished Jul 09 05:46:01 PM PDT 24
Peak memory 220236 kb
Host smart-123e8685-d557-4a74-9ce7-93452f60f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89293775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.89293775
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3997454820
Short name T223
Test name
Test status
Simulation time 55706144 ps
CPU time 1.3 seconds
Started Jul 09 05:46:01 PM PDT 24
Finished Jul 09 05:46:03 PM PDT 24
Peak memory 220308 kb
Host smart-26ae0a07-80cb-4c25-920e-2031cf1e3620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997454820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3997454820
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3753671123
Short name T591
Test name
Test status
Simulation time 29151097 ps
CPU time 0.83 seconds
Started Jul 09 05:46:14 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 218504 kb
Host smart-75e8989f-17dd-4ea4-a12c-6faa3e11c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753671123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3753671123
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3617128333
Short name T381
Test name
Test status
Simulation time 38445876 ps
CPU time 1.47 seconds
Started Jul 09 05:45:56 PM PDT 24
Finished Jul 09 05:45:58 PM PDT 24
Peak memory 217748 kb
Host smart-e179c73f-f3b2-4923-9cd3-018e27631662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617128333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3617128333
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%