Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.60 98.25 93.85 97.02 91.86 96.37 99.77 92.08


Total test records in report: 1130
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T1021 /workspace/coverage/cover_reg_top/31.edn_intr_test.1933651644 Jul 10 05:40:24 PM PDT 24 Jul 10 05:40:26 PM PDT 24 15480487 ps
T1022 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3013678421 Jul 10 05:40:11 PM PDT 24 Jul 10 05:40:15 PM PDT 24 165326799 ps
T1023 /workspace/coverage/cover_reg_top/22.edn_intr_test.714394541 Jul 10 05:40:21 PM PDT 24 Jul 10 05:40:23 PM PDT 24 22794187 ps
T261 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1497974972 Jul 10 05:39:43 PM PDT 24 Jul 10 05:39:45 PM PDT 24 12083494 ps
T1024 /workspace/coverage/cover_reg_top/13.edn_tl_errors.147421905 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:08 PM PDT 24 148387347 ps
T1025 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1678593544 Jul 10 05:40:11 PM PDT 24 Jul 10 05:40:15 PM PDT 24 77625501 ps
T1026 /workspace/coverage/cover_reg_top/25.edn_intr_test.3165239023 Jul 10 05:40:20 PM PDT 24 Jul 10 05:40:22 PM PDT 24 92136510 ps
T280 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1100406794 Jul 10 05:40:15 PM PDT 24 Jul 10 05:40:17 PM PDT 24 41407676 ps
T262 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3205411743 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:06 PM PDT 24 16307881 ps
T1027 /workspace/coverage/cover_reg_top/0.edn_intr_test.1822919054 Jul 10 05:39:27 PM PDT 24 Jul 10 05:39:29 PM PDT 24 43113167 ps
T1028 /workspace/coverage/cover_reg_top/2.edn_tl_errors.463381625 Jul 10 05:39:39 PM PDT 24 Jul 10 05:39:42 PM PDT 24 184793411 ps
T1029 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1554893214 Jul 10 05:40:03 PM PDT 24 Jul 10 05:40:08 PM PDT 24 105595577 ps
T1030 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4074507038 Jul 10 05:39:49 PM PDT 24 Jul 10 05:39:50 PM PDT 24 106637442 ps
T263 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3830134028 Jul 10 05:40:14 PM PDT 24 Jul 10 05:40:15 PM PDT 24 23859781 ps
T281 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3498399672 Jul 10 05:40:08 PM PDT 24 Jul 10 05:40:10 PM PDT 24 29312875 ps
T1031 /workspace/coverage/cover_reg_top/16.edn_intr_test.3818593688 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:18 PM PDT 24 11887876 ps
T1032 /workspace/coverage/cover_reg_top/26.edn_intr_test.1746322426 Jul 10 05:40:21 PM PDT 24 Jul 10 05:40:23 PM PDT 24 54680035 ps
T288 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4177285525 Jul 10 05:39:45 PM PDT 24 Jul 10 05:39:48 PM PDT 24 427990335 ps
T1033 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.339487378 Jul 10 05:40:00 PM PDT 24 Jul 10 05:40:02 PM PDT 24 22411895 ps
T1034 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.481202810 Jul 10 05:39:44 PM PDT 24 Jul 10 05:39:46 PM PDT 24 87277049 ps
T1035 /workspace/coverage/cover_reg_top/35.edn_intr_test.3876526507 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 34854792 ps
T1036 /workspace/coverage/cover_reg_top/33.edn_intr_test.165904725 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 129550639 ps
T264 /workspace/coverage/cover_reg_top/3.edn_csr_rw.267410685 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:40 PM PDT 24 14753813 ps
T1037 /workspace/coverage/cover_reg_top/11.edn_csr_rw.725535720 Jul 10 05:40:03 PM PDT 24 Jul 10 05:40:05 PM PDT 24 22190704 ps
T1038 /workspace/coverage/cover_reg_top/5.edn_intr_test.546612073 Jul 10 05:39:46 PM PDT 24 Jul 10 05:39:48 PM PDT 24 13699488 ps
T1039 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2246098271 Jul 10 05:40:05 PM PDT 24 Jul 10 05:40:09 PM PDT 24 37518466 ps
T291 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3630732594 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:08 PM PDT 24 292449723 ps
T1040 /workspace/coverage/cover_reg_top/17.edn_intr_test.1350903694 Jul 10 05:40:17 PM PDT 24 Jul 10 05:40:19 PM PDT 24 14585928 ps
T1041 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3543318168 Jul 10 05:39:50 PM PDT 24 Jul 10 05:39:53 PM PDT 24 56727594 ps
T292 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3819144950 Jul 10 05:40:05 PM PDT 24 Jul 10 05:40:09 PM PDT 24 85613192 ps
T1042 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1594040287 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:18 PM PDT 24 44814306 ps
T293 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1040076287 Jul 10 05:40:00 PM PDT 24 Jul 10 05:40:02 PM PDT 24 402156661 ps
T1043 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3786880292 Jul 10 05:40:15 PM PDT 24 Jul 10 05:40:18 PM PDT 24 56455257 ps
T1044 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2749432583 Jul 10 05:39:40 PM PDT 24 Jul 10 05:39:42 PM PDT 24 15626477 ps
T1045 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3075324283 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:20 PM PDT 24 66712327 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.28122060 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:20 PM PDT 24 93321818 ps
T1047 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.35191798 Jul 10 05:39:39 PM PDT 24 Jul 10 05:39:42 PM PDT 24 50726619 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4046086137 Jul 10 05:39:37 PM PDT 24 Jul 10 05:39:39 PM PDT 24 28369691 ps
T1049 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.729582321 Jul 10 05:40:11 PM PDT 24 Jul 10 05:40:15 PM PDT 24 269053134 ps
T1050 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2953581639 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:40 PM PDT 24 541259873 ps
T1051 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1081643162 Jul 10 05:40:11 PM PDT 24 Jul 10 05:40:15 PM PDT 24 90878088 ps
T1052 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.681726311 Jul 10 05:39:41 PM PDT 24 Jul 10 05:39:43 PM PDT 24 64649172 ps
T1053 /workspace/coverage/cover_reg_top/34.edn_intr_test.2407358599 Jul 10 05:40:23 PM PDT 24 Jul 10 05:40:25 PM PDT 24 14456627 ps
T265 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.286494723 Jul 10 05:39:27 PM PDT 24 Jul 10 05:39:29 PM PDT 24 40369938 ps
T1054 /workspace/coverage/cover_reg_top/2.edn_intr_test.2914115535 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:40 PM PDT 24 18323553 ps
T1055 /workspace/coverage/cover_reg_top/27.edn_intr_test.583327476 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 69927768 ps
T1056 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2129314287 Jul 10 05:40:15 PM PDT 24 Jul 10 05:40:17 PM PDT 24 78633862 ps
T1057 /workspace/coverage/cover_reg_top/44.edn_intr_test.1520998232 Jul 10 05:40:28 PM PDT 24 Jul 10 05:40:30 PM PDT 24 29475240 ps
T1058 /workspace/coverage/cover_reg_top/30.edn_intr_test.589135351 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:25 PM PDT 24 12273014 ps
T1059 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3470983448 Jul 10 05:39:52 PM PDT 24 Jul 10 05:39:54 PM PDT 24 18624924 ps
T1060 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3918968969 Jul 10 05:39:56 PM PDT 24 Jul 10 05:39:58 PM PDT 24 82165714 ps
T1061 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3932757826 Jul 10 05:39:34 PM PDT 24 Jul 10 05:39:37 PM PDT 24 30074114 ps
T1062 /workspace/coverage/cover_reg_top/40.edn_intr_test.3664936908 Jul 10 05:40:28 PM PDT 24 Jul 10 05:40:30 PM PDT 24 14033891 ps
T266 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3198067910 Jul 10 05:39:32 PM PDT 24 Jul 10 05:39:34 PM PDT 24 126564947 ps
T1063 /workspace/coverage/cover_reg_top/21.edn_intr_test.2923291918 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 14746404 ps
T1064 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1552412561 Jul 10 05:40:05 PM PDT 24 Jul 10 05:40:08 PM PDT 24 107186265 ps
T1065 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.308417569 Jul 10 05:40:09 PM PDT 24 Jul 10 05:40:12 PM PDT 24 32732808 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4108331929 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:45 PM PDT 24 675972682 ps
T1067 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2874337198 Jul 10 05:40:14 PM PDT 24 Jul 10 05:40:18 PM PDT 24 74474669 ps
T1068 /workspace/coverage/cover_reg_top/20.edn_intr_test.2405618362 Jul 10 05:40:24 PM PDT 24 Jul 10 05:40:26 PM PDT 24 46973510 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4048205152 Jul 10 05:40:21 PM PDT 24 Jul 10 05:40:23 PM PDT 24 29818391 ps
T1070 /workspace/coverage/cover_reg_top/19.edn_intr_test.132905778 Jul 10 05:40:23 PM PDT 24 Jul 10 05:40:25 PM PDT 24 13696815 ps
T1071 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1843197130 Jul 10 05:40:10 PM PDT 24 Jul 10 05:40:13 PM PDT 24 122732791 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3405640864 Jul 10 05:39:45 PM PDT 24 Jul 10 05:39:47 PM PDT 24 218130448 ps
T1073 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2988659539 Jul 10 05:39:52 PM PDT 24 Jul 10 05:39:55 PM PDT 24 27804021 ps
T1074 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1042536730 Jul 10 05:39:58 PM PDT 24 Jul 10 05:40:00 PM PDT 24 13544672 ps
T1075 /workspace/coverage/cover_reg_top/38.edn_intr_test.2080296418 Jul 10 05:40:32 PM PDT 24 Jul 10 05:40:33 PM PDT 24 48574256 ps
T1076 /workspace/coverage/cover_reg_top/29.edn_intr_test.2213652134 Jul 10 05:40:21 PM PDT 24 Jul 10 05:40:23 PM PDT 24 25782284 ps
T1077 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.53664812 Jul 10 05:39:53 PM PDT 24 Jul 10 05:39:55 PM PDT 24 296394324 ps
T267 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2169034166 Jul 10 05:39:47 PM PDT 24 Jul 10 05:39:49 PM PDT 24 39672923 ps
T268 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2118024693 Jul 10 05:39:35 PM PDT 24 Jul 10 05:39:37 PM PDT 24 125131187 ps
T270 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3692216623 Jul 10 05:40:05 PM PDT 24 Jul 10 05:40:07 PM PDT 24 28405177 ps
T1078 /workspace/coverage/cover_reg_top/37.edn_intr_test.2345253581 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 14851656 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1632506883 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:40 PM PDT 24 28252778 ps
T1080 /workspace/coverage/cover_reg_top/36.edn_intr_test.1397133334 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:25 PM PDT 24 49871748 ps
T1081 /workspace/coverage/cover_reg_top/48.edn_intr_test.1403248096 Jul 10 05:40:29 PM PDT 24 Jul 10 05:40:31 PM PDT 24 97210557 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4017215588 Jul 10 05:39:45 PM PDT 24 Jul 10 05:39:49 PM PDT 24 180045399 ps
T269 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.634330210 Jul 10 05:39:32 PM PDT 24 Jul 10 05:39:35 PM PDT 24 83231081 ps
T1083 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.687739143 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:19 PM PDT 24 154310720 ps
T1084 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1746172835 Jul 10 05:40:03 PM PDT 24 Jul 10 05:40:04 PM PDT 24 27435592 ps
T1085 /workspace/coverage/cover_reg_top/41.edn_intr_test.3995499883 Jul 10 05:40:30 PM PDT 24 Jul 10 05:40:31 PM PDT 24 24620007 ps
T1086 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1425019169 Jul 10 05:39:50 PM PDT 24 Jul 10 05:39:52 PM PDT 24 31639911 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_intr_test.3847513351 Jul 10 05:39:52 PM PDT 24 Jul 10 05:39:54 PM PDT 24 28757780 ps
T1088 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.796903669 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:06 PM PDT 24 44565366 ps
T1089 /workspace/coverage/cover_reg_top/11.edn_intr_test.438889320 Jul 10 05:40:07 PM PDT 24 Jul 10 05:40:08 PM PDT 24 12828952 ps
T1090 /workspace/coverage/cover_reg_top/28.edn_intr_test.28441303 Jul 10 05:40:23 PM PDT 24 Jul 10 05:40:25 PM PDT 24 16642698 ps
T1091 /workspace/coverage/cover_reg_top/43.edn_intr_test.412894820 Jul 10 05:40:28 PM PDT 24 Jul 10 05:40:30 PM PDT 24 24926435 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.150645588 Jul 10 05:40:10 PM PDT 24 Jul 10 05:40:13 PM PDT 24 33422592 ps
T1093 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1667764311 Jul 10 05:40:17 PM PDT 24 Jul 10 05:40:19 PM PDT 24 84836732 ps
T1094 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2077839952 Jul 10 05:40:08 PM PDT 24 Jul 10 05:40:11 PM PDT 24 68455741 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3687216087 Jul 10 05:40:18 PM PDT 24 Jul 10 05:40:21 PM PDT 24 452787790 ps
T272 /workspace/coverage/cover_reg_top/6.edn_csr_rw.4188218278 Jul 10 05:39:51 PM PDT 24 Jul 10 05:39:53 PM PDT 24 21445324 ps
T273 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2227632048 Jul 10 05:40:20 PM PDT 24 Jul 10 05:40:22 PM PDT 24 14775935 ps
T1096 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3065452681 Jul 10 05:39:40 PM PDT 24 Jul 10 05:39:42 PM PDT 24 14778190 ps
T271 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1888319490 Jul 10 05:40:15 PM PDT 24 Jul 10 05:40:17 PM PDT 24 17993010 ps
T1097 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3414293449 Jul 10 05:39:29 PM PDT 24 Jul 10 05:39:31 PM PDT 24 23868528 ps
T1098 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2202151162 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:06 PM PDT 24 17650048 ps
T1099 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2996124114 Jul 10 05:39:47 PM PDT 24 Jul 10 05:39:49 PM PDT 24 21797590 ps
T1100 /workspace/coverage/cover_reg_top/23.edn_intr_test.3914025346 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:24 PM PDT 24 18233590 ps
T1101 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3317584588 Jul 10 05:39:34 PM PDT 24 Jul 10 05:39:36 PM PDT 24 50726565 ps
T1102 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1114027901 Jul 10 05:40:19 PM PDT 24 Jul 10 05:40:21 PM PDT 24 45519412 ps
T1103 /workspace/coverage/cover_reg_top/49.edn_intr_test.3951961817 Jul 10 05:40:30 PM PDT 24 Jul 10 05:40:31 PM PDT 24 12350546 ps
T1104 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3833514767 Jul 10 05:39:52 PM PDT 24 Jul 10 05:39:54 PM PDT 24 44979209 ps
T1105 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2200478695 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:07 PM PDT 24 241548994 ps
T1106 /workspace/coverage/cover_reg_top/10.edn_intr_test.2518728075 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:06 PM PDT 24 80014122 ps
T1107 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2109748474 Jul 10 05:39:57 PM PDT 24 Jul 10 05:39:59 PM PDT 24 20395658 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.320729329 Jul 10 05:40:09 PM PDT 24 Jul 10 05:40:13 PM PDT 24 109071685 ps
T1109 /workspace/coverage/cover_reg_top/24.edn_intr_test.4056623012 Jul 10 05:40:22 PM PDT 24 Jul 10 05:40:25 PM PDT 24 15522905 ps
T1110 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1140031007 Jul 10 05:39:32 PM PDT 24 Jul 10 05:39:34 PM PDT 24 69427887 ps
T1111 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4058569443 Jul 10 05:40:09 PM PDT 24 Jul 10 05:40:11 PM PDT 24 66475423 ps
T1112 /workspace/coverage/cover_reg_top/7.edn_intr_test.2982768678 Jul 10 05:39:57 PM PDT 24 Jul 10 05:39:59 PM PDT 24 25149964 ps
T1113 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3281774213 Jul 10 05:39:38 PM PDT 24 Jul 10 05:39:40 PM PDT 24 46887659 ps
T1114 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.626843554 Jul 10 05:40:03 PM PDT 24 Jul 10 05:40:06 PM PDT 24 22891746 ps
T1115 /workspace/coverage/cover_reg_top/9.edn_intr_test.2340209895 Jul 10 05:39:56 PM PDT 24 Jul 10 05:39:58 PM PDT 24 11804497 ps
T1116 /workspace/coverage/cover_reg_top/47.edn_intr_test.1122462334 Jul 10 05:40:26 PM PDT 24 Jul 10 05:40:28 PM PDT 24 34412408 ps
T1117 /workspace/coverage/cover_reg_top/1.edn_csr_rw.943335288 Jul 10 05:39:34 PM PDT 24 Jul 10 05:39:36 PM PDT 24 17399889 ps
T1118 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1499913302 Jul 10 05:40:07 PM PDT 24 Jul 10 05:40:09 PM PDT 24 98505192 ps
T1119 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2341115828 Jul 10 05:40:09 PM PDT 24 Jul 10 05:40:12 PM PDT 24 175911251 ps
T1120 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4174794698 Jul 10 05:39:40 PM PDT 24 Jul 10 05:39:44 PM PDT 24 324772834 ps
T1121 /workspace/coverage/cover_reg_top/15.edn_intr_test.3981283391 Jul 10 05:40:11 PM PDT 24 Jul 10 05:40:13 PM PDT 24 15030008 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4237065576 Jul 10 05:39:27 PM PDT 24 Jul 10 05:39:30 PM PDT 24 162572121 ps
T1123 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1348162820 Jul 10 05:39:57 PM PDT 24 Jul 10 05:39:59 PM PDT 24 32236962 ps
T1124 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2570615050 Jul 10 05:40:04 PM PDT 24 Jul 10 05:40:07 PM PDT 24 261352003 ps
T274 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1963368321 Jul 10 05:40:16 PM PDT 24 Jul 10 05:40:18 PM PDT 24 27039253 ps
T1125 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1653053524 Jul 10 05:39:34 PM PDT 24 Jul 10 05:39:36 PM PDT 24 215860910 ps
T1126 /workspace/coverage/cover_reg_top/15.edn_tl_errors.963893037 Jul 10 05:40:10 PM PDT 24 Jul 10 05:40:14 PM PDT 24 170350008 ps
T1127 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1406062737 Jul 10 05:40:23 PM PDT 24 Jul 10 05:40:26 PM PDT 24 15639642 ps
T1128 /workspace/coverage/cover_reg_top/18.edn_intr_test.4138775862 Jul 10 05:40:15 PM PDT 24 Jul 10 05:40:17 PM PDT 24 164586937 ps
T1129 /workspace/coverage/cover_reg_top/3.edn_intr_test.793157618 Jul 10 05:39:39 PM PDT 24 Jul 10 05:39:41 PM PDT 24 15275000 ps
T1130 /workspace/coverage/cover_reg_top/12.edn_intr_test.1531962390 Jul 10 05:40:03 PM PDT 24 Jul 10 05:40:05 PM PDT 24 13647957 ps

Test location /workspace/coverage/default/7.edn_genbits.1155543961
Short name T2
Test name
Test status
Simulation time 208371336 ps
CPU time 1.71 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:02 PM PDT 24
Peak memory 217832 kb
Host smart-1d1d15e6-f664-4f79-9ac7-221db52c86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155543961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1155543961
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1843326387
Short name T5
Test name
Test status
Simulation time 161178707798 ps
CPU time 1100.18 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:40:34 PM PDT 24
Peak memory 225036 kb
Host smart-f16c5a8f-e1a7-40dd-a516-d7d452c8ae37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843326387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1843326387
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.2683805022
Short name T18
Test name
Test status
Simulation time 37603919 ps
CPU time 1.22 seconds
Started Jul 10 07:22:12 PM PDT 24
Finished Jul 10 07:22:17 PM PDT 24
Peak memory 220412 kb
Host smart-bd6eb2fd-21c7-4fb8-9610-8fbf839058de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683805022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2683805022
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4132597789
Short name T16
Test name
Test status
Simulation time 692699458 ps
CPU time 4.17 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 242296 kb
Host smart-921561a4-72f0-4635-ae5c-6b72074a1049
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132597789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4132597789
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_err.1165837847
Short name T87
Test name
Test status
Simulation time 22273324 ps
CPU time 0.98 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 218040 kb
Host smart-4dacb91c-f8e4-4bd8-a5e6-d68389338ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165837847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1165837847
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/196.edn_alert.688069826
Short name T112
Test name
Test status
Simulation time 27558428 ps
CPU time 1.23 seconds
Started Jul 10 07:24:02 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 219828 kb
Host smart-f3176194-9359-452e-9181-ccff5a5ea67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688069826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.688069826
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1040990513
Short name T22
Test name
Test status
Simulation time 226010622 ps
CPU time 1.2 seconds
Started Jul 10 07:22:43 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 217348 kb
Host smart-27d26f68-dff2-4b73-b2ef-ecdaa39bbc97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040990513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1040990513
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3050006862
Short name T19
Test name
Test status
Simulation time 529291460 ps
CPU time 7.2 seconds
Started Jul 10 07:21:46 PM PDT 24
Finished Jul 10 07:21:56 PM PDT 24
Peak memory 237976 kb
Host smart-93cd2976-1619-4abc-a951-8b6d8f949e09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050006862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3050006862
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/28.edn_disable.1598253782
Short name T187
Test name
Test status
Simulation time 18032510 ps
CPU time 0.86 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 216732 kb
Host smart-ae359ed7-8aaa-4a9e-bd40-5baa2183fdc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598253782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1598253782
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2565520514
Short name T79
Test name
Test status
Simulation time 12088432214 ps
CPU time 259.96 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:26:26 PM PDT 24
Peak memory 218700 kb
Host smart-f6909edb-3650-4bfe-8ffb-95f301ea3873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565520514 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2565520514
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2969573921
Short name T31
Test name
Test status
Simulation time 40211597 ps
CPU time 1.07 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:12 PM PDT 24
Peak memory 215992 kb
Host smart-07b407fa-4014-4192-b64a-9f59f6a56ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969573921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2969573921
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.2401575840
Short name T648
Test name
Test status
Simulation time 90843078 ps
CPU time 0.98 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 207440 kb
Host smart-c3eea654-95b6-45fb-a108-3612c93274c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401575840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2401575840
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_disable.1643822834
Short name T99
Test name
Test status
Simulation time 39697107 ps
CPU time 0.86 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 216552 kb
Host smart-9e1dbb54-e3b2-43eb-9732-89c75b74521b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643822834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1643822834
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3819144950
Short name T292
Test name
Test status
Simulation time 85613192 ps
CPU time 2.61 seconds
Started Jul 10 05:40:05 PM PDT 24
Finished Jul 10 05:40:09 PM PDT 24
Peak memory 215040 kb
Host smart-09f6b92f-8c8f-4fc5-af16-adb3576f1dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819144950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3819144950
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/162.edn_alert.2239413401
Short name T94
Test name
Test status
Simulation time 73301854 ps
CPU time 1.23 seconds
Started Jul 10 07:23:45 PM PDT 24
Finished Jul 10 07:23:50 PM PDT 24
Peak memory 216024 kb
Host smart-476a859a-a019-409e-88cc-e5d1bd24b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239413401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2239413401
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.807743321
Short name T167
Test name
Test status
Simulation time 33905947 ps
CPU time 1.41 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 216040 kb
Host smart-fd7fc595-913a-46b3-bca2-5a4d26b870dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807743321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.807743321
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1267939358
Short name T260
Test name
Test status
Simulation time 64248776 ps
CPU time 0.86 seconds
Started Jul 10 05:39:33 PM PDT 24
Finished Jul 10 05:39:35 PM PDT 24
Peak memory 206920 kb
Host smart-f343b302-bbb0-4171-b267-0cbb2d16ae46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267939358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1267939358
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/57.edn_err.521635647
Short name T63
Test name
Test status
Simulation time 25339733 ps
CPU time 1.02 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 224240 kb
Host smart-5d0cd0b3-fdd6-40f3-8dda-1c9d5ed230ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521635647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.521635647
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/31.edn_disable.764952004
Short name T209
Test name
Test status
Simulation time 15546574 ps
CPU time 0.85 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 216576 kb
Host smart-9462f515-f2a9-451c-809e-12be70927c69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764952004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.764952004
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4163037519
Short name T132
Test name
Test status
Simulation time 110084151 ps
CPU time 1.06 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 217208 kb
Host smart-2afd7204-5bff-4d1a-84bc-f6080c63da66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163037519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4163037519
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/241.edn_genbits.2287952619
Short name T21
Test name
Test status
Simulation time 80108983 ps
CPU time 2.98 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 220424 kb
Host smart-ae92f5c3-0bf5-4bd4-acb0-df1ec5933a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287952619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2287952619
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1523849610
Short name T93
Test name
Test status
Simulation time 45980241 ps
CPU time 1.16 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 218972 kb
Host smart-9d40e090-15be-4a9c-85f3-d010c34ab5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523849610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1523849610
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1857300800
Short name T165
Test name
Test status
Simulation time 39565648 ps
CPU time 1.09 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 217148 kb
Host smart-4bc4fcbe-4d8e-4d40-a6b6-2a01d89d9194
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857300800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1857300800
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/225.edn_genbits.2273659526
Short name T98
Test name
Test status
Simulation time 62108610 ps
CPU time 1.28 seconds
Started Jul 10 07:24:03 PM PDT 24
Finished Jul 10 07:24:09 PM PDT 24
Peak memory 218968 kb
Host smart-8c559dcb-36cc-41a9-8177-512bd52d9692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273659526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2273659526
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2659159824
Short name T103
Test name
Test status
Simulation time 24329580 ps
CPU time 1.11 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 220268 kb
Host smart-9ed2d449-eae7-4414-8a17-d5e1d35c0e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659159824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2659159824
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.4217679588
Short name T192
Test name
Test status
Simulation time 122477665 ps
CPU time 1.2 seconds
Started Jul 10 07:23:42 PM PDT 24
Finished Jul 10 07:23:49 PM PDT 24
Peak memory 219340 kb
Host smart-9b0cc23e-16e0-4cf9-83bb-fd125659c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217679588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.4217679588
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/23.edn_intr.3590055804
Short name T29
Test name
Test status
Simulation time 23213471 ps
CPU time 0.93 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 216160 kb
Host smart-48df5c3b-c624-49f6-9da5-d4d6603636e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590055804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3590055804
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/111.edn_alert.1302010152
Short name T829
Test name
Test status
Simulation time 42153647 ps
CPU time 1.18 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 220096 kb
Host smart-9289e499-7e5d-49b7-84b5-92f5a703dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302010152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1302010152
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.1685303961
Short name T146
Test name
Test status
Simulation time 90198864 ps
CPU time 1.33 seconds
Started Jul 10 07:23:25 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 220272 kb
Host smart-75bb5805-d258-43f6-bfdf-6a87bb0aa7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685303961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1685303961
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.2961256251
Short name T594
Test name
Test status
Simulation time 24292255 ps
CPU time 1.22 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 218996 kb
Host smart-e5e4ceae-55d5-458e-8c79-053825ef2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961256251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2961256251
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4261005160
Short name T149
Test name
Test status
Simulation time 28451658 ps
CPU time 1.01 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 219028 kb
Host smart-fb5a58d7-aea5-49b9-bb3e-d2f46535eb04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261005160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4261005160
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.1959071337
Short name T317
Test name
Test status
Simulation time 173624837 ps
CPU time 2.47 seconds
Started Jul 10 07:22:22 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 215608 kb
Host smart-e1d7422e-8262-4871-afee-4cedbb257cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959071337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1959071337
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2002644109
Short name T107
Test name
Test status
Simulation time 24277761 ps
CPU time 0.99 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 216084 kb
Host smart-1974e3a2-aed9-4267-bb20-22bfdd4d6526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002644109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2002644109
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.968494403
Short name T173
Test name
Test status
Simulation time 17888721 ps
CPU time 0.87 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:02 PM PDT 24
Peak memory 215768 kb
Host smart-bc23fe47-e299-4917-9b71-2add65bd644d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968494403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.968494403
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/17.edn_alert.4227025789
Short name T725
Test name
Test status
Simulation time 29113670 ps
CPU time 1.32 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 219856 kb
Host smart-3e8c3789-8c5f-405f-807b-665bce89c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227025789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4227025789
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable.2944507525
Short name T212
Test name
Test status
Simulation time 23838575 ps
CPU time 0.86 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:43 PM PDT 24
Peak memory 216552 kb
Host smart-60baf713-baa1-4c07-9c94-0afddcdf10e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944507525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2944507525
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.1095871821
Short name T217
Test name
Test status
Simulation time 27764862 ps
CPU time 0.8 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 216568 kb
Host smart-fcd1a2e1-6091-4d57-9cff-11d856b61ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095871821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1095871821
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.26226535
Short name T136
Test name
Test status
Simulation time 29036844 ps
CPU time 1.08 seconds
Started Jul 10 07:21:53 PM PDT 24
Finished Jul 10 07:21:55 PM PDT 24
Peak memory 217380 kb
Host smart-5c1461b3-a622-45d6-b50e-cb54bb6e1891
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26226535 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_dis
able_auto_req_mode.26226535
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/120.edn_alert.4058171083
Short name T853
Test name
Test status
Simulation time 61049325 ps
CPU time 1.23 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 218984 kb
Host smart-a72f6f5c-1b5b-4a38-adf2-04abe21314b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058171083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4058171083
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.1959908382
Short name T310
Test name
Test status
Simulation time 28508438 ps
CPU time 1.22 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:48 PM PDT 24
Peak memory 219632 kb
Host smart-d326a025-c732-4943-8485-66e5c39b2af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959908382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1959908382
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.311725605
Short name T500
Test name
Test status
Simulation time 27879863 ps
CPU time 1.26 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 218768 kb
Host smart-cc639cf5-09c2-480e-9e1d-d981478dda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311725605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.311725605
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.3642808231
Short name T720
Test name
Test status
Simulation time 48595135 ps
CPU time 1.26 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 218752 kb
Host smart-8f56f7b7-69dc-485b-82ab-f3993fd882bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642808231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3642808231
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/18.edn_err.2817409523
Short name T206
Test name
Test status
Simulation time 40773473 ps
CPU time 0.88 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 219584 kb
Host smart-aacff9ac-4255-45ea-9f68-76e854e131c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817409523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2817409523
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/20.edn_disable.977587430
Short name T228
Test name
Test status
Simulation time 21117600 ps
CPU time 0.86 seconds
Started Jul 10 07:22:16 PM PDT 24
Finished Jul 10 07:22:20 PM PDT 24
Peak memory 216568 kb
Host smart-355dfe94-0459-4767-9a81-71972c84332a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977587430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.977587430
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2785582637
Short name T202
Test name
Test status
Simulation time 18791396 ps
CPU time 1.05 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 218720 kb
Host smart-b3c94603-2623-44d0-838a-31d70251c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785582637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2785582637
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/32.edn_disable.442904903
Short name T24
Test name
Test status
Simulation time 13921218 ps
CPU time 0.89 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:44 PM PDT 24
Peak memory 215904 kb
Host smart-843d39f8-fc23-41a4-8ffc-904fa8a2fb5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442904903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.442904903
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable.3070835582
Short name T210
Test name
Test status
Simulation time 17537954 ps
CPU time 0.86 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 216004 kb
Host smart-1b2ad184-ecd6-456f-a0e3-e405ada5a7df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070835582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3070835582
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/141.edn_genbits.3645986553
Short name T95
Test name
Test status
Simulation time 29523000 ps
CPU time 1.25 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 220200 kb
Host smart-69477687-db4a-47d9-8a27-97ae818c6052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645986553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3645986553
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.4253530844
Short name T58
Test name
Test status
Simulation time 100186322 ps
CPU time 1.3 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 217812 kb
Host smart-8413c94f-006b-4b57-a6d0-30361f8cf39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253530844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4253530844
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.96620714
Short name T354
Test name
Test status
Simulation time 46594664 ps
CPU time 0.93 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215212 kb
Host smart-66574cea-be64-40f9-8d28-67aa74fea6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96620714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.96620714
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/290.edn_genbits.327522163
Short name T334
Test name
Test status
Simulation time 101865205 ps
CPU time 1.35 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 220392 kb
Host smart-a7f2d140-f62a-467a-b4b2-d4578939f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327522163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.327522163
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3136411518
Short name T297
Test name
Test status
Simulation time 101231821 ps
CPU time 1.2 seconds
Started Jul 10 07:23:34 PM PDT 24
Finished Jul 10 07:23:37 PM PDT 24
Peak memory 220700 kb
Host smart-9ee0152b-5380-42dd-8784-ef6fd77b92d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136411518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3136411518
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.1679541545
Short name T344
Test name
Test status
Simulation time 50496022 ps
CPU time 1.27 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 220512 kb
Host smart-817f0197-d039-4fcc-9a1f-50f1b5125f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679541545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1679541545
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1116512575
Short name T45
Test name
Test status
Simulation time 22468219 ps
CPU time 0.93 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 216052 kb
Host smart-fa61426d-7c70-4ed7-8b05-6dd982aea203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116512575 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1116512575
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/0.edn_stress_all.2666482007
Short name T331
Test name
Test status
Simulation time 254192508 ps
CPU time 4.75 seconds
Started Jul 10 07:21:41 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 215716 kb
Host smart-01426d90-6b70-4e9d-904f-9212e555f3e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666482007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2666482007
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4166356402
Short name T257
Test name
Test status
Simulation time 166338754 ps
CPU time 1.03 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:02 PM PDT 24
Peak memory 217184 kb
Host smart-e2724560-b7b4-485f-bd8a-5603a4b4a3e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166356402 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4166356402
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/125.edn_alert.1976415077
Short name T863
Test name
Test status
Simulation time 53881313 ps
CPU time 1.25 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:43 PM PDT 24
Peak memory 220708 kb
Host smart-ac2f0bea-a2e6-46e3-af4f-9605f88e8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976415077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1976415077
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/13.edn_genbits.1345827693
Short name T609
Test name
Test status
Simulation time 135165458 ps
CPU time 1.24 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 217620 kb
Host smart-dbcb7dca-b5ca-4ebb-8baf-0e90c72cf03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345827693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1345827693
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2956289996
Short name T915
Test name
Test status
Simulation time 100702335 ps
CPU time 1.53 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 219044 kb
Host smart-c759d42b-3ab5-48ab-9283-4697909617d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956289996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2956289996
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1579037188
Short name T314
Test name
Test status
Simulation time 34050856 ps
CPU time 1.47 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 218944 kb
Host smart-7c1060d9-0e55-443a-8b2b-518d12bbba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579037188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1579037188
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1570484163
Short name T332
Test name
Test status
Simulation time 82569877 ps
CPU time 1.76 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 219100 kb
Host smart-49f7e116-2fe3-4b7c-a537-73846adf2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570484163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1570484163
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.1978486170
Short name T23
Test name
Test status
Simulation time 44560163 ps
CPU time 1.44 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 219044 kb
Host smart-86a92b53-5e55-4210-806e-5a8abf83680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978486170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1978486170
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2776817528
Short name T315
Test name
Test status
Simulation time 44514603 ps
CPU time 1.76 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 218840 kb
Host smart-1e19be16-7549-4e3c-a18f-ea6bc46b1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776817528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2776817528
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1297854038
Short name T321
Test name
Test status
Simulation time 59675068 ps
CPU time 1.42 seconds
Started Jul 10 07:23:50 PM PDT 24
Finished Jul 10 07:23:54 PM PDT 24
Peak memory 217672 kb
Host smart-e10fadad-1b10-4e85-8d70-cdb26b099b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297854038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1297854038
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3124533807
Short name T580
Test name
Test status
Simulation time 95529826 ps
CPU time 1.09 seconds
Started Jul 10 07:23:47 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 219996 kb
Host smart-4850a179-035e-4d5e-9346-23cd2d18f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124533807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3124533807
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.899191878
Short name T862
Test name
Test status
Simulation time 57374525 ps
CPU time 1.4 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:24:00 PM PDT 24
Peak memory 218868 kb
Host smart-a341378b-b106-417f-9530-55a283ebb7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899191878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.899191878
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1742070723
Short name T36
Test name
Test status
Simulation time 20305262 ps
CPU time 1 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 216172 kb
Host smart-f6638804-17e5-4eaf-9ac2-d180f1e23281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742070723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1742070723
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/105.edn_alert.1683874355
Short name T120
Test name
Test status
Simulation time 48137564 ps
CPU time 1.18 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 216072 kb
Host smart-955c8146-eb86-435b-971c-72f1fa27960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683874355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1683874355
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/155.edn_alert.1999703013
Short name T200
Test name
Test status
Simulation time 24860796 ps
CPU time 1.23 seconds
Started Jul 10 07:23:52 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 220428 kb
Host smart-a962e098-db77-48ec-8306-d3c06daa0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999703013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1999703013
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/170.edn_alert.3753847699
Short name T124
Test name
Test status
Simulation time 66646148 ps
CPU time 1.13 seconds
Started Jul 10 07:23:47 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 219256 kb
Host smart-63c35a03-5a88-454c-81fc-d901be4c7b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753847699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3753847699
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/19.edn_err.353985308
Short name T6
Test name
Test status
Simulation time 53125347 ps
CPU time 0.94 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 220132 kb
Host smart-0e534170-aa85-471f-a00e-8d8d1a0bbdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353985308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.353985308
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2118024693
Short name T268
Test name
Test status
Simulation time 125131187 ps
CPU time 1.57 seconds
Started Jul 10 05:39:35 PM PDT 24
Finished Jul 10 05:39:37 PM PDT 24
Peak memory 206940 kb
Host smart-95cf00bd-b0a0-4be1-aae2-89d946c2b620
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118024693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2118024693
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3391521028
Short name T1002
Test name
Test status
Simulation time 61655750 ps
CPU time 3.24 seconds
Started Jul 10 05:39:33 PM PDT 24
Finished Jul 10 05:39:37 PM PDT 24
Peak memory 206908 kb
Host smart-9004ac73-b625-43c5-a3db-4d9d758f99e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391521028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3391521028
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.286494723
Short name T265
Test name
Test status
Simulation time 40369938 ps
CPU time 0.9 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:29 PM PDT 24
Peak memory 206920 kb
Host smart-4aaa5aa1-35f6-48b6-9814-37a6454d6967
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286494723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.286494723
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.448596237
Short name T1006
Test name
Test status
Simulation time 290911560 ps
CPU time 1.05 seconds
Started Jul 10 05:39:33 PM PDT 24
Finished Jul 10 05:39:35 PM PDT 24
Peak memory 216200 kb
Host smart-64a956c7-690e-44fe-8992-c5d302368b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448596237 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.448596237
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1822919054
Short name T1027
Test name
Test status
Simulation time 43113167 ps
CPU time 0.9 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:29 PM PDT 24
Peak memory 206924 kb
Host smart-904ca43f-4da7-43c3-836e-981a6103eadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822919054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1822919054
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3932757826
Short name T1061
Test name
Test status
Simulation time 30074114 ps
CPU time 1.34 seconds
Started Jul 10 05:39:34 PM PDT 24
Finished Jul 10 05:39:37 PM PDT 24
Peak memory 207064 kb
Host smart-eb68722d-f2b8-45ba-b049-c7ef3a315825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932757826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3932757826
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3414293449
Short name T1097
Test name
Test status
Simulation time 23868528 ps
CPU time 1.75 seconds
Started Jul 10 05:39:29 PM PDT 24
Finished Jul 10 05:39:31 PM PDT 24
Peak memory 215188 kb
Host smart-9e7753c0-2971-4ae0-a9e1-1ca06ff26703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414293449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3414293449
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4237065576
Short name T1122
Test name
Test status
Simulation time 162572121 ps
CPU time 1.67 seconds
Started Jul 10 05:39:27 PM PDT 24
Finished Jul 10 05:39:30 PM PDT 24
Peak memory 206868 kb
Host smart-02f0bfb5-5eb3-4342-8145-4994931da22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237065576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4237065576
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3198067910
Short name T266
Test name
Test status
Simulation time 126564947 ps
CPU time 1.18 seconds
Started Jul 10 05:39:32 PM PDT 24
Finished Jul 10 05:39:34 PM PDT 24
Peak memory 206860 kb
Host smart-79d62656-a3cf-4052-9cfd-fd838cff612d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198067910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3198067910
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.634330210
Short name T269
Test name
Test status
Simulation time 83231081 ps
CPU time 2.12 seconds
Started Jul 10 05:39:32 PM PDT 24
Finished Jul 10 05:39:35 PM PDT 24
Peak memory 206976 kb
Host smart-da67bc57-df61-40cd-93f7-fd7fa8c91097
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634330210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.634330210
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3317584588
Short name T1101
Test name
Test status
Simulation time 50726565 ps
CPU time 0.94 seconds
Started Jul 10 05:39:34 PM PDT 24
Finished Jul 10 05:39:36 PM PDT 24
Peak memory 206916 kb
Host smart-cefb03b2-a743-49e5-92c4-818491379ed1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317584588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3317584588
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3065452681
Short name T1096
Test name
Test status
Simulation time 14778190 ps
CPU time 1.07 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 216832 kb
Host smart-44ca2924-2229-47c1-aa9a-779363c6de6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065452681 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3065452681
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.943335288
Short name T1117
Test name
Test status
Simulation time 17399889 ps
CPU time 0.96 seconds
Started Jul 10 05:39:34 PM PDT 24
Finished Jul 10 05:39:36 PM PDT 24
Peak memory 206924 kb
Host smart-61598279-f8be-4814-9820-605148419f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943335288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.943335288
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3444166014
Short name T1010
Test name
Test status
Simulation time 16003900 ps
CPU time 0.77 seconds
Started Jul 10 05:39:32 PM PDT 24
Finished Jul 10 05:39:33 PM PDT 24
Peak memory 206680 kb
Host smart-9e2ca5fa-43ca-42da-af50-1f12ececa35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444166014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3444166014
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1140031007
Short name T1110
Test name
Test status
Simulation time 69427887 ps
CPU time 1.41 seconds
Started Jul 10 05:39:32 PM PDT 24
Finished Jul 10 05:39:34 PM PDT 24
Peak memory 207044 kb
Host smart-9379175d-3381-4628-9195-6c37ef0bef2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140031007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1140031007
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1418513618
Short name T1020
Test name
Test status
Simulation time 106483226 ps
CPU time 4.08 seconds
Started Jul 10 05:39:35 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 215188 kb
Host smart-bf2b19f5-d04a-4d26-876e-127c31a79435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418513618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1418513618
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1653053524
Short name T1125
Test name
Test status
Simulation time 215860910 ps
CPU time 1.54 seconds
Started Jul 10 05:39:34 PM PDT 24
Finished Jul 10 05:39:36 PM PDT 24
Peak memory 206924 kb
Host smart-4ea093b7-50d0-43e0-b0eb-ec1c2a3618bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653053524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1653053524
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1499913302
Short name T1118
Test name
Test status
Simulation time 98505192 ps
CPU time 1.64 seconds
Started Jul 10 05:40:07 PM PDT 24
Finished Jul 10 05:40:09 PM PDT 24
Peak memory 215128 kb
Host smart-73ff0c8d-a5c2-48be-a1ce-8c22d825a267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499913302 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1499913302
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3205411743
Short name T262
Test name
Test status
Simulation time 16307881 ps
CPU time 1 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:06 PM PDT 24
Peak memory 206872 kb
Host smart-d47f10f6-8585-409a-95da-7528731f2566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205411743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3205411743
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2518728075
Short name T1106
Test name
Test status
Simulation time 80014122 ps
CPU time 0.83 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:06 PM PDT 24
Peak memory 206692 kb
Host smart-accf6efb-bfe1-40ef-84ee-963f5877fa32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518728075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2518728075
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2570615050
Short name T1124
Test name
Test status
Simulation time 261352003 ps
CPU time 1.45 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:07 PM PDT 24
Peak memory 206924 kb
Host smart-e356e438-7ed3-461e-8bd3-b34bc99f6e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570615050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2570615050
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1554893214
Short name T1029
Test name
Test status
Simulation time 105595577 ps
CPU time 3.55 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:08 PM PDT 24
Peak memory 215096 kb
Host smart-688884dd-a2eb-4ebf-a4ae-40124127f40c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554893214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1554893214
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.879055409
Short name T286
Test name
Test status
Simulation time 256172406 ps
CPU time 2.26 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:07 PM PDT 24
Peak memory 207128 kb
Host smart-7c337f34-aa45-412d-a5ab-1484d7a2f7c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879055409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.879055409
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1366395471
Short name T1004
Test name
Test status
Simulation time 31853842 ps
CPU time 1.46 seconds
Started Jul 10 05:40:02 PM PDT 24
Finished Jul 10 05:40:04 PM PDT 24
Peak memory 215264 kb
Host smart-f6466230-72e3-4c29-af5c-e03ed053f281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366395471 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1366395471
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.725535720
Short name T1037
Test name
Test status
Simulation time 22190704 ps
CPU time 0.86 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:05 PM PDT 24
Peak memory 206920 kb
Host smart-b74f53c9-329b-4840-a3d2-ae5cc7550670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725535720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.725535720
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.438889320
Short name T1089
Test name
Test status
Simulation time 12828952 ps
CPU time 0.88 seconds
Started Jul 10 05:40:07 PM PDT 24
Finished Jul 10 05:40:08 PM PDT 24
Peak memory 206808 kb
Host smart-b880a869-38ea-4725-8fbb-5175045e1a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438889320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.438889320
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1746172835
Short name T1084
Test name
Test status
Simulation time 27435592 ps
CPU time 0.98 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:04 PM PDT 24
Peak memory 207036 kb
Host smart-45bae923-c70e-4021-b3c6-6c490730226b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746172835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1746172835
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3200523266
Short name T1005
Test name
Test status
Simulation time 140549181 ps
CPU time 3.08 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:07 PM PDT 24
Peak memory 215204 kb
Host smart-85970ebd-ba61-4f0d-923d-8cd0c1a385df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200523266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3200523266
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2200478695
Short name T1105
Test name
Test status
Simulation time 241548994 ps
CPU time 1.53 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:07 PM PDT 24
Peak memory 215152 kb
Host smart-5222895b-8c0f-4ac0-8925-8a5c999448d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200478695 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2200478695
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2202151162
Short name T1098
Test name
Test status
Simulation time 17650048 ps
CPU time 0.83 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:06 PM PDT 24
Peak memory 206752 kb
Host smart-5bb2fa8f-c44a-4476-889a-217474d39679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202151162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2202151162
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1531962390
Short name T1130
Test name
Test status
Simulation time 13647957 ps
CPU time 0.9 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:05 PM PDT 24
Peak memory 206808 kb
Host smart-9bcfd435-9e19-4ab9-acdb-2005a7cc1327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531962390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1531962390
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.796903669
Short name T1088
Test name
Test status
Simulation time 44565366 ps
CPU time 1.26 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:06 PM PDT 24
Peak memory 207108 kb
Host smart-5474e4e1-e08b-4f09-b595-e51d337a30a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796903669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.796903669
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2246098271
Short name T1039
Test name
Test status
Simulation time 37518466 ps
CPU time 2.42 seconds
Started Jul 10 05:40:05 PM PDT 24
Finished Jul 10 05:40:09 PM PDT 24
Peak memory 215156 kb
Host smart-8d68ff86-5f1a-48c9-92eb-c0ff65f6bedf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246098271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2246098271
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3630732594
Short name T291
Test name
Test status
Simulation time 292449723 ps
CPU time 2.43 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:08 PM PDT 24
Peak memory 215120 kb
Host smart-f4744b01-66cd-497e-9e05-9d72a5bcfe1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630732594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3630732594
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.150645588
Short name T1092
Test name
Test status
Simulation time 33422592 ps
CPU time 1.31 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 216584 kb
Host smart-069c30b1-e0f4-4327-81ba-b7d1e6bfe852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150645588 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.150645588
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3843047615
Short name T259
Test name
Test status
Simulation time 32954307 ps
CPU time 0.89 seconds
Started Jul 10 05:40:09 PM PDT 24
Finished Jul 10 05:40:12 PM PDT 24
Peak memory 206932 kb
Host smart-ee7cd65b-8b0f-4973-b6ad-5aa4755b18e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843047615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3843047615
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1643513792
Short name T1000
Test name
Test status
Simulation time 12752254 ps
CPU time 0.88 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:12 PM PDT 24
Peak memory 206812 kb
Host smart-1b2e4ce7-186d-444c-880d-7eb4a18a1215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643513792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1643513792
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1843197130
Short name T1071
Test name
Test status
Simulation time 122732791 ps
CPU time 1.39 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 206928 kb
Host smart-9109ecce-0aa6-4759-b53d-3a3aa2d5df3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843197130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1843197130
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.147421905
Short name T1024
Test name
Test status
Simulation time 148387347 ps
CPU time 2.72 seconds
Started Jul 10 05:40:04 PM PDT 24
Finished Jul 10 05:40:08 PM PDT 24
Peak memory 215204 kb
Host smart-392b60ad-57ba-4ec0-a7a5-3bb87c60d3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147421905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.147421905
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2341115828
Short name T1119
Test name
Test status
Simulation time 175911251 ps
CPU time 1.65 seconds
Started Jul 10 05:40:09 PM PDT 24
Finished Jul 10 05:40:12 PM PDT 24
Peak memory 215144 kb
Host smart-03af9171-c9cd-4907-9042-0459169d845c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341115828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2341115828
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2077839952
Short name T1094
Test name
Test status
Simulation time 68455741 ps
CPU time 1.69 seconds
Started Jul 10 05:40:08 PM PDT 24
Finished Jul 10 05:40:11 PM PDT 24
Peak memory 219976 kb
Host smart-4d6be114-5509-40e8-9f7b-b977966945f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077839952 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2077839952
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.944698798
Short name T277
Test name
Test status
Simulation time 33999273 ps
CPU time 0.83 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 207104 kb
Host smart-eae2222c-bacf-4631-b019-4155ace20bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944698798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.944698798
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1534990640
Short name T1003
Test name
Test status
Simulation time 21220804 ps
CPU time 0.81 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 206628 kb
Host smart-2db1efae-a0d2-4b0a-83b4-5add7ae57ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534990640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1534990640
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.308417569
Short name T1065
Test name
Test status
Simulation time 32732808 ps
CPU time 1.18 seconds
Started Jul 10 05:40:09 PM PDT 24
Finished Jul 10 05:40:12 PM PDT 24
Peak memory 206916 kb
Host smart-24505be8-91b9-472e-a80c-a03a164a6214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308417569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.308417569
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1678593544
Short name T1025
Test name
Test status
Simulation time 77625501 ps
CPU time 2.89 seconds
Started Jul 10 05:40:11 PM PDT 24
Finished Jul 10 05:40:15 PM PDT 24
Peak memory 215180 kb
Host smart-3813127f-e121-4a2d-a037-1d2513498d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678593544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1678593544
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.320729329
Short name T1108
Test name
Test status
Simulation time 109071685 ps
CPU time 2.78 seconds
Started Jul 10 05:40:09 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 215232 kb
Host smart-edf7f741-669e-427d-937b-c52682317bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320729329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.320729329
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1022212034
Short name T999
Test name
Test status
Simulation time 23596007 ps
CPU time 1.26 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 215104 kb
Host smart-5cf763a0-1d25-47f5-b5e9-6f03fd6d8e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022212034 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1022212034
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3498399672
Short name T281
Test name
Test status
Simulation time 29312875 ps
CPU time 0.91 seconds
Started Jul 10 05:40:08 PM PDT 24
Finished Jul 10 05:40:10 PM PDT 24
Peak memory 206956 kb
Host smart-0466aea1-9408-4edf-b8b2-f7991f6c8c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498399672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3498399672
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3981283391
Short name T1121
Test name
Test status
Simulation time 15030008 ps
CPU time 0.9 seconds
Started Jul 10 05:40:11 PM PDT 24
Finished Jul 10 05:40:13 PM PDT 24
Peak memory 206856 kb
Host smart-91aa2518-2c28-4925-92f2-f6e72eed2864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981283391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3981283391
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4058569443
Short name T1111
Test name
Test status
Simulation time 66475423 ps
CPU time 1.05 seconds
Started Jul 10 05:40:09 PM PDT 24
Finished Jul 10 05:40:11 PM PDT 24
Peak memory 206868 kb
Host smart-e3e6f05d-9a47-48e9-812d-f346c6af6df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058569443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4058569443
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.963893037
Short name T1126
Test name
Test status
Simulation time 170350008 ps
CPU time 2.24 seconds
Started Jul 10 05:40:10 PM PDT 24
Finished Jul 10 05:40:14 PM PDT 24
Peak memory 215116 kb
Host smart-82ec9c6e-5d74-4c5f-aea9-f8269e84a5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963893037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.963893037
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.729582321
Short name T1049
Test name
Test status
Simulation time 269053134 ps
CPU time 2.35 seconds
Started Jul 10 05:40:11 PM PDT 24
Finished Jul 10 05:40:15 PM PDT 24
Peak memory 206864 kb
Host smart-2fab7334-18e5-49d8-930a-e022895d6da3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729582321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.729582321
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1998144186
Short name T997
Test name
Test status
Simulation time 123445955 ps
CPU time 1.64 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 218404 kb
Host smart-1ae7051e-1718-4beb-a38d-441765906368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998144186 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1998144186
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3830134028
Short name T263
Test name
Test status
Simulation time 23859781 ps
CPU time 0.88 seconds
Started Jul 10 05:40:14 PM PDT 24
Finished Jul 10 05:40:15 PM PDT 24
Peak memory 206868 kb
Host smart-862e32b1-c3f3-44e3-be77-e6c2ae6f5340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830134028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3830134028
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3818593688
Short name T1031
Test name
Test status
Simulation time 11887876 ps
CPU time 0.86 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 206864 kb
Host smart-6a21271f-ac03-478c-bbb9-2a16382349eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818593688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3818593688
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2129314287
Short name T1056
Test name
Test status
Simulation time 78633862 ps
CPU time 1.17 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:17 PM PDT 24
Peak memory 206920 kb
Host smart-8d268a98-598d-4f99-a15e-788c9720b8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129314287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2129314287
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3013678421
Short name T1022
Test name
Test status
Simulation time 165326799 ps
CPU time 2.95 seconds
Started Jul 10 05:40:11 PM PDT 24
Finished Jul 10 05:40:15 PM PDT 24
Peak memory 215192 kb
Host smart-4dd53425-0c1f-41e3-8e5c-1c23f6961a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013678421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3013678421
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1081643162
Short name T1051
Test name
Test status
Simulation time 90878088 ps
CPU time 2.5 seconds
Started Jul 10 05:40:11 PM PDT 24
Finished Jul 10 05:40:15 PM PDT 24
Peak memory 206828 kb
Host smart-581c9582-8ea2-4ee6-8dff-6a064399c6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081643162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1081643162
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1667764311
Short name T1093
Test name
Test status
Simulation time 84836732 ps
CPU time 1.21 seconds
Started Jul 10 05:40:17 PM PDT 24
Finished Jul 10 05:40:19 PM PDT 24
Peak memory 217508 kb
Host smart-a33cb546-7e64-426a-b2a6-b869dbe6f12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667764311 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1667764311
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1888319490
Short name T271
Test name
Test status
Simulation time 17993010 ps
CPU time 1.03 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:17 PM PDT 24
Peak memory 206928 kb
Host smart-8688f178-a56e-4866-9df2-c9af923dad0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888319490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1888319490
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1350903694
Short name T1040
Test name
Test status
Simulation time 14585928 ps
CPU time 0.92 seconds
Started Jul 10 05:40:17 PM PDT 24
Finished Jul 10 05:40:19 PM PDT 24
Peak memory 206872 kb
Host smart-c7047a30-5c4e-4044-9692-62a268f139c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350903694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1350903694
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1594040287
Short name T1042
Test name
Test status
Simulation time 44814306 ps
CPU time 1.41 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 206900 kb
Host smart-b62c55eb-714c-422f-8934-106d925c16bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594040287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1594040287
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2874337198
Short name T1067
Test name
Test status
Simulation time 74474669 ps
CPU time 2.88 seconds
Started Jul 10 05:40:14 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 215192 kb
Host smart-3dea3cfe-22d4-404b-a428-535a4cc1af32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874337198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2874337198
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3687216087
Short name T1095
Test name
Test status
Simulation time 452787790 ps
CPU time 2.45 seconds
Started Jul 10 05:40:18 PM PDT 24
Finished Jul 10 05:40:21 PM PDT 24
Peak memory 215120 kb
Host smart-ded8d3bc-13d1-4d00-b852-719b11add55e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687216087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3687216087
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3786880292
Short name T1043
Test name
Test status
Simulation time 56455257 ps
CPU time 1.63 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 215260 kb
Host smart-dd7471c3-11f2-4e03-9a69-4d8c8f4308d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786880292 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3786880292
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1963368321
Short name T274
Test name
Test status
Simulation time 27039253 ps
CPU time 0.92 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:18 PM PDT 24
Peak memory 206932 kb
Host smart-1d7114b8-ef10-49ee-9bef-384641b60a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963368321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1963368321
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4138775862
Short name T1128
Test name
Test status
Simulation time 164586937 ps
CPU time 0.82 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:17 PM PDT 24
Peak memory 206692 kb
Host smart-7890b634-7f00-45a8-9080-5730d099f9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138775862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4138775862
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1100406794
Short name T280
Test name
Test status
Simulation time 41407676 ps
CPU time 0.98 seconds
Started Jul 10 05:40:15 PM PDT 24
Finished Jul 10 05:40:17 PM PDT 24
Peak memory 206884 kb
Host smart-0941957c-396f-40bb-b3bf-f3a994391c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100406794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1100406794
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3075324283
Short name T1045
Test name
Test status
Simulation time 66712327 ps
CPU time 2.76 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:20 PM PDT 24
Peak memory 215192 kb
Host smart-b01eda61-60fa-40ce-8752-9854408b9d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075324283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3075324283
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.687739143
Short name T1083
Test name
Test status
Simulation time 154310720 ps
CPU time 1.6 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:19 PM PDT 24
Peak memory 206896 kb
Host smart-1acb610e-0059-43b6-9a9b-a1ba632e5117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687739143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.687739143
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1406062737
Short name T1127
Test name
Test status
Simulation time 15639642 ps
CPU time 1.17 seconds
Started Jul 10 05:40:23 PM PDT 24
Finished Jul 10 05:40:26 PM PDT 24
Peak memory 215224 kb
Host smart-4aa20a07-c63f-41b0-9235-be7c6df364f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406062737 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1406062737
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2227632048
Short name T273
Test name
Test status
Simulation time 14775935 ps
CPU time 0.97 seconds
Started Jul 10 05:40:20 PM PDT 24
Finished Jul 10 05:40:22 PM PDT 24
Peak memory 206936 kb
Host smart-2a447a8c-c085-4cf5-b5b7-8553227b8954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227632048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2227632048
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.132905778
Short name T1070
Test name
Test status
Simulation time 13696815 ps
CPU time 0.9 seconds
Started Jul 10 05:40:23 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206852 kb
Host smart-7892d679-617e-499c-82ff-339be663d348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132905778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.132905778
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4048205152
Short name T1069
Test name
Test status
Simulation time 29818391 ps
CPU time 1.29 seconds
Started Jul 10 05:40:21 PM PDT 24
Finished Jul 10 05:40:23 PM PDT 24
Peak memory 206964 kb
Host smart-bbf064f1-6a66-42a3-ad0e-e7a325b441f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048205152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4048205152
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1114027901
Short name T1102
Test name
Test status
Simulation time 45519412 ps
CPU time 1.87 seconds
Started Jul 10 05:40:19 PM PDT 24
Finished Jul 10 05:40:21 PM PDT 24
Peak memory 223356 kb
Host smart-f8f1478f-fc36-4f61-9e50-32c19c16cd51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114027901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1114027901
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.28122060
Short name T1046
Test name
Test status
Simulation time 93321818 ps
CPU time 2.54 seconds
Started Jul 10 05:40:16 PM PDT 24
Finished Jul 10 05:40:20 PM PDT 24
Peak memory 206924 kb
Host smart-8dc810da-c2df-4cdc-aa8f-5f76d8e04e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28122060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.28122060
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.72207782
Short name T258
Test name
Test status
Simulation time 171970613 ps
CPU time 1.57 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 207056 kb
Host smart-3133b330-faa3-40e3-a7fd-f1436d2a58c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72207782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.72207782
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4108331929
Short name T1066
Test name
Test status
Simulation time 675972682 ps
CPU time 5.4 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:45 PM PDT 24
Peak memory 206952 kb
Host smart-f13388f7-8248-4841-9dcf-81fb4f245330
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108331929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4108331929
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2749432583
Short name T1044
Test name
Test status
Simulation time 15626477 ps
CPU time 0.95 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 206940 kb
Host smart-4bd73a2f-0b6f-40c7-b6e2-d6d3e5dfa828
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749432583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2749432583
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.681726311
Short name T1052
Test name
Test status
Simulation time 64649172 ps
CPU time 1.14 seconds
Started Jul 10 05:39:41 PM PDT 24
Finished Jul 10 05:39:43 PM PDT 24
Peak memory 215232 kb
Host smart-0ddb041d-2ff7-42af-a46e-99ffba9b7535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681726311 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.681726311
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2642264067
Short name T1007
Test name
Test status
Simulation time 28715408 ps
CPU time 0.83 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 206728 kb
Host smart-60f82a7e-aeeb-47c6-ace3-1dacfe2390b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642264067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2642264067
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2914115535
Short name T1054
Test name
Test status
Simulation time 18323553 ps
CPU time 0.97 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 206888 kb
Host smart-ceb762fe-81f7-4c7a-bd18-f000afc17535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914115535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2914115535
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1066790605
Short name T278
Test name
Test status
Simulation time 77651143 ps
CPU time 1.06 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 206960 kb
Host smart-ec171b38-7539-4c14-9643-a8170ea83d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066790605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1066790605
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.463381625
Short name T1028
Test name
Test status
Simulation time 184793411 ps
CPU time 2.07 seconds
Started Jul 10 05:39:39 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 215152 kb
Host smart-995f2489-ab23-4749-85af-831b5a4cf607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463381625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.463381625
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.35191798
Short name T1047
Test name
Test status
Simulation time 50726619 ps
CPU time 1.71 seconds
Started Jul 10 05:39:39 PM PDT 24
Finished Jul 10 05:39:42 PM PDT 24
Peak memory 215068 kb
Host smart-005f5ac5-d400-4415-abf9-3f7a44cdc712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.35191798
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2405618362
Short name T1068
Test name
Test status
Simulation time 46973510 ps
CPU time 0.9 seconds
Started Jul 10 05:40:24 PM PDT 24
Finished Jul 10 05:40:26 PM PDT 24
Peak memory 206860 kb
Host smart-b194dff0-9b90-4d7d-9748-ee69be7691d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405618362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2405618362
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2923291918
Short name T1063
Test name
Test status
Simulation time 14746404 ps
CPU time 0.87 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206860 kb
Host smart-4562d425-6f0c-42af-958b-db1c35cd9629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923291918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2923291918
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.714394541
Short name T1023
Test name
Test status
Simulation time 22794187 ps
CPU time 0.89 seconds
Started Jul 10 05:40:21 PM PDT 24
Finished Jul 10 05:40:23 PM PDT 24
Peak memory 206832 kb
Host smart-a3dc771b-7fac-4a8d-ba7d-f3a9711089e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714394541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.714394541
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3914025346
Short name T1100
Test name
Test status
Simulation time 18233590 ps
CPU time 0.82 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206692 kb
Host smart-744529e5-ab9e-4d31-8c7f-b7d8b8ef8ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914025346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3914025346
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4056623012
Short name T1109
Test name
Test status
Simulation time 15522905 ps
CPU time 0.94 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206808 kb
Host smart-d82da510-061d-4b91-9611-b4690745ae68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056623012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4056623012
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3165239023
Short name T1026
Test name
Test status
Simulation time 92136510 ps
CPU time 0.85 seconds
Started Jul 10 05:40:20 PM PDT 24
Finished Jul 10 05:40:22 PM PDT 24
Peak memory 206716 kb
Host smart-a8e31882-2da0-483e-8d34-115b68e9385b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165239023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3165239023
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1746322426
Short name T1032
Test name
Test status
Simulation time 54680035 ps
CPU time 0.83 seconds
Started Jul 10 05:40:21 PM PDT 24
Finished Jul 10 05:40:23 PM PDT 24
Peak memory 206716 kb
Host smart-5360de21-cfb6-4172-ad04-56ca43de707c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746322426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1746322426
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.583327476
Short name T1055
Test name
Test status
Simulation time 69927768 ps
CPU time 0.81 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206688 kb
Host smart-279d2fa1-a833-4450-8d72-4913d92e3aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583327476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.583327476
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.28441303
Short name T1090
Test name
Test status
Simulation time 16642698 ps
CPU time 0.82 seconds
Started Jul 10 05:40:23 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206692 kb
Host smart-0d68ac89-e757-4ad3-a12b-898efe4d70b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28441303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.28441303
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2213652134
Short name T1076
Test name
Test status
Simulation time 25782284 ps
CPU time 0.88 seconds
Started Jul 10 05:40:21 PM PDT 24
Finished Jul 10 05:40:23 PM PDT 24
Peak memory 206848 kb
Host smart-9abbcfde-cf60-45a1-b191-4dc8dfdf0daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213652134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2213652134
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1632506883
Short name T1079
Test name
Test status
Simulation time 28252778 ps
CPU time 1.27 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 206936 kb
Host smart-cb18e4db-608e-431b-bf48-6bfa9a78df41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632506883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1632506883
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3775174379
Short name T1015
Test name
Test status
Simulation time 1785669137 ps
CPU time 3.23 seconds
Started Jul 10 05:39:41 PM PDT 24
Finished Jul 10 05:39:45 PM PDT 24
Peak memory 206920 kb
Host smart-94dca691-19f0-4952-bdb9-982846455a92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775174379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3775174379
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4046086137
Short name T1048
Test name
Test status
Simulation time 28369691 ps
CPU time 0.99 seconds
Started Jul 10 05:39:37 PM PDT 24
Finished Jul 10 05:39:39 PM PDT 24
Peak memory 206900 kb
Host smart-35d011f1-a298-429d-afdc-2a554205ac62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046086137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4046086137
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3281774213
Short name T1113
Test name
Test status
Simulation time 46887659 ps
CPU time 1.09 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 215272 kb
Host smart-4742c619-e121-4e3f-a3f3-0729da6b13a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281774213 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3281774213
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.267410685
Short name T264
Test name
Test status
Simulation time 14753813 ps
CPU time 0.9 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 206892 kb
Host smart-445b331b-9d20-4113-8048-d0b9d9af4bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267410685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.267410685
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.793157618
Short name T1129
Test name
Test status
Simulation time 15275000 ps
CPU time 0.92 seconds
Started Jul 10 05:39:39 PM PDT 24
Finished Jul 10 05:39:41 PM PDT 24
Peak memory 206812 kb
Host smart-e1f629e7-c48c-4aae-bc5f-feabd7b2f65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793157618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.793157618
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2813272784
Short name T276
Test name
Test status
Simulation time 40961352 ps
CPU time 1.12 seconds
Started Jul 10 05:39:41 PM PDT 24
Finished Jul 10 05:39:43 PM PDT 24
Peak memory 206904 kb
Host smart-738208d1-5ffa-4ce2-8a94-073c6ac88c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813272784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2813272784
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4174794698
Short name T1120
Test name
Test status
Simulation time 324772834 ps
CPU time 3.13 seconds
Started Jul 10 05:39:40 PM PDT 24
Finished Jul 10 05:39:44 PM PDT 24
Peak memory 219424 kb
Host smart-7679634f-3188-4e6f-9f7c-7d55223cd87b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174794698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4174794698
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2953581639
Short name T1050
Test name
Test status
Simulation time 541259873 ps
CPU time 1.62 seconds
Started Jul 10 05:39:38 PM PDT 24
Finished Jul 10 05:39:40 PM PDT 24
Peak memory 207040 kb
Host smart-f85d8212-c6c9-4c19-b687-33063133bd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953581639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2953581639
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.589135351
Short name T1058
Test name
Test status
Simulation time 12273014 ps
CPU time 0.89 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206864 kb
Host smart-c298ed69-10d5-47ab-9f5d-4f5a6adb24e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589135351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.589135351
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1933651644
Short name T1021
Test name
Test status
Simulation time 15480487 ps
CPU time 0.91 seconds
Started Jul 10 05:40:24 PM PDT 24
Finished Jul 10 05:40:26 PM PDT 24
Peak memory 206864 kb
Host smart-a1d3e6be-93e2-47cf-96e8-064bea3ba381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933651644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1933651644
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2979753705
Short name T1016
Test name
Test status
Simulation time 17405123 ps
CPU time 0.81 seconds
Started Jul 10 05:40:21 PM PDT 24
Finished Jul 10 05:40:23 PM PDT 24
Peak memory 206684 kb
Host smart-54154ee1-23da-4488-93db-20508b33f432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979753705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2979753705
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.165904725
Short name T1036
Test name
Test status
Simulation time 129550639 ps
CPU time 0.88 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206704 kb
Host smart-e4368394-e681-4c77-9b68-f6bb14a20657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165904725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.165904725
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2407358599
Short name T1053
Test name
Test status
Simulation time 14456627 ps
CPU time 0.9 seconds
Started Jul 10 05:40:23 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206836 kb
Host smart-93d63c70-2e10-4150-aa71-2e4ac7d19574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407358599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2407358599
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3876526507
Short name T1035
Test name
Test status
Simulation time 34854792 ps
CPU time 0.76 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206664 kb
Host smart-08b23d11-0b58-4d0a-b408-a542896e3bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876526507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3876526507
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1397133334
Short name T1080
Test name
Test status
Simulation time 49871748 ps
CPU time 0.93 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:25 PM PDT 24
Peak memory 206888 kb
Host smart-2ad9bcf0-0c01-47a5-9262-f4a28c1a1181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397133334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1397133334
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2345253581
Short name T1078
Test name
Test status
Simulation time 14851656 ps
CPU time 0.81 seconds
Started Jul 10 05:40:22 PM PDT 24
Finished Jul 10 05:40:24 PM PDT 24
Peak memory 206636 kb
Host smart-c8c1cf27-ac8f-48b8-91a5-b5346576eb74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345253581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2345253581
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2080296418
Short name T1075
Test name
Test status
Simulation time 48574256 ps
CPU time 0.92 seconds
Started Jul 10 05:40:32 PM PDT 24
Finished Jul 10 05:40:33 PM PDT 24
Peak memory 206864 kb
Host smart-3ac9e939-6ed7-4ab6-acdd-bcb5f4cd15ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080296418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2080296418
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3934209208
Short name T1001
Test name
Test status
Simulation time 35172472 ps
CPU time 0.87 seconds
Started Jul 10 05:40:27 PM PDT 24
Finished Jul 10 05:40:29 PM PDT 24
Peak memory 206860 kb
Host smart-a1474c7b-330a-493f-8fd2-5f7caa79b82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934209208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3934209208
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2169034166
Short name T267
Test name
Test status
Simulation time 39672923 ps
CPU time 1.53 seconds
Started Jul 10 05:39:47 PM PDT 24
Finished Jul 10 05:39:49 PM PDT 24
Peak memory 206916 kb
Host smart-265477a5-cd0f-4d10-993b-49d5323a5577
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169034166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2169034166
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4017215588
Short name T1082
Test name
Test status
Simulation time 180045399 ps
CPU time 3.17 seconds
Started Jul 10 05:39:45 PM PDT 24
Finished Jul 10 05:39:49 PM PDT 24
Peak memory 206920 kb
Host smart-63674afd-91df-4925-9565-04ed2f3678e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017215588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4017215588
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4074507038
Short name T1030
Test name
Test status
Simulation time 106637442 ps
CPU time 0.82 seconds
Started Jul 10 05:39:49 PM PDT 24
Finished Jul 10 05:39:50 PM PDT 24
Peak memory 206736 kb
Host smart-5c6b9e2c-dbb0-46a1-bf22-8b7a7942f492
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074507038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4074507038
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.481202810
Short name T1034
Test name
Test status
Simulation time 87277049 ps
CPU time 1.3 seconds
Started Jul 10 05:39:44 PM PDT 24
Finished Jul 10 05:39:46 PM PDT 24
Peak memory 223296 kb
Host smart-9fbe39e6-86f4-4f54-91a2-bafe3dc3994f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481202810 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.481202810
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1497974972
Short name T261
Test name
Test status
Simulation time 12083494 ps
CPU time 0.87 seconds
Started Jul 10 05:39:43 PM PDT 24
Finished Jul 10 05:39:45 PM PDT 24
Peak memory 206880 kb
Host smart-944426d7-4d52-4ebb-a72f-8f5ccb5326f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497974972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1497974972
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1173269382
Short name T1012
Test name
Test status
Simulation time 13303461 ps
CPU time 0.86 seconds
Started Jul 10 05:39:45 PM PDT 24
Finished Jul 10 05:39:47 PM PDT 24
Peak memory 206856 kb
Host smart-8b6c0bf1-71ee-4221-b3b3-292047e4e0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173269382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1173269382
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2996124114
Short name T1099
Test name
Test status
Simulation time 21797590 ps
CPU time 1.17 seconds
Started Jul 10 05:39:47 PM PDT 24
Finished Jul 10 05:39:49 PM PDT 24
Peak memory 206988 kb
Host smart-ec4ecd5f-1c2f-4f94-b0ac-6964262b04f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996124114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2996124114
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4225405700
Short name T998
Test name
Test status
Simulation time 49989894 ps
CPU time 1.93 seconds
Started Jul 10 05:39:44 PM PDT 24
Finished Jul 10 05:39:47 PM PDT 24
Peak memory 215252 kb
Host smart-26b21f68-f65e-4162-86f3-9ee101f671ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225405700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4225405700
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3405640864
Short name T1072
Test name
Test status
Simulation time 218130448 ps
CPU time 1.5 seconds
Started Jul 10 05:39:45 PM PDT 24
Finished Jul 10 05:39:47 PM PDT 24
Peak memory 207308 kb
Host smart-97fd934b-ef4e-4c15-bb75-e0198f00952d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405640864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3405640864
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3664936908
Short name T1062
Test name
Test status
Simulation time 14033891 ps
CPU time 0.88 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206808 kb
Host smart-96db09f4-95aa-4ed2-b32c-ffe18418b64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664936908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3664936908
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3995499883
Short name T1085
Test name
Test status
Simulation time 24620007 ps
CPU time 0.88 seconds
Started Jul 10 05:40:30 PM PDT 24
Finished Jul 10 05:40:31 PM PDT 24
Peak memory 206864 kb
Host smart-c82137ff-a1b6-4758-859b-376f3be15cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995499883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3995499883
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.582353699
Short name T1014
Test name
Test status
Simulation time 26934781 ps
CPU time 0.78 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206684 kb
Host smart-b6ab955e-de49-41f2-9cce-71df61a7c316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582353699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.582353699
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.412894820
Short name T1091
Test name
Test status
Simulation time 24926435 ps
CPU time 0.84 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206860 kb
Host smart-da2f7067-ee7a-4aaf-b3f3-60ce36eebdc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412894820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.412894820
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1520998232
Short name T1057
Test name
Test status
Simulation time 29475240 ps
CPU time 0.89 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206948 kb
Host smart-6c545867-df75-49cb-8616-d1c9291f53ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520998232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1520998232
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2799515976
Short name T1013
Test name
Test status
Simulation time 27908964 ps
CPU time 0.95 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206804 kb
Host smart-a4119d97-8a56-466e-9d22-8e7c88410cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799515976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2799515976
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4251676745
Short name T1019
Test name
Test status
Simulation time 21632472 ps
CPU time 0.89 seconds
Started Jul 10 05:40:28 PM PDT 24
Finished Jul 10 05:40:30 PM PDT 24
Peak memory 206944 kb
Host smart-c0c6f0fe-faa8-4332-aa95-2cd7cbf7db74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251676745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4251676745
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1122462334
Short name T1116
Test name
Test status
Simulation time 34412408 ps
CPU time 0.86 seconds
Started Jul 10 05:40:26 PM PDT 24
Finished Jul 10 05:40:28 PM PDT 24
Peak memory 206812 kb
Host smart-b85ea34b-2106-48cf-b213-388a4e3b7b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122462334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1122462334
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1403248096
Short name T1081
Test name
Test status
Simulation time 97210557 ps
CPU time 0.89 seconds
Started Jul 10 05:40:29 PM PDT 24
Finished Jul 10 05:40:31 PM PDT 24
Peak memory 206868 kb
Host smart-b83fb26e-201e-48bf-ae01-6e3530ecb2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403248096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1403248096
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3951961817
Short name T1103
Test name
Test status
Simulation time 12350546 ps
CPU time 0.91 seconds
Started Jul 10 05:40:30 PM PDT 24
Finished Jul 10 05:40:31 PM PDT 24
Peak memory 206864 kb
Host smart-eda06f22-1aa9-4742-bbf2-86b9d2b8add0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951961817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3951961817
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3833514767
Short name T1104
Test name
Test status
Simulation time 44979209 ps
CPU time 1.27 seconds
Started Jul 10 05:39:52 PM PDT 24
Finished Jul 10 05:39:54 PM PDT 24
Peak memory 215180 kb
Host smart-d4c760da-f4c6-4352-915f-5a1563c49fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833514767 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3833514767
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1425019169
Short name T1086
Test name
Test status
Simulation time 31639911 ps
CPU time 0.94 seconds
Started Jul 10 05:39:50 PM PDT 24
Finished Jul 10 05:39:52 PM PDT 24
Peak memory 206920 kb
Host smart-b2120473-15a5-492b-a324-61c14ca8fc15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425019169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1425019169
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.546612073
Short name T1038
Test name
Test status
Simulation time 13699488 ps
CPU time 0.91 seconds
Started Jul 10 05:39:46 PM PDT 24
Finished Jul 10 05:39:48 PM PDT 24
Peak memory 206868 kb
Host smart-d3fdb99f-ebff-4538-b398-5ff308e3347c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546612073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.546612073
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3470983448
Short name T1059
Test name
Test status
Simulation time 18624924 ps
CPU time 1.17 seconds
Started Jul 10 05:39:52 PM PDT 24
Finished Jul 10 05:39:54 PM PDT 24
Peak memory 206928 kb
Host smart-4ddfd158-3d6a-40e5-8ed9-f6f18d486483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470983448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3470983448
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3464755483
Short name T996
Test name
Test status
Simulation time 35515567 ps
CPU time 1.67 seconds
Started Jul 10 05:39:46 PM PDT 24
Finished Jul 10 05:39:49 PM PDT 24
Peak memory 215248 kb
Host smart-cb5d8d46-66ab-47ab-97f5-3ba1a2d33e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464755483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3464755483
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4177285525
Short name T288
Test name
Test status
Simulation time 427990335 ps
CPU time 2.83 seconds
Started Jul 10 05:39:45 PM PDT 24
Finished Jul 10 05:39:48 PM PDT 24
Peak memory 207144 kb
Host smart-4c9d56e2-c735-4271-b178-0d225e017e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177285525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4177285525
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2988659539
Short name T1073
Test name
Test status
Simulation time 27804021 ps
CPU time 1.49 seconds
Started Jul 10 05:39:52 PM PDT 24
Finished Jul 10 05:39:55 PM PDT 24
Peak memory 223416 kb
Host smart-e2b8b7ab-b0cd-42d2-89fb-047d493682dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988659539 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2988659539
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.4188218278
Short name T272
Test name
Test status
Simulation time 21445324 ps
CPU time 0.86 seconds
Started Jul 10 05:39:51 PM PDT 24
Finished Jul 10 05:39:53 PM PDT 24
Peak memory 206896 kb
Host smart-f91aa3bc-1cd2-4e2f-9217-5b123f9b70c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188218278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4188218278
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3847513351
Short name T1087
Test name
Test status
Simulation time 28757780 ps
CPU time 0.82 seconds
Started Jul 10 05:39:52 PM PDT 24
Finished Jul 10 05:39:54 PM PDT 24
Peak memory 206864 kb
Host smart-94635ee5-1818-4ea7-86e8-1857bff9911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847513351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3847513351
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.943123538
Short name T279
Test name
Test status
Simulation time 63757926 ps
CPU time 1.08 seconds
Started Jul 10 05:39:51 PM PDT 24
Finished Jul 10 05:39:53 PM PDT 24
Peak memory 206940 kb
Host smart-3c7e5d9e-bfa3-403c-aa59-0946a59f82f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943123538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.943123538
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3543318168
Short name T1041
Test name
Test status
Simulation time 56727594 ps
CPU time 2.37 seconds
Started Jul 10 05:39:50 PM PDT 24
Finished Jul 10 05:39:53 PM PDT 24
Peak memory 215188 kb
Host smart-d1120f8e-fe18-43dd-afe2-819558e1966e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543318168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3543318168
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.53664812
Short name T1077
Test name
Test status
Simulation time 296394324 ps
CPU time 1.48 seconds
Started Jul 10 05:39:53 PM PDT 24
Finished Jul 10 05:39:55 PM PDT 24
Peak memory 206932 kb
Host smart-81109b6e-a024-4f51-9f14-5c31be17711d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53664812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.53664812
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.339487378
Short name T1033
Test name
Test status
Simulation time 22411895 ps
CPU time 1.22 seconds
Started Jul 10 05:40:00 PM PDT 24
Finished Jul 10 05:40:02 PM PDT 24
Peak memory 215160 kb
Host smart-b2d25684-c7f9-4769-9100-8b0559bc0fe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339487378 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.339487378
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1348162820
Short name T1123
Test name
Test status
Simulation time 32236962 ps
CPU time 0.89 seconds
Started Jul 10 05:39:57 PM PDT 24
Finished Jul 10 05:39:59 PM PDT 24
Peak memory 206920 kb
Host smart-e6c81fd3-cc54-4589-99b0-0de83c5310a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348162820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1348162820
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2982768678
Short name T1112
Test name
Test status
Simulation time 25149964 ps
CPU time 0.88 seconds
Started Jul 10 05:39:57 PM PDT 24
Finished Jul 10 05:39:59 PM PDT 24
Peak memory 206864 kb
Host smart-7bc56e6e-52ae-4a67-9ef3-92f1c7b44695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982768678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2982768678
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1042536730
Short name T1074
Test name
Test status
Simulation time 13544672 ps
CPU time 0.99 seconds
Started Jul 10 05:39:58 PM PDT 24
Finished Jul 10 05:40:00 PM PDT 24
Peak memory 206960 kb
Host smart-8b5a6107-655a-43e6-ac38-b53a2673a445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042536730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1042536730
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.650725072
Short name T1017
Test name
Test status
Simulation time 36247407 ps
CPU time 1.49 seconds
Started Jul 10 05:39:51 PM PDT 24
Finished Jul 10 05:39:53 PM PDT 24
Peak memory 215188 kb
Host smart-b526f5b2-a49c-419c-b3ec-86e0850fa28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650725072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.650725072
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.213531055
Short name T287
Test name
Test status
Simulation time 275482963 ps
CPU time 2.21 seconds
Started Jul 10 05:39:52 PM PDT 24
Finished Jul 10 05:39:55 PM PDT 24
Peak memory 207096 kb
Host smart-b8e12f00-f2bd-4f4d-81b4-a0ea7cf0b63f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213531055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.213531055
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2202485737
Short name T1009
Test name
Test status
Simulation time 35049319 ps
CPU time 1.34 seconds
Started Jul 10 05:39:59 PM PDT 24
Finished Jul 10 05:40:01 PM PDT 24
Peak memory 215500 kb
Host smart-8ce3c14b-11c0-4831-bfd9-e017fb122ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202485737 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2202485737
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3771042088
Short name T275
Test name
Test status
Simulation time 111737414 ps
CPU time 0.96 seconds
Started Jul 10 05:39:56 PM PDT 24
Finished Jul 10 05:39:57 PM PDT 24
Peak memory 206920 kb
Host smart-c67646fc-8352-44a2-b239-6c58b3ac7f4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771042088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3771042088
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1769825882
Short name T1008
Test name
Test status
Simulation time 24161660 ps
CPU time 0.88 seconds
Started Jul 10 05:39:58 PM PDT 24
Finished Jul 10 05:40:00 PM PDT 24
Peak memory 206808 kb
Host smart-6f0453da-a252-4047-a608-65c8230f1bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769825882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1769825882
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2109748474
Short name T1107
Test name
Test status
Simulation time 20395658 ps
CPU time 1.08 seconds
Started Jul 10 05:39:57 PM PDT 24
Finished Jul 10 05:39:59 PM PDT 24
Peak memory 207064 kb
Host smart-f0e8dfd9-5088-4a30-b45f-f7ac0b58ad69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109748474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2109748474
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2285555577
Short name T1018
Test name
Test status
Simulation time 123282347 ps
CPU time 1.94 seconds
Started Jul 10 05:39:58 PM PDT 24
Finished Jul 10 05:40:01 PM PDT 24
Peak memory 215132 kb
Host smart-58f3259b-78e4-4cba-b206-293c644acebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285555577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2285555577
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3918968969
Short name T1060
Test name
Test status
Simulation time 82165714 ps
CPU time 1.52 seconds
Started Jul 10 05:39:56 PM PDT 24
Finished Jul 10 05:39:58 PM PDT 24
Peak memory 215200 kb
Host smart-48798cca-7a51-43ce-9ac3-04878ded7f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918968969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3918968969
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.626843554
Short name T1114
Test name
Test status
Simulation time 22891746 ps
CPU time 1.61 seconds
Started Jul 10 05:40:03 PM PDT 24
Finished Jul 10 05:40:06 PM PDT 24
Peak memory 223424 kb
Host smart-732e4c57-e712-43b1-a572-8946a3c78a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626843554 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.626843554
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3692216623
Short name T270
Test name
Test status
Simulation time 28405177 ps
CPU time 0.84 seconds
Started Jul 10 05:40:05 PM PDT 24
Finished Jul 10 05:40:07 PM PDT 24
Peak memory 206552 kb
Host smart-a43894ea-4e94-4b73-9fa7-42629690e3bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692216623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3692216623
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2340209895
Short name T1115
Test name
Test status
Simulation time 11804497 ps
CPU time 0.86 seconds
Started Jul 10 05:39:56 PM PDT 24
Finished Jul 10 05:39:58 PM PDT 24
Peak memory 206864 kb
Host smart-ac3c017a-6396-4998-849d-faea7e7c05eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340209895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2340209895
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1552412561
Short name T1064
Test name
Test status
Simulation time 107186265 ps
CPU time 1.46 seconds
Started Jul 10 05:40:05 PM PDT 24
Finished Jul 10 05:40:08 PM PDT 24
Peak memory 206960 kb
Host smart-99e0a787-e4d3-4d3c-94c1-dfa080b20cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552412561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1552412561
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3946946954
Short name T1011
Test name
Test status
Simulation time 39157109 ps
CPU time 1.63 seconds
Started Jul 10 05:39:56 PM PDT 24
Finished Jul 10 05:39:58 PM PDT 24
Peak memory 215132 kb
Host smart-291daaca-ae22-439e-8daa-f5b105897a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946946954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3946946954
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1040076287
Short name T293
Test name
Test status
Simulation time 402156661 ps
CPU time 1.57 seconds
Started Jul 10 05:40:00 PM PDT 24
Finished Jul 10 05:40:02 PM PDT 24
Peak memory 215240 kb
Host smart-a15bbab3-cb86-48ef-a6b9-55e4e1f098bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040076287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1040076287
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4272363688
Short name T739
Test name
Test status
Simulation time 43427088 ps
CPU time 1.2 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 220264 kb
Host smart-d4872558-7a37-4e12-bebf-c20285b8fa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272363688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4272363688
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.44976182
Short name T826
Test name
Test status
Simulation time 31013771 ps
CPU time 0.93 seconds
Started Jul 10 07:21:45 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 207044 kb
Host smart-7efa71e2-33d1-44ec-a870-d9159f7b94b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44976182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.44976182
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.774900476
Short name T197
Test name
Test status
Simulation time 41460943 ps
CPU time 0.86 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 216600 kb
Host smart-31327e4b-0da0-46ce-9f28-200f0843f2e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774900476 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.774900476
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.948672392
Short name T282
Test name
Test status
Simulation time 102680300 ps
CPU time 1.18 seconds
Started Jul 10 07:21:41 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 217432 kb
Host smart-427f9a18-f6e6-4ae9-be24-dfa6899190ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948672392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.948672392
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3881878487
Short name T935
Test name
Test status
Simulation time 49181282 ps
CPU time 1.03 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 229872 kb
Host smart-7fe868cf-e118-4b10-803b-5460e15bd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881878487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3881878487
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.717341312
Short name T464
Test name
Test status
Simulation time 71129807 ps
CPU time 1.67 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 219008 kb
Host smart-8846c5e4-e481-47cf-a372-4a0b87fba2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717341312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.717341312
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1772683953
Short name T797
Test name
Test status
Simulation time 27862476 ps
CPU time 1.06 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 224316 kb
Host smart-4a99bb6c-5fda-4830-9610-a60b9f5ba5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772683953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1772683953
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2851834695
Short name T33
Test name
Test status
Simulation time 39228156 ps
CPU time 0.96 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 207348 kb
Host smart-fa0a819e-69a4-46eb-8e0e-d0a10b4f9530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851834695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2851834695
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1116255651
Short name T461
Test name
Test status
Simulation time 54263881 ps
CPU time 0.95 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 215540 kb
Host smart-548a7719-0d80-4bab-8c75-b773a571e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116255651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1116255651
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.510612784
Short name T890
Test name
Test status
Simulation time 39459794678 ps
CPU time 442.45 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:29:09 PM PDT 24
Peak memory 219344 kb
Host smart-98bd6ff2-8111-45f8-82f8-9c68a42e091e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510612784 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.510612784
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3395540810
Short name T307
Test name
Test status
Simulation time 27883829 ps
CPU time 1.3 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 219968 kb
Host smart-481e4b57-4ae3-407a-94cd-c99537ee4505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395540810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3395540810
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3867298320
Short name T965
Test name
Test status
Simulation time 43438806 ps
CPU time 0.92 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:44 PM PDT 24
Peak memory 207068 kb
Host smart-1bd0e22d-669a-4b4a-99af-87cf516ca49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867298320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3867298320
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2253252122
Short name T437
Test name
Test status
Simulation time 24265793 ps
CPU time 0.92 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 216472 kb
Host smart-1641805f-5d18-4b47-848f-f7b5fdc61404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253252122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2253252122
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.850563757
Short name T453
Test name
Test status
Simulation time 38092347 ps
CPU time 1.26 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 220172 kb
Host smart-52a5278c-d9ff-4a30-b98f-9526b97c3d5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850563757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.850563757
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.823771224
Short name T844
Test name
Test status
Simulation time 31054839 ps
CPU time 1.18 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 229828 kb
Host smart-f8663261-766f-4132-b0c3-42936f436023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823771224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.823771224
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.145456004
Short name T502
Test name
Test status
Simulation time 41559641 ps
CPU time 1.13 seconds
Started Jul 10 07:21:37 PM PDT 24
Finished Jul 10 07:21:41 PM PDT 24
Peak memory 217652 kb
Host smart-2e7eafd3-f603-4cec-a24f-61dc62c49c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145456004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.145456004
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.729329172
Short name T748
Test name
Test status
Simulation time 35345292 ps
CPU time 0.94 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 215880 kb
Host smart-6d0c4fef-e42f-4587-8f8b-54d27d36e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729329172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.729329172
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.616047551
Short name T736
Test name
Test status
Simulation time 53162794 ps
CPU time 0.93 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:44 PM PDT 24
Peak memory 207448 kb
Host smart-6f4b4e3c-3b74-421c-b878-5fe01015506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616047551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.616047551
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3936640642
Short name T777
Test name
Test status
Simulation time 52920386 ps
CPU time 0.88 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 215720 kb
Host smart-a799d7ee-eaa1-416c-8d45-9a0880ab6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936640642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3936640642
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1728819490
Short name T993
Test name
Test status
Simulation time 79553243 ps
CPU time 1.42 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 207472 kb
Host smart-61104733-dcc4-4b19-8795-d2b2113b8490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728819490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1728819490
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3807123071
Short name T84
Test name
Test status
Simulation time 343459387832 ps
CPU time 738.14 seconds
Started Jul 10 07:21:46 PM PDT 24
Finished Jul 10 07:34:07 PM PDT 24
Peak memory 220348 kb
Host smart-80f09c35-0926-41cd-9ba5-23644ff8799c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807123071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3807123071
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3017529749
Short name T294
Test name
Test status
Simulation time 25882122 ps
CPU time 1.29 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 220204 kb
Host smart-427d9130-685e-4bfc-b505-9a84ef6a44d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017529749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3017529749
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.3557844335
Short name T126
Test name
Test status
Simulation time 26565062 ps
CPU time 0.97 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:04 PM PDT 24
Peak memory 220088 kb
Host smart-b5ad1b40-c610-41d5-b4af-caf138dd3919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557844335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3557844335
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1689711547
Short name T454
Test name
Test status
Simulation time 126714074 ps
CPU time 3.05 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 218904 kb
Host smart-38184039-f82e-4a3d-aae6-4a5c24a7de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689711547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1689711547
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.832878221
Short name T102
Test name
Test status
Simulation time 17622670 ps
CPU time 0.99 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 215652 kb
Host smart-9746c168-6eea-4e39-a0af-539c35bfacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832878221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.832878221
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1488156560
Short name T81
Test name
Test status
Simulation time 432241441 ps
CPU time 2.69 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 217868 kb
Host smart-543251c4-a01f-4dad-9fd7-67ccfc15399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488156560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1488156560
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.278388113
Short name T9
Test name
Test status
Simulation time 24445820 ps
CPU time 1.33 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 219028 kb
Host smart-3548a8db-d26b-4f31-98d6-31dc50af024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278388113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.278388113
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.386408837
Short name T27
Test name
Test status
Simulation time 133653479 ps
CPU time 1.27 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 217732 kb
Host smart-e6650ee9-9612-4204-ada9-4dc035e20f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386408837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.386408837
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2174469894
Short name T985
Test name
Test status
Simulation time 47376324 ps
CPU time 1.24 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 219972 kb
Host smart-f10abfb3-5efb-44a1-add9-625cb53cbf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174469894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2174469894
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3446416314
Short name T783
Test name
Test status
Simulation time 57433455 ps
CPU time 1.29 seconds
Started Jul 10 07:23:22 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 220144 kb
Host smart-20c15e35-70b4-45fb-a022-3a8bbabec6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446416314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3446416314
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.971973306
Short name T285
Test name
Test status
Simulation time 128206372 ps
CPU time 1.38 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 219084 kb
Host smart-82a93cae-2024-4b53-8f7e-e7d85264ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971973306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.971973306
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.628713086
Short name T477
Test name
Test status
Simulation time 79918028 ps
CPU time 1.41 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 219724 kb
Host smart-6b00d201-8387-412c-bbe7-8e379bece545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628713086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.628713086
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1126625287
Short name T455
Test name
Test status
Simulation time 66113571 ps
CPU time 1.21 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 220168 kb
Host smart-f9690473-2992-49f4-a3fb-5047d22db63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126625287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1126625287
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2492160761
Short name T825
Test name
Test status
Simulation time 64926273 ps
CPU time 1.05 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 217692 kb
Host smart-5021d125-dad3-42e1-94d7-e9e2f9b1f684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492160761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2492160761
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.4180556651
Short name T306
Test name
Test status
Simulation time 146501966 ps
CPU time 1.29 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 220496 kb
Host smart-3e75f605-5456-49d3-b83e-29ec43494b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180556651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.4180556651
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3764563409
Short name T350
Test name
Test status
Simulation time 64292773 ps
CPU time 0.99 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 219624 kb
Host smart-2b356c8c-b915-4386-b013-357ff836cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764563409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3764563409
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1583884118
Short name T865
Test name
Test status
Simulation time 105516085 ps
CPU time 1.27 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 219024 kb
Host smart-b88b2406-37a2-47a3-a9b3-650bb23f7b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583884118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1583884118
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3533036477
Short name T734
Test name
Test status
Simulation time 37835544 ps
CPU time 1.12 seconds
Started Jul 10 07:23:22 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 219120 kb
Host smart-6a54dd90-e875-41e4-bc7a-be0b9a2f592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533036477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3533036477
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2943070075
Short name T13
Test name
Test status
Simulation time 83657960 ps
CPU time 1.17 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 220320 kb
Host smart-4dba4279-f797-42c7-ad87-a932f5ab77c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943070075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2943070075
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.660307928
Short name T667
Test name
Test status
Simulation time 39333171 ps
CPU time 1.17 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 220392 kb
Host smart-85b0e437-ad3e-4052-85fd-3891bc156fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660307928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.660307928
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2215635996
Short name T992
Test name
Test status
Simulation time 148293721 ps
CPU time 1.94 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 220716 kb
Host smart-ad974c79-911e-489e-93be-7ca424103803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215635996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2215635996
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3932279769
Short name T989
Test name
Test status
Simulation time 32309963 ps
CPU time 1.13 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 218996 kb
Host smart-b71b7ff5-abcf-4787-9e3e-b85f1ebbdfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932279769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3932279769
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.699412609
Short name T970
Test name
Test status
Simulation time 62098548 ps
CPU time 1.08 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 219180 kb
Host smart-5db2b508-6313-4638-bee0-870eb3f2d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699412609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.699412609
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1629044153
Short name T3
Test name
Test status
Simulation time 39938329 ps
CPU time 1.06 seconds
Started Jul 10 07:23:32 PM PDT 24
Finished Jul 10 07:23:35 PM PDT 24
Peak memory 219956 kb
Host smart-f02a188c-92e0-4dfc-b6f6-8b8e1b3738c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629044153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1629044153
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2113148934
Short name T967
Test name
Test status
Simulation time 77267048 ps
CPU time 1.3 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 220384 kb
Host smart-c252a4f0-7d5a-4b02-9d53-8714380f265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113148934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2113148934
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1635192838
Short name T987
Test name
Test status
Simulation time 70095569 ps
CPU time 0.97 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:22:08 PM PDT 24
Peak memory 207072 kb
Host smart-df1d2896-2e25-4c39-babd-6e4dd8cbb356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635192838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1635192838
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3801230411
Short name T755
Test name
Test status
Simulation time 20367901 ps
CPU time 0.87 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:22:08 PM PDT 24
Peak memory 216596 kb
Host smart-f684ff25-1946-404e-b283-8bb1c24e4437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801230411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3801230411
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2283813737
Short name T878
Test name
Test status
Simulation time 147706672 ps
CPU time 1.14 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:15 PM PDT 24
Peak memory 219804 kb
Host smart-6de0341c-9da9-453f-80d6-ea86e2827a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283813737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2283813737
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.4254656287
Short name T122
Test name
Test status
Simulation time 24041522 ps
CPU time 1.09 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 216124 kb
Host smart-1a2eb5c8-7480-4fca-9c82-db089f8fd5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254656287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4254656287
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1566997955
Short name T708
Test name
Test status
Simulation time 23304148 ps
CPU time 0.93 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215624 kb
Host smart-20123579-141c-476a-b00b-432e09ea2495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566997955 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1566997955
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2299631106
Short name T582
Test name
Test status
Simulation time 216544862 ps
CPU time 2.64 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 217660 kb
Host smart-2ed3ab58-505d-47e8-b5d7-39ce1f003695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299631106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2299631106
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2049461768
Short name T586
Test name
Test status
Simulation time 494462968477 ps
CPU time 2085.32 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:56:49 PM PDT 24
Peak memory 227284 kb
Host smart-71cda3f9-1433-4c61-93d6-72dd565ff69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049461768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2049461768
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.902529293
Short name T161
Test name
Test status
Simulation time 44248687 ps
CPU time 1.18 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 219780 kb
Host smart-b0023440-bef2-494c-923b-b10603dd696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902529293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.902529293
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1926601542
Short name T442
Test name
Test status
Simulation time 79471037 ps
CPU time 1.36 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 219184 kb
Host smart-4f7484cc-ffa0-43a9-82f2-1edec49b49ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926601542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1926601542
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3508552023
Short name T876
Test name
Test status
Simulation time 55587006 ps
CPU time 1.32 seconds
Started Jul 10 07:23:26 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 218932 kb
Host smart-4fe5574c-1fab-4d87-b02b-adfef6f04050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508552023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3508552023
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1412851916
Short name T572
Test name
Test status
Simulation time 27615915 ps
CPU time 1.24 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 218976 kb
Host smart-657e6321-b03c-419f-bda8-83256db0ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412851916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1412851916
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1492085837
Short name T564
Test name
Test status
Simulation time 110927898 ps
CPU time 1.22 seconds
Started Jul 10 07:23:31 PM PDT 24
Finished Jul 10 07:23:34 PM PDT 24
Peak memory 220356 kb
Host smart-b9b15c7a-3b37-4b36-82a5-e41eeeb4f724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492085837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1492085837
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4241298682
Short name T342
Test name
Test status
Simulation time 90035900 ps
CPU time 2.22 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:34 PM PDT 24
Peak memory 220624 kb
Host smart-cb496f80-a960-420b-9aed-c257eea866ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241298682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4241298682
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3468012020
Short name T855
Test name
Test status
Simulation time 31557510 ps
CPU time 1.25 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:37 PM PDT 24
Peak memory 221012 kb
Host smart-e93b68ae-54f5-4555-9756-48d8f3dfbe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468012020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3468012020
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3267392425
Short name T536
Test name
Test status
Simulation time 69403370 ps
CPU time 1.52 seconds
Started Jul 10 07:23:30 PM PDT 24
Finished Jul 10 07:23:34 PM PDT 24
Peak memory 219344 kb
Host smart-9a00db9f-acbe-4422-9b0c-dd274a7e932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267392425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3267392425
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2923858657
Short name T145
Test name
Test status
Simulation time 88199587 ps
CPU time 1.08 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 220200 kb
Host smart-841c8bf7-7984-4ebb-91de-2f27ed185439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923858657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2923858657
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3195976503
Short name T706
Test name
Test status
Simulation time 66089764 ps
CPU time 1.59 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 218756 kb
Host smart-060b8450-2ff4-4c80-bd2f-2d3d8811197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195976503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3195976503
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4214280305
Short name T656
Test name
Test status
Simulation time 125591808 ps
CPU time 1.17 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 220184 kb
Host smart-b375c6b5-2753-4409-bc44-b2829c1001c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214280305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4214280305
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3339623557
Short name T665
Test name
Test status
Simulation time 108150962 ps
CPU time 1.6 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:42 PM PDT 24
Peak memory 219380 kb
Host smart-6c5f8770-6594-450f-bb60-f679013e8e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339623557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3339623557
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4236343711
Short name T375
Test name
Test status
Simulation time 117449608 ps
CPU time 1.34 seconds
Started Jul 10 07:23:24 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 217576 kb
Host smart-c23c277d-e656-4ef3-b940-43f78fa2ec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236343711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4236343711
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3211990595
Short name T918
Test name
Test status
Simulation time 78841506 ps
CPU time 1.29 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:39 PM PDT 24
Peak memory 216036 kb
Host smart-8336e976-33d8-4b9d-b10b-bb53eef52c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211990595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3211990595
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4157621605
Short name T328
Test name
Test status
Simulation time 63764364 ps
CPU time 1.49 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 219160 kb
Host smart-b2274ffb-df6d-4e43-801b-92e5d8d795c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157621605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4157621605
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3117463670
Short name T990
Test name
Test status
Simulation time 29159415 ps
CPU time 1.21 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 220024 kb
Host smart-7d6876ef-55f0-4192-ad82-edd053414a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117463670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3117463670
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2425272133
Short name T407
Test name
Test status
Simulation time 80430032 ps
CPU time 1.15 seconds
Started Jul 10 07:23:34 PM PDT 24
Finished Jul 10 07:23:36 PM PDT 24
Peak memory 219036 kb
Host smart-c38463bd-64d1-4710-a927-9eb4fd70661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425272133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2425272133
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.230672568
Short name T485
Test name
Test status
Simulation time 51705347 ps
CPU time 1.14 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 221064 kb
Host smart-d394b1a9-29ab-40e1-992d-5c1e24479f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230672568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.230672568
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3702497674
Short name T355
Test name
Test status
Simulation time 57504379 ps
CPU time 0.87 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 215044 kb
Host smart-37ba1ec1-3cac-469c-8d50-c6ecca4886ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702497674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3702497674
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.1486393508
Short name T89
Test name
Test status
Simulation time 19350693 ps
CPU time 1.11 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 218860 kb
Host smart-80145250-36aa-4c36-af10-5bc6aadd764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486393508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1486393508
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.337926928
Short name T838
Test name
Test status
Simulation time 74675251 ps
CPU time 1.76 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:15 PM PDT 24
Peak memory 220480 kb
Host smart-22c6d3f4-4202-4a6d-ba19-94fae6eaee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337926928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.337926928
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1539445734
Short name T827
Test name
Test status
Simulation time 36600710 ps
CPU time 0.88 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:02 PM PDT 24
Peak memory 215856 kb
Host smart-c43b25a4-4e3a-4e58-ac4c-989c89298a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539445734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1539445734
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1730264330
Short name T347
Test name
Test status
Simulation time 23466057 ps
CPU time 0.92 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 215664 kb
Host smart-2dce7c29-661a-4d30-a727-d1130edd6af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730264330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1730264330
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1998288559
Short name T767
Test name
Test status
Simulation time 321769319 ps
CPU time 5.22 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 217644 kb
Host smart-d6bc5600-b5e5-4d6e-9bab-1b14794abf66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998288559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1998288559
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3292822269
Short name T722
Test name
Test status
Simulation time 71490720760 ps
CPU time 1572.31 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:48:19 PM PDT 24
Peak memory 224128 kb
Host smart-f22158cf-ab71-4934-ab30-26617204b89f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292822269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3292822269
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.484981143
Short name T599
Test name
Test status
Simulation time 268349891 ps
CPU time 1.1 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 217588 kb
Host smart-390b0e49-c77b-46f8-aa53-1833faeb4709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484981143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.484981143
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3280160937
Short name T598
Test name
Test status
Simulation time 43020882 ps
CPU time 1.09 seconds
Started Jul 10 07:23:26 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 220500 kb
Host smart-1bdead88-147a-43da-bf2e-637ef6542406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280160937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3280160937
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.895827637
Short name T495
Test name
Test status
Simulation time 31965691 ps
CPU time 1.44 seconds
Started Jul 10 07:23:32 PM PDT 24
Finished Jul 10 07:23:35 PM PDT 24
Peak memory 218780 kb
Host smart-cf097c5b-0929-4869-af0c-79d7e4607807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895827637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.895827637
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1762022027
Short name T300
Test name
Test status
Simulation time 48439924 ps
CPU time 1.15 seconds
Started Jul 10 07:23:39 PM PDT 24
Finished Jul 10 07:23:46 PM PDT 24
Peak memory 220136 kb
Host smart-b4805f64-1353-47df-9d43-cce7dbccc69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762022027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1762022027
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3801700848
Short name T445
Test name
Test status
Simulation time 30920588 ps
CPU time 1.28 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 217520 kb
Host smart-1eac3ef7-0f3a-41b3-808e-10829a090a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801700848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3801700848
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.788826291
Short name T408
Test name
Test status
Simulation time 23572006 ps
CPU time 1.12 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 218952 kb
Host smart-e65ae4ae-ab93-4fdc-b873-89fb006cde1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788826291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.788826291
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3407960924
Short name T371
Test name
Test status
Simulation time 31190690 ps
CPU time 1.2 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 217192 kb
Host smart-4970eaad-10ad-440a-b527-3c215f26bd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407960924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3407960924
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3440351785
Short name T507
Test name
Test status
Simulation time 87406291 ps
CPU time 1 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:41 PM PDT 24
Peak memory 217488 kb
Host smart-c26cf87e-83d5-4041-92b1-8db7e86f9144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440351785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3440351785
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3305501453
Short name T589
Test name
Test status
Simulation time 61513414 ps
CPU time 1.31 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 218952 kb
Host smart-3fcb0212-5f95-4801-94fe-775d25f5a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305501453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3305501453
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2574828615
Short name T879
Test name
Test status
Simulation time 76414737 ps
CPU time 1.27 seconds
Started Jul 10 07:23:24 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 220100 kb
Host smart-d9dba406-8fc9-4241-b743-612deebb84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574828615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2574828615
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3889981227
Short name T519
Test name
Test status
Simulation time 83347234 ps
CPU time 1.34 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 219464 kb
Host smart-a9e301c8-ded3-4cf3-a2f3-c0b0453645de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889981227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3889981227
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3084010888
Short name T520
Test name
Test status
Simulation time 210082313 ps
CPU time 1.4 seconds
Started Jul 10 07:23:29 PM PDT 24
Finished Jul 10 07:23:34 PM PDT 24
Peak memory 219308 kb
Host smart-57813375-736c-40f5-8a62-3cfdcb02fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084010888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3084010888
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3847971159
Short name T501
Test name
Test status
Simulation time 31069977 ps
CPU time 1.23 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:28 PM PDT 24
Peak memory 218720 kb
Host smart-03e76959-26a9-4c37-9a1a-fb4aff9088b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847971159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3847971159
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.4053405454
Short name T950
Test name
Test status
Simulation time 22798107 ps
CPU time 1.22 seconds
Started Jul 10 07:23:39 PM PDT 24
Finished Jul 10 07:23:46 PM PDT 24
Peak memory 219072 kb
Host smart-3e1e6d68-4ba3-4985-b751-d5168d4d160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053405454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4053405454
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.905884969
Short name T296
Test name
Test status
Simulation time 26480800 ps
CPU time 1.19 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 219020 kb
Host smart-9e18590f-a746-4b7e-b650-c3b99b68e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905884969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.905884969
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2967882510
Short name T416
Test name
Test status
Simulation time 46119394 ps
CPU time 1.3 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 219016 kb
Host smart-f75156c4-ab35-4f40-a8b7-9921b2b281a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967882510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2967882510
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.951816504
Short name T193
Test name
Test status
Simulation time 109550517 ps
CPU time 1.17 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 219484 kb
Host smart-f2b2fb9f-02d2-4006-8fa9-3169cc080be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951816504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.951816504
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3274051899
Short name T524
Test name
Test status
Simulation time 20203089 ps
CPU time 0.99 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:09 PM PDT 24
Peak memory 215388 kb
Host smart-5a6e0b27-a653-4b78-b493-96879d48f185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274051899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3274051899
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2110577559
Short name T633
Test name
Test status
Simulation time 13801688 ps
CPU time 0.94 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215936 kb
Host smart-b7ccff93-9c4a-48a9-8fed-71f2c0c91408
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110577559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2110577559
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2161628503
Short name T913
Test name
Test status
Simulation time 159771056 ps
CPU time 1.14 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 217252 kb
Host smart-354a7cb2-c06f-4aa6-b7b1-1c0f2a0c0b29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161628503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2161628503
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2344284514
Short name T129
Test name
Test status
Simulation time 39436408 ps
CPU time 1.04 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 217460 kb
Host smart-a59fb56b-c305-406c-af53-7ee52ca4be08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344284514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2344284514
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.712693646
Short name T647
Test name
Test status
Simulation time 22383207 ps
CPU time 1.06 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 215748 kb
Host smart-ba4fa764-b9d9-4b32-8bba-0b0edf21cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712693646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.712693646
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2273381059
Short name T675
Test name
Test status
Simulation time 19468196 ps
CPU time 0.96 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 215608 kb
Host smart-06983672-7740-4fc2-871d-e04d0c4c099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273381059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2273381059
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1453857991
Short name T837
Test name
Test status
Simulation time 622660600 ps
CPU time 4.69 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 218816 kb
Host smart-afa04bea-623f-49e4-bb85-e38be59dfc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453857991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1453857991
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1365950819
Short name T245
Test name
Test status
Simulation time 100788934614 ps
CPU time 368.51 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:28:11 PM PDT 24
Peak memory 219984 kb
Host smart-3e096fc8-67b6-47be-85a1-e37221850260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365950819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1365950819
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3132819327
Short name T517
Test name
Test status
Simulation time 77159764 ps
CPU time 1.02 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:38 PM PDT 24
Peak memory 220148 kb
Host smart-a28d6f8f-d355-4d5a-89ff-15893b03cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132819327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3132819327
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2058828480
Short name T481
Test name
Test status
Simulation time 102102367 ps
CPU time 1.18 seconds
Started Jul 10 07:23:34 PM PDT 24
Finished Jul 10 07:23:37 PM PDT 24
Peak memory 217724 kb
Host smart-f4c34755-fe0d-48e1-9d94-c93820c291c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058828480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2058828480
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.606313444
Short name T626
Test name
Test status
Simulation time 49876309 ps
CPU time 1.62 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:48 PM PDT 24
Peak memory 218864 kb
Host smart-db6d50c8-f6be-40e9-849b-a746e5987a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606313444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.606313444
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1617589174
Short name T926
Test name
Test status
Simulation time 83408637 ps
CPU time 1.1 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:38 PM PDT 24
Peak memory 216032 kb
Host smart-b5e98a89-f711-4cdb-b0bd-79b360a69eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617589174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1617589174
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1199579981
Short name T468
Test name
Test status
Simulation time 35106813 ps
CPU time 1.32 seconds
Started Jul 10 07:23:36 PM PDT 24
Finished Jul 10 07:23:40 PM PDT 24
Peak memory 218708 kb
Host smart-a7eb0137-de95-43f6-a19e-14b9cf8bb520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199579981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1199579981
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.886384344
Short name T583
Test name
Test status
Simulation time 22835320 ps
CPU time 1.16 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 220096 kb
Host smart-82c49961-f356-4186-b258-1562a0264a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886384344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.886384344
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.178441632
Short name T490
Test name
Test status
Simulation time 55954887 ps
CPU time 2.33 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 220580 kb
Host smart-be7e1f91-6c6c-4251-86b1-c26134ffe009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178441632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.178441632
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3222985248
Short name T410
Test name
Test status
Simulation time 31202384 ps
CPU time 1.34 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 221108 kb
Host smart-e97e5d8d-a72f-46fc-a02e-cf7e463a6e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222985248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3222985248
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.441897195
Short name T563
Test name
Test status
Simulation time 60002873 ps
CPU time 0.98 seconds
Started Jul 10 07:23:39 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217688 kb
Host smart-42bdce09-06bc-4a90-b030-78e9e6fe4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441897195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.441897195
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.4083037227
Short name T963
Test name
Test status
Simulation time 29868563 ps
CPU time 1.25 seconds
Started Jul 10 07:23:39 PM PDT 24
Finished Jul 10 07:23:46 PM PDT 24
Peak memory 218896 kb
Host smart-70ff66ed-d42c-47e5-acff-f89c835ba52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083037227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4083037227
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.272994902
Short name T64
Test name
Test status
Simulation time 98154157 ps
CPU time 1.11 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 219292 kb
Host smart-c6712fb6-abea-4046-b41d-23e34223e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272994902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.272994902
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1035269180
Short name T515
Test name
Test status
Simulation time 88620561 ps
CPU time 1.17 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 219012 kb
Host smart-00eb28dd-3e40-4085-86fb-f1904254fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035269180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1035269180
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.919680657
Short name T543
Test name
Test status
Simulation time 129184436 ps
CPU time 1.22 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 215680 kb
Host smart-749ecf8d-5e06-48bd-8ff1-afbf4d829e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919680657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.919680657
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2815265278
Short name T308
Test name
Test status
Simulation time 24525906 ps
CPU time 1.19 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 219500 kb
Host smart-ba26c152-18b6-4af4-8168-709a5661134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815265278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2815265278
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3262019018
Short name T420
Test name
Test status
Simulation time 60778867 ps
CPU time 1.66 seconds
Started Jul 10 07:23:41 PM PDT 24
Finished Jul 10 07:23:48 PM PDT 24
Peak memory 220316 kb
Host smart-ec90b8b1-93fc-4a90-bfd2-9be526cd748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262019018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3262019018
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1600100121
Short name T134
Test name
Test status
Simulation time 104279569 ps
CPU time 1.2 seconds
Started Jul 10 07:23:35 PM PDT 24
Finished Jul 10 07:23:37 PM PDT 24
Peak memory 220392 kb
Host smart-ac58f6c4-17e2-4aa2-a0b0-6b252dc620cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600100121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1600100121
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.288324255
Short name T77
Test name
Test status
Simulation time 59007452 ps
CPU time 1.51 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:43 PM PDT 24
Peak memory 219044 kb
Host smart-d9cceaa1-05be-4bc2-aa51-cd8bc340cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288324255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.288324255
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1896703076
Short name T605
Test name
Test status
Simulation time 77102217 ps
CPU time 1.16 seconds
Started Jul 10 07:23:25 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 219380 kb
Host smart-a3f40206-b282-4931-ace8-40324a68fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896703076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1896703076
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1399161868
Short name T440
Test name
Test status
Simulation time 52604983 ps
CPU time 1.47 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 218704 kb
Host smart-1f0802e5-e65a-4139-be07-e2bb2337ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399161868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1399161868
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3958974131
Short name T908
Test name
Test status
Simulation time 21605110 ps
CPU time 1.17 seconds
Started Jul 10 07:22:04 PM PDT 24
Finished Jul 10 07:22:09 PM PDT 24
Peak memory 219056 kb
Host smart-aa6f4137-1c62-4d6b-a756-e6dd749dd238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958974131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3958974131
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4141960524
Short name T399
Test name
Test status
Simulation time 48157668 ps
CPU time 0.9 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:22:16 PM PDT 24
Peak memory 207076 kb
Host smart-cd32fce1-ae46-4e06-8742-cffb21b8b0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141960524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4141960524
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1143967794
Short name T188
Test name
Test status
Simulation time 21600007 ps
CPU time 0.88 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 216652 kb
Host smart-803e5d9f-a222-4018-a338-9a9fab4ba5ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143967794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1143967794
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1539740586
Short name T435
Test name
Test status
Simulation time 131756171 ps
CPU time 1.01 seconds
Started Jul 10 07:22:18 PM PDT 24
Finished Jul 10 07:22:23 PM PDT 24
Peak memory 218376 kb
Host smart-55f8e275-08c7-4b24-b231-6645c6b299d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539740586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1539740586
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1033252683
Short name T176
Test name
Test status
Simulation time 18532153 ps
CPU time 1.01 seconds
Started Jul 10 07:22:17 PM PDT 24
Finished Jul 10 07:22:22 PM PDT 24
Peak memory 218776 kb
Host smart-de0ad1e0-abec-47a7-9e91-b70e7f341712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033252683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1033252683
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3256448367
Short name T896
Test name
Test status
Simulation time 43030393 ps
CPU time 1.66 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 220328 kb
Host smart-f8ec9588-7eb0-4272-a3ac-ab4ffab6b249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256448367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3256448367
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3675050424
Short name T35
Test name
Test status
Simulation time 20276281 ps
CPU time 1.14 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 216288 kb
Host smart-1b4ea8e2-18ff-415b-9809-4f0e75595258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675050424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3675050424
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2352898963
Short name T25
Test name
Test status
Simulation time 48522351 ps
CPU time 0.92 seconds
Started Jul 10 07:22:04 PM PDT 24
Finished Jul 10 07:22:08 PM PDT 24
Peak memory 215580 kb
Host smart-5b60a619-00ef-4575-b424-dfcc85cc6b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352898963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2352898963
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.146699032
Short name T482
Test name
Test status
Simulation time 131792016 ps
CPU time 1.53 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 215688 kb
Host smart-d425dbd1-8a56-4db4-87ca-979f7f972dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146699032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.146699032
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.493748755
Short name T246
Test name
Test status
Simulation time 50424597531 ps
CPU time 510.55 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:30:40 PM PDT 24
Peak memory 219136 kb
Host smart-729c88ef-4e76-49de-8709-c6874d3daaa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493748755 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.493748755
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3230700830
Short name T230
Test name
Test status
Simulation time 70115863 ps
CPU time 1.09 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 221712 kb
Host smart-0bf1d382-057c-44bd-8f36-e85d9e1e1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230700830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3230700830
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1584499973
Short name T397
Test name
Test status
Simulation time 80660748 ps
CPU time 1.21 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217912 kb
Host smart-75bcfc77-9a09-4484-b604-4b23646aa452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584499973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1584499973
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2413868940
Short name T234
Test name
Test status
Simulation time 77398946 ps
CPU time 1.17 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 220612 kb
Host smart-a42f2b09-2a32-439f-99ee-cf6b4debaeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413868940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2413868940
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.123347148
Short name T428
Test name
Test status
Simulation time 39438871 ps
CPU time 1.1 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 218808 kb
Host smart-b131e783-1c13-4947-98a0-3a42e5a87d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123347148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.123347148
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1506770009
Short name T367
Test name
Test status
Simulation time 34011391 ps
CPU time 1.29 seconds
Started Jul 10 07:23:37 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 215640 kb
Host smart-dbe39b99-c207-4467-ab5d-d9152821eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506770009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1506770009
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3935517007
Short name T790
Test name
Test status
Simulation time 83167820 ps
CPU time 1.2 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 219408 kb
Host smart-b1690226-f323-4dbe-af9c-afa30cdb2f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935517007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3935517007
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.98257564
Short name T366
Test name
Test status
Simulation time 34703623 ps
CPU time 1.04 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217564 kb
Host smart-e71581e4-7726-48b1-93d8-56ce41a24bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98257564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.98257564
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1032426620
Short name T295
Test name
Test status
Simulation time 223982417 ps
CPU time 1.24 seconds
Started Jul 10 07:23:39 PM PDT 24
Finished Jul 10 07:23:46 PM PDT 24
Peak memory 218944 kb
Host smart-97d5bc82-78c5-497f-b1a1-f123c8dd1f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032426620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1032426620
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4261919416
Short name T473
Test name
Test status
Simulation time 84035219 ps
CPU time 1.25 seconds
Started Jul 10 07:23:25 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 217600 kb
Host smart-5ecca958-382a-4162-b662-f0edf5b7b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261919416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4261919416
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1029072235
Short name T977
Test name
Test status
Simulation time 46808000 ps
CPU time 1.48 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 218660 kb
Host smart-818e5001-5acf-4674-b97c-c30e55202b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029072235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1029072235
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3794335070
Short name T831
Test name
Test status
Simulation time 167328191 ps
CPU time 2.19 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 220348 kb
Host smart-657ee204-353b-45fe-b419-8a86c9877b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794335070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3794335070
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3162078490
Short name T254
Test name
Test status
Simulation time 28180125 ps
CPU time 1.4 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 219088 kb
Host smart-8218254e-ea6c-414b-ad00-32d929e18bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162078490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3162078490
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3264984245
Short name T514
Test name
Test status
Simulation time 23646659 ps
CPU time 1.14 seconds
Started Jul 10 07:23:43 PM PDT 24
Finished Jul 10 07:23:50 PM PDT 24
Peak memory 217624 kb
Host smart-462709f6-e223-49fd-bc6f-8d67c31fff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264984245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3264984245
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2450149148
Short name T916
Test name
Test status
Simulation time 33153057 ps
CPU time 1.19 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 219760 kb
Host smart-3471b7d4-7fbf-4910-88cc-3c9edae96dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450149148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2450149148
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3563032137
Short name T947
Test name
Test status
Simulation time 70103168 ps
CPU time 1.41 seconds
Started Jul 10 07:23:52 PM PDT 24
Finished Jul 10 07:23:56 PM PDT 24
Peak memory 219080 kb
Host smart-7ab3d7e6-8641-4265-93bf-b78f8f2000ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563032137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3563032137
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3054527340
Short name T869
Test name
Test status
Simulation time 280387733 ps
CPU time 1.32 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 219376 kb
Host smart-62f08122-64fb-4737-8600-bbda93f5651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054527340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3054527340
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.2862999181
Short name T299
Test name
Test status
Simulation time 27495810 ps
CPU time 1.29 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 219824 kb
Host smart-a861a3b2-2ed5-4a88-9073-34aafa2c235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862999181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2862999181
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2528581588
Short name T547
Test name
Test status
Simulation time 19522299 ps
CPU time 0.84 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 207176 kb
Host smart-55954b38-7d30-40ba-9319-a1b768ad1737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528581588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2528581588
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3064535279
Short name T198
Test name
Test status
Simulation time 19569611 ps
CPU time 0.91 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 216852 kb
Host smart-41b63e86-9443-44a3-8588-6f2259919a9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064535279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3064535279
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2729282013
Short name T652
Test name
Test status
Simulation time 140126441 ps
CPU time 1.15 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 217312 kb
Host smart-6d70deed-dbb3-4f74-8f0c-7a1ed7d1740c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729282013 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2729282013
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1260171423
Short name T976
Test name
Test status
Simulation time 35481822 ps
CPU time 0.95 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 220028 kb
Host smart-d8db527b-c8ad-400f-9807-c56c2078f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260171423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1260171423
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2679376344
Short name T14
Test name
Test status
Simulation time 27144424 ps
CPU time 1.24 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 219772 kb
Host smart-0f5c75ba-a998-40a8-ae28-cda2224f008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679376344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2679376344
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3995849470
Short name T860
Test name
Test status
Simulation time 20247273 ps
CPU time 1.14 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:15 PM PDT 24
Peak memory 217144 kb
Host smart-daa1401e-0d2a-4304-b185-76132f72d339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995849470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3995849470
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2199489921
Short name T923
Test name
Test status
Simulation time 26944549 ps
CPU time 1.02 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 215624 kb
Host smart-3d9111f5-bda9-4089-8a44-e9f3f99c0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199489921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2199489921
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1053777611
Short name T984
Test name
Test status
Simulation time 472762208 ps
CPU time 5.43 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:16 PM PDT 24
Peak memory 217708 kb
Host smart-8eca4a98-087c-4a9b-a4b3-8e8620fc16af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053777611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1053777611
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.254352630
Short name T508
Test name
Test status
Simulation time 29297758076 ps
CPU time 707.47 seconds
Started Jul 10 07:22:15 PM PDT 24
Finished Jul 10 07:34:07 PM PDT 24
Peak memory 218776 kb
Host smart-be8f06b5-b38c-473d-a6df-6d93bc321f9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254352630 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.254352630
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3258107113
Short name T910
Test name
Test status
Simulation time 36190342 ps
CPU time 1.2 seconds
Started Jul 10 07:23:41 PM PDT 24
Finished Jul 10 07:23:49 PM PDT 24
Peak memory 219156 kb
Host smart-f975de03-eef0-428f-ac6d-3147f5efe497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258107113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3258107113
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.4267462067
Short name T868
Test name
Test status
Simulation time 72195352 ps
CPU time 1.27 seconds
Started Jul 10 07:23:42 PM PDT 24
Finished Jul 10 07:23:49 PM PDT 24
Peak memory 220252 kb
Host smart-0fbfae7d-c7b7-4660-a32c-e287b91dead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267462067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4267462067
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.593253768
Short name T848
Test name
Test status
Simulation time 33547991 ps
CPU time 1.06 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217728 kb
Host smart-b59d4643-706f-49a9-838d-30c85c7e53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593253768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.593253768
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2802548708
Short name T302
Test name
Test status
Simulation time 25019703 ps
CPU time 1.24 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 220272 kb
Host smart-082ed6bb-c3a2-4a9c-89d8-f70fc51533dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802548708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2802548708
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1990107862
Short name T696
Test name
Test status
Simulation time 175732681 ps
CPU time 1.15 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 220356 kb
Host smart-0481e716-9276-478b-8adb-eb275c50655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990107862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1990107862
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3841648513
Short name T139
Test name
Test status
Simulation time 54933490 ps
CPU time 1.3 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 220276 kb
Host smart-55335403-a003-4911-af78-5a227c3525f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841648513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3841648513
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2554632668
Short name T770
Test name
Test status
Simulation time 58954329 ps
CPU time 1.06 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 220264 kb
Host smart-a6e9f9b6-ab63-4600-b947-8c227091694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554632668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2554632668
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.818871580
Short name T92
Test name
Test status
Simulation time 25141312 ps
CPU time 1.16 seconds
Started Jul 10 07:23:43 PM PDT 24
Finished Jul 10 07:23:50 PM PDT 24
Peak memory 217720 kb
Host smart-fcf59305-400a-4ef5-aa04-05527f4dc834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818871580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.818871580
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.603749321
Short name T616
Test name
Test status
Simulation time 67480816 ps
CPU time 1.26 seconds
Started Jul 10 07:23:41 PM PDT 24
Finished Jul 10 07:23:48 PM PDT 24
Peak memory 220128 kb
Host smart-e620d5c2-c863-4f73-80e7-ae4a80fe6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603749321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.603749321
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2015215225
Short name T939
Test name
Test status
Simulation time 85971820 ps
CPU time 3.11 seconds
Started Jul 10 07:23:45 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 220244 kb
Host smart-4f2ea951-3ab7-4ffd-9648-982f68b7a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015215225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2015215225
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2535162266
Short name T710
Test name
Test status
Simulation time 26783607 ps
CPU time 1.27 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 220328 kb
Host smart-54769c29-8f5e-4eac-8abe-896884d0deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535162266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2535162266
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2841463249
Short name T886
Test name
Test status
Simulation time 28212803 ps
CPU time 1.22 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 217660 kb
Host smart-52199699-293e-42ed-b676-7162a201a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841463249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2841463249
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.946695417
Short name T304
Test name
Test status
Simulation time 26967995 ps
CPU time 1.18 seconds
Started Jul 10 07:23:50 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 220060 kb
Host smart-4141eb20-9d11-4fc0-91e9-3c655ee46126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946695417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.946695417
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1671114344
Short name T340
Test name
Test status
Simulation time 37660470 ps
CPU time 1.55 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 218844 kb
Host smart-53bac79a-17ac-41d2-82d7-cfe5940ac6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671114344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1671114344
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.715262402
Short name T559
Test name
Test status
Simulation time 31038289 ps
CPU time 1.3 seconds
Started Jul 10 07:23:44 PM PDT 24
Finished Jul 10 07:23:50 PM PDT 24
Peak memory 219936 kb
Host smart-2ee3d8c6-09eb-4607-a0ff-f9d3c8c1e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715262402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.715262402
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3896848499
Short name T55
Test name
Test status
Simulation time 87056128 ps
CPU time 1.51 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:54 PM PDT 24
Peak memory 219960 kb
Host smart-bfb311c3-0b5a-4760-9891-e4d429c14adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896848499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3896848499
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1115827371
Short name T636
Test name
Test status
Simulation time 85025907 ps
CPU time 1.11 seconds
Started Jul 10 07:22:11 PM PDT 24
Finished Jul 10 07:22:17 PM PDT 24
Peak memory 218724 kb
Host smart-83b5cf07-0881-463b-a22d-ae5cecc54224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115827371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1115827371
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2133390209
Short name T930
Test name
Test status
Simulation time 33167200 ps
CPU time 0.84 seconds
Started Jul 10 07:22:11 PM PDT 24
Finished Jul 10 07:22:17 PM PDT 24
Peak memory 206836 kb
Host smart-7619ab1b-dc39-4125-a0eb-ad9cef6f5548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133390209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2133390209
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2010040809
Short name T172
Test name
Test status
Simulation time 50774681 ps
CPU time 0.85 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:22:15 PM PDT 24
Peak memory 215748 kb
Host smart-68ff4e14-8153-4d63-a1d8-8bdf2be84c73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010040809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2010040809
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.969668177
Short name T964
Test name
Test status
Simulation time 56354101 ps
CPU time 1.24 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 217332 kb
Host smart-9e320698-7921-4dc8-be9e-8ed124ce6d52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969668177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.969668177
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2960086826
Short name T128
Test name
Test status
Simulation time 23336954 ps
CPU time 1.25 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 220100 kb
Host smart-3fa70171-113a-40ef-8a89-a599d92e5aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960086826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2960086826
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3651237288
Short name T446
Test name
Test status
Simulation time 89378983 ps
CPU time 1.07 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:22:08 PM PDT 24
Peak memory 218836 kb
Host smart-f0a4c174-6b5e-4a9c-be95-f17eb71942b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651237288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3651237288
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1340055651
Short name T612
Test name
Test status
Simulation time 31173490 ps
CPU time 0.99 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 215856 kb
Host smart-4136d675-727e-47fc-97ec-fa104493d3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340055651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1340055651
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4226672006
Short name T412
Test name
Test status
Simulation time 114052758 ps
CPU time 0.92 seconds
Started Jul 10 07:22:12 PM PDT 24
Finished Jul 10 07:22:17 PM PDT 24
Peak memory 215608 kb
Host smart-78009522-cf66-438c-add4-3e209b911bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226672006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4226672006
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1638004733
Short name T368
Test name
Test status
Simulation time 59220237 ps
CPU time 1.21 seconds
Started Jul 10 07:22:12 PM PDT 24
Finished Jul 10 07:22:18 PM PDT 24
Peak memory 217384 kb
Host smart-74db61f5-27d7-4afa-9e03-9b1c928b3ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638004733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1638004733
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.196139705
Short name T709
Test name
Test status
Simulation time 117279265945 ps
CPU time 656.65 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:33:09 PM PDT 24
Peak memory 220420 kb
Host smart-256e3143-6da9-49c6-bec8-69bc2db02f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196139705 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.196139705
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1507083793
Short name T133
Test name
Test status
Simulation time 27384291 ps
CPU time 1.26 seconds
Started Jul 10 07:23:43 PM PDT 24
Finished Jul 10 07:23:50 PM PDT 24
Peak memory 220892 kb
Host smart-3d52fe25-3053-4da7-b416-f830f652bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507083793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1507083793
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3344171950
Short name T415
Test name
Test status
Simulation time 72716931 ps
CPU time 1.3 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217732 kb
Host smart-191920cd-6724-4ee5-b042-cac8d156513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344171950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3344171950
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1982596598
Short name T190
Test name
Test status
Simulation time 35171115 ps
CPU time 1.1 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 220144 kb
Host smart-fdf4c758-0a0d-4ded-8942-b5f8e6443573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982596598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1982596598
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2271056953
Short name T902
Test name
Test status
Simulation time 93445550 ps
CPU time 1.48 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 219420 kb
Host smart-0aa93221-b384-45b1-8701-8d21cf2dbbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271056953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2271056953
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.83651803
Short name T341
Test name
Test status
Simulation time 952244543 ps
CPU time 6.76 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 219004 kb
Host smart-ed23e816-2ab5-4885-b6ad-142b1176916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83651803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.83651803
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.268276081
Short name T91
Test name
Test status
Simulation time 65111881 ps
CPU time 1.09 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 219212 kb
Host smart-a85c8e10-0104-4bb4-858c-259209dbebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268276081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.268276081
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/164.edn_alert.1646577736
Short name T651
Test name
Test status
Simulation time 36307445 ps
CPU time 1.13 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:44 PM PDT 24
Peak memory 219604 kb
Host smart-57b00a9e-5693-4e93-a7b1-f53b4d813b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646577736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1646577736
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.4219199746
Short name T897
Test name
Test status
Simulation time 53350481 ps
CPU time 1.51 seconds
Started Jul 10 07:23:41 PM PDT 24
Finished Jul 10 07:23:49 PM PDT 24
Peak memory 218816 kb
Host smart-c00fade4-0cb9-42fc-b03e-6738c51cf0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219199746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4219199746
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.372360591
Short name T597
Test name
Test status
Simulation time 109791197 ps
CPU time 1.23 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 219428 kb
Host smart-8cb14ce5-7120-4832-8bf1-502fb13c3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372360591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.372360591
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1436134422
Short name T447
Test name
Test status
Simulation time 106607690 ps
CPU time 1.11 seconds
Started Jul 10 07:23:38 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 217648 kb
Host smart-63cab500-ab94-4f70-ba5d-094dec671390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436134422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1436134422
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2131116598
Short name T284
Test name
Test status
Simulation time 52518947 ps
CPU time 1.26 seconds
Started Jul 10 07:23:40 PM PDT 24
Finished Jul 10 07:23:47 PM PDT 24
Peak memory 220880 kb
Host smart-2f066c05-ed21-4831-b910-3b30f759a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131116598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2131116598
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.1568703009
Short name T812
Test name
Test status
Simulation time 26712338 ps
CPU time 1.24 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 219668 kb
Host smart-29849ad8-d6f7-4b2f-b1e8-e0fd0661ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568703009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1568703009
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.687560444
Short name T933
Test name
Test status
Simulation time 88193445 ps
CPU time 1.16 seconds
Started Jul 10 07:23:45 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 217708 kb
Host smart-367a921e-4cef-4abf-9965-92de59cce249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687560444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.687560444
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2151350712
Short name T184
Test name
Test status
Simulation time 96296664 ps
CPU time 1.2 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 221236 kb
Host smart-6d877ca8-62f4-4358-8d39-19a75c56ecb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151350712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2151350712
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2545594865
Short name T365
Test name
Test status
Simulation time 51822277 ps
CPU time 1.3 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 219020 kb
Host smart-0ff4b779-60ca-48eb-9e45-e6a274f03204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545594865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2545594865
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.750693752
Short name T971
Test name
Test status
Simulation time 19083093 ps
CPU time 0.99 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 207200 kb
Host smart-794ac890-0d64-48eb-971e-f55b007c9844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750693752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.750693752
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2935915109
Short name T26
Test name
Test status
Simulation time 18858230 ps
CPU time 0.84 seconds
Started Jul 10 07:22:17 PM PDT 24
Finished Jul 10 07:22:21 PM PDT 24
Peak memory 216560 kb
Host smart-4384f2da-488e-43df-8073-b269724710cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935915109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2935915109
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1605532513
Short name T148
Test name
Test status
Simulation time 24917564 ps
CPU time 1.05 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 217108 kb
Host smart-3782608a-bc31-465a-b488-8f160a56bf9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605532513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1605532513
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3074717234
Short name T821
Test name
Test status
Simulation time 24723824 ps
CPU time 1.26 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 220012 kb
Host smart-7b3e8212-0878-40de-aad1-d463d68e0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074717234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3074717234
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1374020516
Short name T732
Test name
Test status
Simulation time 30583578 ps
CPU time 1.41 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 217840 kb
Host smart-dbca597d-eb83-405f-8c43-f8f8a0bcb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374020516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1374020516
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3126259796
Short name T360
Test name
Test status
Simulation time 38857245 ps
CPU time 0.92 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 215756 kb
Host smart-ddd34f9b-5dc7-4a60-a7da-7029c9ebcc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126259796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3126259796
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2846313074
Short name T690
Test name
Test status
Simulation time 38402559 ps
CPU time 0.93 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:09 PM PDT 24
Peak memory 215624 kb
Host smart-9d800692-0a43-4870-93f5-d78ae182897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846313074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2846313074
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3999634619
Short name T396
Test name
Test status
Simulation time 304837037 ps
CPU time 3.75 seconds
Started Jul 10 07:22:17 PM PDT 24
Finished Jul 10 07:22:24 PM PDT 24
Peak memory 218760 kb
Host smart-074453bc-9a8a-453b-9dbf-d5c49b8a3c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999634619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3999634619
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3687478026
Short name T241
Test name
Test status
Simulation time 134737724032 ps
CPU time 868.29 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:36:43 PM PDT 24
Peak memory 224100 kb
Host smart-8c7186ca-5158-406a-937e-999b57c14ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687478026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3687478026
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2474765003
Short name T937
Test name
Test status
Simulation time 57830788 ps
CPU time 1.29 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 217560 kb
Host smart-44752448-58c1-4497-b963-08079db88630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474765003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2474765003
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.664593944
Short name T962
Test name
Test status
Simulation time 49186373 ps
CPU time 1.24 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 220112 kb
Host smart-f0dfe697-4337-486d-bf94-5f89249d8005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664593944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.664593944
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2587584323
Short name T934
Test name
Test status
Simulation time 76786378 ps
CPU time 1.11 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 217796 kb
Host smart-5a880bed-782e-4be1-b416-a28854385aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587584323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2587584323
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2677867878
Short name T928
Test name
Test status
Simulation time 27277811 ps
CPU time 1.16 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:04 PM PDT 24
Peak memory 218944 kb
Host smart-c074037d-5108-48f0-9ed5-5339176b0600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677867878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2677867878
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2254432081
Short name T479
Test name
Test status
Simulation time 402437685 ps
CPU time 3.82 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 220364 kb
Host smart-2b54389f-d26b-4f74-a35a-ba0d594ccf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254432081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2254432081
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1650193676
Short name T475
Test name
Test status
Simulation time 38506263 ps
CPU time 1.19 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 221020 kb
Host smart-d1eccfd8-0664-4d65-a6f0-8e8c36ea1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650193676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1650193676
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.4173131901
Short name T810
Test name
Test status
Simulation time 44910502 ps
CPU time 1.44 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 219060 kb
Host smart-cd2f5486-ee1d-4b3b-887a-8b8f326838f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173131901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4173131901
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2296045903
Short name T631
Test name
Test status
Simulation time 25622400 ps
CPU time 1.14 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 218780 kb
Host smart-f1c35c3f-834d-4ddb-82e2-9129b3da0e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296045903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2296045903
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.4074424306
Short name T97
Test name
Test status
Simulation time 105602510 ps
CPU time 1.09 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 217712 kb
Host smart-a14b0370-a944-433b-baf5-b7b6c39dac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074424306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4074424306
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2603793305
Short name T253
Test name
Test status
Simulation time 50204764 ps
CPU time 1.26 seconds
Started Jul 10 07:23:54 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 219540 kb
Host smart-ac7f0c8e-f852-4873-9f6f-8493da0f1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603793305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2603793305
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1742862199
Short name T474
Test name
Test status
Simulation time 87313391 ps
CPU time 1.1 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 218668 kb
Host smart-f2871225-35cf-47b6-ba10-576f4944afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742862199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1742862199
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3192085898
Short name T470
Test name
Test status
Simulation time 41305526 ps
CPU time 1.13 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 219040 kb
Host smart-2adb815b-c391-4256-9c6d-f57a47c76086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192085898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3192085898
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2536462471
Short name T318
Test name
Test status
Simulation time 50830719 ps
CPU time 1.29 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:56 PM PDT 24
Peak memory 220488 kb
Host smart-2fb65fca-5d9c-4406-9e55-8b0df3d5ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536462471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2536462471
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2894915647
Short name T101
Test name
Test status
Simulation time 24427066 ps
CPU time 1.16 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 218700 kb
Host smart-d907619c-1896-49de-81a0-5c3506ef98d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894915647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2894915647
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3727445253
Short name T469
Test name
Test status
Simulation time 298603894 ps
CPU time 3.57 seconds
Started Jul 10 07:23:47 PM PDT 24
Finished Jul 10 07:23:54 PM PDT 24
Peak memory 220492 kb
Host smart-8059f2f6-8fe6-4615-be67-450f8e98ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727445253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3727445253
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2037955812
Short name T628
Test name
Test status
Simulation time 26044092 ps
CPU time 1.26 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:57 PM PDT 24
Peak memory 220052 kb
Host smart-e2b2989d-34ef-45e5-bf68-c69b9e738127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037955812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2037955812
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.358795282
Short name T335
Test name
Test status
Simulation time 133890376 ps
CPU time 2.37 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:54 PM PDT 24
Peak memory 220296 kb
Host smart-a3534de4-f420-4f6f-92c1-2e213abb36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358795282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.358795282
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1823001928
Short name T525
Test name
Test status
Simulation time 23004048 ps
CPU time 1.16 seconds
Started Jul 10 07:23:47 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 219092 kb
Host smart-535f9df2-d81f-4902-9e3b-411cd88af9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823001928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1823001928
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1961911534
Short name T54
Test name
Test status
Simulation time 91464589 ps
CPU time 1.28 seconds
Started Jul 10 07:23:50 PM PDT 24
Finished Jul 10 07:23:54 PM PDT 24
Peak memory 217752 kb
Host smart-5f31b197-476d-4e8c-a59c-a0e5d9a80798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961911534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1961911534
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2617650711
Short name T948
Test name
Test status
Simulation time 181709187 ps
CPU time 0.94 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 207092 kb
Host smart-1b77d616-d427-43e1-8388-cb434457a2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617650711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2617650711
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.198801804
Short name T401
Test name
Test status
Simulation time 19844682 ps
CPU time 0.87 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:22:16 PM PDT 24
Peak memory 216300 kb
Host smart-fcce39da-e160-4ee9-aa3f-0105f7e18ecc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198801804 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.198801804
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1302919049
Short name T850
Test name
Test status
Simulation time 65956307 ps
CPU time 1.29 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 217080 kb
Host smart-b2b6769a-2366-4061-a6db-62573f530ad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302919049 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1302919049
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.4174235078
Short name T672
Test name
Test status
Simulation time 47167089 ps
CPU time 1.52 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 218732 kb
Host smart-732b5503-96d6-477c-b10f-c0695efdd672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174235078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4174235078
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3413558006
Short name T43
Test name
Test status
Simulation time 22843211 ps
CPU time 1.11 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 215856 kb
Host smart-ae57a1f2-637a-4f09-b542-1165bb9cf9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413558006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3413558006
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2017819364
Short name T480
Test name
Test status
Simulation time 150888697 ps
CPU time 0.95 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 215400 kb
Host smart-69983b8c-f189-4b35-970c-48c57255d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017819364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2017819364
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2215557904
Short name T325
Test name
Test status
Simulation time 81893115 ps
CPU time 1.74 seconds
Started Jul 10 07:22:12 PM PDT 24
Finished Jul 10 07:22:19 PM PDT 24
Peak memory 215596 kb
Host smart-be6185e2-86de-417b-beaa-b4a34a914103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215557904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2215557904
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.241810940
Short name T499
Test name
Test status
Simulation time 79861901 ps
CPU time 1.07 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 218756 kb
Host smart-2cd3e502-e410-421f-bc91-2eaeb830cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241810940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.241810940
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2796989615
Short name T653
Test name
Test status
Simulation time 54794139 ps
CPU time 1.03 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:56 PM PDT 24
Peak memory 217704 kb
Host smart-e0c26c45-4b6a-4354-8049-95182775ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796989615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2796989615
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2463752205
Short name T618
Test name
Test status
Simulation time 53591883 ps
CPU time 1.25 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 221044 kb
Host smart-59c2bd57-81a8-4eab-8206-5062323b7e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463752205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2463752205
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2096693205
Short name T357
Test name
Test status
Simulation time 114880557 ps
CPU time 1.57 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 220548 kb
Host smart-74d41122-5f68-4d36-a19c-3c77678b0c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096693205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2096693205
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.744675851
Short name T972
Test name
Test status
Simulation time 72406240 ps
CPU time 1.23 seconds
Started Jul 10 07:23:54 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 218668 kb
Host smart-0723caab-e7c2-48ee-95d1-9713b0ed7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744675851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.744675851
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.4024912977
Short name T596
Test name
Test status
Simulation time 42101890 ps
CPU time 1.34 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 218992 kb
Host smart-4cc15a24-2985-40fc-a379-7c1ea0debef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024912977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4024912977
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2400164939
Short name T981
Test name
Test status
Simulation time 28822034 ps
CPU time 1.29 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 219472 kb
Host smart-a4bbb63f-3a97-41a3-a883-60f4ec8ec563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400164939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2400164939
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.638865008
Short name T339
Test name
Test status
Simulation time 83902467 ps
CPU time 1.13 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 217368 kb
Host smart-a1441c67-ad19-4637-8c48-b6ab61d0326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638865008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.638865008
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.4233592962
Short name T156
Test name
Test status
Simulation time 64435314 ps
CPU time 1.16 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:56 PM PDT 24
Peak memory 219076 kb
Host smart-eeb96088-3921-4155-9a52-b734e6afd336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233592962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.4233592962
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3605389522
Short name T503
Test name
Test status
Simulation time 41155764 ps
CPU time 1.76 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 218924 kb
Host smart-b69100e1-bc86-4412-ac08-8ca00f4bef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605389522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3605389522
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2678745764
Short name T486
Test name
Test status
Simulation time 26304962 ps
CPU time 1.23 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:58 PM PDT 24
Peak memory 220060 kb
Host smart-9fac0e98-4cde-4850-87a8-4332d9879144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678745764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2678745764
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3844503126
Short name T587
Test name
Test status
Simulation time 44093807 ps
CPU time 1.15 seconds
Started Jul 10 07:23:47 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 217992 kb
Host smart-b3bbd844-9e8b-479a-bf9f-11d397890754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844503126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3844503126
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.205415495
Short name T151
Test name
Test status
Simulation time 42311395 ps
CPU time 1.18 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:53 PM PDT 24
Peak memory 221192 kb
Host smart-45d6e0ec-3156-47e4-a19b-7704057264d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205415495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.205415495
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2290544637
Short name T90
Test name
Test status
Simulation time 75874835 ps
CPU time 1.06 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 217636 kb
Host smart-1e663b23-380d-4580-b475-401428edb288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290544637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2290544637
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1248630918
Short name T859
Test name
Test status
Simulation time 27831661 ps
CPU time 1.29 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 219696 kb
Host smart-24f3c0a3-f237-4a70-ab6f-631cc42b49d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248630918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1248630918
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3846184664
Short name T649
Test name
Test status
Simulation time 29742873 ps
CPU time 1.42 seconds
Started Jul 10 07:23:53 PM PDT 24
Finished Jul 10 07:23:56 PM PDT 24
Peak memory 219112 kb
Host smart-e86b9ba2-07d4-46a5-b8d5-7231cb7b7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846184664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3846184664
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3388322192
Short name T531
Test name
Test status
Simulation time 72826590 ps
CPU time 1.2 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:04 PM PDT 24
Peak memory 219012 kb
Host smart-75f83c4f-57d5-4784-95da-08db965efcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388322192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3388322192
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/189.edn_alert.2804831091
Short name T676
Test name
Test status
Simulation time 29882229 ps
CPU time 1.29 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 216032 kb
Host smart-45114ce5-02c8-472f-818d-a88dd343a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804831091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2804831091
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2711448831
Short name T372
Test name
Test status
Simulation time 35459850 ps
CPU time 1.17 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 219036 kb
Host smart-bc50dd22-7e59-4803-adbf-2a7f47fb6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711448831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2711448831
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1459226486
Short name T309
Test name
Test status
Simulation time 24389276 ps
CPU time 1.19 seconds
Started Jul 10 07:22:17 PM PDT 24
Finished Jul 10 07:22:22 PM PDT 24
Peak memory 219956 kb
Host smart-7b02e3bd-76b8-4c7e-bdb0-1f0ea2ae373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459226486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1459226486
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2202175802
Short name T753
Test name
Test status
Simulation time 51379329 ps
CPU time 0.84 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 207100 kb
Host smart-9c8babb5-a14c-4fad-be46-33c24a229f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202175802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2202175802
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1996862379
Short name T806
Test name
Test status
Simulation time 14464772 ps
CPU time 0.92 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:11 PM PDT 24
Peak memory 216444 kb
Host smart-4d76dcff-8725-44eb-9ebf-716036f16def
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996862379 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1996862379
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3244804278
Short name T137
Test name
Test status
Simulation time 151973290 ps
CPU time 1.25 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 217360 kb
Host smart-104e21f0-8708-481e-9905-e91f2209c17f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244804278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3244804278
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.3793936844
Short name T546
Test name
Test status
Simulation time 152295587 ps
CPU time 2.42 seconds
Started Jul 10 07:22:15 PM PDT 24
Finished Jul 10 07:22:21 PM PDT 24
Peak memory 220064 kb
Host smart-3c35c08a-6d56-428c-8daf-2b36e7beeedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793936844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3793936844
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3035964158
Short name T68
Test name
Test status
Simulation time 32374314 ps
CPU time 0.9 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:09 PM PDT 24
Peak memory 215756 kb
Host smart-7e6b3a7b-3ab9-43f6-b298-5042487c9617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035964158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3035964158
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2684419116
Short name T487
Test name
Test status
Simulation time 24692906 ps
CPU time 0.89 seconds
Started Jul 10 07:22:17 PM PDT 24
Finished Jul 10 07:22:22 PM PDT 24
Peak memory 215612 kb
Host smart-895bb8ea-8ce0-4454-81cd-860e4e1c4d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684419116 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2684419116
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3088590882
Short name T521
Test name
Test status
Simulation time 507120330 ps
CPU time 4.91 seconds
Started Jul 10 07:22:12 PM PDT 24
Finished Jul 10 07:22:22 PM PDT 24
Peak memory 215716 kb
Host smart-8ef896cf-526a-408d-95a1-6e6ef6f19561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088590882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3088590882
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.804772958
Short name T743
Test name
Test status
Simulation time 48749895538 ps
CPU time 1260.54 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:43:11 PM PDT 24
Peak memory 223092 kb
Host smart-5261cc09-5261-4460-a321-f690893e721b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804772958 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.804772958
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.300606595
Short name T861
Test name
Test status
Simulation time 199329643 ps
CPU time 1.17 seconds
Started Jul 10 07:23:48 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 220348 kb
Host smart-8011556f-2616-4170-ac27-7b9d14f45045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300606595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.300606595
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3834984030
Short name T451
Test name
Test status
Simulation time 56836846 ps
CPU time 1.26 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:24:00 PM PDT 24
Peak memory 217660 kb
Host smart-9edba902-e246-404d-aedd-b39592fc78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834984030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3834984030
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.584567042
Short name T828
Test name
Test status
Simulation time 25929081 ps
CPU time 1.2 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 220104 kb
Host smart-3fb0e145-afde-4d86-b8a3-deba1a35ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584567042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.584567042
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.813769696
Short name T329
Test name
Test status
Simulation time 99321340 ps
CPU time 2.22 seconds
Started Jul 10 07:23:49 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 217804 kb
Host smart-a2f07f68-741f-47d6-8576-d04bf1e86830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813769696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.813769696
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3276571479
Short name T484
Test name
Test status
Simulation time 26526232 ps
CPU time 1.18 seconds
Started Jul 10 07:23:51 PM PDT 24
Finished Jul 10 07:23:55 PM PDT 24
Peak memory 216056 kb
Host smart-0c24319e-0128-48cf-b527-b4d24e758456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276571479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3276571479
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2783075436
Short name T707
Test name
Test status
Simulation time 56283176 ps
CPU time 1.39 seconds
Started Jul 10 07:23:45 PM PDT 24
Finished Jul 10 07:23:51 PM PDT 24
Peak memory 219272 kb
Host smart-fb4e68a5-517b-4a36-bcc1-a0fde57b7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783075436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2783075436
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3616013644
Short name T795
Test name
Test status
Simulation time 105106104 ps
CPU time 1.28 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 216116 kb
Host smart-dcc48207-bae0-4614-b2c8-14e4bcb7dc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616013644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3616013644
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.534172291
Short name T290
Test name
Test status
Simulation time 57073357 ps
CPU time 1.98 seconds
Started Jul 10 07:23:46 PM PDT 24
Finished Jul 10 07:23:52 PM PDT 24
Peak memory 220424 kb
Host smart-fe437963-bd4f-4654-ab80-d413e9b49167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534172291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.534172291
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1555781393
Short name T67
Test name
Test status
Simulation time 88598549 ps
CPU time 1.12 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 221004 kb
Host smart-343fa24f-adbf-4545-93c2-48ece2688ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555781393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1555781393
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.2307260253
Short name T298
Test name
Test status
Simulation time 61316444 ps
CPU time 1.22 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 219148 kb
Host smart-9cee4a55-0d4b-481e-a24e-2584b9a77479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307260253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2307260253
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.788853563
Short name T955
Test name
Test status
Simulation time 34437191 ps
CPU time 0.98 seconds
Started Jul 10 07:23:55 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 217616 kb
Host smart-1b95c3ee-f354-4c85-9a14-5217dac94a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788853563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.788853563
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2226126428
Short name T671
Test name
Test status
Simulation time 53795727 ps
CPU time 1.82 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 218624 kb
Host smart-866d9c17-2156-45ea-a8a8-66e6d9bb26f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226126428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2226126428
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2143920692
Short name T901
Test name
Test status
Simulation time 80141229 ps
CPU time 1.18 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 219436 kb
Host smart-4e4e0b7a-23d9-44c0-a8f7-22c69369a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143920692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2143920692
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3688768268
Short name T751
Test name
Test status
Simulation time 126585411 ps
CPU time 1.36 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 220348 kb
Host smart-0f6e330b-7565-4b87-ac92-4828326d9e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688768268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3688768268
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.174619457
Short name T41
Test name
Test status
Simulation time 26868145 ps
CPU time 1.2 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 220148 kb
Host smart-75d363c5-7e87-4689-b02a-1e8c6d9cc924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174619457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.174619457
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3239361880
Short name T742
Test name
Test status
Simulation time 98869619 ps
CPU time 1.18 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:01 PM PDT 24
Peak memory 217808 kb
Host smart-b22a4077-9ab4-4105-bed3-0751c2bb74cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239361880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3239361880
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3722427524
Short name T104
Test name
Test status
Simulation time 28883836 ps
CPU time 1.28 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 219000 kb
Host smart-38cbf5cc-b7ee-4f28-a6c4-2669316c0add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722427524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3722427524
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2841791758
Short name T592
Test name
Test status
Simulation time 56039208 ps
CPU time 1.31 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 215632 kb
Host smart-a20d2680-261c-42cd-bc98-8854c480b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841791758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2841791758
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1726965234
Short name T113
Test name
Test status
Simulation time 30183172 ps
CPU time 1.28 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:21:44 PM PDT 24
Peak memory 219800 kb
Host smart-a0b5910e-9062-43b0-8fff-93f62ae71c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726965234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1726965234
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.482895724
Short name T866
Test name
Test status
Simulation time 14847304 ps
CPU time 0.91 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 207068 kb
Host smart-a349f67e-d8f4-470c-82c2-271b8311b620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482895724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.482895724
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2775573212
Short name T178
Test name
Test status
Simulation time 26121322 ps
CPU time 0.92 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 214932 kb
Host smart-150936b6-7048-49d6-9530-41109a20a547
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775573212 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2775573212
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.4113686620
Short name T80
Test name
Test status
Simulation time 64977107 ps
CPU time 1.19 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 217088 kb
Host smart-7517eb99-54a4-4cb6-a6b4-e1e7da8270a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113686620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.4113686620
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.751585140
Short name T555
Test name
Test status
Simulation time 28843719 ps
CPU time 0.85 seconds
Started Jul 10 07:21:43 PM PDT 24
Finished Jul 10 07:21:48 PM PDT 24
Peak memory 218556 kb
Host smart-cf8e29d8-c9f1-44aa-9729-a7ff5a6bccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751585140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.751585140
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1350583370
Short name T76
Test name
Test status
Simulation time 226157346 ps
CPU time 3.47 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 220384 kb
Host smart-32374f62-b991-4247-b1d3-310f8706d09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350583370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1350583370
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3765154465
Short name T123
Test name
Test status
Simulation time 19656176 ps
CPU time 1.12 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 216120 kb
Host smart-8b79330a-f144-45db-879c-8ab944a4d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765154465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3765154465
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.457132084
Short name T70
Test name
Test status
Simulation time 1680330410 ps
CPU time 7.45 seconds
Started Jul 10 07:21:41 PM PDT 24
Finished Jul 10 07:21:53 PM PDT 24
Peak memory 236924 kb
Host smart-e626a3b6-6875-4fd3-bc8a-8fc8f6fe9994
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457132084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.457132084
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3637569266
Short name T645
Test name
Test status
Simulation time 17858138 ps
CPU time 1 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:45 PM PDT 24
Peak memory 215652 kb
Host smart-31605b91-1237-468a-ac70-7f37664023d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637569266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3637569266
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3032770468
Short name T109
Test name
Test status
Simulation time 2927632005 ps
CPU time 6.36 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 215760 kb
Host smart-02a901ff-8a84-4555-b1ba-a3305ef6b008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032770468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3032770468
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4100730304
Short name T754
Test name
Test status
Simulation time 147299907191 ps
CPU time 853.91 seconds
Started Jul 10 07:21:39 PM PDT 24
Finished Jul 10 07:35:56 PM PDT 24
Peak memory 224116 kb
Host smart-da2d8275-008c-43ad-8f4c-61ec2a0a4ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100730304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4100730304
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3132814853
Short name T160
Test name
Test status
Simulation time 116253822 ps
CPU time 1.21 seconds
Started Jul 10 07:22:06 PM PDT 24
Finished Jul 10 07:22:12 PM PDT 24
Peak memory 219424 kb
Host smart-9ce36698-0936-486f-aa2d-84a0d80f0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132814853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3132814853
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.968881757
Short name T682
Test name
Test status
Simulation time 29829241 ps
CPU time 0.94 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 215468 kb
Host smart-bce97248-27aa-41d1-a3c2-8684fb8a28c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968881757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.968881757
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1913348448
Short name T218
Test name
Test status
Simulation time 32181088 ps
CPU time 1.25 seconds
Started Jul 10 07:22:18 PM PDT 24
Finished Jul 10 07:22:23 PM PDT 24
Peak memory 218400 kb
Host smart-e798fe6b-5549-42f8-9b15-49ea940926ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913348448 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1913348448
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.264803641
Short name T157
Test name
Test status
Simulation time 36750971 ps
CPU time 1.21 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 229956 kb
Host smart-fd32ddb1-6b2e-4bcc-ab14-96884d4fdb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264803641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.264803641
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1729868267
Short name T458
Test name
Test status
Simulation time 42501065 ps
CPU time 1.17 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 217864 kb
Host smart-62b926f1-8480-4580-8713-9ce1169cea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729868267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1729868267
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.363375118
Short name T995
Test name
Test status
Simulation time 22156532 ps
CPU time 1.13 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:22:16 PM PDT 24
Peak memory 224344 kb
Host smart-436adc6e-18dd-4a23-9d96-05d472ec1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363375118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.363375118
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3691227061
Short name T527
Test name
Test status
Simulation time 46103206 ps
CPU time 0.92 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 215640 kb
Host smart-07dd49e3-8db7-4d7c-9a79-3f5afa85e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691227061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3691227061
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2871737921
Short name T695
Test name
Test status
Simulation time 833051178 ps
CPU time 5.1 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:22:20 PM PDT 24
Peak memory 217568 kb
Host smart-64b37003-e3ca-431d-859d-92f1cd33db7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871737921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2871737921
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1144425446
Short name T693
Test name
Test status
Simulation time 35170868208 ps
CPU time 920.75 seconds
Started Jul 10 07:22:13 PM PDT 24
Finished Jul 10 07:37:38 PM PDT 24
Peak memory 220248 kb
Host smart-8d15f2ae-d142-477b-83f4-0315aff876cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144425446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1144425446
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2743545461
Short name T762
Test name
Test status
Simulation time 67509055 ps
CPU time 1.61 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 218848 kb
Host smart-6371abc1-49f4-42b4-b33f-00f6757305b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743545461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2743545461
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.144041119
Short name T12
Test name
Test status
Simulation time 85498752 ps
CPU time 1.41 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 220620 kb
Host smart-a34161eb-9d95-47f9-a6ac-8c9e63c84a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144041119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.144041119
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3837031803
Short name T721
Test name
Test status
Simulation time 46141125 ps
CPU time 1.63 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 218916 kb
Host smart-b6c85999-a307-48c9-8176-d3c3f45701a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837031803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3837031803
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1156295486
Short name T376
Test name
Test status
Simulation time 35159283 ps
CPU time 1.4 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 218876 kb
Host smart-ea207ba3-76c9-48c6-b398-e542de1144b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156295486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1156295486
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1622519268
Short name T833
Test name
Test status
Simulation time 70526379 ps
CPU time 1.38 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 219408 kb
Host smart-92c99f85-1b0d-472f-bf9c-3a06d929d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622519268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1622519268
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1243007002
Short name T523
Test name
Test status
Simulation time 34445837 ps
CPU time 1.11 seconds
Started Jul 10 07:24:03 PM PDT 24
Finished Jul 10 07:24:09 PM PDT 24
Peak memory 219688 kb
Host smart-41d69eab-732f-42b4-a0cd-fdcaa65aef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243007002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1243007002
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2615111842
Short name T544
Test name
Test status
Simulation time 57572536 ps
CPU time 1.23 seconds
Started Jul 10 07:24:02 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 215728 kb
Host smart-b99e3505-ba55-401e-b80b-03561be2ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615111842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2615111842
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3525150167
Short name T316
Test name
Test status
Simulation time 98374571 ps
CPU time 1.65 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 218952 kb
Host smart-8461c321-3c6d-4f4e-bb90-14d75d25d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525150167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3525150167
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3781512256
Short name T669
Test name
Test status
Simulation time 111673600 ps
CPU time 1.42 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 217812 kb
Host smart-d213bbae-6e46-4bee-b727-af8bc12804e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781512256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3781512256
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1022694440
Short name T541
Test name
Test status
Simulation time 43713574 ps
CPU time 1.47 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 217696 kb
Host smart-d0ca3d63-c5d0-435f-ad84-645643ca85aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022694440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1022694440
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4262779193
Short name T10
Test name
Test status
Simulation time 92638677 ps
CPU time 1.18 seconds
Started Jul 10 07:22:15 PM PDT 24
Finished Jul 10 07:22:20 PM PDT 24
Peak memory 220768 kb
Host smart-2653fd99-85e7-4c16-97b5-db4262b5a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262779193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4262779193
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.220377895
Short name T114
Test name
Test status
Simulation time 56313005 ps
CPU time 0.9 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:25 PM PDT 24
Peak memory 215452 kb
Host smart-f968614a-201c-4e1f-ad45-b38626dad516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220377895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.220377895
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3902521635
Short name T906
Test name
Test status
Simulation time 13328565 ps
CPU time 0.93 seconds
Started Jul 10 07:22:11 PM PDT 24
Finished Jul 10 07:22:17 PM PDT 24
Peak memory 216840 kb
Host smart-57fe8b82-864f-43bb-b97e-4d7baad376c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902521635 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3902521635
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2817160133
Short name T681
Test name
Test status
Simulation time 56605440 ps
CPU time 0.99 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 216528 kb
Host smart-118a1948-f6de-490d-99d9-074a7040ebe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817160133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2817160133
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.3179023546
Short name T518
Test name
Test status
Simulation time 82606675 ps
CPU time 1.04 seconds
Started Jul 10 07:22:15 PM PDT 24
Finished Jul 10 07:22:20 PM PDT 24
Peak memory 215708 kb
Host smart-dfee0bcf-8fb4-4f9a-b41d-a8f055a8f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179023546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3179023546
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3400972144
Short name T760
Test name
Test status
Simulation time 42707742 ps
CPU time 0.86 seconds
Started Jul 10 07:22:16 PM PDT 24
Finished Jul 10 07:22:20 PM PDT 24
Peak memory 215676 kb
Host smart-873dc6e2-ffb8-473c-afc1-8e037dedbc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400972144 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3400972144
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1696327296
Short name T745
Test name
Test status
Simulation time 29800248 ps
CPU time 0.95 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 207436 kb
Host smart-21d6dadc-8548-416c-8d5c-b02847af91d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696327296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1696327296
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3390335262
Short name T892
Test name
Test status
Simulation time 414285034 ps
CPU time 8.35 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:21 PM PDT 24
Peak memory 217572 kb
Host smart-e37523fd-ea09-4f2d-ab59-6d22aba864e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390335262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3390335262
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.593423784
Short name T569
Test name
Test status
Simulation time 14529320311 ps
CPU time 305.63 seconds
Started Jul 10 07:22:18 PM PDT 24
Finished Jul 10 07:27:28 PM PDT 24
Peak memory 223420 kb
Host smart-fb39f78b-68b6-4868-9b6c-1bd09f06d78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593423784 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.593423784
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.4254897952
Short name T422
Test name
Test status
Simulation time 49173125 ps
CPU time 1.52 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:01 PM PDT 24
Peak memory 218632 kb
Host smart-694fe2f8-5c35-400d-8c8c-c7939b19e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254897952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4254897952
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.454902795
Short name T349
Test name
Test status
Simulation time 56978252 ps
CPU time 1.01 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:01 PM PDT 24
Peak memory 217636 kb
Host smart-ab6a2e0a-4b28-4bf9-8dad-3a7a5a6246d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454902795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.454902795
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1231911689
Short name T100
Test name
Test status
Simulation time 68588622 ps
CPU time 1.83 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 220568 kb
Host smart-c7363c67-82dd-4b3a-8914-12e1727a29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231911689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1231911689
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1220864690
Short name T439
Test name
Test status
Simulation time 82816992 ps
CPU time 1.23 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 220440 kb
Host smart-2b629156-6773-44de-bca4-6253f237ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220864690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1220864690
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1491571996
Short name T624
Test name
Test status
Simulation time 40960941 ps
CPU time 1.79 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 220348 kb
Host smart-4dbaa7ff-ee2a-42fb-a056-aa5a75f5f711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491571996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1491571996
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1312306298
Short name T319
Test name
Test status
Simulation time 260040451 ps
CPU time 1.32 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 219008 kb
Host smart-4379851d-3fbb-49a9-99fc-049b7c55a351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312306298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1312306298
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3296862149
Short name T391
Test name
Test status
Simulation time 59155229 ps
CPU time 1.15 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 220276 kb
Host smart-52661cc1-9785-4f95-b186-8509f8d71d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296862149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3296862149
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1629322380
Short name T432
Test name
Test status
Simulation time 47477829 ps
CPU time 1.14 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:24:00 PM PDT 24
Peak memory 217748 kb
Host smart-042b4cc0-bbd7-4b90-b29b-3a6d4f20819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629322380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1629322380
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.595867507
Short name T251
Test name
Test status
Simulation time 94688862 ps
CPU time 1.23 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:24:01 PM PDT 24
Peak memory 219500 kb
Host smart-31c516fc-e451-44e3-ad0d-43be9164f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595867507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.595867507
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3190432416
Short name T283
Test name
Test status
Simulation time 30677036 ps
CPU time 1.3 seconds
Started Jul 10 07:22:07 PM PDT 24
Finished Jul 10 07:22:13 PM PDT 24
Peak memory 219804 kb
Host smart-fb22ea45-1acb-4fe5-bf52-f41e84538a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190432416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3190432416
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.598803379
Short name T663
Test name
Test status
Simulation time 28500801 ps
CPU time 0.86 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 207048 kb
Host smart-fcf40f79-2598-4f6b-8d3c-b4d4b9195fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598803379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.598803379
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.116065035
Short name T248
Test name
Test status
Simulation time 37599881 ps
CPU time 0.87 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 216392 kb
Host smart-d833bd84-8df6-4a45-9723-041e16924bb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116065035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.116065035
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1768610546
Short name T839
Test name
Test status
Simulation time 42053008 ps
CPU time 1.21 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 217216 kb
Host smart-d9ae830d-e956-4dff-9bbf-27b7184abb25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768610546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1768610546
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3537989791
Short name T117
Test name
Test status
Simulation time 40770828 ps
CPU time 1.05 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 230028 kb
Host smart-df011724-df0e-4e73-83df-6bafd85e5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537989791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3537989791
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2602507324
Short name T471
Test name
Test status
Simulation time 47383115 ps
CPU time 1.37 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 217704 kb
Host smart-3afe3415-0901-4d2e-b322-9a0a8d599780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602507324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2602507324
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.284725396
Short name T370
Test name
Test status
Simulation time 56559194 ps
CPU time 0.9 seconds
Started Jul 10 07:22:13 PM PDT 24
Finished Jul 10 07:22:18 PM PDT 24
Peak memory 215632 kb
Host smart-8375efcd-592d-4733-89f8-7b87254e8004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284725396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.284725396
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1119174557
Short name T379
Test name
Test status
Simulation time 92684352 ps
CPU time 2.16 seconds
Started Jul 10 07:22:13 PM PDT 24
Finished Jul 10 07:22:19 PM PDT 24
Peak memory 217524 kb
Host smart-d10256bb-4bde-4c72-853a-8c5baf0b5e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119174557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1119174557
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3823971093
Short name T459
Test name
Test status
Simulation time 112416023413 ps
CPU time 1193.65 seconds
Started Jul 10 07:22:09 PM PDT 24
Finished Jul 10 07:42:08 PM PDT 24
Peak memory 224340 kb
Host smart-f05a7468-4bfe-4db4-bb26-a8abc4613f65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823971093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3823971093
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.621215502
Short name T476
Test name
Test status
Simulation time 46345694 ps
CPU time 1.52 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 218956 kb
Host smart-25076fd0-b734-4790-b7e2-f34a0b5027e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621215502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.621215502
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.477361452
Short name T444
Test name
Test status
Simulation time 32711697 ps
CPU time 1.31 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 218680 kb
Host smart-8b1d9117-a928-49bf-a649-eb195504577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477361452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.477361452
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2982388454
Short name T769
Test name
Test status
Simulation time 60494753 ps
CPU time 1.56 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 219220 kb
Host smart-8678e5da-20ad-4f5c-a3d5-e2b02953b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982388454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2982388454
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1740719023
Short name T904
Test name
Test status
Simulation time 95101105 ps
CPU time 1.44 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 219132 kb
Host smart-28749a0b-d741-4fd6-bfde-a14adac81d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740719023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1740719023
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.809030281
Short name T841
Test name
Test status
Simulation time 54808068 ps
CPU time 1.28 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 219016 kb
Host smart-875eb09c-7aa5-49e8-bb46-47ece344a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809030281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.809030281
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1836998629
Short name T857
Test name
Test status
Simulation time 54097261 ps
CPU time 1.47 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 218872 kb
Host smart-a3967f30-e194-4c88-9b77-718f11fdc372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836998629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1836998629
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2740946320
Short name T324
Test name
Test status
Simulation time 71285228 ps
CPU time 1.32 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 220156 kb
Host smart-ab3c0d5c-e5f5-4f79-9f4e-3f787fe0292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740946320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2740946320
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2377633320
Short name T588
Test name
Test status
Simulation time 80182716 ps
CPU time 1.21 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 217656 kb
Host smart-776a6861-9d3e-4ea2-a775-b36a8217edb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377633320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2377633320
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3683492066
Short name T352
Test name
Test status
Simulation time 34078435 ps
CPU time 1.32 seconds
Started Jul 10 07:24:07 PM PDT 24
Finished Jul 10 07:24:12 PM PDT 24
Peak memory 218636 kb
Host smart-6fbb37c0-d463-4e62-b276-cb6c23cc1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683492066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3683492066
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4123161861
Short name T703
Test name
Test status
Simulation time 170051487 ps
CPU time 1.2 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 218712 kb
Host smart-363bcbb0-d53b-4d30-a3b0-350b4177c275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123161861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4123161861
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1324791699
Short name T982
Test name
Test status
Simulation time 16750247 ps
CPU time 0.94 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 215196 kb
Host smart-b7368c96-389c-40c9-984d-4a74cc85ae77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324791699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1324791699
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3039041761
Short name T236
Test name
Test status
Simulation time 23578988 ps
CPU time 0.78 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:24 PM PDT 24
Peak memory 215704 kb
Host smart-fb56065e-ecfc-4454-9c33-9e959d1f9388
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039041761 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3039041761
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3458549315
Short name T138
Test name
Test status
Simulation time 75252143 ps
CPU time 1.33 seconds
Started Jul 10 07:22:18 PM PDT 24
Finished Jul 10 07:22:23 PM PDT 24
Peak memory 217260 kb
Host smart-5c658bef-9900-450d-93ea-fe9b4b66feb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458549315 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3458549315
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1682988583
Short name T404
Test name
Test status
Simulation time 90971166 ps
CPU time 0.96 seconds
Started Jul 10 07:22:25 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 220308 kb
Host smart-57a9bfd0-ccc0-4466-be28-b7385a66290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682988583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1682988583
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1502049681
Short name T842
Test name
Test status
Simulation time 44716181 ps
CPU time 1.63 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:25 PM PDT 24
Peak memory 215616 kb
Host smart-6967b47e-3af9-41a3-a11c-d01e9c3221ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502049681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1502049681
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.3826311421
Short name T617
Test name
Test status
Simulation time 18735843 ps
CPU time 1.03 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 215640 kb
Host smart-a2289801-6677-4bcf-813a-1424d84f3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826311421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3826311421
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3555967569
Short name T380
Test name
Test status
Simulation time 117970043 ps
CPU time 1.1 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 207456 kb
Host smart-102ebd59-5c51-4339-a940-56fa981d848d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555967569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3555967569
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4184423820
Short name T929
Test name
Test status
Simulation time 88209301734 ps
CPU time 2019.32 seconds
Started Jul 10 07:22:22 PM PDT 24
Finished Jul 10 07:56:07 PM PDT 24
Peak memory 226780 kb
Host smart-e86c3ab5-d414-4883-9b2c-b2596de3e6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184423820 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4184423820
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.393614307
Short name T566
Test name
Test status
Simulation time 49055700 ps
CPU time 1.44 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 220176 kb
Host smart-acf124e6-bfee-4a38-891a-2bc8b77c52e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393614307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.393614307
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3384833677
Short name T576
Test name
Test status
Simulation time 36649251 ps
CPU time 1.11 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:04 PM PDT 24
Peak memory 217732 kb
Host smart-b3b66c5b-e3cf-446b-ae4b-ee27933efca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384833677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3384833677
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1588433374
Short name T488
Test name
Test status
Simulation time 97348904 ps
CPU time 1.61 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:05 PM PDT 24
Peak memory 220320 kb
Host smart-929eff58-00bc-454b-ba1b-2de8a7e96cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588433374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1588433374
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3738709013
Short name T560
Test name
Test status
Simulation time 90986945 ps
CPU time 1.24 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 217648 kb
Host smart-7f0c1b3a-cfce-4e58-a260-107868b1b06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738709013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3738709013
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3746939889
Short name T322
Test name
Test status
Simulation time 95366316 ps
CPU time 1.27 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 219968 kb
Host smart-8fc9a15c-d0a5-4943-8d07-a5fed803b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746939889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3746939889
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.334636535
Short name T765
Test name
Test status
Simulation time 41474407 ps
CPU time 1.4 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 218968 kb
Host smart-003ce0aa-dc40-463b-b3b0-168ce186e5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334636535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.334636535
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.318902645
Short name T692
Test name
Test status
Simulation time 83567146 ps
CPU time 1.19 seconds
Started Jul 10 07:24:09 PM PDT 24
Finished Jul 10 07:24:14 PM PDT 24
Peak memory 217680 kb
Host smart-676504ab-09d1-4223-9dc5-76834fa811ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318902645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.318902645
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2190632829
Short name T466
Test name
Test status
Simulation time 61972654 ps
CPU time 1.38 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 220704 kb
Host smart-d0b88755-d83c-4c34-8955-80abb5c79e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190632829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2190632829
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1229848400
Short name T423
Test name
Test status
Simulation time 38591219 ps
CPU time 1.01 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 217764 kb
Host smart-f4a4b0bc-ec2c-4203-ac97-ac53fa49c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229848400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1229848400
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.367478668
Short name T353
Test name
Test status
Simulation time 19558642 ps
CPU time 1.17 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 215688 kb
Host smart-c6fb5331-99e7-49d6-a321-173751a2e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367478668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.367478668
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2216801494
Short name T779
Test name
Test status
Simulation time 47483693 ps
CPU time 1.17 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:29 PM PDT 24
Peak memory 218940 kb
Host smart-1add7b9b-de2f-4181-88aa-fc37bbcd0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216801494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2216801494
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3293077833
Short name T646
Test name
Test status
Simulation time 16711551 ps
CPU time 1.05 seconds
Started Jul 10 07:22:22 PM PDT 24
Finished Jul 10 07:22:29 PM PDT 24
Peak memory 215308 kb
Host smart-dee3b903-001b-43fb-810c-6c133160e88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293077833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3293077833
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3777842093
Short name T691
Test name
Test status
Simulation time 11620060 ps
CPU time 0.89 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 216580 kb
Host smart-a5648e04-df0c-48b9-b501-ed6c3c5b4e9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777842093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3777842093
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2337728808
Short name T483
Test name
Test status
Simulation time 97161996 ps
CPU time 1.06 seconds
Started Jul 10 07:22:25 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 219048 kb
Host smart-2648ea5a-2d44-4fd9-9509-e1a36949e73b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337728808 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2337728808
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2584952844
Short name T216
Test name
Test status
Simulation time 44954706 ps
CPU time 0.79 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 219496 kb
Host smart-f4d34579-09d2-4bc1-b36b-5673fce220c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584952844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2584952844
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.4120940220
Short name T638
Test name
Test status
Simulation time 19663249 ps
CPU time 1.07 seconds
Started Jul 10 07:22:25 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 216212 kb
Host smart-ccadc0b6-520e-4d09-ac4f-a8e014249029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120940220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4120940220
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2799672216
Short name T907
Test name
Test status
Simulation time 61683734 ps
CPU time 0.93 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:24 PM PDT 24
Peak memory 215636 kb
Host smart-6feb2c61-53d7-4a08-9858-c4b81ad0a39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799672216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2799672216
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1942269886
Short name T389
Test name
Test status
Simulation time 1570721133 ps
CPU time 3.06 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 215184 kb
Host smart-74c7d2b5-a444-4fea-834e-e88754385a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942269886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1942269886
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2047306465
Short name T752
Test name
Test status
Simulation time 99317559931 ps
CPU time 2532.99 seconds
Started Jul 10 07:22:26 PM PDT 24
Finished Jul 10 08:04:45 PM PDT 24
Peak memory 232848 kb
Host smart-0b6dbc6e-bede-4e63-b53b-89ee98625cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047306465 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2047306465
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4265105970
Short name T988
Test name
Test status
Simulation time 56418427 ps
CPU time 1.36 seconds
Started Jul 10 07:24:05 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 218720 kb
Host smart-df3cdd4f-a30c-41a5-beaa-0bf35e676db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265105970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4265105970
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3193434318
Short name T738
Test name
Test status
Simulation time 37633979 ps
CPU time 1.3 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:04 PM PDT 24
Peak memory 217600 kb
Host smart-4c67c300-6b65-4ce7-ad62-5e422f7e2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193434318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3193434318
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3835300562
Short name T11
Test name
Test status
Simulation time 78686345 ps
CPU time 1.58 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 215600 kb
Host smart-548326c9-9a52-4979-a4c2-55cfcef41b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835300562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3835300562
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.900555982
Short name T506
Test name
Test status
Simulation time 56448121 ps
CPU time 1.02 seconds
Started Jul 10 07:24:02 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 217680 kb
Host smart-f85c9a52-1910-4fd8-8eb7-c9b3aa79890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900555982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.900555982
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.527893462
Short name T614
Test name
Test status
Simulation time 57821103 ps
CPU time 1.34 seconds
Started Jul 10 07:23:58 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 217776 kb
Host smart-e05f2848-c7ce-4f25-bb4c-d5767bfb86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527893462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.527893462
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1996803019
Short name T733
Test name
Test status
Simulation time 44762011 ps
CPU time 1.5 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 215636 kb
Host smart-8d11d910-41bf-4393-812b-65c92ffcb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996803019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1996803019
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.339237070
Short name T343
Test name
Test status
Simulation time 177298606 ps
CPU time 1.25 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 220260 kb
Host smart-e75aacb6-856d-4bf5-9a0f-9b2f84ba8cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339237070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.339237070
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2727258827
Short name T426
Test name
Test status
Simulation time 55970572 ps
CPU time 1.17 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 220492 kb
Host smart-00792435-8645-45b1-ac55-d04bc7a65cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727258827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2727258827
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2957442920
Short name T345
Test name
Test status
Simulation time 67743560 ps
CPU time 1.12 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 217668 kb
Host smart-4b574632-bb9d-450c-929c-02cbe71cd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957442920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2957442920
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2797544984
Short name T611
Test name
Test status
Simulation time 126640241 ps
CPU time 1.23 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 219360 kb
Host smart-c9fd89a7-eb6c-4501-aaf6-47151abd6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797544984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2797544984
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1648320523
Short name T728
Test name
Test status
Simulation time 21931003 ps
CPU time 1.04 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 207156 kb
Host smart-e89ad962-a092-431e-9b7a-bf31ae76a309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648320523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1648320523
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1585298017
Short name T183
Test name
Test status
Simulation time 10856438 ps
CPU time 0.93 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 216604 kb
Host smart-f88f3b2d-9d56-4321-9805-8f55385e9f7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585298017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1585298017
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1543095539
Short name T166
Test name
Test status
Simulation time 41867247 ps
CPU time 1.44 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 217308 kb
Host smart-8846aed0-7109-492c-8e79-2c62b924d1bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543095539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1543095539
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1289584979
Short name T170
Test name
Test status
Simulation time 32129226 ps
CPU time 0.86 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 218520 kb
Host smart-0d002adb-7ced-45d7-9f1a-143ccfe9fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289584979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1289584979
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1150910756
Short name T289
Test name
Test status
Simulation time 45558916 ps
CPU time 1.18 seconds
Started Jul 10 07:22:19 PM PDT 24
Finished Jul 10 07:22:26 PM PDT 24
Peak memory 218716 kb
Host smart-47f43467-6db5-40eb-9f33-b112f04845d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150910756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1150910756
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3648393056
Short name T452
Test name
Test status
Simulation time 31488414 ps
CPU time 0.93 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 215800 kb
Host smart-ed0caffc-4f8c-4895-878d-64d077179cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648393056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3648393056
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2359559078
Short name T775
Test name
Test status
Simulation time 47332172 ps
CPU time 0.92 seconds
Started Jul 10 07:22:26 PM PDT 24
Finished Jul 10 07:22:32 PM PDT 24
Peak memory 215792 kb
Host smart-b8a8c1d6-1d96-4fcd-a15c-d74f66a0be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359559078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2359559078
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3468106845
Short name T642
Test name
Test status
Simulation time 241219428 ps
CPU time 4.82 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 217728 kb
Host smart-2cfc6675-df09-453c-b064-3f839d266197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468106845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3468106845
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.314023333
Short name T243
Test name
Test status
Simulation time 46722063533 ps
CPU time 1049.47 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:39:55 PM PDT 24
Peak memory 220388 kb
Host smart-d280d818-3622-441c-847f-a0cde62ac111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314023333 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.314023333
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1607832209
Short name T509
Test name
Test status
Simulation time 121062939 ps
CPU time 1.13 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 217808 kb
Host smart-9be68ea0-0c8e-4bca-9ace-bf8319ddcc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607832209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1607832209
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1288681006
Short name T668
Test name
Test status
Simulation time 37179021 ps
CPU time 1.16 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 217740 kb
Host smart-f06220a5-c421-4eab-ad8e-76e086e591c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288681006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1288681006
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.347361446
Short name T326
Test name
Test status
Simulation time 54893222 ps
CPU time 1.09 seconds
Started Jul 10 07:23:59 PM PDT 24
Finished Jul 10 07:24:03 PM PDT 24
Peak memory 219408 kb
Host smart-a40de98e-14f2-465d-88d1-53060b7ea5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347361446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.347361446
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3494465797
Short name T975
Test name
Test status
Simulation time 72488258 ps
CPU time 2.09 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:02 PM PDT 24
Peak memory 220296 kb
Host smart-1dbbc117-e29a-4ed8-ad78-10cc6ac8bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494465797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3494465797
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.916108435
Short name T72
Test name
Test status
Simulation time 68379989 ps
CPU time 1.06 seconds
Started Jul 10 07:23:57 PM PDT 24
Finished Jul 10 07:24:01 PM PDT 24
Peak memory 217748 kb
Host smart-4db5933d-c3cc-42df-b4b3-2deeb20679e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916108435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.916108435
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1594009074
Short name T884
Test name
Test status
Simulation time 33641123 ps
CPU time 1.03 seconds
Started Jul 10 07:23:56 PM PDT 24
Finished Jul 10 07:23:59 PM PDT 24
Peak memory 217536 kb
Host smart-12afbd0c-b751-4a2c-9ba8-0ac8c1bac575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594009074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1594009074
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2058553804
Short name T540
Test name
Test status
Simulation time 106299786 ps
CPU time 1.71 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 219208 kb
Host smart-1e20f093-fef0-483a-aea5-dc02b53d39e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058553804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2058553804
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2272865191
Short name T952
Test name
Test status
Simulation time 30018453 ps
CPU time 1.27 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:07 PM PDT 24
Peak memory 217716 kb
Host smart-6ab34ca6-9471-442e-99f0-610b5791810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272865191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2272865191
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1503556227
Short name T704
Test name
Test status
Simulation time 184459541 ps
CPU time 1.53 seconds
Started Jul 10 07:24:01 PM PDT 24
Finished Jul 10 07:24:08 PM PDT 24
Peak memory 219108 kb
Host smart-61ce62bb-fcb9-4dc6-bc17-6dd81e3080c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503556227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1503556227
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3171309466
Short name T601
Test name
Test status
Simulation time 109998986 ps
CPU time 1.45 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 218968 kb
Host smart-ab746caa-3b6f-45a4-a50d-79b7e0e42a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171309466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3171309466
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2267720136
Short name T233
Test name
Test status
Simulation time 249129864 ps
CPU time 1.32 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 218980 kb
Host smart-862c13aa-1fa6-4087-96b2-5bd4d54b70a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267720136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2267720136
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1978724501
Short name T561
Test name
Test status
Simulation time 16178430 ps
CPU time 0.95 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 207024 kb
Host smart-371f39e6-1bda-407c-8d26-e44a4e8a2c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978724501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1978724501
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1326500241
Short name T106
Test name
Test status
Simulation time 24033710 ps
CPU time 0.86 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 216576 kb
Host smart-b1c80eda-d8d2-4cd1-8187-7c2d51a9fb9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326500241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1326500241
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.2366082468
Short name T153
Test name
Test status
Simulation time 23011022 ps
CPU time 1.24 seconds
Started Jul 10 07:22:24 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 224324 kb
Host smart-a5016162-3474-4266-9b48-6014ac323c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366082468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2366082468
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.161469556
Short name T383
Test name
Test status
Simulation time 31550068 ps
CPU time 1.29 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 217664 kb
Host smart-aa2354b7-209c-4bc5-af2a-290842e127e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161469556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.161469556
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.393340549
Short name T430
Test name
Test status
Simulation time 21139861 ps
CPU time 1.12 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 215760 kb
Host smart-300ca57c-8a83-471e-b4af-bc57c4f01b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393340549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.393340549
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1311788983
Short name T895
Test name
Test status
Simulation time 48113942 ps
CPU time 0.97 seconds
Started Jul 10 07:22:21 PM PDT 24
Finished Jul 10 07:22:28 PM PDT 24
Peak memory 215708 kb
Host smart-c5042f2c-ad09-4fe9-b3cc-a4234da795b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311788983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1311788983
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.652279156
Short name T949
Test name
Test status
Simulation time 358789741 ps
CPU time 1.78 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:27 PM PDT 24
Peak memory 217536 kb
Host smart-cd9c75ca-02b0-4286-bf4f-a2bffff23581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652279156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.652279156
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1748371312
Short name T493
Test name
Test status
Simulation time 143127537131 ps
CPU time 1894.98 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:54:04 PM PDT 24
Peak memory 228756 kb
Host smart-172b1720-8b2e-46ed-a507-859cb7f03a18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748371312 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1748371312
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1815832127
Short name T694
Test name
Test status
Simulation time 29841869 ps
CPU time 1.32 seconds
Started Jul 10 07:24:00 PM PDT 24
Finished Jul 10 07:24:06 PM PDT 24
Peak memory 218716 kb
Host smart-2826de0f-bf17-4678-89fd-5e454be2c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815832127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1815832127
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2964414629
Short name T917
Test name
Test status
Simulation time 31970708 ps
CPU time 1.24 seconds
Started Jul 10 07:24:05 PM PDT 24
Finished Jul 10 07:24:10 PM PDT 24
Peak memory 218660 kb
Host smart-eac0dbf0-4a31-424f-ad86-1fd7b71ab5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964414629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2964414629
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.4030475953
Short name T320
Test name
Test status
Simulation time 35818476 ps
CPU time 1.5 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 219076 kb
Host smart-13aa05eb-f657-4ff9-8744-80bd732e570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030475953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4030475953
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.939709066
Short name T974
Test name
Test status
Simulation time 186533548 ps
CPU time 1.33 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 219228 kb
Host smart-cc069e17-861f-4721-be88-7c2afef6a1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939709066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.939709066
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3970909790
Short name T773
Test name
Test status
Simulation time 143214645 ps
CPU time 1.47 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 219112 kb
Host smart-8e5a67ce-41d1-4822-a0be-c712c3c64882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970909790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3970909790
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3968920929
Short name T337
Test name
Test status
Simulation time 89942578 ps
CPU time 1.59 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 219580 kb
Host smart-da18252a-cc33-4489-a677-c823d04edb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968920929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3968920929
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2244252531
Short name T323
Test name
Test status
Simulation time 60976778 ps
CPU time 1.33 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 220396 kb
Host smart-bcb4edd7-30b4-4075-85ff-f763e09d695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244252531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2244252531
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.301254693
Short name T393
Test name
Test status
Simulation time 86846420 ps
CPU time 1.09 seconds
Started Jul 10 07:24:14 PM PDT 24
Finished Jul 10 07:24:21 PM PDT 24
Peak memory 217652 kb
Host smart-194e1d99-e44b-4d20-bf2d-13ea60e4fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301254693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.301254693
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4086285341
Short name T513
Test name
Test status
Simulation time 144305760 ps
CPU time 1.71 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 220564 kb
Host smart-994d855d-7b34-41ca-b52c-21e3e775c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086285341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4086285341
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.446544218
Short name T832
Test name
Test status
Simulation time 84283028 ps
CPU time 1.34 seconds
Started Jul 10 07:24:12 PM PDT 24
Finished Jul 10 07:24:18 PM PDT 24
Peak memory 217664 kb
Host smart-d8713419-4768-45de-b7ff-d015126ab155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446544218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.446544218
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3818919382
Short name T168
Test name
Test status
Simulation time 71335319 ps
CPU time 1.21 seconds
Started Jul 10 07:22:26 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 220008 kb
Host smart-7ce35b01-d01b-420d-9e02-c425b76def58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818919382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3818919382
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2418179219
Short name T386
Test name
Test status
Simulation time 13454131 ps
CPU time 0.93 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 215576 kb
Host smart-646176e8-5c0a-4d01-8818-c932c1623386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418179219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2418179219
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3650043329
Short name T958
Test name
Test status
Simulation time 18135932 ps
CPU time 0.89 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 216256 kb
Host smart-af154122-0529-4daa-97e0-92d9dfc0a990
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650043329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3650043329
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.951479860
Short name T712
Test name
Test status
Simulation time 102671791 ps
CPU time 0.99 seconds
Started Jul 10 07:22:31 PM PDT 24
Finished Jul 10 07:22:36 PM PDT 24
Peak memory 217084 kb
Host smart-780a8fa1-cca5-4089-9fab-5620a02946fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951479860 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.951479860
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3226849932
Short name T169
Test name
Test status
Simulation time 28275533 ps
CPU time 0.99 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 224132 kb
Host smart-90e2c529-dc1f-49ac-9f87-87132a0d0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226849932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3226849932
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1623925449
Short name T312
Test name
Test status
Simulation time 146576635 ps
CPU time 1.26 seconds
Started Jul 10 07:22:22 PM PDT 24
Finished Jul 10 07:22:29 PM PDT 24
Peak memory 217604 kb
Host smart-13e8741a-c72c-4170-88aa-0d3503d23d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623925449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1623925449
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.21136854
Short name T390
Test name
Test status
Simulation time 26116542 ps
CPU time 0.92 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 215860 kb
Host smart-736d6ea3-bba5-4952-9343-3d92cf62c2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21136854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.21136854
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3166866766
Short name T811
Test name
Test status
Simulation time 17493216 ps
CPU time 1 seconds
Started Jul 10 07:22:23 PM PDT 24
Finished Jul 10 07:22:30 PM PDT 24
Peak memory 215652 kb
Host smart-f2b86774-6ab4-4764-98a3-6c068c727602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166866766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3166866766
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3513935205
Short name T899
Test name
Test status
Simulation time 322366935 ps
CPU time 6.35 seconds
Started Jul 10 07:22:20 PM PDT 24
Finished Jul 10 07:22:32 PM PDT 24
Peak memory 218740 kb
Host smart-61699a5b-c733-4ae5-9bec-d8ccd804962e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513935205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3513935205
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1347287588
Short name T789
Test name
Test status
Simulation time 41147797703 ps
CPU time 252.31 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:26:45 PM PDT 24
Peak memory 218112 kb
Host smart-e4e854c2-274a-4404-a3af-74ff39e34db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347287588 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1347287588
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3797285189
Short name T57
Test name
Test status
Simulation time 59783134 ps
CPU time 1.34 seconds
Started Jul 10 07:24:12 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 219148 kb
Host smart-ea646c84-dfc6-4b9b-9e2f-b0e515b54cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797285189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3797285189
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2507560216
Short name T943
Test name
Test status
Simulation time 33946214 ps
CPU time 1.43 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 217804 kb
Host smart-80ecbeea-aed4-4e71-a8a0-25d8c52f0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507560216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2507560216
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1550030824
Short name T627
Test name
Test status
Simulation time 22609361 ps
CPU time 1.23 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 220292 kb
Host smart-1b069dd0-3893-4f3d-89da-6b3240a2b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550030824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1550030824
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3394823823
Short name T577
Test name
Test status
Simulation time 34979833 ps
CPU time 1.6 seconds
Started Jul 10 07:24:12 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 218896 kb
Host smart-92b755e8-a4f6-454a-b773-afed1cd04c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394823823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3394823823
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1318327521
Short name T394
Test name
Test status
Simulation time 263967612 ps
CPU time 1.79 seconds
Started Jul 10 07:24:15 PM PDT 24
Finished Jul 10 07:24:22 PM PDT 24
Peak memory 219328 kb
Host smart-493996d4-c89b-479b-a57c-70c497c7b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318327521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1318327521
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.440739536
Short name T528
Test name
Test status
Simulation time 45179496 ps
CPU time 1.08 seconds
Started Jul 10 07:24:07 PM PDT 24
Finished Jul 10 07:24:12 PM PDT 24
Peak memory 218884 kb
Host smart-1f764545-5ff5-48b7-9509-b1c715ecc6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440739536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.440739536
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4279530696
Short name T438
Test name
Test status
Simulation time 46502992 ps
CPU time 1.78 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:12 PM PDT 24
Peak memory 220276 kb
Host smart-e0e2969f-7344-45f2-b908-1992f42a2727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279530696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4279530696
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3871706759
Short name T384
Test name
Test status
Simulation time 76949326 ps
CPU time 1.07 seconds
Started Jul 10 07:24:09 PM PDT 24
Finished Jul 10 07:24:14 PM PDT 24
Peak memory 217524 kb
Host smart-be35c1f2-91e2-4fa3-93bd-1712044d1bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871706759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3871706759
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4282456006
Short name T377
Test name
Test status
Simulation time 36703300 ps
CPU time 1.5 seconds
Started Jul 10 07:24:09 PM PDT 24
Finished Jul 10 07:24:14 PM PDT 24
Peak memory 217836 kb
Host smart-a9889d89-8657-490d-9474-844426791e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282456006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4282456006
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3216517581
Short name T78
Test name
Test status
Simulation time 43245356 ps
CPU time 1.21 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:16 PM PDT 24
Peak memory 220352 kb
Host smart-e7f03f0a-1bad-413e-ad8e-9988c32fbb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216517581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3216517581
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.667668602
Short name T140
Test name
Test status
Simulation time 87682986 ps
CPU time 1.26 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 218924 kb
Host smart-ee3632f1-f377-48ce-9a38-965cf073b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667668602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.667668602
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2682254442
Short name T870
Test name
Test status
Simulation time 19072853 ps
CPU time 0.81 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:32 PM PDT 24
Peak memory 207124 kb
Host smart-999804f9-c1d2-402a-8e4c-5845412d28cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682254442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2682254442
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1441256939
Short name T131
Test name
Test status
Simulation time 63328131 ps
CPU time 1.18 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 217424 kb
Host smart-f391c091-3330-46a3-b6c4-6c7b5c1e7c52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441256939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1441256939
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.2429597414
Short name T911
Test name
Test status
Simulation time 64053503 ps
CPU time 1.33 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 217556 kb
Host smart-d176caa8-3a28-429b-89d9-1f55caa58d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429597414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2429597414
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1468887097
Short name T941
Test name
Test status
Simulation time 51597889 ps
CPU time 0.99 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:32 PM PDT 24
Peak memory 224148 kb
Host smart-79be343b-0b0d-4d56-a08a-8c3e1bdb9e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468887097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1468887097
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3091732611
Short name T462
Test name
Test status
Simulation time 15460461 ps
CPU time 1 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 215616 kb
Host smart-1d9f40f8-4a8b-48b9-a28c-308b9418b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091732611 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3091732611
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1286178108
Short name T979
Test name
Test status
Simulation time 469599838 ps
CPU time 2.26 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 215652 kb
Host smart-cf586f85-140b-49f9-92d7-0fb10fcf246a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286178108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1286178108
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3727705996
Short name T888
Test name
Test status
Simulation time 106656125453 ps
CPU time 1158.12 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:41:51 PM PDT 24
Peak memory 222356 kb
Host smart-f8688de0-4036-4eee-b990-2352f9d2c555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727705996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3727705996
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.354871131
Short name T749
Test name
Test status
Simulation time 57314994 ps
CPU time 1.02 seconds
Started Jul 10 07:24:09 PM PDT 24
Finished Jul 10 07:24:14 PM PDT 24
Peak memory 217744 kb
Host smart-922f5b87-5ebb-4fb2-a4f9-afc1ca9e6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354871131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.354871131
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.72015813
Short name T53
Test name
Test status
Simulation time 40877787 ps
CPU time 1.63 seconds
Started Jul 10 07:24:07 PM PDT 24
Finished Jul 10 07:24:12 PM PDT 24
Peak memory 218932 kb
Host smart-1eaeb709-28ef-4c0e-a1c4-13e7f7ea5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72015813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.72015813
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3104444777
Short name T553
Test name
Test status
Simulation time 93226568 ps
CPU time 1.24 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 217760 kb
Host smart-4d2abae8-6e56-4b3b-9732-0244d6a81822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104444777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3104444777
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3646884894
Short name T403
Test name
Test status
Simulation time 178374461 ps
CPU time 1.21 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 217944 kb
Host smart-25b763e4-01cb-47ee-83da-863bbc1c7e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646884894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3646884894
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2028775469
Short name T741
Test name
Test status
Simulation time 69729806 ps
CPU time 1.09 seconds
Started Jul 10 07:24:09 PM PDT 24
Finished Jul 10 07:24:14 PM PDT 24
Peak memory 217524 kb
Host smart-740cd6f3-d994-4665-b8fe-1f3f2a3870a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028775469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2028775469
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1279534006
Short name T874
Test name
Test status
Simulation time 57785116 ps
CPU time 1.25 seconds
Started Jul 10 07:24:18 PM PDT 24
Finished Jul 10 07:24:23 PM PDT 24
Peak memory 217612 kb
Host smart-d1ea71ae-3efd-4e6e-9dd1-00669c0e36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279534006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1279534006
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1826920637
Short name T356
Test name
Test status
Simulation time 71901607 ps
CPU time 1.68 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:20 PM PDT 24
Peak memory 218944 kb
Host smart-431b8cab-40f8-4ef1-a670-135257a62583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826920637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1826920637
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1556856306
Short name T678
Test name
Test status
Simulation time 35543038 ps
CPU time 1.09 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:15 PM PDT 24
Peak memory 217800 kb
Host smart-0661991b-32f3-4834-97d4-2e5500f11e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556856306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1556856306
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.805158623
Short name T526
Test name
Test status
Simulation time 60259862 ps
CPU time 1.65 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 219140 kb
Host smart-97a9cca6-aa9b-4f1b-8bbf-759ca5dc310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805158623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.805158623
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3064645659
Short name T449
Test name
Test status
Simulation time 119090976 ps
CPU time 2.69 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:22 PM PDT 24
Peak memory 219620 kb
Host smart-9f496633-0952-4e3e-a6e6-03cffd296e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064645659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3064645659
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2581657291
Short name T533
Test name
Test status
Simulation time 73888487 ps
CPU time 1.26 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 221788 kb
Host smart-2bfbce3c-e812-40d1-8f69-ad1e4d3a4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581657291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2581657291
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2233181403
Short name T852
Test name
Test status
Simulation time 25480601 ps
CPU time 0.89 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 207032 kb
Host smart-c5ea5d03-f218-4666-8c84-f77fcf4e382c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233181403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2233181403
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1521609992
Short name T894
Test name
Test status
Simulation time 10302230 ps
CPU time 0.84 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 216564 kb
Host smart-5688ac39-bc22-4b6a-8bde-389727e1670b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521609992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1521609992
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.381167244
Short name T798
Test name
Test status
Simulation time 42313960 ps
CPU time 0.98 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 217412 kb
Host smart-1d3224a6-c0ed-434b-829e-63c587e5bfdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381167244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.381167244
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2770141225
Short name T73
Test name
Test status
Simulation time 47987192 ps
CPU time 0.83 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 218584 kb
Host smart-644c873a-c584-4fae-a961-df5a9704808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770141225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2770141225
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2999192716
Short name T535
Test name
Test status
Simulation time 130786493 ps
CPU time 2.25 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 219960 kb
Host smart-a9e4c49e-b1a9-447f-919d-3ca9ac09a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999192716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2999192716
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2304255399
Short name T37
Test name
Test status
Simulation time 27752377 ps
CPU time 0.89 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 216112 kb
Host smart-50296b05-6df1-45e7-a6d1-16b0ad3406ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304255399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2304255399
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.241651117
Short name T768
Test name
Test status
Simulation time 18693375 ps
CPU time 1.01 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 215636 kb
Host smart-78b88e19-6a7e-4dfe-ad7e-c89c57b674a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241651117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.241651117
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.572255922
Short name T716
Test name
Test status
Simulation time 617078407 ps
CPU time 1.99 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 217792 kb
Host smart-82edda6e-a7b2-41b3-aa3b-7159a85b416c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572255922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.572255922
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1506857125
Short name T687
Test name
Test status
Simulation time 64820493453 ps
CPU time 1409.14 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:46:14 PM PDT 24
Peak memory 223740 kb
Host smart-863d91e0-d4bf-4e10-989c-4b6ef83ab440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506857125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1506857125
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.3691317517
Short name T465
Test name
Test status
Simulation time 73369043 ps
CPU time 2.87 seconds
Started Jul 10 07:24:15 PM PDT 24
Finished Jul 10 07:24:23 PM PDT 24
Peak memory 219608 kb
Host smart-e9554db3-8591-4ab7-b22c-f79b427bbfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691317517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3691317517
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.820678372
Short name T602
Test name
Test status
Simulation time 48189440 ps
CPU time 1.33 seconds
Started Jul 10 07:24:06 PM PDT 24
Finished Jul 10 07:24:11 PM PDT 24
Peak memory 219380 kb
Host smart-325e1339-f7a5-4d28-afe9-311a8be73c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820678372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.820678372
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1395981540
Short name T382
Test name
Test status
Simulation time 29621364 ps
CPU time 1.3 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 220224 kb
Host smart-67154426-33ae-4306-a707-854f99e3342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395981540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1395981540
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2173405302
Short name T715
Test name
Test status
Simulation time 32061988 ps
CPU time 1.29 seconds
Started Jul 10 07:24:13 PM PDT 24
Finished Jul 10 07:24:19 PM PDT 24
Peak memory 218784 kb
Host smart-5e8988cf-147a-4bd3-9fc4-1c7ed7ad351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173405302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2173405302
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2421307963
Short name T108
Test name
Test status
Simulation time 19624029 ps
CPU time 1.07 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:15 PM PDT 24
Peak memory 217896 kb
Host smart-b969cbfe-0e19-44a9-a0f4-fda51c7f61cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421307963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2421307963
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2762928756
Short name T411
Test name
Test status
Simulation time 22211212 ps
CPU time 1.09 seconds
Started Jul 10 07:24:19 PM PDT 24
Finished Jul 10 07:24:24 PM PDT 24
Peak memory 218184 kb
Host smart-d21d432b-fa50-4d5b-bd04-385a7a8e4768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762928756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2762928756
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2344523497
Short name T414
Test name
Test status
Simulation time 55112360 ps
CPU time 1.18 seconds
Started Jul 10 07:24:14 PM PDT 24
Finished Jul 10 07:24:20 PM PDT 24
Peak memory 217584 kb
Host smart-553f6475-49c5-49a6-b850-a74d3b1af4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344523497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2344523497
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2545608902
Short name T799
Test name
Test status
Simulation time 76839513 ps
CPU time 1.2 seconds
Started Jul 10 07:24:11 PM PDT 24
Finished Jul 10 07:24:17 PM PDT 24
Peak memory 218928 kb
Host smart-49858923-f49e-4e6c-8b67-0be90f66a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545608902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2545608902
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3278816087
Short name T554
Test name
Test status
Simulation time 124417422 ps
CPU time 1.2 seconds
Started Jul 10 07:24:10 PM PDT 24
Finished Jul 10 07:24:16 PM PDT 24
Peak memory 218760 kb
Host smart-5bbfc30d-5d9c-4c73-81e1-e48a2293cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278816087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3278816087
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3051386032
Short name T191
Test name
Test status
Simulation time 29533976 ps
CPU time 1.25 seconds
Started Jul 10 07:21:46 PM PDT 24
Finished Jul 10 07:21:50 PM PDT 24
Peak memory 219884 kb
Host smart-6fe69787-72d9-43ba-8b09-3934df02878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051386032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3051386032
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3592154513
Short name T434
Test name
Test status
Simulation time 20572515 ps
CPU time 1.01 seconds
Started Jul 10 07:21:46 PM PDT 24
Finished Jul 10 07:21:50 PM PDT 24
Peak memory 215472 kb
Host smart-7a634868-78c6-4714-95b0-7f1776959e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592154513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3592154513
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.287474436
Short name T235
Test name
Test status
Simulation time 64383663 ps
CPU time 0.89 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 216572 kb
Host smart-9d34b199-c908-4f0b-b8e4-eeb90e04c0b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287474436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.287474436
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1746994192
Short name T903
Test name
Test status
Simulation time 28940202 ps
CPU time 1.16 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 217116 kb
Host smart-78c789eb-06f3-4dc6-9fb3-465cbe0b9add
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746994192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1746994192
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3671045083
Short name T177
Test name
Test status
Simulation time 27057043 ps
CPU time 0.94 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 219052 kb
Host smart-e28aebfc-b9b8-403d-87ca-f27b13986a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671045083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3671045083
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.542693914
Short name T558
Test name
Test status
Simulation time 114647584 ps
CPU time 1.63 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:47 PM PDT 24
Peak memory 217624 kb
Host smart-2f600e30-4e59-4b9d-b534-24f5b24f70bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542693914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.542693914
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1040099728
Short name T30
Test name
Test status
Simulation time 28648306 ps
CPU time 0.95 seconds
Started Jul 10 07:21:45 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 216060 kb
Host smart-ac13a68e-d57b-44ad-91ca-4a3be343d2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040099728 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1040099728
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4020488344
Short name T448
Test name
Test status
Simulation time 51665365 ps
CPU time 0.88 seconds
Started Jul 10 07:21:44 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 207372 kb
Host smart-6fc74dad-5b59-46c1-a561-fc350c001fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020488344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4020488344
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1611184697
Short name T20
Test name
Test status
Simulation time 275396876 ps
CPU time 4.62 seconds
Started Jul 10 07:21:41 PM PDT 24
Finished Jul 10 07:21:49 PM PDT 24
Peak memory 242320 kb
Host smart-de574e24-b266-4bf0-9223-c97619ac09f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611184697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1611184697
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2220041030
Short name T623
Test name
Test status
Simulation time 50737627 ps
CPU time 0.92 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 215624 kb
Host smart-1e465216-0f4f-4e25-8484-44e3cd6dee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220041030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2220041030
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2803741090
Short name T4
Test name
Test status
Simulation time 193868796 ps
CPU time 1.89 seconds
Started Jul 10 07:21:40 PM PDT 24
Finished Jul 10 07:21:46 PM PDT 24
Peak memory 215536 kb
Host smart-a7316eee-3e45-480e-861b-cd9e8f5ec186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803741090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2803741090
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.558635667
Short name T542
Test name
Test status
Simulation time 184043071233 ps
CPU time 532.51 seconds
Started Jul 10 07:21:42 PM PDT 24
Finished Jul 10 07:30:39 PM PDT 24
Peak memory 219624 kb
Host smart-7a91fb5d-bb96-4214-a20f-7afb28d04867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558635667 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.558635667
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.918284954
Short name T185
Test name
Test status
Simulation time 59140191 ps
CPU time 1.19 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 219036 kb
Host smart-a946a583-0290-4803-b65a-343dd0d39fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918284954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.918284954
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3801746822
Short name T550
Test name
Test status
Simulation time 12013273 ps
CPU time 0.91 seconds
Started Jul 10 07:22:29 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 206848 kb
Host smart-abbc2bfa-2a10-40f8-bedf-d63fb629c6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801746822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3801746822
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2760433711
Short name T237
Test name
Test status
Simulation time 15215512 ps
CPU time 0.86 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 216672 kb
Host smart-3ef86df6-8a6e-441b-b36d-46e75d538bab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760433711 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2760433711
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4095365472
Short name T159
Test name
Test status
Simulation time 80471145 ps
CPU time 1.05 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 217336 kb
Host smart-193e5234-d5cd-4365-a2be-2384515f7ef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095365472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4095365472
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.652242725
Short name T689
Test name
Test status
Simulation time 29001629 ps
CPU time 1 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 218952 kb
Host smart-1dc85183-a469-4eba-9576-fba3ca22f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652242725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.652242725
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4220031773
Short name T450
Test name
Test status
Simulation time 98988979 ps
CPU time 1.59 seconds
Started Jul 10 07:22:26 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 219104 kb
Host smart-06f7ea17-f956-44b0-aab2-e9570a4d29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220031773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4220031773
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3104376815
Short name T565
Test name
Test status
Simulation time 22244385 ps
CPU time 1.11 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 215928 kb
Host smart-15b4019f-0c7b-4637-a350-361c5344a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104376815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3104376815
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2458410056
Short name T409
Test name
Test status
Simulation time 178222153 ps
CPU time 0.88 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 215648 kb
Host smart-cf064e63-253d-416f-857d-0ee8785c0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458410056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2458410056
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3090152849
Short name T699
Test name
Test status
Simulation time 341485838 ps
CPU time 7.11 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 220708 kb
Host smart-0cce3073-4226-4ea7-a85e-991d9bc2bf38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090152849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3090152849
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3630351122
Short name T893
Test name
Test status
Simulation time 79954836239 ps
CPU time 2108.11 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:57:43 PM PDT 24
Peak memory 229852 kb
Host smart-ea13f8a3-b71d-4314-88ff-75a70f28646c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630351122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3630351122
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1858990017
Short name T944
Test name
Test status
Simulation time 110336142 ps
CPU time 1.32 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 216028 kb
Host smart-f69a26c8-2100-4cff-83f7-f938f9ec1b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858990017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1858990017
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1575049268
Short name T781
Test name
Test status
Simulation time 29060904 ps
CPU time 0.97 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:22:41 PM PDT 24
Peak memory 215228 kb
Host smart-191a5183-9ce8-4d08-9e6e-6f2cf4741c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575049268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1575049268
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3062762648
Short name T85
Test name
Test status
Simulation time 39490985 ps
CPU time 1.06 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 217112 kb
Host smart-7e4b51f6-3ec5-4f15-a73d-d05680de314c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062762648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3062762648
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.859253430
Short name T152
Test name
Test status
Simulation time 59038437 ps
CPU time 1.18 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 232476 kb
Host smart-01689a61-370e-4add-85af-5bf71942d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859253430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.859253430
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1402256444
Short name T417
Test name
Test status
Simulation time 43930896 ps
CPU time 1.6 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 219028 kb
Host smart-e4d166f4-3395-43ad-b6e2-7c33d6a4b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402256444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1402256444
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.91501249
Short name T807
Test name
Test status
Simulation time 48283256 ps
CPU time 0.82 seconds
Started Jul 10 07:22:25 PM PDT 24
Finished Jul 10 07:22:31 PM PDT 24
Peak memory 215824 kb
Host smart-ec07283f-df8f-47d3-959e-8b042656bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91501249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.91501249
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1824872066
Short name T702
Test name
Test status
Simulation time 44609907 ps
CPU time 0.96 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 215652 kb
Host smart-a0928aaf-48d3-461a-8a3e-e8fc9412aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824872066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1824872066
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4131581801
Short name T610
Test name
Test status
Simulation time 364498258 ps
CPU time 3.94 seconds
Started Jul 10 07:22:43 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 217388 kb
Host smart-11b51103-4139-4b26-af60-75063531cab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131581801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4131581801
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2812586725
Short name T845
Test name
Test status
Simulation time 49369656861 ps
CPU time 643.48 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:33:18 PM PDT 24
Peak memory 218872 kb
Host smart-535cd2b0-61b8-4be2-96bb-f2f316f9c076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812586725 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2812586725
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.207576644
Short name T581
Test name
Test status
Simulation time 37261693 ps
CPU time 1.04 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:44 PM PDT 24
Peak memory 220144 kb
Host smart-8fab048f-38c6-40ad-b78a-274c9400bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207576644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.207576644
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3887916109
Short name T362
Test name
Test status
Simulation time 42022586 ps
CPU time 0.99 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 215208 kb
Host smart-c8597838-dd64-4081-bd7e-5113460071d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887916109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3887916109
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_err.231378306
Short name T419
Test name
Test status
Simulation time 27796399 ps
CPU time 0.88 seconds
Started Jul 10 07:32:15 PM PDT 24
Finished Jul 10 07:32:17 PM PDT 24
Peak memory 219736 kb
Host smart-00eb72ca-d2e3-43b2-98a9-ae8da79f346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231378306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.231378306
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2107103111
Short name T719
Test name
Test status
Simulation time 2233883420 ps
CPU time 70.69 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:23:45 PM PDT 24
Peak memory 218964 kb
Host smart-050cf318-3daf-495b-b20c-aca8e4068147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107103111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2107103111
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2122235900
Short name T620
Test name
Test status
Simulation time 39887476 ps
CPU time 1 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 224328 kb
Host smart-e0a240fd-b686-4763-a3f4-1cebd8dddb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122235900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2122235900
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2073637855
Short name T398
Test name
Test status
Simulation time 54274435 ps
CPU time 0.97 seconds
Started Jul 10 07:22:27 PM PDT 24
Finished Jul 10 07:22:33 PM PDT 24
Peak memory 215624 kb
Host smart-84695d89-1971-4c7a-96c2-271d87da09e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073637855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2073637855
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1252710780
Short name T630
Test name
Test status
Simulation time 133744588 ps
CPU time 2.09 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:48 PM PDT 24
Peak memory 215632 kb
Host smart-e05fa92e-7f41-420d-8660-77f69e37c1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252710780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1252710780
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3653590074
Short name T622
Test name
Test status
Simulation time 82393127358 ps
CPU time 569.05 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:32:13 PM PDT 24
Peak memory 224020 kb
Host smart-4a5acea5-07cf-433f-8015-257255df1a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653590074 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3653590074
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1564268849
Short name T111
Test name
Test status
Simulation time 126346703 ps
CPU time 1.18 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 219084 kb
Host smart-32a1022f-fc63-4762-8b02-29b8e926395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564268849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1564268849
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3388418860
Short name T361
Test name
Test status
Simulation time 32930317 ps
CPU time 1.02 seconds
Started Jul 10 07:22:30 PM PDT 24
Finished Jul 10 07:22:35 PM PDT 24
Peak memory 207092 kb
Host smart-95af75a4-1412-4894-8df2-6e01922ac9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388418860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3388418860
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3893207957
Short name T885
Test name
Test status
Simulation time 59459880 ps
CPU time 0.87 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 215764 kb
Host smart-53f0924c-e8b6-4bed-a6d1-994647ca6e7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893207957 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3893207957
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.449409739
Short name T431
Test name
Test status
Simulation time 37821331 ps
CPU time 1.25 seconds
Started Jul 10 07:22:33 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 217232 kb
Host smart-7485e70b-0912-40b9-8429-4b785325519d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449409739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.449409739
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1217996034
Short name T549
Test name
Test status
Simulation time 30691936 ps
CPU time 0.9 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 218708 kb
Host smart-c8863dbe-b5bd-4c1a-87e4-bca1d376deb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217996034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1217996034
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1169591837
Short name T802
Test name
Test status
Simulation time 270552603 ps
CPU time 3.69 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 217852 kb
Host smart-a1d56d5c-0980-415b-9b45-8dffb68ab1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169591837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1169591837
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.828300751
Short name T882
Test name
Test status
Simulation time 41550301 ps
CPU time 0.9 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 216184 kb
Host smart-ce73538c-68b0-42f6-8998-367a7fd4505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828300751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.828300751
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1951517881
Short name T688
Test name
Test status
Simulation time 20615292 ps
CPU time 0.96 seconds
Started Jul 10 07:22:28 PM PDT 24
Finished Jul 10 07:22:34 PM PDT 24
Peak memory 215636 kb
Host smart-e413790c-dafe-43b7-b318-7c90eb4cd6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951517881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1951517881
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.47664027
Short name T744
Test name
Test status
Simulation time 48476263 ps
CPU time 1.5 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:44 PM PDT 24
Peak memory 215556 kb
Host smart-12bf004b-51fa-4da5-afea-a6779ae5665c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47664027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.47664027
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1565013042
Short name T684
Test name
Test status
Simulation time 51433237155 ps
CPU time 767.44 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:35:30 PM PDT 24
Peak memory 220068 kb
Host smart-888d9450-24bb-4577-8f07-5138455edcab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565013042 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1565013042
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3831998143
Short name T856
Test name
Test status
Simulation time 66830604 ps
CPU time 1.07 seconds
Started Jul 10 07:22:33 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 219028 kb
Host smart-695129b7-77f3-4abe-8c41-2e782a594df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831998143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3831998143
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3228496311
Short name T65
Test name
Test status
Simulation time 53898051 ps
CPU time 0.88 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 215308 kb
Host smart-9e2d8c28-3e39-44f7-a4a8-7f99d03fe84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228496311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3228496311
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4131858643
Short name T425
Test name
Test status
Simulation time 12929069 ps
CPU time 0.91 seconds
Started Jul 10 07:22:35 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 216456 kb
Host smart-2b201202-2711-4f93-8e49-224dc21247a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131858643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4131858643
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.675197811
Short name T927
Test name
Test status
Simulation time 31308037 ps
CPU time 1.04 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 217416 kb
Host smart-b669527c-3086-4aa7-85a6-ba51d869f916
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675197811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.675197811
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4239928880
Short name T945
Test name
Test status
Simulation time 23209712 ps
CPU time 1.04 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 224248 kb
Host smart-4661a9ab-5def-423a-a0a4-f7da34594c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239928880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4239928880
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4028174037
Short name T634
Test name
Test status
Simulation time 163787232 ps
CPU time 1.2 seconds
Started Jul 10 07:22:35 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 217544 kb
Host smart-373ea9ed-6e0c-4543-a2d0-90a7d9085fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028174037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4028174037
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1074306748
Short name T723
Test name
Test status
Simulation time 25769798 ps
CPU time 1.17 seconds
Started Jul 10 07:22:33 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 224332 kb
Host smart-726be8b6-501b-4a20-a0c9-b8116f52f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074306748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1074306748
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1238287761
Short name T805
Test name
Test status
Simulation time 17019150 ps
CPU time 1 seconds
Started Jul 10 07:22:43 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 215628 kb
Host smart-c53aa7a3-e058-4c24-8539-acd0a318acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238287761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1238287761
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1321278602
Short name T66
Test name
Test status
Simulation time 1373502742 ps
CPU time 3.16 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:48 PM PDT 24
Peak memory 215620 kb
Host smart-ea1ed6d9-3d1d-4707-a44b-9486acefedc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321278602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1321278602
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2439842010
Short name T240
Test name
Test status
Simulation time 61015256025 ps
CPU time 1273.21 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:43:53 PM PDT 24
Peak memory 224260 kb
Host smart-ed524d47-9141-4f10-a6e0-d7cd7a3c8fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439842010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2439842010
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1693507810
Short name T991
Test name
Test status
Simulation time 52849192 ps
CPU time 1.27 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:44 PM PDT 24
Peak memory 220860 kb
Host smart-2b9a282e-0dff-4f8e-b64d-aa42b6aae17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693507810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1693507810
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.723935717
Short name T567
Test name
Test status
Simulation time 59233549 ps
CPU time 0.99 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 207116 kb
Host smart-b74cd61a-b59e-407d-8a6d-3b87f63165c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723935717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.723935717
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2125366095
Short name T222
Test name
Test status
Simulation time 17625838 ps
CPU time 0.83 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:42 PM PDT 24
Peak memory 216580 kb
Host smart-fc78d345-72b3-4d34-b56c-7d92b6f5767c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125366095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2125366095
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3383786490
Short name T655
Test name
Test status
Simulation time 78098217 ps
CPU time 1.26 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 219944 kb
Host smart-b9baf2d9-edf1-4e0d-8fae-47ec06ab8864
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383786490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3383786490
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2653779793
Short name T980
Test name
Test status
Simulation time 23735489 ps
CPU time 1.14 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:22:42 PM PDT 24
Peak memory 220948 kb
Host smart-44ba1c47-072b-4c4d-9157-52b013259342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653779793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2653779793
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2095806905
Short name T718
Test name
Test status
Simulation time 392053670 ps
CPU time 3.32 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 220728 kb
Host smart-3c836938-e969-4aeb-b7ea-b9c1e55fb589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095806905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2095806905
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.769037857
Short name T47
Test name
Test status
Simulation time 32738325 ps
CPU time 0.92 seconds
Started Jul 10 07:22:35 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 216112 kb
Host smart-c9dbc593-fcd3-4779-99ff-c748f2b996b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769037857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.769037857
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1296551540
Short name T969
Test name
Test status
Simulation time 44241235 ps
CPU time 1.07 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 215636 kb
Host smart-4304a003-c5f0-47c8-8e07-5135c37dba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296551540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1296551540
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1293379033
Short name T311
Test name
Test status
Simulation time 590526503 ps
CPU time 4.79 seconds
Started Jul 10 07:22:35 PM PDT 24
Finished Jul 10 07:22:41 PM PDT 24
Peak memory 217736 kb
Host smart-af547c98-99a0-4387-a0e9-a1d591e4723b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293379033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1293379033
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4277732759
Short name T83
Test name
Test status
Simulation time 143955747809 ps
CPU time 1646.63 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:50:05 PM PDT 24
Peak memory 224308 kb
Host smart-8cd31b9d-3e1e-47b7-909e-223bbb068ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277732759 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4277732759
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1460472545
Short name T179
Test name
Test status
Simulation time 27818706 ps
CPU time 1.22 seconds
Started Jul 10 07:22:44 PM PDT 24
Finished Jul 10 07:22:48 PM PDT 24
Peak memory 216064 kb
Host smart-b26bf3ee-007f-4580-b6b9-11f99651e4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460472545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1460472545
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3631879454
Short name T373
Test name
Test status
Simulation time 72384953 ps
CPU time 0.96 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:44 PM PDT 24
Peak memory 207148 kb
Host smart-7d3bafe4-6430-4d88-8439-6e57e66a2259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631879454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3631879454
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2250157746
Short name T522
Test name
Test status
Simulation time 35645820 ps
CPU time 0.85 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:38 PM PDT 24
Peak memory 216260 kb
Host smart-20f66d3e-0c24-49b9-b5e1-537e5ce89246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250157746 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2250157746
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.563562348
Short name T213
Test name
Test status
Simulation time 58488470 ps
CPU time 1.17 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 219692 kb
Host smart-7b762ef4-ccc5-4fcb-94aa-b45c56801f55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563562348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.563562348
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3168532536
Short name T147
Test name
Test status
Simulation time 38411279 ps
CPU time 1.21 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:43 PM PDT 24
Peak memory 230112 kb
Host smart-5bc2e61c-7189-4798-ad0a-ab4f364048c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168532536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3168532536
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3438653021
Short name T670
Test name
Test status
Simulation time 35315910 ps
CPU time 1.48 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 217580 kb
Host smart-35b2a779-5a58-42ac-80b6-3e9e7305e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438653021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3438653021
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2723530078
Short name T835
Test name
Test status
Simulation time 31502128 ps
CPU time 0.99 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:46 PM PDT 24
Peak memory 224148 kb
Host smart-c671dca1-92c4-4e6f-86f3-9d0677e25516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723530078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2723530078
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3780525641
Short name T358
Test name
Test status
Simulation time 38816405 ps
CPU time 0.91 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 215636 kb
Host smart-c0444b76-3c54-42a6-b04d-6ef887b577e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780525641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3780525641
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2094401926
Short name T600
Test name
Test status
Simulation time 244373246 ps
CPU time 3.11 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 215724 kb
Host smart-9e4b0cdf-f0ec-4e94-a08d-dcc40e0e1f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094401926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2094401926
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2801291827
Short name T244
Test name
Test status
Simulation time 346876850517 ps
CPU time 1899.27 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:54:18 PM PDT 24
Peak memory 225212 kb
Host smart-0ecb8c5a-dac6-4b54-8f31-37763a075f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801291827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2801291827
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2306743514
Short name T162
Test name
Test status
Simulation time 22236837 ps
CPU time 1.14 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 220984 kb
Host smart-65935b05-d345-479f-b711-473bcdc4f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306743514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2306743514
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1166635107
Short name T644
Test name
Test status
Simulation time 16908950 ps
CPU time 1 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 207028 kb
Host smart-daefdaa5-9c75-4ddd-9cc7-4c196a5ac3fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166635107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1166635107
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.182300233
Short name T925
Test name
Test status
Simulation time 37605444 ps
CPU time 0.83 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:22:43 PM PDT 24
Peak memory 216572 kb
Host smart-b02815a0-1e57-4740-976b-c51e1fa1c0e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182300233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.182300233
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3541974851
Short name T392
Test name
Test status
Simulation time 34895622 ps
CPU time 1.18 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:40 PM PDT 24
Peak memory 218580 kb
Host smart-8c829d4d-0156-4a3b-bf43-2b82e5014d89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541974851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3541974851
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2910896678
Short name T164
Test name
Test status
Simulation time 48632175 ps
CPU time 1.13 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 229980 kb
Host smart-df333805-03e2-4dd8-a016-64ff75b1eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910896678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2910896678
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2304036250
Short name T429
Test name
Test status
Simulation time 34192801 ps
CPU time 1.32 seconds
Started Jul 10 07:22:37 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 217564 kb
Host smart-dec7d5d8-547a-474c-9a50-3e721b741eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304036250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2304036250
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1975011216
Short name T666
Test name
Test status
Simulation time 32533584 ps
CPU time 0.87 seconds
Started Jul 10 07:22:33 PM PDT 24
Finished Jul 10 07:22:36 PM PDT 24
Peak memory 215820 kb
Host smart-30158c4e-f0b3-4a85-b0cc-0250f5195111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975011216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1975011216
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.979939591
Short name T387
Test name
Test status
Simulation time 46675598 ps
CPU time 0.91 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 215620 kb
Host smart-eb998fd5-02bf-4238-ad84-a1820a907315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979939591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.979939591
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1130533929
Short name T697
Test name
Test status
Simulation time 609907302 ps
CPU time 3.57 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:52 PM PDT 24
Peak memory 218788 kb
Host smart-035b86e5-3ab0-407e-88a3-abb1ebe7f812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130533929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1130533929
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3947180417
Short name T49
Test name
Test status
Simulation time 314249468731 ps
CPU time 1693.83 seconds
Started Jul 10 07:22:40 PM PDT 24
Finished Jul 10 07:50:57 PM PDT 24
Peak memory 225152 kb
Host smart-9e218479-ba2e-493e-9757-f3349b89629d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947180417 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3947180417
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1313833190
Short name T685
Test name
Test status
Simulation time 176161319 ps
CPU time 1.38 seconds
Started Jul 10 07:22:42 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 218784 kb
Host smart-2e93f546-ccd8-4f74-b6b4-a0b67a36c371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313833190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1313833190
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.175520529
Short name T534
Test name
Test status
Simulation time 47948266 ps
CPU time 0.88 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 207048 kb
Host smart-16c8e780-cc48-4059-be2c-be59dea8f3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175520529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.175520529
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_err.2822564731
Short name T539
Test name
Test status
Simulation time 51080171 ps
CPU time 0.85 seconds
Started Jul 10 07:22:43 PM PDT 24
Finished Jul 10 07:22:47 PM PDT 24
Peak memory 218560 kb
Host smart-13f0c138-1a27-4f27-bec7-1a5d3e274de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822564731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2822564731
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1705486325
Short name T871
Test name
Test status
Simulation time 49782915 ps
CPU time 1.21 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 217884 kb
Host smart-bcea9824-78ec-4f9a-9767-53fe0694b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705486325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1705486325
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3913086337
Short name T427
Test name
Test status
Simulation time 21365599 ps
CPU time 1.08 seconds
Started Jul 10 07:22:34 PM PDT 24
Finished Jul 10 07:22:37 PM PDT 24
Peak memory 215832 kb
Host smart-3250b8c7-940f-4191-aed3-09a5b99e4f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913086337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3913086337
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3341934292
Short name T359
Test name
Test status
Simulation time 29502076 ps
CPU time 1.03 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 215656 kb
Host smart-a72dbca0-64a2-448a-a558-69f75822a93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341934292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3341934292
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1945814311
Short name T834
Test name
Test status
Simulation time 145595592 ps
CPU time 1.19 seconds
Started Jul 10 07:22:47 PM PDT 24
Finished Jul 10 07:22:50 PM PDT 24
Peak memory 215600 kb
Host smart-3d63da72-3105-43c2-94a0-ac622d2f916c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945814311 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1945814311
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3577738461
Short name T731
Test name
Test status
Simulation time 15245087595 ps
CPU time 370.82 seconds
Started Jul 10 07:22:34 PM PDT 24
Finished Jul 10 07:28:47 PM PDT 24
Peak memory 218772 kb
Host smart-e22f1e55-d1f9-4dcd-a157-bc48faaa7ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577738461 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3577738461
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.465995510
Short name T119
Test name
Test status
Simulation time 25525800 ps
CPU time 1.15 seconds
Started Jul 10 07:22:41 PM PDT 24
Finished Jul 10 07:22:45 PM PDT 24
Peak memory 221120 kb
Host smart-8ec076d7-ad03-46aa-b056-0dbbabe7b2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465995510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.465995510
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.937680145
Short name T872
Test name
Test status
Simulation time 88962725 ps
CPU time 0.81 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 206356 kb
Host smart-9f768468-61fa-4eac-8012-19605853521b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937680145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.937680145
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3927711598
Short name T221
Test name
Test status
Simulation time 19882870 ps
CPU time 0.88 seconds
Started Jul 10 07:22:34 PM PDT 24
Finished Jul 10 07:22:36 PM PDT 24
Peak memory 216824 kb
Host smart-316cd6f1-113a-446d-9e4b-d6e02cb7ee12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927711598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3927711598
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3808941577
Short name T226
Test name
Test status
Simulation time 90170988 ps
CPU time 1.1 seconds
Started Jul 10 07:22:51 PM PDT 24
Finished Jul 10 07:22:55 PM PDT 24
Peak memory 217232 kb
Host smart-f644a290-6292-4044-8a12-e67f7ac7a1bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808941577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3808941577
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.190995593
Short name T223
Test name
Test status
Simulation time 20213282 ps
CPU time 0.97 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:22:42 PM PDT 24
Peak memory 218748 kb
Host smart-b1492cf6-4630-4b75-ab0a-9e730878c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190995593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.190995593
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1088334156
Short name T110
Test name
Test status
Simulation time 39038401 ps
CPU time 1.47 seconds
Started Jul 10 07:22:39 PM PDT 24
Finished Jul 10 07:22:43 PM PDT 24
Peak memory 217644 kb
Host smart-9870d494-72f5-49f8-9473-e9bb89995db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088334156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1088334156
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4034517500
Short name T510
Test name
Test status
Simulation time 76314774 ps
CPU time 0.94 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:22:42 PM PDT 24
Peak memory 224152 kb
Host smart-fca58d6b-f631-4e91-9af2-f1c36716a7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034517500 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4034517500
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.117256044
Short name T794
Test name
Test status
Simulation time 61362079 ps
CPU time 0.97 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:22:41 PM PDT 24
Peak memory 215620 kb
Host smart-b02d7045-59c1-4560-9184-3ea5bede5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117256044 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.117256044
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2671081714
Short name T891
Test name
Test status
Simulation time 346804654 ps
CPU time 1.56 seconds
Started Jul 10 07:22:36 PM PDT 24
Finished Jul 10 07:22:39 PM PDT 24
Peak memory 215628 kb
Host smart-f4ac5ee5-bd54-4f82-9111-aab5625b4edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671081714 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2671081714
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.151158303
Short name T494
Test name
Test status
Simulation time 70180853930 ps
CPU time 1788.74 seconds
Started Jul 10 07:22:38 PM PDT 24
Finished Jul 10 07:52:30 PM PDT 24
Peak memory 227932 kb
Host smart-a97fca08-238b-4a78-80a0-e1eb7c01240b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151158303 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.151158303
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.934919777
Short name T303
Test name
Test status
Simulation time 186778874 ps
CPU time 1.23 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:22:00 PM PDT 24
Peak memory 220792 kb
Host smart-f8cea765-daef-4ac1-a09a-e9716f82ab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934919777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.934919777
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3159312569
Short name T460
Test name
Test status
Simulation time 16597866 ps
CPU time 0.93 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 206832 kb
Host smart-44954767-7aa7-4499-a56a-db91f2512be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159312569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3159312569
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.52961461
Short name T400
Test name
Test status
Simulation time 36636008 ps
CPU time 0.81 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 216192 kb
Host smart-e8652461-dac8-4d5c-b185-0749ab0bbc85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52961461 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.52961461
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2880149679
Short name T433
Test name
Test status
Simulation time 33784952 ps
CPU time 1.16 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 218752 kb
Host smart-20097764-89bb-422b-afcc-0e868cb03b1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880149679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2880149679
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.805306558
Short name T497
Test name
Test status
Simulation time 37368639 ps
CPU time 0.85 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 218492 kb
Host smart-bb857c86-c3e0-4a95-b503-90b70da21590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805306558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.805306558
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1767414089
Short name T940
Test name
Test status
Simulation time 86588952 ps
CPU time 1.12 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 219428 kb
Host smart-082fa887-1f69-4695-a54f-f2e6f76c5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767414089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1767414089
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.804021243
Short name T39
Test name
Test status
Simulation time 147401968 ps
CPU time 0.99 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:53 PM PDT 24
Peak memory 207448 kb
Host smart-34fcf7ac-aca5-435a-b69d-6f6c40d20759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804021243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.804021243
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.670140072
Short name T71
Test name
Test status
Simulation time 913366910 ps
CPU time 7.93 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 237568 kb
Host smart-19e3a770-58e5-470b-9fe8-c4e7f6bd5f72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670140072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.670140072
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1172677871
Short name T86
Test name
Test status
Simulation time 23517398 ps
CPU time 0.92 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:53 PM PDT 24
Peak memory 215656 kb
Host smart-b20e7440-2ed2-4c9a-9cbd-c94e4cb63568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172677871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1172677871
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4285041965
Short name T571
Test name
Test status
Simulation time 255558367 ps
CPU time 2.82 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 215616 kb
Host smart-e860010a-39c7-4209-bc4e-17e3aa080e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285041965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4285041965
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2854191638
Short name T662
Test name
Test status
Simulation time 49162060706 ps
CPU time 605.52 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:32:09 PM PDT 24
Peak memory 219580 kb
Host smart-dbc8e0d4-759b-48a9-acd6-d4250f2df912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854191638 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2854191638
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3610068800
Short name T205
Test name
Test status
Simulation time 52950500 ps
CPU time 1.24 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:23:00 PM PDT 24
Peak memory 219348 kb
Host smart-9e1577db-b463-44a6-885b-e7736fe3e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610068800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3610068800
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3550336618
Short name T784
Test name
Test status
Simulation time 29901226 ps
CPU time 0.92 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 207092 kb
Host smart-0075ac78-cee4-4d9e-9578-f9c2828c8d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550336618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3550336618
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1459318006
Short name T171
Test name
Test status
Simulation time 13169153 ps
CPU time 0.94 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 207772 kb
Host smart-007b8b3b-dd30-4a3b-b3d4-3edbe58f91c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459318006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1459318006
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3786148823
Short name T158
Test name
Test status
Simulation time 261759611 ps
CPU time 1.08 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 217320 kb
Host smart-51b04e04-545f-41ba-8444-3cc145220df6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786148823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3786148823
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3708995964
Short name T220
Test name
Test status
Simulation time 46894720 ps
CPU time 1.09 seconds
Started Jul 10 07:22:52 PM PDT 24
Finished Jul 10 07:22:55 PM PDT 24
Peak memory 219968 kb
Host smart-be7b2088-b059-452f-93f4-a1b52d7776e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708995964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3708995964
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.503263201
Short name T336
Test name
Test status
Simulation time 63809022 ps
CPU time 1.24 seconds
Started Jul 10 07:22:58 PM PDT 24
Finished Jul 10 07:23:04 PM PDT 24
Peak memory 219164 kb
Host smart-c74b6ef5-e059-4e0b-9def-4ac457963883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503263201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.503263201
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3511402658
Short name T740
Test name
Test status
Simulation time 30690778 ps
CPU time 0.99 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 215736 kb
Host smart-77970102-53b7-441b-b0e4-90bc7e53f3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511402658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3511402658
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3339069721
Short name T346
Test name
Test status
Simulation time 16497909 ps
CPU time 0.97 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:02 PM PDT 24
Peak memory 215620 kb
Host smart-10d8aafd-4813-4b18-8f01-681a8955c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339069721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3339069721
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3423207143
Short name T816
Test name
Test status
Simulation time 316374005 ps
CPU time 1.5 seconds
Started Jul 10 07:22:53 PM PDT 24
Finished Jul 10 07:22:57 PM PDT 24
Peak memory 217652 kb
Host smart-35076ace-6848-44ee-b589-53571b79c151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423207143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3423207143
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3242169915
Short name T239
Test name
Test status
Simulation time 24618181853 ps
CPU time 521.44 seconds
Started Jul 10 07:22:57 PM PDT 24
Finished Jul 10 07:31:43 PM PDT 24
Peak memory 218416 kb
Host smart-cfcc894b-5c62-40a5-9597-792e2466fc8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242169915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3242169915
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2956397450
Short name T814
Test name
Test status
Simulation time 126432059 ps
CPU time 1.15 seconds
Started Jul 10 07:22:59 PM PDT 24
Finished Jul 10 07:23:04 PM PDT 24
Peak memory 220064 kb
Host smart-9f12e52a-a977-4799-8061-55ed59c364fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956397450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2956397450
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.274788517
Short name T641
Test name
Test status
Simulation time 37794848 ps
CPU time 0.93 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 215508 kb
Host smart-b2882298-57ce-4d0f-98f6-b64878b771f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274788517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.274788517
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.4006346083
Short name T199
Test name
Test status
Simulation time 22200306 ps
CPU time 0.87 seconds
Started Jul 10 07:23:00 PM PDT 24
Finished Jul 10 07:23:04 PM PDT 24
Peak memory 216580 kb
Host smart-869d7bd2-e831-442a-b5f6-942fb768f954
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006346083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4006346083
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1595831816
Short name T664
Test name
Test status
Simulation time 103559015 ps
CPU time 1.2 seconds
Started Jul 10 07:22:53 PM PDT 24
Finished Jul 10 07:22:57 PM PDT 24
Peak memory 217252 kb
Host smart-331294c3-4dd1-49c9-89b3-8cd8b63b9356
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595831816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1595831816
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1622609
Short name T747
Test name
Test status
Simulation time 21748635 ps
CPU time 0.9 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 218936 kb
Host smart-12a8a05d-3191-424c-9d06-749d192b6b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1622609
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2037563135
Short name T467
Test name
Test status
Simulation time 62493933 ps
CPU time 1.12 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 220096 kb
Host smart-6d697aa2-e3d6-4a05-aef0-6c5d8e8a2c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037563135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2037563135
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1097860493
Short name T613
Test name
Test status
Simulation time 22221291 ps
CPU time 1.13 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 223712 kb
Host smart-106868c9-5840-4b66-aeaa-c17ab65af98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097860493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1097860493
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2694893679
Short name T516
Test name
Test status
Simulation time 49093608 ps
CPU time 0.91 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 215636 kb
Host smart-d79eea2a-c705-44c6-bbbe-cb58be3acd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694893679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2694893679
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2121979282
Short name T705
Test name
Test status
Simulation time 765610682 ps
CPU time 2.12 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 217632 kb
Host smart-10b246f3-4f35-4ac2-abe2-3772e52f42f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121979282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2121979282
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1035778726
Short name T48
Test name
Test status
Simulation time 44493613321 ps
CPU time 522.35 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:31:41 PM PDT 24
Peak memory 219268 kb
Host smart-71e31bec-ab32-40ec-b7b5-2d0f043ba60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035778726 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1035778726
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.581758111
Short name T105
Test name
Test status
Simulation time 48119717 ps
CPU time 1.24 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 215364 kb
Host smart-282e3f9d-6281-43c9-81a5-e8ec5c03dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581758111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.581758111
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4218121576
Short name T788
Test name
Test status
Simulation time 35054513 ps
CPU time 0.88 seconds
Started Jul 10 07:22:52 PM PDT 24
Finished Jul 10 07:22:55 PM PDT 24
Peak memory 215208 kb
Host smart-ac583171-900a-464f-9fc8-76dfff3dffc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218121576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4218121576
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1319959023
Short name T229
Test name
Test status
Simulation time 11126168 ps
CPU time 0.87 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:02 PM PDT 24
Peak memory 216152 kb
Host smart-f264cfb6-7449-4d8c-b4a1-8a43c3a9c862
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319959023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1319959023
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.897490020
Short name T606
Test name
Test status
Simulation time 38041768 ps
CPU time 1.26 seconds
Started Jul 10 07:22:53 PM PDT 24
Finished Jul 10 07:22:57 PM PDT 24
Peak memory 217320 kb
Host smart-238366df-efd2-49d1-a009-e1ff378a0337
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897490020 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.897490020
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2842681134
Short name T75
Test name
Test status
Simulation time 23580312 ps
CPU time 1.11 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 219852 kb
Host smart-2fcae80e-5088-4060-af69-95816c4c9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842681134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2842681134
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.556309588
Short name T333
Test name
Test status
Simulation time 41901428 ps
CPU time 1.73 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:23:00 PM PDT 24
Peak memory 218784 kb
Host smart-ad714998-5b5b-4fed-bf68-41b0ab02f4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556309588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.556309588
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3460283307
Short name T121
Test name
Test status
Simulation time 28930510 ps
CPU time 0.91 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 216120 kb
Host smart-fc348ada-0a27-4145-97c6-effa12556a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460283307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3460283307
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2857495968
Short name T472
Test name
Test status
Simulation time 19765983 ps
CPU time 1.11 seconds
Started Jul 10 07:22:58 PM PDT 24
Finished Jul 10 07:23:03 PM PDT 24
Peak memory 215812 kb
Host smart-04e7e044-7ec1-4028-8763-21d0989e065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857495968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2857495968
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3730828074
Short name T562
Test name
Test status
Simulation time 701442185 ps
CPU time 4.69 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:23:04 PM PDT 24
Peak memory 217444 kb
Host smart-e5368887-a3c3-467e-972e-c4bb6d642487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730828074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3730828074
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2166079400
Short name T815
Test name
Test status
Simulation time 140642460261 ps
CPU time 872.87 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:37:31 PM PDT 24
Peak memory 224040 kb
Host smart-a39545fd-329d-4e48-abe2-9833558dc060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166079400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2166079400
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2276754057
Short name T256
Test name
Test status
Simulation time 31857450 ps
CPU time 1.38 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:00 PM PDT 24
Peak memory 220340 kb
Host smart-cacbef48-4e21-465e-948d-c4b7bd546142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276754057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2276754057
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3287236434
Short name T369
Test name
Test status
Simulation time 22484912 ps
CPU time 0.87 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 207104 kb
Host smart-279fa5da-c647-4e55-9e7b-f21f60725c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287236434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3287236434
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3248354435
Short name T659
Test name
Test status
Simulation time 11546505 ps
CPU time 0.92 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 216320 kb
Host smart-6b3b33ee-22af-43e4-8006-6d7cda7fc6b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248354435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3248354435
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1601725856
Short name T727
Test name
Test status
Simulation time 38818357 ps
CPU time 1.32 seconds
Started Jul 10 07:22:57 PM PDT 24
Finished Jul 10 07:23:03 PM PDT 24
Peak memory 219944 kb
Host smart-08d64b0b-8bf6-4ff9-9698-a5549a2df0ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601725856 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1601725856
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4125541216
Short name T552
Test name
Test status
Simulation time 22904764 ps
CPU time 1.1 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 224380 kb
Host smart-7d4c0564-9ae3-471b-9175-bd41533128b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125541216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4125541216
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3013816399
Short name T758
Test name
Test status
Simulation time 47763521 ps
CPU time 2.11 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:03 PM PDT 24
Peak memory 217900 kb
Host smart-f6ab5204-14d0-4824-8264-e48d0e3924ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013816399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3013816399
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1995420713
Short name T639
Test name
Test status
Simulation time 25542487 ps
CPU time 0.98 seconds
Started Jul 10 07:22:53 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 215956 kb
Host smart-2de193dc-a8b4-474d-8d6e-002c43230a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995420713 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1995420713
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1139003937
Short name T556
Test name
Test status
Simulation time 47652430 ps
CPU time 0.97 seconds
Started Jul 10 07:22:52 PM PDT 24
Finished Jul 10 07:22:55 PM PDT 24
Peak memory 215624 kb
Host smart-9a557cc1-3e53-49f6-ac1c-9f3224e6307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139003937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1139003937
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1844359787
Short name T363
Test name
Test status
Simulation time 48956944 ps
CPU time 1.62 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 217460 kb
Host smart-4d1c666a-c137-4c00-b8b4-3eda3f157447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844359787 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1844359787
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1042038406
Short name T242
Test name
Test status
Simulation time 235486724443 ps
CPU time 1558.39 seconds
Started Jul 10 07:22:58 PM PDT 24
Finished Jul 10 07:49:01 PM PDT 24
Peak memory 223724 kb
Host smart-02c22564-3ea1-48b2-90ae-6725aee9b9d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042038406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1042038406
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1302743705
Short name T824
Test name
Test status
Simulation time 28067279 ps
CPU time 1.22 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 220108 kb
Host smart-be0f6766-de61-46a9-a2c9-6c19f8e442ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302743705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1302743705
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2545436875
Short name T867
Test name
Test status
Simulation time 33091567 ps
CPU time 0.82 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 207100 kb
Host smart-07df62f2-3fa0-4bfa-a219-f55078f2e7b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545436875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2545436875
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.661813838
Short name T215
Test name
Test status
Simulation time 13074905 ps
CPU time 0.92 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 216764 kb
Host smart-1beaef97-ed6a-4f95-847e-7eac9b70f2d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661813838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.661813838
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1718774684
Short name T574
Test name
Test status
Simulation time 36271738 ps
CPU time 1.08 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:59 PM PDT 24
Peak memory 219040 kb
Host smart-70d6eca9-ab4b-4733-ae1f-f8806effbd9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718774684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1718774684
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3996214590
Short name T847
Test name
Test status
Simulation time 20518212 ps
CPU time 1.14 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:23:00 PM PDT 24
Peak memory 220196 kb
Host smart-b4099856-cd4c-4239-afaa-1e9dbbfe17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996214590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3996214590
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3844632816
Short name T388
Test name
Test status
Simulation time 93205469 ps
CPU time 1.01 seconds
Started Jul 10 07:22:53 PM PDT 24
Finished Jul 10 07:22:56 PM PDT 24
Peak memory 217620 kb
Host smart-9eeadc94-f16d-4110-b545-9ace7925ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844632816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3844632816
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1211875588
Short name T953
Test name
Test status
Simulation time 22711025 ps
CPU time 1.06 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:22:58 PM PDT 24
Peak memory 215744 kb
Host smart-2b97ea7a-28d1-44ff-a803-c540d158928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211875588 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1211875588
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.962285359
Short name T898
Test name
Test status
Simulation time 34754059 ps
CPU time 0.92 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 215624 kb
Host smart-a1270077-bec0-40ea-b268-0ce6c611dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962285359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.962285359
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.847559789
Short name T491
Test name
Test status
Simulation time 192731037 ps
CPU time 2.34 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 217544 kb
Host smart-14bd29cd-824b-46ed-bf98-b5d989b0467f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847559789 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.847559789
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1712646572
Short name T796
Test name
Test status
Simulation time 129900484955 ps
CPU time 406.77 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:29:46 PM PDT 24
Peak memory 219368 kb
Host smart-bbf3c8f2-9754-4376-a42a-1306e794de4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712646572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1712646572
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1013702634
Short name T405
Test name
Test status
Simulation time 45112153 ps
CPU time 1.2 seconds
Started Jul 10 07:22:55 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 218876 kb
Host smart-cde98323-f128-4416-b8f9-d6b01c4b883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013702634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1013702634
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3639097018
Short name T843
Test name
Test status
Simulation time 67647964 ps
CPU time 0.8 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 207004 kb
Host smart-2749380c-0978-4b59-9771-89eed4e8d799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639097018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3639097018
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.640275646
Short name T994
Test name
Test status
Simulation time 12683423 ps
CPU time 0.89 seconds
Started Jul 10 07:22:52 PM PDT 24
Finished Jul 10 07:22:55 PM PDT 24
Peak memory 216864 kb
Host smart-f411af48-aa50-44aa-b370-7d8a1ee26624
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640275646 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.640275646
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3308154423
Short name T621
Test name
Test status
Simulation time 111097907 ps
CPU time 1.06 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:02 PM PDT 24
Peak memory 217188 kb
Host smart-20b44f2c-518e-4d9e-be9e-6b7dba347ea7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308154423 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3308154423
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3729166031
Short name T204
Test name
Test status
Simulation time 19249779 ps
CPU time 1.09 seconds
Started Jul 10 07:22:58 PM PDT 24
Finished Jul 10 07:23:03 PM PDT 24
Peak memory 218728 kb
Host smart-7a5a8891-15cf-4ab6-a50e-ec19aedfae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729166031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3729166031
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1218891039
Short name T873
Test name
Test status
Simulation time 34885677 ps
CPU time 1.04 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:02 PM PDT 24
Peak memory 215180 kb
Host smart-ca1ec134-e225-4ab7-b2c8-846f997abbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218891039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1218891039
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1772260818
Short name T42
Test name
Test status
Simulation time 33268130 ps
CPU time 0.87 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:02 PM PDT 24
Peak memory 215976 kb
Host smart-11cbf300-cbbd-43e6-8723-1f3c1af5e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772260818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1772260818
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1838476192
Short name T249
Test name
Test status
Simulation time 29203586 ps
CPU time 0.95 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:23:01 PM PDT 24
Peak memory 215704 kb
Host smart-f873c7e9-0ee4-41af-b1e3-94419ba94512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838476192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1838476192
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4149506364
Short name T38
Test name
Test status
Simulation time 877341028 ps
CPU time 4.43 seconds
Started Jul 10 07:22:54 PM PDT 24
Finished Jul 10 07:23:03 PM PDT 24
Peak memory 217664 kb
Host smart-c62db847-7329-4b0f-a45e-ee0eaeeed114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149506364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4149506364
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1165758447
Short name T643
Test name
Test status
Simulation time 92489830159 ps
CPU time 1093.18 seconds
Started Jul 10 07:22:56 PM PDT 24
Finished Jul 10 07:41:14 PM PDT 24
Peak memory 224044 kb
Host smart-2fd51110-cce8-4d78-9a34-ed42c2139be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165758447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1165758447
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2432295393
Short name T909
Test name
Test status
Simulation time 84637812 ps
CPU time 1.16 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 219724 kb
Host smart-469c6042-2fd3-4700-b524-b1e3917243ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432295393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2432295393
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3817294440
Short name T686
Test name
Test status
Simulation time 55351999 ps
CPU time 0.94 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 207120 kb
Host smart-c8b9defc-208a-4fbe-9fe6-b1194c999cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817294440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3817294440
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.546063613
Short name T764
Test name
Test status
Simulation time 10562281 ps
CPU time 0.85 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 216252 kb
Host smart-fd37a108-8ba2-41bd-a08c-4fc644aa5d0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546063613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.546063613
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1163839641
Short name T211
Test name
Test status
Simulation time 34541329 ps
CPU time 1.17 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 218512 kb
Host smart-16cc0b9f-58f3-4459-8307-1b0cdb8a3ad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163839641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1163839641
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1246685683
Short name T127
Test name
Test status
Simulation time 20526763 ps
CPU time 1.2 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 229696 kb
Host smart-5df9e57f-0926-4f1e-aac9-ec3fc7cd1330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246685683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1246685683
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1598538218
Short name T381
Test name
Test status
Simulation time 51084397 ps
CPU time 1.34 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 217608 kb
Host smart-38e45fd4-aa63-4906-b350-c24ecfd27a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598538218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1598538218
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3301961412
Short name T456
Test name
Test status
Simulation time 25207998 ps
CPU time 0.99 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 215864 kb
Host smart-5a40e816-6447-43ba-b536-c0863a602baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301961412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3301961412
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.279047650
Short name T575
Test name
Test status
Simulation time 30630377 ps
CPU time 0.94 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 215624 kb
Host smart-bfd6de3c-e08e-45ad-b0dc-16b2fd77645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279047650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.279047650
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.236177028
Short name T330
Test name
Test status
Simulation time 217090992 ps
CPU time 4.63 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 216928 kb
Host smart-cf9806c1-fddd-4fff-a160-eb93f7cce3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236177028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.236177028
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1737398739
Short name T800
Test name
Test status
Simulation time 34851992658 ps
CPU time 907.72 seconds
Started Jul 10 07:23:03 PM PDT 24
Finished Jul 10 07:38:13 PM PDT 24
Peak memory 224032 kb
Host smart-14386ec8-202a-4193-b64f-51af9837bcd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737398739 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1737398739
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.96287758
Short name T118
Test name
Test status
Simulation time 39718709 ps
CPU time 1.04 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 218968 kb
Host smart-9bfbb745-fd73-4ebc-8a01-a22b9cd548f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96287758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.96287758
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3634994916
Short name T635
Test name
Test status
Simulation time 69719312 ps
CPU time 0.86 seconds
Started Jul 10 07:23:01 PM PDT 24
Finished Jul 10 07:23:04 PM PDT 24
Peak memory 215216 kb
Host smart-152a3496-3186-4b56-aa61-5631e3a2f89f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634994916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3634994916
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1586788958
Short name T130
Test name
Test status
Simulation time 91049827 ps
CPU time 1.29 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 217120 kb
Host smart-785f2b21-3c3f-4e1a-8d0a-8fd5673717ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586788958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1586788958
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3154188248
Short name T492
Test name
Test status
Simulation time 29524928 ps
CPU time 1.17 seconds
Started Jul 10 07:23:01 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 219948 kb
Host smart-dcff5757-6f2b-42a4-9c88-cacfbd1f7dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154188248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3154188248
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1326770621
Short name T849
Test name
Test status
Simulation time 78695883 ps
CPU time 2.72 seconds
Started Jul 10 07:23:03 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 220232 kb
Host smart-836f48db-7499-4c7d-8241-678b0c01c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326770621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1326770621
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.137185486
Short name T548
Test name
Test status
Simulation time 33428018 ps
CPU time 1.07 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 224324 kb
Host smart-3c1f47c6-403f-424c-acb3-7861957b522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137185486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.137185486
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1160929699
Short name T625
Test name
Test status
Simulation time 16021774 ps
CPU time 0.97 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 215612 kb
Host smart-8e17a7ba-727d-4adc-a085-0a6a6d1a2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160929699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1160929699
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.462385811
Short name T418
Test name
Test status
Simulation time 212468445 ps
CPU time 2.81 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:07 PM PDT 24
Peak memory 217632 kb
Host smart-fa44081e-0530-40c2-84fa-4b381ba28e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462385811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.462385811
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1889285625
Short name T654
Test name
Test status
Simulation time 102053049546 ps
CPU time 1270.53 seconds
Started Jul 10 07:23:00 PM PDT 24
Finished Jul 10 07:44:14 PM PDT 24
Peak memory 225544 kb
Host smart-954a8a53-ba04-41c9-8de8-e4e65be3bd4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889285625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1889285625
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.4164063762
Short name T700
Test name
Test status
Simulation time 77988862 ps
CPU time 1.16 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 218436 kb
Host smart-ee89c415-5f3d-4f76-8f56-c8d0d0ab7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164063762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.4164063762
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4242073743
Short name T801
Test name
Test status
Simulation time 31905963 ps
CPU time 0.93 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 215356 kb
Host smart-0ba5c7fd-cd34-49d6-8e76-991c1f89761c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242073743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4242073743
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3424660171
Short name T189
Test name
Test status
Simulation time 10307548 ps
CPU time 0.87 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 216248 kb
Host smart-5e16c18f-3c92-483b-afe2-5f1de9b81c0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424660171 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3424660171
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3988559317
Short name T959
Test name
Test status
Simulation time 68904382 ps
CPU time 1.04 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 218796 kb
Host smart-f08e5295-3d85-4140-997e-e979f7d472d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988559317 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3988559317
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2694199580
Short name T214
Test name
Test status
Simulation time 35802066 ps
CPU time 1.32 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 215760 kb
Host smart-9c1e5cd9-8326-4930-8ca9-f19be4588a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694199580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2694199580
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.916056007
Short name T395
Test name
Test status
Simulation time 185963815 ps
CPU time 1.79 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:12 PM PDT 24
Peak memory 219036 kb
Host smart-eade011c-443c-4737-ac39-333b0958212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916056007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.916056007
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1687882510
Short name T650
Test name
Test status
Simulation time 23821933 ps
CPU time 1.01 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 215784 kb
Host smart-5a10f5a1-1ba7-4c2c-8197-982324820f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687882510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1687882510
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.200394913
Short name T836
Test name
Test status
Simulation time 25925110 ps
CPU time 0.98 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:12 PM PDT 24
Peak memory 215616 kb
Host smart-79efe2a6-204a-43cc-b621-3fb89aed009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200394913 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.200394913
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.764255375
Short name T726
Test name
Test status
Simulation time 423079530 ps
CPU time 4.43 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 215664 kb
Host smart-8e4df9f1-59a4-4508-942b-f780a5d0e980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764255375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.764255375
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.620895740
Short name T247
Test name
Test status
Simulation time 26201758650 ps
CPU time 161.64 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:25:46 PM PDT 24
Peak memory 219024 kb
Host smart-4efc653b-7e4e-493c-869f-767314b1fd3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620895740 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.620895740
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1848067074
Short name T570
Test name
Test status
Simulation time 43923746 ps
CPU time 1.14 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 219500 kb
Host smart-ff112638-85f4-4617-a4c0-dbb4e48e8cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848067074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1848067074
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3349447067
Short name T680
Test name
Test status
Simulation time 172569744 ps
CPU time 0.9 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:06 PM PDT 24
Peak memory 215220 kb
Host smart-9c4ecbea-069e-4def-bf00-459918191539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349447067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3349447067
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2063102877
Short name T348
Test name
Test status
Simulation time 43168064 ps
CPU time 0.92 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 216284 kb
Host smart-03de757f-3693-4fa4-a024-f7200b96565f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063102877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2063102877
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2287745369
Short name T579
Test name
Test status
Simulation time 170091355 ps
CPU time 1.25 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 219068 kb
Host smart-6d99c81d-a0e7-4b0c-9209-0c011fb54627
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287745369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2287745369
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1469763423
Short name T498
Test name
Test status
Simulation time 21177608 ps
CPU time 1.12 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 218968 kb
Host smart-3de79a97-2d46-4ee4-be98-9605019d5b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469763423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1469763423
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4099273531
Short name T413
Test name
Test status
Simulation time 183959340 ps
CPU time 2.78 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 220180 kb
Host smart-33f4da3c-5e5a-4408-961c-a821001f55fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099273531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4099273531
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.561631590
Short name T961
Test name
Test status
Simulation time 21745964 ps
CPU time 1.13 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 215768 kb
Host smart-0aa02003-7b93-4f7a-aac7-73176aca312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561631590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.561631590
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3494552211
Short name T538
Test name
Test status
Simulation time 31322095 ps
CPU time 0.94 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:06 PM PDT 24
Peak memory 215632 kb
Host smart-e48d1a7d-a910-4b0d-8334-3707dd78820d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494552211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3494552211
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2084871175
Short name T920
Test name
Test status
Simulation time 616235608 ps
CPU time 3.3 seconds
Started Jul 10 07:23:03 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 217768 kb
Host smart-15dce801-5f7a-4b8b-80a8-a26eaaa32c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084871175 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2084871175
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2591920321
Short name T661
Test name
Test status
Simulation time 75854544411 ps
CPU time 397.69 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:29:42 PM PDT 24
Peak memory 219932 kb
Host smart-4813a1f4-26e6-42f9-8d58-a773c3271a3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591920321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2591920321
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3563533974
Short name T155
Test name
Test status
Simulation time 43259729 ps
CPU time 1.26 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:22:00 PM PDT 24
Peak memory 218832 kb
Host smart-8514ce01-b192-4b42-9368-d77746804ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563533974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3563533974
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1814956141
Short name T591
Test name
Test status
Simulation time 51543333 ps
CPU time 0.84 seconds
Started Jul 10 07:21:49 PM PDT 24
Finished Jul 10 07:21:51 PM PDT 24
Peak memory 207120 kb
Host smart-1494c742-60a1-4342-b1ca-5d64a9a2d930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814956141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1814956141
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.224310078
Short name T182
Test name
Test status
Simulation time 17604378 ps
CPU time 0.83 seconds
Started Jul 10 07:21:48 PM PDT 24
Finished Jul 10 07:21:51 PM PDT 24
Peak memory 216660 kb
Host smart-ca862eee-4bb8-40dc-9026-906ef9dbb946
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224310078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.224310078
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1380076156
Short name T568
Test name
Test status
Simulation time 74792686 ps
CPU time 1.07 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 218560 kb
Host smart-abc8f89d-ac1d-4e0e-87ab-cecfc96319d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380076156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1380076156
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2290291078
Short name T786
Test name
Test status
Simulation time 23146409 ps
CPU time 0.91 seconds
Started Jul 10 07:21:49 PM PDT 24
Finished Jul 10 07:21:51 PM PDT 24
Peak memory 219780 kb
Host smart-c26e3881-4e69-4b84-a333-1e41bb046358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290291078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2290291078
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1938261127
Short name T327
Test name
Test status
Simulation time 35660064 ps
CPU time 1.6 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:22:00 PM PDT 24
Peak memory 218832 kb
Host smart-3a18c5cf-00cc-4d61-8dd0-816f11859c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938261127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1938261127
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2164666265
Short name T28
Test name
Test status
Simulation time 22863603 ps
CPU time 1 seconds
Started Jul 10 07:21:51 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 216192 kb
Host smart-6c81acdc-2bed-475c-b1b0-aa9145d5e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164666265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2164666265
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3664057115
Short name T305
Test name
Test status
Simulation time 16073746 ps
CPU time 1 seconds
Started Jul 10 07:21:49 PM PDT 24
Finished Jul 10 07:21:51 PM PDT 24
Peak memory 207428 kb
Host smart-1b747536-a27c-4c02-a87e-04da2246e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664057115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3664057115
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2171971831
Short name T774
Test name
Test status
Simulation time 104871553 ps
CPU time 0.89 seconds
Started Jul 10 07:21:49 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 215452 kb
Host smart-81ea2736-8a47-41f2-af36-2324b9a1154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171971831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2171971831
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.297660585
Short name T364
Test name
Test status
Simulation time 992023259 ps
CPU time 4.49 seconds
Started Jul 10 07:21:47 PM PDT 24
Finished Jul 10 07:21:54 PM PDT 24
Peak memory 217636 kb
Host smart-c4d32ef5-549e-4ad5-aeac-df755de1dc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297660585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.297660585
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.674613572
Short name T846
Test name
Test status
Simulation time 52112795102 ps
CPU time 654.03 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:32:58 PM PDT 24
Peak memory 224016 kb
Host smart-3c4d6444-80d6-4a65-b71c-5007a8d0fbd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674613572 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.674613572
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.783141313
Short name T174
Test name
Test status
Simulation time 22683513 ps
CPU time 1 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:05 PM PDT 24
Peak memory 218856 kb
Host smart-af04d9dd-7418-4662-bfed-8bc483d4cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783141313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.783141313
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2750406093
Short name T960
Test name
Test status
Simulation time 47734671 ps
CPU time 1.58 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 218656 kb
Host smart-625c57cf-da59-4cd1-a42d-35ba05939470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750406093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2750406093
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3063671537
Short name T701
Test name
Test status
Simulation time 88585781 ps
CPU time 1.19 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 216020 kb
Host smart-7fc331ca-b9b5-461d-ad3a-e26da626716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063671537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3063671537
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2711418545
Short name T17
Test name
Test status
Simulation time 28212681 ps
CPU time 1.02 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 224080 kb
Host smart-e177e414-6da8-42ec-8cc5-a6bdf065cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711418545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2711418545
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2558962241
Short name T313
Test name
Test status
Simulation time 32959521 ps
CPU time 1.27 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 218728 kb
Host smart-16978062-d864-4ef1-b7a7-bc7f5ac414f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558962241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2558962241
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1222104159
Short name T619
Test name
Test status
Simulation time 26242007 ps
CPU time 1.26 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:09 PM PDT 24
Peak memory 219088 kb
Host smart-e710fa9b-9e75-40b1-b40c-6bf648e23529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222104159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1222104159
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2319088631
Short name T61
Test name
Test status
Simulation time 35611109 ps
CPU time 1.16 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 229868 kb
Host smart-77ea90b7-4868-4dfc-b70b-9a850227cef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319088631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2319088631
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3719681268
Short name T511
Test name
Test status
Simulation time 86300706 ps
CPU time 1.32 seconds
Started Jul 10 07:23:05 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 219296 kb
Host smart-619b84a4-3a44-4b03-b9df-989deb960a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719681268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3719681268
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3284416643
Short name T150
Test name
Test status
Simulation time 37502317 ps
CPU time 1.13 seconds
Started Jul 10 07:23:04 PM PDT 24
Finished Jul 10 07:23:08 PM PDT 24
Peak memory 219884 kb
Host smart-2cedb4b9-eb88-49dc-a56a-b524fdaba62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284416643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3284416643
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3667933364
Short name T225
Test name
Test status
Simulation time 21553585 ps
CPU time 0.98 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:10 PM PDT 24
Peak memory 218268 kb
Host smart-1d235ff5-7503-408a-8552-891764cc3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667933364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3667933364
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.935613538
Short name T875
Test name
Test status
Simulation time 31391209 ps
CPU time 1.22 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 217708 kb
Host smart-4e608923-b04d-4f38-8c92-fe39d786ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935613538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.935613538
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3466942427
Short name T496
Test name
Test status
Simulation time 44470433 ps
CPU time 1.15 seconds
Started Jul 10 07:23:02 PM PDT 24
Finished Jul 10 07:23:06 PM PDT 24
Peak memory 218932 kb
Host smart-f79d42f9-dbcf-44f6-84e7-904762e04e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466942427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3466942427
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2097552266
Short name T804
Test name
Test status
Simulation time 24118600 ps
CPU time 0.91 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 218784 kb
Host smart-b0eb7de1-7eca-4b11-9436-1455878dbcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097552266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2097552266
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1572082523
Short name T489
Test name
Test status
Simulation time 75027489 ps
CPU time 1.69 seconds
Started Jul 10 07:23:06 PM PDT 24
Finished Jul 10 07:23:11 PM PDT 24
Peak memory 219160 kb
Host smart-95730021-d951-47d2-9e3e-9c38b19ffc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572082523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1572082523
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3162939846
Short name T436
Test name
Test status
Simulation time 68141083 ps
CPU time 1.12 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:16 PM PDT 24
Peak memory 219076 kb
Host smart-35d55b85-6622-4675-ac4c-a0edb8603267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162939846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3162939846
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1288362224
Short name T143
Test name
Test status
Simulation time 48801810 ps
CPU time 1.16 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 229896 kb
Host smart-515ca11a-ccae-4a06-8b38-cf830883704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288362224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1288362224
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3178458900
Short name T792
Test name
Test status
Simulation time 151739343 ps
CPU time 1.01 seconds
Started Jul 10 07:23:03 PM PDT 24
Finished Jul 10 07:23:06 PM PDT 24
Peak memory 217656 kb
Host smart-4b6b154d-a047-4a46-a650-f6f8cf9cab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178458900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3178458900
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.662674447
Short name T604
Test name
Test status
Simulation time 44312080 ps
CPU time 1.2 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 220128 kb
Host smart-6da3b563-cb4a-4135-80f0-16c177be4746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662674447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.662674447
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1865638811
Short name T457
Test name
Test status
Simulation time 27853047 ps
CPU time 0.83 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 218640 kb
Host smart-28e90934-c579-4a63-837d-350f3273a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865638811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1865638811
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3438417731
Short name T887
Test name
Test status
Simulation time 63304575 ps
CPU time 2.3 seconds
Started Jul 10 07:23:12 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 220648 kb
Host smart-5984fad1-9fc3-4d6b-bf2c-1f5d8166280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438417731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3438417731
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.358042612
Short name T194
Test name
Test status
Simulation time 185366566 ps
CPU time 1.2 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 219680 kb
Host smart-47a769a9-1717-4d09-8268-d2c3e0be4231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358042612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.358042612
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.1787488795
Short name T478
Test name
Test status
Simulation time 97476377 ps
CPU time 3.18 seconds
Started Jul 10 07:23:11 PM PDT 24
Finished Jul 10 07:23:18 PM PDT 24
Peak memory 219676 kb
Host smart-7d95e8e3-92d9-463e-b60b-c24ae9fa8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787488795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1787488795
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2943709754
Short name T912
Test name
Test status
Simulation time 64310150 ps
CPU time 1.28 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 220420 kb
Host smart-36557615-5065-4526-bbba-271e6fd0d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943709754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2943709754
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.130671282
Short name T142
Test name
Test status
Simulation time 23302350 ps
CPU time 1.18 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 220152 kb
Host smart-ce4b82ba-45ff-409a-8050-9f787983f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130671282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.130671282
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1887013537
Short name T96
Test name
Test status
Simulation time 42980610 ps
CPU time 1.22 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 217768 kb
Host smart-1901d6e0-344e-46bd-a124-dcd649d9bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887013537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1887013537
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1871540375
Short name T584
Test name
Test status
Simulation time 34594714 ps
CPU time 1.14 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 220472 kb
Host smart-e7dac05f-e02a-4381-935c-7a98cd1ed252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871540375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1871540375
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1249860650
Short name T181
Test name
Test status
Simulation time 20408507 ps
CPU time 1.05 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 218756 kb
Host smart-a6302559-9d0e-4ee1-a8bc-c12b1cad2022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249860650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1249860650
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3102410758
Short name T817
Test name
Test status
Simulation time 338665646 ps
CPU time 1.13 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 217772 kb
Host smart-e9b6018d-bf0e-4c9d-b3d3-12ef8cf91ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102410758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3102410758
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.630710554
Short name T782
Test name
Test status
Simulation time 120121616 ps
CPU time 1.21 seconds
Started Jul 10 07:21:56 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 218884 kb
Host smart-e931de09-eae8-4db2-b030-71b0b1a287b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630710554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.630710554
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3098121190
Short name T787
Test name
Test status
Simulation time 46902068 ps
CPU time 1.2 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:04 PM PDT 24
Peak memory 207236 kb
Host smart-34919223-9f65-401d-8cb8-2040137de598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098121190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3098121190
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1915403281
Short name T658
Test name
Test status
Simulation time 40091845 ps
CPU time 1.1 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 218920 kb
Host smart-86b7a1ff-2e0c-4c03-bbdf-2021e45e91af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915403281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1915403281
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.963322152
Short name T851
Test name
Test status
Simulation time 36314527 ps
CPU time 1.05 seconds
Started Jul 10 07:21:56 PM PDT 24
Finished Jul 10 07:21:58 PM PDT 24
Peak memory 220084 kb
Host smart-59f6ef0b-a1e2-42dc-a631-c5920e538931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963322152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.963322152
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2272969497
Short name T673
Test name
Test status
Simulation time 46416943 ps
CPU time 1.59 seconds
Started Jul 10 07:21:50 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 220072 kb
Host smart-f1314cf2-3161-4e26-85af-9c77bf140a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272969497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2272969497
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.917231466
Short name T966
Test name
Test status
Simulation time 21507642 ps
CPU time 1.17 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 215728 kb
Host smart-9689b2f4-859f-42aa-97f8-c07fbdddcf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917231466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.917231466
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.537723163
Short name T880
Test name
Test status
Simulation time 16377654 ps
CPU time 1 seconds
Started Jul 10 07:21:48 PM PDT 24
Finished Jul 10 07:21:51 PM PDT 24
Peak memory 207428 kb
Host smart-ea3ed38a-9c95-49de-b51e-5894ea423210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537723163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.537723163
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1164262471
Short name T698
Test name
Test status
Simulation time 16390937 ps
CPU time 1 seconds
Started Jul 10 07:21:50 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 215652 kb
Host smart-ad24679e-1142-44c4-af07-3726f7d462dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164262471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1164262471
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.446407284
Short name T69
Test name
Test status
Simulation time 63503810 ps
CPU time 1.31 seconds
Started Jul 10 07:21:49 PM PDT 24
Finished Jul 10 07:21:52 PM PDT 24
Peak memory 215636 kb
Host smart-1a7968e1-eca8-46e8-8d90-582162b1da74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446407284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.446407284
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1170269163
Short name T238
Test name
Test status
Simulation time 196237515130 ps
CPU time 712.99 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:33:59 PM PDT 24
Peak memory 221460 kb
Host smart-de780a7d-16e6-4bad-ac5b-693a02ab640e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170269163 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1170269163
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3490718367
Short name T116
Test name
Test status
Simulation time 26471968 ps
CPU time 1.22 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 219572 kb
Host smart-a10b3627-bba7-4952-814d-06ad9815ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490718367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3490718367
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2927480042
Short name T763
Test name
Test status
Simulation time 28139160 ps
CPU time 0.86 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 218492 kb
Host smart-ccafa573-f6b1-4226-aafd-f5ffb447117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927480042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2927480042
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.742896844
Short name T889
Test name
Test status
Simulation time 77594494 ps
CPU time 1.18 seconds
Started Jul 10 07:23:12 PM PDT 24
Finished Jul 10 07:23:16 PM PDT 24
Peak memory 219676 kb
Host smart-ea426619-cc0c-4546-bc48-4fa4483955a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742896844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.742896844
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1167252890
Short name T32
Test name
Test status
Simulation time 90319448 ps
CPU time 1.2 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 220040 kb
Host smart-7bcb3794-3181-49f6-9c6b-1a99490ae8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167252890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1167252890
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2859737997
Short name T7
Test name
Test status
Simulation time 20325767 ps
CPU time 1.12 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 220180 kb
Host smart-a776fef9-4b80-4b3a-ac35-6f7b1e74eecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859737997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2859737997
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3905019576
Short name T56
Test name
Test status
Simulation time 193512725 ps
CPU time 1.29 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 217668 kb
Host smart-1908adc4-232f-41c8-8329-41293647dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905019576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3905019576
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.659681386
Short name T957
Test name
Test status
Simulation time 71174934 ps
CPU time 1.12 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:28 PM PDT 24
Peak memory 219852 kb
Host smart-5bdce1e7-fc97-46c7-8744-fa123e19aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659681386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.659681386
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2079445023
Short name T968
Test name
Test status
Simulation time 97578238 ps
CPU time 1.2 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 225596 kb
Host smart-8b4da2ac-62fd-45ec-b630-912ba00cbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079445023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2079445023
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1144061548
Short name T674
Test name
Test status
Simulation time 50274244 ps
CPU time 1.2 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:12 PM PDT 24
Peak memory 215716 kb
Host smart-beac5557-cf38-479f-9fb2-d91796255715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144061548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1144061548
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1435822436
Short name T545
Test name
Test status
Simulation time 42900498 ps
CPU time 1.14 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 220004 kb
Host smart-c22847b3-2030-4091-8b6b-9393e65fc6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435822436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1435822436
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2533997839
Short name T932
Test name
Test status
Simulation time 18074436 ps
CPU time 1.16 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 224252 kb
Host smart-acb5ee99-4522-4a78-bede-3996732c6a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533997839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2533997839
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1890050871
Short name T657
Test name
Test status
Simulation time 209309016 ps
CPU time 1.19 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 217592 kb
Host smart-99230bf9-a670-4f86-81f0-002b73bf21a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890050871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1890050871
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3684110049
Short name T34
Test name
Test status
Simulation time 25079520 ps
CPU time 1.25 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 221348 kb
Host smart-b3e962db-ef8b-49ff-81ad-aa91122b2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684110049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3684110049
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1028684157
Short name T973
Test name
Test status
Simulation time 38292283 ps
CPU time 0.82 seconds
Started Jul 10 07:23:12 PM PDT 24
Finished Jul 10 07:23:16 PM PDT 24
Peak memory 218408 kb
Host smart-f19f9d96-4080-4472-8adb-163f377e4cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028684157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1028684157
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2537229881
Short name T595
Test name
Test status
Simulation time 75483819 ps
CPU time 1.62 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:28 PM PDT 24
Peak memory 219008 kb
Host smart-8667f0be-490c-4b0d-be09-ec9ae5b2e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537229881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2537229881
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3196750737
Short name T252
Test name
Test status
Simulation time 33476048 ps
CPU time 1.19 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 220892 kb
Host smart-08f2e531-11ac-42b0-83d9-4f65641526cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196750737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3196750737
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2264374671
Short name T60
Test name
Test status
Simulation time 19090392 ps
CPU time 1.15 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 224284 kb
Host smart-389d4533-6534-4d2c-9325-d8abec42c52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264374671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2264374671
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1514285641
Short name T757
Test name
Test status
Simulation time 56544855 ps
CPU time 1.25 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 217536 kb
Host smart-5a3f9c3a-e245-4c4b-9027-17530fab4d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514285641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1514285641
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4089276833
Short name T537
Test name
Test status
Simulation time 77527730 ps
CPU time 1.22 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 218884 kb
Host smart-506c9883-e6f1-4f23-bdea-e49ba82d7f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089276833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4089276833
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2241169151
Short name T593
Test name
Test status
Simulation time 34004129 ps
CPU time 0.9 seconds
Started Jul 10 07:23:07 PM PDT 24
Finished Jul 10 07:23:12 PM PDT 24
Peak memory 218792 kb
Host smart-eb26de7e-d101-4a03-abfc-ec8050ff6764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241169151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2241169151
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1096068893
Short name T578
Test name
Test status
Simulation time 37859298 ps
CPU time 1.33 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 217608 kb
Host smart-72d91093-3b98-471a-805c-26c98b3e6720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096068893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1096068893
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.410289511
Short name T793
Test name
Test status
Simulation time 31318094 ps
CPU time 1.15 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 220272 kb
Host smart-85a1c18b-2bee-4990-9259-e2fc08423b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410289511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.410289511
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.4104604355
Short name T986
Test name
Test status
Simulation time 20498021 ps
CPU time 1.15 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 224296 kb
Host smart-e72091d8-4a91-4edd-985d-37df2965ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104604355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4104604355
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1397483781
Short name T938
Test name
Test status
Simulation time 88786419 ps
CPU time 1.15 seconds
Started Jul 10 07:23:11 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 217616 kb
Host smart-4e61336b-4357-4fc3-8682-44954ad106cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397483781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1397483781
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3526725210
Short name T232
Test name
Test status
Simulation time 24124666 ps
CPU time 1.26 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 219048 kb
Host smart-30eb2e1a-d0fe-4652-b472-f0a2b42ec9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526725210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3526725210
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1047004146
Short name T154
Test name
Test status
Simulation time 19797755 ps
CPU time 1.15 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 224268 kb
Host smart-221d5a63-d2bf-473a-914f-8088662dae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047004146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1047004146
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1168316875
Short name T766
Test name
Test status
Simulation time 191808442 ps
CPU time 2.76 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 219680 kb
Host smart-27a0be44-ab66-4489-b9b4-8adb06aab4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168316875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1168316875
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3196210806
Short name T180
Test name
Test status
Simulation time 77080567 ps
CPU time 1.16 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 220144 kb
Host smart-feb29960-54b0-483d-aeae-138a6d21e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196210806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3196210806
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3033512217
Short name T840
Test name
Test status
Simulation time 73996663 ps
CPU time 1.32 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 225324 kb
Host smart-c772c4ac-6a96-45b4-a589-f67e3fff4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033512217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3033512217
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4170582458
Short name T761
Test name
Test status
Simulation time 63942897 ps
CPU time 1.8 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 218696 kb
Host smart-d3d1853b-0ca0-49d3-8c4d-aa8b4cccbd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170582458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4170582458
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1935498288
Short name T924
Test name
Test status
Simulation time 41196579 ps
CPU time 1.15 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 220180 kb
Host smart-950e084d-20cc-4a18-83e4-4203cbc3e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935498288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1935498288
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2436934839
Short name T82
Test name
Test status
Simulation time 21999119 ps
CPU time 1.04 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215212 kb
Host smart-ae675236-828d-466a-811e-38e8d9dd8461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436934839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2436934839
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1640454954
Short name T227
Test name
Test status
Simulation time 14991753 ps
CPU time 0.95 seconds
Started Jul 10 07:21:56 PM PDT 24
Finished Jul 10 07:21:58 PM PDT 24
Peak memory 216784 kb
Host smart-b2e4eae8-695b-43ff-b626-d48fcfb6c078
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640454954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1640454954
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2443278118
Short name T759
Test name
Test status
Simulation time 37485730 ps
CPU time 1.06 seconds
Started Jul 10 07:21:55 PM PDT 24
Finished Jul 10 07:21:57 PM PDT 24
Peak memory 220284 kb
Host smart-118958f1-39ba-4890-8970-c3fd6d6a04c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443278118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2443278118
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3368330170
Short name T791
Test name
Test status
Simulation time 24307732 ps
CPU time 0.96 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 218876 kb
Host smart-e2a8aef9-de74-4b77-9141-4afd82782531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368330170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3368330170
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.3148836653
Short name T608
Test name
Test status
Simulation time 36949406 ps
CPU time 0.93 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 215688 kb
Host smart-36e4ab98-e564-48df-b012-6f7b3771b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148836653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3148836653
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1290661387
Short name T735
Test name
Test status
Simulation time 19661831 ps
CPU time 1.01 seconds
Started Jul 10 07:21:56 PM PDT 24
Finished Jul 10 07:21:57 PM PDT 24
Peak memory 207440 kb
Host smart-33086d14-1322-497f-84b4-cddb9c6dfe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290661387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1290661387
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1221132826
Short name T881
Test name
Test status
Simulation time 44486798 ps
CPU time 0.89 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215632 kb
Host smart-0ea9f83e-f955-4814-b76f-0119b9301d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221132826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1221132826
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3462913044
Short name T714
Test name
Test status
Simulation time 101134317 ps
CPU time 1.33 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 218824 kb
Host smart-982b3b52-a5c1-4fbb-b908-ed0e102ae13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462913044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3462913044
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1227833861
Short name T946
Test name
Test status
Simulation time 123968689517 ps
CPU time 1314.02 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:43:56 PM PDT 24
Peak memory 226024 kb
Host smart-80e7614e-008e-4bec-8231-6599778e6e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227833861 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1227833861
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2411598946
Short name T877
Test name
Test status
Simulation time 34703683 ps
CPU time 1.14 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 219516 kb
Host smart-6f0cbb30-bfbc-4f89-ad80-f77e9a41ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411598946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2411598946
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1459428296
Short name T207
Test name
Test status
Simulation time 22398119 ps
CPU time 0.95 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 219832 kb
Host smart-eca845c8-425d-416a-9e62-9c1732aa8481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459428296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1459428296
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3109321579
Short name T717
Test name
Test status
Simulation time 59236020 ps
CPU time 1.82 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 215828 kb
Host smart-4d3f3f39-3e1a-490d-bb6b-fd51573da631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109321579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3109321579
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2917881279
Short name T677
Test name
Test status
Simulation time 45512984 ps
CPU time 1.31 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 220584 kb
Host smart-c0e75e6a-5963-4f3c-8a84-57858a36f55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917881279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2917881279
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3943086435
Short name T186
Test name
Test status
Simulation time 36130345 ps
CPU time 0.87 seconds
Started Jul 10 07:23:15 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 218648 kb
Host smart-f5522cad-b35e-47a3-a5f6-827aa7990065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943086435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3943086435
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1394606400
Short name T922
Test name
Test status
Simulation time 26691720 ps
CPU time 1.18 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 218924 kb
Host smart-542a5ba2-3aca-49e6-98b2-55d863190824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394606400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1394606400
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1225567729
Short name T803
Test name
Test status
Simulation time 43967078 ps
CPU time 1.21 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:16 PM PDT 24
Peak memory 219932 kb
Host smart-7d37be2f-cbb4-4ca0-a131-8be38844cede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225567729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1225567729
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3167360186
Short name T195
Test name
Test status
Simulation time 18695123 ps
CPU time 1.04 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 218996 kb
Host smart-c3a8591d-f109-445f-9718-a41f0a0a33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167360186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3167360186
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2896249703
Short name T914
Test name
Test status
Simulation time 51314687 ps
CPU time 1.83 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:16 PM PDT 24
Peak memory 218624 kb
Host smart-e0edeaa4-9ea5-470f-a7e9-fcb77d1b47e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896249703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2896249703
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2586134362
Short name T808
Test name
Test status
Simulation time 60141754 ps
CPU time 1.11 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220048 kb
Host smart-c8d7c1be-d89a-4f27-aecb-d497c4ddcc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586134362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2586134362
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.582310776
Short name T830
Test name
Test status
Simulation time 50568283 ps
CPU time 0.86 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 218624 kb
Host smart-911751bf-71dd-41b9-baa6-eab3a4b91170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582310776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.582310776
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.105122021
Short name T951
Test name
Test status
Simulation time 122899843 ps
CPU time 1.11 seconds
Started Jul 10 07:23:08 PM PDT 24
Finished Jul 10 07:23:13 PM PDT 24
Peak memory 217620 kb
Host smart-c529e675-1a43-4de8-bd45-0a6299f36c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105122021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.105122021
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2720624994
Short name T505
Test name
Test status
Simulation time 66662492 ps
CPU time 1.22 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 219868 kb
Host smart-32395f5d-9192-4656-b546-5200811a4172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720624994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2720624994
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.752248217
Short name T820
Test name
Test status
Simulation time 51061801 ps
CPU time 0.88 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 218848 kb
Host smart-96cf7b13-8a3b-411d-a087-da14d5b1fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752248217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.752248217
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2016848347
Short name T443
Test name
Test status
Simulation time 34566397 ps
CPU time 1.33 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 219020 kb
Host smart-6617eddf-5fba-454c-8d1b-072b79e30923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016848347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2016848347
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1774448099
Short name T809
Test name
Test status
Simulation time 74507317 ps
CPU time 1.07 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 218468 kb
Host smart-929858e8-7789-4363-b804-7d7890659976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774448099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1774448099
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1148801202
Short name T750
Test name
Test status
Simulation time 47503675 ps
CPU time 0.88 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 220032 kb
Host smart-849b646c-31d4-4b48-90c9-5e8b5c781e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148801202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1148801202
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2315424066
Short name T385
Test name
Test status
Simulation time 64816353 ps
CPU time 1.06 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 217760 kb
Host smart-f605b3ca-c8fa-47e3-be6e-a494018b94bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315424066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2315424066
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2741331372
Short name T504
Test name
Test status
Simulation time 75997971 ps
CPU time 1.18 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 219744 kb
Host smart-d70bebf5-304d-47e8-ab67-26633a2ada0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741331372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2741331372
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2660107750
Short name T125
Test name
Test status
Simulation time 35919094 ps
CPU time 0.94 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 219724 kb
Host smart-8e2b8094-3489-436f-8013-1b20364b0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660107750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2660107750
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.870204565
Short name T74
Test name
Test status
Simulation time 31949933 ps
CPU time 1.26 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 219116 kb
Host smart-c2e93f56-f473-4485-a060-5fb04e3fa2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870204565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.870204565
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.534709694
Short name T956
Test name
Test status
Simulation time 81399859 ps
CPU time 1.07 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 218760 kb
Host smart-33a4c238-816b-463d-9be4-6fe286487b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534709694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.534709694
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2221550659
Short name T8
Test name
Test status
Simulation time 23919268 ps
CPU time 1.18 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 219920 kb
Host smart-f5f26d0f-050d-46ec-aef9-67ee5dd6cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221550659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2221550659
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3602913529
Short name T883
Test name
Test status
Simulation time 122703951 ps
CPU time 1.14 seconds
Started Jul 10 07:23:09 PM PDT 24
Finished Jul 10 07:23:14 PM PDT 24
Peak memory 217660 kb
Host smart-fb48335a-4d5f-48a4-88d7-6fbd9e978643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602913529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3602913529
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.134114063
Short name T201
Test name
Test status
Simulation time 25004465 ps
CPU time 1.31 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 220096 kb
Host smart-ff27e3c7-01b3-4ec3-8b7f-fc594769a851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134114063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.134114063
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2630055488
Short name T551
Test name
Test status
Simulation time 37580880 ps
CPU time 1.44 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 225836 kb
Host smart-e52f682b-1459-4d46-bdda-68d04ca3b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630055488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2630055488
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1316785800
Short name T778
Test name
Test status
Simulation time 37451532 ps
CPU time 1.34 seconds
Started Jul 10 07:23:10 PM PDT 24
Finished Jul 10 07:23:15 PM PDT 24
Peak memory 218728 kb
Host smart-95cacb34-a558-4095-b05e-581385d4283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316785800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1316785800
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3469522566
Short name T818
Test name
Test status
Simulation time 101433783 ps
CPU time 1.24 seconds
Started Jul 10 07:23:13 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 220540 kb
Host smart-8e9b3171-1c3f-4acb-b283-8ef1e97abca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469522566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3469522566
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2338049143
Short name T730
Test name
Test status
Simulation time 25200407 ps
CPU time 1.04 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 224088 kb
Host smart-387a1a06-491a-4a00-9b65-ddb253717760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338049143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2338049143
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3051994508
Short name T936
Test name
Test status
Simulation time 91627352 ps
CPU time 1.41 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 217720 kb
Host smart-6f484001-82e8-458a-bb6e-bbf313563acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051994508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3051994508
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1138799728
Short name T771
Test name
Test status
Simulation time 37276154 ps
CPU time 1.04 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 220020 kb
Host smart-00663e0c-952c-4258-981e-3196e576de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138799728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1138799728
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1585289206
Short name T679
Test name
Test status
Simulation time 14570047 ps
CPU time 0.92 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 207000 kb
Host smart-7bcac6cb-0f6e-432f-8474-c9aee251fae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585289206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1585289206
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1966684192
Short name T603
Test name
Test status
Simulation time 12643750 ps
CPU time 0.91 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 216824 kb
Host smart-bf5e9448-8ee2-4682-b9d1-3e900fc65c08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966684192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1966684192
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.136749918
Short name T463
Test name
Test status
Simulation time 93229324 ps
CPU time 1.12 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 217216 kb
Host smart-cc691f1e-7653-4581-a026-7d93915e8f16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136749918 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.136749918
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3466726720
Short name T196
Test name
Test status
Simulation time 19526876 ps
CPU time 1.25 seconds
Started Jul 10 07:22:04 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 224244 kb
Host smart-4eb6ddcf-c9f7-48f6-879e-e5adcfc223d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466726720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3466726720
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.358903890
Short name T441
Test name
Test status
Simulation time 106628910 ps
CPU time 1.52 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 218808 kb
Host smart-f11ff09e-8782-4046-af5a-c56e8aa0f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358903890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.358903890
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1612410911
Short name T46
Test name
Test status
Simulation time 22508690 ps
CPU time 0.94 seconds
Started Jul 10 07:22:03 PM PDT 24
Finished Jul 10 07:22:08 PM PDT 24
Peak memory 216188 kb
Host smart-9e13f3e3-c1e7-40f9-9352-3465ae7d7ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612410911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1612410911
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1638833124
Short name T40
Test name
Test status
Simulation time 28851432 ps
CPU time 1.06 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 207436 kb
Host smart-15134ab3-78f3-4f3d-9fe5-0e4020d9ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638833124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1638833124
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1003807701
Short name T729
Test name
Test status
Simulation time 35376272 ps
CPU time 0.96 seconds
Started Jul 10 07:22:00 PM PDT 24
Finished Jul 10 07:22:05 PM PDT 24
Peak memory 215592 kb
Host smart-acbfd689-3363-48b1-a7ff-cdcf7d8e5032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003807701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1003807701
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4266479619
Short name T1
Test name
Test status
Simulation time 75998404 ps
CPU time 1.15 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:21:59 PM PDT 24
Peak memory 215612 kb
Host smart-9e8652b6-7040-4b70-b1c3-51d08164e2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266479619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4266479619
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1539799635
Short name T931
Test name
Test status
Simulation time 393969471124 ps
CPU time 1264.14 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:43:04 PM PDT 24
Peak memory 223644 kb
Host smart-b2b9ca66-d382-4e75-a495-03c290b3d54c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539799635 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1539799635
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3423320317
Short name T683
Test name
Test status
Simulation time 84609006 ps
CPU time 1.26 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 220040 kb
Host smart-eef0a013-3702-4913-8a86-f1c8b32358c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423320317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3423320317
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.965616540
Short name T224
Test name
Test status
Simulation time 44754884 ps
CPU time 1.16 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 215724 kb
Host smart-368cc1eb-0786-4c25-9648-ca9583b6439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965616540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.965616540
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.613426913
Short name T402
Test name
Test status
Simulation time 55725865 ps
CPU time 1.08 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 218844 kb
Host smart-f45e5ad8-1111-4db8-878a-d023dc339b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613426913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.613426913
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1845913257
Short name T629
Test name
Test status
Simulation time 125277034 ps
CPU time 1.21 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 220552 kb
Host smart-a750c61c-1e16-4917-bb5a-007d04fa623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845913257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1845913257
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.974473283
Short name T15
Test name
Test status
Simulation time 23218146 ps
CPU time 1.1 seconds
Started Jul 10 07:23:26 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 224292 kb
Host smart-0722d521-8f16-456d-bceb-94ced4898780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974473283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.974473283
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1892259935
Short name T338
Test name
Test status
Simulation time 35759657 ps
CPU time 1.46 seconds
Started Jul 10 07:23:15 PM PDT 24
Finished Jul 10 07:23:18 PM PDT 24
Peak memory 217928 kb
Host smart-df7b06c2-f88e-448f-a0cf-82c945fa8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892259935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1892259935
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4125222457
Short name T421
Test name
Test status
Simulation time 85629489 ps
CPU time 1.15 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 220040 kb
Host smart-73b8fc2e-723d-4654-a453-6966601d75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125222457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4125222457
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1793882487
Short name T640
Test name
Test status
Simulation time 18222062 ps
CPU time 1.02 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 218612 kb
Host smart-84f73142-9db9-44dd-8c14-2e49425205fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793882487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1793882487
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3826124125
Short name T573
Test name
Test status
Simulation time 83299877 ps
CPU time 1.24 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 217700 kb
Host smart-32ed0fe8-566a-4e55-b28c-63e7c35be6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826124125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3826124125
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2812638211
Short name T141
Test name
Test status
Simulation time 107917701 ps
CPU time 1.31 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 216192 kb
Host smart-58f4605d-e4ee-48ae-a07b-9e81efd3b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812638211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2812638211
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3846982619
Short name T219
Test name
Test status
Simulation time 41736219 ps
CPU time 1.41 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 225996 kb
Host smart-64df434b-9967-46c7-8bed-f0e2143f7329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846982619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3846982619
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2770483641
Short name T772
Test name
Test status
Simulation time 81975653 ps
CPU time 1.16 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 217560 kb
Host smart-badc79c3-00a8-4e0c-90e3-0a511e881f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770483641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2770483641
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3315640243
Short name T529
Test name
Test status
Simulation time 104152305 ps
CPU time 1.25 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 216024 kb
Host smart-9543aa1f-83cb-40b4-9e7f-ddf523fab32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315640243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3315640243
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1075255013
Short name T175
Test name
Test status
Simulation time 34016795 ps
CPU time 0.84 seconds
Started Jul 10 07:23:15 PM PDT 24
Finished Jul 10 07:23:18 PM PDT 24
Peak memory 218528 kb
Host smart-cab9ac12-5eb6-4bec-acf8-d596ac9d3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075255013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1075255013
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2579252172
Short name T50
Test name
Test status
Simulation time 320249227 ps
CPU time 1.99 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 219384 kb
Host smart-d1160773-0f5c-44b6-9d63-13af74b6fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579252172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2579252172
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1134712162
Short name T301
Test name
Test status
Simulation time 27022900 ps
CPU time 1.24 seconds
Started Jul 10 07:23:15 PM PDT 24
Finished Jul 10 07:23:18 PM PDT 24
Peak memory 219968 kb
Host smart-1cac7f5a-2133-44f0-86ee-96b6e92ffeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134712162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1134712162
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3034173964
Short name T208
Test name
Test status
Simulation time 26519272 ps
CPU time 1.01 seconds
Started Jul 10 07:23:26 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 220084 kb
Host smart-5d7c5e1d-4fa0-41aa-9d8d-c302e6efac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034173964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3034173964
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3541937322
Short name T607
Test name
Test status
Simulation time 73691691 ps
CPU time 1.09 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 219476 kb
Host smart-8a1d00a7-cb9e-424b-a41f-7fed184868ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541937322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3541937322
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2349718560
Short name T921
Test name
Test status
Simulation time 28751407 ps
CPU time 1.23 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:21 PM PDT 24
Peak memory 218828 kb
Host smart-46b6b4c1-b365-47e9-a33d-6580edd3774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349718560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2349718560
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1153477253
Short name T378
Test name
Test status
Simulation time 18929663 ps
CPU time 1.09 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 218816 kb
Host smart-27ff4938-1a70-4f44-93a8-9ec46cc33d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153477253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1153477253
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3616946970
Short name T660
Test name
Test status
Simulation time 85362965 ps
CPU time 1.39 seconds
Started Jul 10 07:23:21 PM PDT 24
Finished Jul 10 07:23:28 PM PDT 24
Peak memory 219160 kb
Host smart-434701d0-20bd-4b73-b436-c8c79a0a6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616946970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3616946970
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.205066407
Short name T819
Test name
Test status
Simulation time 76928933 ps
CPU time 1.15 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 219128 kb
Host smart-82c4f22e-1e07-48f8-9937-e642a4562d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205066407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.205066407
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2360623393
Short name T88
Test name
Test status
Simulation time 54623119 ps
CPU time 0.84 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 218476 kb
Host smart-66751690-130a-4940-866a-84c40e36592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360623393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2360623393
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1477561543
Short name T905
Test name
Test status
Simulation time 86892073 ps
CPU time 1.47 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 218936 kb
Host smart-5de02871-e533-4b63-b39e-0eed98841a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477561543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1477561543
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1428697473
Short name T590
Test name
Test status
Simulation time 64055692 ps
CPU time 1.11 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 220020 kb
Host smart-a1f724e0-2397-4e6c-9a5b-8887633aa88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428697473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1428697473
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.966196994
Short name T954
Test name
Test status
Simulation time 22320026 ps
CPU time 0.9 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 218832 kb
Host smart-04690045-bc3c-4ef9-86bb-b0534f0a96ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966196994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.966196994
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2852226667
Short name T52
Test name
Test status
Simulation time 77102818 ps
CPU time 1.33 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 217580 kb
Host smart-ddb0db5e-b9e7-4a06-84d9-1e802b94b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852226667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2852226667
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.16511642
Short name T785
Test name
Test status
Simulation time 27341367 ps
CPU time 1.25 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 220288 kb
Host smart-abb338a8-0214-48b0-9ae2-b622911ac0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16511642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.16511642
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2309914181
Short name T62
Test name
Test status
Simulation time 20636494 ps
CPU time 1.09 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 224320 kb
Host smart-c3df68fe-9a9a-4ec7-a7a1-5ad717ee5544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309914181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2309914181
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2363158034
Short name T780
Test name
Test status
Simulation time 258843520 ps
CPU time 3.62 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 217812 kb
Host smart-90f06e1e-4e9e-4130-a14d-2500412688cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363158034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2363158034
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3864142000
Short name T713
Test name
Test status
Simulation time 39599143 ps
CPU time 1.23 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 219624 kb
Host smart-5b7e48bd-1d13-4c58-bd78-67e641bcd633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864142000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3864142000
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1365334667
Short name T351
Test name
Test status
Simulation time 22806900 ps
CPU time 0.82 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 207128 kb
Host smart-d177f286-ed3e-4d44-a388-30ade767cb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365334667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1365334667
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.905031344
Short name T231
Test name
Test status
Simulation time 11295503 ps
CPU time 0.92 seconds
Started Jul 10 07:22:05 PM PDT 24
Finished Jul 10 07:22:09 PM PDT 24
Peak memory 215696 kb
Host smart-a16bf2ea-29ca-4b9d-b289-c85cda5639bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905031344 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.905031344
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.64854139
Short name T737
Test name
Test status
Simulation time 36776100 ps
CPU time 1.29 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 217044 kb
Host smart-eeaa1df2-b08a-4940-b164-f7145ed9c82f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64854139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disa
ble_auto_req_mode.64854139
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1973420017
Short name T144
Test name
Test status
Simulation time 54642106 ps
CPU time 1.12 seconds
Started Jul 10 07:21:58 PM PDT 24
Finished Jul 10 07:22:01 PM PDT 24
Peak memory 230088 kb
Host smart-f0cfce3e-6a57-4342-a0c8-138861a509b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973420017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1973420017
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.61359899
Short name T512
Test name
Test status
Simulation time 45060087 ps
CPU time 1.26 seconds
Started Jul 10 07:21:59 PM PDT 24
Finished Jul 10 07:22:03 PM PDT 24
Peak memory 219284 kb
Host smart-a87824ac-cfd9-4ab5-ba82-e9b1aee0f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61359899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.61359899
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3251592676
Short name T858
Test name
Test status
Simulation time 25257914 ps
CPU time 0.91 seconds
Started Jul 10 07:22:08 PM PDT 24
Finished Jul 10 07:22:14 PM PDT 24
Peak memory 215880 kb
Host smart-7f3b85a3-d99a-4951-90c4-d9b516a53710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251592676 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3251592676
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2122891827
Short name T250
Test name
Test status
Simulation time 16060353 ps
CPU time 1.04 seconds
Started Jul 10 07:22:02 PM PDT 24
Finished Jul 10 07:22:07 PM PDT 24
Peak memory 207416 kb
Host smart-286fb2d4-7636-481e-ae03-1f19e969c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122891827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2122891827
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2221718869
Short name T854
Test name
Test status
Simulation time 84002004 ps
CPU time 0.94 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:06 PM PDT 24
Peak memory 215724 kb
Host smart-6d1be63e-afe9-4daa-8ed1-4396f2685e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221718869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2221718869
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.808270952
Short name T919
Test name
Test status
Simulation time 1196298128 ps
CPU time 4.89 seconds
Started Jul 10 07:22:01 PM PDT 24
Finished Jul 10 07:22:10 PM PDT 24
Peak memory 217820 kb
Host smart-00c5ea7e-7a94-4231-a0ff-cc02c87b07a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808270952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.808270952
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2200551872
Short name T823
Test name
Test status
Simulation time 55104291394 ps
CPU time 1242.36 seconds
Started Jul 10 07:21:57 PM PDT 24
Finished Jul 10 07:42:41 PM PDT 24
Peak memory 224032 kb
Host smart-ea2bde4a-017b-42db-95c7-aea1a175032b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200551872 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2200551872
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.4004105224
Short name T864
Test name
Test status
Simulation time 21001964 ps
CPU time 1.09 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:25 PM PDT 24
Peak memory 219088 kb
Host smart-2f7ca65b-c87b-4959-bc8a-646329342e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004105224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.4004105224
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2873126927
Short name T983
Test name
Test status
Simulation time 35097724 ps
CPU time 0.9 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 219708 kb
Host smart-6a4babb7-b83d-4afc-996e-fa46d3586b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873126927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2873126927
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.100914264
Short name T615
Test name
Test status
Simulation time 259597038 ps
CPU time 3.8 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 220428 kb
Host smart-f26dbb86-9485-48c0-9216-ba4c9120304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100914264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.100914264
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.962630785
Short name T632
Test name
Test status
Simulation time 32570718 ps
CPU time 1.19 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 219780 kb
Host smart-5a83ca5e-b184-4a5d-acb3-b5e96c3eff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962630785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.962630785
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2361652741
Short name T135
Test name
Test status
Simulation time 40660688 ps
CPU time 0.96 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220032 kb
Host smart-0676dd6b-5462-48e2-a5de-d0f8cc9e0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361652741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2361652741
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.611030074
Short name T557
Test name
Test status
Simulation time 61771169 ps
CPU time 1.35 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 218852 kb
Host smart-623ac374-e1f7-4b22-bc7d-9b3c6d78ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611030074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.611030074
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1843241407
Short name T255
Test name
Test status
Simulation time 84124090 ps
CPU time 1.17 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 219088 kb
Host smart-07738e52-e6ef-4ad1-8629-eb7f640af701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843241407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1843241407
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.324074159
Short name T44
Test name
Test status
Simulation time 19161941 ps
CPU time 1.06 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 218864 kb
Host smart-9357674f-8c4e-47a2-bccb-06ff2972da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324074159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.324074159
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3205752106
Short name T530
Test name
Test status
Simulation time 35107925 ps
CPU time 1.43 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 220696 kb
Host smart-19e4ac2a-6c9c-44aa-a331-af335130aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205752106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3205752106
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.911244306
Short name T978
Test name
Test status
Simulation time 28482948 ps
CPU time 1.34 seconds
Started Jul 10 07:23:14 PM PDT 24
Finished Jul 10 07:23:17 PM PDT 24
Peak memory 219496 kb
Host smart-ea068df9-9139-44f2-81b6-c2d30fddd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911244306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.911244306
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3488913515
Short name T585
Test name
Test status
Simulation time 43266995 ps
CPU time 1.23 seconds
Started Jul 10 07:23:16 PM PDT 24
Finished Jul 10 07:23:19 PM PDT 24
Peak memory 225880 kb
Host smart-5ab79fb7-62db-46a0-8393-0a332562b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488913515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3488913515
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.462005448
Short name T900
Test name
Test status
Simulation time 238207165 ps
CPU time 3.33 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220660 kb
Host smart-46b09e96-b3c2-4a52-b054-f2c229d56f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462005448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.462005448
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.677820105
Short name T532
Test name
Test status
Simulation time 70000961 ps
CPU time 1.15 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220764 kb
Host smart-28024d1a-99bf-4a59-9784-2cadf2a320c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677820105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.677820105
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3053308546
Short name T746
Test name
Test status
Simulation time 51139527 ps
CPU time 0.86 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 218716 kb
Host smart-1fd66a08-cd9e-479e-8523-e4851bd245ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053308546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3053308546
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.139185415
Short name T406
Test name
Test status
Simulation time 39558746 ps
CPU time 1.55 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 218656 kb
Host smart-9b3ff110-7327-409c-8dcd-f4e400e4e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139185415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.139185415
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.860956626
Short name T776
Test name
Test status
Simulation time 35462749 ps
CPU time 1.15 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 219756 kb
Host smart-c1860188-8869-4ad0-a267-d7e465fb837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860956626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.860956626
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2659102612
Short name T59
Test name
Test status
Simulation time 76084354 ps
CPU time 0.95 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 224120 kb
Host smart-836f1854-b803-47f6-abdd-6b1c4e354a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659102612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2659102612
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.844115258
Short name T813
Test name
Test status
Simulation time 32427318 ps
CPU time 1.29 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 217704 kb
Host smart-2b816a55-37fd-4316-9c02-43e285351983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844115258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.844115258
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1966845410
Short name T756
Test name
Test status
Simulation time 81853707 ps
CPU time 1.23 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220696 kb
Host smart-c4e016ae-0822-4d9d-ac17-b445b2a06626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966845410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1966845410
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1826752169
Short name T163
Test name
Test status
Simulation time 51862964 ps
CPU time 1 seconds
Started Jul 10 07:23:19 PM PDT 24
Finished Jul 10 07:23:24 PM PDT 24
Peak memory 220140 kb
Host smart-c467c9ff-92dc-427a-be24-54f88f0a7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826752169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1826752169
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4038651056
Short name T374
Test name
Test status
Simulation time 41207698 ps
CPU time 1.28 seconds
Started Jul 10 07:23:26 PM PDT 24
Finished Jul 10 07:23:31 PM PDT 24
Peak memory 219072 kb
Host smart-8902dc42-d88d-4ee9-b474-2c1950467b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038651056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4038651056
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.621328008
Short name T724
Test name
Test status
Simulation time 55247760 ps
CPU time 1.23 seconds
Started Jul 10 07:23:28 PM PDT 24
Finished Jul 10 07:23:33 PM PDT 24
Peak memory 216020 kb
Host smart-046df37d-5606-4bf9-9407-68583cd68ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621328008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.621328008
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4039343395
Short name T424
Test name
Test status
Simulation time 18685457 ps
CPU time 1.09 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:23 PM PDT 24
Peak memory 218768 kb
Host smart-111fa9b7-0c2f-4abe-97ef-85d162755357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039343395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4039343395
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3621386748
Short name T51
Test name
Test status
Simulation time 349106933 ps
CPU time 1.14 seconds
Started Jul 10 07:23:18 PM PDT 24
Finished Jul 10 07:23:22 PM PDT 24
Peak memory 217712 kb
Host smart-492f42f2-0ad3-4348-8079-465ed8757f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621386748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3621386748
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2292085724
Short name T711
Test name
Test status
Simulation time 93921628 ps
CPU time 1.25 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:27 PM PDT 24
Peak memory 215996 kb
Host smart-613100c8-a101-4d50-a9bf-d7331c04bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292085724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2292085724
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2037892398
Short name T637
Test name
Test status
Simulation time 36307230 ps
CPU time 0.94 seconds
Started Jul 10 07:23:20 PM PDT 24
Finished Jul 10 07:23:26 PM PDT 24
Peak memory 220064 kb
Host smart-3d3f5cd7-0137-4e34-83ce-391f2520f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037892398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2037892398
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2195432637
Short name T942
Test name
Test status
Simulation time 27419501 ps
CPU time 1.03 seconds
Started Jul 10 07:23:27 PM PDT 24
Finished Jul 10 07:23:32 PM PDT 24
Peak memory 217528 kb
Host smart-0aea29c7-4fd1-4ddf-9085-9c07a1942172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195432637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2195432637
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.45241109
Short name T115
Test name
Test status
Simulation time 56008303 ps
CPU time 1.29 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:30 PM PDT 24
Peak memory 219036 kb
Host smart-566e0b9e-b556-45c6-8366-b95107bef05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45241109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.45241109
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1183274725
Short name T203
Test name
Test status
Simulation time 28161239 ps
CPU time 0.89 seconds
Started Jul 10 07:23:23 PM PDT 24
Finished Jul 10 07:23:29 PM PDT 24
Peak memory 218528 kb
Host smart-169482cb-737a-4242-8a5d-99f30f720c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183274725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1183274725
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3085234383
Short name T822
Test name
Test status
Simulation time 34889683 ps
CPU time 1 seconds
Started Jul 10 07:23:17 PM PDT 24
Finished Jul 10 07:23:20 PM PDT 24
Peak memory 217836 kb
Host smart-acdf1630-4cfe-4b2d-b390-38ef7940c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085234383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3085234383
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%