Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
111492 |
1 |
|
|
T1 |
408 |
|
T2 |
17 |
|
T3 |
20 |
all_pins[1] |
111492 |
1 |
|
|
T1 |
408 |
|
T2 |
17 |
|
T3 |
20 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
213008 |
1 |
|
|
T1 |
754 |
|
T2 |
34 |
|
T3 |
40 |
values[0x1] |
9976 |
1 |
|
|
T1 |
62 |
|
T42 |
20 |
|
T35 |
234 |
transitions[0x0=>0x1] |
9163 |
1 |
|
|
T1 |
54 |
|
T42 |
17 |
|
T35 |
217 |
transitions[0x1=>0x0] |
9173 |
1 |
|
|
T1 |
54 |
|
T42 |
17 |
|
T35 |
217 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
103321 |
1 |
|
|
T1 |
369 |
|
T2 |
17 |
|
T3 |
20 |
all_pins[0] |
values[0x1] |
8171 |
1 |
|
|
T1 |
39 |
|
T42 |
12 |
|
T35 |
193 |
all_pins[0] |
transitions[0x0=>0x1] |
7743 |
1 |
|
|
T1 |
34 |
|
T42 |
10 |
|
T35 |
188 |
all_pins[0] |
transitions[0x1=>0x0] |
1377 |
1 |
|
|
T1 |
18 |
|
T42 |
6 |
|
T35 |
36 |
all_pins[1] |
values[0x0] |
109687 |
1 |
|
|
T1 |
385 |
|
T2 |
17 |
|
T3 |
20 |
all_pins[1] |
values[0x1] |
1805 |
1 |
|
|
T1 |
23 |
|
T42 |
8 |
|
T35 |
41 |
all_pins[1] |
transitions[0x0=>0x1] |
1420 |
1 |
|
|
T1 |
20 |
|
T42 |
7 |
|
T35 |
29 |
all_pins[1] |
transitions[0x1=>0x0] |
7796 |
1 |
|
|
T1 |
36 |
|
T42 |
11 |
|
T35 |
181 |