Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.55 98.25 93.91 97.02 91.28 96.37 99.77 92.28


Total test records in report: 1130
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T1023 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3211494876 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 36157145 ps
T1024 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2563716512 Jul 11 05:36:50 PM PDT 24 Jul 11 05:36:55 PM PDT 24 74358922 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3550777563 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:32 PM PDT 24 100073121 ps
T268 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1972343709 Jul 11 05:36:38 PM PDT 24 Jul 11 05:36:41 PM PDT 24 15125261 ps
T303 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2129220569 Jul 11 05:36:26 PM PDT 24 Jul 11 05:36:31 PM PDT 24 169979007 ps
T1026 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1244792423 Jul 11 05:36:38 PM PDT 24 Jul 11 05:36:41 PM PDT 24 29602893 ps
T1027 /workspace/coverage/cover_reg_top/49.edn_intr_test.2537167657 Jul 11 05:36:46 PM PDT 24 Jul 11 05:36:50 PM PDT 24 47813249 ps
T285 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4112382682 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 106656212 ps
T269 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3997376807 Jul 11 05:36:50 PM PDT 24 Jul 11 05:37:01 PM PDT 24 1318299450 ps
T301 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1692868627 Jul 11 05:36:21 PM PDT 24 Jul 11 05:36:27 PM PDT 24 86538602 ps
T286 /workspace/coverage/cover_reg_top/12.edn_csr_rw.932957268 Jul 11 05:36:36 PM PDT 24 Jul 11 05:36:39 PM PDT 24 11116689 ps
T1028 /workspace/coverage/cover_reg_top/26.edn_intr_test.962740731 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:53 PM PDT 24 42109913 ps
T302 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2576830137 Jul 11 05:37:30 PM PDT 24 Jul 11 05:37:33 PM PDT 24 146895097 ps
T1029 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2716868134 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 51883060 ps
T1030 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.709642743 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 19526263 ps
T270 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1945281028 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:32 PM PDT 24 39026239 ps
T1031 /workspace/coverage/cover_reg_top/3.edn_intr_test.1504870909 Jul 11 05:36:28 PM PDT 24 Jul 11 05:36:32 PM PDT 24 44848677 ps
T1032 /workspace/coverage/cover_reg_top/25.edn_intr_test.3186443742 Jul 11 05:37:10 PM PDT 24 Jul 11 05:37:12 PM PDT 24 11453150 ps
T287 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4120601617 Jul 11 05:36:29 PM PDT 24 Jul 11 05:36:33 PM PDT 24 33564521 ps
T1033 /workspace/coverage/cover_reg_top/17.edn_intr_test.1651212276 Jul 11 05:37:30 PM PDT 24 Jul 11 05:37:32 PM PDT 24 139299413 ps
T1034 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4188386501 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 19281703 ps
T1035 /workspace/coverage/cover_reg_top/10.edn_intr_test.2037656633 Jul 11 05:36:43 PM PDT 24 Jul 11 05:36:46 PM PDT 24 24750094 ps
T288 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.640158878 Jul 11 05:43:21 PM PDT 24 Jul 11 05:43:26 PM PDT 24 70141587 ps
T1036 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3319125742 Jul 11 05:36:33 PM PDT 24 Jul 11 05:36:40 PM PDT 24 372648495 ps
T271 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2071744227 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:38 PM PDT 24 17247459 ps
T1037 /workspace/coverage/cover_reg_top/48.edn_intr_test.3333556243 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:53 PM PDT 24 105108534 ps
T1038 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1026992179 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:10 PM PDT 24 169545588 ps
T289 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1798867065 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 43287265 ps
T1039 /workspace/coverage/cover_reg_top/28.edn_intr_test.547205441 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:53 PM PDT 24 17072315 ps
T1040 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3601532986 Jul 11 05:36:25 PM PDT 24 Jul 11 05:36:30 PM PDT 24 28716230 ps
T1041 /workspace/coverage/cover_reg_top/43.edn_intr_test.738147654 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 12129432 ps
T1042 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3830644384 Jul 11 05:36:37 PM PDT 24 Jul 11 05:36:41 PM PDT 24 73995756 ps
T1043 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.182978755 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 87581694 ps
T1044 /workspace/coverage/cover_reg_top/37.edn_intr_test.916946714 Jul 11 05:37:19 PM PDT 24 Jul 11 05:37:22 PM PDT 24 21606480 ps
T1045 /workspace/coverage/cover_reg_top/22.edn_intr_test.2080686413 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:48 PM PDT 24 12118761 ps
T1046 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2408807739 Jul 11 05:37:08 PM PDT 24 Jul 11 05:37:11 PM PDT 24 15236355 ps
T1047 /workspace/coverage/cover_reg_top/9.edn_intr_test.1490111119 Jul 11 05:36:30 PM PDT 24 Jul 11 05:36:36 PM PDT 24 11267687 ps
T1048 /workspace/coverage/cover_reg_top/11.edn_tl_errors.246792726 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:49 PM PDT 24 42877105 ps
T1049 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2441563925 Jul 11 05:36:33 PM PDT 24 Jul 11 05:36:38 PM PDT 24 146586644 ps
T1050 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2935610086 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:55 PM PDT 24 94297634 ps
T1051 /workspace/coverage/cover_reg_top/14.edn_intr_test.787830283 Jul 11 05:37:28 PM PDT 24 Jul 11 05:37:30 PM PDT 24 13569148 ps
T1052 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2377138934 Jul 11 05:36:42 PM PDT 24 Jul 11 05:36:44 PM PDT 24 27874122 ps
T1053 /workspace/coverage/cover_reg_top/31.edn_intr_test.397589412 Jul 11 05:36:46 PM PDT 24 Jul 11 05:36:50 PM PDT 24 11357776 ps
T1054 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1719792206 Jul 11 05:36:57 PM PDT 24 Jul 11 05:37:02 PM PDT 24 14258840 ps
T1055 /workspace/coverage/cover_reg_top/21.edn_intr_test.6469111 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 12809435 ps
T272 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1904784889 Jul 11 05:36:53 PM PDT 24 Jul 11 05:36:59 PM PDT 24 18066965 ps
T1056 /workspace/coverage/cover_reg_top/0.edn_intr_test.4253395078 Jul 11 05:36:29 PM PDT 24 Jul 11 05:36:34 PM PDT 24 26234057 ps
T274 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1267730319 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:33 PM PDT 24 258275281 ps
T1057 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2199772649 Jul 11 05:36:56 PM PDT 24 Jul 11 05:37:04 PM PDT 24 279724118 ps
T1058 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3723387958 Jul 11 05:36:46 PM PDT 24 Jul 11 05:36:50 PM PDT 24 33314977 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_intr_test.675934203 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 46244011 ps
T1060 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1358655800 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:54 PM PDT 24 111505579 ps
T1061 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3153118560 Jul 11 05:37:30 PM PDT 24 Jul 11 05:37:38 PM PDT 24 372625262 ps
T1062 /workspace/coverage/cover_reg_top/29.edn_intr_test.2883925703 Jul 11 05:36:49 PM PDT 24 Jul 11 05:36:54 PM PDT 24 87659289 ps
T1063 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3490834886 Jul 11 05:36:19 PM PDT 24 Jul 11 05:36:24 PM PDT 24 80894364 ps
T1064 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2622899410 Jul 11 05:36:56 PM PDT 24 Jul 11 05:37:03 PM PDT 24 54567253 ps
T1065 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1324152005 Jul 11 05:36:32 PM PDT 24 Jul 11 05:36:40 PM PDT 24 107782181 ps
T273 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4120814271 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:31 PM PDT 24 36952932 ps
T1066 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2025580036 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 91223554 ps
T275 /workspace/coverage/cover_reg_top/3.edn_csr_rw.705488058 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:56 PM PDT 24 39447933 ps
T1067 /workspace/coverage/cover_reg_top/0.edn_csr_rw.139996183 Jul 11 05:36:28 PM PDT 24 Jul 11 05:36:32 PM PDT 24 26682465 ps
T276 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2580046263 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:30 PM PDT 24 15910969 ps
T1068 /workspace/coverage/cover_reg_top/36.edn_intr_test.2762463406 Jul 11 05:36:54 PM PDT 24 Jul 11 05:37:00 PM PDT 24 32343584 ps
T1069 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1654333773 Jul 11 05:36:28 PM PDT 24 Jul 11 05:36:33 PM PDT 24 87514453 ps
T1070 /workspace/coverage/cover_reg_top/30.edn_intr_test.1840592487 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:57 PM PDT 24 14106310 ps
T1071 /workspace/coverage/cover_reg_top/23.edn_intr_test.1278220235 Jul 11 05:37:08 PM PDT 24 Jul 11 05:37:11 PM PDT 24 40432281 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2190043770 Jul 11 05:36:42 PM PDT 24 Jul 11 05:36:45 PM PDT 24 34180728 ps
T279 /workspace/coverage/cover_reg_top/18.edn_csr_rw.4263644649 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:10 PM PDT 24 42518979 ps
T1073 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3381694560 Jul 11 05:36:46 PM PDT 24 Jul 11 05:36:50 PM PDT 24 151210715 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.445484530 Jul 11 05:36:36 PM PDT 24 Jul 11 05:36:40 PM PDT 24 28914630 ps
T1075 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3651878193 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:47 PM PDT 24 18187400 ps
T1076 /workspace/coverage/cover_reg_top/27.edn_intr_test.1675484468 Jul 11 05:37:19 PM PDT 24 Jul 11 05:37:22 PM PDT 24 29666978 ps
T1077 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4176732532 Jul 11 05:36:41 PM PDT 24 Jul 11 05:36:44 PM PDT 24 34128520 ps
T1078 /workspace/coverage/cover_reg_top/13.edn_intr_test.1278633028 Jul 11 05:36:36 PM PDT 24 Jul 11 05:36:40 PM PDT 24 11848747 ps
T1079 /workspace/coverage/cover_reg_top/45.edn_intr_test.2265992074 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:52 PM PDT 24 12362488 ps
T277 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2347996997 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 14076426 ps
T1080 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2623822301 Jul 11 05:36:32 PM PDT 24 Jul 11 05:36:37 PM PDT 24 19748539 ps
T1081 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2010935521 Jul 11 05:36:56 PM PDT 24 Jul 11 05:37:02 PM PDT 24 48573197 ps
T1082 /workspace/coverage/cover_reg_top/20.edn_intr_test.2873576731 Jul 11 05:36:39 PM PDT 24 Jul 11 05:36:42 PM PDT 24 26125975 ps
T1083 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4195270961 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:58 PM PDT 24 1012798491 ps
T1084 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4181878198 Jul 11 05:37:29 PM PDT 24 Jul 11 05:37:32 PM PDT 24 18136891 ps
T1085 /workspace/coverage/cover_reg_top/19.edn_tl_errors.877669900 Jul 11 05:37:28 PM PDT 24 Jul 11 05:37:32 PM PDT 24 75739815 ps
T1086 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4037768118 Jul 11 05:36:31 PM PDT 24 Jul 11 05:36:37 PM PDT 24 35407624 ps
T1087 /workspace/coverage/cover_reg_top/16.edn_intr_test.47227077 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:52 PM PDT 24 14093382 ps
T1088 /workspace/coverage/cover_reg_top/44.edn_intr_test.1051661338 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 14129720 ps
T1089 /workspace/coverage/cover_reg_top/35.edn_intr_test.92935138 Jul 11 05:36:49 PM PDT 24 Jul 11 05:36:54 PM PDT 24 16543549 ps
T1090 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1937804348 Jul 11 05:36:41 PM PDT 24 Jul 11 05:36:44 PM PDT 24 30313874 ps
T1091 /workspace/coverage/cover_reg_top/2.edn_intr_test.3929646541 Jul 11 05:36:27 PM PDT 24 Jul 11 05:36:31 PM PDT 24 25702820 ps
T1092 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1342032964 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 16988611 ps
T1093 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.804230505 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 32279264 ps
T278 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1501478592 Jul 11 05:36:45 PM PDT 24 Jul 11 05:36:48 PM PDT 24 18270378 ps
T1094 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3783762195 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:48 PM PDT 24 107613930 ps
T1095 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4100072456 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:53 PM PDT 24 87385663 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3918367094 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:11 PM PDT 24 629952388 ps
T1097 /workspace/coverage/cover_reg_top/24.edn_intr_test.260807934 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:57 PM PDT 24 16153900 ps
T1098 /workspace/coverage/cover_reg_top/40.edn_intr_test.486778325 Jul 11 05:36:49 PM PDT 24 Jul 11 05:36:54 PM PDT 24 36339586 ps
T1099 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3294441659 Jul 11 05:36:23 PM PDT 24 Jul 11 05:36:27 PM PDT 24 17157884 ps
T1100 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.450033217 Jul 11 05:37:29 PM PDT 24 Jul 11 05:37:31 PM PDT 24 30525189 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1559888342 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 77775629 ps
T1102 /workspace/coverage/cover_reg_top/1.edn_intr_test.775331581 Jul 11 05:36:25 PM PDT 24 Jul 11 05:36:29 PM PDT 24 10875924 ps
T1103 /workspace/coverage/cover_reg_top/7.edn_tl_errors.4290713834 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:53 PM PDT 24 69772243 ps
T1104 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4158837397 Jul 11 05:36:41 PM PDT 24 Jul 11 05:36:44 PM PDT 24 80221146 ps
T1105 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2708371772 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:53 PM PDT 24 38325688 ps
T1106 /workspace/coverage/cover_reg_top/15.edn_tl_errors.517301797 Jul 11 05:36:39 PM PDT 24 Jul 11 05:36:44 PM PDT 24 69399138 ps
T280 /workspace/coverage/cover_reg_top/19.edn_csr_rw.273075533 Jul 11 05:36:40 PM PDT 24 Jul 11 05:36:42 PM PDT 24 40621312 ps
T1107 /workspace/coverage/cover_reg_top/7.edn_intr_test.2629962613 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:39 PM PDT 24 15762076 ps
T1108 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2088191041 Jul 11 05:36:26 PM PDT 24 Jul 11 05:36:30 PM PDT 24 41487917 ps
T1109 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2471858977 Jul 11 05:36:41 PM PDT 24 Jul 11 05:36:44 PM PDT 24 93876119 ps
T1110 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3126846954 Jul 11 05:36:50 PM PDT 24 Jul 11 05:36:55 PM PDT 24 76037914 ps
T1111 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1263747427 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:40 PM PDT 24 168563902 ps
T1112 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3927798698 Jul 11 05:36:41 PM PDT 24 Jul 11 05:36:44 PM PDT 24 32547620 ps
T1113 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3936594458 Jul 11 05:36:31 PM PDT 24 Jul 11 05:36:38 PM PDT 24 52734916 ps
T1114 /workspace/coverage/cover_reg_top/6.edn_intr_test.3111310499 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 11018156 ps
T1115 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1533497398 Jul 11 05:36:43 PM PDT 24 Jul 11 05:36:46 PM PDT 24 745777506 ps
T1116 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4096553643 Jul 11 05:36:43 PM PDT 24 Jul 11 05:36:46 PM PDT 24 25115729 ps
T1117 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1211173474 Jul 11 05:36:37 PM PDT 24 Jul 11 05:36:42 PM PDT 24 315472650 ps
T1118 /workspace/coverage/cover_reg_top/9.edn_tl_errors.490156538 Jul 11 05:36:46 PM PDT 24 Jul 11 05:36:51 PM PDT 24 67771930 ps
T1119 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1932524260 Jul 11 05:36:29 PM PDT 24 Jul 11 05:36:33 PM PDT 24 23319651 ps
T1120 /workspace/coverage/cover_reg_top/39.edn_intr_test.2140530763 Jul 11 05:36:47 PM PDT 24 Jul 11 05:36:51 PM PDT 24 28496898 ps
T1121 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1555532318 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:48 PM PDT 24 16261901 ps
T1122 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2184941500 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:58 PM PDT 24 79653625 ps
T281 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1628737451 Jul 11 05:36:28 PM PDT 24 Jul 11 05:36:32 PM PDT 24 139450666 ps
T1123 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1154299556 Jul 11 05:36:24 PM PDT 24 Jul 11 05:36:30 PM PDT 24 121070361 ps
T1124 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2539954711 Jul 11 05:36:34 PM PDT 24 Jul 11 05:36:41 PM PDT 24 367470568 ps
T1125 /workspace/coverage/cover_reg_top/18.edn_tl_errors.772428322 Jul 11 05:37:17 PM PDT 24 Jul 11 05:37:23 PM PDT 24 112316534 ps
T1126 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2802956089 Jul 11 05:36:56 PM PDT 24 Jul 11 05:37:03 PM PDT 24 71884781 ps
T1127 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2649946977 Jul 11 05:37:08 PM PDT 24 Jul 11 05:37:11 PM PDT 24 50042991 ps
T1128 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.89857553 Jul 11 05:36:45 PM PDT 24 Jul 11 05:36:49 PM PDT 24 23341830 ps
T1129 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3863357591 Jul 11 05:37:29 PM PDT 24 Jul 11 05:37:31 PM PDT 24 30822592 ps
T1130 /workspace/coverage/cover_reg_top/18.edn_intr_test.727910664 Jul 11 05:37:08 PM PDT 24 Jul 11 05:37:11 PM PDT 24 74398222 ps

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2747784742
Short name T1
Test name
Test status
Simulation time 265778694752 ps
CPU time 1126.31 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 222720 kb
Host smart-3530c0b7-394a-4bd9-b7ee-7e99d3f18275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747784742 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2747784742
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.1968882936
Short name T15
Test name
Test status
Simulation time 92569924 ps
CPU time 1.56 seconds
Started Jul 11 05:41:36 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 220472 kb
Host smart-bf9222ce-2c2f-474c-84e9-1e22551fcad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968882936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1968882936
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_err.3175058532
Short name T4
Test name
Test status
Simulation time 19739300 ps
CPU time 1.15 seconds
Started Jul 11 05:39:18 PM PDT 24
Finished Jul 11 05:39:20 PM PDT 24
Peak memory 224232 kb
Host smart-8b105334-fb18-4ff3-9408-b609849b50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175058532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3175058532
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.10574195
Short name T51
Test name
Test status
Simulation time 481578852 ps
CPU time 4.2 seconds
Started Jul 11 05:38:51 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 236064 kb
Host smart-fce14132-688a-44da-aa7e-24a422aba025
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.10574195
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/105.edn_alert.2765433936
Short name T41
Test name
Test status
Simulation time 70773139 ps
CPU time 1.29 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:08 PM PDT 24
Peak memory 220544 kb
Host smart-b0531021-613a-4eca-8892-d21ebab5d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765433936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2765433936
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4040035867
Short name T191
Test name
Test status
Simulation time 68564269 ps
CPU time 1.11 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:58 PM PDT 24
Peak memory 218864 kb
Host smart-c53d7d35-e35d-46e6-bfbb-be72665fe03c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040035867 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4040035867
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/148.edn_alert.4080415248
Short name T69
Test name
Test status
Simulation time 30912475 ps
CPU time 1.27 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 220060 kb
Host smart-68cfb572-dc1c-4d8c-b823-0dfc2096cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080415248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4080415248
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/38.edn_intr.1276375020
Short name T43
Test name
Test status
Simulation time 21592816 ps
CPU time 1.24 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:40 PM PDT 24
Peak memory 224296 kb
Host smart-133332cf-4d1a-4532-afcf-54055fabf87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276375020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1276375020
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1923053063
Short name T88
Test name
Test status
Simulation time 220219310257 ps
CPU time 1376.17 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 226356 kb
Host smart-b4a49c19-fef1-4c50-96db-472eee292b86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923053063 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1923053063
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_disable.1342563195
Short name T38
Test name
Test status
Simulation time 58256036 ps
CPU time 0.89 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:39 PM PDT 24
Peak memory 216516 kb
Host smart-44d40d35-6e74-48f9-92ce-629d06a0c59f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342563195 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1342563195
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/103.edn_alert.1310566184
Short name T20
Test name
Test status
Simulation time 63191852 ps
CPU time 1.13 seconds
Started Jul 11 05:41:20 PM PDT 24
Finished Jul 11 05:41:30 PM PDT 24
Peak memory 221140 kb
Host smart-6dc44bea-0cdf-4874-9fbf-418b91bc5140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310566184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1310566184
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3473405518
Short name T217
Test name
Test status
Simulation time 145258805892 ps
CPU time 1651.59 seconds
Started Jul 11 05:39:03 PM PDT 24
Finished Jul 11 06:06:36 PM PDT 24
Peak memory 224224 kb
Host smart-f00f4a9e-6e29-49eb-bef3-cc33697f973c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473405518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3473405518
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.edn_alert.4201944747
Short name T91
Test name
Test status
Simulation time 26652101 ps
CPU time 1.21 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 219088 kb
Host smart-bbca687d-9761-4574-8083-df2238390cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201944747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.4201944747
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2762801744
Short name T107
Test name
Test status
Simulation time 268129279 ps
CPU time 1.06 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 217200 kb
Host smart-8ef8e96f-a336-42f4-ba38-6023e19c58db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762801744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2762801744
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.2679330248
Short name T636
Test name
Test status
Simulation time 124157637 ps
CPU time 0.95 seconds
Started Jul 11 05:38:41 PM PDT 24
Finished Jul 11 05:38:43 PM PDT 24
Peak memory 207428 kb
Host smart-161fedd7-bcfe-4ef0-aafa-f8c5496a8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679330248 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2679330248
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_genbits.1536487181
Short name T67
Test name
Test status
Simulation time 47207924 ps
CPU time 1.09 seconds
Started Jul 11 05:38:55 PM PDT 24
Finished Jul 11 05:38:58 PM PDT 24
Peak memory 218660 kb
Host smart-e0fa7e41-4673-476e-95a9-ba7c974150db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536487181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1536487181
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2262248185
Short name T296
Test name
Test status
Simulation time 288168038 ps
CPU time 2.37 seconds
Started Jul 11 05:36:42 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 215172 kb
Host smart-053fc96d-fddb-4c51-b588-67ad3b2757c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262248185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2262248185
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/181.edn_alert.2120392711
Short name T186
Test name
Test status
Simulation time 27179803 ps
CPU time 1.21 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 220072 kb
Host smart-b30b9ccd-19e2-48f6-99fb-42f470f8beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120392711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2120392711
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.671195147
Short name T128
Test name
Test status
Simulation time 37483075 ps
CPU time 1.21 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 219772 kb
Host smart-9891484c-fd8c-4281-b6ce-323a54cb201c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671195147 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.671195147
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_disable.2656488462
Short name T195
Test name
Test status
Simulation time 17551741 ps
CPU time 0.98 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 216760 kb
Host smart-af798758-1cf6-49f2-bb06-c6f39a2c4fa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656488462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2656488462
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2505324988
Short name T197
Test name
Test status
Simulation time 36821292 ps
CPU time 1.33 seconds
Started Jul 11 05:39:20 PM PDT 24
Finished Jul 11 05:39:23 PM PDT 24
Peak memory 217136 kb
Host smart-e17a2257-775d-4ce9-bb26-5d7a4856888e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505324988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2505324988
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/102.edn_alert.342017283
Short name T139
Test name
Test status
Simulation time 32034497 ps
CPU time 1.34 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:06 PM PDT 24
Peak memory 216016 kb
Host smart-c5dc254d-79c3-4870-bd6d-e48d04d5e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342017283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.342017283
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.2530110042
Short name T181
Test name
Test status
Simulation time 94802593 ps
CPU time 1.31 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 220616 kb
Host smart-c99c2060-fc6a-4992-8948-2e4d7e4c8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530110042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2530110042
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2697042230
Short name T157
Test name
Test status
Simulation time 20262123 ps
CPU time 1.1 seconds
Started Jul 11 05:41:20 PM PDT 24
Finished Jul 11 05:41:30 PM PDT 24
Peak memory 215676 kb
Host smart-7e58fa14-8b94-43ed-893b-72c17a9de6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697042230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2697042230
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/23.edn_err.1244181789
Short name T183
Test name
Test status
Simulation time 26680655 ps
CPU time 0.86 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:58 PM PDT 24
Peak memory 218740 kb
Host smart-28160917-cb95-4bf5-acee-567403c20985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244181789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1244181789
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.1195639763
Short name T28
Test name
Test status
Simulation time 40179352 ps
CPU time 0.85 seconds
Started Jul 11 05:38:54 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 215896 kb
Host smart-909a04d5-a4dc-41e4-968a-4904849dd690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195639763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1195639763
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/144.edn_alert.2927934467
Short name T176
Test name
Test status
Simulation time 30233978 ps
CPU time 1.24 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 216048 kb
Host smart-c141fbc3-7000-4138-ad4d-c773f246eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927934467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2927934467
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.517466158
Short name T173
Test name
Test status
Simulation time 24675909 ps
CPU time 1.2 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 219812 kb
Host smart-f121d81e-1046-4d2c-a7c2-7805bb443892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517466158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.517466158
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.3879901737
Short name T21
Test name
Test status
Simulation time 189456686 ps
CPU time 1.09 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 219800 kb
Host smart-23f3f766-041c-4908-b466-d68c52caa9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879901737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3879901737
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.1917938883
Short name T962
Test name
Test status
Simulation time 197879889 ps
CPU time 1.27 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 218848 kb
Host smart-74e9e941-1d89-439a-a2fe-cb3afab83dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917938883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1917938883
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.1306984205
Short name T599
Test name
Test status
Simulation time 91097238 ps
CPU time 1.16 seconds
Started Jul 11 05:41:33 PM PDT 24
Finished Jul 11 05:41:38 PM PDT 24
Peak memory 219260 kb
Host smart-6f9e5811-0767-4ffa-90a4-4badbab4d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306984205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1306984205
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.2672441531
Short name T130
Test name
Test status
Simulation time 35063573 ps
CPU time 1.29 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 215960 kb
Host smart-5ebdd254-b1e3-4488-aa02-968ffdda3077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672441531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2672441531
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/246.edn_genbits.3865125057
Short name T76
Test name
Test status
Simulation time 81006599 ps
CPU time 1.4 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 219088 kb
Host smart-9c7001d5-2a12-4eec-90cc-01008bf3d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865125057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3865125057
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1403872333
Short name T332
Test name
Test status
Simulation time 132085934 ps
CPU time 1.47 seconds
Started Jul 11 05:42:02 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 219248 kb
Host smart-a45636d0-5756-41b4-aebc-560038a27c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403872333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1403872333
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.521798057
Short name T81
Test name
Test status
Simulation time 35633954 ps
CPU time 0.93 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 216020 kb
Host smart-9b8f6a13-1efb-46b0-a36e-bc2197084a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521798057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.521798057
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.1604051476
Short name T200
Test name
Test status
Simulation time 23113234 ps
CPU time 0.85 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 216632 kb
Host smart-1c1506b2-f663-42ec-9485-57f40a5cdef1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604051476 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1604051476
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_alert.2030404726
Short name T475
Test name
Test status
Simulation time 90483806 ps
CPU time 1.2 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 220244 kb
Host smart-2614d987-12d5-4bc5-80d2-f93f70947996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030404726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2030404726
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.2653760615
Short name T203
Test name
Test status
Simulation time 24501720 ps
CPU time 0.84 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:16 PM PDT 24
Peak memory 216636 kb
Host smart-74440f69-4eaa-4056-a19e-aaf3bd384e0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653760615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2653760615
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.330197155
Short name T137
Test name
Test status
Simulation time 37433861 ps
CPU time 1.28 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:17 PM PDT 24
Peak memory 217152 kb
Host smart-64753947-8853-420a-bc72-0c7c8276379b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330197155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.330197155
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/107.edn_alert.4266393444
Short name T164
Test name
Test status
Simulation time 23720489 ps
CPU time 1.15 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 219064 kb
Host smart-d83428a7-7df9-4235-b578-559303d3d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266393444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.4266393444
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.3280023650
Short name T445
Test name
Test status
Simulation time 89353936 ps
CPU time 1.11 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 220612 kb
Host smart-dc9afa1b-aed2-4e6d-bf23-469974113b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280023650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3280023650
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/13.edn_err.2051601749
Short name T424
Test name
Test status
Simulation time 30759599 ps
CPU time 0.97 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:21 PM PDT 24
Peak memory 229688 kb
Host smart-ee2b2c33-8daa-424a-a815-03124d5a08e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051601749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2051601749
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/18.edn_disable.2016032853
Short name T171
Test name
Test status
Simulation time 14080646 ps
CPU time 0.9 seconds
Started Jul 11 05:39:43 PM PDT 24
Finished Jul 11 05:39:45 PM PDT 24
Peak memory 216624 kb
Host smart-cd258396-79b0-4fb3-8adc-8b67110b6138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016032853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2016032853
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.1867380072
Short name T193
Test name
Test status
Simulation time 16180736 ps
CPU time 0.89 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:12 PM PDT 24
Peak memory 216596 kb
Host smart-d32ff73f-f6a7-4d6f-9de8-2a976209ce86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867380072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1867380072
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.2459322137
Short name T163
Test name
Test status
Simulation time 69223030 ps
CPU time 0.83 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 216436 kb
Host smart-1338fd42-307f-4c36-ac90-332eaf15e228
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459322137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2459322137
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.137876048
Short name T854
Test name
Test status
Simulation time 28515310 ps
CPU time 1.07 seconds
Started Jul 11 05:40:06 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 224248 kb
Host smart-786d9d1e-bfcf-426d-9587-cec681b40ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137876048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.137876048
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4155359480
Short name T115
Test name
Test status
Simulation time 32733489 ps
CPU time 1.14 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:22 PM PDT 24
Peak memory 217356 kb
Host smart-0551a373-aaf7-4045-951d-e9d5a482e22a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155359480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4155359480
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1945281028
Short name T270
Test name
Test status
Simulation time 39026239 ps
CPU time 1.58 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 206912 kb
Host smart-7a410baa-99c1-48b3-b601-62bae84ffd55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945281028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1945281028
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/42.edn_stress_all.2176071090
Short name T240
Test name
Test status
Simulation time 364603923 ps
CPU time 2.58 seconds
Started Jul 11 05:40:37 PM PDT 24
Finished Jul 11 05:40:40 PM PDT 24
Peak memory 215592 kb
Host smart-6afddd97-4145-4303-af09-0a751444a59f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176071090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2176071090
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert_test.2750124142
Short name T94
Test name
Test status
Simulation time 21005812 ps
CPU time 1.02 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:16 PM PDT 24
Peak memory 215156 kb
Host smart-1491c7ce-f437-40b3-8231-9cb9fb3fe9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750124142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2750124142
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/238.edn_genbits.845751898
Short name T320
Test name
Test status
Simulation time 60953571 ps
CPU time 2.13 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 219952 kb
Host smart-b7396ac4-32dd-4652-b58d-a95469af5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845751898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.845751898
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3529077396
Short name T66
Test name
Test status
Simulation time 32036302 ps
CPU time 1.28 seconds
Started Jul 11 05:42:18 PM PDT 24
Finished Jul 11 05:42:24 PM PDT 24
Peak memory 217728 kb
Host smart-bb9ea860-5a2c-44c4-85e1-bf8261a2b4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529077396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3529077396
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.877226891
Short name T305
Test name
Test status
Simulation time 103802573 ps
CPU time 1.14 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 219956 kb
Host smart-17822ae3-c876-48d5-b398-b03444cc40ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877226891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.877226891
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/46.edn_intr.1799450189
Short name T33
Test name
Test status
Simulation time 25282810 ps
CPU time 0.95 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:41:01 PM PDT 24
Peak memory 216184 kb
Host smart-058d650b-b90c-4399-ad90-769f676a1265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799450189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1799450189
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/94.edn_err.237422500
Short name T7
Test name
Test status
Simulation time 181964644 ps
CPU time 0.98 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 221052 kb
Host smart-46bdcc44-3751-4919-9a46-4c634c8b8bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237422500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.237422500
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/229.edn_genbits.4080219579
Short name T333
Test name
Test status
Simulation time 33810092 ps
CPU time 1.3 seconds
Started Jul 11 05:41:59 PM PDT 24
Finished Jul 11 05:42:06 PM PDT 24
Peak memory 220216 kb
Host smart-9f392234-3267-4f8a-b3c6-1678a880fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080219579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4080219579
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2728925027
Short name T259
Test name
Test status
Simulation time 18356629 ps
CPU time 0.98 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 206904 kb
Host smart-0781a8b6-f9dd-4ed6-bcea-77c720981488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728925027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2728925027
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3263052794
Short name T294
Test name
Test status
Simulation time 143157025 ps
CPU time 1.48 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 215172 kb
Host smart-242a3e5b-e436-42a0-93fc-690f0927c0c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263052794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3263052794
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2740611321
Short name T35
Test name
Test status
Simulation time 167328574994 ps
CPU time 2126.19 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 06:14:22 PM PDT 24
Peak memory 231520 kb
Host smart-1fde115f-febc-496a-a40b-bf41ee0d593c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740611321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2740611321
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.2426110481
Short name T344
Test name
Test status
Simulation time 61664849 ps
CPU time 1.48 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 218940 kb
Host smart-bfc0abe1-164b-4b42-8a7d-1b3dcc693376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426110481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2426110481
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.392214246
Short name T338
Test name
Test status
Simulation time 39664819 ps
CPU time 1.64 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 218856 kb
Host smart-5d84ab68-be6a-461d-bb33-00820e28c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392214246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.392214246
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2840787274
Short name T343
Test name
Test status
Simulation time 43925707 ps
CPU time 1.47 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 220300 kb
Host smart-ed694d40-04e2-486c-8cf9-31076236d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840787274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2840787274
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2510336099
Short name T889
Test name
Test status
Simulation time 27357034 ps
CPU time 1.23 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 218904 kb
Host smart-84ace8a3-ee62-47bf-901b-57c88c5fe4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510336099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2510336099
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.439582476
Short name T924
Test name
Test status
Simulation time 72796005 ps
CPU time 1.12 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:06 PM PDT 24
Peak memory 220096 kb
Host smart-8e22563a-02c0-4702-9df9-ba537bc57f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439582476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.439582476
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.770126299
Short name T324
Test name
Test status
Simulation time 63375370 ps
CPU time 1.58 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 218928 kb
Host smart-050cfd26-339b-4bcf-90e8-f973ddb29e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770126299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.770126299
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3568185423
Short name T319
Test name
Test status
Simulation time 107762576 ps
CPU time 1.53 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 219292 kb
Host smart-f21bbbe0-09ee-44de-8dae-1099acbdfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568185423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3568185423
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.210944765
Short name T646
Test name
Test status
Simulation time 41391877 ps
CPU time 1.5 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 217472 kb
Host smart-75616a1a-0959-4b54-997d-2b95897c0e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210944765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.210944765
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_stress_all.2378121037
Short name T336
Test name
Test status
Simulation time 288082636 ps
CPU time 5.87 seconds
Started Jul 11 05:38:47 PM PDT 24
Finished Jul 11 05:38:54 PM PDT 24
Peak memory 215676 kb
Host smart-3b1842f3-6ede-434d-ae72-e9fb9122ded1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378121037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2378121037
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/219.edn_genbits.3349945647
Short name T345
Test name
Test status
Simulation time 217020722 ps
CPU time 1.35 seconds
Started Jul 11 05:41:54 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 220296 kb
Host smart-5be33f7e-daf0-4f61-9a23-db2a4a302861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349945647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3349945647
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4075422863
Short name T299
Test name
Test status
Simulation time 27076281 ps
CPU time 1.1 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 217196 kb
Host smart-eb5dd23f-7366-490a-b8f3-d40ae7b654cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075422863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4075422863
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/253.edn_genbits.1538683081
Short name T327
Test name
Test status
Simulation time 181404965 ps
CPU time 2.63 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:34 PM PDT 24
Peak memory 220512 kb
Host smart-e02af240-dc80-4af2-82bb-49c721cadc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538683081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1538683081
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_alert.3980164472
Short name T298
Test name
Test status
Simulation time 53698859 ps
CPU time 1.32 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 218936 kb
Host smart-360f8045-d455-49b9-9382-d7b52adabd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980164472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3980164472
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/34.edn_intr.3831800240
Short name T31
Test name
Test status
Simulation time 36619870 ps
CPU time 0.9 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 215860 kb
Host smart-2f4647be-4353-4716-bfc7-b25c8d6e7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831800240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3831800240
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.3394186361
Short name T208
Test name
Test status
Simulation time 138670606 ps
CPU time 0.82 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:17 PM PDT 24
Peak memory 216584 kb
Host smart-bf00806a-fc95-4951-80e1-89b24f9c8324
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394186361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3394186361
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/34.edn_genbits.3414585436
Short name T14
Test name
Test status
Simulation time 82347653 ps
CPU time 1.69 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 220096 kb
Host smart-f2f5963f-b8cc-493e-b067-8903b4b895d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414585436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3414585436
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1267730319
Short name T274
Test name
Test status
Simulation time 258275281 ps
CPU time 3.66 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 206888 kb
Host smart-88091f7b-6456-49e9-9d9a-c4ba17fa5e44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267730319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1267730319
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1244792423
Short name T1026
Test name
Test status
Simulation time 29602893 ps
CPU time 0.92 seconds
Started Jul 11 05:36:38 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 206920 kb
Host smart-cf2ebd9f-878d-4dcf-a574-f7430487600a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244792423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1244792423
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.210002626
Short name T1010
Test name
Test status
Simulation time 127268495 ps
CPU time 1.47 seconds
Started Jul 11 05:36:37 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 215188 kb
Host smart-8cb1caa4-d5f4-4833-9d4c-47a8d8183ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210002626 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.210002626
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.139996183
Short name T1067
Test name
Test status
Simulation time 26682465 ps
CPU time 0.86 seconds
Started Jul 11 05:36:28 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 206928 kb
Host smart-32f41798-829f-46bd-b827-f1a513fd0ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139996183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.139996183
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4253395078
Short name T1056
Test name
Test status
Simulation time 26234057 ps
CPU time 0.89 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:34 PM PDT 24
Peak memory 206832 kb
Host smart-4bd9c9f8-8d8f-48df-b963-41f544658419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253395078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4253395078
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3294441659
Short name T1099
Test name
Test status
Simulation time 17157884 ps
CPU time 0.93 seconds
Started Jul 11 05:36:23 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 207004 kb
Host smart-76cae23b-af31-4f3a-ac58-042c85eae7e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294441659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3294441659
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3601532986
Short name T1040
Test name
Test status
Simulation time 28716230 ps
CPU time 1.96 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 215304 kb
Host smart-22f8adbf-be71-4bdf-98b0-9f67f1c61949
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601532986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3601532986
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1654333773
Short name T1069
Test name
Test status
Simulation time 87514453 ps
CPU time 1.58 seconds
Started Jul 11 05:36:28 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 215108 kb
Host smart-ba8bcf92-fb07-45ab-9eed-6f4ca281a32c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654333773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1654333773
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1628737451
Short name T281
Test name
Test status
Simulation time 139450666 ps
CPU time 1.07 seconds
Started Jul 11 05:36:28 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 206836 kb
Host smart-ae8bea0e-5948-43d2-92c1-bd3ef6368e1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628737451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1628737451
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3319125742
Short name T1036
Test name
Test status
Simulation time 372648495 ps
CPU time 3.24 seconds
Started Jul 11 05:36:33 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 206956 kb
Host smart-8101e79e-51b3-4cf9-bae4-eaf0946373f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319125742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3319125742
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3550777563
Short name T1025
Test name
Test status
Simulation time 100073121 ps
CPU time 0.89 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 206952 kb
Host smart-9ee49a3d-22d4-4a5e-ba4b-bd3b6a4dd489
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550777563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3550777563
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.307233501
Short name T1002
Test name
Test status
Simulation time 207983888 ps
CPU time 1.35 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 217480 kb
Host smart-2afe62d0-89a5-4897-9fbb-dbcba1798ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307233501 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.307233501
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.775331581
Short name T1102
Test name
Test status
Simulation time 10875924 ps
CPU time 0.83 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 206868 kb
Host smart-ecd27713-5d3c-410c-b4d7-2fe96b854709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775331581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.775331581
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2471858977
Short name T1109
Test name
Test status
Simulation time 93876119 ps
CPU time 1.08 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 207120 kb
Host smart-5afa412a-b9c6-4c7a-b351-a31824e0aec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471858977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2471858977
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2230145722
Short name T1000
Test name
Test status
Simulation time 70087530 ps
CPU time 2.69 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 215252 kb
Host smart-80266c06-c2b2-4c63-b07c-2aa2328b562c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230145722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2230145722
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1692868627
Short name T301
Test name
Test status
Simulation time 86538602 ps
CPU time 2.57 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 207072 kb
Host smart-753ebf4e-6d68-4cfa-88e2-4163544f4f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692868627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1692868627
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4176732532
Short name T1077
Test name
Test status
Simulation time 34128520 ps
CPU time 1.05 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 207040 kb
Host smart-0a5e19ee-9126-4e5e-b5a5-57245767443f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176732532 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4176732532
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1904784889
Short name T272
Test name
Test status
Simulation time 18066965 ps
CPU time 0.86 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206980 kb
Host smart-1ce25b4c-9017-4bd5-9190-20c27d36eb68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904784889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1904784889
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2037656633
Short name T1035
Test name
Test status
Simulation time 24750094 ps
CPU time 0.88 seconds
Started Jul 11 05:36:43 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 206824 kb
Host smart-e8eb62ce-56cb-4ca0-82f2-d57c3fad1976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037656633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2037656633
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.804230505
Short name T1093
Test name
Test status
Simulation time 32279264 ps
CPU time 0.98 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206824 kb
Host smart-a0eaaf58-350b-4154-b90d-41dcb088fc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804230505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.804230505
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1737375853
Short name T1006
Test name
Test status
Simulation time 204309068 ps
CPU time 3.78 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 215192 kb
Host smart-7782b537-8d43-4638-8a1c-79d312440815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737375853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1737375853
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.445484530
Short name T1074
Test name
Test status
Simulation time 28914630 ps
CPU time 0.96 seconds
Started Jul 11 05:36:36 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 206936 kb
Host smart-5df64da7-3362-48cd-a49b-c2f6c58169e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445484530 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.445484530
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2347996997
Short name T277
Test name
Test status
Simulation time 14076426 ps
CPU time 0.9 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206908 kb
Host smart-abeac688-0e41-4f15-83fe-b8dad4e561aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347996997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2347996997
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.420151917
Short name T998
Test name
Test status
Simulation time 67857590 ps
CPU time 0.88 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:47 PM PDT 24
Peak memory 206976 kb
Host smart-69037f8f-1c55-43ac-aad8-1eda7f98b0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420151917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.420151917
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2025580036
Short name T1066
Test name
Test status
Simulation time 91223554 ps
CPU time 1.24 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206928 kb
Host smart-caf47f76-a5aa-40ea-9393-ec6f51dd35aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025580036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2025580036
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.246792726
Short name T1048
Test name
Test status
Simulation time 42877105 ps
CPU time 2.86 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 219680 kb
Host smart-9767dcfd-ccf1-42b0-8c6f-0b75012b807b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246792726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.246792726
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2441563925
Short name T1049
Test name
Test status
Simulation time 146586644 ps
CPU time 1.56 seconds
Started Jul 11 05:36:33 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 206984 kb
Host smart-7a22d206-a463-4bcc-8599-d83651d019c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441563925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2441563925
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1937804348
Short name T1090
Test name
Test status
Simulation time 30313874 ps
CPU time 1.3 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 217632 kb
Host smart-82d909d9-69de-40ed-9523-3c2630143b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937804348 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1937804348
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.932957268
Short name T286
Test name
Test status
Simulation time 11116689 ps
CPU time 0.87 seconds
Started Jul 11 05:36:36 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206876 kb
Host smart-96f2d944-fd2c-4e34-b27c-340bd4f17b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932957268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.932957268
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1223442838
Short name T1013
Test name
Test status
Simulation time 164072942 ps
CPU time 0.86 seconds
Started Jul 11 05:36:39 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 206804 kb
Host smart-d42f513c-4ec1-4f19-a417-1d41d762cdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223442838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1223442838
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3723387958
Short name T1058
Test name
Test status
Simulation time 33314977 ps
CPU time 1.04 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 206908 kb
Host smart-20cfcf4d-433d-4eab-8668-227397017724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723387958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3723387958
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1358655800
Short name T1060
Test name
Test status
Simulation time 111505579 ps
CPU time 2.09 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:54 PM PDT 24
Peak memory 215108 kb
Host smart-423d6cfe-2a63-4fca-a598-8644fd71dfa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358655800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1358655800
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4277002716
Short name T295
Test name
Test status
Simulation time 77353089 ps
CPU time 1.52 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:47 PM PDT 24
Peak memory 207040 kb
Host smart-c337abdb-c6e7-478d-b9f9-bfc0c26c0edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277002716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4277002716
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2716868134
Short name T1029
Test name
Test status
Simulation time 51883060 ps
CPU time 1.1 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 215168 kb
Host smart-e807d685-78b9-4d3c-8b63-47747dea89e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716868134 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2716868134
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3651878193
Short name T1075
Test name
Test status
Simulation time 18187400 ps
CPU time 0.8 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:47 PM PDT 24
Peak memory 206756 kb
Host smart-d26dc725-20c9-4ffb-8eaf-76e3a766c633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651878193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3651878193
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1278633028
Short name T1078
Test name
Test status
Simulation time 11848747 ps
CPU time 0.88 seconds
Started Jul 11 05:36:36 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 206860 kb
Host smart-cf4f6a08-9796-4c5e-a4f1-7d1cfc19acf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278633028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1278633028
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3830644384
Short name T1042
Test name
Test status
Simulation time 73995756 ps
CPU time 1.07 seconds
Started Jul 11 05:36:37 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 207144 kb
Host smart-7bc41e94-b676-4d88-9c05-adb44e8120a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830644384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3830644384
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2110653343
Short name T1016
Test name
Test status
Simulation time 76047163 ps
CPU time 2.14 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 215340 kb
Host smart-7356772a-e6f8-4c3e-bcde-b57107ab4449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110653343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2110653343
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3925856294
Short name T304
Test name
Test status
Simulation time 211279574 ps
CPU time 1.57 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:47 PM PDT 24
Peak memory 206904 kb
Host smart-52c58fbc-6d6f-454a-a01f-b8bf6b9063b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925856294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3925856294
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3863357591
Short name T1129
Test name
Test status
Simulation time 30822592 ps
CPU time 0.98 seconds
Started Jul 11 05:37:29 PM PDT 24
Finished Jul 11 05:37:31 PM PDT 24
Peak memory 206952 kb
Host smart-5c2266e0-bc2f-4ca6-aa66-0cc66f0e46db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863357591 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3863357591
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2408807739
Short name T1046
Test name
Test status
Simulation time 15236355 ps
CPU time 0.96 seconds
Started Jul 11 05:37:08 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206828 kb
Host smart-9bea1322-6f49-4804-b24a-9798e3a2b106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408807739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2408807739
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.787830283
Short name T1051
Test name
Test status
Simulation time 13569148 ps
CPU time 0.84 seconds
Started Jul 11 05:37:28 PM PDT 24
Finished Jul 11 05:37:30 PM PDT 24
Peak memory 206804 kb
Host smart-6394d52d-24b5-4e28-ac68-990ee47e9b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787830283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.787830283
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2377138934
Short name T1052
Test name
Test status
Simulation time 27874122 ps
CPU time 1 seconds
Started Jul 11 05:36:42 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 206924 kb
Host smart-8ff20a7a-bddc-49b1-bb4f-e883f554a41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377138934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2377138934
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.331610530
Short name T1005
Test name
Test status
Simulation time 260013403 ps
CPU time 2.75 seconds
Started Jul 11 05:36:45 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 215228 kb
Host smart-1cbe1ef3-e201-4c77-927b-416e39efba0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331610530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.331610530
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1026992179
Short name T1038
Test name
Test status
Simulation time 169545588 ps
CPU time 1.47 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206968 kb
Host smart-2a6ba671-fc33-49c1-90cf-32f5eb3c2dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026992179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1026992179
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.709642743
Short name T1030
Test name
Test status
Simulation time 19526263 ps
CPU time 1.02 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 215200 kb
Host smart-b5118b4f-1d0d-47a8-a3e0-f861b57b6c5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709642743 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.709642743
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1501478592
Short name T278
Test name
Test status
Simulation time 18270378 ps
CPU time 0.95 seconds
Started Jul 11 05:36:45 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 206868 kb
Host smart-7cec9fa8-bbad-42b1-8bb5-c4c4cb6a28b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501478592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1501478592
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1257643753
Short name T1017
Test name
Test status
Simulation time 99872986 ps
CPU time 0.87 seconds
Started Jul 11 05:36:43 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 207068 kb
Host smart-acfa4691-9207-4680-916a-2a766dfb01ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257643753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1257643753
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1555532318
Short name T1121
Test name
Test status
Simulation time 16261901 ps
CPU time 1.01 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 206960 kb
Host smart-8bbeacec-b589-4863-b122-6f93e5cfcb43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555532318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1555532318
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.517301797
Short name T1106
Test name
Test status
Simulation time 69399138 ps
CPU time 2.53 seconds
Started Jul 11 05:36:39 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 215240 kb
Host smart-395528e9-e6f8-4f3f-9dae-d281f603a7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517301797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.517301797
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3918367094
Short name T1096
Test name
Test status
Simulation time 629952388 ps
CPU time 1.38 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206964 kb
Host smart-b4332db8-d7e0-4614-9e06-b60ced4bf75e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918367094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3918367094
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.450033217
Short name T1100
Test name
Test status
Simulation time 30525189 ps
CPU time 1.22 seconds
Started Jul 11 05:37:29 PM PDT 24
Finished Jul 11 05:37:31 PM PDT 24
Peak memory 223424 kb
Host smart-23492311-3d88-4d67-a0ca-8dd8a6b32094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450033217 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.450033217
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1342032964
Short name T1092
Test name
Test status
Simulation time 16988611 ps
CPU time 0.81 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 206768 kb
Host smart-5d10d78e-40c5-45ed-b974-0a6c36d76d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342032964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1342032964
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.47227077
Short name T1087
Test name
Test status
Simulation time 14093382 ps
CPU time 0.84 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206800 kb
Host smart-782c2812-a08f-4784-939f-53121c9b0e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47227077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.47227077
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4112382682
Short name T285
Test name
Test status
Simulation time 106656212 ps
CPU time 1.29 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206908 kb
Host smart-d51dcce1-e533-4046-a34a-527ac64704dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112382682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4112382682
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3927798698
Short name T1112
Test name
Test status
Simulation time 32547620 ps
CPU time 2.17 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 223368 kb
Host smart-6931a9ec-32e3-431f-bb53-63ae912b5b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927798698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3927798698
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4100072456
Short name T1095
Test name
Test status
Simulation time 87385663 ps
CPU time 1.57 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206744 kb
Host smart-33d792eb-529d-4e7f-8dac-297b2d4323ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100072456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4100072456
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3211494876
Short name T1023
Test name
Test status
Simulation time 36157145 ps
CPU time 1.51 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 215312 kb
Host smart-90735843-ae22-4538-83d4-b01d4ade49a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211494876 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3211494876
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3381694560
Short name T1073
Test name
Test status
Simulation time 151210715 ps
CPU time 0.91 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 206928 kb
Host smart-f8e86f14-696a-4c9a-9718-d35f9804c9d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381694560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3381694560
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1651212276
Short name T1033
Test name
Test status
Simulation time 139299413 ps
CPU time 0.87 seconds
Started Jul 11 05:37:30 PM PDT 24
Finished Jul 11 05:37:32 PM PDT 24
Peak memory 206804 kb
Host smart-6a5c9757-65c2-4f64-988a-4f6dfa788298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651212276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1651212276
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.89857553
Short name T1128
Test name
Test status
Simulation time 23341830 ps
CPU time 1.19 seconds
Started Jul 11 05:36:45 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 206868 kb
Host smart-c3b3dd7a-57c6-4fc8-bf8a-637a43d31d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89857553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.89857553
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2935610086
Short name T1050
Test name
Test status
Simulation time 94297634 ps
CPU time 3.61 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 215136 kb
Host smart-401be48b-207d-4f6e-ad41-fe38e52197bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935610086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2935610086
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3153118560
Short name T1061
Test name
Test status
Simulation time 372625262 ps
CPU time 6.2 seconds
Started Jul 11 05:37:30 PM PDT 24
Finished Jul 11 05:37:38 PM PDT 24
Peak memory 207136 kb
Host smart-26a84ec3-d74c-4f15-8d92-84be9196940f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153118560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3153118560
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2649946977
Short name T1127
Test name
Test status
Simulation time 50042991 ps
CPU time 1.2 seconds
Started Jul 11 05:37:08 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 215216 kb
Host smart-e568169a-4b9d-4014-9845-2cc44a86dd47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649946977 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2649946977
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.4263644649
Short name T279
Test name
Test status
Simulation time 42518979 ps
CPU time 0.86 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206968 kb
Host smart-a067a3ce-6aaf-45ca-8e1f-4945ca6989f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263644649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4263644649
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.727910664
Short name T1130
Test name
Test status
Simulation time 74398222 ps
CPU time 0.83 seconds
Started Jul 11 05:37:08 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206724 kb
Host smart-89da607a-e600-47fe-9916-a85338d216d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727910664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.727910664
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4181878198
Short name T1084
Test name
Test status
Simulation time 18136891 ps
CPU time 1.15 seconds
Started Jul 11 05:37:29 PM PDT 24
Finished Jul 11 05:37:32 PM PDT 24
Peak memory 206920 kb
Host smart-e967c5ac-dc8f-4d3b-853f-2c7b0edf904e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181878198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4181878198
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.772428322
Short name T1125
Test name
Test status
Simulation time 112316534 ps
CPU time 3.8 seconds
Started Jul 11 05:37:17 PM PDT 24
Finished Jul 11 05:37:23 PM PDT 24
Peak memory 215320 kb
Host smart-7ef42976-fc9f-493b-9de4-767bfaabe92e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772428322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.772428322
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2576830137
Short name T302
Test name
Test status
Simulation time 146895097 ps
CPU time 1.62 seconds
Started Jul 11 05:37:30 PM PDT 24
Finished Jul 11 05:37:33 PM PDT 24
Peak memory 206924 kb
Host smart-37bdf966-96b2-407d-a455-2c5306492ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576830137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2576830137
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4158837397
Short name T1104
Test name
Test status
Simulation time 80221146 ps
CPU time 1.38 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 215184 kb
Host smart-5403e4da-94eb-4596-b2a8-e7adba2321ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158837397 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4158837397
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.273075533
Short name T280
Test name
Test status
Simulation time 40621312 ps
CPU time 0.93 seconds
Started Jul 11 05:36:40 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 206924 kb
Host smart-95e32062-6556-40e3-8c86-f2b12c85f7ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273075533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.273075533
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3975816137
Short name T1018
Test name
Test status
Simulation time 31228895 ps
CPU time 0.82 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206792 kb
Host smart-5d60aebd-03ed-4a9a-a4ae-4a002affae38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975816137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3975816137
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2708371772
Short name T1105
Test name
Test status
Simulation time 38325688 ps
CPU time 1.1 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206996 kb
Host smart-e41598da-9e80-4275-a208-2b5afcdd4976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708371772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2708371772
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.877669900
Short name T1085
Test name
Test status
Simulation time 75739815 ps
CPU time 2.57 seconds
Started Jul 11 05:37:28 PM PDT 24
Finished Jul 11 05:37:32 PM PDT 24
Peak memory 215128 kb
Host smart-2638cad2-2690-4551-b013-0965901f7136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877669900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.877669900
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3126846954
Short name T1110
Test name
Test status
Simulation time 76037914 ps
CPU time 1.48 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 206920 kb
Host smart-a6ac01a6-73d5-40a5-b13e-fe4539f919ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126846954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3126846954
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4120814271
Short name T273
Test name
Test status
Simulation time 36952932 ps
CPU time 0.99 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 206948 kb
Host smart-46cfa028-5570-43a0-8df0-e9ffcc9255d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120814271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4120814271
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2199772649
Short name T1057
Test name
Test status
Simulation time 279724118 ps
CPU time 3.39 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 207004 kb
Host smart-eff0b399-6b75-4639-96df-08927c1fa46f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199772649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2199772649
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3298966639
Short name T267
Test name
Test status
Simulation time 20920175 ps
CPU time 0.88 seconds
Started Jul 11 05:36:43 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 206968 kb
Host smart-979a3230-2567-4444-b45c-d1b36dd7fc69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298966639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3298966639
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3490834886
Short name T1063
Test name
Test status
Simulation time 80894364 ps
CPU time 1.45 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 215272 kb
Host smart-cecccd0d-b4ad-4396-8482-d008cc648601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490834886 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3490834886
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2071744227
Short name T271
Test name
Test status
Simulation time 17247459 ps
CPU time 0.93 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 206964 kb
Host smart-17ccf25c-c11a-4dee-8352-56a48346e749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071744227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2071744227
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3929646541
Short name T1091
Test name
Test status
Simulation time 25702820 ps
CPU time 0.86 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 206780 kb
Host smart-422fc5af-b257-421d-87bf-d4175c50d6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929646541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3929646541
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4120601617
Short name T287
Test name
Test status
Simulation time 33564521 ps
CPU time 1.41 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 206808 kb
Host smart-f4967ca9-2725-4b9a-a3bf-76be9effbe43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120601617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4120601617
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2622899410
Short name T1064
Test name
Test status
Simulation time 54567253 ps
CPU time 2.02 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 215204 kb
Host smart-e31471cf-2e62-44c1-a87b-9cbc0f86d48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622899410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2622899410
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2563716512
Short name T1024
Test name
Test status
Simulation time 74358922 ps
CPU time 1.43 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 206888 kb
Host smart-33894fd6-0ea9-4737-a8c9-33f68f5eb638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563716512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2563716512
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2873576731
Short name T1082
Test name
Test status
Simulation time 26125975 ps
CPU time 0.89 seconds
Started Jul 11 05:36:39 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 206856 kb
Host smart-094c2cf5-0f1a-43b8-9e1e-5890d2d17039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873576731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2873576731
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.6469111
Short name T1055
Test name
Test status
Simulation time 12809435 ps
CPU time 0.85 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 206876 kb
Host smart-64eea83c-159f-438d-a6e3-2d38c38b1cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6469111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.6469111
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2080686413
Short name T1045
Test name
Test status
Simulation time 12118761 ps
CPU time 0.81 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 206696 kb
Host smart-9d65fe91-168b-4c37-b44c-0f2389a9810b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080686413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2080686413
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1278220235
Short name T1071
Test name
Test status
Simulation time 40432281 ps
CPU time 0.83 seconds
Started Jul 11 05:37:08 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206776 kb
Host smart-5db64575-06e0-4b74-8d38-791cd7caa54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278220235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1278220235
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.260807934
Short name T1097
Test name
Test status
Simulation time 16153900 ps
CPU time 0.89 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:57 PM PDT 24
Peak memory 206808 kb
Host smart-bfdddfd1-fe6c-4846-b398-3072e8a4bf4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260807934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.260807934
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3186443742
Short name T1032
Test name
Test status
Simulation time 11453150 ps
CPU time 0.82 seconds
Started Jul 11 05:37:10 PM PDT 24
Finished Jul 11 05:37:12 PM PDT 24
Peak memory 206872 kb
Host smart-7b3a443a-afdf-4685-b8b9-cd0d4bbf7049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186443742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3186443742
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.962740731
Short name T1028
Test name
Test status
Simulation time 42109913 ps
CPU time 0.85 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206896 kb
Host smart-61721ee6-f130-40a8-948c-11c95d998216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962740731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.962740731
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1675484468
Short name T1076
Test name
Test status
Simulation time 29666978 ps
CPU time 0.95 seconds
Started Jul 11 05:37:19 PM PDT 24
Finished Jul 11 05:37:22 PM PDT 24
Peak memory 206812 kb
Host smart-b2e1038a-2f40-4a7d-97a8-ca9f5f6b9431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675484468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1675484468
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.547205441
Short name T1039
Test name
Test status
Simulation time 17072315 ps
CPU time 0.81 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206728 kb
Host smart-197fc6bd-6676-4200-bcc6-d8fef5e8f60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547205441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.547205441
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2883925703
Short name T1062
Test name
Test status
Simulation time 87659289 ps
CPU time 0.88 seconds
Started Jul 11 05:36:49 PM PDT 24
Finished Jul 11 05:36:54 PM PDT 24
Peak memory 206788 kb
Host smart-d61f31b9-5ea7-41cb-af12-5f9c0ceadb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883925703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2883925703
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3867202336
Short name T258
Test name
Test status
Simulation time 43009080 ps
CPU time 1.51 seconds
Started Jul 11 05:36:33 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 207040 kb
Host smart-53623731-7e88-4956-981d-51774323cf7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867202336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3867202336
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1263747427
Short name T1111
Test name
Test status
Simulation time 168563902 ps
CPU time 2.85 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 206976 kb
Host smart-1d69159e-4e53-4fde-b309-b19f0c670515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263747427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1263747427
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1719792206
Short name T1054
Test name
Test status
Simulation time 14258840 ps
CPU time 0.88 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206928 kb
Host smart-305f8449-b9ec-434f-b29a-8217bec276d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719792206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1719792206
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.422634327
Short name T1001
Test name
Test status
Simulation time 30863460 ps
CPU time 1.77 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 219824 kb
Host smart-fe50f27c-8c8a-4074-ae2a-82dd7f490a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422634327 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.422634327
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.705488058
Short name T275
Test name
Test status
Simulation time 39447933 ps
CPU time 0.88 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 206712 kb
Host smart-6618e813-dfc0-470f-a8e5-eef035ac4756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705488058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.705488058
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1504870909
Short name T1031
Test name
Test status
Simulation time 44848677 ps
CPU time 0.85 seconds
Started Jul 11 05:36:28 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 206868 kb
Host smart-253989d5-9338-40e3-a03c-47d915bd3393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504870909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1504870909
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.640158878
Short name T288
Test name
Test status
Simulation time 70141587 ps
CPU time 1.06 seconds
Started Jul 11 05:43:21 PM PDT 24
Finished Jul 11 05:43:26 PM PDT 24
Peak memory 206848 kb
Host smart-ec0b4dea-d048-4357-81ff-044e2626d16f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640158878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.640158878
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2539954711
Short name T1124
Test name
Test status
Simulation time 367470568 ps
CPU time 3.65 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 215092 kb
Host smart-f326f3de-2f8b-4ccc-966d-25e6138c6217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539954711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2539954711
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1840592487
Short name T1070
Test name
Test status
Simulation time 14106310 ps
CPU time 0.86 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:57 PM PDT 24
Peak memory 206812 kb
Host smart-9347895d-5e78-45da-9d65-28b42364b7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840592487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1840592487
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.397589412
Short name T1053
Test name
Test status
Simulation time 11357776 ps
CPU time 0.85 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 206864 kb
Host smart-e763951b-72c8-4df1-9704-c52fd7658ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397589412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.397589412
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1372952809
Short name T1014
Test name
Test status
Simulation time 70962702 ps
CPU time 0.81 seconds
Started Jul 11 05:37:17 PM PDT 24
Finished Jul 11 05:37:20 PM PDT 24
Peak memory 206816 kb
Host smart-9d5ca733-067c-4bcb-87ad-7f81aa80e38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372952809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1372952809
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2348833001
Short name T1020
Test name
Test status
Simulation time 14119749 ps
CPU time 0.83 seconds
Started Jul 11 05:36:45 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 206868 kb
Host smart-22406807-17fe-4e24-9b1f-138e9ab3b282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348833001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2348833001
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2996001745
Short name T1003
Test name
Test status
Simulation time 14071746 ps
CPU time 0.86 seconds
Started Jul 11 05:37:17 PM PDT 24
Finished Jul 11 05:37:20 PM PDT 24
Peak memory 206812 kb
Host smart-8db11007-cd2c-4b3a-bdd7-7550dff07763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996001745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2996001745
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.92935138
Short name T1089
Test name
Test status
Simulation time 16543549 ps
CPU time 0.89 seconds
Started Jul 11 05:36:49 PM PDT 24
Finished Jul 11 05:36:54 PM PDT 24
Peak memory 206840 kb
Host smart-d67452b5-51cc-4362-b8ad-3ea86e2acb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92935138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.92935138
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2762463406
Short name T1068
Test name
Test status
Simulation time 32343584 ps
CPU time 0.78 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206740 kb
Host smart-5bd2ebe8-b71c-4f17-8591-b8ba348194ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762463406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2762463406
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.916946714
Short name T1044
Test name
Test status
Simulation time 21606480 ps
CPU time 0.93 seconds
Started Jul 11 05:37:19 PM PDT 24
Finished Jul 11 05:37:22 PM PDT 24
Peak memory 206796 kb
Host smart-e92f5968-1f1e-4448-b775-5f1e76b88238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916946714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.916946714
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3961020505
Short name T1009
Test name
Test status
Simulation time 28418997 ps
CPU time 0.79 seconds
Started Jul 11 05:36:49 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206628 kb
Host smart-0dd5ca6e-21a2-4194-9d98-ff2eb907ff80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961020505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3961020505
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2140530763
Short name T1120
Test name
Test status
Simulation time 28496898 ps
CPU time 0.92 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 207064 kb
Host smart-24e244f9-82b4-4521-9911-7f322d4213df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140530763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2140530763
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.182978755
Short name T1043
Test name
Test status
Simulation time 87581694 ps
CPU time 1.11 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206968 kb
Host smart-7f75939b-f7db-43bf-9052-7ddfd6247728
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182978755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.182978755
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3997376807
Short name T269
Test name
Test status
Simulation time 1318299450 ps
CPU time 7.11 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:37:01 PM PDT 24
Peak memory 206880 kb
Host smart-b96976d8-26e4-4ac9-bd61-a49fe21731dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997376807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3997376807
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2190043770
Short name T1072
Test name
Test status
Simulation time 34180728 ps
CPU time 0.9 seconds
Started Jul 11 05:36:42 PM PDT 24
Finished Jul 11 05:36:45 PM PDT 24
Peak memory 206968 kb
Host smart-653c0fbc-3a12-439b-9bdb-47e07483f59c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190043770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2190043770
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2010935521
Short name T1081
Test name
Test status
Simulation time 48573197 ps
CPU time 1.25 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 215232 kb
Host smart-b6304d02-eaf9-4bc2-a22f-ac7c90f74b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010935521 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2010935521
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2580046263
Short name T276
Test name
Test status
Simulation time 15910969 ps
CPU time 0.78 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 206660 kb
Host smart-50d5e09d-ce10-40ae-8003-a9a31f2bd9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580046263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2580046263
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.675934203
Short name T1059
Test name
Test status
Simulation time 46244011 ps
CPU time 0.9 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206908 kb
Host smart-ac091dc5-1064-4e03-81d3-63ac2f82dd39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675934203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.675934203
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2011925883
Short name T284
Test name
Test status
Simulation time 16914541 ps
CPU time 1.11 seconds
Started Jul 11 05:36:26 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 206876 kb
Host smart-ce45b0a7-65bd-494e-8704-5457973de3fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011925883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2011925883
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2184941500
Short name T1122
Test name
Test status
Simulation time 79653625 ps
CPU time 2.94 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 215152 kb
Host smart-67a8da1b-1059-41d8-850d-8ee91eb5b987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184941500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2184941500
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2129220569
Short name T303
Test name
Test status
Simulation time 169979007 ps
CPU time 2.36 seconds
Started Jul 11 05:36:26 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 206776 kb
Host smart-f07db94e-944f-4bca-978e-e4ef3d9eefc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129220569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2129220569
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.486778325
Short name T1098
Test name
Test status
Simulation time 36339586 ps
CPU time 0.83 seconds
Started Jul 11 05:36:49 PM PDT 24
Finished Jul 11 05:36:54 PM PDT 24
Peak memory 206872 kb
Host smart-75e0554a-77db-4ff9-9f29-7bf72e61d6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486778325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.486778325
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1283112954
Short name T999
Test name
Test status
Simulation time 19433576 ps
CPU time 1.03 seconds
Started Jul 11 05:37:02 PM PDT 24
Finished Jul 11 05:37:05 PM PDT 24
Peak memory 206848 kb
Host smart-ad93258e-fed7-422f-ac0b-33ef6759be34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283112954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1283112954
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3335592889
Short name T1004
Test name
Test status
Simulation time 13074126 ps
CPU time 0.86 seconds
Started Jul 11 05:37:19 PM PDT 24
Finished Jul 11 05:37:22 PM PDT 24
Peak memory 206804 kb
Host smart-39d7cd02-f20a-46bc-ae27-75ac72dc25a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335592889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3335592889
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.738147654
Short name T1041
Test name
Test status
Simulation time 12129432 ps
CPU time 0.84 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206836 kb
Host smart-f81fac4e-f54f-482a-9027-1d376f2a5df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738147654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.738147654
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1051661338
Short name T1088
Test name
Test status
Simulation time 14129720 ps
CPU time 0.83 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 206864 kb
Host smart-2aa29511-129a-4f4a-826e-7091e513ce04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051661338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1051661338
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2265992074
Short name T1079
Test name
Test status
Simulation time 12362488 ps
CPU time 0.83 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206840 kb
Host smart-66c8c42d-9f14-4e90-8f89-59db4af83cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265992074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2265992074
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1148144898
Short name T1012
Test name
Test status
Simulation time 41935073 ps
CPU time 0.82 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 206916 kb
Host smart-81919420-a595-4670-ab32-47bd18d49a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148144898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1148144898
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4199524275
Short name T1015
Test name
Test status
Simulation time 61862323 ps
CPU time 0.82 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 206672 kb
Host smart-c671333f-5d81-4ae3-97a1-ee1d98f0c22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199524275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4199524275
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3333556243
Short name T1037
Test name
Test status
Simulation time 105108534 ps
CPU time 0.87 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206816 kb
Host smart-de1ea6a3-cfeb-410f-9931-ba869c899cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333556243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3333556243
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2537167657
Short name T1027
Test name
Test status
Simulation time 47813249 ps
CPU time 0.82 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 206848 kb
Host smart-92052267-0cee-4661-afd1-cb908eb688a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537167657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2537167657
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4096553643
Short name T1116
Test name
Test status
Simulation time 25115729 ps
CPU time 1.5 seconds
Started Jul 11 05:36:43 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 215300 kb
Host smart-7141be70-a64c-4718-882f-3ab9cc443ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096553643 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4096553643
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1932524260
Short name T1119
Test name
Test status
Simulation time 23319651 ps
CPU time 0.88 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 206884 kb
Host smart-f03abc6d-68fc-4046-a34b-45a6db256852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932524260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1932524260
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.577104774
Short name T1021
Test name
Test status
Simulation time 22637942 ps
CPU time 0.97 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 206832 kb
Host smart-02eb06ca-fc32-4ba6-8576-a02ca84fe773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577104774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.577104774
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1384088147
Short name T282
Test name
Test status
Simulation time 73234929 ps
CPU time 1.09 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206940 kb
Host smart-d7ba88de-d738-4ed8-bea4-609f9a226c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384088147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1384088147
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2802956089
Short name T1126
Test name
Test status
Simulation time 71884781 ps
CPU time 2.54 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 215200 kb
Host smart-d0b529f0-43d6-417c-9605-608f0179eea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802956089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2802956089
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1533497398
Short name T1115
Test name
Test status
Simulation time 745777506 ps
CPU time 1.68 seconds
Started Jul 11 05:36:43 PM PDT 24
Finished Jul 11 05:36:46 PM PDT 24
Peak memory 215316 kb
Host smart-b93c816b-6af6-4eef-85e8-4b8da65ba55f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533497398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1533497398
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1645102301
Short name T1022
Test name
Test status
Simulation time 52148412 ps
CPU time 1.31 seconds
Started Jul 11 05:36:32 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 217984 kb
Host smart-7d0fb2a7-8e07-4fa8-961b-04d440b04e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645102301 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1645102301
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1478957372
Short name T1007
Test name
Test status
Simulation time 21081872 ps
CPU time 0.88 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 206960 kb
Host smart-10658917-52f6-4dd8-9a8a-b745a0fc1601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478957372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1478957372
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3111310499
Short name T1114
Test name
Test status
Simulation time 11018156 ps
CPU time 0.82 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 206900 kb
Host smart-0b951e25-a963-4707-a1cd-000c1f5e30ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111310499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3111310499
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1798867065
Short name T289
Test name
Test status
Simulation time 43287265 ps
CPU time 1.11 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 207040 kb
Host smart-802a7453-fb9f-4586-b1a7-320061ba5a21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798867065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1798867065
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1324152005
Short name T1065
Test name
Test status
Simulation time 107782181 ps
CPU time 3.65 seconds
Started Jul 11 05:36:32 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 215444 kb
Host smart-36b0d7c9-f74b-4e7a-954d-2fddcbe97541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324152005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1324152005
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3783762195
Short name T1094
Test name
Test status
Simulation time 107613930 ps
CPU time 1.57 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 207088 kb
Host smart-7a9c9ff7-42dd-4949-bd72-d5064a20a784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783762195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3783762195
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2088191041
Short name T1108
Test name
Test status
Simulation time 41487917 ps
CPU time 1.56 seconds
Started Jul 11 05:36:26 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 215304 kb
Host smart-87745df2-7b8a-4c17-81d8-5654e2ea43c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088191041 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2088191041
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4188386501
Short name T1034
Test name
Test status
Simulation time 19281703 ps
CPU time 0.86 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:52 PM PDT 24
Peak memory 206788 kb
Host smart-3d1825ee-8275-4655-9795-03b2833b5d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188386501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4188386501
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2629962613
Short name T1107
Test name
Test status
Simulation time 15762076 ps
CPU time 0.92 seconds
Started Jul 11 05:36:34 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 206908 kb
Host smart-fcea00b3-d246-4f34-a3cf-36796f02fa90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629962613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2629962613
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4037768118
Short name T1086
Test name
Test status
Simulation time 35407624 ps
CPU time 1.46 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 207296 kb
Host smart-6b589304-63d8-44b6-9440-b77140df3c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037768118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.4037768118
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.4290713834
Short name T1103
Test name
Test status
Simulation time 69772243 ps
CPU time 2.56 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 215228 kb
Host smart-46b5473e-dadd-4990-951a-38a65878025c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290713834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.4290713834
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3936594458
Short name T1113
Test name
Test status
Simulation time 52734916 ps
CPU time 1.85 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 215336 kb
Host smart-30d9452a-c8ed-42aa-97ed-006f6fdf1a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936594458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3936594458
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1055189358
Short name T1011
Test name
Test status
Simulation time 141949657 ps
CPU time 1.15 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 215148 kb
Host smart-e526915a-2bd5-45bc-a9e1-ae4c2391c94d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055189358 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1055189358
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1559888342
Short name T1101
Test name
Test status
Simulation time 77775629 ps
CPU time 0.88 seconds
Started Jul 11 05:36:47 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 206964 kb
Host smart-7f8324a9-19ef-413c-8d7d-dd79ba87e1c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559888342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1559888342
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2912609818
Short name T1019
Test name
Test status
Simulation time 13560099 ps
CPU time 0.87 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:50 PM PDT 24
Peak memory 206904 kb
Host smart-5f2630ee-59e3-40a1-ba00-01a99a1e58b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912609818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2912609818
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1993638651
Short name T283
Test name
Test status
Simulation time 70757144 ps
CPU time 1.11 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 206888 kb
Host smart-ad1685e3-8d79-4139-a202-fb62efc78f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993638651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1993638651
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1154299556
Short name T1123
Test name
Test status
Simulation time 121070361 ps
CPU time 3.24 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 215244 kb
Host smart-0259836e-e9b2-46c9-8758-4b81e210cff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154299556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1154299556
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4195270961
Short name T1083
Test name
Test status
Simulation time 1012798491 ps
CPU time 2.4 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 207208 kb
Host smart-bb525a87-c65c-439b-bd47-ed6464794195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195270961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4195270961
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3961510245
Short name T1008
Test name
Test status
Simulation time 38113794 ps
CPU time 1.39 seconds
Started Jul 11 05:36:41 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 217788 kb
Host smart-18e11470-599d-44d2-9fef-16ecd2c87519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961510245 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3961510245
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1972343709
Short name T268
Test name
Test status
Simulation time 15125261 ps
CPU time 0.88 seconds
Started Jul 11 05:36:38 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 206928 kb
Host smart-4b8fb838-3ff5-4715-a05c-0ad399adf4d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972343709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1972343709
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1490111119
Short name T1047
Test name
Test status
Simulation time 11267687 ps
CPU time 0.84 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 206844 kb
Host smart-f01535ef-9a0a-4304-af02-a5381d0f21f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490111119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1490111119
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2623822301
Short name T1080
Test name
Test status
Simulation time 19748539 ps
CPU time 1.14 seconds
Started Jul 11 05:36:32 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 207080 kb
Host smart-4dd51350-ff7f-48ed-9d35-599fa3585e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623822301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2623822301
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.490156538
Short name T1118
Test name
Test status
Simulation time 67771930 ps
CPU time 2.39 seconds
Started Jul 11 05:36:46 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 215228 kb
Host smart-4778e271-0707-40b0-b198-a215dcee7b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490156538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.490156538
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1211173474
Short name T1117
Test name
Test status
Simulation time 315472650 ps
CPU time 2.24 seconds
Started Jul 11 05:36:37 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 207000 kb
Host smart-9eb19f7b-3c45-4b81-aaa8-73671d6b404d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211173474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1211173474
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.192471249
Short name T838
Test name
Test status
Simulation time 22956556 ps
CPU time 1.21 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 219868 kb
Host smart-ebd2327a-f200-483f-ba23-3cbb3f5d9f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192471249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.192471249
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1185248171
Short name T717
Test name
Test status
Simulation time 40503794 ps
CPU time 1.09 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:39:04 PM PDT 24
Peak memory 207148 kb
Host smart-e364f051-f80d-492f-9516-a7fd6f91e402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185248171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1185248171
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.172466161
Short name T231
Test name
Test status
Simulation time 30915783 ps
CPU time 1.13 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:39:07 PM PDT 24
Peak memory 217172 kb
Host smart-d2940b0c-5fba-4103-ba42-b94ee73088f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172466161 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.172466161
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2199526804
Short name T184
Test name
Test status
Simulation time 19844494 ps
CPU time 1.13 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 224324 kb
Host smart-2d99ea8e-fba0-4884-8575-bc529866e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199526804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2199526804
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4238560837
Short name T9
Test name
Test status
Simulation time 49397183 ps
CPU time 1.83 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 220300 kb
Host smart-b38720d8-758a-4923-ba3a-dc415dec3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238560837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4238560837
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1528361839
Short name T927
Test name
Test status
Simulation time 26490311 ps
CPU time 1.07 seconds
Started Jul 11 05:38:41 PM PDT 24
Finished Jul 11 05:38:44 PM PDT 24
Peak memory 224284 kb
Host smart-13a7040f-381b-4d54-91b8-69a66c667423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528361839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1528361839
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3325028822
Short name T18
Test name
Test status
Simulation time 262377181 ps
CPU time 4.31 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:39:06 PM PDT 24
Peak memory 235768 kb
Host smart-00b5f5bf-eb69-43e5-af4a-86ee3676821c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325028822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3325028822
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4033554162
Short name T781
Test name
Test status
Simulation time 14684817 ps
CPU time 0.95 seconds
Started Jul 11 05:38:41 PM PDT 24
Finished Jul 11 05:38:43 PM PDT 24
Peak memory 215648 kb
Host smart-a5b25c42-c114-42e6-85d4-5e8b25fcbe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033554162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4033554162
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.978850039
Short name T383
Test name
Test status
Simulation time 350337791 ps
CPU time 4.28 seconds
Started Jul 11 05:38:41 PM PDT 24
Finished Jul 11 05:38:47 PM PDT 24
Peak memory 217500 kb
Host smart-3843270c-e2e4-4ff8-9370-749dd930a6ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978850039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.978850039
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.2698119425
Short name T431
Test name
Test status
Simulation time 15039659 ps
CPU time 1.01 seconds
Started Jul 11 05:39:10 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 206948 kb
Host smart-278e0cfa-8175-472d-99c8-fb6bfaa0131e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698119425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2698119425
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.385748795
Short name T179
Test name
Test status
Simulation time 13922778 ps
CPU time 0.89 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 216616 kb
Host smart-77de8eb0-6609-4187-9c83-4fc139935898
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385748795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.385748795
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.905428206
Short name T481
Test name
Test status
Simulation time 25629794 ps
CPU time 0.98 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:39:08 PM PDT 24
Peak memory 219956 kb
Host smart-fac57ada-36b0-4861-a6a9-a0a09cfb20bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905428206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.905428206
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.366170271
Short name T883
Test name
Test status
Simulation time 67328803 ps
CPU time 1.17 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:39:03 PM PDT 24
Peak memory 219316 kb
Host smart-c58c6c60-6b5f-4446-8a91-f6a04e6cd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366170271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.366170271
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2154443742
Short name T87
Test name
Test status
Simulation time 28262874 ps
CPU time 0.86 seconds
Started Jul 11 05:38:46 PM PDT 24
Finished Jul 11 05:38:47 PM PDT 24
Peak memory 216188 kb
Host smart-4374bd92-be81-43b4-b745-9e86f7797f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154443742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2154443742
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1518577593
Short name T26
Test name
Test status
Simulation time 72366809 ps
CPU time 0.92 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 207412 kb
Host smart-632cb230-cd14-493d-98e7-4ae0842d6f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518577593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1518577593
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.34718350
Short name T52
Test name
Test status
Simulation time 478740000 ps
CPU time 4.64 seconds
Started Jul 11 05:38:49 PM PDT 24
Finished Jul 11 05:38:54 PM PDT 24
Peak memory 236152 kb
Host smart-02b740b3-ce83-441d-bc31-cbef59f0ec11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34718350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.34718350
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1256132841
Short name T653
Test name
Test status
Simulation time 45503121 ps
CPU time 0.91 seconds
Started Jul 11 05:38:41 PM PDT 24
Finished Jul 11 05:38:43 PM PDT 24
Peak memory 215628 kb
Host smart-fa5d62d2-981e-43b1-936e-db2c21810bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256132841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1256132841
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2885124511
Short name T442
Test name
Test status
Simulation time 180298686 ps
CPU time 2.37 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:39:04 PM PDT 24
Peak memory 217572 kb
Host smart-1e0e157d-3f8f-4ece-a385-e297c65b6ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885124511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2885124511
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1646152290
Short name T696
Test name
Test status
Simulation time 237661304937 ps
CPU time 945.34 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:54:48 PM PDT 24
Peak memory 224252 kb
Host smart-8e26f057-614e-4e6a-bcaf-aa91d1aac1e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646152290 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1646152290
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2375054128
Short name T764
Test name
Test status
Simulation time 24278270 ps
CPU time 1.19 seconds
Started Jul 11 05:39:15 PM PDT 24
Finished Jul 11 05:39:17 PM PDT 24
Peak memory 219080 kb
Host smart-fa6daea0-079a-4fab-ab0c-3b59e11a6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375054128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2375054128
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.3391295396
Short name T113
Test name
Test status
Simulation time 54947805 ps
CPU time 0.95 seconds
Started Jul 11 05:39:13 PM PDT 24
Finished Jul 11 05:39:15 PM PDT 24
Peak memory 219932 kb
Host smart-3f411450-581a-4978-83a1-2c55dcb12220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391295396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3391295396
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2519620102
Short name T535
Test name
Test status
Simulation time 74219369 ps
CPU time 1.78 seconds
Started Jul 11 05:39:12 PM PDT 24
Finished Jul 11 05:39:16 PM PDT 24
Peak memory 219020 kb
Host smart-79169a37-c939-46aa-af14-572d9fe7363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519620102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2519620102
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3815085189
Short name T549
Test name
Test status
Simulation time 22270072 ps
CPU time 1.18 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:16 PM PDT 24
Peak memory 224320 kb
Host smart-0922ec77-4ef8-4d9b-b378-13ba74794d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815085189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3815085189
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1726370557
Short name T397
Test name
Test status
Simulation time 18619779 ps
CPU time 1.01 seconds
Started Jul 11 05:39:15 PM PDT 24
Finished Jul 11 05:39:17 PM PDT 24
Peak memory 215616 kb
Host smart-2ebfa6e0-66ff-427d-a5c7-49ae27944905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726370557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1726370557
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3277997024
Short name T457
Test name
Test status
Simulation time 239518880 ps
CPU time 4.79 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:14 PM PDT 24
Peak memory 217780 kb
Host smart-ff1b8778-3632-4562-8141-68d7697aa9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277997024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3277997024
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.237322806
Short name T918
Test name
Test status
Simulation time 55055675814 ps
CPU time 1424.9 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 06:02:47 PM PDT 24
Peak memory 224560 kb
Host smart-965b5eb4-4d5a-4879-81d1-47238893ae66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237322806 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.237322806
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2372723479
Short name T501
Test name
Test status
Simulation time 95144380 ps
CPU time 1.12 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 219768 kb
Host smart-6f572fc0-9bac-4fef-b460-8fe33ed0550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372723479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2372723479
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2859654904
Short name T615
Test name
Test status
Simulation time 65230813 ps
CPU time 1.26 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 219316 kb
Host smart-1a8672e7-2af7-41cc-bcd9-d41344aa4750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859654904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2859654904
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1414169096
Short name T945
Test name
Test status
Simulation time 132716485 ps
CPU time 1.22 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:23 PM PDT 24
Peak memory 219372 kb
Host smart-3f84eb79-4eaf-4518-a167-fe11ae777997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414169096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1414169096
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2795034104
Short name T228
Test name
Test status
Simulation time 72231028 ps
CPU time 1.09 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 217740 kb
Host smart-7f49c64c-48e3-448a-9556-3aafbfd1b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795034104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2795034104
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.795493014
Short name T264
Test name
Test status
Simulation time 100743577 ps
CPU time 1.28 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 219680 kb
Host smart-fcd7336d-c782-4b12-bece-de9baadf0f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795493014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.795493014
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1760681310
Short name T845
Test name
Test status
Simulation time 98115457 ps
CPU time 1.59 seconds
Started Jul 11 05:41:07 PM PDT 24
Finished Jul 11 05:41:12 PM PDT 24
Peak memory 219140 kb
Host smart-6a5d25a9-5273-49a1-8ed6-543d4845e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760681310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1760681310
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2360997633
Short name T315
Test name
Test status
Simulation time 38894243 ps
CPU time 1.16 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 220196 kb
Host smart-4b794128-c363-4aa0-b1f0-fe99b24012e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360997633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2360997633
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3974774604
Short name T409
Test name
Test status
Simulation time 59193462 ps
CPU time 1.02 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 217760 kb
Host smart-1d589a5b-7790-4fb9-97fb-7429a120657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974774604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3974774604
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1907898791
Short name T366
Test name
Test status
Simulation time 40798699 ps
CPU time 1.07 seconds
Started Jul 11 05:41:27 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 217512 kb
Host smart-f0484875-74ff-4ae8-ad5c-4e1fe00140e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907898791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1907898791
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3284750175
Short name T654
Test name
Test status
Simulation time 143231554 ps
CPU time 1.23 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 218732 kb
Host smart-10c42158-9052-4a58-b261-f400e3c0c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284750175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3284750175
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2807376509
Short name T585
Test name
Test status
Simulation time 59681276 ps
CPU time 1.21 seconds
Started Jul 11 05:41:07 PM PDT 24
Finished Jul 11 05:41:11 PM PDT 24
Peak memory 217528 kb
Host smart-b3491615-3844-4cef-82e2-44e017776f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807376509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2807376509
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.207676492
Short name T246
Test name
Test status
Simulation time 49012874 ps
CPU time 1.25 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:32 PM PDT 24
Peak memory 219228 kb
Host smart-287baed1-2d66-46c1-a5cd-81d27e4c7c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207676492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.207676492
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.50858273
Short name T831
Test name
Test status
Simulation time 43376278 ps
CPU time 1.49 seconds
Started Jul 11 05:41:21 PM PDT 24
Finished Jul 11 05:41:30 PM PDT 24
Peak memory 218672 kb
Host smart-964c9a0b-3508-46e5-992d-7ce4312a4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50858273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.50858273
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1262977696
Short name T711
Test name
Test status
Simulation time 43307738 ps
CPU time 1.19 seconds
Started Jul 11 05:39:08 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 221504 kb
Host smart-603c2389-da51-4bad-807f-614a316aaf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262977696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1262977696
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4239068262
Short name T639
Test name
Test status
Simulation time 36455331 ps
CPU time 0.83 seconds
Started Jul 11 05:39:15 PM PDT 24
Finished Jul 11 05:39:17 PM PDT 24
Peak memory 215280 kb
Host smart-2dba01dd-cdd2-48ad-9939-7755c7f10af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239068262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4239068262
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1878825472
Short name T577
Test name
Test status
Simulation time 19592488 ps
CPU time 0.87 seconds
Started Jul 11 05:39:30 PM PDT 24
Finished Jul 11 05:39:32 PM PDT 24
Peak memory 216320 kb
Host smart-fb3f866a-16c5-4f71-a0f5-a2780e8bbe69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878825472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1878825472
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.64317589
Short name T487
Test name
Test status
Simulation time 31519228 ps
CPU time 1.28 seconds
Started Jul 11 05:39:30 PM PDT 24
Finished Jul 11 05:39:33 PM PDT 24
Peak memory 218752 kb
Host smart-773ef439-430b-40e2-80a0-97dffb496b36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64317589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_dis
able_auto_req_mode.64317589
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1659937331
Short name T132
Test name
Test status
Simulation time 26861967 ps
CPU time 1.24 seconds
Started Jul 11 05:39:08 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 220768 kb
Host smart-d7415cd6-fae8-47fc-88e5-1a7fd60d33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659937331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1659937331
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4285169497
Short name T782
Test name
Test status
Simulation time 87360603 ps
CPU time 1.36 seconds
Started Jul 11 05:39:16 PM PDT 24
Finished Jul 11 05:39:18 PM PDT 24
Peak memory 220408 kb
Host smart-c7a2c2a3-abd0-4592-9876-46d7ee30c064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285169497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4285169497
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3192548660
Short name T756
Test name
Test status
Simulation time 30007119 ps
CPU time 0.89 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 215812 kb
Host smart-93857c30-cc32-4d34-8b6e-e0dcd4f0a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192548660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3192548660
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3790954760
Short name T591
Test name
Test status
Simulation time 139311583 ps
CPU time 0.89 seconds
Started Jul 11 05:39:12 PM PDT 24
Finished Jul 11 05:39:14 PM PDT 24
Peak memory 215636 kb
Host smart-a140cd79-7fc5-43eb-88ba-6322ccdb7462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790954760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3790954760
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2261941663
Short name T983
Test name
Test status
Simulation time 362571103 ps
CPU time 4.06 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:37 PM PDT 24
Peak memory 215160 kb
Host smart-cfa4f073-ff0c-4ba3-8940-002f149cce20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261941663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2261941663
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4250923344
Short name T955
Test name
Test status
Simulation time 55686793478 ps
CPU time 675.07 seconds
Started Jul 11 05:39:30 PM PDT 24
Finished Jul 11 05:50:46 PM PDT 24
Peak memory 224060 kb
Host smart-57851937-b746-4040-b262-8a90435b68f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250923344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4250923344
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1997574783
Short name T291
Test name
Test status
Simulation time 42447187 ps
CPU time 1.07 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:32 PM PDT 24
Peak memory 221016 kb
Host smart-851e8f69-3e4a-452b-a708-89fbbbc7e35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997574783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1997574783
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.447536500
Short name T236
Test name
Test status
Simulation time 41143367 ps
CPU time 1.75 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 217812 kb
Host smart-93f48452-04b3-4ec8-a6df-b7fdc2ce6c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447536500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.447536500
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2887613246
Short name T99
Test name
Test status
Simulation time 71293969 ps
CPU time 1.18 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:23 PM PDT 24
Peak memory 216012 kb
Host smart-b03920f9-c79f-4eb7-a5dd-8b5f240e2d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887613246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2887613246
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3403463725
Short name T432
Test name
Test status
Simulation time 46605754 ps
CPU time 1.11 seconds
Started Jul 11 05:41:22 PM PDT 24
Finished Jul 11 05:41:32 PM PDT 24
Peak memory 217520 kb
Host smart-b7d71b80-2987-47d3-8783-c86478f67716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403463725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3403463725
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1401315026
Short name T899
Test name
Test status
Simulation time 243989192 ps
CPU time 1.12 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 219180 kb
Host smart-8462da9f-7ed8-4e43-85b8-65b5c80155da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401315026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1401315026
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2817882319
Short name T873
Test name
Test status
Simulation time 22739479 ps
CPU time 1.1 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 218600 kb
Host smart-d3a668e1-7f0f-495e-95b4-10f0a37bcf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817882319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2817882319
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2327062543
Short name T827
Test name
Test status
Simulation time 194447432 ps
CPU time 1.5 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 219268 kb
Host smart-757efbc8-9015-4c29-b9b5-bd2b747c5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327062543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2327062543
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1485964810
Short name T510
Test name
Test status
Simulation time 41572616 ps
CPU time 1.21 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 219572 kb
Host smart-08a8310a-075c-40a7-8c57-51976612d318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485964810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1485964810
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3430918984
Short name T476
Test name
Test status
Simulation time 37657655 ps
CPU time 1.5 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:42 PM PDT 24
Peak memory 217492 kb
Host smart-728e5e0b-89f1-48bd-b39e-d48209814d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430918984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3430918984
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.798373797
Short name T437
Test name
Test status
Simulation time 177422825 ps
CPU time 1.28 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 219048 kb
Host smart-c20b09ec-d6bf-4f6c-b18d-f8a8cdb81c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798373797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.798373797
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3960982659
Short name T797
Test name
Test status
Simulation time 140758043 ps
CPU time 1.43 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 217852 kb
Host smart-290b29a6-6d6f-4bb4-910b-73f52d6298d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960982659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3960982659
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1331522074
Short name T842
Test name
Test status
Simulation time 41920324 ps
CPU time 1.18 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 220124 kb
Host smart-23c695f0-2a49-4a55-b114-b71ee7eba956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331522074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1331522074
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1160268943
Short name T715
Test name
Test status
Simulation time 37043072 ps
CPU time 1.38 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:26 PM PDT 24
Peak memory 219732 kb
Host smart-99fafa27-9561-4903-8200-f75f505c9948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160268943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1160268943
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.625285526
Short name T859
Test name
Test status
Simulation time 54904543 ps
CPU time 1.29 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 218412 kb
Host smart-148236c9-699b-4bc6-80b0-c0eebc4a8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625285526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.625285526
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1633421277
Short name T749
Test name
Test status
Simulation time 28228572 ps
CPU time 1.28 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 218860 kb
Host smart-297e381f-9522-41e1-b52f-8a403ab2db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633421277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1633421277
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1132753145
Short name T937
Test name
Test status
Simulation time 38331942 ps
CPU time 1.43 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 217720 kb
Host smart-40c9af88-1b2e-4e76-941e-9768c2d5dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132753145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1132753145
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.920750328
Short name T559
Test name
Test status
Simulation time 42614430 ps
CPU time 1.15 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 221348 kb
Host smart-cf8eb3c6-71ca-4555-ac89-3634dac5ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920750328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.920750328
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.4207876990
Short name T512
Test name
Test status
Simulation time 36346172 ps
CPU time 1.22 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 218868 kb
Host smart-3df349f0-1063-44f5-be74-a2bbcf8fb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207876990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4207876990
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1274073209
Short name T810
Test name
Test status
Simulation time 27241846 ps
CPU time 1.25 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:35 PM PDT 24
Peak memory 220008 kb
Host smart-4d25fe01-6417-4fe1-8d4e-d95d948fdd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274073209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1274073209
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.509639546
Short name T789
Test name
Test status
Simulation time 29148188 ps
CPU time 0.95 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 207008 kb
Host smart-5693119f-afd2-44d2-9b56-65a1f9f6f055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509639546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.509639546
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3063424735
Short name T863
Test name
Test status
Simulation time 74894841 ps
CPU time 1.04 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:39:16 PM PDT 24
Peak memory 218796 kb
Host smart-69b5bc8f-bcad-4d18-a7ed-bb284f5e8fba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063424735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3063424735
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.933417364
Short name T525
Test name
Test status
Simulation time 46468382 ps
CPU time 1.48 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:35 PM PDT 24
Peak memory 218832 kb
Host smart-dea1288c-84a9-4c6e-b0f8-c4f6666b7e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933417364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.933417364
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3424581359
Short name T458
Test name
Test status
Simulation time 43969583 ps
CPU time 0.87 seconds
Started Jul 11 05:39:17 PM PDT 24
Finished Jul 11 05:39:19 PM PDT 24
Peak memory 215508 kb
Host smart-e531796d-827e-429d-90ee-7f1c67b73fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424581359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3424581359
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3191749360
Short name T989
Test name
Test status
Simulation time 23055520 ps
CPU time 0.94 seconds
Started Jul 11 05:39:30 PM PDT 24
Finished Jul 11 05:39:32 PM PDT 24
Peak memory 215592 kb
Host smart-04b6b341-689c-40e3-b65a-547c0e61eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191749360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3191749360
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.924358310
Short name T492
Test name
Test status
Simulation time 338519319 ps
CPU time 6.33 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:27 PM PDT 24
Peak memory 217628 kb
Host smart-5edd853a-f724-43f9-b4bb-954c5d76436d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924358310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.924358310
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2794080377
Short name T214
Test name
Test status
Simulation time 43760568238 ps
CPU time 915.74 seconds
Started Jul 11 05:39:20 PM PDT 24
Finished Jul 11 05:54:37 PM PDT 24
Peak memory 224036 kb
Host smart-8aac838f-5804-4d71-89e3-7c60fef50759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794080377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2794080377
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1973400894
Short name T650
Test name
Test status
Simulation time 187639084 ps
CPU time 1.27 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 220656 kb
Host smart-356ad649-9328-4d89-84ce-fd533ccfad20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973400894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1973400894
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.234295098
Short name T935
Test name
Test status
Simulation time 60264740 ps
CPU time 2.17 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 220288 kb
Host smart-e8f122bf-6a16-48af-b3ba-3b2c0fae59ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234295098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.234295098
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1081700273
Short name T521
Test name
Test status
Simulation time 64425482 ps
CPU time 1.1 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 220208 kb
Host smart-40855f5d-5f3a-44de-b179-2b98323e21c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081700273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1081700273
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3901278420
Short name T618
Test name
Test status
Simulation time 33726851 ps
CPU time 1.33 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 220748 kb
Host smart-22e752b2-2a75-4315-9931-a2fd44f04a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901278420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3901278420
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.27446583
Short name T470
Test name
Test status
Simulation time 66207002 ps
CPU time 0.98 seconds
Started Jul 11 05:41:11 PM PDT 24
Finished Jul 11 05:41:14 PM PDT 24
Peak memory 219412 kb
Host smart-31c532b3-1b2e-4427-8190-ed496e86901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27446583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.27446583
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2863777632
Short name T138
Test name
Test status
Simulation time 173463044 ps
CPU time 1.32 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 218680 kb
Host smart-ab4c6d13-703b-438e-b4bb-43923fc3d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863777632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2863777632
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2384603052
Short name T387
Test name
Test status
Simulation time 82567213 ps
CPU time 1.09 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 219092 kb
Host smart-2dd10c1f-08c3-47d2-9a47-eabff5fa6635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384603052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2384603052
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2376065967
Short name T98
Test name
Test status
Simulation time 76272965 ps
CPU time 1.16 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 219852 kb
Host smart-2e18160d-232b-4cb1-9763-02f1be1b3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376065967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2376065967
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.207103086
Short name T624
Test name
Test status
Simulation time 78523041 ps
CPU time 1.4 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 219340 kb
Host smart-6e7b28e3-ef00-4559-b396-4d781c2dc7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207103086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.207103086
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2436072360
Short name T247
Test name
Test status
Simulation time 23620253 ps
CPU time 1.15 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 215944 kb
Host smart-29e1fc53-9306-4127-ba7b-a30be0633885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436072360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2436072360
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2790220913
Short name T322
Test name
Test status
Simulation time 49250948 ps
CPU time 1.22 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 217520 kb
Host smart-adcca50e-52f9-4b3f-98bb-1f8fdf024fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790220913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2790220913
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2998700892
Short name T730
Test name
Test status
Simulation time 100368108 ps
CPU time 1.21 seconds
Started Jul 11 05:41:28 PM PDT 24
Finished Jul 11 05:41:35 PM PDT 24
Peak memory 220528 kb
Host smart-b1d90a8a-478b-4df9-8a65-752a453132b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998700892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2998700892
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.1114577544
Short name T701
Test name
Test status
Simulation time 185109825 ps
CPU time 1.08 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218980 kb
Host smart-506418df-8a58-4841-ae03-9dddcc49fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114577544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1114577544
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3971558900
Short name T522
Test name
Test status
Simulation time 65347409 ps
CPU time 1.52 seconds
Started Jul 11 05:41:25 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 219024 kb
Host smart-a9fd3f73-15f4-4029-afb3-68af786836b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971558900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3971558900
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3435631467
Short name T631
Test name
Test status
Simulation time 95144419 ps
CPU time 1.21 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 220736 kb
Host smart-ecf9b569-4aca-4f29-98a0-f66d66d3284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435631467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3435631467
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2790855142
Short name T471
Test name
Test status
Simulation time 32108883 ps
CPU time 1.38 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 217720 kb
Host smart-5484d485-d7bf-49d4-b7e1-e3b9057a24d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790855142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2790855142
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1619645465
Short name T608
Test name
Test status
Simulation time 38245468 ps
CPU time 1.06 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:22 PM PDT 24
Peak memory 218804 kb
Host smart-51434519-cedc-4d2b-96a4-3523ccfbd646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619645465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1619645465
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3396476824
Short name T890
Test name
Test status
Simulation time 59161201 ps
CPU time 0.92 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:21 PM PDT 24
Peak memory 207092 kb
Host smart-84760146-a275-4485-a8e9-5c3ce69102a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396476824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3396476824
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1107838665
Short name T713
Test name
Test status
Simulation time 30494710 ps
CPU time 0.84 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 216496 kb
Host smart-79f4332d-0074-4222-9a55-9ded9462511d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107838665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1107838665
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.203528124
Short name T868
Test name
Test status
Simulation time 56988991 ps
CPU time 1 seconds
Started Jul 11 05:39:24 PM PDT 24
Finished Jul 11 05:39:26 PM PDT 24
Peak memory 218100 kb
Host smart-6887e07a-5039-4a7e-95b4-e1192b77a75c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203528124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.203528124
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.2682177473
Short name T680
Test name
Test status
Simulation time 26473433 ps
CPU time 1.16 seconds
Started Jul 11 05:39:23 PM PDT 24
Finished Jul 11 05:39:24 PM PDT 24
Peak memory 217560 kb
Host smart-dd81d6ca-9485-4ab2-b6a8-beb93584bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682177473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2682177473
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1723034632
Short name T849
Test name
Test status
Simulation time 21996538 ps
CPU time 1.12 seconds
Started Jul 11 05:39:12 PM PDT 24
Finished Jul 11 05:39:15 PM PDT 24
Peak memory 215832 kb
Host smart-c7714808-cb78-451e-9b91-d034b7524ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723034632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1723034632
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1617759803
Short name T401
Test name
Test status
Simulation time 31581350 ps
CPU time 0.85 seconds
Started Jul 11 05:39:18 PM PDT 24
Finished Jul 11 05:39:19 PM PDT 24
Peak memory 215380 kb
Host smart-325672e3-1a68-45fc-80a9-d08bab47017c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617759803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1617759803
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3163171594
Short name T507
Test name
Test status
Simulation time 464360440 ps
CPU time 4.69 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:38 PM PDT 24
Peak memory 218368 kb
Host smart-94f3c3a6-050b-4650-b116-90d7e6291aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163171594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3163171594
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1621811237
Short name T211
Test name
Test status
Simulation time 94768198079 ps
CPU time 1588.2 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 06:05:48 PM PDT 24
Peak memory 227580 kb
Host smart-a8401f58-2919-4415-911b-7414882fd46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621811237 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1621811237
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2476910031
Short name T317
Test name
Test status
Simulation time 183847785 ps
CPU time 1.13 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 216024 kb
Host smart-7ce02281-f103-4c1b-b7a5-2872ec60c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476910031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2476910031
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1095735051
Short name T959
Test name
Test status
Simulation time 145412042 ps
CPU time 1.26 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 219000 kb
Host smart-cd905fd6-74fb-4c70-aae5-22008b3a674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095735051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1095735051
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.4030021096
Short name T775
Test name
Test status
Simulation time 78704888 ps
CPU time 1.24 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 218896 kb
Host smart-a170248d-d5e3-4c29-a07f-d3af519d3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030021096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.4030021096
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.269042842
Short name T942
Test name
Test status
Simulation time 72351507 ps
CPU time 1.58 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 219240 kb
Host smart-9c2fc7da-a983-4dbe-8a7e-cebdf4c8e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269042842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.269042842
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4178653133
Short name T925
Test name
Test status
Simulation time 26154657 ps
CPU time 1.23 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219964 kb
Host smart-eef4145d-af0b-4f70-ac01-dc5dcd817065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178653133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4178653133
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3587617350
Short name T678
Test name
Test status
Simulation time 43515294 ps
CPU time 1.56 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 217764 kb
Host smart-0f938e93-657a-402f-96fd-c4bc83a7b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587617350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3587617350
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3436649057
Short name T261
Test name
Test status
Simulation time 87927615 ps
CPU time 1.2 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 218920 kb
Host smart-e07edf60-723c-4a40-899b-b065c7c7b850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436649057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3436649057
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3180404943
Short name T633
Test name
Test status
Simulation time 80002364 ps
CPU time 2.77 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:30 PM PDT 24
Peak memory 220488 kb
Host smart-f7305a00-4a22-4fd0-a851-117694f81951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180404943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3180404943
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.326632310
Short name T919
Test name
Test status
Simulation time 24704692 ps
CPU time 1.13 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 218976 kb
Host smart-b3cb8e8c-5d11-4638-8d00-b702833139eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326632310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.326632310
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1639592932
Short name T971
Test name
Test status
Simulation time 44876323 ps
CPU time 1.57 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 218800 kb
Host smart-e61be54f-f9d5-4a6a-9fbe-7d28c336bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639592932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1639592932
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1993860969
Short name T367
Test name
Test status
Simulation time 68938144 ps
CPU time 1.17 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:26 PM PDT 24
Peak memory 220496 kb
Host smart-e87d7027-f96c-4275-8af6-5e47b765ea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993860969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1993860969
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.293573236
Short name T356
Test name
Test status
Simulation time 33164922 ps
CPU time 1.2 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 217488 kb
Host smart-9040d9b9-ec18-4186-9549-941701f62bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293573236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.293573236
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.343088103
Short name T578
Test name
Test status
Simulation time 40685120 ps
CPU time 1.17 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 220928 kb
Host smart-18daccdd-381e-4966-b615-8b50f8f41526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343088103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.343088103
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.769793329
Short name T493
Test name
Test status
Simulation time 39106612 ps
CPU time 1.06 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 217956 kb
Host smart-fdb671dc-8cb6-452f-bad6-8871412bc1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769793329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.769793329
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2598638674
Short name T888
Test name
Test status
Simulation time 109391340 ps
CPU time 1.2 seconds
Started Jul 11 05:41:21 PM PDT 24
Finished Jul 11 05:41:31 PM PDT 24
Peak memory 218988 kb
Host smart-3afed403-7139-436c-8945-bf8e1e1d5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598638674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2598638674
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3217514691
Short name T913
Test name
Test status
Simulation time 22475645 ps
CPU time 1.17 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219848 kb
Host smart-294234c9-1582-4469-8e11-2ff5c6254403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217514691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3217514691
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1102594286
Short name T671
Test name
Test status
Simulation time 124867718 ps
CPU time 1.36 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 219164 kb
Host smart-4829b8c2-93bc-44c1-8c75-5f6d0e4f2e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102594286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1102594286
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.926401434
Short name T452
Test name
Test status
Simulation time 105802445 ps
CPU time 1.18 seconds
Started Jul 11 05:41:45 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 218952 kb
Host smart-ab6d7517-7695-4fb6-a40d-e1d088bb9c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926401434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.926401434
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2764336616
Short name T368
Test name
Test status
Simulation time 31216263 ps
CPU time 1.09 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 217536 kb
Host smart-68e333c9-2d06-40c6-b8c8-e4249e0cda8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764336616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2764336616
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3263859071
Short name T813
Test name
Test status
Simulation time 78747603 ps
CPU time 1.18 seconds
Started Jul 11 05:39:20 PM PDT 24
Finished Jul 11 05:39:22 PM PDT 24
Peak memory 215960 kb
Host smart-bee07c31-8894-47bc-a585-19857cec41a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263859071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3263859071
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1372483176
Short name T746
Test name
Test status
Simulation time 22739977 ps
CPU time 0.86 seconds
Started Jul 11 05:39:23 PM PDT 24
Finished Jul 11 05:39:25 PM PDT 24
Peak memory 214944 kb
Host smart-4a639b03-ca5d-4d16-8745-6d764142cb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372483176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1372483176
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1171726980
Short name T144
Test name
Test status
Simulation time 13732183 ps
CPU time 0.92 seconds
Started Jul 11 05:39:23 PM PDT 24
Finished Jul 11 05:39:24 PM PDT 24
Peak memory 215820 kb
Host smart-bdf8c539-85d5-41b6-b12c-15257df1898a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171726980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1171726980
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2541844169
Short name T662
Test name
Test status
Simulation time 35712224 ps
CPU time 0.84 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:20 PM PDT 24
Peak memory 219416 kb
Host smart-3e423e45-508c-46c4-a457-ee997d12cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541844169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2541844169
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.4215728623
Short name T463
Test name
Test status
Simulation time 45316424 ps
CPU time 1.69 seconds
Started Jul 11 05:39:17 PM PDT 24
Finished Jul 11 05:39:20 PM PDT 24
Peak memory 218864 kb
Host smart-0fd69dfc-0550-4dad-8fb7-7978ad8c0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215728623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4215728623
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3774397710
Short name T48
Test name
Test status
Simulation time 22434935 ps
CPU time 1.27 seconds
Started Jul 11 05:39:20 PM PDT 24
Finished Jul 11 05:39:22 PM PDT 24
Peak memory 224304 kb
Host smart-e85e3fb5-f63a-41fa-9efc-87f548c1ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774397710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3774397710
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2788977834
Short name T642
Test name
Test status
Simulation time 55835825 ps
CPU time 0.98 seconds
Started Jul 11 05:39:18 PM PDT 24
Finished Jul 11 05:39:20 PM PDT 24
Peak memory 215560 kb
Host smart-f6a5295f-a7a8-4662-8318-9cfa21faeede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788977834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2788977834
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1338672933
Short name T266
Test name
Test status
Simulation time 489301149 ps
CPU time 4.5 seconds
Started Jul 11 05:39:24 PM PDT 24
Finished Jul 11 05:39:29 PM PDT 24
Peak memory 216908 kb
Host smart-d2139250-c061-487f-a94b-9894fae3d818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338672933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1338672933
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2061366968
Short name T260
Test name
Test status
Simulation time 81432988455 ps
CPU time 994.99 seconds
Started Jul 11 05:39:14 PM PDT 24
Finished Jul 11 05:55:51 PM PDT 24
Peak memory 224464 kb
Host smart-b468256a-094c-4ed3-a20e-38df7df684c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061366968 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2061366968
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1533829049
Short name T670
Test name
Test status
Simulation time 23456946 ps
CPU time 1.16 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 219124 kb
Host smart-c3aa52e0-e76d-4215-a668-91839a20309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533829049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1533829049
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3648107000
Short name T37
Test name
Test status
Simulation time 153433184 ps
CPU time 1.41 seconds
Started Jul 11 05:41:51 PM PDT 24
Finished Jul 11 05:42:01 PM PDT 24
Peak memory 217696 kb
Host smart-f98c492d-a3c8-4902-a463-9147ff84368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648107000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3648107000
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4005470903
Short name T628
Test name
Test status
Simulation time 31267061 ps
CPU time 1.16 seconds
Started Jul 11 05:41:39 PM PDT 24
Finished Jul 11 05:41:45 PM PDT 24
Peak memory 221088 kb
Host smart-e9a5339f-d143-487d-b6ae-182477a6aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005470903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4005470903
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.389188597
Short name T792
Test name
Test status
Simulation time 43599109 ps
CPU time 1.08 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 220288 kb
Host smart-20431727-63f4-4b68-960d-2c01a48e2292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389188597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.389188597
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2214782048
Short name T684
Test name
Test status
Simulation time 72643396 ps
CPU time 1.3 seconds
Started Jul 11 05:41:39 PM PDT 24
Finished Jul 11 05:41:45 PM PDT 24
Peak memory 219104 kb
Host smart-acc3c085-81cd-48d4-a904-79afe3e3f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214782048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2214782048
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4028752072
Short name T379
Test name
Test status
Simulation time 46599556 ps
CPU time 1.7 seconds
Started Jul 11 05:41:45 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 220576 kb
Host smart-b0320132-4b28-4516-9022-a6d5ca08b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028752072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4028752072
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1467197267
Short name T508
Test name
Test status
Simulation time 52130588 ps
CPU time 1.6 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 219056 kb
Host smart-2105b0f7-cd16-4c65-ae6c-c011f6460a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467197267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1467197267
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1875305165
Short name T514
Test name
Test status
Simulation time 41188253 ps
CPU time 1.17 seconds
Started Jul 11 05:41:33 PM PDT 24
Finished Jul 11 05:41:38 PM PDT 24
Peak memory 219216 kb
Host smart-96707b5f-2cc9-4320-be13-8ce046ddfef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875305165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1875305165
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.420288836
Short name T787
Test name
Test status
Simulation time 23974136 ps
CPU time 1.19 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 217652 kb
Host smart-0c84b669-e012-4a63-853f-38952dc8d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420288836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.420288836
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3075334330
Short name T966
Test name
Test status
Simulation time 48247038 ps
CPU time 1.54 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 218804 kb
Host smart-407aaede-53e2-4ccd-9a7d-aec803c17ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075334330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3075334330
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1073739946
Short name T882
Test name
Test status
Simulation time 40554270 ps
CPU time 1.17 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 220240 kb
Host smart-001dc88a-3004-4553-a356-6af4b8310d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073739946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1073739946
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3359861531
Short name T594
Test name
Test status
Simulation time 238768347 ps
CPU time 1.23 seconds
Started Jul 11 05:41:34 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 217540 kb
Host smart-bc48385d-5b3e-4f98-bb5a-204ea0322219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359861531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3359861531
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1672175856
Short name T703
Test name
Test status
Simulation time 56765825 ps
CPU time 1.23 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 217704 kb
Host smart-064a10ea-c3dd-41a5-9643-13dd0cbafa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672175856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1672175856
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2882633505
Short name T292
Test name
Test status
Simulation time 29390896 ps
CPU time 1.28 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 220044 kb
Host smart-e449ba03-fb77-417f-9ead-8ab2113c6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882633505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2882633505
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.179072909
Short name T369
Test name
Test status
Simulation time 15717168 ps
CPU time 0.97 seconds
Started Jul 11 05:39:40 PM PDT 24
Finished Jul 11 05:39:41 PM PDT 24
Peak memory 207056 kb
Host smart-cc185d90-3d13-4d93-b84c-769820f84b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179072909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.179072909
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.764427524
Short name T496
Test name
Test status
Simulation time 19177623 ps
CPU time 0.86 seconds
Started Jul 11 05:39:40 PM PDT 24
Finished Jul 11 05:39:42 PM PDT 24
Peak memory 215656 kb
Host smart-2fa9894d-0481-49a3-9198-184a6a9cb9b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764427524 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.764427524
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2110558283
Short name T908
Test name
Test status
Simulation time 73468053 ps
CPU time 1.29 seconds
Started Jul 11 05:39:42 PM PDT 24
Finished Jul 11 05:39:45 PM PDT 24
Peak memory 217116 kb
Host smart-94c7ce17-c70f-4e08-ba72-5765654c4736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110558283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2110558283
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2366559634
Short name T192
Test name
Test status
Simulation time 31523147 ps
CPU time 0.88 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:58 PM PDT 24
Peak memory 218740 kb
Host smart-40eab74e-ca72-4e54-80a4-8a1a593621dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366559634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2366559634
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.997099421
Short name T539
Test name
Test status
Simulation time 48077392 ps
CPU time 1.4 seconds
Started Jul 11 05:39:22 PM PDT 24
Finished Jul 11 05:39:24 PM PDT 24
Peak memory 219004 kb
Host smart-f2b55967-e01d-4150-b8d7-142dacefd552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997099421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.997099421
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.937308448
Short name T86
Test name
Test status
Simulation time 20231403 ps
CPU time 1.04 seconds
Started Jul 11 05:39:19 PM PDT 24
Finished Jul 11 05:39:21 PM PDT 24
Peak memory 216124 kb
Host smart-8ea51d30-437e-4645-a65f-4561e725201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937308448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.937308448
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2353858129
Short name T551
Test name
Test status
Simulation time 15602043 ps
CPU time 0.95 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 215604 kb
Host smart-f2ece2a6-249f-4ff9-97aa-1098f90b6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353858129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2353858129
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3401519719
Short name T826
Test name
Test status
Simulation time 373090362 ps
CPU time 2.54 seconds
Started Jul 11 05:39:23 PM PDT 24
Finished Jul 11 05:39:27 PM PDT 24
Peak memory 215588 kb
Host smart-bbd250d5-d355-4be8-b19c-f3dff470624a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401519719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3401519719
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4272050454
Short name T673
Test name
Test status
Simulation time 995405064857 ps
CPU time 1873.66 seconds
Started Jul 11 05:39:20 PM PDT 24
Finished Jul 11 06:10:35 PM PDT 24
Peak memory 228976 kb
Host smart-5dbe865a-530d-48d1-9c1e-36675d65e6c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272050454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4272050454
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2102893053
Short name T307
Test name
Test status
Simulation time 73942129 ps
CPU time 1.11 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 220228 kb
Host smart-d4f06417-239a-4799-b4b6-c5459990c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102893053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2102893053
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.385139181
Short name T335
Test name
Test status
Simulation time 71417867 ps
CPU time 1.19 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 219812 kb
Host smart-286e6b70-a824-4b38-95e7-7b72b38ca817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385139181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.385139181
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3383736874
Short name T96
Test name
Test status
Simulation time 92299056 ps
CPU time 1.22 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 220252 kb
Host smart-3f08d954-6548-4169-a061-920776cb0ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383736874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3383736874
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2389629796
Short name T378
Test name
Test status
Simulation time 27861152 ps
CPU time 1.25 seconds
Started Jul 11 05:41:26 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 217620 kb
Host smart-2c83794e-6a0b-4fe3-bfda-cbabec254ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389629796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2389629796
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.982325568
Short name T977
Test name
Test status
Simulation time 27538412 ps
CPU time 1.14 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 220212 kb
Host smart-b0352960-b770-4779-aa8b-d4dcba4c007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982325568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.982325568
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4190723017
Short name T807
Test name
Test status
Simulation time 71268697 ps
CPU time 1.62 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 219024 kb
Host smart-14aac516-85fd-4501-9903-b2e4e095babe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190723017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4190723017
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2969508643
Short name T166
Test name
Test status
Simulation time 24629151 ps
CPU time 1.13 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:48 PM PDT 24
Peak memory 219068 kb
Host smart-6271245c-78b9-4f97-9d62-ac65a4c3ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969508643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2969508643
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1267410193
Short name T541
Test name
Test status
Simulation time 28504815 ps
CPU time 1.17 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 217556 kb
Host smart-c023e077-7920-4e48-b2a8-9d3de94ba029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267410193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1267410193
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4054634618
Short name T154
Test name
Test status
Simulation time 50270245 ps
CPU time 1.16 seconds
Started Jul 11 05:41:30 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 219088 kb
Host smart-2277740f-0b73-44af-adaf-8be503c07cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054634618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4054634618
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3013484415
Short name T399
Test name
Test status
Simulation time 63720071 ps
CPU time 1.53 seconds
Started Jul 11 05:41:35 PM PDT 24
Finished Jul 11 05:41:40 PM PDT 24
Peak memory 219172 kb
Host smart-a5aa9687-3eb6-44ea-9428-f824ef774e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013484415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3013484415
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2298229476
Short name T92
Test name
Test status
Simulation time 116376233 ps
CPU time 1.16 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 218804 kb
Host smart-1a52e958-03b7-4617-9600-6f2220be4811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298229476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2298229476
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1588613858
Short name T351
Test name
Test status
Simulation time 26842248 ps
CPU time 1.15 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:50 PM PDT 24
Peak memory 220192 kb
Host smart-64d0bbbc-ebda-4026-99fb-e2f3ec16a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588613858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1588613858
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.654527302
Short name T839
Test name
Test status
Simulation time 70352434 ps
CPU time 1.15 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 220644 kb
Host smart-04c2a9a7-a803-4bf6-bafa-4086f8d8c056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654527302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.654527302
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3084950908
Short name T490
Test name
Test status
Simulation time 62826949 ps
CPU time 1.05 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:04 PM PDT 24
Peak memory 217612 kb
Host smart-aed09d06-4fbc-4252-a37e-b4c1a483396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084950908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3084950908
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1389579227
Short name T118
Test name
Test status
Simulation time 47506017 ps
CPU time 1.17 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 219052 kb
Host smart-1391f0ab-daba-44b9-8ca2-e0b0d791a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389579227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1389579227
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.472446427
Short name T933
Test name
Test status
Simulation time 286004839 ps
CPU time 3.58 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 220560 kb
Host smart-18d6ade7-ac75-4a97-b4f4-0fea8bc53b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472446427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.472446427
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2683706265
Short name T120
Test name
Test status
Simulation time 97097277 ps
CPU time 1.3 seconds
Started Jul 11 05:41:25 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 216024 kb
Host smart-cc3a7e1b-fa4f-4efd-85c3-d84e58912cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683706265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2683706265
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1672789674
Short name T446
Test name
Test status
Simulation time 192803942 ps
CPU time 1.08 seconds
Started Jul 11 05:41:34 PM PDT 24
Finished Jul 11 05:41:38 PM PDT 24
Peak memory 217512 kb
Host smart-5785a896-0455-40f5-b1bc-a2e36d0c5716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672789674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1672789674
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4261389103
Short name T803
Test name
Test status
Simulation time 299935185 ps
CPU time 1.22 seconds
Started Jul 11 05:41:26 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 220112 kb
Host smart-9d9d8872-e066-4962-a543-eddb3478f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261389103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4261389103
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3550165104
Short name T408
Test name
Test status
Simulation time 131050274 ps
CPU time 1.95 seconds
Started Jul 11 05:41:30 PM PDT 24
Finished Jul 11 05:41:37 PM PDT 24
Peak memory 219928 kb
Host smart-dc06623c-6c03-4d10-8e2b-ec3d764a9e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550165104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3550165104
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.581931272
Short name T244
Test name
Test status
Simulation time 27714145 ps
CPU time 1.22 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 218720 kb
Host smart-26314163-dc07-434f-a4ea-144033d546c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581931272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.581931272
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.4243107935
Short name T390
Test name
Test status
Simulation time 67916086 ps
CPU time 0.97 seconds
Started Jul 11 05:39:42 PM PDT 24
Finished Jul 11 05:39:44 PM PDT 24
Peak memory 215248 kb
Host smart-c22a3f09-b11c-4d40-b73d-4e1eb7318aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243107935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4243107935
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4218012448
Short name T548
Test name
Test status
Simulation time 14682623 ps
CPU time 0.88 seconds
Started Jul 11 05:39:40 PM PDT 24
Finished Jul 11 05:39:42 PM PDT 24
Peak memory 216484 kb
Host smart-59684654-bc00-46a4-bcc3-552b44bb2965
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218012448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4218012448
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3103108815
Short name T290
Test name
Test status
Simulation time 27101783 ps
CPU time 1.07 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 218724 kb
Host smart-b229e564-e5c6-47c0-b6a8-3f23610f0191
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103108815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3103108815
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1836869118
Short name T17
Test name
Test status
Simulation time 18881677 ps
CPU time 1.06 seconds
Started Jul 11 05:39:37 PM PDT 24
Finished Jul 11 05:39:39 PM PDT 24
Peak memory 224252 kb
Host smart-525bfc9b-cb93-46db-8290-36d0f0f82a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836869118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1836869118
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3915507531
Short name T500
Test name
Test status
Simulation time 77958978 ps
CPU time 2.29 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:59 PM PDT 24
Peak memory 220104 kb
Host smart-d4f39523-fab0-42b0-ada3-c37abaaa0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915507531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3915507531
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1756258841
Short name T860
Test name
Test status
Simulation time 94634499 ps
CPU time 0.95 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:59 PM PDT 24
Peak memory 224144 kb
Host smart-08999f9d-79ff-4f68-8af3-d381d527bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756258841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1756258841
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4247279823
Short name T779
Test name
Test status
Simulation time 30260421 ps
CPU time 0.99 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:39:43 PM PDT 24
Peak memory 215660 kb
Host smart-b42f04a9-5986-4fbc-b934-b5bc56ca7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247279823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4247279823
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.486242267
Short name T233
Test name
Test status
Simulation time 2117299328 ps
CPU time 5.12 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:39:48 PM PDT 24
Peak memory 217696 kb
Host smart-a854b07d-6562-4fb9-a125-ea924dc2ee60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486242267 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.486242267
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.624653634
Short name T216
Test name
Test status
Simulation time 27171262147 ps
CPU time 631.48 seconds
Started Jul 11 05:39:53 PM PDT 24
Finished Jul 11 05:50:26 PM PDT 24
Peak memory 224000 kb
Host smart-0a190d52-cff1-49b3-8062-d776c219cbee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624653634 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.624653634
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2707676058
Short name T707
Test name
Test status
Simulation time 43597604 ps
CPU time 1.18 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:53 PM PDT 24
Peak memory 218980 kb
Host smart-a5535d03-52c9-4aec-b2a1-7305f2bd121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707676058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2707676058
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.170705109
Short name T468
Test name
Test status
Simulation time 88652378 ps
CPU time 1.21 seconds
Started Jul 11 05:41:26 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 220000 kb
Host smart-5d11908c-32f0-4c5a-84d7-4c986ba2225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170705109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.170705109
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3689686489
Short name T794
Test name
Test status
Simulation time 68540830 ps
CPU time 1.05 seconds
Started Jul 11 05:41:26 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 218812 kb
Host smart-0ad8c210-d3bc-47cc-8db2-ec12d38c59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689686489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3689686489
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1104311022
Short name T571
Test name
Test status
Simulation time 220603654 ps
CPU time 3.12 seconds
Started Jul 11 05:41:36 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 217872 kb
Host smart-fabb6996-70bb-4a41-8aa8-25f487d3ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104311022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1104311022
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2087168697
Short name T456
Test name
Test status
Simulation time 27676032 ps
CPU time 1.24 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219516 kb
Host smart-b1313c61-3913-4c4e-ad19-8cf25228a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087168697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2087168697
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1307360838
Short name T687
Test name
Test status
Simulation time 99319010 ps
CPU time 3.33 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 220580 kb
Host smart-48e7aef3-0e44-4aae-8f53-1c38390d05b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307360838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1307360838
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.144637708
Short name T635
Test name
Test status
Simulation time 134722312 ps
CPU time 1.13 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219940 kb
Host smart-1d682fb6-1a8e-4cd3-8120-4b0c9a1a13f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144637708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.144637708
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/164.edn_alert.15471436
Short name T79
Test name
Test status
Simulation time 81267829 ps
CPU time 1.18 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 218992 kb
Host smart-961e0156-e8d2-4681-a4bb-447d7a52d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15471436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.15471436
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1609352902
Short name T384
Test name
Test status
Simulation time 38130456 ps
CPU time 1.37 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 218676 kb
Host smart-7dd908d3-f5a4-4a08-a016-64d9b65f20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609352902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1609352902
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2604289735
Short name T312
Test name
Test status
Simulation time 246292442 ps
CPU time 1.14 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 219940 kb
Host smart-33c3d662-5d2a-40f5-9aa7-3048be40dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604289735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2604289735
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1967163896
Short name T428
Test name
Test status
Simulation time 239040086 ps
CPU time 1.05 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 217692 kb
Host smart-71cd9348-4658-445a-b946-a6d52e591c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967163896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1967163896
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3443866384
Short name T821
Test name
Test status
Simulation time 29878026 ps
CPU time 1.29 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 220708 kb
Host smart-3d710988-25d6-4c9a-9abe-04b56783dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443866384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3443866384
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1753969207
Short name T70
Test name
Test status
Simulation time 38552465 ps
CPU time 1.44 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 217868 kb
Host smart-529ad551-693a-4598-868d-25bc9c78c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753969207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1753969207
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.151721994
Short name T940
Test name
Test status
Simulation time 49490322 ps
CPU time 1.19 seconds
Started Jul 11 05:41:24 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 220052 kb
Host smart-2c00c7f8-7e62-4115-b5a9-a303c8ba4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151721994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.151721994
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1611189694
Short name T526
Test name
Test status
Simulation time 43715795 ps
CPU time 1.29 seconds
Started Jul 11 05:41:29 PM PDT 24
Finished Jul 11 05:41:36 PM PDT 24
Peak memory 218800 kb
Host smart-db444aa0-c5ef-4493-8520-7a9ba4524574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611189694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1611189694
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2766851530
Short name T105
Test name
Test status
Simulation time 28954908 ps
CPU time 1.31 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 219408 kb
Host smart-a77213cd-8883-4d7c-b20c-b05e9565dd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766851530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2766851530
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3796173400
Short name T902
Test name
Test status
Simulation time 139822583 ps
CPU time 3.13 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:50 PM PDT 24
Peak memory 220584 kb
Host smart-a3bb0500-aab0-4028-8a36-fdf767031790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796173400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3796173400
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2824028773
Short name T75
Test name
Test status
Simulation time 28081663 ps
CPU time 1.12 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:50 PM PDT 24
Peak memory 218924 kb
Host smart-cddfeaef-a98a-41d9-bcbf-86b631964f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824028773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2824028773
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.870449781
Short name T552
Test name
Test status
Simulation time 79008375 ps
CPU time 2.52 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218904 kb
Host smart-566b866c-aaaa-4af6-96df-832fb858d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870449781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.870449781
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1028953146
Short name T238
Test name
Test status
Simulation time 26158181 ps
CPU time 1.26 seconds
Started Jul 11 05:39:53 PM PDT 24
Finished Jul 11 05:39:55 PM PDT 24
Peak memory 220624 kb
Host smart-e41f6990-3726-4446-bb4d-e720f9d30d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028953146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1028953146
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.167414418
Short name T263
Test name
Test status
Simulation time 53514611 ps
CPU time 0.91 seconds
Started Jul 11 05:39:53 PM PDT 24
Finished Jul 11 05:39:55 PM PDT 24
Peak memory 206932 kb
Host smart-50330dd2-bab3-4cb3-8b7b-1741b2c6f176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167414418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.167414418
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.186629689
Short name T818
Test name
Test status
Simulation time 13441344 ps
CPU time 0.89 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:39:42 PM PDT 24
Peak memory 216752 kb
Host smart-a3c8a333-04d1-4cdd-9897-b30a18be304a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186629689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.186629689
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.3001845210
Short name T474
Test name
Test status
Simulation time 20687948 ps
CPU time 1.04 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:58 PM PDT 24
Peak memory 219936 kb
Host smart-a45471b9-b072-4f5f-a5f3-7aa61e6b4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001845210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3001845210
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2646068929
Short name T73
Test name
Test status
Simulation time 163502287 ps
CPU time 1.87 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 219540 kb
Host smart-c6906f81-1f23-4c7b-ace1-b061cca328b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646068929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2646068929
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.317189946
Short name T509
Test name
Test status
Simulation time 32538001 ps
CPU time 0.91 seconds
Started Jul 11 05:39:42 PM PDT 24
Finished Jul 11 05:39:44 PM PDT 24
Peak memory 215720 kb
Host smart-9b2cb605-1df5-4f37-a7ee-8cab1824ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317189946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.317189946
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2301656026
Short name T537
Test name
Test status
Simulation time 21297948 ps
CPU time 0.98 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:39:43 PM PDT 24
Peak memory 215616 kb
Host smart-ce8e5428-dc9e-487a-a278-74be1b6d249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301656026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2301656026
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3732116373
Short name T716
Test name
Test status
Simulation time 389651620 ps
CPU time 4.23 seconds
Started Jul 11 05:39:39 PM PDT 24
Finished Jul 11 05:39:43 PM PDT 24
Peak memory 215600 kb
Host smart-4c593cd0-eeac-44be-bcb1-f5d8c7da61f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732116373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3732116373
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4014313389
Short name T220
Test name
Test status
Simulation time 91412888174 ps
CPU time 500.27 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:48:02 PM PDT 24
Peak memory 224124 kb
Host smart-84368dfa-170e-4fa1-b257-b3d4bb838e4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014313389 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4014313389
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.4183832334
Short name T540
Test name
Test status
Simulation time 38964260 ps
CPU time 1.13 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 220140 kb
Host smart-c868c6ea-bb9b-409f-b1b9-d8b1c87b54a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183832334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.4183832334
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3814527618
Short name T24
Test name
Test status
Simulation time 57792566 ps
CPU time 1.22 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 217724 kb
Host smart-b678a2d9-950b-49c0-8def-cc377887ae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814527618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3814527618
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2319564395
Short name T864
Test name
Test status
Simulation time 21208513 ps
CPU time 1.15 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 219872 kb
Host smart-24df1dec-917f-42ff-adf9-96aae163db9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319564395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2319564395
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3288787107
Short name T40
Test name
Test status
Simulation time 22856407 ps
CPU time 1.29 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 220084 kb
Host smart-de9869c7-6d3b-4f8e-806d-71e08bd50051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288787107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3288787107
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2953747834
Short name T441
Test name
Test status
Simulation time 79227934 ps
CPU time 1.23 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218932 kb
Host smart-13b8528a-3636-4d6e-8a59-77d9aea05da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953747834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2953747834
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2850593652
Short name T418
Test name
Test status
Simulation time 39406942 ps
CPU time 1.42 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 218900 kb
Host smart-cfb2e462-4109-4ef0-b3a9-3ec88858d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850593652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2850593652
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1527179956
Short name T572
Test name
Test status
Simulation time 79457282 ps
CPU time 1.17 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 220944 kb
Host smart-f521a737-6d9f-4947-80f5-3cde6dce8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527179956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1527179956
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.248338771
Short name T448
Test name
Test status
Simulation time 98210254 ps
CPU time 1.11 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 218996 kb
Host smart-90301483-23d7-4211-a716-2cd10503284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248338771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.248338771
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.330661227
Short name T848
Test name
Test status
Simulation time 24323400 ps
CPU time 1.16 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 218680 kb
Host smart-7b5896ff-b49b-486b-a77c-298d0865c1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330661227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.330661227
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2111201132
Short name T451
Test name
Test status
Simulation time 30614016 ps
CPU time 1.22 seconds
Started Jul 11 05:41:34 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 215644 kb
Host smart-d367fbf1-a85c-451a-bcea-b35091532848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111201132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2111201132
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2360930309
Short name T314
Test name
Test status
Simulation time 44632452 ps
CPU time 1.19 seconds
Started Jul 11 05:41:35 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 215972 kb
Host smart-61a9b104-c7d7-47ca-9088-65ec1ed1fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360930309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2360930309
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2251002868
Short name T530
Test name
Test status
Simulation time 44188706 ps
CPU time 1.2 seconds
Started Jul 11 05:41:35 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 217692 kb
Host smart-2dc447ce-19d2-4338-a23d-cea8f6c39982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251002868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2251002868
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1229592582
Short name T188
Test name
Test status
Simulation time 49095233 ps
CPU time 1.26 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 216028 kb
Host smart-56d1391b-7eb2-4883-97d8-367dfb3a8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229592582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1229592582
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2107407401
Short name T777
Test name
Test status
Simulation time 42868529 ps
CPU time 1.59 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218820 kb
Host smart-2cdaad7f-e2a3-4aed-b229-19dfe8ccf946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107407401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2107407401
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3787827792
Short name T97
Test name
Test status
Simulation time 23368937 ps
CPU time 1.21 seconds
Started Jul 11 05:41:38 PM PDT 24
Finished Jul 11 05:41:43 PM PDT 24
Peak memory 220024 kb
Host smart-c52e6b03-1b3c-47be-9011-61a16bc6c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787827792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3787827792
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1491545548
Short name T334
Test name
Test status
Simulation time 114688243 ps
CPU time 1.39 seconds
Started Jul 11 05:41:36 PM PDT 24
Finished Jul 11 05:41:40 PM PDT 24
Peak memory 220268 kb
Host smart-5d47610f-c4b7-43bf-9116-b125b33a149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491545548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1491545548
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3738422665
Short name T901
Test name
Test status
Simulation time 84328394 ps
CPU time 1.26 seconds
Started Jul 11 05:41:35 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 218748 kb
Host smart-4f334541-924f-44d8-8efb-97aa7c6d1bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738422665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3738422665
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.663020501
Short name T340
Test name
Test status
Simulation time 43068469 ps
CPU time 1.6 seconds
Started Jul 11 05:41:46 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218828 kb
Host smart-de861967-fda7-44a7-b7aa-23fad1dc0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663020501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.663020501
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3023256934
Short name T579
Test name
Test status
Simulation time 145388707 ps
CPU time 1.13 seconds
Started Jul 11 05:41:35 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 221136 kb
Host smart-295b34cf-de6e-4a80-a0d5-d6826a450c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023256934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3023256934
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3882330034
Short name T855
Test name
Test status
Simulation time 81029077 ps
CPU time 1.12 seconds
Started Jul 11 05:41:39 PM PDT 24
Finished Jul 11 05:41:44 PM PDT 24
Peak memory 218736 kb
Host smart-4609c8dc-1ddf-48ff-9a8c-625ef1d83f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882330034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3882330034
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3433484152
Short name T733
Test name
Test status
Simulation time 43626150 ps
CPU time 1.13 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 220120 kb
Host smart-84e96c49-21ce-40d6-90f2-6ab79bbb1f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433484152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3433484152
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1869516446
Short name T760
Test name
Test status
Simulation time 21006053 ps
CPU time 1.02 seconds
Started Jul 11 05:40:18 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 207036 kb
Host smart-d82ddd8f-7d91-4b17-9fdc-b931876b9b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869516446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1869516446
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1660137577
Short name T109
Test name
Test status
Simulation time 54273272 ps
CPU time 1.34 seconds
Started Jul 11 05:39:40 PM PDT 24
Finished Jul 11 05:39:42 PM PDT 24
Peak memory 217252 kb
Host smart-90ab3fec-87bc-459f-8928-f98c5dff233d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660137577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1660137577
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2929236154
Short name T150
Test name
Test status
Simulation time 44119366 ps
CPU time 1.15 seconds
Started Jul 11 05:39:41 PM PDT 24
Finished Jul 11 05:39:44 PM PDT 24
Peak memory 220176 kb
Host smart-f7a95ee0-bc30-4d85-8227-e3dccf9a83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929236154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2929236154
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2729890940
Short name T484
Test name
Test status
Simulation time 99077286 ps
CPU time 1.75 seconds
Started Jul 11 05:39:39 PM PDT 24
Finished Jul 11 05:39:41 PM PDT 24
Peak memory 219324 kb
Host smart-99db3956-485e-4b2d-9643-610dba66b816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729890940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2729890940
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1899889157
Short name T434
Test name
Test status
Simulation time 46968810 ps
CPU time 0.84 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 215492 kb
Host smart-54fa3087-91c0-4f44-ba24-3eb383db9cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899889157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1899889157
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.847616454
Short name T675
Test name
Test status
Simulation time 57658933 ps
CPU time 0.91 seconds
Started Jul 11 05:39:47 PM PDT 24
Finished Jul 11 05:39:48 PM PDT 24
Peak memory 215572 kb
Host smart-c5ee13e2-d193-490c-9cc0-ade40b2f9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847616454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.847616454
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.484512940
Short name T407
Test name
Test status
Simulation time 478938900 ps
CPU time 3.87 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 217480 kb
Host smart-c30455d2-d5f5-4bb9-b9e8-d8b6dfd03af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484512940 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.484512940
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2602324675
Short name T218
Test name
Test status
Simulation time 149428629072 ps
CPU time 817.24 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:53:35 PM PDT 24
Peak memory 224076 kb
Host smart-9813842f-312d-4f02-9eb2-07cae5d3d723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602324675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2602324675
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.271367167
Short name T916
Test name
Test status
Simulation time 22631836 ps
CPU time 1.14 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 218712 kb
Host smart-bafe8fd4-0a5c-49d1-8492-4f6bf2402bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271367167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.271367167
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3052473202
Short name T423
Test name
Test status
Simulation time 81644110 ps
CPU time 1.28 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 217728 kb
Host smart-c2a2f842-152c-4f37-9f28-1a5f7837e477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052473202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3052473202
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.421901147
Short name T382
Test name
Test status
Simulation time 31553849 ps
CPU time 1.21 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 219692 kb
Host smart-48bd8a83-0f88-4bcc-97a1-93cdfb4fa526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421901147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.421901147
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1567137729
Short name T685
Test name
Test status
Simulation time 29187495 ps
CPU time 1.24 seconds
Started Jul 11 05:41:36 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 219696 kb
Host smart-622b28f7-438e-491d-8732-d1da44facc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567137729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1567137729
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.902331588
Short name T39
Test name
Test status
Simulation time 92370184 ps
CPU time 1.45 seconds
Started Jul 11 05:41:36 PM PDT 24
Finished Jul 11 05:41:41 PM PDT 24
Peak memory 218984 kb
Host smart-25950bbc-d49e-4502-9994-ea8298d8a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902331588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.902331588
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3067124351
Short name T669
Test name
Test status
Simulation time 65672391 ps
CPU time 1.03 seconds
Started Jul 11 05:41:34 PM PDT 24
Finished Jul 11 05:41:38 PM PDT 24
Peak memory 218652 kb
Host smart-aedc48bd-f8c2-4571-8df1-7923504a0b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067124351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3067124351
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.3596362204
Short name T809
Test name
Test status
Simulation time 48839582 ps
CPU time 1.17 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:50 PM PDT 24
Peak memory 218896 kb
Host smart-673594d4-7135-49ce-bafd-fa40c435c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596362204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3596362204
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3242198576
Short name T784
Test name
Test status
Simulation time 80231773 ps
CPU time 1.29 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:51 PM PDT 24
Peak memory 217640 kb
Host smart-8740a08a-5289-4cd0-b737-208d6441774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242198576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3242198576
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1894702984
Short name T672
Test name
Test status
Simulation time 329622071 ps
CPU time 1.47 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 218952 kb
Host smart-8960da8f-a926-4358-94aa-e0e3a2e8ba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894702984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1894702984
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.310987783
Short name T567
Test name
Test status
Simulation time 82319980 ps
CPU time 1.19 seconds
Started Jul 11 05:41:37 PM PDT 24
Finished Jul 11 05:41:42 PM PDT 24
Peak memory 220612 kb
Host smart-ccec995e-a88b-4938-a224-1946b404af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310987783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.310987783
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2907735501
Short name T204
Test name
Test status
Simulation time 32017591 ps
CPU time 1.25 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219912 kb
Host smart-be68873d-c1c1-4756-b45c-a2aaa84ee9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907735501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2907735501
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.620185076
Short name T683
Test name
Test status
Simulation time 20985880 ps
CPU time 1.05 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 217588 kb
Host smart-92f75b2e-a1cf-4a57-90d3-e300da86508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620185076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.620185076
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1067554499
Short name T751
Test name
Test status
Simulation time 57536111 ps
CPU time 1.43 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 218736 kb
Host smart-273e34e7-8d46-445e-887b-02a8c6e7701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067554499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1067554499
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2956275132
Short name T878
Test name
Test status
Simulation time 44370794 ps
CPU time 1.16 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 218832 kb
Host smart-c589ce80-0ada-43b4-ac8c-29f604322ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956275132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2956275132
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2694231175
Short name T776
Test name
Test status
Simulation time 235391238 ps
CPU time 1.27 seconds
Started Jul 11 05:41:53 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 219836 kb
Host smart-da3268f4-81ca-40bb-a2b7-95204d72e7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694231175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2694231175
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1267843997
Short name T306
Test name
Test status
Simulation time 26720772 ps
CPU time 1.16 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 219224 kb
Host smart-8da28ef7-47bb-403b-b2e8-73906d433e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267843997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1267843997
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2808514098
Short name T430
Test name
Test status
Simulation time 122202741 ps
CPU time 1.6 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:53 PM PDT 24
Peak memory 219300 kb
Host smart-86fce32f-ed78-42fa-abd6-d5846b27eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808514098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2808514098
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2109080400
Short name T54
Test name
Test status
Simulation time 27670607 ps
CPU time 1.24 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 218928 kb
Host smart-f40b4d44-3b83-4c0b-8408-1f7f1da01b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109080400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2109080400
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2291611418
Short name T362
Test name
Test status
Simulation time 40761286 ps
CPU time 0.93 seconds
Started Jul 11 05:39:44 PM PDT 24
Finished Jul 11 05:39:46 PM PDT 24
Peak memory 215480 kb
Host smart-a6e53a6d-936b-4133-9a3c-02fdb94b35c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291611418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2291611418
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1536688780
Short name T857
Test name
Test status
Simulation time 22026837 ps
CPU time 0.86 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 216228 kb
Host smart-fed1437a-c293-4d1f-b4be-2fe39112107d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536688780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1536688780
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3086830472
Short name T697
Test name
Test status
Simulation time 119384778 ps
CPU time 1.06 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:04 PM PDT 24
Peak memory 218468 kb
Host smart-46753acb-4a78-4dde-883f-08b7cd3e63ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086830472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3086830472
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.5919714
Short name T595
Test name
Test status
Simulation time 53859901 ps
CPU time 1.27 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 226040 kb
Host smart-80fed6a4-d57e-410b-ba4b-596509442769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5919714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.5919714
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1001274790
Short name T621
Test name
Test status
Simulation time 99473501 ps
CPU time 1.27 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 218544 kb
Host smart-aae67f28-8e12-4b5c-a981-5a8f101e5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001274790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1001274790
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3766736172
Short name T44
Test name
Test status
Simulation time 22174236 ps
CPU time 1.2 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:18 PM PDT 24
Peak memory 223912 kb
Host smart-365cd449-315b-4f0a-ad2d-c96e8367f4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766736172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3766736172
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.55805557
Short name T2
Test name
Test status
Simulation time 15284375 ps
CPU time 0.96 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:04 PM PDT 24
Peak memory 215588 kb
Host smart-a562bad8-85a6-4d64-be63-51c7ac607ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55805557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.55805557
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2727854279
Short name T372
Test name
Test status
Simulation time 39029861 ps
CPU time 1.18 seconds
Started Jul 11 05:39:44 PM PDT 24
Finished Jul 11 05:39:46 PM PDT 24
Peak memory 217500 kb
Host smart-ab7b2e93-9751-4bfb-abbb-4e84842e262e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727854279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2727854279
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2966654099
Short name T223
Test name
Test status
Simulation time 126484715836 ps
CPU time 1398.09 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 06:03:35 PM PDT 24
Peak memory 223212 kb
Host smart-ad2d17a7-a76c-4866-b2e9-c86900e251eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966654099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2966654099
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3985903488
Short name T78
Test name
Test status
Simulation time 25335460 ps
CPU time 1.15 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 219128 kb
Host smart-04949f79-13ee-46ca-af2e-18d05dacac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985903488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3985903488
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.567461847
Short name T420
Test name
Test status
Simulation time 105776949 ps
CPU time 1.21 seconds
Started Jul 11 05:42:46 PM PDT 24
Finished Jul 11 05:42:54 PM PDT 24
Peak memory 217736 kb
Host smart-4ddd8555-8ce4-4b44-b481-baa0822e4faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567461847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.567461847
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3198103118
Short name T155
Test name
Test status
Simulation time 94575125 ps
CPU time 1.12 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 220060 kb
Host smart-3e86d260-7666-4e6c-a653-22ae78527b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198103118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3198103118
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.699136515
Short name T686
Test name
Test status
Simulation time 113693719 ps
CPU time 1.15 seconds
Started Jul 11 05:41:45 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 217608 kb
Host smart-13bf28d8-9064-4440-b194-0c37bca8176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699136515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.699136515
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3732169370
Short name T729
Test name
Test status
Simulation time 372236601 ps
CPU time 1.33 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219720 kb
Host smart-36da81e3-3a6e-4d7d-8d4f-1d957db7a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732169370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3732169370
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1775235242
Short name T527
Test name
Test status
Simulation time 68036970 ps
CPU time 2.41 seconds
Started Jul 11 05:41:39 PM PDT 24
Finished Jul 11 05:41:45 PM PDT 24
Peak memory 218848 kb
Host smart-1c21336f-763c-4054-a5ff-608a345b161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775235242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1775235242
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3718039369
Short name T523
Test name
Test status
Simulation time 114478707 ps
CPU time 1.17 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 219572 kb
Host smart-5216f735-4fdf-49b2-b51c-a5acf511831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718039369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3718039369
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1171751990
Short name T55
Test name
Test status
Simulation time 24875028 ps
CPU time 1.17 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 217644 kb
Host smart-42e67bf7-bcc3-4165-b473-bcc6abfa98e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171751990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1171751990
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1782108131
Short name T565
Test name
Test status
Simulation time 161821011 ps
CPU time 1.15 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 221728 kb
Host smart-166a3e2a-b2e1-44b7-9d08-864030b98b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782108131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1782108131
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2309957216
Short name T531
Test name
Test status
Simulation time 93329569 ps
CPU time 1.21 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:42:01 PM PDT 24
Peak memory 217504 kb
Host smart-2832bcb4-85c5-40ae-8086-5433733f54a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309957216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2309957216
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2056002753
Short name T395
Test name
Test status
Simulation time 25614786 ps
CPU time 1.23 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 219140 kb
Host smart-04b8744a-5962-4c4c-86ea-c13d486454fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056002753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2056002753
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3804695477
Short name T676
Test name
Test status
Simulation time 51957598 ps
CPU time 1.8 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 218656 kb
Host smart-7a4f60fd-14cb-4eed-88db-7a9822c8aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804695477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3804695477
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.4117406978
Short name T604
Test name
Test status
Simulation time 22933749 ps
CPU time 1.16 seconds
Started Jul 11 05:41:56 PM PDT 24
Finished Jul 11 05:42:04 PM PDT 24
Peak memory 218876 kb
Host smart-1a947ce5-b58b-4210-a5e0-9e34220cc4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117406978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.4117406978
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.4085405519
Short name T341
Test name
Test status
Simulation time 25920536 ps
CPU time 1.21 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 219412 kb
Host smart-3aed12ab-c9ef-4568-9afe-5930296c6ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085405519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.4085405519
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2455581554
Short name T632
Test name
Test status
Simulation time 36883935 ps
CPU time 1.32 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 219748 kb
Host smart-c223bcee-eebe-4863-b542-2eb73a194d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455581554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2455581554
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1643618412
Short name T461
Test name
Test status
Simulation time 51359211 ps
CPU time 1.33 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:50 PM PDT 24
Peak memory 217656 kb
Host smart-222c2509-41e4-49f8-bcb3-57fc0b7b0dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643618412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1643618412
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.653033642
Short name T954
Test name
Test status
Simulation time 272131214 ps
CPU time 1.18 seconds
Started Jul 11 05:42:23 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 218928 kb
Host smart-4a2bbcc2-ebec-415a-a787-ee9b237e6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653033642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.653033642
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2985733811
Short name T768
Test name
Test status
Simulation time 58478720 ps
CPU time 0.97 seconds
Started Jul 11 05:41:52 PM PDT 24
Finished Jul 11 05:42:02 PM PDT 24
Peak memory 217708 kb
Host smart-f22092ff-54ca-4bdd-8b9b-23be169df4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985733811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2985733811
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1413384196
Short name T720
Test name
Test status
Simulation time 38256756 ps
CPU time 1.09 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 219896 kb
Host smart-6816785a-0623-40d2-b7a2-9ae2c717c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413384196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1413384196
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2772590864
Short name T532
Test name
Test status
Simulation time 30032674 ps
CPU time 1.18 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 219036 kb
Host smart-3e616a55-1869-41bb-8ed7-ca801e8a8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772590864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2772590864
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3440722517
Short name T316
Test name
Test status
Simulation time 27669652 ps
CPU time 1.2 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 215980 kb
Host smart-4b89a9fa-3b8c-42b8-8425-7ca7a077c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440722517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3440722517
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1537614354
Short name T936
Test name
Test status
Simulation time 15365713 ps
CPU time 0.91 seconds
Started Jul 11 05:47:11 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 206952 kb
Host smart-7b25099d-e80d-4eff-ac45-afbb0444b9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537614354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1537614354
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4243833592
Short name T513
Test name
Test status
Simulation time 30911401 ps
CPU time 0.82 seconds
Started Jul 11 05:38:49 PM PDT 24
Finished Jul 11 05:38:50 PM PDT 24
Peak memory 216636 kb
Host smart-385aaf63-fd72-4c09-abf2-149e478a0315
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243833592 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4243833592
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3112080219
Short name T817
Test name
Test status
Simulation time 37013832 ps
CPU time 1.16 seconds
Started Jul 11 05:39:01 PM PDT 24
Finished Jul 11 05:39:03 PM PDT 24
Peak memory 217176 kb
Host smart-249f37da-3934-4ce6-b255-4fb1e74908fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112080219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3112080219
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.672092972
Short name T142
Test name
Test status
Simulation time 21537707 ps
CPU time 1.14 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 224344 kb
Host smart-645e9e41-15a6-49ca-91f5-c211570820b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672092972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.672092972
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.165171958
Short name T723
Test name
Test status
Simulation time 63775733 ps
CPU time 1.78 seconds
Started Jul 11 05:38:46 PM PDT 24
Finished Jul 11 05:38:49 PM PDT 24
Peak memory 218884 kb
Host smart-ce80e7b4-b7f8-4cf4-962f-bd49639b0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165171958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.165171958
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2799079743
Short name T780
Test name
Test status
Simulation time 71836857 ps
CPU time 0.96 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 207308 kb
Host smart-cbe32e08-cc85-4ae1-b437-4712219a693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799079743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2799079743
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.537581798
Short name T19
Test name
Test status
Simulation time 505934112 ps
CPU time 4.23 seconds
Started Jul 11 05:39:03 PM PDT 24
Finished Jul 11 05:39:08 PM PDT 24
Peak memory 236336 kb
Host smart-fee006be-e72c-4c14-84ea-1f272122683b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537581798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.537581798
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1099173912
Short name T491
Test name
Test status
Simulation time 50352165 ps
CPU time 0.92 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:54 PM PDT 24
Peak memory 215628 kb
Host smart-a57ee3b4-7b41-4100-9b0f-f1e3080fcf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099173912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1099173912
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1926745102
Short name T262
Test name
Test status
Simulation time 181235171787 ps
CPU time 1128.63 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 224920 kb
Host smart-56047d86-1bcd-4210-8379-a581629f650a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926745102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1926745102
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2304326220
Short name T949
Test name
Test status
Simulation time 24533398 ps
CPU time 1.18 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 220092 kb
Host smart-0dfc0807-ee64-4c22-aeeb-4d3a021b8792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304326220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2304326220
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1186599926
Short name T739
Test name
Test status
Simulation time 20293401 ps
CPU time 0.83 seconds
Started Jul 11 05:39:46 PM PDT 24
Finished Jul 11 05:39:47 PM PDT 24
Peak memory 206860 kb
Host smart-10dea572-0dfc-4cd3-b135-710d77e4d94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186599926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1186599926
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1707681398
Short name T620
Test name
Test status
Simulation time 39910676 ps
CPU time 0.86 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 215704 kb
Host smart-6d82f166-e44a-466e-b732-eec390ab1a22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707681398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1707681398
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2988659592
Short name T651
Test name
Test status
Simulation time 37693112 ps
CPU time 1.13 seconds
Started Jul 11 05:39:44 PM PDT 24
Finished Jul 11 05:39:45 PM PDT 24
Peak memory 218792 kb
Host smart-61166544-4b34-4069-95dc-f7e9f1a5659d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988659592 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2988659592
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.91339149
Short name T141
Test name
Test status
Simulation time 70236919 ps
CPU time 1.13 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 226060 kb
Host smart-ea4be46c-bd61-4980-8b2f-a86149366c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91339149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.91339149
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3639397463
Short name T657
Test name
Test status
Simulation time 31135500 ps
CPU time 1.54 seconds
Started Jul 11 05:39:47 PM PDT 24
Finished Jul 11 05:39:49 PM PDT 24
Peak memory 218896 kb
Host smart-47b62ba0-abee-43ad-af70-8a4f5d9c662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639397463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3639397463
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.806991752
Short name T413
Test name
Test status
Simulation time 21762263 ps
CPU time 1.01 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:17 PM PDT 24
Peak memory 215728 kb
Host smart-241f2065-71d7-4ec5-be48-c79cd4423ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806991752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.806991752
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3117989677
Short name T705
Test name
Test status
Simulation time 36537128 ps
CPU time 0.91 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 215604 kb
Host smart-22521263-5457-427e-a34e-1c16036a00ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117989677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3117989677
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3537766610
Short name T331
Test name
Test status
Simulation time 377496061 ps
CPU time 7 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 215608 kb
Host smart-5381f869-a88c-424f-820f-f326ffbb335a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537766610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3537766610
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3072785482
Short name T737
Test name
Test status
Simulation time 57497540775 ps
CPU time 737.68 seconds
Started Jul 11 05:39:47 PM PDT 24
Finished Jul 11 05:52:06 PM PDT 24
Peak memory 219728 kb
Host smart-41c2a63c-527e-40b7-ae95-d02c9ecb1837
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072785482 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3072785482
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3919319416
Short name T389
Test name
Test status
Simulation time 35761511 ps
CPU time 1.44 seconds
Started Jul 11 05:41:56 PM PDT 24
Finished Jul 11 05:42:04 PM PDT 24
Peak memory 218968 kb
Host smart-9dab3f69-0b57-4225-beb4-c22c102d81f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919319416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3919319416
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2914480678
Short name T886
Test name
Test status
Simulation time 60374622 ps
CPU time 1.42 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 217588 kb
Host smart-2776f0d8-2b78-4fb7-b5b3-0dbdeb9e2b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914480678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2914480678
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3523735582
Short name T359
Test name
Test status
Simulation time 842819758 ps
CPU time 4.98 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 218896 kb
Host smart-6dcb29f3-83c6-4fab-80f6-494a24a43da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523735582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3523735582
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3938194400
Short name T721
Test name
Test status
Simulation time 48816587 ps
CPU time 1.39 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:52 PM PDT 24
Peak memory 218880 kb
Host smart-ecb51e4c-8570-4507-aa99-1dfd307b7ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938194400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3938194400
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4212791449
Short name T612
Test name
Test status
Simulation time 73168103 ps
CPU time 1.27 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:53 PM PDT 24
Peak memory 219040 kb
Host smart-63d9ceb2-23ab-431a-b15e-09e016c8137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212791449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4212791449
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.551919635
Short name T562
Test name
Test status
Simulation time 36906327 ps
CPU time 1.49 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 218900 kb
Host smart-27c2adec-8ecb-43fb-8d6e-251e5283a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551919635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.551919635
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2330305382
Short name T649
Test name
Test status
Simulation time 178696699 ps
CPU time 2.61 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 220380 kb
Host smart-0fb20e41-9589-4056-a139-849fad73b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330305382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2330305382
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1608928562
Short name T772
Test name
Test status
Simulation time 49151316 ps
CPU time 1.92 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:56 PM PDT 24
Peak memory 217904 kb
Host smart-30d84b0d-598f-435c-84ae-df7f3cfd5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608928562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1608928562
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4183896853
Short name T350
Test name
Test status
Simulation time 35091610 ps
CPU time 1.29 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:30 PM PDT 24
Peak memory 219172 kb
Host smart-4d954c37-42d6-4036-bafd-2eaf0ef58a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183896853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4183896853
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3655854971
Short name T679
Test name
Test status
Simulation time 88879621 ps
CPU time 2.37 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 217944 kb
Host smart-002198ca-f8bc-4163-83ab-1762ed594aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655854971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3655854971
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2893954950
Short name T943
Test name
Test status
Simulation time 26251020 ps
CPU time 1.27 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 218936 kb
Host smart-5226ed71-27ce-4cf4-bb54-2cc8735be59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893954950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2893954950
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2201448834
Short name T811
Test name
Test status
Simulation time 20557507 ps
CPU time 1.07 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 215372 kb
Host smart-578b77e3-3f16-4f3a-8b9a-69687ceacb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201448834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2201448834
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2852509224
Short name T909
Test name
Test status
Simulation time 228948813 ps
CPU time 1.06 seconds
Started Jul 11 05:39:54 PM PDT 24
Finished Jul 11 05:39:56 PM PDT 24
Peak memory 217208 kb
Host smart-7c9c5bd0-1404-45e4-8275-c5f4daa2a92b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852509224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2852509224
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2103150795
Short name T929
Test name
Test status
Simulation time 21335163 ps
CPU time 1.11 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 220460 kb
Host smart-64536012-6ebe-4be2-a4c3-2a5613f9d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103150795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2103150795
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3963316917
Short name T941
Test name
Test status
Simulation time 34969869 ps
CPU time 1.29 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:04 PM PDT 24
Peak memory 217652 kb
Host smart-f84e8cfc-3c8f-44da-94c5-dabf1ec5acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963316917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3963316917
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.2906122526
Short name T483
Test name
Test status
Simulation time 18426599 ps
CPU time 1.03 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 215600 kb
Host smart-947d0e6d-9053-4da6-ad24-a829f3727d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906122526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2906122526
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1394429264
Short name T224
Test name
Test status
Simulation time 464618993 ps
CPU time 4.79 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:21 PM PDT 24
Peak memory 217056 kb
Host smart-a8be6f4a-4158-4687-ab52-4b78837a6446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394429264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1394429264
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.4265073236
Short name T682
Test name
Test status
Simulation time 158807862 ps
CPU time 2.42 seconds
Started Jul 11 05:41:59 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 218872 kb
Host smart-bb1c65f2-e8e9-4884-93e6-3fefdc38bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265073236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4265073236
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3720876434
Short name T516
Test name
Test status
Simulation time 23274824 ps
CPU time 1.15 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 217604 kb
Host smart-27cf816a-a529-4a20-ad15-515b9c938c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720876434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3720876434
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4134881088
Short name T614
Test name
Test status
Simulation time 129794699 ps
CPU time 1.41 seconds
Started Jul 11 05:42:23 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 220008 kb
Host smart-b4c8ecbf-d046-4202-8e8c-d11db2209e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134881088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4134881088
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2775088792
Short name T667
Test name
Test status
Simulation time 50080788 ps
CPU time 1.13 seconds
Started Jul 11 05:42:23 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 218900 kb
Host smart-98d803fd-368f-41f3-bf00-198f0914931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775088792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2775088792
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3992969807
Short name T422
Test name
Test status
Simulation time 42686336 ps
CPU time 1.58 seconds
Started Jul 11 05:41:44 PM PDT 24
Finished Jul 11 05:41:54 PM PDT 24
Peak memory 220144 kb
Host smart-8edcea80-6284-40a5-bef3-6fd176326ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992969807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3992969807
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2843985582
Short name T946
Test name
Test status
Simulation time 48786086 ps
CPU time 1.16 seconds
Started Jul 11 05:41:42 PM PDT 24
Finished Jul 11 05:41:49 PM PDT 24
Peak memory 217728 kb
Host smart-bb498dc3-41c0-405c-ab1a-8bc79dcd8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843985582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2843985582
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2504328179
Short name T574
Test name
Test status
Simulation time 118346111 ps
CPU time 1.48 seconds
Started Jul 11 05:41:41 PM PDT 24
Finished Jul 11 05:41:48 PM PDT 24
Peak memory 219448 kb
Host smart-e41b1aab-6e1c-40f6-a10b-1a1293b77b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504328179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2504328179
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.278402799
Short name T895
Test name
Test status
Simulation time 40165517 ps
CPU time 1.12 seconds
Started Jul 11 05:41:45 PM PDT 24
Finished Jul 11 05:41:55 PM PDT 24
Peak memory 217904 kb
Host smart-959f9f35-bb47-4394-974e-4b99646c0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278402799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.278402799
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.416419970
Short name T348
Test name
Test status
Simulation time 44338325 ps
CPU time 1.16 seconds
Started Jul 11 05:42:23 PM PDT 24
Finished Jul 11 05:42:31 PM PDT 24
Peak memory 219820 kb
Host smart-7c509830-8cac-45f7-a753-88da8407efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416419970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.416419970
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3164317664
Short name T648
Test name
Test status
Simulation time 124199819 ps
CPU time 1.25 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 216088 kb
Host smart-f4dc54cd-3ada-4fae-86e0-6900e262991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164317664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3164317664
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1031147312
Short name T755
Test name
Test status
Simulation time 20342268 ps
CPU time 0.86 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:07 PM PDT 24
Peak memory 215028 kb
Host smart-30096b95-56c3-4440-8f38-0b2896fc9ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031147312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1031147312
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3082479668
Short name T815
Test name
Test status
Simulation time 15161688 ps
CPU time 0.85 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 216300 kb
Host smart-3c7d3614-2113-4ed0-a244-d2b57d4f0544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082479668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3082479668
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.2132093017
Short name T731
Test name
Test status
Simulation time 19241461 ps
CPU time 1.09 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:18 PM PDT 24
Peak memory 218816 kb
Host smart-44c9d515-3a9c-4226-b022-77f60228bab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132093017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2132093017
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2450014859
Short name T961
Test name
Test status
Simulation time 55829979 ps
CPU time 1.77 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 218720 kb
Host smart-f75f13fa-756f-45c1-92f9-fd2f91459280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450014859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2450014859
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1416016351
Short name T588
Test name
Test status
Simulation time 24070403 ps
CPU time 1.07 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 215824 kb
Host smart-30fa7035-9a6d-471f-a2b8-8e0167288e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416016351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1416016351
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2231127944
Short name T879
Test name
Test status
Simulation time 15934051 ps
CPU time 0.96 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:39:59 PM PDT 24
Peak memory 215616 kb
Host smart-2b7761fd-a34a-4172-9447-25047ae77689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231127944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2231127944
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1820782342
Short name T374
Test name
Test status
Simulation time 452638911 ps
CPU time 4.93 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 215660 kb
Host smart-32316453-1449-4573-827d-5fb5abe7ce26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820782342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1820782342
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3126205675
Short name T517
Test name
Test status
Simulation time 160158993427 ps
CPU time 1886.26 seconds
Started Jul 11 05:39:54 PM PDT 24
Finished Jul 11 06:11:21 PM PDT 24
Peak memory 225284 kb
Host smart-20352e35-ea0e-491f-9339-71439fabbeee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126205675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3126205675
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1773868955
Short name T342
Test name
Test status
Simulation time 349875470 ps
CPU time 1.41 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 220548 kb
Host smart-b96ec84d-f145-4e3c-9054-64090efe8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773868955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1773868955
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2340252686
Short name T65
Test name
Test status
Simulation time 55102402 ps
CPU time 1.61 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 218672 kb
Host smart-b8f81ac1-be3e-4c0e-ba9f-9236ff026779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340252686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2340252686
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.779290292
Short name T554
Test name
Test status
Simulation time 36499054 ps
CPU time 1.47 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 218976 kb
Host smart-7c2b4ecb-70dc-463d-a28e-8b0746798d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779290292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.779290292
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3258543861
Short name T225
Test name
Test status
Simulation time 58334256 ps
CPU time 1.08 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 218956 kb
Host smart-c91bbc0c-a9f0-4132-af54-1d9fc33fdadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258543861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3258543861
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1928545928
Short name T58
Test name
Test status
Simulation time 32792209 ps
CPU time 1.24 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 219620 kb
Host smart-fba5153d-7bb7-400c-a87d-9052f1bdd40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928545928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1928545928
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3471921343
Short name T22
Test name
Test status
Simulation time 42773693 ps
CPU time 1.7 seconds
Started Jul 11 05:41:49 PM PDT 24
Finished Jul 11 05:42:00 PM PDT 24
Peak memory 218800 kb
Host smart-af2b9dd4-95f8-43ca-812b-c0cf359d223f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471921343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3471921343
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1037354252
Short name T352
Test name
Test status
Simulation time 44034719 ps
CPU time 1.45 seconds
Started Jul 11 05:42:02 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 218808 kb
Host smart-eca44bf3-b3a4-4335-a986-c641a7e81dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037354252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1037354252
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2598935260
Short name T3
Test name
Test status
Simulation time 89504546 ps
CPU time 1.1 seconds
Started Jul 11 05:41:53 PM PDT 24
Finished Jul 11 05:42:02 PM PDT 24
Peak memory 218964 kb
Host smart-9879de9d-61a2-4f10-8ad2-93de377b4abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598935260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2598935260
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1142612740
Short name T249
Test name
Test status
Simulation time 50177804 ps
CPU time 1.13 seconds
Started Jul 11 05:42:02 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 217668 kb
Host smart-7bd4a852-417c-46dc-be7d-db7577fe8689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142612740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1142612740
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3008068352
Short name T227
Test name
Test status
Simulation time 49092854 ps
CPU time 1.2 seconds
Started Jul 11 05:40:22 PM PDT 24
Finished Jul 11 05:40:24 PM PDT 24
Peak memory 220204 kb
Host smart-032d3d61-a9e4-41e6-9673-bb84328af014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008068352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3008068352
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4019527766
Short name T630
Test name
Test status
Simulation time 53279022 ps
CPU time 0.89 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:03 PM PDT 24
Peak memory 206928 kb
Host smart-3191e115-e3b0-4abb-b55d-c28e2cf9b9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019527766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4019527766
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3990491420
Short name T151
Test name
Test status
Simulation time 11866043 ps
CPU time 0.88 seconds
Started Jul 11 05:39:57 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 216588 kb
Host smart-cce71b76-c587-43ab-b252-a3a53e9cf913
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990491420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3990491420
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.405902961
Short name T700
Test name
Test status
Simulation time 66132036 ps
CPU time 1.2 seconds
Started Jul 11 05:39:54 PM PDT 24
Finished Jul 11 05:39:56 PM PDT 24
Peak memory 218640 kb
Host smart-5f640d5b-919a-450b-a990-283a16782835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405902961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.405902961
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.973487662
Short name T951
Test name
Test status
Simulation time 44228851 ps
CPU time 1.41 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:03 PM PDT 24
Peak memory 218512 kb
Host smart-f37d64c3-ce4f-4c98-b8b5-5345f9c14389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973487662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.973487662
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4110630648
Short name T447
Test name
Test status
Simulation time 32841974 ps
CPU time 0.97 seconds
Started Jul 11 05:39:54 PM PDT 24
Finished Jul 11 05:39:56 PM PDT 24
Peak memory 224320 kb
Host smart-4b88bca7-80e2-41bd-90f2-c0448c051b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110630648 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4110630648
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1981644784
Short name T748
Test name
Test status
Simulation time 16566775 ps
CPU time 0.96 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 215604 kb
Host smart-9114b587-dc7f-4fb6-8dee-5c6f1fa38a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981644784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1981644784
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2787954985
Short name T606
Test name
Test status
Simulation time 2235206930 ps
CPU time 5.03 seconds
Started Jul 11 05:39:58 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 217620 kb
Host smart-2b6fbf9d-3175-4ffc-9015-5c34e1fea142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787954985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2787954985
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.162883486
Short name T894
Test name
Test status
Simulation time 51783182785 ps
CPU time 241.75 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:44:04 PM PDT 24
Peak memory 218360 kb
Host smart-4acd6ed3-496e-449c-a271-adc83e40417f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162883486 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.162883486
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2609302029
Short name T990
Test name
Test status
Simulation time 71378238 ps
CPU time 1.78 seconds
Started Jul 11 05:42:04 PM PDT 24
Finished Jul 11 05:42:10 PM PDT 24
Peak memory 218992 kb
Host smart-7b7aadfc-56e2-40ad-b39b-c41c7b754dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609302029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2609302029
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1025065484
Short name T592
Test name
Test status
Simulation time 36048314 ps
CPU time 1.41 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 217504 kb
Host smart-5cd24c0b-e2bd-4781-9a87-0aada4059c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025065484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1025065484
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4002936330
Short name T974
Test name
Test status
Simulation time 102426254 ps
CPU time 1.19 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:14 PM PDT 24
Peak memory 217528 kb
Host smart-e47ad5ce-dffb-48b1-ad7a-2ee02e3dbeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002936330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4002936330
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3163064861
Short name T421
Test name
Test status
Simulation time 33286450 ps
CPU time 1.35 seconds
Started Jul 11 05:41:43 PM PDT 24
Finished Jul 11 05:41:53 PM PDT 24
Peak memory 220364 kb
Host smart-0b4ddf9d-4495-42c0-8bfd-715e5a021706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163064861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3163064861
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.656124011
Short name T425
Test name
Test status
Simulation time 35253822 ps
CPU time 1.52 seconds
Started Jul 11 05:42:45 PM PDT 24
Finished Jul 11 05:42:53 PM PDT 24
Peak memory 220364 kb
Host smart-36743262-827e-48b9-a7e3-27f755c41644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656124011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.656124011
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.774366386
Short name T56
Test name
Test status
Simulation time 68375813 ps
CPU time 1.37 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 218612 kb
Host smart-52efa203-e5bc-425f-a6f7-dd9ef7ba5429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774366386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.774366386
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.909782633
Short name T930
Test name
Test status
Simulation time 38476763 ps
CPU time 1.3 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 220404 kb
Host smart-3a57c328-5f8c-46dd-884f-ab3e98220ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909782633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.909782633
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4132052956
Short name T311
Test name
Test status
Simulation time 42549391 ps
CPU time 1.28 seconds
Started Jul 11 05:42:00 PM PDT 24
Finished Jul 11 05:42:07 PM PDT 24
Peak memory 220232 kb
Host smart-0faac892-15ed-4356-a885-da6b1dfba065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132052956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4132052956
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4022457676
Short name T402
Test name
Test status
Simulation time 50189580 ps
CPU time 1.3 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 220152 kb
Host smart-2512a165-069d-4bae-8404-eeba74ed621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022457676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4022457676
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1954875248
Short name T938
Test name
Test status
Simulation time 86168396 ps
CPU time 1.2 seconds
Started Jul 11 05:40:22 PM PDT 24
Finished Jul 11 05:40:25 PM PDT 24
Peak memory 220684 kb
Host smart-07d73e13-596c-4086-8bb9-3db684d10597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954875248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1954875248
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2688064028
Short name T519
Test name
Test status
Simulation time 14086696 ps
CPU time 0.89 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 207076 kb
Host smart-902d1e93-9b3b-4d68-b6e5-330fdb4c220f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688064028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2688064028
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_err.1374880393
Short name T905
Test name
Test status
Simulation time 29703976 ps
CPU time 1.24 seconds
Started Jul 11 05:40:22 PM PDT 24
Finished Jul 11 05:40:25 PM PDT 24
Peak memory 219928 kb
Host smart-edfe350a-4c8c-4b50-ab09-b6a2cb55d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374880393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1374880393
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.299967239
Short name T607
Test name
Test status
Simulation time 58812736 ps
CPU time 1.4 seconds
Started Jul 11 05:40:09 PM PDT 24
Finished Jul 11 05:40:12 PM PDT 24
Peak memory 217792 kb
Host smart-3af3fcc1-d1be-4687-8092-e078c9bbb367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299967239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.299967239
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1674810405
Short name T100
Test name
Test status
Simulation time 32836730 ps
CPU time 0.86 seconds
Started Jul 11 05:39:57 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 215996 kb
Host smart-90f80429-a654-4cea-943c-01ac97bf1774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674810405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1674810405
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4013567687
Short name T518
Test name
Test status
Simulation time 44467098 ps
CPU time 0.91 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:04 PM PDT 24
Peak memory 215484 kb
Host smart-af1cf215-84c1-4bad-b1dc-257365f6392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013567687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4013567687
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.273916688
Short name T416
Test name
Test status
Simulation time 61485175 ps
CPU time 1.69 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 218860 kb
Host smart-f558d20c-72d9-4c99-9cc3-58c453232ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273916688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.273916688
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4056255434
Short name T880
Test name
Test status
Simulation time 52145706956 ps
CPU time 1382.91 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 224124 kb
Host smart-2a858679-9a4a-4bc4-b6e9-31e102b2fab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056255434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4056255434
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3001610445
Short name T656
Test name
Test status
Simulation time 166599587 ps
CPU time 2.54 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:06 PM PDT 24
Peak memory 220748 kb
Host smart-4789a24b-1958-4df9-9240-3fa486f8f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001610445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3001610445
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.577338725
Short name T709
Test name
Test status
Simulation time 22918372 ps
CPU time 1.18 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 219000 kb
Host smart-ddadaf11-800a-4ca4-bd94-b95fc87b09a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577338725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.577338725
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2254217293
Short name T834
Test name
Test status
Simulation time 41355795 ps
CPU time 1.64 seconds
Started Jul 11 05:42:01 PM PDT 24
Finished Jul 11 05:42:08 PM PDT 24
Peak memory 218860 kb
Host smart-b9aac882-e3b7-4950-8f7a-49a2010c2a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254217293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2254217293
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.99231303
Short name T435
Test name
Test status
Simulation time 52891971 ps
CPU time 1 seconds
Started Jul 11 05:42:09 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 220140 kb
Host smart-11d28a87-9d15-449f-8987-a3f137e096d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99231303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.99231303
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.849317612
Short name T71
Test name
Test status
Simulation time 117385419 ps
CPU time 1.35 seconds
Started Jul 11 05:42:02 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 217732 kb
Host smart-e2c00aff-8298-4fbf-89a6-9979b9c7f7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849317612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.849317612
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.241945825
Short name T870
Test name
Test status
Simulation time 36827906 ps
CPU time 1.36 seconds
Started Jul 11 05:41:48 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 220308 kb
Host smart-dcc40a33-551d-4055-a9f4-055f97caf125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241945825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.241945825
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1587809350
Short name T660
Test name
Test status
Simulation time 33669254 ps
CPU time 1.31 seconds
Started Jul 11 05:42:02 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 217572 kb
Host smart-f779c0d2-b4be-4c64-8484-83407ab10c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587809350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1587809350
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2662853944
Short name T480
Test name
Test status
Simulation time 53540023 ps
CPU time 1.67 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 218580 kb
Host smart-c506bfe5-c950-4b03-b6f3-a4f8fb3cddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662853944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2662853944
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4035456199
Short name T812
Test name
Test status
Simulation time 66111103 ps
CPU time 1.12 seconds
Started Jul 11 05:40:03 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 219028 kb
Host smart-e363ee40-0421-4617-9ff6-6e64171f0c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035456199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4035456199
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2127572670
Short name T355
Test name
Test status
Simulation time 13078970 ps
CPU time 0.9 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 207096 kb
Host smart-dfe1b85d-46c2-47dc-9a69-57ae208c8ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127572670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2127572670
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.981241655
Short name T836
Test name
Test status
Simulation time 52212546 ps
CPU time 0.83 seconds
Started Jul 11 05:39:58 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 216344 kb
Host smart-5bba53e4-c421-4976-a502-d91d1893c101
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981241655 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.981241655
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4033744457
Short name T688
Test name
Test status
Simulation time 27035162 ps
CPU time 1.11 seconds
Started Jul 11 05:39:58 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 218548 kb
Host smart-81e1be64-a030-4086-b9d2-4f46b1f582b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033744457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4033744457
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.688594044
Short name T5
Test name
Test status
Simulation time 20769416 ps
CPU time 1.05 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 219840 kb
Host smart-0b34d4ed-27dd-47c5-8793-a6bc9d75ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688594044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.688594044
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2220779280
Short name T328
Test name
Test status
Simulation time 76818138 ps
CPU time 2.82 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 215464 kb
Host smart-5549381f-e496-488d-aa61-a8a9e4f9f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220779280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2220779280
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2635967010
Short name T101
Test name
Test status
Simulation time 21526800 ps
CPU time 1.13 seconds
Started Jul 11 05:40:06 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 216040 kb
Host smart-b23fefeb-313f-4d76-8dd0-3dc14f2e3182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635967010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2635967010
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2410728705
Short name T371
Test name
Test status
Simulation time 15590257 ps
CPU time 0.95 seconds
Started Jul 11 05:40:01 PM PDT 24
Finished Jul 11 05:40:04 PM PDT 24
Peak memory 215484 kb
Host smart-c93e8843-9f7f-4fc6-945a-bc12d2127b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410728705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2410728705
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2329507792
Short name T900
Test name
Test status
Simulation time 374971980 ps
CPU time 2.82 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 217496 kb
Host smart-89e571f7-56f4-43ce-81d0-fb432d11a2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329507792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2329507792
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3270166394
Short name T213
Test name
Test status
Simulation time 22449458388 ps
CPU time 465.23 seconds
Started Jul 11 05:39:55 PM PDT 24
Finished Jul 11 05:47:43 PM PDT 24
Peak memory 223688 kb
Host smart-1e9f32b6-1df5-4421-9ece-b19b1de22b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270166394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3270166394
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.33038793
Short name T702
Test name
Test status
Simulation time 113519731 ps
CPU time 1.3 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:14 PM PDT 24
Peak memory 219132 kb
Host smart-d65a6f5e-c308-4620-b816-e1301b80f4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33038793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.33038793
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3884153089
Short name T761
Test name
Test status
Simulation time 51667462 ps
CPU time 1.74 seconds
Started Jul 11 05:42:06 PM PDT 24
Finished Jul 11 05:42:12 PM PDT 24
Peak memory 218776 kb
Host smart-0e0bb89e-647b-4418-9183-94a9dbf23570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884153089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3884153089
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2086672012
Short name T454
Test name
Test status
Simulation time 43758676 ps
CPU time 1.09 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:12 PM PDT 24
Peak memory 218800 kb
Host smart-e1658449-3c7e-4db2-b8e5-d0df9aabcbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086672012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2086672012
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1428813321
Short name T444
Test name
Test status
Simulation time 102029377 ps
CPU time 1.23 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 220252 kb
Host smart-aba08e8f-755c-4ee0-b2b3-44dc04dea4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428813321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1428813321
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.770397467
Short name T347
Test name
Test status
Simulation time 67876246 ps
CPU time 1.97 seconds
Started Jul 11 05:41:56 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 217916 kb
Host smart-f280f0d0-5146-47fb-a30d-3ef6641ad0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770397467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.770397467
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3382351296
Short name T469
Test name
Test status
Simulation time 194916359 ps
CPU time 1.88 seconds
Started Jul 11 05:42:09 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 219276 kb
Host smart-2daa4d99-350d-4b03-95dd-bdb1f82ffe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382351296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3382351296
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2343800210
Short name T884
Test name
Test status
Simulation time 362788444 ps
CPU time 1.85 seconds
Started Jul 11 05:42:04 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 218932 kb
Host smart-7ef28164-bff6-4489-8797-f2cd46401dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343800210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2343800210
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.428664543
Short name T494
Test name
Test status
Simulation time 32000590 ps
CPU time 1.31 seconds
Started Jul 11 05:41:51 PM PDT 24
Finished Jul 11 05:42:01 PM PDT 24
Peak memory 218776 kb
Host smart-94e317b7-581e-4c99-9f55-437dd9023a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428664543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.428664543
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2323651239
Short name T339
Test name
Test status
Simulation time 58413725 ps
CPU time 1.33 seconds
Started Jul 11 05:42:03 PM PDT 24
Finished Jul 11 05:42:10 PM PDT 24
Peak memory 219380 kb
Host smart-d70708a8-7be0-44ca-8fb6-64f153ad9fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323651239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2323651239
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3661391705
Short name T110
Test name
Test status
Simulation time 52606124 ps
CPU time 1.29 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 220888 kb
Host smart-4e1482d9-9918-4085-981f-af11b7abc53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661391705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3661391705
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1612049614
Short name T973
Test name
Test status
Simulation time 55583522 ps
CPU time 0.9 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 207040 kb
Host smart-1d6a04f7-b166-429e-852e-3bd1bfdbd2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612049614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1612049614
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3184529194
Short name T910
Test name
Test status
Simulation time 16823732 ps
CPU time 0.85 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 216668 kb
Host smart-934668bf-c2cc-4752-a92a-f7dd104f898b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184529194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3184529194
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2777466011
Short name T505
Test name
Test status
Simulation time 94852630 ps
CPU time 1.15 seconds
Started Jul 11 05:40:06 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 220080 kb
Host smart-88f10ede-2e9d-45b3-b5a9-93e71e4cf757
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777466011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2777466011
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1269838309
Short name T698
Test name
Test status
Simulation time 17772549 ps
CPU time 1.1 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 218780 kb
Host smart-a6f52764-7a5b-4eb6-bfd5-cad2af044945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269838309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1269838309
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.597844483
Short name T460
Test name
Test status
Simulation time 105565866 ps
CPU time 0.94 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 215636 kb
Host smart-c2b1e6f1-e32b-4a67-9a17-ac366cb4175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597844483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.597844483
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1201087828
Short name T958
Test name
Test status
Simulation time 31399484 ps
CPU time 0.95 seconds
Started Jul 11 05:39:57 PM PDT 24
Finished Jul 11 05:40:00 PM PDT 24
Peak memory 215816 kb
Host smart-12cf2ca1-9e2c-4b11-84da-8c1d4096d685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201087828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1201087828
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3480406524
Short name T360
Test name
Test status
Simulation time 26318465 ps
CPU time 0.94 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 215752 kb
Host smart-1c1763cd-7943-446a-84a7-a28cd5932f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480406524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3480406524
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1572876192
Short name T581
Test name
Test status
Simulation time 1584688262 ps
CPU time 3.9 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:16 PM PDT 24
Peak memory 217648 kb
Host smart-5c23d9b8-8c65-4f8b-8c9b-55e326d66906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572876192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1572876192
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3813869287
Short name T221
Test name
Test status
Simulation time 26363510152 ps
CPU time 617.32 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 05:50:21 PM PDT 24
Peak memory 219372 kb
Host smart-38d5e8f8-85b8-4db7-9374-ba362b2df8f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813869287 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3813869287
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.609593253
Short name T791
Test name
Test status
Simulation time 63145542 ps
CPU time 1.31 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 219068 kb
Host smart-f1bda01c-8381-47ee-87d7-8e077ed2efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609593253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.609593253
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.965486970
Short name T613
Test name
Test status
Simulation time 34331701 ps
CPU time 1.68 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 217712 kb
Host smart-66641000-da48-475b-be30-1659e8d749e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965486970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.965486970
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.502612426
Short name T638
Test name
Test status
Simulation time 40877918 ps
CPU time 1.64 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 219048 kb
Host smart-2ad1c2f7-b4f1-4db4-aab3-a67ee8184063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502612426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.502612426
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.376049520
Short name T664
Test name
Test status
Simulation time 150815458 ps
CPU time 2.66 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:15 PM PDT 24
Peak memory 218644 kb
Host smart-1b7fe9e6-e813-4b9e-8642-1cb9de7269ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376049520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.376049520
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1966183228
Short name T801
Test name
Test status
Simulation time 87185730 ps
CPU time 1.2 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:33 PM PDT 24
Peak memory 217500 kb
Host smart-c5e02514-ded6-4e39-9fb7-0d580785b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966183228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1966183228
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2327746956
Short name T765
Test name
Test status
Simulation time 47028996 ps
CPU time 1.81 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 220480 kb
Host smart-dc34c201-3316-4dd0-94fe-51edfef425d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327746956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2327746956
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2203459416
Short name T326
Test name
Test status
Simulation time 138442931 ps
CPU time 3.28 seconds
Started Jul 11 05:41:54 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 220536 kb
Host smart-a2130f21-c59e-4654-9660-00b195aea712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203459416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2203459416
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3598312225
Short name T917
Test name
Test status
Simulation time 44184993 ps
CPU time 1.53 seconds
Started Jul 11 05:41:56 PM PDT 24
Finished Jul 11 05:42:04 PM PDT 24
Peak memory 217688 kb
Host smart-39b19c9f-dbe5-484e-b866-1ac9616fee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598312225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3598312225
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2898125783
Short name T694
Test name
Test status
Simulation time 51064703 ps
CPU time 1.66 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:06 PM PDT 24
Peak memory 218688 kb
Host smart-361753c2-8339-4f90-8af9-5d37693f14d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898125783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2898125783
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1784188596
Short name T464
Test name
Test status
Simulation time 49420455 ps
CPU time 1.18 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:33 PM PDT 24
Peak memory 217564 kb
Host smart-21a3533d-0d88-409f-b117-c793c21a0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784188596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1784188596
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1140905136
Short name T555
Test name
Test status
Simulation time 33697083 ps
CPU time 1.21 seconds
Started Jul 11 05:40:06 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 219008 kb
Host smart-16f5b033-2d3e-4f6a-9138-e176e5d9a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140905136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1140905136
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3587989638
Short name T251
Test name
Test status
Simulation time 15921024 ps
CPU time 1.03 seconds
Started Jul 11 05:40:00 PM PDT 24
Finished Jul 11 05:40:03 PM PDT 24
Peak memory 215176 kb
Host smart-9e1d497c-0267-4669-97c3-2c8520230bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587989638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3587989638
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3282581010
Short name T209
Test name
Test status
Simulation time 12087236 ps
CPU time 0.88 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 216792 kb
Host smart-9bb43e2c-58d8-44e6-aa59-e4a9140ee824
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282581010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3282581010
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1811728467
Short name T637
Test name
Test status
Simulation time 79056311 ps
CPU time 1 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:39:59 PM PDT 24
Peak memory 218560 kb
Host smart-b8cc4181-8bb8-454d-a97f-bf1a62a4cfbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811728467 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1811728467
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2738150242
Short name T914
Test name
Test status
Simulation time 24361925 ps
CPU time 0.94 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:09 PM PDT 24
Peak memory 218944 kb
Host smart-8bf4583b-08d1-42b8-a2a4-176f4761db9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738150242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2738150242
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3832040186
Short name T850
Test name
Test status
Simulation time 262204401 ps
CPU time 1.39 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:02 PM PDT 24
Peak memory 220488 kb
Host smart-429ff56f-f147-41b3-bd0b-4c44b4418e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832040186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3832040186
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.30989960
Short name T912
Test name
Test status
Simulation time 27729789 ps
CPU time 0.9 seconds
Started Jul 11 05:39:58 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 215836 kb
Host smart-c9a38fc1-6279-426e-af3e-b8acbf2adea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30989960 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.30989960
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.27738737
Short name T719
Test name
Test status
Simulation time 17072197 ps
CPU time 0.98 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:07 PM PDT 24
Peak memory 215624 kb
Host smart-e26f2f36-2564-4cf1-91ef-cd6195c5208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27738737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.27738737
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.928179601
Short name T766
Test name
Test status
Simulation time 370902353 ps
CPU time 7.19 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 217740 kb
Host smart-21091811-7918-4f01-9c75-dd0fcf27e0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928179601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.928179601
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1158920956
Short name T896
Test name
Test status
Simulation time 36963693787 ps
CPU time 933.69 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 224096 kb
Host smart-ebebb4bb-920b-41ac-aa24-28acd7c8f8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158920956 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1158920956
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3161058594
Short name T90
Test name
Test status
Simulation time 61701053 ps
CPU time 1.02 seconds
Started Jul 11 05:41:58 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 217704 kb
Host smart-9c297aa2-dafb-4b2e-99e2-70e58ee9f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161058594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3161058594
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4052209255
Short name T346
Test name
Test status
Simulation time 48332479 ps
CPU time 1.73 seconds
Started Jul 11 05:41:54 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 218916 kb
Host smart-cb793d5b-f8bb-4e72-baea-1ce9c8811d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052209255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4052209255
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.4106917727
Short name T906
Test name
Test status
Simulation time 33572639 ps
CPU time 1.37 seconds
Started Jul 11 05:42:16 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 218916 kb
Host smart-b797e832-e33d-4742-ab9b-ed96311f1575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106917727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4106917727
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3899930386
Short name T830
Test name
Test status
Simulation time 43316501 ps
CPU time 1.25 seconds
Started Jul 11 05:42:04 PM PDT 24
Finished Jul 11 05:42:10 PM PDT 24
Peak memory 219544 kb
Host smart-a30a469d-bd81-425b-a64d-2670da0d4aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899930386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3899930386
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2045765676
Short name T13
Test name
Test status
Simulation time 66117131 ps
CPU time 1.38 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 218948 kb
Host smart-84ba55c0-7393-412a-9f07-5cbf9da3116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045765676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2045765676
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3091735115
Short name T987
Test name
Test status
Simulation time 27820928 ps
CPU time 1.42 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 217816 kb
Host smart-e55dffc8-b8d9-43cc-b3e3-452114c54c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091735115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3091735115
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3039603660
Short name T325
Test name
Test status
Simulation time 40122869 ps
CPU time 1.53 seconds
Started Jul 11 05:42:08 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 218628 kb
Host smart-5040046b-d3b5-41cb-8595-15fe90b7c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039603660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3039603660
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2603336116
Short name T529
Test name
Test status
Simulation time 86213493 ps
CPU time 1.17 seconds
Started Jul 11 05:41:52 PM PDT 24
Finished Jul 11 05:42:02 PM PDT 24
Peak memory 217540 kb
Host smart-f4687fd1-655c-4096-9dda-bc2032deeef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603336116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2603336116
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.725683570
Short name T467
Test name
Test status
Simulation time 57932880 ps
CPU time 1.66 seconds
Started Jul 11 05:41:53 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 218836 kb
Host smart-7d5e41dc-e4fb-413f-b110-1940b993c0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725683570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.725683570
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2794665735
Short name T629
Test name
Test status
Simulation time 77451744 ps
CPU time 1.11 seconds
Started Jul 11 05:42:09 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 220336 kb
Host smart-f809b9e4-7e47-43d7-b9d5-71e0465bb15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794665735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2794665735
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1141184698
Short name T172
Test name
Test status
Simulation time 34443321 ps
CPU time 1.05 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 218884 kb
Host smart-9702ee64-4fde-4933-ae74-6cffaa36e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141184698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1141184698
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3239560760
Short name T385
Test name
Test status
Simulation time 46649012 ps
CPU time 0.82 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:09 PM PDT 24
Peak memory 206776 kb
Host smart-29d5f3ad-397a-42d3-ab8e-4c6c715d5588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239560760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3239560760
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.580122395
Short name T201
Test name
Test status
Simulation time 14082053 ps
CPU time 0.97 seconds
Started Jul 11 05:40:19 PM PDT 24
Finished Jul 11 05:40:21 PM PDT 24
Peak memory 216668 kb
Host smart-31d47c71-0f49-4e46-a389-4e20726790d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580122395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.580122395
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.664225865
Short name T584
Test name
Test status
Simulation time 209980283 ps
CPU time 1.26 seconds
Started Jul 11 05:40:19 PM PDT 24
Finished Jul 11 05:40:22 PM PDT 24
Peak memory 218892 kb
Host smart-5fd1f482-2aa5-4869-aee1-ef67d880eacf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664225865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.664225865
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.863923574
Short name T712
Test name
Test status
Simulation time 152402692 ps
CPU time 2.09 seconds
Started Jul 11 05:40:04 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 217820 kb
Host smart-8faabdd6-b4a1-4648-b4f8-7dd026a41099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863923574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.863923574
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.268598442
Short name T34
Test name
Test status
Simulation time 20175276 ps
CPU time 1.14 seconds
Started Jul 11 05:40:14 PM PDT 24
Finished Jul 11 05:40:16 PM PDT 24
Peak memory 216224 kb
Host smart-9d5cc283-f26e-4ae8-ac43-31bd4e8414a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268598442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.268598442
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.839839430
Short name T939
Test name
Test status
Simulation time 15302177 ps
CPU time 0.98 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:09 PM PDT 24
Peak memory 215584 kb
Host smart-21bafd7b-ee46-429a-9e47-fcdc10364d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839839430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.839839430
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1297551731
Short name T482
Test name
Test status
Simulation time 705486083 ps
CPU time 4.12 seconds
Started Jul 11 05:40:14 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 217688 kb
Host smart-4958c063-3b48-4d97-9e60-7224d50b0b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297551731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1297551731
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1686055669
Short name T212
Test name
Test status
Simulation time 230913508449 ps
CPU time 919.64 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 222664 kb
Host smart-e952f168-4c8a-4838-8e03-1ee068ee41f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686055669 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1686055669
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2738825540
Short name T68
Test name
Test status
Simulation time 47850806 ps
CPU time 1.25 seconds
Started Jul 11 05:42:38 PM PDT 24
Finished Jul 11 05:42:44 PM PDT 24
Peak memory 217552 kb
Host smart-a1986aea-dfcd-4d9a-b1f0-92bdf7b1d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738825540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2738825540
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.490435817
Short name T837
Test name
Test status
Simulation time 68771593 ps
CPU time 2.41 seconds
Started Jul 11 05:41:52 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 218876 kb
Host smart-a494c785-a3dc-47d9-8b07-1ed726ff97cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490435817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.490435817
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1318421824
Short name T459
Test name
Test status
Simulation time 52777769 ps
CPU time 1.2 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 220228 kb
Host smart-9e3e9b2f-d2ba-4735-a662-ea9db01c7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318421824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1318421824
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3596198922
Short name T769
Test name
Test status
Simulation time 83312148 ps
CPU time 1.2 seconds
Started Jul 11 05:42:25 PM PDT 24
Finished Jul 11 05:42:33 PM PDT 24
Peak memory 218884 kb
Host smart-972e0508-4ac6-4a0a-9394-72b5905a7739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596198922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3596198922
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3278380326
Short name T805
Test name
Test status
Simulation time 66659219 ps
CPU time 1.46 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 218936 kb
Host smart-a1d75bd9-518b-4cf6-80db-345f7d0e17e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278380326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3278380326
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3147257296
Short name T589
Test name
Test status
Simulation time 30391998 ps
CPU time 1.24 seconds
Started Jul 11 05:42:04 PM PDT 24
Finished Jul 11 05:42:10 PM PDT 24
Peak memory 217648 kb
Host smart-77d5d000-bd0c-4307-8813-94bc4b6542e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147257296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3147257296
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3172146577
Short name T932
Test name
Test status
Simulation time 53199434 ps
CPU time 1.62 seconds
Started Jul 11 05:42:26 PM PDT 24
Finished Jul 11 05:42:33 PM PDT 24
Peak memory 218604 kb
Host smart-e5a336dd-54ac-422f-8293-d4009d6a245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172146577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3172146577
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4178287464
Short name T994
Test name
Test status
Simulation time 75168110 ps
CPU time 1.03 seconds
Started Jul 11 05:42:03 PM PDT 24
Finished Jul 11 05:42:09 PM PDT 24
Peak memory 217672 kb
Host smart-4487b343-92cb-4696-b00e-e2f110e1b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178287464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4178287464
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1723505990
Short name T626
Test name
Test status
Simulation time 78458528 ps
CPU time 1.06 seconds
Started Jul 11 05:42:07 PM PDT 24
Finished Jul 11 05:42:12 PM PDT 24
Peak memory 217460 kb
Host smart-4eee969d-2136-46e2-a1a9-421ed371096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723505990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1723505990
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2250563515
Short name T866
Test name
Test status
Simulation time 48563565 ps
CPU time 1.37 seconds
Started Jul 11 05:41:56 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 218980 kb
Host smart-d1c31f71-f12b-4125-a5ed-13a62e2bd2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250563515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2250563515
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.314194857
Short name T123
Test name
Test status
Simulation time 41590643 ps
CPU time 1.21 seconds
Started Jul 11 05:40:14 PM PDT 24
Finished Jul 11 05:40:16 PM PDT 24
Peak memory 219716 kb
Host smart-55a468b2-d133-495d-b436-d8f5c56cfd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314194857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.314194857
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2742970760
Short name T652
Test name
Test status
Simulation time 19748202 ps
CPU time 1.02 seconds
Started Jul 11 05:40:03 PM PDT 24
Finished Jul 11 05:40:06 PM PDT 24
Peak memory 207104 kb
Host smart-1af227a3-8d38-4f59-bb40-d5b8946429e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742970760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2742970760
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1912564427
Short name T556
Test name
Test status
Simulation time 72454229 ps
CPU time 0.85 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 216600 kb
Host smart-5109455d-df4e-480f-ba03-5ae205d7ed35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912564427 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1912564427
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1636357035
Short name T89
Test name
Test status
Simulation time 106969841 ps
CPU time 1.18 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:22 PM PDT 24
Peak memory 219032 kb
Host smart-c48cd609-6519-441c-bd33-88001c7df52a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636357035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1636357035
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2634115854
Short name T174
Test name
Test status
Simulation time 19292209 ps
CPU time 1.02 seconds
Started Jul 11 05:40:03 PM PDT 24
Finished Jul 11 05:40:06 PM PDT 24
Peak memory 215668 kb
Host smart-8a976e61-6117-4b12-88a8-7d601fdd0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634115854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2634115854
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2639869779
Short name T865
Test name
Test status
Simulation time 27574487 ps
CPU time 1.25 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:22 PM PDT 24
Peak memory 218908 kb
Host smart-a980f4a8-d2b6-4105-86b1-1997adfd718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639869779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2639869779
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2645682282
Short name T29
Test name
Test status
Simulation time 27122809 ps
CPU time 0.82 seconds
Started Jul 11 05:39:59 PM PDT 24
Finished Jul 11 05:40:01 PM PDT 24
Peak memory 215948 kb
Host smart-9129eb2f-3ca7-4c05-bc62-85f73ad04a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645682282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2645682282
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.980682281
Short name T524
Test name
Test status
Simulation time 111373705 ps
CPU time 0.96 seconds
Started Jul 11 05:40:19 PM PDT 24
Finished Jul 11 05:40:21 PM PDT 24
Peak memory 215576 kb
Host smart-c112a335-9caf-4ec9-ab33-5a7e2af47a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980682281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.980682281
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2523923812
Short name T455
Test name
Test status
Simulation time 753927074 ps
CPU time 3.16 seconds
Started Jul 11 05:40:05 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 217476 kb
Host smart-ad34da36-20b2-4ed9-85c2-d00bf1367274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523923812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2523923812
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1791530874
Short name T743
Test name
Test status
Simulation time 142755105457 ps
CPU time 1587.08 seconds
Started Jul 11 05:40:02 PM PDT 24
Finished Jul 11 06:06:31 PM PDT 24
Peak memory 225664 kb
Host smart-619d3e72-b500-482c-bc15-efe82cf53ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791530874 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1791530874
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.936585923
Short name T72
Test name
Test status
Simulation time 55100822 ps
CPU time 1.44 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 218940 kb
Host smart-c713b776-9523-4146-8607-26b9db6fa815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936585923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.936585923
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3642269408
Short name T714
Test name
Test status
Simulation time 59732596 ps
CPU time 1.62 seconds
Started Jul 11 05:41:57 PM PDT 24
Finished Jul 11 05:42:05 PM PDT 24
Peak memory 218984 kb
Host smart-3a6fe7d1-d5b0-4934-b4d8-40523f326bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642269408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3642269408
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.881154199
Short name T953
Test name
Test status
Simulation time 68868477 ps
CPU time 1.57 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:14 PM PDT 24
Peak memory 219696 kb
Host smart-9b9b1d25-f919-4347-85db-3d96ccd8ddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881154199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.881154199
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1073008830
Short name T601
Test name
Test status
Simulation time 34765191 ps
CPU time 1.11 seconds
Started Jul 11 05:42:19 PM PDT 24
Finished Jul 11 05:42:25 PM PDT 24
Peak memory 218768 kb
Host smart-ad75dbb2-45bd-4aed-a921-73ab5d6b320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073008830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1073008830
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2420839678
Short name T881
Test name
Test status
Simulation time 31643184 ps
CPU time 1.23 seconds
Started Jul 11 05:42:17 PM PDT 24
Finished Jul 11 05:42:22 PM PDT 24
Peak memory 217676 kb
Host smart-4aa70743-562f-40a5-b570-73c517bcdb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420839678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2420839678
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3652687379
Short name T443
Test name
Test status
Simulation time 60954736 ps
CPU time 1.17 seconds
Started Jul 11 05:42:10 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 219500 kb
Host smart-0e90ab6c-3071-4dd9-9ee5-f39bcaab4b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652687379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3652687379
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.797382222
Short name T681
Test name
Test status
Simulation time 65418822 ps
CPU time 1.32 seconds
Started Jul 11 05:42:21 PM PDT 24
Finished Jul 11 05:42:28 PM PDT 24
Peak memory 219128 kb
Host smart-2e6a2ef3-69f5-4ea6-813d-9acf6edb9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797382222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.797382222
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1032739311
Short name T928
Test name
Test status
Simulation time 59761322 ps
CPU time 2.16 seconds
Started Jul 11 05:42:15 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 220596 kb
Host smart-9ec0bf73-5a3b-458c-86d7-ce1929a020e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032739311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1032739311
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.4190494870
Short name T396
Test name
Test status
Simulation time 47019290 ps
CPU time 1.22 seconds
Started Jul 11 05:42:06 PM PDT 24
Finished Jul 11 05:42:11 PM PDT 24
Peak memory 219644 kb
Host smart-cdca47e2-ccec-44c5-a780-bdd177b40acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190494870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.4190494870
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.174920688
Short name T309
Test name
Test status
Simulation time 90840630 ps
CPU time 1.07 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 219908 kb
Host smart-5275bd43-ac5b-44cb-ab87-71ddf9441402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174920688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.174920688
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1296421713
Short name T61
Test name
Test status
Simulation time 27130822 ps
CPU time 0.89 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 215192 kb
Host smart-e72971a6-e1b4-40b9-9c83-ed697ebd0ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296421713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1296421713
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.770758811
Short name T690
Test name
Test status
Simulation time 12523042 ps
CPU time 0.9 seconds
Started Jul 11 05:39:10 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 216760 kb
Host smart-8c3264ae-f341-40f8-9216-326bdca45c90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770758811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.770758811
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2353552034
Short name T134
Test name
Test status
Simulation time 69225906 ps
CPU time 1.38 seconds
Started Jul 11 05:39:09 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 217060 kb
Host smart-e5d3682d-047a-44ea-b700-891af8c67c80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353552034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2353552034
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1607554055
Short name T185
Test name
Test status
Simulation time 32482379 ps
CPU time 0.89 seconds
Started Jul 11 05:39:09 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 218600 kb
Host smart-512c23b7-0536-47f9-8607-af845266294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607554055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1607554055
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.227136769
Short name T903
Test name
Test status
Simulation time 31842086 ps
CPU time 1.27 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 220072 kb
Host smart-097684c8-c831-45c3-9c36-b9f2986a0bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227136769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.227136769
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.612733361
Short name T915
Test name
Test status
Simulation time 48647745 ps
CPU time 1.01 seconds
Started Jul 11 05:38:57 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 224172 kb
Host smart-2635dca4-351e-4a42-ae89-6c8feb596f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612733361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.612733361
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1247649177
Short name T852
Test name
Test status
Simulation time 17508629 ps
CPU time 1.01 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:57 PM PDT 24
Peak memory 207420 kb
Host smart-f50afea3-1350-4771-8b2e-4bca2ab92ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247649177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1247649177
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2675785424
Short name T553
Test name
Test status
Simulation time 38241391 ps
CPU time 0.9 seconds
Started Jul 11 05:38:57 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 215428 kb
Host smart-61aeb1f3-7e3f-410c-974c-939234eee03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675785424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2675785424
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.205856388
Short name T42
Test name
Test status
Simulation time 1496287779 ps
CPU time 3.76 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 217472 kb
Host smart-445b0060-c994-4dc4-8ebf-9e7efde78873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205856388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.205856388
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4226517696
Short name T767
Test name
Test status
Simulation time 56581161974 ps
CPU time 334.64 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:44:41 PM PDT 24
Peak memory 218408 kb
Host smart-5136e809-ddde-406e-9f76-ccde328e80da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226517696 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4226517696
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1593199778
Short name T187
Test name
Test status
Simulation time 84443881 ps
CPU time 1.2 seconds
Started Jul 11 05:40:04 PM PDT 24
Finished Jul 11 05:40:07 PM PDT 24
Peak memory 219612 kb
Host smart-7bf47cf3-6a15-4bcd-9f2e-16839d2c2be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593199778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1593199778
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4241888136
Short name T478
Test name
Test status
Simulation time 32942904 ps
CPU time 0.97 seconds
Started Jul 11 05:40:19 PM PDT 24
Finished Jul 11 05:40:22 PM PDT 24
Peak memory 207040 kb
Host smart-c8e01865-6d91-4cb9-ba70-f22148acb635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241888136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4241888136
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3226577262
Short name T793
Test name
Test status
Simulation time 13130890 ps
CPU time 0.86 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 215696 kb
Host smart-af5a13fd-5acd-475b-919f-7025367a7d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226577262 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3226577262
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.3630343774
Short name T126
Test name
Test status
Simulation time 28767667 ps
CPU time 1.34 seconds
Started Jul 11 05:40:04 PM PDT 24
Finished Jul 11 05:40:07 PM PDT 24
Peak memory 230064 kb
Host smart-4429ffeb-363c-405b-b602-a8fcd36a0fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630343774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3630343774
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2069953954
Short name T563
Test name
Test status
Simulation time 32464982 ps
CPU time 1.22 seconds
Started Jul 11 05:40:07 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 217652 kb
Host smart-5c707c3e-d0c6-4c46-9e28-223df16133c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069953954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2069953954
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2742712309
Short name T611
Test name
Test status
Simulation time 35077547 ps
CPU time 1.02 seconds
Started Jul 11 05:40:03 PM PDT 24
Finished Jul 11 05:40:05 PM PDT 24
Peak memory 224348 kb
Host smart-d4c70ca1-66db-4583-8958-4029d09eeb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742712309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2742712309
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.72964883
Short name T393
Test name
Test status
Simulation time 24375407 ps
CPU time 0.93 seconds
Started Jul 11 05:40:11 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 215652 kb
Host smart-f8e7ff18-4211-4c40-bcdb-90f820970e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72964883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.72964883
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3337979435
Short name T576
Test name
Test status
Simulation time 48811685 ps
CPU time 1.54 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 215584 kb
Host smart-c8072b0e-07db-4fe9-9a5c-3ca71c08e766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337979435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3337979435
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.62466358
Short name T897
Test name
Test status
Simulation time 31581510034 ps
CPU time 671.15 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:51:21 PM PDT 24
Peak memory 218912 kb
Host smart-a318b5fa-8feb-4110-acee-1142768805f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62466358 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.62466358
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.2578830725
Short name T644
Test name
Test status
Simulation time 18963419 ps
CPU time 0.93 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 215124 kb
Host smart-6fa9ae1c-fa6e-404f-b125-d293288d07b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578830725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2578830725
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.4017165229
Short name T143
Test name
Test status
Simulation time 26667651 ps
CPU time 0.82 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 215720 kb
Host smart-2b71fa90-cb02-42d1-89eb-916c5c140289
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017165229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4017165229
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3204646859
Short name T116
Test name
Test status
Simulation time 92189663 ps
CPU time 1.16 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:18 PM PDT 24
Peak memory 217116 kb
Host smart-e3a9b986-0bc1-4f64-8ea3-acc675c5222b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204646859 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3204646859
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3316806678
Short name T875
Test name
Test status
Simulation time 28034323 ps
CPU time 0.86 seconds
Started Jul 11 05:39:56 PM PDT 24
Finished Jul 11 05:39:59 PM PDT 24
Peak memory 218756 kb
Host smart-00ac131a-52dc-4c7b-a150-fa20e8308757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316806678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3316806678
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3555196179
Short name T12
Test name
Test status
Simulation time 201578922 ps
CPU time 1.3 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 220216 kb
Host smart-56c8ce95-f29c-4349-b28b-79ad609e3ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555196179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3555196179
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1839433116
Short name T32
Test name
Test status
Simulation time 25645767 ps
CPU time 0.94 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 215684 kb
Host smart-edabfa8f-3140-4130-8252-a9c6712258a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839433116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1839433116
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3864023579
Short name T710
Test name
Test status
Simulation time 41374470 ps
CPU time 0.91 seconds
Started Jul 11 05:40:00 PM PDT 24
Finished Jul 11 05:40:03 PM PDT 24
Peak memory 215576 kb
Host smart-ea371279-2314-4b72-b703-2625443b4924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864023579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3864023579
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.323530290
Short name T625
Test name
Test status
Simulation time 341549509 ps
CPU time 1.74 seconds
Started Jul 11 05:40:04 PM PDT 24
Finished Jul 11 05:40:08 PM PDT 24
Peak memory 217652 kb
Host smart-78b081e3-79e4-4072-a1c9-0e64045bceb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323530290 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.323530290
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2508194545
Short name T658
Test name
Test status
Simulation time 38939454684 ps
CPU time 751.18 seconds
Started Jul 11 05:40:03 PM PDT 24
Finished Jul 11 05:52:36 PM PDT 24
Peak memory 218156 kb
Host smart-e782cfa3-58a1-4a3d-abb3-bf593ec70e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508194545 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2508194545
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2473973737
Short name T125
Test name
Test status
Simulation time 36223381 ps
CPU time 1.39 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:31 PM PDT 24
Peak memory 215940 kb
Host smart-67c4021d-1a5e-4489-81c9-39f4d6e464f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473973737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2473973737
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3200936658
Short name T747
Test name
Test status
Simulation time 45709416 ps
CPU time 0.9 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:31 PM PDT 24
Peak memory 215412 kb
Host smart-bb999767-f222-42d1-8b0c-022936029111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200936658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3200936658
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3880238228
Short name T169
Test name
Test status
Simulation time 95211280 ps
CPU time 0.81 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:18 PM PDT 24
Peak memory 216560 kb
Host smart-695da9c1-c17e-46da-b0f7-6ff82e3d82ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880238228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3880238228
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3722228709
Short name T634
Test name
Test status
Simulation time 245860011 ps
CPU time 1 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:31 PM PDT 24
Peak memory 220004 kb
Host smart-2d4036b7-cb03-4d6c-bb21-860e5134213d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722228709 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3722228709
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3757801559
Short name T429
Test name
Test status
Simulation time 24301931 ps
CPU time 1.1 seconds
Started Jul 11 05:40:18 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 224144 kb
Host smart-87ae2fd2-1d20-4e6d-a0d9-515c27cfcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757801559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3757801559
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2469819777
Short name T403
Test name
Test status
Simulation time 34399853 ps
CPU time 1.39 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 218888 kb
Host smart-b76c7b3b-ed62-49b7-8888-f8ddbae0fee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469819777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2469819777
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1439661502
Short name T622
Test name
Test status
Simulation time 22041595 ps
CPU time 1.1 seconds
Started Jul 11 05:40:13 PM PDT 24
Finished Jul 11 05:40:15 PM PDT 24
Peak memory 215744 kb
Host smart-24c6b075-d579-4fdd-b91f-d892ef4021cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439661502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1439661502
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3781078508
Short name T357
Test name
Test status
Simulation time 47902752 ps
CPU time 0.87 seconds
Started Jul 11 05:40:13 PM PDT 24
Finished Jul 11 05:40:15 PM PDT 24
Peak memory 215616 kb
Host smart-b274e611-13e9-450f-93b2-f97f93d93e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781078508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3781078508
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4244320277
Short name T239
Test name
Test status
Simulation time 228191606 ps
CPU time 3.05 seconds
Started Jul 11 05:40:16 PM PDT 24
Finished Jul 11 05:40:21 PM PDT 24
Peak memory 217544 kb
Host smart-b354f18c-96ca-4c8d-beb3-a5641f5de870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244320277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4244320277
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2206471010
Short name T742
Test name
Test status
Simulation time 433812020046 ps
CPU time 2354.6 seconds
Started Jul 11 05:40:08 PM PDT 24
Finished Jul 11 06:19:25 PM PDT 24
Peak memory 228604 kb
Host smart-b528154d-ebbd-4600-98a3-80489f505e42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206471010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2206471010
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3933636715
Short name T546
Test name
Test status
Simulation time 87871189 ps
CPU time 1.15 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 220532 kb
Host smart-8022a286-45b6-4314-9cb4-65081dad138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933636715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3933636715
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1006740507
Short name T370
Test name
Test status
Simulation time 12741604 ps
CPU time 0.83 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 207284 kb
Host smart-7d894dc0-547c-4fd5-a9ce-9632bc31b128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006740507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1006740507
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4199691356
Short name T825
Test name
Test status
Simulation time 40274564 ps
CPU time 0.86 seconds
Started Jul 11 05:40:11 PM PDT 24
Finished Jul 11 05:40:14 PM PDT 24
Peak memory 216624 kb
Host smart-3954c0fe-fb7f-4426-9468-9e22e7eeb16a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199691356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4199691356
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1381258626
Short name T722
Test name
Test status
Simulation time 39231842 ps
CPU time 1.27 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:13 PM PDT 24
Peak memory 217052 kb
Host smart-e7448975-cbfe-4023-bfdd-43863f4b7d05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381258626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1381258626
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2311025335
Short name T131
Test name
Test status
Simulation time 31254931 ps
CPU time 1.08 seconds
Started Jul 11 05:40:12 PM PDT 24
Finished Jul 11 05:40:14 PM PDT 24
Peak memory 218732 kb
Host smart-d1b22fab-41cc-4c6d-a24a-56976bb35f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311025335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2311025335
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.292597119
Short name T365
Test name
Test status
Simulation time 93534330 ps
CPU time 1.64 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 218956 kb
Host smart-9abcdd91-f53b-4aa8-b3e4-f917671bd21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292597119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.292597119
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3565465224
Short name T861
Test name
Test status
Simulation time 37811288 ps
CPU time 0.88 seconds
Started Jul 11 05:40:12 PM PDT 24
Finished Jul 11 05:40:14 PM PDT 24
Peak memory 215704 kb
Host smart-56032e11-d5fc-429a-8ead-4904c63770a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565465224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3565465224
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2028271171
Short name T353
Test name
Test status
Simulation time 38914094 ps
CPU time 0.91 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:12 PM PDT 24
Peak memory 215576 kb
Host smart-16eacaf3-6b12-43c0-9460-955b521c919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028271171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2028271171
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2471106490
Short name T241
Test name
Test status
Simulation time 781206061 ps
CPU time 4.3 seconds
Started Jul 11 05:40:31 PM PDT 24
Finished Jul 11 05:40:36 PM PDT 24
Peak memory 217340 kb
Host smart-bc1575b8-16ab-4dcc-a386-f087da55aeb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471106490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2471106490
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.351992657
Short name T783
Test name
Test status
Simulation time 67611507856 ps
CPU time 435.62 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:47:34 PM PDT 24
Peak memory 218552 kb
Host smart-4c4387be-fba7-4364-b684-258463383b4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351992657 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.351992657
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1066704982
Short name T754
Test name
Test status
Simulation time 27603188 ps
CPU time 1.2 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 218656 kb
Host smart-f8b1a44a-101e-41f4-b0c3-135d7ec0de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066704982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1066704982
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1514955079
Short name T804
Test name
Test status
Simulation time 98251080 ps
CPU time 0.83 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 206824 kb
Host smart-18c68bdb-81da-4aa5-84f4-7b3a8ef6b575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514955079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1514955079
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3887325728
Short name T23
Test name
Test status
Simulation time 40265577 ps
CPU time 0.86 seconds
Started Jul 11 05:40:27 PM PDT 24
Finished Jul 11 05:40:29 PM PDT 24
Peak memory 215688 kb
Host smart-ea4c7ead-6127-4ed1-812b-a31848631dc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887325728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3887325728
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1204224341
Short name T136
Test name
Test status
Simulation time 113585284 ps
CPU time 1.14 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 217160 kb
Host smart-363f61c8-3aaf-4303-a6d4-02d075f2b4c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204224341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1204224341
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2844918410
Short name T161
Test name
Test status
Simulation time 26874518 ps
CPU time 1.07 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 224288 kb
Host smart-5d1fa76c-47b7-4421-b503-a7ec3e7ba032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844918410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2844918410
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_smoke.440242145
Short name T400
Test name
Test status
Simulation time 20296978 ps
CPU time 1.03 seconds
Started Jul 11 05:40:17 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 215520 kb
Host smart-1ba473a3-ffc5-4a36-b769-aff472f075ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440242145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.440242145
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3555831600
Short name T851
Test name
Test status
Simulation time 89037850 ps
CPU time 1.52 seconds
Started Jul 11 05:40:13 PM PDT 24
Finished Jul 11 05:40:16 PM PDT 24
Peak memory 217484 kb
Host smart-af6ba882-7298-431f-b2a9-278280c5c37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555831600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3555831600
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3677195754
Short name T542
Test name
Test status
Simulation time 20900670193 ps
CPU time 555.53 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:49:46 PM PDT 24
Peak memory 218228 kb
Host smart-5ccc0729-9dbc-4844-b0ef-de2c23f90d49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677195754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3677195754
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1956738583
Short name T824
Test name
Test status
Simulation time 100795203 ps
CPU time 1.1 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 220796 kb
Host smart-b2cc88aa-2821-4bc4-9e2e-bbb50a13975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956738583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1956738583
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2419944082
Short name T381
Test name
Test status
Simulation time 111643113 ps
CPU time 0.88 seconds
Started Jul 11 05:40:21 PM PDT 24
Finished Jul 11 05:40:24 PM PDT 24
Peak memory 215068 kb
Host smart-5ea2f68e-7cdd-430f-bf2a-e99978b5cdb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419944082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2419944082
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.683959151
Short name T74
Test name
Test status
Simulation time 18620007 ps
CPU time 0.85 seconds
Started Jul 11 05:40:35 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 216648 kb
Host smart-db19f60d-c295-45da-a358-ea4b10a11739
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683959151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.683959151
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2374330542
Short name T11
Test name
Test status
Simulation time 266685147 ps
CPU time 1.1 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:31 PM PDT 24
Peak memory 216632 kb
Host smart-932810ad-ebc9-4878-a75e-2d8aa7b4a46c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374330542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2374330542
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.681278024
Short name T485
Test name
Test status
Simulation time 75078645 ps
CPU time 1.19 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 220068 kb
Host smart-8c4eb2b6-37c1-4ad8-9759-19a72a88f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681278024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.681278024
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2298992649
Short name T533
Test name
Test status
Simulation time 150983825 ps
CPU time 1.17 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 215612 kb
Host smart-30cdf8af-51fb-496e-a11b-4ac99704c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298992649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2298992649
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1398167624
Short name T503
Test name
Test status
Simulation time 32846900 ps
CPU time 0.86 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:42 PM PDT 24
Peak memory 215760 kb
Host smart-135b1a86-66e5-4464-b19f-5ad46f123ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398167624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1398167624
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2464190618
Short name T640
Test name
Test status
Simulation time 33922185 ps
CPU time 0.88 seconds
Started Jul 11 05:40:27 PM PDT 24
Finished Jul 11 05:40:28 PM PDT 24
Peak memory 215596 kb
Host smart-9b46837b-0ddc-4be8-bed2-3687cfecc17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464190618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2464190618
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.22983265
Short name T997
Test name
Test status
Simulation time 742304495 ps
CPU time 3.97 seconds
Started Jul 11 05:40:30 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 217584 kb
Host smart-2a9733d5-85f6-4ddc-97cd-b75a1b162c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.22983265
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3041950514
Short name T808
Test name
Test status
Simulation time 84700796900 ps
CPU time 1900.15 seconds
Started Jul 11 05:40:35 PM PDT 24
Finished Jul 11 06:12:17 PM PDT 24
Peak memory 227052 kb
Host smart-296bc87d-f826-40f6-88d0-65f12751af54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041950514 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3041950514
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1553152713
Short name T93
Test name
Test status
Simulation time 25101455 ps
CPU time 1.2 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 220884 kb
Host smart-be5a2324-6c33-4e5e-a008-0815a78a2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553152713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1553152713
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3934539331
Short name T975
Test name
Test status
Simulation time 46345773 ps
CPU time 1.4 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 207148 kb
Host smart-ef5438a7-1454-4130-95e0-90275749ab32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934539331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3934539331
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3889705403
Short name T80
Test name
Test status
Simulation time 24809666 ps
CPU time 0.83 seconds
Started Jul 11 05:40:27 PM PDT 24
Finished Jul 11 05:40:28 PM PDT 24
Peak memory 216568 kb
Host smart-3dc5e829-b4ac-43e3-9d03-2d06a785db02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889705403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3889705403
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.676497250
Short name T582
Test name
Test status
Simulation time 80882380 ps
CPU time 1.03 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:42 PM PDT 24
Peak memory 219044 kb
Host smart-4e5cea60-abf9-47ce-9a95-daf118cac470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676497250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.676497250
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4183618847
Short name T6
Test name
Test status
Simulation time 28096783 ps
CPU time 1.21 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:41 PM PDT 24
Peak memory 219784 kb
Host smart-60a1dd90-68e4-4e35-b000-8fc81c1e005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183618847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4183618847
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3414580440
Short name T753
Test name
Test status
Simulation time 23203104 ps
CPU time 1.23 seconds
Started Jul 11 05:40:32 PM PDT 24
Finished Jul 11 05:40:34 PM PDT 24
Peak memory 217676 kb
Host smart-57a4c699-24d0-4ca7-8f4d-3c10e325fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414580440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3414580440
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1665373661
Short name T411
Test name
Test status
Simulation time 33781975 ps
CPU time 0.99 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 224284 kb
Host smart-eac4932d-2601-4da2-9366-5bffe7bc0971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665373661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1665373661
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3932891090
Short name T967
Test name
Test status
Simulation time 21917696 ps
CPU time 0.95 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:40 PM PDT 24
Peak memory 207460 kb
Host smart-6b7f1137-6f15-4d87-9a4b-59c7cdf97884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932891090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3932891090
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2246127039
Short name T439
Test name
Test status
Simulation time 396965600 ps
CPU time 7.16 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 216912 kb
Host smart-42f89115-8483-4ba4-b9f6-382c1d18cc40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246127039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2246127039
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1130268965
Short name T62
Test name
Test status
Simulation time 262628397686 ps
CPU time 1720.3 seconds
Started Jul 11 05:40:19 PM PDT 24
Finished Jul 11 06:09:01 PM PDT 24
Peak memory 226524 kb
Host smart-9b5c1601-f693-43ab-af6d-4f462fe30565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130268965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1130268965
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.175810751
Short name T948
Test name
Test status
Simulation time 39584422 ps
CPU time 1.17 seconds
Started Jul 11 05:40:20 PM PDT 24
Finished Jul 11 05:40:23 PM PDT 24
Peak memory 220048 kb
Host smart-dc0fc3fd-9af3-4145-8adc-27152bb82044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175810751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.175810751
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.787131103
Short name T874
Test name
Test status
Simulation time 59486149 ps
CPU time 0.83 seconds
Started Jul 11 05:40:26 PM PDT 24
Finished Jul 11 05:40:27 PM PDT 24
Peak memory 215012 kb
Host smart-3f4e0609-4bd5-44b0-a289-3fea6bfb07ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787131103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.787131103
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2046578026
Short name T757
Test name
Test status
Simulation time 19392019 ps
CPU time 0.84 seconds
Started Jul 11 05:40:27 PM PDT 24
Finished Jul 11 05:40:28 PM PDT 24
Peak memory 216524 kb
Host smart-25a79ace-bd27-4507-b21f-8000ab5a9f41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046578026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2046578026
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4251670916
Short name T196
Test name
Test status
Simulation time 193050022 ps
CPU time 0.99 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 217204 kb
Host smart-0660ffaf-b00c-42bb-881e-5b119016be0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251670916 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4251670916
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3330092740
Short name T799
Test name
Test status
Simulation time 31989043 ps
CPU time 0.96 seconds
Started Jul 11 05:40:33 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 224076 kb
Host smart-c7dfa990-0f8b-4579-bf3d-a349f69b18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330092740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3330092740
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.607139959
Short name T472
Test name
Test status
Simulation time 45623686 ps
CPU time 1.32 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 217584 kb
Host smart-0d8df819-cf53-47db-911a-4c54df29c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607139959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.607139959
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3117801671
Short name T85
Test name
Test status
Simulation time 20662931 ps
CPU time 1.07 seconds
Started Jul 11 05:40:28 PM PDT 24
Finished Jul 11 05:40:30 PM PDT 24
Peak memory 216172 kb
Host smart-0d9f8f11-de7d-498f-870c-17ad220d1240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117801671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3117801671
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1116538976
Short name T876
Test name
Test status
Simulation time 16731507 ps
CPU time 0.99 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:41 PM PDT 24
Peak memory 215536 kb
Host smart-57e4ceee-c0f2-4e12-9afe-0b83c508439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116538976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1116538976
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1746407831
Short name T674
Test name
Test status
Simulation time 370273383 ps
CPU time 2.31 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:44 PM PDT 24
Peak memory 217780 kb
Host smart-2ddafcdf-1e42-4d07-96b0-f0ac93698e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746407831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1746407831
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.2301860813
Short name T146
Test name
Test status
Simulation time 25020461 ps
CPU time 1.16 seconds
Started Jul 11 05:40:33 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 219004 kb
Host smart-44fd3b67-42f4-41db-9eae-277cf584dd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301860813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2301860813
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.738915423
Short name T774
Test name
Test status
Simulation time 26773100 ps
CPU time 1.05 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:36 PM PDT 24
Peak memory 207060 kb
Host smart-d75bbe7a-8c97-4e4c-bf45-97fdd4d8cd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738915423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.738915423
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2200759628
Short name T152
Test name
Test status
Simulation time 13305892 ps
CPU time 0.93 seconds
Started Jul 11 05:40:22 PM PDT 24
Finished Jul 11 05:40:24 PM PDT 24
Peak memory 216820 kb
Host smart-67d2ae4a-dd7a-4ec9-9a26-8006ef3bb93a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200759628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2200759628
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1555099346
Short name T922
Test name
Test status
Simulation time 31883097 ps
CPU time 1.19 seconds
Started Jul 11 05:40:24 PM PDT 24
Finished Jul 11 05:40:26 PM PDT 24
Peak memory 217228 kb
Host smart-fc6f99cf-d6f0-4c82-a57f-a8c21a9562c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555099346 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1555099346
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1025277227
Short name T869
Test name
Test status
Simulation time 49531684 ps
CPU time 1.05 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:41 PM PDT 24
Peak memory 218788 kb
Host smart-deed1764-d8f9-4e75-bff4-93620ab7962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025277227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1025277227
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2066806589
Short name T364
Test name
Test status
Simulation time 25721745 ps
CPU time 1.24 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 217492 kb
Host smart-3c55ca16-00cf-466d-9f2f-05273ff86d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066806589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2066806589
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.536077426
Short name T477
Test name
Test status
Simulation time 25809691 ps
CPU time 0.98 seconds
Started Jul 11 05:40:21 PM PDT 24
Finished Jul 11 05:40:24 PM PDT 24
Peak memory 215616 kb
Host smart-1ad75f99-ac65-4eee-98ed-41ec07d8d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536077426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.536077426
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2874802959
Short name T745
Test name
Test status
Simulation time 508523755 ps
CPU time 4.51 seconds
Started Jul 11 05:40:21 PM PDT 24
Finished Jul 11 05:40:27 PM PDT 24
Peak memory 217536 kb
Host smart-e1c060a7-3e24-4034-880d-1978ce5fa563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874802959 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2874802959
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2397732131
Short name T222
Test name
Test status
Simulation time 470176245787 ps
CPU time 1525.32 seconds
Started Jul 11 05:40:25 PM PDT 24
Finished Jul 11 06:05:51 PM PDT 24
Peak memory 225096 kb
Host smart-28f402a7-94bf-4537-9554-70066cffcdb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397732131 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2397732131
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3470787591
Short name T691
Test name
Test status
Simulation time 51807026 ps
CPU time 1.28 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:40 PM PDT 24
Peak memory 220204 kb
Host smart-9489a38e-fc18-4332-a45b-2151b5470360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470787591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3470787591
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1468565912
Short name T534
Test name
Test status
Simulation time 13712918 ps
CPU time 0.87 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:36 PM PDT 24
Peak memory 206984 kb
Host smart-35abcb44-852e-4359-8001-620f305e598c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468565912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1468565912
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3361021265
Short name T117
Test name
Test status
Simulation time 81292838 ps
CPU time 1.06 seconds
Started Jul 11 05:40:35 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 217080 kb
Host smart-cd689301-88c9-426a-b8df-a20c27337027
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361021265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3361021265
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1686152066
Short name T149
Test name
Test status
Simulation time 22819324 ps
CPU time 0.91 seconds
Started Jul 11 05:40:33 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 215672 kb
Host smart-fe7101bf-f31b-4a47-88d5-60d551780b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686152066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1686152066
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3094755850
Short name T486
Test name
Test status
Simulation time 204782654 ps
CPU time 1.21 seconds
Started Jul 11 05:40:22 PM PDT 24
Finished Jul 11 05:40:24 PM PDT 24
Peak memory 219272 kb
Host smart-57bcccda-6841-417d-8e1e-fc509eba24ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094755850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3094755850
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.312410135
Short name T449
Test name
Test status
Simulation time 39975638 ps
CPU time 0.89 seconds
Started Jul 11 05:40:32 PM PDT 24
Finished Jul 11 05:40:34 PM PDT 24
Peak memory 215696 kb
Host smart-ba4ffe32-4d56-4db1-b927-0403dd8a2729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312410135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.312410135
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3581519409
Short name T623
Test name
Test status
Simulation time 29362010 ps
CPU time 0.96 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:40:32 PM PDT 24
Peak memory 215504 kb
Host smart-4a15da52-8f43-45b7-9d24-91edec9ae4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581519409 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3581519409
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1525096476
Short name T375
Test name
Test status
Simulation time 1268249183 ps
CPU time 4.66 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:40 PM PDT 24
Peak memory 215588 kb
Host smart-be5a5d90-cf6b-4ddf-a1ff-c8da1ee5fe04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525096476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1525096476
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1170643127
Short name T538
Test name
Test status
Simulation time 60463530021 ps
CPU time 1503.04 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 06:05:34 PM PDT 24
Peak memory 224348 kb
Host smart-c4f22e3d-8f2d-4c4f-b36d-ad3662de0d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170643127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1170643127
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2066174028
Short name T257
Test name
Test status
Simulation time 96348971 ps
CPU time 1.27 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:54 PM PDT 24
Peak memory 218680 kb
Host smart-03a5e3c1-30e8-4d60-8515-00cc6398e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066174028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2066174028
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4026982618
Short name T708
Test name
Test status
Simulation time 24228909 ps
CPU time 0.86 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 207088 kb
Host smart-02f53c8b-412e-452d-8f54-21766849fbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026982618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4026982618
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.408808503
Short name T198
Test name
Test status
Simulation time 10885291 ps
CPU time 0.86 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 216436 kb
Host smart-579801c9-f1b9-4eb2-9614-eed0cc010229
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408808503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.408808503
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2200439741
Short name T361
Test name
Test status
Simulation time 225080091 ps
CPU time 1.19 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 217312 kb
Host smart-25dbe95b-d87c-465b-8dbc-7463688e4877
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200439741 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2200439741
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3195960958
Short name T800
Test name
Test status
Simulation time 30474554 ps
CPU time 1.05 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 220952 kb
Host smart-3b6b66d9-b228-4494-ae0f-32955ce4141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195960958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3195960958
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2072347706
Short name T718
Test name
Test status
Simulation time 49042975 ps
CPU time 1.31 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:39:08 PM PDT 24
Peak memory 217600 kb
Host smart-3c2a6fd2-b5e8-4902-a8c4-baa309e548c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072347706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2072347706
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.318646714
Short name T226
Test name
Test status
Simulation time 24959230 ps
CPU time 1.03 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:54 PM PDT 24
Peak memory 224288 kb
Host smart-119b28c7-c76d-4444-b639-61f3b6a64d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318646714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.318646714
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2551300430
Short name T736
Test name
Test status
Simulation time 17883646 ps
CPU time 1.12 seconds
Started Jul 11 05:39:10 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 207348 kb
Host smart-280b4934-fa73-4eb5-ac92-808eb21c9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551300430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2551300430
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2066067302
Short name T16
Test name
Test status
Simulation time 1449519393 ps
CPU time 4.34 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:37 PM PDT 24
Peak memory 236940 kb
Host smart-780559d9-8063-4db4-a176-24fc56fdf7c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066067302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2066067302
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.485796078
Short name T724
Test name
Test status
Simulation time 41195672 ps
CPU time 0.94 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 215676 kb
Host smart-09eebf66-bbe9-495a-93c0-8c8bcb823131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485796078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.485796078
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2462634068
Short name T392
Test name
Test status
Simulation time 191403765 ps
CPU time 2.33 seconds
Started Jul 11 05:38:52 PM PDT 24
Finished Jul 11 05:38:55 PM PDT 24
Peak memory 217376 kb
Host smart-6daee7b8-3292-4eb8-a7fa-e0a2bde80357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462634068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2462634068
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2822159518
Short name T219
Test name
Test status
Simulation time 335096443960 ps
CPU time 3087.97 seconds
Started Jul 11 05:38:51 PM PDT 24
Finished Jul 11 06:30:21 PM PDT 24
Peak memory 231256 kb
Host smart-d23b17f9-6919-4756-88fc-940ba8aea9ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822159518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2822159518
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3832619316
Short name T762
Test name
Test status
Simulation time 47219466 ps
CPU time 1.17 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:36 PM PDT 24
Peak memory 219752 kb
Host smart-96de3073-9a16-4c94-877e-32b6e4cf7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832619316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3832619316
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2026806485
Short name T840
Test name
Test status
Simulation time 12926525 ps
CPU time 0.9 seconds
Started Jul 11 05:40:46 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 207200 kb
Host smart-3ce548cb-94b5-4236-bd14-c73b9213be55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026806485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2026806485
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1821129716
Short name T170
Test name
Test status
Simulation time 16713107 ps
CPU time 0.85 seconds
Started Jul 11 05:40:46 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 216564 kb
Host smart-bc80af05-f44a-4866-ace8-065924e9b1c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821129716 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1821129716
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2684253628
Short name T60
Test name
Test status
Simulation time 43736207 ps
CPU time 1.3 seconds
Started Jul 11 05:40:55 PM PDT 24
Finished Jul 11 05:40:57 PM PDT 24
Peak memory 218764 kb
Host smart-5fa1e535-809a-49c5-82f2-721a6c0c55cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684253628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2684253628
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2557441029
Short name T427
Test name
Test status
Simulation time 30146030 ps
CPU time 1.03 seconds
Started Jul 11 05:40:40 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 218768 kb
Host smart-1748cde6-9443-44cf-be07-abbc89375329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557441029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2557441029
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1968540221
Short name T323
Test name
Test status
Simulation time 119008450 ps
CPU time 1.12 seconds
Started Jul 11 05:40:23 PM PDT 24
Finished Jul 11 05:40:25 PM PDT 24
Peak memory 217620 kb
Host smart-e6e82dd4-491e-4218-a81e-11d39026e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968540221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1968540221
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1262644190
Short name T968
Test name
Test status
Simulation time 28425861 ps
CPU time 0.93 seconds
Started Jul 11 05:40:24 PM PDT 24
Finished Jul 11 05:40:26 PM PDT 24
Peak memory 215720 kb
Host smart-dbd5c2d9-66f2-4d58-aad6-a23de89adac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262644190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1262644190
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2556147652
Short name T750
Test name
Test status
Simulation time 25030155 ps
CPU time 0.98 seconds
Started Jul 11 05:40:25 PM PDT 24
Finished Jul 11 05:40:26 PM PDT 24
Peak memory 215616 kb
Host smart-33a60548-9e4a-4a99-9a34-c1b1151cd590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556147652 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2556147652
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1891356896
Short name T243
Test name
Test status
Simulation time 674318544 ps
CPU time 6.71 seconds
Started Jul 11 05:40:24 PM PDT 24
Finished Jul 11 05:40:31 PM PDT 24
Peak memory 217700 kb
Host smart-7fd0d69c-8a0f-46b3-8c31-94e0565390b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891356896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1891356896
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2764930125
Short name T741
Test name
Test status
Simulation time 104074470199 ps
CPU time 602.2 seconds
Started Jul 11 05:40:29 PM PDT 24
Finished Jul 11 05:50:33 PM PDT 24
Peak memory 219992 kb
Host smart-f90affe9-0ade-4d6a-b452-4ed6a67e2cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764930125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2764930125
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.842589405
Short name T63
Test name
Test status
Simulation time 95556780 ps
CPU time 1.27 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:41 PM PDT 24
Peak memory 216016 kb
Host smart-dff4ca3c-7196-4a25-b8c0-291d9c442f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842589405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.842589405
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2689495658
Short name T417
Test name
Test status
Simulation time 24899056 ps
CPU time 0.9 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 207016 kb
Host smart-d57f6638-2160-4f92-bc8c-098d801fbc76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689495658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2689495658
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1780452666
Short name T190
Test name
Test status
Simulation time 12008233 ps
CPU time 0.88 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:40:41 PM PDT 24
Peak memory 216568 kb
Host smart-3489f275-501e-4fdb-b993-df2df230d043
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780452666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1780452666
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2298324110
Short name T50
Test name
Test status
Simulation time 253593031 ps
CPU time 1.19 seconds
Started Jul 11 05:40:33 PM PDT 24
Finished Jul 11 05:40:35 PM PDT 24
Peak memory 217360 kb
Host smart-9a72dd2b-75db-477e-821d-4808f669c344
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298324110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2298324110
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1992698516
Short name T122
Test name
Test status
Simulation time 33673444 ps
CPU time 1.07 seconds
Started Jul 11 05:40:41 PM PDT 24
Finished Jul 11 05:40:44 PM PDT 24
Peak memory 220924 kb
Host smart-0e479b7b-edfe-48ed-b8a0-e0d8e0fe960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992698516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1992698516
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3956888439
Short name T844
Test name
Test status
Simulation time 34900518 ps
CPU time 1.3 seconds
Started Jul 11 05:40:40 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 215580 kb
Host smart-49e80671-c1c6-4478-b7c9-f3ed895a35db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956888439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3956888439
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3368383983
Short name T82
Test name
Test status
Simulation time 22131400 ps
CPU time 0.95 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:42 PM PDT 24
Peak memory 216088 kb
Host smart-10788917-c00e-47bd-afdc-7a2c0ec964ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368383983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3368383983
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2666608720
Short name T593
Test name
Test status
Simulation time 29565336 ps
CPU time 0.96 seconds
Started Jul 11 05:40:40 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 215516 kb
Host smart-c3533d2f-7eaa-48f0-b21f-445d31ebdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666608720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2666608720
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3985839208
Short name T242
Test name
Test status
Simulation time 194198570 ps
CPU time 2.33 seconds
Started Jul 11 05:40:44 PM PDT 24
Finished Jul 11 05:40:47 PM PDT 24
Peak memory 215524 kb
Host smart-5e75c254-6822-488a-a49a-4bff0a3cc90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985839208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3985839208
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3577148197
Short name T36
Test name
Test status
Simulation time 551702553468 ps
CPU time 2691.58 seconds
Started Jul 11 05:40:54 PM PDT 24
Finished Jul 11 06:25:47 PM PDT 24
Peak memory 232848 kb
Host smart-821bd25e-490a-4bf2-801a-4e0d61f3d8aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577148197 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3577148197
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2222129023
Short name T643
Test name
Test status
Simulation time 58291328 ps
CPU time 1.14 seconds
Started Jul 11 05:40:34 PM PDT 24
Finished Jul 11 05:40:36 PM PDT 24
Peak memory 218676 kb
Host smart-97b78c23-4588-4e7f-a8ce-b4144d7124a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222129023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2222129023
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3940411122
Short name T740
Test name
Test status
Simulation time 17763083 ps
CPU time 0.83 seconds
Started Jul 11 05:40:44 PM PDT 24
Finished Jul 11 05:40:46 PM PDT 24
Peak memory 206340 kb
Host smart-969a3cc2-3f6b-4ca1-aa4e-359d3abf2c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940411122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3940411122
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2793109859
Short name T732
Test name
Test status
Simulation time 13679055 ps
CPU time 0.88 seconds
Started Jul 11 05:50:26 PM PDT 24
Finished Jul 11 05:50:28 PM PDT 24
Peak memory 216336 kb
Host smart-67bfb610-6204-4793-bbca-706a9031da85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793109859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2793109859
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4045591816
Short name T960
Test name
Test status
Simulation time 29774377 ps
CPU time 1.18 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:42 PM PDT 24
Peak memory 217236 kb
Host smart-72fee933-d991-4005-a95e-2ac0b91f6c70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045591816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4045591816
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3858186888
Short name T547
Test name
Test status
Simulation time 25463711 ps
CPU time 1.07 seconds
Started Jul 11 05:40:46 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 219940 kb
Host smart-d88fa634-e1e9-4e81-a65b-c4eed157ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858186888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3858186888
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1114136942
Short name T440
Test name
Test status
Simulation time 52151014 ps
CPU time 1.34 seconds
Started Jul 11 05:40:42 PM PDT 24
Finished Jul 11 05:40:44 PM PDT 24
Peak memory 219040 kb
Host smart-005ebfa8-a987-40da-8d7c-98da19a1eb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114136942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1114136942
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.714514433
Short name T30
Test name
Test status
Simulation time 30651570 ps
CPU time 0.89 seconds
Started Jul 11 05:40:46 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 215832 kb
Host smart-d983d7ad-0df8-49e0-95fb-d0f86d446a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714514433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.714514433
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.458184000
Short name T972
Test name
Test status
Simulation time 36388110 ps
CPU time 0.92 seconds
Started Jul 11 05:40:39 PM PDT 24
Finished Jul 11 05:40:42 PM PDT 24
Peak memory 215616 kb
Host smart-c6125685-f786-42c2-8e0d-a2da8b86b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458184000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.458184000
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1140404192
Short name T957
Test name
Test status
Simulation time 25708686190 ps
CPU time 592.11 seconds
Started Jul 11 05:40:38 PM PDT 24
Finished Jul 11 05:50:32 PM PDT 24
Peak memory 218644 kb
Host smart-4368f308-adf0-4051-bad1-2e44d4060327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140404192 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1140404192
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3631648157
Short name T502
Test name
Test status
Simulation time 66448305 ps
CPU time 1.12 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 220176 kb
Host smart-4c91ddbd-544b-4259-a364-8c93207352df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631648157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3631648157
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2037098636
Short name T659
Test name
Test status
Simulation time 53257226 ps
CPU time 0.79 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:47 PM PDT 24
Peak memory 206740 kb
Host smart-814bdb55-19e6-45c1-8f3e-481182c6ab25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037098636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2037098636
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.72699588
Short name T202
Test name
Test status
Simulation time 14215346 ps
CPU time 0.93 seconds
Started Jul 11 05:40:59 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 215960 kb
Host smart-a5884dda-21d5-4160-b663-90d137cde98a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72699588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.72699588
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.621455801
Short name T77
Test name
Test status
Simulation time 61455435 ps
CPU time 1.14 seconds
Started Jul 11 05:40:41 PM PDT 24
Finished Jul 11 05:40:44 PM PDT 24
Peak memory 217172 kb
Host smart-1006dfdb-ec7f-4dd8-b77b-6ba363559286
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621455801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.621455801
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1886021566
Short name T158
Test name
Test status
Simulation time 18236666 ps
CPU time 1.19 seconds
Started Jul 11 05:40:52 PM PDT 24
Finished Jul 11 05:40:55 PM PDT 24
Peak memory 224316 kb
Host smart-e80e6233-66de-493a-8c09-4fbbc0cc5fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886021566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1886021566
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.208493789
Short name T433
Test name
Test status
Simulation time 69241450 ps
CPU time 1.1 seconds
Started Jul 11 05:40:46 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 218800 kb
Host smart-21d5f231-0fd8-44a8-9ac4-48ef6c041591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208493789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.208493789
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1484127619
Short name T568
Test name
Test status
Simulation time 33115246 ps
CPU time 0.91 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 215648 kb
Host smart-f935b4c5-3cac-4939-a87d-bfb575a5ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484127619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1484127619
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1976028122
Short name T934
Test name
Test status
Simulation time 48074955 ps
CPU time 0.9 seconds
Started Jul 11 05:40:55 PM PDT 24
Finished Jul 11 05:40:56 PM PDT 24
Peak memory 215640 kb
Host smart-391428d1-600c-42c0-a627-cad40517ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976028122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1976028122
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.413730494
Short name T735
Test name
Test status
Simulation time 94924942 ps
CPU time 2.23 seconds
Started Jul 11 05:40:36 PM PDT 24
Finished Jul 11 05:40:39 PM PDT 24
Peak memory 217644 kb
Host smart-acb68767-5cec-44c2-9ba1-14764f4e377b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413730494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.413730494
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2835540427
Short name T885
Test name
Test status
Simulation time 64520550957 ps
CPU time 358.17 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 224064 kb
Host smart-7b417c18-9c19-4a5a-9501-0b3bc0a76e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835540427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2835540427
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1172913979
Short name T786
Test name
Test status
Simulation time 62554633 ps
CPU time 1.01 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:40:58 PM PDT 24
Peak memory 220128 kb
Host smart-d0e34436-c39b-4a4d-a48e-f91b1106a23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172913979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1172913979
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1983654758
Short name T931
Test name
Test status
Simulation time 50327751 ps
CPU time 0.91 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:47 PM PDT 24
Peak memory 207032 kb
Host smart-51653e86-1cff-4545-816f-3701b087c7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983654758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1983654758
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3733157556
Short name T180
Test name
Test status
Simulation time 44105089 ps
CPU time 0.81 seconds
Started Jul 11 05:40:51 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 216532 kb
Host smart-84e1f69f-41a7-44a3-bcea-95b54562c0d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733157556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3733157556
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4164391959
Short name T877
Test name
Test status
Simulation time 36372948 ps
CPU time 1.3 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 218776 kb
Host smart-fd43f4ff-984e-4efb-97e4-4491a3b4417f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164391959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4164391959
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1086580950
Short name T770
Test name
Test status
Simulation time 20133454 ps
CPU time 1.11 seconds
Started Jul 11 05:40:59 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 219928 kb
Host smart-a8d00905-7fd0-4736-89a7-b1c7755d8da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086580950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1086580950
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2579032417
Short name T596
Test name
Test status
Simulation time 36464706 ps
CPU time 1.08 seconds
Started Jul 11 05:40:51 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 218956 kb
Host smart-c3917760-59d8-47c9-a233-9941e04328ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579032417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2579032417
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2360510998
Short name T83
Test name
Test status
Simulation time 21094710 ps
CPU time 1.07 seconds
Started Jul 11 05:40:40 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 216172 kb
Host smart-0da030f1-ee65-4ea7-919e-e6061499c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360510998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2360510998
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2000539694
Short name T603
Test name
Test status
Simulation time 18976468 ps
CPU time 0.98 seconds
Started Jul 11 05:40:42 PM PDT 24
Finished Jul 11 05:40:44 PM PDT 24
Peak memory 207376 kb
Host smart-ba4c69c6-5072-4166-8667-107e48f61f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000539694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2000539694
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.116336205
Short name T250
Test name
Test status
Simulation time 825809272 ps
CPU time 5.02 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:41:03 PM PDT 24
Peak memory 217700 kb
Host smart-15b138c8-06b9-4133-b146-aab3ee8de27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116336205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.116336205
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1657181447
Short name T560
Test name
Test status
Simulation time 203595146669 ps
CPU time 840.06 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:55:24 PM PDT 24
Peak memory 222108 kb
Host smart-32510069-3bd4-49c9-a964-624a8c2fb346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657181447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1657181447
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.4255197084
Short name T10
Test name
Test status
Simulation time 25088303 ps
CPU time 1.23 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:41:01 PM PDT 24
Peak memory 218956 kb
Host smart-220376eb-578c-43b9-b1bb-0f0cfb8bdeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255197084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4255197084
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1360436621
Short name T495
Test name
Test status
Simulation time 22653905 ps
CPU time 0.86 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 207132 kb
Host smart-0eec0198-a5f7-4867-b008-7afac92d7727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360436621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1360436621
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2791745738
Short name T893
Test name
Test status
Simulation time 13374411 ps
CPU time 0.89 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 215900 kb
Host smart-7260b9f6-d901-41b7-ae8b-d2c7d5d56eb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791745738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2791745738
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1808362030
Short name T689
Test name
Test status
Simulation time 47833863 ps
CPU time 0.91 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 217148 kb
Host smart-506c9e6f-23b8-4b81-ae88-74c948cf2a45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808362030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1808362030
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3524269241
Short name T8
Test name
Test status
Simulation time 34576396 ps
CPU time 1.45 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 226108 kb
Host smart-c88768a7-caa6-4e7d-9be2-f2c1c6b1ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524269241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3524269241
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3306426900
Short name T666
Test name
Test status
Simulation time 97818842 ps
CPU time 1.21 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:41:00 PM PDT 24
Peak memory 218776 kb
Host smart-b5b47173-c73d-4d2c-aefb-08ad7a4ad17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306426900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3306426900
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1838115847
Short name T602
Test name
Test status
Simulation time 70698559 ps
CPU time 0.85 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:51 PM PDT 24
Peak memory 215552 kb
Host smart-d47373b6-4b16-4349-a7cd-9cb1acd4a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838115847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1838115847
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.910846587
Short name T234
Test name
Test status
Simulation time 50814494 ps
CPU time 0.97 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 207440 kb
Host smart-ca30b591-199e-47e5-8e88-6669980a1c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910846587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.910846587
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3457696934
Short name T587
Test name
Test status
Simulation time 245787716 ps
CPU time 1.49 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:40:58 PM PDT 24
Peak memory 217676 kb
Host smart-66a460cb-e990-4cbf-8ad2-00e241d2b96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457696934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3457696934
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3572424556
Short name T734
Test name
Test status
Simulation time 38724431787 ps
CPU time 780.75 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:53:59 PM PDT 24
Peak memory 224076 kb
Host smart-3b3972c9-25b4-45b5-b9d2-a423067d18c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572424556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3572424556
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2192766294
Short name T984
Test name
Test status
Simulation time 96763047 ps
CPU time 1.26 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:40:59 PM PDT 24
Peak memory 219784 kb
Host smart-92867426-a109-49ee-bc87-c1cbb3964647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192766294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2192766294
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2247864308
Short name T410
Test name
Test status
Simulation time 47863741 ps
CPU time 1.44 seconds
Started Jul 11 05:40:59 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 207220 kb
Host smart-077fc52c-97fc-4bdd-b40b-9a1ad64aa141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247864308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2247864308
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1341909881
Short name T981
Test name
Test status
Simulation time 62820510 ps
CPU time 1.18 seconds
Started Jul 11 05:40:44 PM PDT 24
Finished Jul 11 05:40:46 PM PDT 24
Peak memory 217252 kb
Host smart-46b2ccc8-c2e6-4fe2-bf87-a170e6beb897
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341909881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1341909881
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3607436961
Short name T795
Test name
Test status
Simulation time 30012266 ps
CPU time 0.96 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 232812 kb
Host smart-42fcffd9-74de-4a92-ba71-f3077c581696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607436961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3607436961
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.468819328
Short name T436
Test name
Test status
Simulation time 151355508 ps
CPU time 1.22 seconds
Started Jul 11 05:40:44 PM PDT 24
Finished Jul 11 05:40:47 PM PDT 24
Peak memory 217704 kb
Host smart-157056ab-06af-458f-b156-1451cd20d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468819328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.468819328
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.1303201725
Short name T405
Test name
Test status
Simulation time 46903871 ps
CPU time 0.91 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 215640 kb
Host smart-2d003710-1f58-4a2a-a097-c1ff4f1debba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303201725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1303201725
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1736286285
Short name T229
Test name
Test status
Simulation time 1769560765 ps
CPU time 3.72 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 215616 kb
Host smart-e01cc9b2-8f4e-4646-9636-374272e330ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736286285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1736286285
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1309809941
Short name T337
Test name
Test status
Simulation time 47015462030 ps
CPU time 1025.55 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 224092 kb
Host smart-7e201f59-185d-495c-8df6-3b760f67e487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309809941 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1309809941
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1018005158
Short name T610
Test name
Test status
Simulation time 22544158 ps
CPU time 1.14 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 220072 kb
Host smart-b233f374-09e4-4f13-902c-6155872b988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018005158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1018005158
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2164207696
Short name T872
Test name
Test status
Simulation time 53368238 ps
CPU time 0.8 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:41:00 PM PDT 24
Peak memory 207076 kb
Host smart-5e9d6134-ae58-45f8-8668-813e4dad6d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164207696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2164207696
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4137351703
Short name T828
Test name
Test status
Simulation time 20833588 ps
CPU time 0.84 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:41:00 PM PDT 24
Peak memory 216600 kb
Host smart-85afbae4-520c-4f3b-9c75-be722ec30c86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137351703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4137351703
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.291636642
Short name T600
Test name
Test status
Simulation time 45664538 ps
CPU time 0.95 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 218548 kb
Host smart-8be85a0f-20cb-4e83-b0fe-7b1b0dd1afca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291636642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.291636642
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4147843624
Short name T167
Test name
Test status
Simulation time 42941549 ps
CPU time 0.99 seconds
Started Jul 11 05:40:51 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 223912 kb
Host smart-854bd48d-b5c5-46a5-a538-149ca1299e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147843624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4147843624
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2137562789
Short name T820
Test name
Test status
Simulation time 55086411 ps
CPU time 1.65 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:22 PM PDT 24
Peak memory 218728 kb
Host smart-dcb08ece-d967-428b-bc34-2acb9586990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137562789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2137562789
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3848458784
Short name T528
Test name
Test status
Simulation time 35031262 ps
CPU time 0.87 seconds
Started Jul 11 05:40:45 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 215692 kb
Host smart-9ece984c-01cf-4306-af78-f451d47d18d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848458784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3848458784
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1451467480
Short name T426
Test name
Test status
Simulation time 19384769 ps
CPU time 1.01 seconds
Started Jul 11 05:40:59 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 215640 kb
Host smart-fafad5cc-0fe8-47ac-99bd-51f4c846ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451467480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1451467480
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3538653195
Short name T985
Test name
Test status
Simulation time 647868531 ps
CPU time 3.76 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 217484 kb
Host smart-63091bd9-ea4a-4edc-9425-bc25d5d72d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538653195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3538653195
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.654536297
Short name T867
Test name
Test status
Simulation time 50663627782 ps
CPU time 1086.92 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 220236 kb
Host smart-bf7d7572-79e0-4636-8238-409e449a0f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654536297 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.654536297
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3554612607
Short name T597
Test name
Test status
Simulation time 26571268 ps
CPU time 1.16 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:26 PM PDT 24
Peak memory 216016 kb
Host smart-06fbf533-3303-4446-a4c0-42d66694b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554612607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3554612607
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1386735159
Short name T419
Test name
Test status
Simulation time 19479765 ps
CPU time 0.94 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:51 PM PDT 24
Peak memory 207024 kb
Host smart-03c2e00e-b4cb-42dc-9603-2c780533a7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386735159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1386735159
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2960014603
Short name T558
Test name
Test status
Simulation time 10955717 ps
CPU time 0.83 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 216556 kb
Host smart-dd94bf48-9a38-4920-acfa-c12dfbfab724
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960014603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2960014603
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1240237686
Short name T995
Test name
Test status
Simulation time 95211494 ps
CPU time 1.07 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:52 PM PDT 24
Peak memory 217276 kb
Host smart-4e43d33e-2e41-44c6-ab4a-7dc5ed78b032
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240237686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1240237686
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3467376227
Short name T148
Test name
Test status
Simulation time 21929173 ps
CPU time 0.95 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:52 PM PDT 24
Peak memory 218736 kb
Host smart-196a4ebf-7208-4260-8d7a-a615910015eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467376227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3467376227
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1226410960
Short name T726
Test name
Test status
Simulation time 49443985 ps
CPU time 1.38 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:41:01 PM PDT 24
Peak memory 218664 kb
Host smart-3af15322-8ca0-4440-a1f6-4d467723cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226410960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1226410960
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3389095123
Short name T986
Test name
Test status
Simulation time 42956200 ps
CPU time 0.88 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:26 PM PDT 24
Peak memory 215736 kb
Host smart-c2e57a98-bc11-499b-912b-ee78863208c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389095123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3389095123
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.183866648
Short name T373
Test name
Test status
Simulation time 17229755 ps
CPU time 0.96 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 215628 kb
Host smart-1c2e6e80-a4fb-45eb-80b2-9e476f31709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183866648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.183866648
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3997922624
Short name T663
Test name
Test status
Simulation time 51712852 ps
CPU time 1.58 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 220048 kb
Host smart-39dda46a-3950-48b3-b5af-67398d3ebc82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997922624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3997922624
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2558549535
Short name T699
Test name
Test status
Simulation time 132880109766 ps
CPU time 1349.33 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 06:03:55 PM PDT 24
Peak memory 224620 kb
Host smart-a480520c-4df8-4534-b167-b561f192bd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558549535 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2558549535
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.468482550
Short name T911
Test name
Test status
Simulation time 22688538 ps
CPU time 1.16 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 218932 kb
Host smart-84511dc1-2d18-4314-a162-a628c30fe959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468482550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.468482550
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1898186518
Short name T406
Test name
Test status
Simulation time 37334743 ps
CPU time 0.91 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:16 PM PDT 24
Peak memory 215084 kb
Host smart-6e664960-1b86-4049-a185-57c5fbf61f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898186518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1898186518
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1085071070
Short name T162
Test name
Test status
Simulation time 17620999 ps
CPU time 0.85 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 216552 kb
Host smart-49e6c1da-aac9-4ccc-ac88-01780d05631d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085071070 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1085071070
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2675935296
Short name T129
Test name
Test status
Simulation time 98988852 ps
CPU time 1.15 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 217140 kb
Host smart-da07cd7e-2d9f-4f4c-9cb1-6a80a0418cce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675935296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2675935296
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1608421662
Short name T956
Test name
Test status
Simulation time 22267300 ps
CPU time 1.33 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 224284 kb
Host smart-cb5e2f4d-0b31-42c3-b892-89580dfa34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608421662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1608421662
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2853180986
Short name T318
Test name
Test status
Simulation time 164122359 ps
CPU time 1.13 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:40:59 PM PDT 24
Peak memory 217672 kb
Host smart-907fe232-8682-43a1-9bfc-7e3873234e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853180986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2853180986
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2312760961
Short name T189
Test name
Test status
Simulation time 26934119 ps
CPU time 1.04 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:41:00 PM PDT 24
Peak memory 215788 kb
Host smart-7ccb2291-e65d-4c3c-a1cc-18fcdb7a1043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312760961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2312760961
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2089274440
Short name T829
Test name
Test status
Simulation time 18517807 ps
CPU time 1.07 seconds
Started Jul 11 05:40:52 PM PDT 24
Finished Jul 11 05:40:55 PM PDT 24
Peak memory 215576 kb
Host smart-09f91b46-e537-487b-b10d-b25208fc3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089274440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2089274440
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1875332436
Short name T543
Test name
Test status
Simulation time 229566596 ps
CPU time 3 seconds
Started Jul 11 05:40:47 PM PDT 24
Finished Jul 11 05:40:51 PM PDT 24
Peak memory 220040 kb
Host smart-3c7f61dc-66ac-4e72-9ada-d32fa7350b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875332436 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1875332436
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.693132997
Short name T847
Test name
Test status
Simulation time 240796295647 ps
CPU time 2681.52 seconds
Started Jul 11 05:41:01 PM PDT 24
Finished Jul 11 06:25:43 PM PDT 24
Peak memory 229304 kb
Host smart-28b8ec45-6cb7-49d4-b5da-bfc24caea492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693132997 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.693132997
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4262248081
Short name T182
Test name
Test status
Simulation time 24873622 ps
CPU time 1.26 seconds
Started Jul 11 05:39:10 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 220312 kb
Host smart-4b50901f-c535-4afc-898a-029821548fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262248081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4262248081
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.669582986
Short name T544
Test name
Test status
Simulation time 48351222 ps
CPU time 0.99 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 215156 kb
Host smart-df3b6ad5-d71e-49f6-869a-5e42cc725835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669582986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.669582986
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.743038316
Short name T605
Test name
Test status
Simulation time 19972802 ps
CPU time 0.98 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 216224 kb
Host smart-542ff511-bd9b-4790-b736-c06464a02ab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743038316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.743038316
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3736322974
Short name T108
Test name
Test status
Simulation time 143849584 ps
CPU time 1.23 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 217144 kb
Host smart-0cd5982c-75c8-41a6-b6a1-33cf2794f5ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736322974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3736322974
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.851218677
Short name T506
Test name
Test status
Simulation time 19982954 ps
CPU time 1.06 seconds
Started Jul 11 05:38:50 PM PDT 24
Finished Jul 11 05:38:52 PM PDT 24
Peak memory 218796 kb
Host smart-5daef77e-783a-4091-986b-24f3fef26c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851218677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.851218677
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3077758818
Short name T655
Test name
Test status
Simulation time 77624057 ps
CPU time 1.12 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:39:08 PM PDT 24
Peak memory 217524 kb
Host smart-4f88e922-855f-4d26-9982-ca49df9ce812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077758818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3077758818
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2029702787
Short name T970
Test name
Test status
Simulation time 22396003 ps
CPU time 0.99 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 216096 kb
Host smart-721ddf9b-0a04-48eb-9a11-7bd90a447c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029702787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2029702787
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2215033015
Short name T27
Test name
Test status
Simulation time 24232615 ps
CPU time 0.96 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 207464 kb
Host smart-a6bda6d9-b7fb-425b-b388-a9699f139728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215033015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2215033015
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2052023063
Short name T564
Test name
Test status
Simulation time 23383187 ps
CPU time 0.92 seconds
Started Jul 11 05:38:53 PM PDT 24
Finished Jul 11 05:38:56 PM PDT 24
Peak memory 215612 kb
Host smart-5fc5b3a1-abbe-47e0-9ebc-6c6618011e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052023063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2052023063
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.4161438770
Short name T785
Test name
Test status
Simulation time 863125758 ps
CPU time 4.51 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 220392 kb
Host smart-6db7eb22-52df-4dd8-a144-02e4bf9f468b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161438770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.4161438770
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1970811752
Short name T725
Test name
Test status
Simulation time 107910394512 ps
CPU time 1196.42 seconds
Started Jul 11 05:39:09 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 223604 kb
Host smart-f13cb1e4-0394-4eda-949a-c2da138c55f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970811752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1970811752
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1234358292
Short name T177
Test name
Test status
Simulation time 35649145 ps
CPU time 1.13 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 220064 kb
Host smart-a20cfbc2-f97c-4c6f-9376-d75be4500120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234358292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1234358292
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3400725845
Short name T586
Test name
Test status
Simulation time 40438277 ps
CPU time 0.97 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 223924 kb
Host smart-184fd2e8-438a-4c61-9af8-3936baadbbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400725845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3400725845
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2997358321
Short name T300
Test name
Test status
Simulation time 43846386 ps
CPU time 1.48 seconds
Started Jul 11 05:40:59 PM PDT 24
Finished Jul 11 05:41:02 PM PDT 24
Peak memory 219212 kb
Host smart-a9377e60-c07d-4c67-80e0-119ebca587b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997358321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2997358321
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3263008237
Short name T668
Test name
Test status
Simulation time 94174952 ps
CPU time 1.17 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 219224 kb
Host smart-f0481290-5cb7-4593-8368-890de1fb03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263008237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3263008237
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.4166870306
Short name T819
Test name
Test status
Simulation time 19534513 ps
CPU time 1.23 seconds
Started Jul 11 05:40:53 PM PDT 24
Finished Jul 11 05:40:56 PM PDT 24
Peak memory 229816 kb
Host smart-81be01e6-7ff5-4d4c-9d6a-44997211ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166870306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4166870306
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.162673096
Short name T982
Test name
Test status
Simulation time 74906169 ps
CPU time 1.08 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 218852 kb
Host smart-2eb146b7-7c88-4af6-86a1-8a081120bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162673096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.162673096
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1167604393
Short name T256
Test name
Test status
Simulation time 77862733 ps
CPU time 1.18 seconds
Started Jul 11 05:40:52 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 218840 kb
Host smart-9c8c655a-54f0-471b-859b-ceb4fd3c67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167604393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1167604393
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4006634786
Short name T45
Test name
Test status
Simulation time 23569494 ps
CPU time 1.02 seconds
Started Jul 11 05:40:52 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 229784 kb
Host smart-43f61555-be88-4002-8486-a0083fa8f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006634786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4006634786
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3175848204
Short name T952
Test name
Test status
Simulation time 62880635 ps
CPU time 1.32 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:16 PM PDT 24
Peak memory 218556 kb
Host smart-ceeefce9-3bc7-4009-a005-29c7819acd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175848204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3175848204
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.523488241
Short name T590
Test name
Test status
Simulation time 44565257 ps
CPU time 1.18 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:54 PM PDT 24
Peak memory 219980 kb
Host smart-78f8fd05-77ba-4baf-a2f6-5e1fdcc3944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523488241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.523488241
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2659553131
Short name T106
Test name
Test status
Simulation time 20694316 ps
CPU time 1.11 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 219976 kb
Host smart-7e1cea52-3f5c-4cdb-aff4-535dec6d3c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659553131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2659553131
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4159704549
Short name T511
Test name
Test status
Simulation time 259916996 ps
CPU time 3.25 seconds
Started Jul 11 05:41:11 PM PDT 24
Finished Jul 11 05:41:16 PM PDT 24
Peak memory 220064 kb
Host smart-76430e8e-7609-493b-af1d-e2e935439425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159704549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4159704549
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.542829346
Short name T313
Test name
Test status
Simulation time 40981790 ps
CPU time 1.13 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 220156 kb
Host smart-d6b3b503-160c-4699-8a4d-0c49f7c319e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542829346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.542829346
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1487937000
Short name T84
Test name
Test status
Simulation time 46030099 ps
CPU time 0.84 seconds
Started Jul 11 05:41:09 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 218636 kb
Host smart-db440de7-79b8-4176-8437-5d72ee279769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487937000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1487937000
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.46464842
Short name T993
Test name
Test status
Simulation time 24892957 ps
CPU time 0.94 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 217512 kb
Host smart-73f344c6-8211-405a-9394-dc78c3cd57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46464842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.46464842
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3836675393
Short name T677
Test name
Test status
Simulation time 92136648 ps
CPU time 1.11 seconds
Started Jul 11 05:40:54 PM PDT 24
Finished Jul 11 05:40:56 PM PDT 24
Peak memory 218888 kb
Host smart-b6b710f4-cb1c-41c3-a691-7f8adf84280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836675393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3836675393
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.432764030
Short name T64
Test name
Test status
Simulation time 18969904 ps
CPU time 1.15 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 219960 kb
Host smart-ecdad3b2-c084-49a6-be29-129faff78f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432764030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.432764030
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3333455873
Short name T354
Test name
Test status
Simulation time 30984517 ps
CPU time 1.12 seconds
Started Jul 11 05:41:09 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 217684 kb
Host smart-30932c3d-9912-4f93-a92f-63e9f5b667e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333455873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3333455873
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.244552238
Short name T489
Test name
Test status
Simulation time 31011950 ps
CPU time 1.21 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 218820 kb
Host smart-e48aad7f-cea5-4ae0-94f1-bdf4321243a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244552238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.244552238
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.495487643
Short name T178
Test name
Test status
Simulation time 24358448 ps
CPU time 0.94 seconds
Started Jul 11 05:41:10 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 218668 kb
Host smart-41982cf3-0d77-4fdd-8273-ba6504424f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495487643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.495487643
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.395100464
Short name T832
Test name
Test status
Simulation time 67164126 ps
CPU time 1.19 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 219140 kb
Host smart-738e0149-1592-4c09-a421-949e0ddd028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395100464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.395100464
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1319402768
Short name T308
Test name
Test status
Simulation time 44964364 ps
CPU time 1.25 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:41:00 PM PDT 24
Peak memory 219896 kb
Host smart-f110f72d-3e44-4095-bd09-731b5fd78980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319402768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1319402768
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3162917343
Short name T102
Test name
Test status
Simulation time 46078463 ps
CPU time 1.08 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:52 PM PDT 24
Peak memory 229956 kb
Host smart-d1d9a026-c618-47cc-9314-9aa570f07870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162917343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3162917343
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2093269457
Short name T479
Test name
Test status
Simulation time 39279673 ps
CPU time 1.02 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 217520 kb
Host smart-746c6fd3-310b-48b3-a5c4-f4162b071b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093269457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2093269457
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3039613482
Short name T140
Test name
Test status
Simulation time 99316431 ps
CPU time 1.42 seconds
Started Jul 11 05:40:53 PM PDT 24
Finished Jul 11 05:40:56 PM PDT 24
Peak memory 220000 kb
Host smart-3b6e1a65-cd46-4f4a-bcad-eb09e28f010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039613482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3039613482
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2680621231
Short name T853
Test name
Test status
Simulation time 19782055 ps
CPU time 1.05 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 218736 kb
Host smart-b553d35d-5657-4bb0-b429-b4624987b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680621231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2680621231
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1116296269
Short name T49
Test name
Test status
Simulation time 84065482 ps
CPU time 1.39 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:52 PM PDT 24
Peak memory 219172 kb
Host smart-e10566a1-3f63-4f6d-8b3e-0d0d06b73614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116296269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1116296269
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1606739201
Short name T230
Test name
Test status
Simulation time 54935348 ps
CPU time 1.34 seconds
Started Jul 11 05:41:01 PM PDT 24
Finished Jul 11 05:41:03 PM PDT 24
Peak memory 216052 kb
Host smart-392f79ef-218d-42cc-af6c-43103021e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606739201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1606739201
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3982975081
Short name T380
Test name
Test status
Simulation time 22751095 ps
CPU time 0.91 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 219712 kb
Host smart-8964ddc3-1dde-4ee5-9e3a-00259774a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982975081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3982975081
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1695979588
Short name T598
Test name
Test status
Simulation time 28651001 ps
CPU time 1.25 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 218824 kb
Host smart-259ae290-c633-4b32-bf29-8398796adb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695979588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1695979588
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.304769453
Short name T206
Test name
Test status
Simulation time 196199048 ps
CPU time 1.31 seconds
Started Jul 11 05:39:09 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 219076 kb
Host smart-dfc9c1a1-31af-42ec-a59b-1f1d28d4f34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304769453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.304769453
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2679587738
Short name T59
Test name
Test status
Simulation time 24819497 ps
CPU time 0.9 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 206948 kb
Host smart-615a34da-44b0-47b0-a82a-2823014314ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679587738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2679587738
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1196838721
Short name T616
Test name
Test status
Simulation time 11537187 ps
CPU time 0.9 seconds
Started Jul 11 05:39:04 PM PDT 24
Finished Jul 11 05:39:06 PM PDT 24
Peak memory 215904 kb
Host smart-8ae51bda-a04f-47c3-86ca-06105079e338
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196838721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1196838721
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4067614839
Short name T944
Test name
Test status
Simulation time 36503858 ps
CPU time 1.21 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 218704 kb
Host smart-84a8877f-0477-40fc-94d5-c9066f2329a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067614839 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4067614839
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2588080044
Short name T996
Test name
Test status
Simulation time 37241476 ps
CPU time 0.91 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 220092 kb
Host smart-d77683e3-643d-48de-a92b-4ebd55c16401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588080044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2588080044
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1316343963
Short name T376
Test name
Test status
Simulation time 32946209 ps
CPU time 1.27 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 218688 kb
Host smart-287fd3b9-974e-4bdd-be23-b3bf6fd3ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316343963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1316343963
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3772328493
Short name T823
Test name
Test status
Simulation time 85333518 ps
CPU time 0.9 seconds
Started Jul 11 05:39:09 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 215488 kb
Host smart-89029a0b-a6df-4e7c-bf93-2aaa5499c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772328493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3772328493
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3420658946
Short name T25
Test name
Test status
Simulation time 26402732 ps
CPU time 0.93 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 207460 kb
Host smart-b2cb7cae-00ea-48ea-83cb-e1092a4ce7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420658946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3420658946
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3532745285
Short name T921
Test name
Test status
Simulation time 19355465 ps
CPU time 1 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 215664 kb
Host smart-70bbf20b-106f-49d8-9292-10ffd9e40208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532745285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3532745285
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1840368213
Short name T545
Test name
Test status
Simulation time 850443583 ps
CPU time 2.91 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 215620 kb
Host smart-cea26c6c-0fc7-4742-95e3-a3227e6c75be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840368213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1840368213
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1347058419
Short name T248
Test name
Test status
Simulation time 154013290377 ps
CPU time 854.51 seconds
Started Jul 11 05:38:54 PM PDT 24
Finished Jul 11 05:53:11 PM PDT 24
Peak memory 222324 kb
Host smart-691111e3-f51b-4458-8b86-a759f2d2c51b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347058419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1347058419
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2374244073
Short name T124
Test name
Test status
Simulation time 34627347 ps
CPU time 1.37 seconds
Started Jul 11 05:41:01 PM PDT 24
Finished Jul 11 05:41:03 PM PDT 24
Peak memory 216056 kb
Host smart-53308a86-971f-49b1-8587-bbf85f8a231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374244073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2374244073
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3125706662
Short name T386
Test name
Test status
Simulation time 17727096 ps
CPU time 1.02 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 218224 kb
Host smart-3b570b7f-2644-4bf3-8fd2-8f5d766a2318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125706662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3125706662
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2583901096
Short name T453
Test name
Test status
Simulation time 116801247 ps
CPU time 1.5 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 219140 kb
Host smart-20792bba-f74d-4d6d-8f61-56cd82c3f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583901096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2583901096
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1295935328
Short name T255
Test name
Test status
Simulation time 98026511 ps
CPU time 1.2 seconds
Started Jul 11 05:41:09 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 219796 kb
Host smart-b727dfaa-b167-4aa8-b9ef-9c354cef2040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295935328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1295935328
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.384206906
Short name T46
Test name
Test status
Simulation time 19812313 ps
CPU time 1.17 seconds
Started Jul 11 05:40:49 PM PDT 24
Finished Jul 11 05:40:52 PM PDT 24
Peak memory 229852 kb
Host smart-00585c23-3b75-4f89-92af-14d9fab0c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384206906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.384206906
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3584751294
Short name T992
Test name
Test status
Simulation time 52014164 ps
CPU time 1.23 seconds
Started Jul 11 05:41:01 PM PDT 24
Finished Jul 11 05:41:03 PM PDT 24
Peak memory 217856 kb
Host smart-d21a2889-b785-413a-9f67-4f1684d9b2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584751294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3584751294
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.77491133
Short name T627
Test name
Test status
Simulation time 220040831 ps
CPU time 1.35 seconds
Started Jul 11 05:41:01 PM PDT 24
Finished Jul 11 05:41:03 PM PDT 24
Peak memory 220096 kb
Host smart-639a5258-2102-4e31-af6a-35099fdb6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77491133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.77491133
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2370587682
Short name T199
Test name
Test status
Simulation time 29663871 ps
CPU time 1.16 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 219828 kb
Host smart-2226b5ba-a163-4266-9f20-22df739fd856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370587682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2370587682
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2338934359
Short name T904
Test name
Test status
Simulation time 70021882 ps
CPU time 1.11 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 217580 kb
Host smart-37589451-e333-42db-b163-1cd0a3eba8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338934359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2338934359
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.4065897909
Short name T165
Test name
Test status
Simulation time 87767971 ps
CPU time 1.12 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 215948 kb
Host smart-a387b34e-9355-485f-80fd-66790eabb460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065897909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.4065897909
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.969379535
Short name T969
Test name
Test status
Simulation time 58329447 ps
CPU time 1 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 220180 kb
Host smart-b531fb17-f29e-4de3-b11e-235a1f2b3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969379535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.969379535
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2475618640
Short name T488
Test name
Test status
Simulation time 60861104 ps
CPU time 1.28 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 220252 kb
Host smart-3a2514b1-ab49-4c1b-9f95-2098498f3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475618640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2475618640
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3606870832
Short name T293
Test name
Test status
Simulation time 80807165 ps
CPU time 1.11 seconds
Started Jul 11 05:40:50 PM PDT 24
Finished Jul 11 05:40:53 PM PDT 24
Peak memory 218608 kb
Host smart-09857f24-688e-47d9-8097-654b9cb372ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606870832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3606870832
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1340969091
Short name T160
Test name
Test status
Simulation time 59020811 ps
CPU time 0.85 seconds
Started Jul 11 05:41:10 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 218644 kb
Host smart-1e477f93-92b7-40a3-8551-638444ab8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340969091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1340969091
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.545496438
Short name T321
Test name
Test status
Simulation time 83436191 ps
CPU time 1.3 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 219424 kb
Host smart-8c13fcaa-3969-4fb1-9179-c09beefe4d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545496438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.545496438
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3320013071
Short name T207
Test name
Test status
Simulation time 47881081 ps
CPU time 1.25 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 218640 kb
Host smart-41c6968e-2d92-48e6-9edd-05b9a4594ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320013071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3320013071
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3709381025
Short name T771
Test name
Test status
Simulation time 18362613 ps
CPU time 1 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 218708 kb
Host smart-ca1dfc9e-1dea-4782-8a44-6d5712980a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709381025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3709381025
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3334414048
Short name T727
Test name
Test status
Simulation time 57448517 ps
CPU time 1.29 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 219704 kb
Host smart-5b742806-6f46-47bd-bef3-c9083c1aae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334414048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3334414048
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2710949861
Short name T473
Test name
Test status
Simulation time 77161341 ps
CPU time 1.15 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:40:58 PM PDT 24
Peak memory 218936 kb
Host smart-b7728630-b27b-4925-bd4c-88eb6d086ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710949861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2710949861
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2154824635
Short name T798
Test name
Test status
Simulation time 47442283 ps
CPU time 0.87 seconds
Started Jul 11 05:41:03 PM PDT 24
Finished Jul 11 05:41:05 PM PDT 24
Peak memory 215540 kb
Host smart-8bbe3410-71bb-4918-ab09-919a9498ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154824635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2154824635
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1143591559
Short name T843
Test name
Test status
Simulation time 61454947 ps
CPU time 1.29 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 217740 kb
Host smart-086e94ce-588a-4776-b050-6105462c3250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143591559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1143591559
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.228767931
Short name T759
Test name
Test status
Simulation time 41775886 ps
CPU time 1.18 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:08 PM PDT 24
Peak memory 219116 kb
Host smart-593f5bd4-0a26-48f5-aff8-95c17b4e2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228767931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.228767931
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2370886832
Short name T693
Test name
Test status
Simulation time 42664042 ps
CPU time 0.91 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 224080 kb
Host smart-5c9e2b92-0028-49fe-8ca8-e2c97991c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370886832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2370886832
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.688397989
Short name T778
Test name
Test status
Simulation time 261120237 ps
CPU time 1.03 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 217480 kb
Host smart-a1f70784-8da3-4a2f-976d-53ecbdff5d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688397989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.688397989
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.479215507
Short name T465
Test name
Test status
Simulation time 101349961 ps
CPU time 1.23 seconds
Started Jul 11 05:40:53 PM PDT 24
Finished Jul 11 05:40:56 PM PDT 24
Peak memory 220092 kb
Host smart-38f50415-8949-4dfd-a6c6-0de53e1ac9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479215507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.479215507
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.4018441235
Short name T57
Test name
Test status
Simulation time 41756241 ps
CPU time 1.08 seconds
Started Jul 11 05:41:11 PM PDT 24
Finished Jul 11 05:41:15 PM PDT 24
Peak memory 220016 kb
Host smart-35d25a91-b109-44ef-8cdf-ed3d36f8760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018441235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4018441235
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.942965819
Short name T504
Test name
Test status
Simulation time 36444949 ps
CPU time 1.64 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:06 PM PDT 24
Peak memory 219020 kb
Host smart-6eba30e9-cebd-4064-97f0-261e184baa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942965819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.942965819
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.427646191
Short name T145
Test name
Test status
Simulation time 53878114 ps
CPU time 1.29 seconds
Started Jul 11 05:41:08 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 215916 kb
Host smart-67e84916-8a60-4962-a1a2-989ca8c7408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427646191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.427646191
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.246960037
Short name T175
Test name
Test status
Simulation time 43258086 ps
CPU time 0.99 seconds
Started Jul 11 05:41:03 PM PDT 24
Finished Jul 11 05:41:05 PM PDT 24
Peak memory 224040 kb
Host smart-8dd74437-62e9-4472-b53e-10bd693e9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246960037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.246960037
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.833403030
Short name T330
Test name
Test status
Simulation time 75414628 ps
CPU time 1.09 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 217652 kb
Host smart-8b9df06b-2a71-49ee-aae7-b0f3d162e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833403030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.833403030
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1455927009
Short name T752
Test name
Test status
Simulation time 302810167 ps
CPU time 1.48 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 219168 kb
Host smart-40a24ec7-184f-4ccd-a582-2c8fcf3a26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455927009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1455927009
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3469159084
Short name T415
Test name
Test status
Simulation time 23925369 ps
CPU time 0.86 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 207028 kb
Host smart-c725fa3f-5f1c-4860-81f7-dcb8cef6e838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469159084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3469159084
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1005280285
Short name T965
Test name
Test status
Simulation time 41668427 ps
CPU time 0.88 seconds
Started Jul 11 05:39:12 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 216576 kb
Host smart-6bc3d49b-88f8-4215-9525-0121894c9b66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005280285 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1005280285
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3997997704
Short name T133
Test name
Test status
Simulation time 80426540 ps
CPU time 1.25 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 217020 kb
Host smart-1d71a0c9-669b-48ed-ab9e-b735d3566375
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997997704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3997997704
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2844473806
Short name T950
Test name
Test status
Simulation time 24320126 ps
CPU time 0.9 seconds
Started Jul 11 05:39:02 PM PDT 24
Finished Jul 11 05:39:03 PM PDT 24
Peak memory 218388 kb
Host smart-823cb847-7748-421c-bfb7-5d1f41ea6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844473806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2844473806
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.2282348575
Short name T237
Test name
Test status
Simulation time 23715408 ps
CPU time 1.14 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 224336 kb
Host smart-55374345-c608-4f49-8c95-239073e88980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282348575 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2282348575
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1212022241
Short name T310
Test name
Test status
Simulation time 19018421 ps
CPU time 1.05 seconds
Started Jul 11 05:39:04 PM PDT 24
Finished Jul 11 05:39:06 PM PDT 24
Peak memory 207444 kb
Host smart-6418f723-addd-4baa-8095-eb681270347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212022241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1212022241
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.666995973
Short name T394
Test name
Test status
Simulation time 17373221 ps
CPU time 0.96 seconds
Started Jul 11 05:39:30 PM PDT 24
Finished Jul 11 05:39:32 PM PDT 24
Peak memory 215580 kb
Host smart-ad800a90-e2c0-4771-b7e1-b7aca7f87721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666995973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.666995973
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1062745268
Short name T499
Test name
Test status
Simulation time 489034670 ps
CPU time 5.25 seconds
Started Jul 11 05:39:03 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 215616 kb
Host smart-1fb7e08c-dcd7-4a9a-a249-eec90502f38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062745268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1062745268
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1787330154
Short name T215
Test name
Test status
Simulation time 285445979046 ps
CPU time 1782.45 seconds
Started Jul 11 05:38:57 PM PDT 24
Finished Jul 11 06:08:41 PM PDT 24
Peak memory 228972 kb
Host smart-786ad579-37a4-42d8-969f-54be1085924a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787330154 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1787330154
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3605164027
Short name T53
Test name
Test status
Simulation time 83365835 ps
CPU time 1.15 seconds
Started Jul 11 05:41:03 PM PDT 24
Finished Jul 11 05:41:06 PM PDT 24
Peak memory 215944 kb
Host smart-e11d22ff-7cef-4de8-b743-90302d2f1044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605164027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3605164027
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1392347912
Short name T103
Test name
Test status
Simulation time 25162520 ps
CPU time 1.17 seconds
Started Jul 11 05:41:08 PM PDT 24
Finished Jul 11 05:41:12 PM PDT 24
Peak memory 229956 kb
Host smart-84cde4c1-9e52-4f62-9b1c-d319fd604428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392347912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1392347912
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2460909735
Short name T822
Test name
Test status
Simulation time 115291006 ps
CPU time 1.35 seconds
Started Jul 11 05:40:56 PM PDT 24
Finished Jul 11 05:40:58 PM PDT 24
Peak memory 219408 kb
Host smart-9486cff5-3534-437f-86e8-86ab7190822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460909735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2460909735
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.910242309
Short name T497
Test name
Test status
Simulation time 41078107 ps
CPU time 1.13 seconds
Started Jul 11 05:41:09 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 218704 kb
Host smart-138d2449-551a-4bbd-b7dd-c9ec4f086046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910242309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.910242309
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.852561790
Short name T114
Test name
Test status
Simulation time 26485048 ps
CPU time 1 seconds
Started Jul 11 05:40:55 PM PDT 24
Finished Jul 11 05:40:57 PM PDT 24
Peak memory 220128 kb
Host smart-e18bf96b-f844-43cf-aa19-ce456272b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852561790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.852561790
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2362393105
Short name T412
Test name
Test status
Simulation time 46461982 ps
CPU time 1.66 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 218348 kb
Host smart-ebe7b668-c33c-473c-83dd-cfbb9cee5a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362393105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2362393105
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.691874992
Short name T438
Test name
Test status
Simulation time 32580420 ps
CPU time 1.29 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:11 PM PDT 24
Peak memory 215996 kb
Host smart-452a0946-ba95-4b2a-a8ee-fa25524321dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691874992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.691874992
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1612050972
Short name T450
Test name
Test status
Simulation time 43350252 ps
CPU time 1.22 seconds
Started Jul 11 05:41:02 PM PDT 24
Finished Jul 11 05:41:04 PM PDT 24
Peak memory 225756 kb
Host smart-a7b2a33c-f2a9-45f7-acc3-f018ab72348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612050972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1612050972
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3005205207
Short name T978
Test name
Test status
Simulation time 2308638874 ps
CPU time 62.43 seconds
Started Jul 11 05:40:58 PM PDT 24
Finished Jul 11 05:42:03 PM PDT 24
Peak memory 220592 kb
Host smart-f7071ae9-e1be-4626-9259-4b1b85ec67b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005205207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3005205207
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.4116753084
Short name T414
Test name
Test status
Simulation time 231824971 ps
CPU time 1.16 seconds
Started Jul 11 05:41:34 PM PDT 24
Finished Jul 11 05:41:38 PM PDT 24
Peak memory 220028 kb
Host smart-53ddf858-f715-4c6a-9d7a-151e29b8735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116753084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.4116753084
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2124606967
Short name T194
Test name
Test status
Simulation time 28229502 ps
CPU time 1.25 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:08 PM PDT 24
Peak memory 220124 kb
Host smart-f169a2ff-7922-46a6-982a-0785ac8eafe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124606967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2124606967
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3078286690
Short name T796
Test name
Test status
Simulation time 220544186 ps
CPU time 1.25 seconds
Started Jul 11 05:41:21 PM PDT 24
Finished Jul 11 05:41:30 PM PDT 24
Peak memory 217672 kb
Host smart-f562f0e8-6e68-4c0b-ba6c-1baccecd9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078286690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3078286690
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3199575080
Short name T641
Test name
Test status
Simulation time 37407277 ps
CPU time 1.29 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 219712 kb
Host smart-c41946ed-ea06-45d5-a777-c8a0922618f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199575080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3199575080
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.346567582
Short name T235
Test name
Test status
Simulation time 20430735 ps
CPU time 1 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 218440 kb
Host smart-90b087ed-5f18-4ea6-89db-304ece8f8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346567582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.346567582
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.931795763
Short name T515
Test name
Test status
Simulation time 36707484 ps
CPU time 1.64 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:26 PM PDT 24
Peak memory 218964 kb
Host smart-f90f8061-a049-4be6-b754-12a0b9100532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931795763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.931795763
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2859146732
Short name T210
Test name
Test status
Simulation time 80638504 ps
CPU time 1.17 seconds
Started Jul 11 05:41:08 PM PDT 24
Finished Jul 11 05:41:13 PM PDT 24
Peak memory 220500 kb
Host smart-e95d7a19-0696-4380-8a34-d42aa57497b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859146732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2859146732
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2175233956
Short name T147
Test name
Test status
Simulation time 28481564 ps
CPU time 0.82 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:25 PM PDT 24
Peak memory 218700 kb
Host smart-bf1df1f9-9e61-49c6-93da-e408fece13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175233956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2175233956
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.10376139
Short name T265
Test name
Test status
Simulation time 54824812 ps
CPU time 1.32 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 217732 kb
Host smart-cc7c0704-f4dc-452b-80a5-65453b81bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10376139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.10376139
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1505760731
Short name T758
Test name
Test status
Simulation time 49361197 ps
CPU time 1.23 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:08 PM PDT 24
Peak memory 220036 kb
Host smart-e6a0d073-c1da-4a10-bd67-19e6de36ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505760731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1505760731
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1947735441
Short name T466
Test name
Test status
Simulation time 58063646 ps
CPU time 1.37 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:22 PM PDT 24
Peak memory 226048 kb
Host smart-0d07e01e-30b5-479a-89d5-b79ef41b0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947735441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1947735441
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.213203594
Short name T907
Test name
Test status
Simulation time 29699334 ps
CPU time 1.28 seconds
Started Jul 11 05:40:55 PM PDT 24
Finished Jul 11 05:40:57 PM PDT 24
Peak memory 215628 kb
Host smart-a2e9bdc9-a00d-40d6-b7a5-9fc8b332fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213203594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.213203594
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.249785035
Short name T254
Test name
Test status
Simulation time 82349571 ps
CPU time 1.19 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 219632 kb
Host smart-5479bc91-29de-4e1a-bac3-110d7fcf0dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249785035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.249785035
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3877311406
Short name T862
Test name
Test status
Simulation time 70812048 ps
CPU time 0.84 seconds
Started Jul 11 05:41:04 PM PDT 24
Finished Jul 11 05:41:06 PM PDT 24
Peak memory 218624 kb
Host smart-dd537308-9568-4573-a72a-d4605ef2df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877311406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3877311406
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1960850404
Short name T979
Test name
Test status
Simulation time 96447623 ps
CPU time 1.55 seconds
Started Jul 11 05:41:07 PM PDT 24
Finished Jul 11 05:41:12 PM PDT 24
Peak memory 219080 kb
Host smart-484d648e-c485-4bea-bade-47b5253f0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960850404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1960850404
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.992779997
Short name T566
Test name
Test status
Simulation time 41759557 ps
CPU time 1.33 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 216052 kb
Host smart-6380bc59-9987-4ade-8001-1b3c867d120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992779997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.992779997
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.254598737
Short name T833
Test name
Test status
Simulation time 51411178 ps
CPU time 1.1 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:16 PM PDT 24
Peak memory 230112 kb
Host smart-d2da788a-4126-4038-81ae-6cabb21c4931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254598737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.254598737
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3306798709
Short name T573
Test name
Test status
Simulation time 37682065 ps
CPU time 1.42 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:22 PM PDT 24
Peak memory 217720 kb
Host smart-f01ad442-46d1-4c5e-ab6a-210b6ade16a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306798709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3306798709
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3864257332
Short name T205
Test name
Test status
Simulation time 98710169 ps
CPU time 1.23 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 218680 kb
Host smart-ac3e33f3-1f71-4258-b7a0-f6a246a2dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864257332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3864257332
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3952515266
Short name T763
Test name
Test status
Simulation time 77066221 ps
CPU time 0.85 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 218668 kb
Host smart-eeda0a90-2ffd-4337-a6e0-19787f3c6ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952515266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3952515266
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2953967273
Short name T744
Test name
Test status
Simulation time 279776060 ps
CPU time 2.18 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 219028 kb
Host smart-1047c8fd-d6e5-4be5-b191-282b76ebdfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953967273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2953967273
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4200127350
Short name T111
Test name
Test status
Simulation time 28989136 ps
CPU time 1.27 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 220376 kb
Host smart-6c298191-ff6b-4a33-8526-26718d177ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200127350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4200127350
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2975605081
Short name T363
Test name
Test status
Simulation time 45750735 ps
CPU time 0.87 seconds
Started Jul 11 05:39:08 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 215320 kb
Host smart-64ee0471-4e43-4374-a5f1-4de3dff2253a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975605081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2975605081
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2328956494
Short name T963
Test name
Test status
Simulation time 21536395 ps
CPU time 0.93 seconds
Started Jul 11 05:39:11 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 216572 kb
Host smart-e8e1a344-4090-4f2e-820e-fbf6610c0f30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328956494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2328956494
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.100618022
Short name T704
Test name
Test status
Simulation time 112539970 ps
CPU time 1.12 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 217316 kb
Host smart-3cd58e0d-32d1-40ea-ac7c-6560226edfb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100618022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.100618022
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3293411177
Short name T738
Test name
Test status
Simulation time 38020084 ps
CPU time 1.14 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 230128 kb
Host smart-2e68dafc-c6ae-4e93-9e38-ddf36aa2594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293411177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3293411177
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2463028033
Short name T835
Test name
Test status
Simulation time 63991093 ps
CPU time 1.23 seconds
Started Jul 11 05:39:03 PM PDT 24
Finished Jul 11 05:39:06 PM PDT 24
Peak memory 218696 kb
Host smart-dab24dc8-98d0-415a-9218-9abd203f6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463028033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2463028033
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2566333380
Short name T988
Test name
Test status
Simulation time 26362443 ps
CPU time 0.94 seconds
Started Jul 11 05:39:04 PM PDT 24
Finished Jul 11 05:39:06 PM PDT 24
Peak memory 215852 kb
Host smart-d9ce6f7e-d3f1-4b9a-91a2-ca78a83c13e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566333380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2566333380
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.110749304
Short name T790
Test name
Test status
Simulation time 18563054 ps
CPU time 1.04 seconds
Started Jul 11 05:39:31 PM PDT 24
Finished Jul 11 05:39:34 PM PDT 24
Peak memory 207396 kb
Host smart-3cb7e5df-1136-4faf-9d26-94c670ace16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110749304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.110749304
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3058192108
Short name T377
Test name
Test status
Simulation time 36369951 ps
CPU time 0.91 seconds
Started Jul 11 05:39:05 PM PDT 24
Finished Jul 11 05:39:09 PM PDT 24
Peak memory 215676 kb
Host smart-51a79b10-e458-4e48-833d-9f8ab2c8cc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058192108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3058192108
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2052233359
Short name T806
Test name
Test status
Simulation time 316319206 ps
CPU time 2.77 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 217612 kb
Host smart-59bcbe0d-09b4-4f77-9dbe-aa57d04da6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052233359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2052233359
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_alert.2785600945
Short name T926
Test name
Test status
Simulation time 79365809 ps
CPU time 1.21 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 219324 kb
Host smart-5d276876-f604-463f-81dd-4bcdd26cb472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785600945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2785600945
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3396280823
Short name T404
Test name
Test status
Simulation time 18465135 ps
CPU time 1.05 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 218596 kb
Host smart-d9e9e575-8913-4ce2-953f-6902e955d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396280823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3396280823
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.320204678
Short name T462
Test name
Test status
Simulation time 126250154 ps
CPU time 2.83 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 219712 kb
Host smart-c43bb105-6a98-4ae8-9a8f-9331439d0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320204678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.320204678
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1721840878
Short name T920
Test name
Test status
Simulation time 65869577 ps
CPU time 1.02 seconds
Started Jul 11 05:41:08 PM PDT 24
Finished Jul 11 05:41:12 PM PDT 24
Peak memory 218640 kb
Host smart-a7e10689-8032-4108-83d9-14f3d4267817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721840878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1721840878
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4027071615
Short name T168
Test name
Test status
Simulation time 32844914 ps
CPU time 0.84 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:21 PM PDT 24
Peak memory 218740 kb
Host smart-74246d3b-1bac-4bfc-9d93-ce0a084eb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027071615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4027071615
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.980849638
Short name T391
Test name
Test status
Simulation time 104167224 ps
CPU time 1.23 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 220292 kb
Host smart-da268b0f-0fdd-4c5c-9013-c8a64692e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980849638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.980849638
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4199791925
Short name T297
Test name
Test status
Simulation time 49430872 ps
CPU time 1.21 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 218764 kb
Host smart-0ef9334f-acf3-4851-b2e8-f08c8f1b8d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199791925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4199791925
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1162319276
Short name T47
Test name
Test status
Simulation time 34759778 ps
CPU time 1.02 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 224076 kb
Host smart-4c35ea02-fc01-4b05-97c2-42894ea023ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162319276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1162319276
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.553889630
Short name T923
Test name
Test status
Simulation time 102322080 ps
CPU time 1.27 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:23 PM PDT 24
Peak memory 218688 kb
Host smart-52d7807a-21bc-42ac-a9e9-41cceecafe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553889630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.553889630
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.63392128
Short name T557
Test name
Test status
Simulation time 48284151 ps
CPU time 1.18 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 221040 kb
Host smart-6339d44a-0d86-4c7d-855a-ecf89d6ad12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63392128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.63392128
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_genbits.1337592177
Short name T617
Test name
Test status
Simulation time 47724059 ps
CPU time 1.46 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 217480 kb
Host smart-faab2f07-72c3-4ce8-a125-2cc7b774541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337592177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1337592177
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2566515822
Short name T891
Test name
Test status
Simulation time 147884350 ps
CPU time 1.11 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:46 PM PDT 24
Peak memory 219912 kb
Host smart-f67661a2-1dfc-4fab-bd2d-2a60f22fbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566515822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2566515822
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2620361415
Short name T121
Test name
Test status
Simulation time 89265300 ps
CPU time 1.13 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 229900 kb
Host smart-f76a75df-8bab-4e29-b718-81ae2a382a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620361415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2620361415
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3497534242
Short name T609
Test name
Test status
Simulation time 43310733 ps
CPU time 1.43 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 217576 kb
Host smart-f9069084-8578-47a0-85b1-161de855c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497534242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3497534242
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3264070956
Short name T773
Test name
Test status
Simulation time 46478449 ps
CPU time 1.15 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 219912 kb
Host smart-82aa92c7-0610-4294-8074-7ecd92708c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264070956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3264070956
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2676110833
Short name T665
Test name
Test status
Simulation time 49378575 ps
CPU time 0.9 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:16 PM PDT 24
Peak memory 218624 kb
Host smart-74fd84d8-038e-4b2f-ace8-8ac66af78917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676110833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2676110833
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1791656956
Short name T329
Test name
Test status
Simulation time 75731996 ps
CPU time 1.15 seconds
Started Jul 11 05:41:07 PM PDT 24
Finished Jul 11 05:41:12 PM PDT 24
Peak memory 220300 kb
Host smart-f978b8cd-fcd8-4c69-918f-99de417f4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791656956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1791656956
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.254388637
Short name T498
Test name
Test status
Simulation time 74455563 ps
CPU time 1.21 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 216052 kb
Host smart-4814fd4f-fee7-4616-be97-666a4b0c0d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254388637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.254388637
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2860431736
Short name T858
Test name
Test status
Simulation time 31975156 ps
CPU time 1.17 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 224228 kb
Host smart-a258e289-c8c3-43fe-9389-f03f88597fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860431736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2860431736
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4127118814
Short name T358
Test name
Test status
Simulation time 33511763 ps
CPU time 1.21 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 217684 kb
Host smart-7badd983-89e5-454f-8c36-fafd600e2f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127118814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4127118814
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2705644024
Short name T898
Test name
Test status
Simulation time 63172387 ps
CPU time 1.06 seconds
Started Jul 11 05:41:11 PM PDT 24
Finished Jul 11 05:41:15 PM PDT 24
Peak memory 219956 kb
Host smart-9b6fb68f-f0c7-4d0a-823b-12c50f9394fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705644024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2705644024
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.668757750
Short name T112
Test name
Test status
Simulation time 43781121 ps
CPU time 1.02 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 220856 kb
Host smart-4cb37317-2d4c-4b62-9fc3-60b33c0a13d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668757750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.668757750
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2546062067
Short name T388
Test name
Test status
Simulation time 165953594 ps
CPU time 1.91 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:48 PM PDT 24
Peak memory 220536 kb
Host smart-07e03bb9-1e03-429b-bfdd-12be126eb987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546062067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2546062067
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.916062392
Short name T119
Test name
Test status
Simulation time 193678824 ps
CPU time 1.19 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:10 PM PDT 24
Peak memory 219076 kb
Host smart-43a71c82-bdf7-4a0e-85b4-b03086c277a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916062392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.916062392
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2580578578
Short name T104
Test name
Test status
Simulation time 33511990 ps
CPU time 1.12 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 219704 kb
Host smart-a68127dc-9b4a-469b-bcab-5bd21866122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580578578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2580578578
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3375373565
Short name T816
Test name
Test status
Simulation time 75869029 ps
CPU time 1.97 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 220552 kb
Host smart-8ad5a4b1-8308-4afd-a74a-a9ba7528e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375373565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3375373565
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.4078706018
Short name T692
Test name
Test status
Simulation time 59018151 ps
CPU time 1.17 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 221116 kb
Host smart-d7d2056a-7975-433e-a5d8-6cf531d33963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078706018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.4078706018
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.4002868068
Short name T580
Test name
Test status
Simulation time 20911955 ps
CPU time 0.9 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:10 PM PDT 24
Peak memory 218844 kb
Host smart-c343c268-507f-4820-8d4f-ff4574c17cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002868068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4002868068
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1404259437
Short name T661
Test name
Test status
Simulation time 254178665 ps
CPU time 1.42 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 219004 kb
Host smart-d6d92e44-7b71-4e07-ae7f-d1f172812b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404259437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1404259437
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1076093126
Short name T252
Test name
Test status
Simulation time 118578644 ps
CPU time 1.17 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 221128 kb
Host smart-08816dfb-bead-41ed-91d5-a46fed6aa76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076093126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1076093126
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3933498628
Short name T575
Test name
Test status
Simulation time 50882855 ps
CPU time 0.89 seconds
Started Jul 11 05:39:13 PM PDT 24
Finished Jul 11 05:39:15 PM PDT 24
Peak memory 206984 kb
Host smart-7a3cdb33-c755-4963-aaa1-a6c95fcc408a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933498628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3933498628
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4213926471
Short name T536
Test name
Test status
Simulation time 16809216 ps
CPU time 0.86 seconds
Started Jul 11 05:39:13 PM PDT 24
Finished Jul 11 05:39:15 PM PDT 24
Peak memory 216656 kb
Host smart-dbe8e777-1368-497f-a0d3-bea80c704079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213926471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4213926471
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2094053259
Short name T802
Test name
Test status
Simulation time 40653652 ps
CPU time 1.06 seconds
Started Jul 11 05:39:08 PM PDT 24
Finished Jul 11 05:39:12 PM PDT 24
Peak memory 219916 kb
Host smart-dc90a7d5-53b7-485e-a62b-d9c765897a5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094053259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2094053259
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1411339898
Short name T980
Test name
Test status
Simulation time 27826870 ps
CPU time 0.96 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 224088 kb
Host smart-6723913d-72e4-4dde-98cc-f7e145db0b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411339898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1411339898
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2634024210
Short name T349
Test name
Test status
Simulation time 214570688 ps
CPU time 3.06 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:13 PM PDT 24
Peak memory 220788 kb
Host smart-191c8c6c-eb93-4eb0-aab1-6311f5d2d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634024210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2634024210
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3863541942
Short name T398
Test name
Test status
Simulation time 43507123 ps
CPU time 0.92 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:39:11 PM PDT 24
Peak memory 215852 kb
Host smart-89d85178-4ab2-4d75-93d2-025326fb83a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863541942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3863541942
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2920604551
Short name T856
Test name
Test status
Simulation time 164894098 ps
CPU time 0.88 seconds
Started Jul 11 05:39:03 PM PDT 24
Finished Jul 11 05:39:05 PM PDT 24
Peak memory 207412 kb
Host smart-d54b4a73-5f53-402e-aff2-9ad3bdb2d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920604551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2920604551
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2720136111
Short name T814
Test name
Test status
Simulation time 21768662 ps
CPU time 0.95 seconds
Started Jul 11 05:39:06 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 215740 kb
Host smart-b26ba784-9504-4bdd-a73e-cfb1d749de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720136111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2720136111
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4028182778
Short name T841
Test name
Test status
Simulation time 20246150 ps
CPU time 1 seconds
Started Jul 11 05:39:13 PM PDT 24
Finished Jul 11 05:39:15 PM PDT 24
Peak memory 206820 kb
Host smart-e3a94862-719c-4397-afb8-3a3f7100e923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028182778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4028182778
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.708766298
Short name T964
Test name
Test status
Simulation time 180028821533 ps
CPU time 1058.78 seconds
Started Jul 11 05:39:07 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 223996 kb
Host smart-0636c9f9-3a0c-4747-bec9-d87e31f7d3a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708766298 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.708766298
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.450256235
Short name T647
Test name
Test status
Simulation time 46579619 ps
CPU time 1.13 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 219020 kb
Host smart-607ec7b3-0134-486d-b88c-253d17851481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450256235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.450256235
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2035377271
Short name T127
Test name
Test status
Simulation time 24010569 ps
CPU time 1.16 seconds
Started Jul 11 05:41:17 PM PDT 24
Finished Jul 11 05:41:27 PM PDT 24
Peak memory 220968 kb
Host smart-32407ad9-3a08-41a6-a52e-b8aa983fd887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035377271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2035377271
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3580424489
Short name T232
Test name
Test status
Simulation time 35879903 ps
CPU time 1.47 seconds
Started Jul 11 05:41:21 PM PDT 24
Finished Jul 11 05:41:31 PM PDT 24
Peak memory 218840 kb
Host smart-f9af90f6-ab12-4d4e-b423-ef7fabc73d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580424489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3580424489
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1755175964
Short name T550
Test name
Test status
Simulation time 30010215 ps
CPU time 1.27 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 218996 kb
Host smart-de742ff4-731e-47ce-99c8-9d863e6a533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755175964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1755175964
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.67207009
Short name T135
Test name
Test status
Simulation time 26523523 ps
CPU time 0.99 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:22 PM PDT 24
Peak memory 219992 kb
Host smart-5931e79e-86d2-4cef-895c-3ff0c64cada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67207009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.67207009
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4152758629
Short name T569
Test name
Test status
Simulation time 40385609 ps
CPU time 1.12 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:10 PM PDT 24
Peak memory 219252 kb
Host smart-4fb89bec-6a8a-423f-ad92-2b43fda806e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152758629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4152758629
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1603530219
Short name T159
Test name
Test status
Simulation time 33548523 ps
CPU time 1.26 seconds
Started Jul 11 05:41:13 PM PDT 24
Finished Jul 11 05:41:19 PM PDT 24
Peak memory 215704 kb
Host smart-5ea0612c-cd0c-4815-a222-37729d646f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603530219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1603530219
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2326504665
Short name T245
Test name
Test status
Simulation time 18170966 ps
CPU time 1.06 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 218664 kb
Host smart-749d082c-fe6b-402b-90d0-9f1676c34d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326504665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2326504665
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.185496118
Short name T570
Test name
Test status
Simulation time 51020110 ps
CPU time 1.33 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 218848 kb
Host smart-29d3144f-5b98-492a-8997-016425889e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185496118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.185496118
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.234872426
Short name T95
Test name
Test status
Simulation time 44433057 ps
CPU time 1.16 seconds
Started Jul 11 05:41:07 PM PDT 24
Finished Jul 11 05:41:11 PM PDT 24
Peak memory 219688 kb
Host smart-1e6f7b90-79c9-4d87-9e81-8c6317704a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234872426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.234872426
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.124548327
Short name T846
Test name
Test status
Simulation time 29606013 ps
CPU time 0.83 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:23 PM PDT 24
Peak memory 218404 kb
Host smart-1a2d7fde-99bc-43dd-bf4e-2652ba84cc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124548327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.124548327
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3284303617
Short name T695
Test name
Test status
Simulation time 121855509 ps
CPU time 2.75 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:18 PM PDT 24
Peak memory 218956 kb
Host smart-aa299d2f-743f-4cbd-b170-668ec5b37b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284303617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3284303617
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1188704239
Short name T947
Test name
Test status
Simulation time 88213850 ps
CPU time 1.18 seconds
Started Jul 11 05:41:40 PM PDT 24
Finished Jul 11 05:41:47 PM PDT 24
Peak memory 219960 kb
Host smart-8722c8ff-bfa8-4af0-a53c-0153940aca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188704239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1188704239
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_genbits.4040977289
Short name T871
Test name
Test status
Simulation time 93555910 ps
CPU time 1.66 seconds
Started Jul 11 05:41:18 PM PDT 24
Finished Jul 11 05:41:28 PM PDT 24
Peak memory 219448 kb
Host smart-2000ecdf-2964-4a35-86b0-27d12e8a0e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040977289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4040977289
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3052203207
Short name T153
Test name
Test status
Simulation time 88302464 ps
CPU time 1.08 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 220680 kb
Host smart-5cb24c46-43e9-4c4d-b717-2f69effb9c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052203207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3052203207
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1596335062
Short name T156
Test name
Test status
Simulation time 68786650 ps
CPU time 1.12 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:10 PM PDT 24
Peak memory 219828 kb
Host smart-6e5ca2ae-763c-4120-bd5e-3c01fc3f45e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596335062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1596335062
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3492856085
Short name T645
Test name
Test status
Simulation time 122796710 ps
CPU time 1.1 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 217816 kb
Host smart-dfad3bc4-2a57-4765-89d4-dfb636719af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492856085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3492856085
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3610623515
Short name T253
Test name
Test status
Simulation time 80505450 ps
CPU time 1.21 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 218640 kb
Host smart-c0d83e13-f302-4458-aa13-b168feab3661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610623515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3610623515
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3686193565
Short name T619
Test name
Test status
Simulation time 21238065 ps
CPU time 1.07 seconds
Started Jul 11 05:41:19 PM PDT 24
Finished Jul 11 05:41:29 PM PDT 24
Peak memory 218564 kb
Host smart-f78cdbcc-4a3c-4af1-8abb-f74e0122918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686193565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3686193565
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.202029241
Short name T976
Test name
Test status
Simulation time 87954261 ps
CPU time 1.11 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:57 PM PDT 24
Peak memory 217620 kb
Host smart-bc4b8c51-e2d2-4c8b-9047-1fb6071b3a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202029241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.202029241
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1149952293
Short name T583
Test name
Test status
Simulation time 26844872 ps
CPU time 1.25 seconds
Started Jul 11 05:41:47 PM PDT 24
Finished Jul 11 05:41:58 PM PDT 24
Peak memory 219620 kb
Host smart-d66e8896-9633-475d-a2b1-c3200c84fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149952293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1149952293
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1560329770
Short name T892
Test name
Test status
Simulation time 20691090 ps
CPU time 1.2 seconds
Started Jul 11 05:41:23 PM PDT 24
Finished Jul 11 05:41:33 PM PDT 24
Peak memory 224256 kb
Host smart-7485c249-1267-4911-9b31-89d8d2708db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560329770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1560329770
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4032957377
Short name T788
Test name
Test status
Simulation time 103886010 ps
CPU time 1.01 seconds
Started Jul 11 05:41:11 PM PDT 24
Finished Jul 11 05:41:14 PM PDT 24
Peak memory 217712 kb
Host smart-463f8549-b7ed-4528-8eb7-600b3239dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032957377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4032957377
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1420390466
Short name T887
Test name
Test status
Simulation time 56963813 ps
CPU time 1.13 seconds
Started Jul 11 05:41:15 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 218968 kb
Host smart-c31fbfda-143c-4e34-85df-45ba857b8f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420390466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1420390466
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2723202624
Short name T520
Test name
Test status
Simulation time 21470637 ps
CPU time 0.95 seconds
Started Jul 11 05:41:12 PM PDT 24
Finished Jul 11 05:41:17 PM PDT 24
Peak memory 218808 kb
Host smart-a7866c9d-017b-4e34-a66c-03fc70c2a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723202624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2723202624
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2322075543
Short name T706
Test name
Test status
Simulation time 35983097 ps
CPU time 1.35 seconds
Started Jul 11 05:41:05 PM PDT 24
Finished Jul 11 05:41:09 PM PDT 24
Peak memory 217636 kb
Host smart-0b2be1dd-1915-4440-a000-e99234be76a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322075543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2322075543
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3276204584
Short name T561
Test name
Test status
Simulation time 25665030 ps
CPU time 1.34 seconds
Started Jul 11 05:41:14 PM PDT 24
Finished Jul 11 05:41:22 PM PDT 24
Peak memory 219156 kb
Host smart-d6766f71-49b2-466d-b707-3a0afe48a80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276204584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3276204584
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2994285991
Short name T728
Test name
Test status
Simulation time 33305669 ps
CPU time 1.02 seconds
Started Jul 11 05:41:06 PM PDT 24
Finished Jul 11 05:41:11 PM PDT 24
Peak memory 224092 kb
Host smart-7e9adc43-4ca0-473c-b822-133436a304cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994285991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2994285991
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2512923256
Short name T991
Test name
Test status
Simulation time 31927460 ps
CPU time 1.27 seconds
Started Jul 11 05:41:16 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 219880 kb
Host smart-b113701f-29dd-4902-99ca-4e15a3eecca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512923256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2512923256
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%