Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.84 98.25 93.97 97.02 93.60 96.37 99.77 91.89


Total test records in report: 1130
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T285 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1700208543 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:58 PM PDT 24 234112251 ps
T1017 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.944070895 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 60701498 ps
T269 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2662709498 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:57 PM PDT 24 14047535 ps
T270 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.614670317 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:03 PM PDT 24 36018808 ps
T287 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1990010685 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:58 PM PDT 24 93543779 ps
T1018 /workspace/coverage/cover_reg_top/0.edn_csr_rw.44126596 Jul 12 05:45:30 PM PDT 24 Jul 12 05:45:32 PM PDT 24 43881120 ps
T1019 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2486332465 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:48 PM PDT 24 120700490 ps
T1020 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2941390515 Jul 12 05:45:48 PM PDT 24 Jul 12 05:45:51 PM PDT 24 145925661 ps
T1021 /workspace/coverage/cover_reg_top/22.edn_intr_test.1200987013 Jul 12 05:46:00 PM PDT 24 Jul 12 05:46:01 PM PDT 24 20174850 ps
T1022 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1198785750 Jul 12 05:45:46 PM PDT 24 Jul 12 05:45:49 PM PDT 24 28077896 ps
T262 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4199054057 Jul 12 05:45:51 PM PDT 24 Jul 12 05:45:55 PM PDT 24 37597973 ps
T1023 /workspace/coverage/cover_reg_top/12.edn_intr_test.1691834641 Jul 12 05:45:47 PM PDT 24 Jul 12 05:45:49 PM PDT 24 13412645 ps
T1024 /workspace/coverage/cover_reg_top/20.edn_intr_test.1459182353 Jul 12 05:45:59 PM PDT 24 Jul 12 05:46:01 PM PDT 24 23363846 ps
T286 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1100730145 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:57 PM PDT 24 254149635 ps
T1025 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3299343906 Jul 12 05:45:40 PM PDT 24 Jul 12 05:45:42 PM PDT 24 53675586 ps
T1026 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4029713852 Jul 12 05:45:57 PM PDT 24 Jul 12 05:45:59 PM PDT 24 127909432 ps
T254 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3919902584 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:47 PM PDT 24 13395918 ps
T1027 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2358046180 Jul 12 05:45:40 PM PDT 24 Jul 12 05:45:42 PM PDT 24 12784438 ps
T1028 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2149854245 Jul 12 05:45:30 PM PDT 24 Jul 12 05:45:33 PM PDT 24 29822723 ps
T1029 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1546505172 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 82683517 ps
T1030 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3191732713 Jul 12 05:45:47 PM PDT 24 Jul 12 05:45:49 PM PDT 24 14541293 ps
T1031 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3580200669 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:47 PM PDT 24 22796387 ps
T1032 /workspace/coverage/cover_reg_top/14.edn_intr_test.2666077678 Jul 12 05:45:55 PM PDT 24 Jul 12 05:45:57 PM PDT 24 17354143 ps
T1033 /workspace/coverage/cover_reg_top/45.edn_intr_test.3478970533 Jul 12 05:46:04 PM PDT 24 Jul 12 05:46:06 PM PDT 24 18313139 ps
T1034 /workspace/coverage/cover_reg_top/17.edn_intr_test.3399188337 Jul 12 05:45:55 PM PDT 24 Jul 12 05:45:57 PM PDT 24 43161951 ps
T1035 /workspace/coverage/cover_reg_top/23.edn_intr_test.3379084340 Jul 12 05:46:00 PM PDT 24 Jul 12 05:46:01 PM PDT 24 26937923 ps
T1036 /workspace/coverage/cover_reg_top/11.edn_intr_test.1684106940 Jul 12 05:45:46 PM PDT 24 Jul 12 05:45:48 PM PDT 24 20074840 ps
T255 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1393530808 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:45 PM PDT 24 68009814 ps
T1037 /workspace/coverage/cover_reg_top/49.edn_intr_test.4169282938 Jul 12 05:46:03 PM PDT 24 Jul 12 05:46:05 PM PDT 24 48112946 ps
T1038 /workspace/coverage/cover_reg_top/27.edn_intr_test.2552659528 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:03 PM PDT 24 14066245 ps
T1039 /workspace/coverage/cover_reg_top/35.edn_intr_test.3957648639 Jul 12 05:46:04 PM PDT 24 Jul 12 05:46:06 PM PDT 24 16010832 ps
T1040 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1527376752 Jul 12 05:45:31 PM PDT 24 Jul 12 05:45:35 PM PDT 24 73981314 ps
T1041 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1955730313 Jul 12 05:45:34 PM PDT 24 Jul 12 05:45:37 PM PDT 24 19750242 ps
T1042 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.159580165 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:45 PM PDT 24 19470642 ps
T1043 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2669230398 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:48 PM PDT 24 65755916 ps
T1044 /workspace/coverage/cover_reg_top/13.edn_tl_errors.59243279 Jul 12 05:45:47 PM PDT 24 Jul 12 05:45:51 PM PDT 24 235574587 ps
T1045 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1091649100 Jul 12 05:45:57 PM PDT 24 Jul 12 05:46:00 PM PDT 24 58949395 ps
T1046 /workspace/coverage/cover_reg_top/30.edn_intr_test.3549842849 Jul 12 05:46:05 PM PDT 24 Jul 12 05:46:06 PM PDT 24 43721534 ps
T1047 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1220491979 Jul 12 05:45:39 PM PDT 24 Jul 12 05:45:44 PM PDT 24 645322129 ps
T1048 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3988746646 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:57 PM PDT 24 34303940 ps
T1049 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4223645286 Jul 12 05:45:38 PM PDT 24 Jul 12 05:45:41 PM PDT 24 234931730 ps
T288 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.641735049 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:59 PM PDT 24 89118246 ps
T1050 /workspace/coverage/cover_reg_top/5.edn_intr_test.922925909 Jul 12 05:45:40 PM PDT 24 Jul 12 05:45:42 PM PDT 24 33509401 ps
T1051 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.209641561 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:44 PM PDT 24 30240523 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1325491140 Jul 12 05:45:38 PM PDT 24 Jul 12 05:45:40 PM PDT 24 45429045 ps
T1053 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2063196156 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:43 PM PDT 24 54038742 ps
T1054 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3831485963 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:47 PM PDT 24 75038993 ps
T1055 /workspace/coverage/cover_reg_top/39.edn_intr_test.1357045634 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:03 PM PDT 24 110151978 ps
T1056 /workspace/coverage/cover_reg_top/0.edn_intr_test.1763183347 Jul 12 05:45:32 PM PDT 24 Jul 12 05:45:35 PM PDT 24 32261685 ps
T256 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2152803971 Jul 12 05:45:36 PM PDT 24 Jul 12 05:45:38 PM PDT 24 85695934 ps
T1057 /workspace/coverage/cover_reg_top/13.edn_intr_test.2516318626 Jul 12 05:45:48 PM PDT 24 Jul 12 05:45:50 PM PDT 24 25726871 ps
T1058 /workspace/coverage/cover_reg_top/19.edn_intr_test.2827171147 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:04 PM PDT 24 33116595 ps
T1059 /workspace/coverage/cover_reg_top/41.edn_intr_test.364124403 Jul 12 05:46:05 PM PDT 24 Jul 12 05:46:07 PM PDT 24 44681045 ps
T1060 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1365119161 Jul 12 05:45:39 PM PDT 24 Jul 12 05:45:44 PM PDT 24 111879447 ps
T1061 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.91483674 Jul 12 05:45:33 PM PDT 24 Jul 12 05:45:36 PM PDT 24 62484065 ps
T289 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2855865044 Jul 12 05:45:39 PM PDT 24 Jul 12 05:45:42 PM PDT 24 240461943 ps
T1062 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.498957121 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:47 PM PDT 24 32006395 ps
T1063 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3826509975 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:46 PM PDT 24 194882355 ps
T1064 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2762078770 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:58 PM PDT 24 30990274 ps
T1065 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.949227558 Jul 12 05:45:39 PM PDT 24 Jul 12 05:45:43 PM PDT 24 94546092 ps
T1066 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.722914725 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 53573925 ps
T1067 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2027270380 Jul 12 05:45:58 PM PDT 24 Jul 12 05:46:00 PM PDT 24 15671580 ps
T1068 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.872419245 Jul 12 05:45:52 PM PDT 24 Jul 12 05:45:54 PM PDT 24 27905315 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.291603300 Jul 12 05:46:04 PM PDT 24 Jul 12 05:46:06 PM PDT 24 59927384 ps
T1070 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2588784502 Jul 12 05:45:53 PM PDT 24 Jul 12 05:46:00 PM PDT 24 2868890811 ps
T1071 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3026747922 Jul 12 05:45:44 PM PDT 24 Jul 12 05:45:47 PM PDT 24 85608254 ps
T1072 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2938030510 Jul 12 05:47:37 PM PDT 24 Jul 12 05:47:41 PM PDT 24 110831524 ps
T257 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2752580830 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:47 PM PDT 24 45454531 ps
T1073 /workspace/coverage/cover_reg_top/16.edn_tl_errors.960840918 Jul 12 05:45:55 PM PDT 24 Jul 12 05:45:59 PM PDT 24 140160465 ps
T1074 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3367954869 Jul 12 05:45:55 PM PDT 24 Jul 12 05:45:57 PM PDT 24 51616635 ps
T258 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1672861749 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:45 PM PDT 24 19494115 ps
T1075 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3666384976 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 52145420 ps
T1076 /workspace/coverage/cover_reg_top/26.edn_intr_test.3531155960 Jul 12 05:46:00 PM PDT 24 Jul 12 05:46:01 PM PDT 24 13595334 ps
T1077 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.375212941 Jul 12 05:46:34 PM PDT 24 Jul 12 05:46:36 PM PDT 24 61092713 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1245492223 Jul 12 05:46:04 PM PDT 24 Jul 12 05:46:06 PM PDT 24 28180929 ps
T1079 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2799858641 Jul 12 05:45:50 PM PDT 24 Jul 12 05:45:53 PM PDT 24 95009109 ps
T1080 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3166121264 Jul 12 05:45:51 PM PDT 24 Jul 12 05:45:54 PM PDT 24 16799301 ps
T1081 /workspace/coverage/cover_reg_top/48.edn_intr_test.4094136337 Jul 12 05:46:00 PM PDT 24 Jul 12 05:46:01 PM PDT 24 62459358 ps
T1082 /workspace/coverage/cover_reg_top/40.edn_intr_test.3924003420 Jul 12 05:46:03 PM PDT 24 Jul 12 05:46:05 PM PDT 24 14589113 ps
T259 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2668118935 Jul 12 05:45:46 PM PDT 24 Jul 12 05:45:48 PM PDT 24 60143733 ps
T1083 /workspace/coverage/cover_reg_top/33.edn_intr_test.3444195080 Jul 12 05:46:19 PM PDT 24 Jul 12 05:46:21 PM PDT 24 15303386 ps
T1084 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.921432766 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:59 PM PDT 24 154625557 ps
T1085 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3159286987 Jul 12 05:45:30 PM PDT 24 Jul 12 05:45:34 PM PDT 24 84910712 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1358020124 Jul 12 05:45:52 PM PDT 24 Jul 12 05:45:56 PM PDT 24 146440800 ps
T1087 /workspace/coverage/cover_reg_top/29.edn_intr_test.694754002 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:04 PM PDT 24 61750941 ps
T1088 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2069051113 Jul 12 05:45:30 PM PDT 24 Jul 12 05:45:33 PM PDT 24 93427238 ps
T1089 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1776432590 Jul 12 05:45:31 PM PDT 24 Jul 12 05:45:35 PM PDT 24 98156861 ps
T1090 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1496237854 Jul 12 05:45:44 PM PDT 24 Jul 12 05:45:46 PM PDT 24 25398226 ps
T1091 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2171251275 Jul 12 05:45:37 PM PDT 24 Jul 12 05:45:39 PM PDT 24 35900298 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3100853410 Jul 12 05:45:44 PM PDT 24 Jul 12 05:45:47 PM PDT 24 761104802 ps
T1093 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3403674384 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:48 PM PDT 24 96785652 ps
T1094 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.950733900 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:43 PM PDT 24 17868387 ps
T1095 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.501047718 Jul 12 05:45:37 PM PDT 24 Jul 12 05:45:41 PM PDT 24 261508643 ps
T1096 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1224662229 Jul 12 05:45:40 PM PDT 24 Jul 12 05:45:44 PM PDT 24 92900037 ps
T1097 /workspace/coverage/cover_reg_top/16.edn_intr_test.4221798111 Jul 12 05:45:55 PM PDT 24 Jul 12 05:45:58 PM PDT 24 24341188 ps
T1098 /workspace/coverage/cover_reg_top/46.edn_intr_test.1021552299 Jul 12 05:46:02 PM PDT 24 Jul 12 05:46:04 PM PDT 24 23530306 ps
T1099 /workspace/coverage/cover_reg_top/7.edn_tl_errors.336785725 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:46 PM PDT 24 86394290 ps
T1100 /workspace/coverage/cover_reg_top/21.edn_intr_test.227706529 Jul 12 05:46:51 PM PDT 24 Jul 12 05:46:53 PM PDT 24 23048842 ps
T1101 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3176875182 Jul 12 05:45:31 PM PDT 24 Jul 12 05:45:34 PM PDT 24 192142591 ps
T1102 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1460561886 Jul 12 05:45:51 PM PDT 24 Jul 12 05:45:54 PM PDT 24 571673738 ps
T1103 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3368023552 Jul 12 05:45:38 PM PDT 24 Jul 12 05:45:43 PM PDT 24 156358081 ps
T1104 /workspace/coverage/cover_reg_top/3.edn_intr_test.3885398478 Jul 12 05:45:41 PM PDT 24 Jul 12 05:45:43 PM PDT 24 26824890 ps
T1105 /workspace/coverage/cover_reg_top/6.edn_intr_test.782835328 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:44 PM PDT 24 43533847 ps
T1106 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.746816587 Jul 12 05:45:52 PM PDT 24 Jul 12 05:45:54 PM PDT 24 22151074 ps
T1107 /workspace/coverage/cover_reg_top/32.edn_intr_test.771574078 Jul 12 05:46:05 PM PDT 24 Jul 12 05:46:06 PM PDT 24 48462358 ps
T1108 /workspace/coverage/cover_reg_top/25.edn_intr_test.3018787730 Jul 12 05:46:05 PM PDT 24 Jul 12 05:46:07 PM PDT 24 42015221 ps
T1109 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3772848731 Jul 12 05:45:31 PM PDT 24 Jul 12 05:45:38 PM PDT 24 521072159 ps
T1110 /workspace/coverage/cover_reg_top/2.edn_intr_test.2408118458 Jul 12 05:45:34 PM PDT 24 Jul 12 05:45:36 PM PDT 24 37155663 ps
T1111 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2326524142 Jul 12 05:45:44 PM PDT 24 Jul 12 05:45:47 PM PDT 24 51359633 ps
T260 /workspace/coverage/cover_reg_top/4.edn_csr_rw.672288121 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:45 PM PDT 24 15347599 ps
T1112 /workspace/coverage/cover_reg_top/7.edn_intr_test.4105941393 Jul 12 05:45:57 PM PDT 24 Jul 12 05:45:58 PM PDT 24 10706092 ps
T1113 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3747977766 Jul 12 05:45:33 PM PDT 24 Jul 12 05:45:39 PM PDT 24 1337015842 ps
T1114 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3356279162 Jul 12 05:45:48 PM PDT 24 Jul 12 05:45:50 PM PDT 24 145000777 ps
T1115 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1552009148 Jul 12 05:45:38 PM PDT 24 Jul 12 05:45:40 PM PDT 24 63511734 ps
T1116 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.814041458 Jul 12 05:45:58 PM PDT 24 Jul 12 05:46:01 PM PDT 24 93080824 ps
T1117 /workspace/coverage/cover_reg_top/37.edn_intr_test.3219799224 Jul 12 05:46:03 PM PDT 24 Jul 12 05:46:05 PM PDT 24 21848435 ps
T1118 /workspace/coverage/cover_reg_top/18.edn_intr_test.2293748073 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 47777531 ps
T1119 /workspace/coverage/cover_reg_top/36.edn_intr_test.1805258213 Jul 12 05:46:01 PM PDT 24 Jul 12 05:46:03 PM PDT 24 27094104 ps
T1120 /workspace/coverage/cover_reg_top/38.edn_intr_test.1986063509 Jul 12 05:46:03 PM PDT 24 Jul 12 05:46:05 PM PDT 24 16669283 ps
T1121 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3014260637 Jul 12 05:45:42 PM PDT 24 Jul 12 05:45:44 PM PDT 24 27706839 ps
T1122 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1238162707 Jul 12 05:45:54 PM PDT 24 Jul 12 05:45:59 PM PDT 24 335474803 ps
T1123 /workspace/coverage/cover_reg_top/47.edn_intr_test.141190375 Jul 12 05:46:00 PM PDT 24 Jul 12 05:46:02 PM PDT 24 44407317 ps
T1124 /workspace/coverage/cover_reg_top/4.edn_intr_test.3384579266 Jul 12 05:45:43 PM PDT 24 Jul 12 05:45:45 PM PDT 24 12182260 ps
T1125 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1560065052 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:48 PM PDT 24 62826929 ps
T1126 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1647316126 Jul 12 05:45:32 PM PDT 24 Jul 12 05:45:34 PM PDT 24 30133263 ps
T1127 /workspace/coverage/cover_reg_top/34.edn_intr_test.2281202590 Jul 12 05:46:01 PM PDT 24 Jul 12 05:46:03 PM PDT 24 37813921 ps
T1128 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2449525852 Jul 12 05:45:53 PM PDT 24 Jul 12 05:45:55 PM PDT 24 80053916 ps
T261 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2171938112 Jul 12 05:45:29 PM PDT 24 Jul 12 05:45:32 PM PDT 24 37242589 ps
T1129 /workspace/coverage/cover_reg_top/13.edn_csr_rw.866377909 Jul 12 05:45:56 PM PDT 24 Jul 12 05:45:58 PM PDT 24 40161008 ps
T1130 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1519733434 Jul 12 05:45:45 PM PDT 24 Jul 12 05:45:49 PM PDT 24 140041217 ps

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3927080392
Short name T6
Test name
Test status
Simulation time 95103095941 ps
CPU time 1052.33 seconds
Started Jul 12 06:37:37 PM PDT 24
Finished Jul 12 06:55:11 PM PDT 24
Peak memory 222732 kb
Host smart-426621c4-562d-462e-bd7c-effe9663b574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927080392 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3927080392
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_genbits.3468065790
Short name T42
Test name
Test status
Simulation time 87989248 ps
CPU time 1.33 seconds
Started Jul 12 06:38:00 PM PDT 24
Finished Jul 12 06:38:02 PM PDT 24
Peak memory 219208 kb
Host smart-244300fe-b798-4f23-b3a7-ce461e119322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468065790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3468065790
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_genbits.3499556302
Short name T10
Test name
Test status
Simulation time 31867568 ps
CPU time 1.38 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:29 PM PDT 24
Peak memory 218824 kb
Host smart-cf9731de-51e8-40ce-9317-7749b81a1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499556302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3499556302
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2393980751
Short name T5
Test name
Test status
Simulation time 98749581 ps
CPU time 1 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 220160 kb
Host smart-c39b7a27-353d-4e7e-b91d-ce5e442b8034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393980751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2393980751
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.991279237
Short name T19
Test name
Test status
Simulation time 495618464 ps
CPU time 7.78 seconds
Started Jul 12 06:36:49 PM PDT 24
Finished Jul 12 06:36:58 PM PDT 24
Peak memory 237648 kb
Host smart-b3db5079-57c3-4ddb-8ce7-310566395ec3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991279237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.991279237
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/125.edn_alert.2224998463
Short name T17
Test name
Test status
Simulation time 65023555 ps
CPU time 1.17 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 221252 kb
Host smart-8a210814-083c-4411-a63e-3b79e182d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224998463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2224998463
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/45.edn_disable.2868707046
Short name T25
Test name
Test status
Simulation time 13533040 ps
CPU time 0.96 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:03 PM PDT 24
Peak memory 216688 kb
Host smart-9241a358-b924-450d-aa47-bc728d17deeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868707046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2868707046
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/52.edn_alert.3589074667
Short name T14
Test name
Test status
Simulation time 47865348 ps
CPU time 1.27 seconds
Started Jul 12 06:38:09 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 215972 kb
Host smart-d2ed6b64-c372-4af8-92a7-f01ebf5dd7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589074667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3589074667
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3580529714
Short name T76
Test name
Test status
Simulation time 72387695 ps
CPU time 0.98 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 217212 kb
Host smart-854a5614-3fcd-4b7a-913d-36b548548a68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580529714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3580529714
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3600509871
Short name T52
Test name
Test status
Simulation time 19803164 ps
CPU time 1.13 seconds
Started Jul 12 06:36:48 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 229768 kb
Host smart-a2c83799-1bdd-4090-8224-6bd7039505ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600509871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3600509871
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/2.edn_regwen.229253933
Short name T29
Test name
Test status
Simulation time 16083157 ps
CPU time 0.97 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 207376 kb
Host smart-619799ed-b7bf-497b-b5a7-1ff3397c29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229253933 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.229253933
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/168.edn_alert.3083848594
Short name T58
Test name
Test status
Simulation time 28703961 ps
CPU time 1.23 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 218904 kb
Host smart-bb8d6817-6f91-4078-8469-9e92a15f8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083848594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3083848594
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1700208543
Short name T285
Test name
Test status
Simulation time 234112251 ps
CPU time 2.22 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 206928 kb
Host smart-e494c34a-50c5-43e7-9469-7e553547a2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700208543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1700208543
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/22.edn_disable.152977838
Short name T87
Test name
Test status
Simulation time 11777856 ps
CPU time 0.9 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 216532 kb
Host smart-32130068-72ba-4a83-8c1d-543c9543ed8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152977838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.152977838
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/40.edn_intr.581219911
Short name T31
Test name
Test status
Simulation time 21045752 ps
CPU time 1.12 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 216228 kb
Host smart-d4aac2e0-362c-452b-9e0f-392d95300a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581219911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.581219911
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3923097032
Short name T149
Test name
Test status
Simulation time 108290673 ps
CPU time 1.24 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 217064 kb
Host smart-16e8cd9a-65a7-444d-95dc-9e2f5ceca703
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923097032 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3923097032
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2837794212
Short name T88
Test name
Test status
Simulation time 429204104 ps
CPU time 1.37 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 217304 kb
Host smart-e11de0dd-7160-4acd-be6d-09cc2870d509
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837794212 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2837794212
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/196.edn_alert.2863456478
Short name T94
Test name
Test status
Simulation time 80762049 ps
CPU time 1.2 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 218744 kb
Host smart-005d839e-fe1c-4471-9695-7ef5a236a823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863456478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2863456478
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.2038266615
Short name T219
Test name
Test status
Simulation time 40480873 ps
CPU time 1.1 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219144 kb
Host smart-9d086dcf-e98f-4490-b8e5-b16ef617d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038266615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2038266615
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/49.edn_disable.2614412129
Short name T202
Test name
Test status
Simulation time 44186283 ps
CPU time 0.88 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:10 PM PDT 24
Peak memory 216544 kb
Host smart-d868cebe-aec9-4741-acd3-c1ca0ba1dc63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614412129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2614412129
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.291251111
Short name T216
Test name
Test status
Simulation time 44827482 ps
CPU time 0.86 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 216644 kb
Host smart-12338d7a-b3b0-45c8-805e-460aa0ccb921
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291251111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.291251111
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.261038849
Short name T171
Test name
Test status
Simulation time 12714666 ps
CPU time 0.87 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 216728 kb
Host smart-fa7ab457-0f4a-4c0a-b552-b6817e620b4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261038849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.261038849
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/149.edn_alert.2942520314
Short name T109
Test name
Test status
Simulation time 30232367 ps
CPU time 1.28 seconds
Started Jul 12 06:38:53 PM PDT 24
Finished Jul 12 06:38:55 PM PDT 24
Peak memory 219868 kb
Host smart-0ff079cc-f608-4548-a0d2-9be25706d1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942520314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2942520314
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1289578245
Short name T253
Test name
Test status
Simulation time 17848178 ps
CPU time 0.93 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206932 kb
Host smart-fd703060-de99-4a16-9d1d-71d206136607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289578245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1289578245
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/90.edn_genbits.4249584836
Short name T12
Test name
Test status
Simulation time 90656104 ps
CPU time 1.37 seconds
Started Jul 12 06:39:40 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 220212 kb
Host smart-f2d866e4-923c-4687-9b39-0b2e80ef621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249584836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4249584836
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1435097167
Short name T71
Test name
Test status
Simulation time 47243899 ps
CPU time 1.21 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 221480 kb
Host smart-36bb7eab-7aa3-449e-89aa-dafb73bf69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435097167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1435097167
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.1549899436
Short name T172
Test name
Test status
Simulation time 46029489 ps
CPU time 1.24 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 215968 kb
Host smart-61087c1e-ca1f-4418-8586-37b731785444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549899436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1549899436
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert.935397789
Short name T250
Test name
Test status
Simulation time 37823476 ps
CPU time 1.31 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 219700 kb
Host smart-e2f0ca83-cfee-4315-8283-a44dd3aad04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935397789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.935397789
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/223.edn_genbits.139894165
Short name T299
Test name
Test status
Simulation time 239425067 ps
CPU time 3.23 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217804 kb
Host smart-a911bb6b-ff84-4647-b5f1-c1a7f9f87e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139894165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.139894165
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.973538749
Short name T18
Test name
Test status
Simulation time 3072702702 ps
CPU time 5.35 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:52 PM PDT 24
Peak memory 237156 kb
Host smart-24316316-ad9c-4b42-bc88-1aaedba2c180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973538749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.973538749
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/108.edn_alert.1109655468
Short name T328
Test name
Test status
Simulation time 26948025 ps
CPU time 1.3 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 219032 kb
Host smart-59f75d5b-6133-4ee5-adb7-ca95606371da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109655468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1109655468
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.2746576993
Short name T650
Test name
Test status
Simulation time 73018128 ps
CPU time 1.2 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 220136 kb
Host smart-b2039d3c-f984-4131-ada0-2bfa5a3e05bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746576993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2746576993
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.3197936518
Short name T575
Test name
Test status
Simulation time 41395096 ps
CPU time 1.21 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 219380 kb
Host smart-bcc78a45-e50a-44a1-a80d-fea50051883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197936518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3197936518
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/166.edn_alert.2793136527
Short name T505
Test name
Test status
Simulation time 75393008 ps
CPU time 1.16 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 218952 kb
Host smart-514bccd8-388b-4332-ad72-9d48d363616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793136527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2793136527
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/14.edn_intr.1977896593
Short name T33
Test name
Test status
Simulation time 20630521 ps
CPU time 1.09 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 216156 kb
Host smart-82b1d928-2d3c-43b4-86fc-bc17d67db414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977896593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1977896593
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.2690906920
Short name T161
Test name
Test status
Simulation time 12905836 ps
CPU time 0.93 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 216112 kb
Host smart-92e43d73-bc05-4caa-96c8-27a5e6267378
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690906920 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2690906920
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.1664451387
Short name T207
Test name
Test status
Simulation time 10952627 ps
CPU time 0.89 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 216592 kb
Host smart-607a453e-e38f-422b-89e5-1a436b5fe1e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664451387 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1664451387
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/78.edn_alert.4136583389
Short name T97
Test name
Test status
Simulation time 30794994 ps
CPU time 1.18 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 218780 kb
Host smart-fbd1ea0a-bb89-44d2-bc5e-ab806c2c67ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136583389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4136583389
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/7.edn_stress_all.269819219
Short name T239
Test name
Test status
Simulation time 324966988 ps
CPU time 6.33 seconds
Started Jul 12 06:37:01 PM PDT 24
Finished Jul 12 06:37:10 PM PDT 24
Peak memory 218904 kb
Host smart-58efa09e-191e-4535-b5c1-ce38abc0dce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269819219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.269819219
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/101.edn_alert.4020508360
Short name T246
Test name
Test status
Simulation time 120618307 ps
CPU time 1.19 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:42 PM PDT 24
Peak memory 218668 kb
Host smart-fa7f5e95-e0e6-4fc4-977b-8c173ade5389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020508360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.4020508360
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/12.edn_err.3201923395
Short name T186
Test name
Test status
Simulation time 35311678 ps
CPU time 1.01 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:11 PM PDT 24
Peak memory 224032 kb
Host smart-9eafe7b4-fecd-4716-a8dc-2386569aa3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201923395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3201923395
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/15.edn_disable.3073070558
Short name T213
Test name
Test status
Simulation time 37523153 ps
CPU time 0.86 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 216528 kb
Host smart-baf432fc-8147-4231-975d-a27b4bbd739c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073070558 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3073070558
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/185.edn_alert.3979277542
Short name T135
Test name
Test status
Simulation time 32802542 ps
CPU time 1.17 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219808 kb
Host smart-f51f8c25-f515-48eb-8ab4-618de1114ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979277542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3979277542
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/21.edn_disable.2957960755
Short name T193
Test name
Test status
Simulation time 16054135 ps
CPU time 0.84 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 216612 kb
Host smart-a63a0404-dcd3-4195-992a-2d4303640a8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957960755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2957960755
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.582021814
Short name T129
Test name
Test status
Simulation time 246623633 ps
CPU time 1.09 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:25 PM PDT 24
Peak memory 217068 kb
Host smart-cea9143b-5a55-42e6-aaca-28571e9f0b30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582021814 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.582021814
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.7875313
Short name T156
Test name
Test status
Simulation time 87724255 ps
CPU time 1.16 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 217216 kb
Host smart-abc988a5-62b3-4206-baf8-3bb4ac04d50f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7875313 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disa
ble_auto_req_mode.7875313
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.2482482175
Short name T177
Test name
Test status
Simulation time 37861098 ps
CPU time 0.95 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 216528 kb
Host smart-1381d521-8531-4fee-a368-8d16a4b241d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482482175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2482482175
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/58.edn_err.4126218045
Short name T198
Test name
Test status
Simulation time 20230999 ps
CPU time 1.07 seconds
Started Jul 12 06:38:18 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 224240 kb
Host smart-f10433c6-474c-48bc-a749-b6d0743a3f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126218045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4126218045
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/8.edn_disable.892266858
Short name T203
Test name
Test status
Simulation time 40693247 ps
CPU time 0.9 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 216352 kb
Host smart-0a0f0ab1-23ad-4bef-b181-61e34521354d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892266858 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.892266858
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/12.edn_alert_test.568666727
Short name T370
Test name
Test status
Simulation time 18161346 ps
CPU time 1.01 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 207044 kb
Host smart-77c4b749-1a5c-4e7a-b129-73242a40d72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568666727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.568666727
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/262.edn_genbits.4182313580
Short name T293
Test name
Test status
Simulation time 76190337 ps
CPU time 1.05 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:23 PM PDT 24
Peak memory 217836 kb
Host smart-2da4db3c-77bc-458b-86f9-4c8952f80180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182313580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4182313580
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2830527303
Short name T3
Test name
Test status
Simulation time 113862541 ps
CPU time 1.31 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 217752 kb
Host smart-441d41a6-3100-458d-9282-8eb8746b533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830527303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2830527303
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2900792412
Short name T108
Test name
Test status
Simulation time 63877482733 ps
CPU time 382.33 seconds
Started Jul 12 06:37:25 PM PDT 24
Finished Jul 12 06:43:49 PM PDT 24
Peak memory 224040 kb
Host smart-87d5d5f4-c19c-4bda-9242-3b1964781dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900792412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2900792412
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_intr.2099246763
Short name T38
Test name
Test status
Simulation time 23558068 ps
CPU time 1.01 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 216132 kb
Host smart-375ac6ec-9099-454b-ac26-990eba1f8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099246763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2099246763
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2171938112
Short name T261
Test name
Test status
Simulation time 37242589 ps
CPU time 1.94 seconds
Started Jul 12 05:45:29 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 206928 kb
Host smart-5fa94de6-ab24-4989-82a5-d9b6a67a1956
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171938112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2171938112
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1460561886
Short name T1102
Test name
Test status
Simulation time 571673738 ps
CPU time 2.1 seconds
Started Jul 12 05:45:51 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 206960 kb
Host smart-773097ff-eba3-4431-8356-3042b5d23adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460561886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1460561886
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_smoke.1911637232
Short name T1
Test name
Test status
Simulation time 37755079 ps
CPU time 0.91 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 215636 kb
Host smart-d647d29f-50cf-4802-90f8-e41b5e443b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911637232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1911637232
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/109.edn_genbits.4161524987
Short name T305
Test name
Test status
Simulation time 102094507 ps
CPU time 2.44 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 220312 kb
Host smart-8eb63d0d-9a7e-451a-b657-8adb3c60a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161524987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4161524987
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3446731417
Short name T290
Test name
Test status
Simulation time 50901851 ps
CPU time 1.2 seconds
Started Jul 12 06:38:45 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 215944 kb
Host smart-b0e88c7c-c90d-400c-8f7e-0a76e02e2f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446731417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3446731417
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2497646684
Short name T44
Test name
Test status
Simulation time 44496377 ps
CPU time 1.56 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 218856 kb
Host smart-7c4b2ab1-774a-4b39-b231-96b949a2f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497646684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2497646684
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3559201261
Short name T815
Test name
Test status
Simulation time 116028922 ps
CPU time 1.27 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 215448 kb
Host smart-9db7797f-5451-41ef-af48-62d569b03f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559201261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3559201261
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2661648970
Short name T310
Test name
Test status
Simulation time 36641986 ps
CPU time 1.73 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 219120 kb
Host smart-5b0bbfd2-cbf7-461b-a444-5ee54851b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661648970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2661648970
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2931493929
Short name T308
Test name
Test status
Simulation time 31443306 ps
CPU time 1.54 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 218944 kb
Host smart-6783cf9d-12b2-4838-972f-6cf5d07bd232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931493929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2931493929
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1359248593
Short name T297
Test name
Test status
Simulation time 39431157 ps
CPU time 1.58 seconds
Started Jul 12 06:38:51 PM PDT 24
Finished Jul 12 06:38:53 PM PDT 24
Peak memory 218824 kb
Host smart-c0c8d5cf-6b9d-4810-b1d5-9993f8935107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359248593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1359248593
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.458494944
Short name T301
Test name
Test status
Simulation time 147163011 ps
CPU time 1.19 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 219208 kb
Host smart-c7946ae1-f366-4adf-a1bd-5eafc76c1a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458494944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.458494944
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_genbits.3439588114
Short name T309
Test name
Test status
Simulation time 139242358 ps
CPU time 3 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:30 PM PDT 24
Peak memory 220296 kb
Host smart-fdad995f-14bf-4676-b4f7-6a2e6207ff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439588114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3439588114
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1006656851
Short name T39
Test name
Test status
Simulation time 84037540 ps
CPU time 0.84 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 215800 kb
Host smart-9063a472-e7e9-47b9-8cde-693c843394a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006656851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1006656851
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/110.edn_alert.3026765294
Short name T107
Test name
Test status
Simulation time 136989348 ps
CPU time 1.1 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 219184 kb
Host smart-8a9422ae-6410-4166-bf60-b45cd2df833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026765294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3026765294
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/140.edn_alert.2168572250
Short name T500
Test name
Test status
Simulation time 27887385 ps
CPU time 1.25 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 218860 kb
Host smart-e061765d-00df-4421-9be5-f71d8fb4f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168572250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2168572250
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.750842338
Short name T365
Test name
Test status
Simulation time 51625597 ps
CPU time 1.32 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 217612 kb
Host smart-1b2e0b22-4ec3-4354-809c-45481a9fc066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750842338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.750842338
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.377111835
Short name T480
Test name
Test status
Simulation time 167626826 ps
CPU time 1.62 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 218904 kb
Host smart-c0122f3a-fc0a-47ec-a31a-aa2f047930e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377111835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.377111835
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2985867755
Short name T999
Test name
Test status
Simulation time 28362766 ps
CPU time 1.2 seconds
Started Jul 12 05:45:34 PM PDT 24
Finished Jul 12 05:45:37 PM PDT 24
Peak memory 206996 kb
Host smart-a52f8f43-45c6-4a1d-b078-8cc757ce1d0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985867755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2985867755
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2182173706
Short name T1011
Test name
Test status
Simulation time 249487934 ps
CPU time 3.16 seconds
Started Jul 12 05:45:34 PM PDT 24
Finished Jul 12 05:45:39 PM PDT 24
Peak memory 207032 kb
Host smart-3814d97b-b7e1-4892-8313-bf8ae847089d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182173706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2182173706
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4167154415
Short name T994
Test name
Test status
Simulation time 46852713 ps
CPU time 0.9 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 206908 kb
Host smart-bb4dc65e-bef7-4248-957e-780ed6d506b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167154415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4167154415
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.91483674
Short name T1061
Test name
Test status
Simulation time 62484065 ps
CPU time 1.29 seconds
Started Jul 12 05:45:33 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 215372 kb
Host smart-73473789-cd23-42fb-9403-aafbe3a7346a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91483674 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.91483674
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.44126596
Short name T1018
Test name
Test status
Simulation time 43881120 ps
CPU time 0.86 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:32 PM PDT 24
Peak memory 206896 kb
Host smart-baf9c902-628e-4b57-9d29-6f73827ac826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44126596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.44126596
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1763183347
Short name T1056
Test name
Test status
Simulation time 32261685 ps
CPU time 0.83 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 206648 kb
Host smart-64ecda82-d9ac-4108-918e-14189dbab940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763183347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1763183347
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2149854245
Short name T1028
Test name
Test status
Simulation time 29822723 ps
CPU time 1.11 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 206972 kb
Host smart-3d340d28-4da8-4785-937b-50f1e4b37bbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149854245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2149854245
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3772848731
Short name T1109
Test name
Test status
Simulation time 521072159 ps
CPU time 4.7 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:38 PM PDT 24
Peak memory 215344 kb
Host smart-f82ba976-f3b2-4b14-9fb7-fe21b87ab578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772848731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3772848731
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1776432590
Short name T1089
Test name
Test status
Simulation time 98156861 ps
CPU time 1.67 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 206932 kb
Host smart-5951090b-f5db-450d-8a72-66bbc81f1041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776432590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1776432590
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2069051113
Short name T1088
Test name
Test status
Simulation time 93427238 ps
CPU time 1.16 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:33 PM PDT 24
Peak memory 206940 kb
Host smart-742a5824-b09a-41ff-9e4d-5ad30ffa41a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069051113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2069051113
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1647316126
Short name T1126
Test name
Test status
Simulation time 30133263 ps
CPU time 0.86 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 206912 kb
Host smart-9f3078e3-fc9c-44d4-b1ea-ca7d8b576b1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647316126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1647316126
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1615534159
Short name T1002
Test name
Test status
Simulation time 205739363 ps
CPU time 1.47 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 218748 kb
Host smart-cdd0a0af-b32b-4cc1-a4f5-81567e7c04fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615534159 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1615534159
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4064321861
Short name T1015
Test name
Test status
Simulation time 55884867 ps
CPU time 0.9 seconds
Started Jul 12 05:45:32 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 206888 kb
Host smart-69e74cad-4456-4167-8930-3883380ffd56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064321861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4064321861
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.898711610
Short name T1012
Test name
Test status
Simulation time 20138370 ps
CPU time 0.86 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 207048 kb
Host smart-647b8f24-d0a7-435e-b0f4-47cf8dd9c526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898711610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.898711610
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3578129171
Short name T265
Test name
Test status
Simulation time 34498145 ps
CPU time 1.07 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 206780 kb
Host smart-9d430a5e-5e13-4ba1-b38d-ec293c9d8354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578129171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3578129171
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3747977766
Short name T1113
Test name
Test status
Simulation time 1337015842 ps
CPU time 4.6 seconds
Started Jul 12 05:45:33 PM PDT 24
Finished Jul 12 05:45:39 PM PDT 24
Peak memory 215164 kb
Host smart-1c9bc46d-74da-42fa-b4fd-f7f38053de9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747977766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3747977766
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3176875182
Short name T1101
Test name
Test status
Simulation time 192142591 ps
CPU time 1.35 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 207160 kb
Host smart-54e357f5-c4ac-4a4e-bd7d-febf669275ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176875182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3176875182
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2799858641
Short name T1079
Test name
Test status
Simulation time 95009109 ps
CPU time 1.53 seconds
Started Jul 12 05:45:50 PM PDT 24
Finished Jul 12 05:45:53 PM PDT 24
Peak memory 214636 kb
Host smart-a22dc366-6e74-4d5d-87f3-f23cea19c846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799858641 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2799858641
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.977766887
Short name T1013
Test name
Test status
Simulation time 49585292 ps
CPU time 0.89 seconds
Started Jul 12 05:45:50 PM PDT 24
Finished Jul 12 05:45:52 PM PDT 24
Peak memory 206252 kb
Host smart-f4bf0d23-0ebe-4c39-8c34-a0c35b10170d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977766887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.977766887
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1560065052
Short name T1125
Test name
Test status
Simulation time 62826929 ps
CPU time 1.42 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 206916 kb
Host smart-b9768df2-f69a-4778-b2db-29523df489fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560065052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1560065052
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1198785750
Short name T1022
Test name
Test status
Simulation time 28077896 ps
CPU time 1.88 seconds
Started Jul 12 05:45:46 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 215104 kb
Host smart-a3fc399b-26b3-430a-8056-a750610beffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198785750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1198785750
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3356279162
Short name T1114
Test name
Test status
Simulation time 145000777 ps
CPU time 1.34 seconds
Started Jul 12 05:45:48 PM PDT 24
Finished Jul 12 05:45:50 PM PDT 24
Peak memory 218204 kb
Host smart-449f9e6e-ec80-4125-a6aa-eeec2b1fc31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356279162 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3356279162
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3919902584
Short name T254
Test name
Test status
Simulation time 13395918 ps
CPU time 0.89 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206896 kb
Host smart-e38aac95-1978-4e6b-b974-d784c891c383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919902584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3919902584
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1684106940
Short name T1036
Test name
Test status
Simulation time 20074840 ps
CPU time 0.82 seconds
Started Jul 12 05:45:46 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 206648 kb
Host smart-6a5e258e-5d6d-48d0-963c-64e394f60539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684106940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1684106940
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3166121264
Short name T1080
Test name
Test status
Simulation time 16799301 ps
CPU time 1.2 seconds
Started Jul 12 05:45:51 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 206812 kb
Host smart-b9d9291f-f592-478a-8a61-9477ade7063c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166121264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3166121264
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1519733434
Short name T1130
Test name
Test status
Simulation time 140041217 ps
CPU time 2.71 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 215128 kb
Host smart-77f5b7fe-c7ad-4fd8-9896-2669cb80ac28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519733434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1519733434
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.100386694
Short name T278
Test name
Test status
Simulation time 99421509 ps
CPU time 1.74 seconds
Started Jul 12 05:45:44 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 207012 kb
Host smart-f520f158-815a-4474-a2ba-5d1ad9a8ec6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100386694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.100386694
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2275990568
Short name T1001
Test name
Test status
Simulation time 41500221 ps
CPU time 1.01 seconds
Started Jul 12 05:45:47 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 215184 kb
Host smart-3a4cbde9-d1b8-4a9a-87a8-09419ea7ab8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275990568 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2275990568
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2668118935
Short name T259
Test name
Test status
Simulation time 60143733 ps
CPU time 0.95 seconds
Started Jul 12 05:45:46 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 206932 kb
Host smart-b8597162-962c-4ddb-b171-f13d7dcacf53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668118935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2668118935
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1691834641
Short name T1023
Test name
Test status
Simulation time 13412645 ps
CPU time 0.91 seconds
Started Jul 12 05:45:47 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 206844 kb
Host smart-12162e8b-5b02-4e2c-a1b1-0c5282c6235e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691834641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1691834641
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1091649100
Short name T1045
Test name
Test status
Simulation time 58949395 ps
CPU time 1.09 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:46:00 PM PDT 24
Peak memory 206896 kb
Host smart-d3482e49-d177-4c0a-ab47-e35dad259ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091649100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1091649100
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3026747922
Short name T1071
Test name
Test status
Simulation time 85608254 ps
CPU time 1.68 seconds
Started Jul 12 05:45:44 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 215220 kb
Host smart-2f8961fe-9fd1-4a9d-aeaf-ae4a143098f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026747922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3026747922
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3596275605
Short name T277
Test name
Test status
Simulation time 52167008 ps
CPU time 1.69 seconds
Started Jul 12 05:45:51 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 206816 kb
Host smart-d0b92928-0f1c-4fa4-9885-0ecdf61fcf53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596275605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3596275605
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2762078770
Short name T1064
Test name
Test status
Simulation time 30990274 ps
CPU time 2.07 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 215156 kb
Host smart-37c0078a-35d4-4dc6-b82a-e4bb82422d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762078770 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2762078770
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.866377909
Short name T1129
Test name
Test status
Simulation time 40161008 ps
CPU time 0.83 seconds
Started Jul 12 05:45:56 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 206900 kb
Host smart-98c562a2-ba6b-459e-bdc2-6b86230a685d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866377909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.866377909
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2516318626
Short name T1057
Test name
Test status
Simulation time 25726871 ps
CPU time 0.83 seconds
Started Jul 12 05:45:48 PM PDT 24
Finished Jul 12 05:45:50 PM PDT 24
Peak memory 206476 kb
Host smart-09b35bb8-e5c4-4181-9906-16883fc80aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516318626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2516318626
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2027270380
Short name T1067
Test name
Test status
Simulation time 15671580 ps
CPU time 0.96 seconds
Started Jul 12 05:45:58 PM PDT 24
Finished Jul 12 05:46:00 PM PDT 24
Peak memory 206900 kb
Host smart-e7788a5f-333b-4391-98b6-7472e8a5574e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027270380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2027270380
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.59243279
Short name T1044
Test name
Test status
Simulation time 235574587 ps
CPU time 2.38 seconds
Started Jul 12 05:45:47 PM PDT 24
Finished Jul 12 05:45:51 PM PDT 24
Peak memory 215188 kb
Host smart-76fb7961-1c98-4655-97ca-32dd6dafc7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59243279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.59243279
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3100853410
Short name T1092
Test name
Test status
Simulation time 761104802 ps
CPU time 2.36 seconds
Started Jul 12 05:45:44 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206960 kb
Host smart-41231201-8341-4d36-9499-467add32c0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100853410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3100853410
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.872419245
Short name T1068
Test name
Test status
Simulation time 27905315 ps
CPU time 1.37 seconds
Started Jul 12 05:45:52 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 217100 kb
Host smart-32893bf8-9523-4f72-b985-63fd5e80b717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872419245 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.872419245
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1245492223
Short name T1078
Test name
Test status
Simulation time 28180929 ps
CPU time 0.8 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206728 kb
Host smart-475a8dbf-9be4-4d69-9ae7-7532118df3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245492223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1245492223
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2666077678
Short name T1032
Test name
Test status
Simulation time 17354143 ps
CPU time 0.97 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 207052 kb
Host smart-ebfd17d4-1e55-43ac-8a4e-766a599abe15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666077678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2666077678
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.722914725
Short name T1066
Test name
Test status
Simulation time 53573925 ps
CPU time 1.39 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 206988 kb
Host smart-791c2a77-0f77-43da-b758-c3fb9f427fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722914725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.722914725
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1358020124
Short name T1086
Test name
Test status
Simulation time 146440800 ps
CPU time 2.85 seconds
Started Jul 12 05:45:52 PM PDT 24
Finished Jul 12 05:45:56 PM PDT 24
Peak memory 219364 kb
Host smart-d8bf3194-7310-40db-be15-9396817db907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358020124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1358020124
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.921432766
Short name T1084
Test name
Test status
Simulation time 154625557 ps
CPU time 3.37 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 206984 kb
Host smart-d267487e-89b9-4932-80f0-201aaa1fdbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921432766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.921432766
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1984811259
Short name T1010
Test name
Test status
Simulation time 31502757 ps
CPU time 2.03 seconds
Started Jul 12 05:45:51 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 215212 kb
Host smart-a8c0d8c8-4887-47be-ad57-4f09cb65473f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984811259 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1984811259
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2662709498
Short name T269
Test name
Test status
Simulation time 14047535 ps
CPU time 0.92 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 206864 kb
Host smart-62e5429b-9173-4d48-8d11-2f2d5a57ff02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662709498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2662709498
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2226660909
Short name T1007
Test name
Test status
Simulation time 36354673 ps
CPU time 0.78 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:56 PM PDT 24
Peak memory 206608 kb
Host smart-a9eecd75-0eac-4033-99a2-620f30c726fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226660909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2226660909
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1546505172
Short name T1029
Test name
Test status
Simulation time 82683517 ps
CPU time 1.49 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 206888 kb
Host smart-2c5a8d27-6f6d-4e48-9ea4-0b598aa6a7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546505172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1546505172
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1238162707
Short name T1122
Test name
Test status
Simulation time 335474803 ps
CPU time 3 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 215244 kb
Host smart-2723e090-a1c6-4ca8-a24d-faf2a19f7767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238162707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1238162707
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.641735049
Short name T288
Test name
Test status
Simulation time 89118246 ps
CPU time 2.61 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 215148 kb
Host smart-eab87f25-3234-4a64-8bb5-f615a42253bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641735049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.641735049
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.944070895
Short name T1017
Test name
Test status
Simulation time 60701498 ps
CPU time 1.1 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 215188 kb
Host smart-591cf8fc-9729-47c6-a3ac-3917c5ddad6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944070895 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.944070895
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3666384976
Short name T1075
Test name
Test status
Simulation time 52145420 ps
CPU time 0.82 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 206688 kb
Host smart-2d68a39e-f608-4e23-a631-203c310fea7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666384976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3666384976
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4221798111
Short name T1097
Test name
Test status
Simulation time 24341188 ps
CPU time 0.92 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 206812 kb
Host smart-a33e7a6b-17f5-4004-9958-070339a94ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221798111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4221798111
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3988746646
Short name T1048
Test name
Test status
Simulation time 34303940 ps
CPU time 1.14 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 206872 kb
Host smart-bce6fb08-21ba-4e28-95de-86a6137593dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988746646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3988746646
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.960840918
Short name T1073
Test name
Test status
Simulation time 140160465 ps
CPU time 2.5 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 215148 kb
Host smart-3d567e3f-37e9-4ffe-9936-5a6e043ae7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960840918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.960840918
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.375212941
Short name T1077
Test name
Test status
Simulation time 61092713 ps
CPU time 1.07 seconds
Started Jul 12 05:46:34 PM PDT 24
Finished Jul 12 05:46:36 PM PDT 24
Peak memory 206948 kb
Host smart-a7516c44-6588-44ef-a002-67305db3176a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375212941 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.375212941
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3367954869
Short name T1074
Test name
Test status
Simulation time 51616635 ps
CPU time 0.95 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 207108 kb
Host smart-ebebf197-5329-4f9c-a098-0a54256c1e2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367954869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3367954869
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3399188337
Short name T1034
Test name
Test status
Simulation time 43161951 ps
CPU time 0.81 seconds
Started Jul 12 05:45:55 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 206684 kb
Host smart-8b0e36c4-59ac-4f2b-9832-bce81de3b996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399188337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3399188337
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.641018439
Short name T264
Test name
Test status
Simulation time 45372273 ps
CPU time 0.96 seconds
Started Jul 12 05:45:58 PM PDT 24
Finished Jul 12 05:46:00 PM PDT 24
Peak memory 206932 kb
Host smart-d46dab1c-4883-41a0-8e0b-c012dfc64268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641018439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.641018439
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2914866323
Short name T998
Test name
Test status
Simulation time 85566455 ps
CPU time 3.08 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 215140 kb
Host smart-7dd28588-586c-46f1-abdc-528d9d703fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914866323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2914866323
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1100730145
Short name T286
Test name
Test status
Simulation time 254149635 ps
CPU time 2.02 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 206928 kb
Host smart-fdcb77d0-767b-4f3f-b6cb-afc899ec7bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100730145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1100730145
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2449525852
Short name T1128
Test name
Test status
Simulation time 80053916 ps
CPU time 1.15 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 215224 kb
Host smart-64446764-0226-481b-9c84-9c066a7fdb03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449525852 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2449525852
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2938705935
Short name T268
Test name
Test status
Simulation time 16025541 ps
CPU time 0.93 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 206932 kb
Host smart-06ef26b9-6640-43d9-95ba-ba7cec43ffa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938705935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2938705935
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2293748073
Short name T1118
Test name
Test status
Simulation time 47777531 ps
CPU time 0.85 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 206784 kb
Host smart-cdd214bf-6503-496e-ad1e-5ef061ea5944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293748073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2293748073
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.746816587
Short name T1106
Test name
Test status
Simulation time 22151074 ps
CPU time 1.14 seconds
Started Jul 12 05:45:52 PM PDT 24
Finished Jul 12 05:45:54 PM PDT 24
Peak memory 206872 kb
Host smart-55874454-173e-425a-a911-20f1d2b7ffcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746816587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.746816587
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3732428201
Short name T1000
Test name
Test status
Simulation time 168561314 ps
CPU time 1.79 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:46:00 PM PDT 24
Peak memory 219112 kb
Host smart-d45c4c38-52aa-49e6-8798-751e344cb304
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732428201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3732428201
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1990010685
Short name T287
Test name
Test status
Simulation time 93543779 ps
CPU time 2.6 seconds
Started Jul 12 05:45:54 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 206928 kb
Host smart-2f264f9e-3975-4a74-a6be-9af717c7a4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990010685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1990010685
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.291603300
Short name T1069
Test name
Test status
Simulation time 59927384 ps
CPU time 1.21 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 215152 kb
Host smart-4848dc1e-ab54-4c21-8c45-57d25b5f20e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291603300 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.291603300
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2262367976
Short name T1008
Test name
Test status
Simulation time 22720474 ps
CPU time 0.89 seconds
Started Jul 12 05:46:01 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206764 kb
Host smart-e7d674d8-26ee-4a2a-b149-cb7dec35ab1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262367976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2262367976
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2827171147
Short name T1058
Test name
Test status
Simulation time 33116595 ps
CPU time 0.9 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:04 PM PDT 24
Peak memory 206856 kb
Host smart-dcef1b71-e2f3-4aa3-b6a2-8e3fb568a59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827171147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2827171147
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.614670317
Short name T270
Test name
Test status
Simulation time 36018808 ps
CPU time 1.09 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206896 kb
Host smart-20f9b16a-2fb3-45a9-a44d-c0168fbb500f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614670317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.614670317
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2588784502
Short name T1070
Test name
Test status
Simulation time 2868890811 ps
CPU time 4.7 seconds
Started Jul 12 05:45:53 PM PDT 24
Finished Jul 12 05:46:00 PM PDT 24
Peak memory 215364 kb
Host smart-8cfb07b2-85de-4bf9-8922-85b4bbb1450c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588784502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2588784502
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.814041458
Short name T1116
Test name
Test status
Simulation time 93080824 ps
CPU time 1.62 seconds
Started Jul 12 05:45:58 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 207208 kb
Host smart-402b3da6-7df0-4ee6-8e7a-d36971a165cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814041458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.814041458
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1393530808
Short name T255
Test name
Test status
Simulation time 68009814 ps
CPU time 1.43 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206864 kb
Host smart-7c45d1de-7163-400e-9fe2-ac57a308388d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393530808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1393530808
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.949227558
Short name T1065
Test name
Test status
Simulation time 94546092 ps
CPU time 2.97 seconds
Started Jul 12 05:45:39 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 206932 kb
Host smart-5217a9d1-00a1-4bad-bfbd-81a805971b6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949227558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.949227558
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1955730313
Short name T1041
Test name
Test status
Simulation time 19750242 ps
CPU time 0.95 seconds
Started Jul 12 05:45:34 PM PDT 24
Finished Jul 12 05:45:37 PM PDT 24
Peak memory 206832 kb
Host smart-c4436536-6b67-48eb-9f88-502290839045
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955730313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1955730313
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2063196156
Short name T1053
Test name
Test status
Simulation time 54038742 ps
CPU time 1.03 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 206940 kb
Host smart-22e0aaba-0945-4d1e-8198-ff520e482ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063196156 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2063196156
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1496237854
Short name T1090
Test name
Test status
Simulation time 25398226 ps
CPU time 0.82 seconds
Started Jul 12 05:45:44 PM PDT 24
Finished Jul 12 05:45:46 PM PDT 24
Peak memory 206748 kb
Host smart-8f00351e-01b7-46e1-ade3-05cba81365f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496237854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1496237854
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2408118458
Short name T1110
Test name
Test status
Simulation time 37155663 ps
CPU time 0.79 seconds
Started Jul 12 05:45:34 PM PDT 24
Finished Jul 12 05:45:36 PM PDT 24
Peak memory 206696 kb
Host smart-3b0642c4-d7b5-427e-b0e8-14896a4f29b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408118458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2408118458
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2486332465
Short name T1019
Test name
Test status
Simulation time 120700490 ps
CPU time 1.36 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 206972 kb
Host smart-9fc46ca2-1fc8-4fc8-a0aa-f23c63bb4192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486332465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2486332465
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3159286987
Short name T1085
Test name
Test status
Simulation time 84910712 ps
CPU time 2.12 seconds
Started Jul 12 05:45:30 PM PDT 24
Finished Jul 12 05:45:34 PM PDT 24
Peak memory 215116 kb
Host smart-507acad8-1e7e-49aa-aaa5-24dc1e6f633a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159286987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3159286987
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1527376752
Short name T1040
Test name
Test status
Simulation time 73981314 ps
CPU time 2.34 seconds
Started Jul 12 05:45:31 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 207164 kb
Host smart-665ac068-d736-4bc7-ab65-e2c84bf263c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527376752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1527376752
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1459182353
Short name T1024
Test name
Test status
Simulation time 23363846 ps
CPU time 0.86 seconds
Started Jul 12 05:45:59 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206900 kb
Host smart-2b5f1821-bc5c-423e-a209-f468096bfc78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459182353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1459182353
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.227706529
Short name T1100
Test name
Test status
Simulation time 23048842 ps
CPU time 0.85 seconds
Started Jul 12 05:46:51 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 206836 kb
Host smart-e973d088-fe3d-4823-8d7e-7522d11df131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227706529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.227706529
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1200987013
Short name T1021
Test name
Test status
Simulation time 20174850 ps
CPU time 0.83 seconds
Started Jul 12 05:46:00 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206656 kb
Host smart-255a086d-f0e9-494a-b72c-0826c7efd81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200987013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1200987013
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3379084340
Short name T1035
Test name
Test status
Simulation time 26937923 ps
CPU time 0.91 seconds
Started Jul 12 05:46:00 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206808 kb
Host smart-64ce985a-15a4-45a4-ba39-c283e21b949c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379084340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3379084340
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.519179088
Short name T995
Test name
Test status
Simulation time 22573230 ps
CPU time 0.79 seconds
Started Jul 12 05:46:03 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 206684 kb
Host smart-eae8e5ca-d7ad-4a26-94a0-52814b8554bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519179088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.519179088
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3018787730
Short name T1108
Test name
Test status
Simulation time 42015221 ps
CPU time 0.88 seconds
Started Jul 12 05:46:05 PM PDT 24
Finished Jul 12 05:46:07 PM PDT 24
Peak memory 206760 kb
Host smart-daec2c23-14dc-4091-a886-10bfa13b4739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018787730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3018787730
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3531155960
Short name T1076
Test name
Test status
Simulation time 13595334 ps
CPU time 0.86 seconds
Started Jul 12 05:46:00 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206836 kb
Host smart-956d280e-8241-4fbb-bc29-3b637d1bdae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531155960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3531155960
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2552659528
Short name T1038
Test name
Test status
Simulation time 14066245 ps
CPU time 0.96 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206804 kb
Host smart-67a6580b-23f7-42b8-9886-12f4ffb30f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552659528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2552659528
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3346535176
Short name T1005
Test name
Test status
Simulation time 22085353 ps
CPU time 0.98 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206876 kb
Host smart-ffe42214-971c-49cc-95ca-7c340d829b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346535176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3346535176
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.694754002
Short name T1087
Test name
Test status
Simulation time 61750941 ps
CPU time 0.85 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:04 PM PDT 24
Peak memory 206664 kb
Host smart-36160a5e-7df7-4f02-a8da-c5fe1196f6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694754002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.694754002
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2152803971
Short name T256
Test name
Test status
Simulation time 85695934 ps
CPU time 1.11 seconds
Started Jul 12 05:45:36 PM PDT 24
Finished Jul 12 05:45:38 PM PDT 24
Peak memory 206776 kb
Host smart-275d7a86-cde2-4694-870c-4cea453582b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152803971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2152803971
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.501047718
Short name T1095
Test name
Test status
Simulation time 261508643 ps
CPU time 3.59 seconds
Started Jul 12 05:45:37 PM PDT 24
Finished Jul 12 05:45:41 PM PDT 24
Peak memory 206864 kb
Host smart-c3fde9e7-e06d-4aa1-b1f5-03bd35cae3f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501047718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.501047718
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1325491140
Short name T1052
Test name
Test status
Simulation time 45429045 ps
CPU time 0.86 seconds
Started Jul 12 05:45:38 PM PDT 24
Finished Jul 12 05:45:40 PM PDT 24
Peak memory 206684 kb
Host smart-d898f875-c7c9-4032-b616-1b3cecb281df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325491140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1325491140
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1552009148
Short name T1115
Test name
Test status
Simulation time 63511734 ps
CPU time 1.28 seconds
Started Jul 12 05:45:38 PM PDT 24
Finished Jul 12 05:45:40 PM PDT 24
Peak memory 218800 kb
Host smart-d583a705-db44-400b-aef7-2d10b446d94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552009148 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1552009148
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1672861749
Short name T258
Test name
Test status
Simulation time 19494115 ps
CPU time 0.89 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206928 kb
Host smart-b728cc0f-9602-45d0-86c0-605d41301ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672861749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1672861749
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3885398478
Short name T1104
Test name
Test status
Simulation time 26824890 ps
CPU time 0.76 seconds
Started Jul 12 05:45:41 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 206692 kb
Host smart-ef61dab9-88bd-4ed7-bd56-e4237de71ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885398478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3885398478
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2572088558
Short name T263
Test name
Test status
Simulation time 38644974 ps
CPU time 1.54 seconds
Started Jul 12 05:45:39 PM PDT 24
Finished Jul 12 05:45:41 PM PDT 24
Peak memory 206860 kb
Host smart-955e07eb-0c60-4d36-9c5d-49806f72bc8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572088558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2572088558
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4223645286
Short name T1049
Test name
Test status
Simulation time 234931730 ps
CPU time 2.55 seconds
Started Jul 12 05:45:38 PM PDT 24
Finished Jul 12 05:45:41 PM PDT 24
Peak memory 215136 kb
Host smart-9fa39a9e-3889-4a78-9ed9-52e15f26e2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223645286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4223645286
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3046744480
Short name T276
Test name
Test status
Simulation time 114679663 ps
CPU time 2.18 seconds
Started Jul 12 05:45:40 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 207168 kb
Host smart-4146efe8-8bb4-4a8d-a645-e3107ca33981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046744480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3046744480
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3549842849
Short name T1046
Test name
Test status
Simulation time 43721534 ps
CPU time 0.87 seconds
Started Jul 12 05:46:05 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206760 kb
Host smart-3601fa44-41bf-4f75-b6c4-cdc0e500a24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549842849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3549842849
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3209622551
Short name T996
Test name
Test status
Simulation time 12018628 ps
CPU time 0.9 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:04 PM PDT 24
Peak memory 206808 kb
Host smart-57c7050c-4845-47b8-be05-d318530436b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209622551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3209622551
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.771574078
Short name T1107
Test name
Test status
Simulation time 48462358 ps
CPU time 0.84 seconds
Started Jul 12 05:46:05 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206768 kb
Host smart-f4b6489b-c950-40bf-bb85-4e985fbb2193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771574078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.771574078
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3444195080
Short name T1083
Test name
Test status
Simulation time 15303386 ps
CPU time 0.93 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:21 PM PDT 24
Peak memory 206824 kb
Host smart-2a4d0601-d1fe-439e-9b71-b3ff05687db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444195080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3444195080
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2281202590
Short name T1127
Test name
Test status
Simulation time 37813921 ps
CPU time 0.87 seconds
Started Jul 12 05:46:01 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206680 kb
Host smart-ff2271ef-8efc-464c-a7e2-6c3ec0ed5aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281202590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2281202590
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3957648639
Short name T1039
Test name
Test status
Simulation time 16010832 ps
CPU time 0.92 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206840 kb
Host smart-4824f848-2e4d-44fa-9224-1db3be5a5a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957648639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3957648639
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1805258213
Short name T1119
Test name
Test status
Simulation time 27094104 ps
CPU time 0.9 seconds
Started Jul 12 05:46:01 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206724 kb
Host smart-cfb6519d-2bf3-4e8c-bcfb-318788d65c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805258213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1805258213
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3219799224
Short name T1117
Test name
Test status
Simulation time 21848435 ps
CPU time 0.81 seconds
Started Jul 12 05:46:03 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 206752 kb
Host smart-23d740b2-e88d-4c7c-bdd6-df57fa8d8981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219799224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3219799224
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1986063509
Short name T1120
Test name
Test status
Simulation time 16669283 ps
CPU time 1 seconds
Started Jul 12 05:46:03 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 206836 kb
Host smart-4dcd6afe-acab-4e6c-9f90-1d004ce15f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986063509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1986063509
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1357045634
Short name T1055
Test name
Test status
Simulation time 110151978 ps
CPU time 0.86 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206816 kb
Host smart-7473ba3a-2871-4304-8e4a-981b9a45f3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357045634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1357045634
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2171251275
Short name T1091
Test name
Test status
Simulation time 35900298 ps
CPU time 1.29 seconds
Started Jul 12 05:45:37 PM PDT 24
Finished Jul 12 05:45:39 PM PDT 24
Peak memory 206976 kb
Host smart-a26f330c-4812-4d7f-b36c-39492726ed19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171251275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2171251275
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4199054057
Short name T262
Test name
Test status
Simulation time 37597973 ps
CPU time 2.06 seconds
Started Jul 12 05:45:51 PM PDT 24
Finished Jul 12 05:45:55 PM PDT 24
Peak memory 206908 kb
Host smart-49ab1f46-9542-4d7c-bfc5-43e9425a9d35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199054057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4199054057
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.950733900
Short name T1094
Test name
Test status
Simulation time 17868387 ps
CPU time 1.02 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 206924 kb
Host smart-6870a939-615c-457c-b80e-fb2f20cb98f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950733900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.950733900
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.159580165
Short name T1042
Test name
Test status
Simulation time 19470642 ps
CPU time 1.06 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 215184 kb
Host smart-3a0b2fd9-811e-43a6-9850-331dfc5f6122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159580165 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.159580165
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.672288121
Short name T260
Test name
Test status
Simulation time 15347599 ps
CPU time 0.96 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206864 kb
Host smart-78a7d887-af0a-4b29-bf74-cc2652912630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672288121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.672288121
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3384579266
Short name T1124
Test name
Test status
Simulation time 12182260 ps
CPU time 0.94 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206864 kb
Host smart-3ab36211-ad66-4e72-b27a-76a2eff22ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384579266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3384579266
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3014260637
Short name T1121
Test name
Test status
Simulation time 27706839 ps
CPU time 1.14 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 206972 kb
Host smart-4ec1a213-1ed3-46e2-b0c9-d26d04f7d119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014260637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3014260637
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1220491979
Short name T1047
Test name
Test status
Simulation time 645322129 ps
CPU time 3.76 seconds
Started Jul 12 05:45:39 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 215264 kb
Host smart-16d50956-7f80-4271-9f04-ac9949c93217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220491979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1220491979
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2855865044
Short name T289
Test name
Test status
Simulation time 240461943 ps
CPU time 2.9 seconds
Started Jul 12 05:45:39 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 206884 kb
Host smart-14076a6c-a302-4419-b312-b0461b4dc81b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855865044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2855865044
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3924003420
Short name T1082
Test name
Test status
Simulation time 14589113 ps
CPU time 0.91 seconds
Started Jul 12 05:46:03 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 206844 kb
Host smart-5e1c205f-81a8-46fa-89f6-3c9b71789b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924003420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3924003420
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.364124403
Short name T1059
Test name
Test status
Simulation time 44681045 ps
CPU time 0.89 seconds
Started Jul 12 05:46:05 PM PDT 24
Finished Jul 12 05:46:07 PM PDT 24
Peak memory 206748 kb
Host smart-405a53b3-55f5-43a6-9753-fa97ca1cd73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364124403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.364124403
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.952982087
Short name T997
Test name
Test status
Simulation time 16631626 ps
CPU time 0.84 seconds
Started Jul 12 05:46:01 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206648 kb
Host smart-2333b8f2-4178-4f27-a285-42e000c691f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952982087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.952982087
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4195567531
Short name T1016
Test name
Test status
Simulation time 41945377 ps
CPU time 0.84 seconds
Started Jul 12 05:45:59 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206776 kb
Host smart-e5545f7f-ab47-4833-9b95-94467ebd52ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195567531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4195567531
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2024780444
Short name T1006
Test name
Test status
Simulation time 101426826 ps
CPU time 0.85 seconds
Started Jul 12 05:46:01 PM PDT 24
Finished Jul 12 05:46:03 PM PDT 24
Peak memory 206872 kb
Host smart-667fdbec-4a9b-43d5-88dc-5db94c57370c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024780444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2024780444
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3478970533
Short name T1033
Test name
Test status
Simulation time 18313139 ps
CPU time 0.82 seconds
Started Jul 12 05:46:04 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 206572 kb
Host smart-d12310b8-9e87-4adb-8e5e-7c6b0255cc27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478970533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3478970533
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1021552299
Short name T1098
Test name
Test status
Simulation time 23530306 ps
CPU time 0.82 seconds
Started Jul 12 05:46:02 PM PDT 24
Finished Jul 12 05:46:04 PM PDT 24
Peak memory 206748 kb
Host smart-876e2c7c-d4ac-4cc2-abeb-3b046f87242c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021552299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1021552299
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.141190375
Short name T1123
Test name
Test status
Simulation time 44407317 ps
CPU time 0.9 seconds
Started Jul 12 05:46:00 PM PDT 24
Finished Jul 12 05:46:02 PM PDT 24
Peak memory 206852 kb
Host smart-1fb8fc80-0da3-48ef-9a20-da76b8662990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141190375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.141190375
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4094136337
Short name T1081
Test name
Test status
Simulation time 62459358 ps
CPU time 0.81 seconds
Started Jul 12 05:46:00 PM PDT 24
Finished Jul 12 05:46:01 PM PDT 24
Peak memory 206660 kb
Host smart-96f4d0cc-8819-425d-8337-1d7f49b53fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094136337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4094136337
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4169282938
Short name T1037
Test name
Test status
Simulation time 48112946 ps
CPU time 0.83 seconds
Started Jul 12 05:46:03 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 206876 kb
Host smart-23e6ec76-2e9b-4bde-8231-a6b96793a554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169282938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4169282938
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2938030510
Short name T1072
Test name
Test status
Simulation time 110831524 ps
CPU time 1.23 seconds
Started Jul 12 05:47:37 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 215160 kb
Host smart-64f035d9-fbd8-4533-8211-5d16eca5162a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938030510 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2938030510
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2358046180
Short name T1027
Test name
Test status
Simulation time 12784438 ps
CPU time 0.93 seconds
Started Jul 12 05:45:40 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 206876 kb
Host smart-6119795e-b9d9-4f90-9995-958c6c0192da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358046180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2358046180
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.922925909
Short name T1050
Test name
Test status
Simulation time 33509401 ps
CPU time 0.9 seconds
Started Jul 12 05:45:40 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 207044 kb
Host smart-16b941c8-5a4d-47c5-8d02-0c47b9e80658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922925909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.922925909
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.498957121
Short name T1062
Test name
Test status
Simulation time 32006395 ps
CPU time 1.48 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206996 kb
Host smart-c08636ab-0989-488c-9a29-3316dd39dadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498957121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.498957121
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1365119161
Short name T1060
Test name
Test status
Simulation time 111879447 ps
CPU time 3.84 seconds
Started Jul 12 05:45:39 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 215152 kb
Host smart-01b21172-4da9-42a0-878f-873e5eb2ce14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365119161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1365119161
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3368023552
Short name T1103
Test name
Test status
Simulation time 156358081 ps
CPU time 3.19 seconds
Started Jul 12 05:45:38 PM PDT 24
Finished Jul 12 05:45:43 PM PDT 24
Peak memory 215112 kb
Host smart-b97c53cf-a722-4af7-be00-249c81bbc7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368023552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3368023552
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.209641561
Short name T1051
Test name
Test status
Simulation time 30240523 ps
CPU time 1.15 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 215172 kb
Host smart-df47c9dc-1d58-4ab2-9a09-6daa55d62f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209641561 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.209641561
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3299343906
Short name T1025
Test name
Test status
Simulation time 53675586 ps
CPU time 0.97 seconds
Started Jul 12 05:45:40 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 206812 kb
Host smart-d7475d93-5ad3-4844-ae32-81611b647be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299343906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3299343906
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.782835328
Short name T1105
Test name
Test status
Simulation time 43533847 ps
CPU time 0.85 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 206852 kb
Host smart-e4528986-8519-4f6a-bf3c-5d4aedb29745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782835328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.782835328
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2730706024
Short name T266
Test name
Test status
Simulation time 36249869 ps
CPU time 1.45 seconds
Started Jul 12 05:45:38 PM PDT 24
Finished Jul 12 05:45:41 PM PDT 24
Peak memory 206912 kb
Host smart-0aad8205-2ac4-41c2-8f10-1355172d2625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730706024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2730706024
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1224662229
Short name T1096
Test name
Test status
Simulation time 92900037 ps
CPU time 3.49 seconds
Started Jul 12 05:45:40 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 215184 kb
Host smart-3c0c3a32-96ac-4d88-8604-926a7335c23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224662229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1224662229
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2739275409
Short name T284
Test name
Test status
Simulation time 3552421372 ps
CPU time 13.55 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 206980 kb
Host smart-bb8f6af9-9961-4d33-9745-46063c917c47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739275409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2739275409
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4029713852
Short name T1026
Test name
Test status
Simulation time 127909432 ps
CPU time 1.55 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 215304 kb
Host smart-03e03698-52e9-4d7c-a707-6505864b97fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029713852 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.4029713852
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3191732713
Short name T1030
Test name
Test status
Simulation time 14541293 ps
CPU time 0.98 seconds
Started Jul 12 05:45:47 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 206916 kb
Host smart-03512a16-8a2b-4728-8ae7-7b44e6ec0c7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191732713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3191732713
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4105941393
Short name T1112
Test name
Test status
Simulation time 10706092 ps
CPU time 0.85 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:45:58 PM PDT 24
Peak memory 206840 kb
Host smart-e78a23c2-f23d-44c3-8be3-59218c75c7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105941393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4105941393
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3403674384
Short name T1093
Test name
Test status
Simulation time 96785652 ps
CPU time 1.52 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 206924 kb
Host smart-d0b5c9ac-5864-45e9-aea6-c8992c5f8e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403674384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3403674384
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.336785725
Short name T1099
Test name
Test status
Simulation time 86394290 ps
CPU time 3.21 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:46 PM PDT 24
Peak memory 215208 kb
Host smart-4ae81014-2dae-464d-90d8-9bb6aab01604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336785725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.336785725
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3831485963
Short name T1054
Test name
Test status
Simulation time 75038993 ps
CPU time 1.55 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206972 kb
Host smart-211496de-dce5-4eb7-865c-988d6b639a52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831485963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3831485963
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2669230398
Short name T1043
Test name
Test status
Simulation time 65755916 ps
CPU time 1.47 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:48 PM PDT 24
Peak memory 215104 kb
Host smart-cdab4cdb-1b77-4f0d-966b-da51632c7f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669230398 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2669230398
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1456968330
Short name T252
Test name
Test status
Simulation time 31461488 ps
CPU time 0.79 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206724 kb
Host smart-db70f98e-bfa6-4792-a879-eb6fdd90b958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456968330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1456968330
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3505952002
Short name T1014
Test name
Test status
Simulation time 25954541 ps
CPU time 0.82 seconds
Started Jul 12 05:45:47 PM PDT 24
Finished Jul 12 05:45:49 PM PDT 24
Peak memory 206800 kb
Host smart-5d4c8891-776d-48d7-bec7-f20dd89c521c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505952002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3505952002
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1757456951
Short name T267
Test name
Test status
Simulation time 21820354 ps
CPU time 1.08 seconds
Started Jul 12 05:45:43 PM PDT 24
Finished Jul 12 05:45:45 PM PDT 24
Peak memory 206880 kb
Host smart-b43d9de3-0873-4d4f-9dd2-c4e7dcf1fb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757456951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1757456951
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3826509975
Short name T1063
Test name
Test status
Simulation time 194882355 ps
CPU time 3.35 seconds
Started Jul 12 05:45:42 PM PDT 24
Finished Jul 12 05:45:46 PM PDT 24
Peak memory 215108 kb
Host smart-0a14f0f5-38ac-4696-8de0-1bc8500e1d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826509975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3826509975
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2326524142
Short name T1111
Test name
Test status
Simulation time 51359633 ps
CPU time 1.65 seconds
Started Jul 12 05:45:44 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206912 kb
Host smart-8fb68ae6-e3f7-4733-af9f-50c21c21142a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326524142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2326524142
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.506920506
Short name T1003
Test name
Test status
Simulation time 15776376 ps
CPU time 0.97 seconds
Started Jul 12 05:45:48 PM PDT 24
Finished Jul 12 05:45:50 PM PDT 24
Peak memory 206760 kb
Host smart-ce144341-27ae-4ff8-a5ce-0f6c41759105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506920506 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.506920506
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2752580830
Short name T257
Test name
Test status
Simulation time 45454531 ps
CPU time 0.9 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 207108 kb
Host smart-e9dafff7-fa31-4887-a80a-5cba34f79814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752580830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2752580830
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2123511903
Short name T1004
Test name
Test status
Simulation time 123470928 ps
CPU time 0.87 seconds
Started Jul 12 05:45:57 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 206840 kb
Host smart-9260a702-d950-4d9f-b130-7b8ce988d382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123511903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2123511903
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3580200669
Short name T1031
Test name
Test status
Simulation time 22796387 ps
CPU time 1.1 seconds
Started Jul 12 05:45:45 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 206864 kb
Host smart-7244069f-e894-4a2c-88af-9ff2a4cad612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580200669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3580200669
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1393812291
Short name T1009
Test name
Test status
Simulation time 133942148 ps
CPU time 3.83 seconds
Started Jul 12 05:45:48 PM PDT 24
Finished Jul 12 05:45:53 PM PDT 24
Peak memory 215192 kb
Host smart-61d5d38a-54ea-4a8c-ab87-fc2c02828901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393812291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1393812291
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2941390515
Short name T1020
Test name
Test status
Simulation time 145925661 ps
CPU time 1.62 seconds
Started Jul 12 05:45:48 PM PDT 24
Finished Jul 12 05:45:51 PM PDT 24
Peak memory 215060 kb
Host smart-026a78ba-b5b6-4d4c-a92d-0ce6345ac86d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941390515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2941390515
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2467524253
Short name T282
Test name
Test status
Simulation time 33177535 ps
CPU time 1.15 seconds
Started Jul 12 06:36:40 PM PDT 24
Finished Jul 12 06:36:43 PM PDT 24
Peak memory 219104 kb
Host smart-b6f141f7-e2a5-48ac-9b5b-1fd0aabc8d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467524253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2467524253
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.195705636
Short name T915
Test name
Test status
Simulation time 12779283 ps
CPU time 0.87 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 207228 kb
Host smart-dab4a06e-bdc9-4091-affa-cfd9acebd545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195705636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.195705636
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3624578801
Short name T560
Test name
Test status
Simulation time 18925692 ps
CPU time 0.87 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 216468 kb
Host smart-310e726a-d6b4-44f3-a835-348864b56f78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624578801 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3624578801
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1544981289
Short name T151
Test name
Test status
Simulation time 73200280 ps
CPU time 0.99 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 217132 kb
Host smart-5c71d0c9-fba0-44f8-9f7f-237566bdc714
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544981289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1544981289
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2858795847
Short name T618
Test name
Test status
Simulation time 73832709 ps
CPU time 1.16 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 226100 kb
Host smart-1c7e242d-bb81-49e2-b2c9-84b3042a728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858795847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2858795847
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2018520340
Short name T531
Test name
Test status
Simulation time 63181517 ps
CPU time 1.16 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 217596 kb
Host smart-b593a5ae-3f5f-4f8a-80e1-948091d60e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018520340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2018520340
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.4263108799
Short name T316
Test name
Test status
Simulation time 35223088 ps
CPU time 0.99 seconds
Started Jul 12 06:36:41 PM PDT 24
Finished Jul 12 06:36:43 PM PDT 24
Peak memory 207424 kb
Host smart-63913c8e-9547-4dbe-9062-df84049a265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263108799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4263108799
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3536399773
Short name T65
Test name
Test status
Simulation time 244251084 ps
CPU time 4.49 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:59 PM PDT 24
Peak memory 237464 kb
Host smart-1c7a37ac-1e51-433b-8467-7a4e7e0979d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536399773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3536399773
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4106349205
Short name T554
Test name
Test status
Simulation time 18168933 ps
CPU time 1 seconds
Started Jul 12 06:36:44 PM PDT 24
Finished Jul 12 06:36:47 PM PDT 24
Peak memory 215608 kb
Host smart-e08bb090-a660-426f-a705-f107d8d5ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106349205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4106349205
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.430283673
Short name T961
Test name
Test status
Simulation time 81039189 ps
CPU time 1.52 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:46 PM PDT 24
Peak memory 217488 kb
Host smart-b38619b8-7b52-4ef7-88b6-7e157d86aeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430283673 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.430283673
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3974883597
Short name T420
Test name
Test status
Simulation time 229466229860 ps
CPU time 1344.36 seconds
Started Jul 12 06:36:40 PM PDT 24
Finished Jul 12 06:59:06 PM PDT 24
Peak memory 224156 kb
Host smart-590ed445-27cf-4897-bafc-a39727a821a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974883597 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3974883597
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1885618429
Short name T580
Test name
Test status
Simulation time 86644063 ps
CPU time 1.14 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 218912 kb
Host smart-be13d9d4-a96e-49b7-bbc7-ac9330bae2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885618429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1885618429
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2707178561
Short name T386
Test name
Test status
Simulation time 19928403 ps
CPU time 0.86 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 215152 kb
Host smart-bb0f948f-3e02-4fbc-87d9-dddbb598e985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707178561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2707178561
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1536426414
Short name T969
Test name
Test status
Simulation time 33287359 ps
CPU time 0.82 seconds
Started Jul 12 06:36:48 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 216452 kb
Host smart-de2419e8-4674-42fe-994d-55e0bc33afc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536426414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1536426414
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1900289247
Short name T698
Test name
Test status
Simulation time 132228905 ps
CPU time 1.16 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 217208 kb
Host smart-8b967c40-5241-4645-b0be-2a22ed86f4a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900289247 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1900289247
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3933914442
Short name T217
Test name
Test status
Simulation time 22463430 ps
CPU time 1.07 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 219972 kb
Host smart-8d1223cb-d72d-46f9-8701-52bd7cc151e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933914442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3933914442
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.151284255
Short name T979
Test name
Test status
Simulation time 54351371 ps
CPU time 1.48 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 219004 kb
Host smart-255a83b1-f163-4445-b8b0-63170403f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151284255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.151284255
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2881795417
Short name T658
Test name
Test status
Simulation time 58114396 ps
CPU time 0.87 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 215780 kb
Host smart-2cf53c6b-7a85-46f3-ad06-7e5d8dd59315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881795417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2881795417
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3062488192
Short name T27
Test name
Test status
Simulation time 174734685 ps
CPU time 0.97 seconds
Started Jul 12 06:38:51 PM PDT 24
Finished Jul 12 06:38:53 PM PDT 24
Peak memory 207340 kb
Host smart-e6208f8c-0ef5-48ee-a07a-d1ba2ebb5e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062488192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3062488192
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all.442007357
Short name T954
Test name
Test status
Simulation time 439118237 ps
CPU time 5.37 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 215608 kb
Host smart-00bc2186-0c65-4ee1-8933-ae89d692b599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442007357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.442007357
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4054894963
Short name T236
Test name
Test status
Simulation time 131100154973 ps
CPU time 809.39 seconds
Started Jul 12 06:36:44 PM PDT 24
Finished Jul 12 06:50:16 PM PDT 24
Peak memory 222032 kb
Host smart-923217f8-5cce-45bf-a64c-d8668179964c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054894963 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4054894963
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2359544542
Short name T613
Test name
Test status
Simulation time 22229756 ps
CPU time 1.14 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:12 PM PDT 24
Peak memory 218784 kb
Host smart-9cef25de-ea80-4fe5-a5fb-5ca9cbdd82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359544542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2359544542
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.232746338
Short name T545
Test name
Test status
Simulation time 15933294 ps
CPU time 0.95 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 215300 kb
Host smart-5ccc0e25-394c-4bb5-a057-48c2829925d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232746338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.232746338
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1220972699
Short name T150
Test name
Test status
Simulation time 45532563 ps
CPU time 0.99 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 217000 kb
Host smart-9a0f2b72-a9bc-4201-95d6-dd5015f375b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220972699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1220972699
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1417413000
Short name T542
Test name
Test status
Simulation time 161830776 ps
CPU time 0.96 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 219444 kb
Host smart-2ec1ab73-67f6-48ad-883e-0e8dfcf17c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417413000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1417413000
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.779924418
Short name T701
Test name
Test status
Simulation time 98049456 ps
CPU time 1.56 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:11 PM PDT 24
Peak memory 218944 kb
Host smart-5376ef6e-d44d-42cc-9ef8-1656611edc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779924418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.779924418
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.796750977
Short name T789
Test name
Test status
Simulation time 29999995 ps
CPU time 1 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 215908 kb
Host smart-ddc8f1dd-82e0-4a5a-9a90-b984007c0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796750977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.796750977
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3106276157
Short name T606
Test name
Test status
Simulation time 45554628 ps
CPU time 0.93 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:10 PM PDT 24
Peak memory 215560 kb
Host smart-b11b0c09-7504-4c2e-a1aa-b1ab4afad85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106276157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3106276157
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1122700287
Short name T359
Test name
Test status
Simulation time 597949259 ps
CPU time 1.46 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:12 PM PDT 24
Peak memory 217600 kb
Host smart-ff2eeff3-13da-4595-8364-fc8bc03bff53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122700287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1122700287
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3725081353
Short name T496
Test name
Test status
Simulation time 81432815009 ps
CPU time 509.56 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:45:49 PM PDT 24
Peak memory 221104 kb
Host smart-3d0ccd94-fb44-4ff6-ad18-b4062d45fc40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725081353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3725081353
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3537835422
Short name T552
Test name
Test status
Simulation time 47387863 ps
CPU time 1.23 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 219480 kb
Host smart-eca595f2-91dd-4852-8c8d-c5517f4e7ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537835422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3537835422
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1836771910
Short name T905
Test name
Test status
Simulation time 51578772 ps
CPU time 1.12 seconds
Started Jul 12 06:38:39 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 217440 kb
Host smart-3d9479f4-4e27-4d01-9e23-a97e502807ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836771910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1836771910
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2138342843
Short name T367
Test name
Test status
Simulation time 88429137 ps
CPU time 1.38 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 219024 kb
Host smart-bf77d09f-e4dd-402e-80bd-f3319e4d2dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138342843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2138342843
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1333638380
Short name T668
Test name
Test status
Simulation time 29907386 ps
CPU time 1.27 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 220184 kb
Host smart-e73d467c-52b9-4f24-bb55-1c620d0578ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333638380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1333638380
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3702489888
Short name T987
Test name
Test status
Simulation time 111472370 ps
CPU time 1.12 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 217504 kb
Host smart-cc835ef5-7ded-4429-a729-ff503748b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702489888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3702489888
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2696229293
Short name T164
Test name
Test status
Simulation time 48023081 ps
CPU time 1.17 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 221560 kb
Host smart-448100ec-4d8b-4ff1-99d3-d25172faf2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696229293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2696229293
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.721073069
Short name T649
Test name
Test status
Simulation time 46434540 ps
CPU time 1.33 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:43 PM PDT 24
Peak memory 219004 kb
Host smart-cc7aa671-3ae2-460a-adbe-b70ebcc5bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721073069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.721073069
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3834795421
Short name T561
Test name
Test status
Simulation time 67502623 ps
CPU time 1.13 seconds
Started Jul 12 06:38:33 PM PDT 24
Finished Jul 12 06:38:36 PM PDT 24
Peak memory 218860 kb
Host smart-8b418212-f52d-4cf4-bc72-00815f04f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834795421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3834795421
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.198582821
Short name T862
Test name
Test status
Simulation time 58563916 ps
CPU time 1.32 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:39 PM PDT 24
Peak memory 217652 kb
Host smart-2f41026c-83be-4dcd-aac7-98782f00f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198582821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.198582821
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.162149947
Short name T59
Test name
Test status
Simulation time 22636437 ps
CPU time 1.13 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 219824 kb
Host smart-e462dbaa-3e26-465a-9d65-3a0b31106911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162149947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.162149947
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.436475638
Short name T517
Test name
Test status
Simulation time 33821809 ps
CPU time 1.29 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 218768 kb
Host smart-0376d85e-374c-429f-938d-bee267710929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436475638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.436475638
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2198130107
Short name T131
Test name
Test status
Simulation time 27226561 ps
CPU time 1.32 seconds
Started Jul 12 06:38:38 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 219560 kb
Host smart-5006b8fd-dec4-4abd-a54e-7e8f5599826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198130107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2198130107
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.350346512
Short name T468
Test name
Test status
Simulation time 135902588 ps
CPU time 2 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:39 PM PDT 24
Peak memory 220412 kb
Host smart-1c63f4f9-c9db-40c6-981d-d623ab837fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350346512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.350346512
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2828022037
Short name T633
Test name
Test status
Simulation time 40405812 ps
CPU time 1.11 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:42 PM PDT 24
Peak memory 220992 kb
Host smart-e7df8a4d-3079-4269-bce0-99c296f78114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828022037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2828022037
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2177120468
Short name T533
Test name
Test status
Simulation time 173213768 ps
CPU time 1.51 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:39 PM PDT 24
Peak memory 218920 kb
Host smart-75ac2464-f589-4234-910b-4f8787c4c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177120468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2177120468
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2453001880
Short name T445
Test name
Test status
Simulation time 105318986 ps
CPU time 1.89 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 220144 kb
Host smart-4557a9d2-0c10-4998-ace6-241cb6466d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453001880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2453001880
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.597893413
Short name T85
Test name
Test status
Simulation time 31495311 ps
CPU time 1.38 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 215952 kb
Host smart-2096f2b1-8651-42c7-8941-0afa9b259483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597893413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.597893413
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.2403747975
Short name T141
Test name
Test status
Simulation time 149625555 ps
CPU time 1.23 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 219768 kb
Host smart-5e23b04f-d550-4519-92e3-4ea67ec2fb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403747975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2403747975
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4235971340
Short name T376
Test name
Test status
Simulation time 29571513 ps
CPU time 0.94 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:10 PM PDT 24
Peak memory 215208 kb
Host smart-bde0c095-711a-4389-9498-ddb5558346dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235971340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4235971340
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2850687583
Short name T79
Test name
Test status
Simulation time 18410953 ps
CPU time 0.84 seconds
Started Jul 12 06:37:03 PM PDT 24
Finished Jul 12 06:37:05 PM PDT 24
Peak memory 215716 kb
Host smart-7124d752-5fb6-4bb9-9834-173189a42947
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850687583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2850687583
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1440547026
Short name T694
Test name
Test status
Simulation time 84532836 ps
CPU time 1.02 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:07 PM PDT 24
Peak memory 217228 kb
Host smart-b84cb4e2-66a2-4c51-ad7c-d3fb33e38ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440547026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1440547026
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3688633187
Short name T743
Test name
Test status
Simulation time 32106770 ps
CPU time 0.89 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 218100 kb
Host smart-bda3e630-58df-4db4-9a3d-716fa2b355ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688633187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3688633187
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1631309528
Short name T983
Test name
Test status
Simulation time 48828723 ps
CPU time 1.32 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 217760 kb
Host smart-d4c2ceff-fd58-4b4c-bdec-60e071ae78f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631309528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1631309528
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.295340484
Short name T102
Test name
Test status
Simulation time 45912313 ps
CPU time 0.83 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 215652 kb
Host smart-a6484bbb-5ca6-426f-9a2c-858f7e0fa187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295340484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.295340484
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.9319011
Short name T105
Test name
Test status
Simulation time 41742101 ps
CPU time 0.93 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:13 PM PDT 24
Peak memory 215580 kb
Host smart-cd722403-fecc-4805-819d-b247f71deba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9319011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.9319011
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1858545359
Short name T968
Test name
Test status
Simulation time 248817143 ps
CPU time 5.51 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 215672 kb
Host smart-eca7b86c-148f-4774-8ef1-e15988c0f2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858545359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1858545359
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.742459939
Short name T557
Test name
Test status
Simulation time 65196846306 ps
CPU time 752.83 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:49:51 PM PDT 24
Peak memory 219304 kb
Host smart-c4147cda-e098-4420-8877-749859227e25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742459939 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.742459939
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2755282520
Short name T340
Test name
Test status
Simulation time 111963186 ps
CPU time 1.57 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 220280 kb
Host smart-0d2bc3ec-c156-4658-a519-fc8517fd6557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755282520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2755282520
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4128854826
Short name T251
Test name
Test status
Simulation time 47161614 ps
CPU time 1.19 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:44 PM PDT 24
Peak memory 220844 kb
Host smart-a58f894b-fbee-4c8a-984d-59c6ad36e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128854826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4128854826
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.289468508
Short name T470
Test name
Test status
Simulation time 42222949 ps
CPU time 1.63 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 218812 kb
Host smart-c920a057-f420-458a-ac6f-7dba30200e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289468508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.289468508
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3333652441
Short name T487
Test name
Test status
Simulation time 123987364 ps
CPU time 1.18 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 218892 kb
Host smart-ddece604-df34-4b36-bdda-5c889380a597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333652441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3333652441
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1554467539
Short name T749
Test name
Test status
Simulation time 43445123 ps
CPU time 1.44 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 218836 kb
Host smart-3b1d6e3b-636a-4807-993c-f3175010e8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554467539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1554467539
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1341271553
Short name T153
Test name
Test status
Simulation time 55924558 ps
CPU time 1.32 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 220252 kb
Host smart-65a3e8cd-00d7-4e89-ad3d-a03417dfb707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341271553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1341271553
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3453281694
Short name T765
Test name
Test status
Simulation time 28793088 ps
CPU time 1.27 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 220264 kb
Host smart-6bb57215-afc5-4973-8c9c-11070e434913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453281694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3453281694
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3015388850
Short name T11
Test name
Test status
Simulation time 53828378 ps
CPU time 1.32 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 220208 kb
Host smart-e13dd239-f9b7-4528-ac3a-ef53968b09b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015388850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3015388850
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3614837839
Short name T49
Test name
Test status
Simulation time 26429747 ps
CPU time 1.25 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 220124 kb
Host smart-3e87c328-3622-4d9f-8543-4b8ce62e7687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614837839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3614837839
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.907732597
Short name T394
Test name
Test status
Simulation time 68440395 ps
CPU time 1.37 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 219152 kb
Host smart-83448fdc-6074-4aef-ac33-42864d9d5729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907732597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.907732597
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1376354500
Short name T931
Test name
Test status
Simulation time 50200914 ps
CPU time 1.54 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 217480 kb
Host smart-cde24a23-9a0f-4610-8090-343b27b8072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376354500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1376354500
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1284437082
Short name T629
Test name
Test status
Simulation time 38344800 ps
CPU time 1.1 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 218724 kb
Host smart-41f94589-65cc-48be-b5c6-f795ae902910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284437082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1284437082
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1361797246
Short name T644
Test name
Test status
Simulation time 35908725 ps
CPU time 1.5 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 218940 kb
Host smart-032ea7ca-434f-47fb-bb52-1bab07204b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361797246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1361797246
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2163640686
Short name T955
Test name
Test status
Simulation time 29819895 ps
CPU time 1.27 seconds
Started Jul 12 06:39:04 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 220096 kb
Host smart-4cc8d31c-5732-457e-8804-02f347142918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163640686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2163640686
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.2764505913
Short name T928
Test name
Test status
Simulation time 95662357 ps
CPU time 1.25 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 216108 kb
Host smart-b6854f33-5feb-4f62-87fe-1832dd69b020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764505913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2764505913
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1458262600
Short name T845
Test name
Test status
Simulation time 38864585 ps
CPU time 1.52 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 219728 kb
Host smart-e19e535c-89f0-4fd4-ac2d-a9ef39a3bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458262600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1458262600
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3592747845
Short name T592
Test name
Test status
Simulation time 110602082 ps
CPU time 1.1 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:11 PM PDT 24
Peak memory 219712 kb
Host smart-500d857e-006f-4041-ad5e-5d7820a2c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592747845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3592747845
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.862794600
Short name T208
Test name
Test status
Simulation time 33064294 ps
CPU time 1.16 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 216828 kb
Host smart-908dc31a-2f46-4c4d-a0ed-5b507c3df035
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862794600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.862794600
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.4179325169
Short name T243
Test name
Test status
Simulation time 40640570 ps
CPU time 1.15 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 219168 kb
Host smart-059fe175-2480-46a7-a2d4-bd780e7c2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179325169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4179325169
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2695246976
Short name T405
Test name
Test status
Simulation time 20654965 ps
CPU time 1.18 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:12 PM PDT 24
Peak memory 224312 kb
Host smart-485c1256-f25a-4e2b-84e3-f94a70c93019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695246976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2695246976
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2719344751
Short name T904
Test name
Test status
Simulation time 19134436 ps
CPU time 1 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 215568 kb
Host smart-54571ad3-92cc-4461-99fb-bd2de8b5788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719344751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2719344751
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1491695693
Short name T596
Test name
Test status
Simulation time 801586539 ps
CPU time 4.44 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 215604 kb
Host smart-366fbcd6-9374-4594-9be2-c8296ead186c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491695693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1491695693
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1659942204
Short name T814
Test name
Test status
Simulation time 184335298932 ps
CPU time 1044.28 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:54:35 PM PDT 24
Peak memory 223592 kb
Host smart-8d2dc0ea-e8c0-4691-8e05-63f12efce48d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659942204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1659942204
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1673380891
Short name T927
Test name
Test status
Simulation time 39352006 ps
CPU time 1.1 seconds
Started Jul 12 06:39:34 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 220020 kb
Host smart-6dd7b3b7-38df-42a4-88fa-4259403a99f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673380891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1673380891
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3425868904
Short name T479
Test name
Test status
Simulation time 80505059 ps
CPU time 1.4 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 219044 kb
Host smart-9f83d359-1b36-4c9b-aa75-c29760af9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425868904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3425868904
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1067088348
Short name T636
Test name
Test status
Simulation time 48220786 ps
CPU time 1.2 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 219196 kb
Host smart-20adcd11-b91b-4bbe-99e5-380d0befb41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067088348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1067088348
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3071099646
Short name T900
Test name
Test status
Simulation time 91769201 ps
CPU time 1.16 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 217500 kb
Host smart-33df9175-4220-4db2-a4e5-ca305b4e6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071099646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3071099646
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.4181288735
Short name T247
Test name
Test status
Simulation time 104161427 ps
CPU time 1.2 seconds
Started Jul 12 06:38:46 PM PDT 24
Finished Jul 12 06:38:49 PM PDT 24
Peak memory 218892 kb
Host smart-c9731b2c-9f0b-4ccd-ae15-1f32aa5e3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181288735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4181288735
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2829195132
Short name T559
Test name
Test status
Simulation time 45188877 ps
CPU time 1.53 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:47 PM PDT 24
Peak memory 218748 kb
Host smart-9e543479-f740-4768-a7d0-b544d97a2f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829195132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2829195132
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2839431679
Short name T991
Test name
Test status
Simulation time 65996212 ps
CPU time 1.15 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 219368 kb
Host smart-1eac0b18-c3ff-4da2-8394-bc4296c0b005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839431679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2839431679
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.3282125816
Short name T604
Test name
Test status
Simulation time 62899653 ps
CPU time 1.18 seconds
Started Jul 12 06:38:41 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 219084 kb
Host smart-1ef2046f-310c-48a4-866e-c12cf56c5620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282125816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3282125816
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.2722302908
Short name T570
Test name
Test status
Simulation time 22979802 ps
CPU time 1.16 seconds
Started Jul 12 06:38:44 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 218900 kb
Host smart-b570eead-d80c-4b3b-9e3c-000a69d8a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722302908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2722302908
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1933622360
Short name T870
Test name
Test status
Simulation time 92119491 ps
CPU time 2.2 seconds
Started Jul 12 06:38:43 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 219572 kb
Host smart-57521146-dac4-4039-a455-bdb3315a5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933622360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1933622360
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3320804966
Short name T864
Test name
Test status
Simulation time 44093390 ps
CPU time 1.25 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:45 PM PDT 24
Peak memory 220856 kb
Host smart-246d3d4e-eb66-4660-bb19-f03968886a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320804966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3320804966
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.3211752929
Short name T908
Test name
Test status
Simulation time 25565138 ps
CPU time 1.22 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 220040 kb
Host smart-e0149bb7-dd57-4eb6-9e99-5ae58b8a5709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211752929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3211752929
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.337818744
Short name T777
Test name
Test status
Simulation time 123447310 ps
CPU time 2.67 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 220308 kb
Host smart-4abf9b43-da8a-453c-8e18-060dbb5eced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337818744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.337818744
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.332498486
Short name T925
Test name
Test status
Simulation time 38642020 ps
CPU time 1.11 seconds
Started Jul 12 06:37:13 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 218912 kb
Host smart-040a21cd-fe39-4580-a19f-6fe435f40434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332498486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.332498486
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3303227556
Short name T581
Test name
Test status
Simulation time 38629970 ps
CPU time 1.04 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 215196 kb
Host smart-2d1405e2-57c9-4e41-a4d0-02f6d96c12ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303227556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3303227556
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2464512849
Short name T182
Test name
Test status
Simulation time 30191570 ps
CPU time 0.82 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 216556 kb
Host smart-e24b61f4-7d35-4498-9bc3-d438d0b57aa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464512849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2464512849
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2561036880
Short name T822
Test name
Test status
Simulation time 39758162 ps
CPU time 1.27 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 217144 kb
Host smart-7f24bea5-6a19-4f7c-b225-7109a840ae36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561036880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2561036880
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.4015166320
Short name T654
Test name
Test status
Simulation time 30620405 ps
CPU time 0.89 seconds
Started Jul 12 06:37:13 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 218696 kb
Host smart-e85a69f9-fce6-494b-8b32-f2be3403f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015166320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.4015166320
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3558800656
Short name T392
Test name
Test status
Simulation time 65323953 ps
CPU time 1.37 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:11 PM PDT 24
Peak memory 219260 kb
Host smart-3eed1304-de6c-489c-811f-2080fe95f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558800656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3558800656
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1592903465
Short name T817
Test name
Test status
Simulation time 20009069 ps
CPU time 1.05 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:12 PM PDT 24
Peak memory 216152 kb
Host smart-4604cf57-90fc-4a29-9a8b-58feddc4ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592903465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1592903465
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.80964410
Short name T369
Test name
Test status
Simulation time 46294217 ps
CPU time 0.91 seconds
Started Jul 12 06:37:03 PM PDT 24
Finished Jul 12 06:37:06 PM PDT 24
Peak memory 207396 kb
Host smart-84cbf0b4-6226-481b-9af2-b99207aa06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80964410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.80964410
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3388924720
Short name T346
Test name
Test status
Simulation time 75213570 ps
CPU time 1.95 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:37:10 PM PDT 24
Peak memory 215560 kb
Host smart-c13a93fa-60a0-4451-aa37-60e94202d99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388924720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3388924720
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.174827230
Short name T916
Test name
Test status
Simulation time 83490772601 ps
CPU time 925.39 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:52:34 PM PDT 24
Peak memory 223240 kb
Host smart-ee93a121-5c26-4a7b-9729-f3f2cb46a432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174827230 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.174827230
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3682476311
Short name T516
Test name
Test status
Simulation time 44987204 ps
CPU time 1.14 seconds
Started Jul 12 06:38:47 PM PDT 24
Finished Jul 12 06:38:50 PM PDT 24
Peak memory 215972 kb
Host smart-2daa3bdd-6803-405f-bb52-dc2f9decd5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682476311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3682476311
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.4041457508
Short name T491
Test name
Test status
Simulation time 47029608 ps
CPU time 1.14 seconds
Started Jul 12 06:38:48 PM PDT 24
Finished Jul 12 06:38:51 PM PDT 24
Peak memory 217848 kb
Host smart-37d933ae-9e6f-4e10-9a1c-7c015102a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041457508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4041457508
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3056979288
Short name T378
Test name
Test status
Simulation time 267458935 ps
CPU time 1.07 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 220108 kb
Host smart-60835141-14ea-4ac3-aaa3-32a1cacc11f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056979288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3056979288
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3941199039
Short name T797
Test name
Test status
Simulation time 65401172 ps
CPU time 1.14 seconds
Started Jul 12 06:38:47 PM PDT 24
Finished Jul 12 06:38:50 PM PDT 24
Peak memory 219920 kb
Host smart-7605a4d4-e027-48ad-8c0e-2dcf37cdf08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941199039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3941199039
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4101568063
Short name T110
Test name
Test status
Simulation time 22051646 ps
CPU time 1.19 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 219024 kb
Host smart-8acc288d-8d8d-430d-877d-cd28b5fc2b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101568063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4101568063
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.707606880
Short name T692
Test name
Test status
Simulation time 86211308 ps
CPU time 1.16 seconds
Started Jul 12 06:38:45 PM PDT 24
Finished Jul 12 06:38:48 PM PDT 24
Peak memory 219856 kb
Host smart-f13fdb12-7995-41d5-8287-e5854c3a1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707606880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.707606880
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3679210664
Short name T522
Test name
Test status
Simulation time 81341368 ps
CPU time 1.22 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:53 PM PDT 24
Peak memory 217572 kb
Host smart-74573348-d88b-41a2-9745-1ce3f680a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679210664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3679210664
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3822217919
Short name T962
Test name
Test status
Simulation time 108119760 ps
CPU time 1.24 seconds
Started Jul 12 06:38:47 PM PDT 24
Finished Jul 12 06:38:50 PM PDT 24
Peak memory 217588 kb
Host smart-cf0db87f-a5d7-477a-aadb-d807978d34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822217919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3822217919
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.455198397
Short name T922
Test name
Test status
Simulation time 22601782 ps
CPU time 1.12 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 220068 kb
Host smart-6591acac-5fe9-48b4-bac6-51b6723ab906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455198397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.455198397
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1536284974
Short name T841
Test name
Test status
Simulation time 96248261 ps
CPU time 3.27 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:07 PM PDT 24
Peak memory 220484 kb
Host smart-374bff16-368b-4024-bdac-4a9c7cc7d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536284974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1536284974
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2099355072
Short name T458
Test name
Test status
Simulation time 73963848 ps
CPU time 1.09 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:51 PM PDT 24
Peak memory 221012 kb
Host smart-eef9427c-9724-4312-a529-5084e38fa764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099355072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2099355072
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.3832668346
Short name T978
Test name
Test status
Simulation time 64972703 ps
CPU time 1.1 seconds
Started Jul 12 06:38:47 PM PDT 24
Finished Jul 12 06:38:50 PM PDT 24
Peak memory 220612 kb
Host smart-a894f50e-4252-4cc9-a022-59e82ce411c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832668346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3832668346
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3951205636
Short name T351
Test name
Test status
Simulation time 58504934 ps
CPU time 1.54 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 218968 kb
Host smart-ba9c553d-7252-404c-a4fc-d9ec2e33858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951205636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3951205636
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2855552087
Short name T973
Test name
Test status
Simulation time 32446195 ps
CPU time 1.2 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 218972 kb
Host smart-9402c78c-1754-49e3-bc47-682c3ce25257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855552087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2855552087
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.912636417
Short name T576
Test name
Test status
Simulation time 37123620 ps
CPU time 1.04 seconds
Started Jul 12 06:38:48 PM PDT 24
Finished Jul 12 06:38:51 PM PDT 24
Peak memory 217820 kb
Host smart-9f443602-4166-4380-a112-274a2aae4d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912636417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.912636417
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.223338399
Short name T719
Test name
Test status
Simulation time 153089591 ps
CPU time 1.21 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 218956 kb
Host smart-717d1845-cf80-43c8-bf65-800faa7fdb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223338399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.223338399
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.146214094
Short name T397
Test name
Test status
Simulation time 120273622 ps
CPU time 1.42 seconds
Started Jul 12 06:38:49 PM PDT 24
Finished Jul 12 06:38:52 PM PDT 24
Peak memory 218956 kb
Host smart-77fa2bc2-e02f-4add-a0bf-cd842d357d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146214094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.146214094
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2985033099
Short name T700
Test name
Test status
Simulation time 48049528 ps
CPU time 1.19 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 219952 kb
Host smart-df8fa3a0-e25f-4aa6-b392-bfe5c4fb2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985033099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2985033099
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3101241700
Short name T363
Test name
Test status
Simulation time 13454236 ps
CPU time 0.9 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 207000 kb
Host smart-25a2ea97-ee82-4842-b525-cf8184235a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101241700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3101241700
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.406904232
Short name T833
Test name
Test status
Simulation time 12286551 ps
CPU time 0.9 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 215880 kb
Host smart-94073085-9575-4383-abaf-a24e7bf0ff8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406904232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.406904232
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1636969539
Short name T899
Test name
Test status
Simulation time 25162910 ps
CPU time 1.18 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 218596 kb
Host smart-d96a354b-354b-4b4a-add0-14632e54f581
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636969539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1636969539
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1304226262
Short name T8
Test name
Test status
Simulation time 61464745 ps
CPU time 1.15 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 229916 kb
Host smart-4cc5798d-2441-4649-8c16-40c484feb701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304226262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1304226262
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.532916977
Short name T831
Test name
Test status
Simulation time 143525164 ps
CPU time 1.28 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 218932 kb
Host smart-08cc5c7b-cc3a-4f1d-8786-4668e8932506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532916977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.532916977
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.2064555892
Short name T959
Test name
Test status
Simulation time 23182103 ps
CPU time 0.91 seconds
Started Jul 12 06:37:13 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 215544 kb
Host smart-f603f461-2b48-48df-8b66-790ee85df3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064555892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2064555892
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.357623906
Short name T50
Test name
Test status
Simulation time 185745954 ps
CPU time 4.16 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 217420 kb
Host smart-2ade0370-0c41-4a6a-8aa9-27aa8a11a81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357623906 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.357623906
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1253481917
Short name T537
Test name
Test status
Simulation time 77922629937 ps
CPU time 857.98 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:51:35 PM PDT 24
Peak memory 220544 kb
Host smart-4fac1b7f-cca3-461b-b93c-6e91ca63dc74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253481917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1253481917
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1482636637
Short name T298
Test name
Test status
Simulation time 134341230 ps
CPU time 1.24 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 219336 kb
Host smart-23d65eb2-7fde-41ec-a8e7-554a144f557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482636637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1482636637
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.140945954
Short name T163
Test name
Test status
Simulation time 49122504 ps
CPU time 1.19 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 220140 kb
Host smart-6c45af46-5f02-4931-a7f2-2b8e0a7faae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140945954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.140945954
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3004605439
Short name T463
Test name
Test status
Simulation time 78253480 ps
CPU time 1.01 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:53 PM PDT 24
Peak memory 215564 kb
Host smart-2552f9aa-496f-4ac9-bf39-17156f9063f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004605439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3004605439
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1808949826
Short name T600
Test name
Test status
Simulation time 42249258 ps
CPU time 1.21 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 220728 kb
Host smart-00cd27ec-d8ea-440e-9f58-51a7ac2260e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808949826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1808949826
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3838845795
Short name T674
Test name
Test status
Simulation time 155424867 ps
CPU time 2.07 seconds
Started Jul 12 06:38:50 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 220040 kb
Host smart-29e2a446-940c-4342-89c6-3e4646d39b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838845795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3838845795
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2275168659
Short name T813
Test name
Test status
Simulation time 27589012 ps
CPU time 1.2 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 220516 kb
Host smart-5a3add51-a056-4f6b-be9e-7ccdf63fb438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275168659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2275168659
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3956687762
Short name T474
Test name
Test status
Simulation time 51171017 ps
CPU time 1.87 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 219100 kb
Host smart-048d9e0c-3c72-4c46-b33f-32ab314712db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956687762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3956687762
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1067329786
Short name T448
Test name
Test status
Simulation time 73880608 ps
CPU time 1.18 seconds
Started Jul 12 06:38:55 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 219844 kb
Host smart-d3ef956e-e522-48f7-b93e-8fb21d1e1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067329786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1067329786
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.531121825
Short name T682
Test name
Test status
Simulation time 77337122 ps
CPU time 1.14 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 217572 kb
Host smart-636ee0c3-3bfd-444c-9415-9c133f3fa86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531121825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.531121825
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.611404105
Short name T707
Test name
Test status
Simulation time 23195937 ps
CPU time 1.25 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 218708 kb
Host smart-f589100c-531a-4960-8613-c9b7a1ee8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611404105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.611404105
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1078784925
Short name T43
Test name
Test status
Simulation time 68727087 ps
CPU time 1.24 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 217672 kb
Host smart-b19e159e-ab90-4c8d-9533-b6e9f0a96f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078784925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1078784925
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.985259442
Short name T548
Test name
Test status
Simulation time 290203848 ps
CPU time 1.26 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 219648 kb
Host smart-306eb869-cac9-4251-9ab2-d94c010198f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985259442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.985259442
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1832361711
Short name T891
Test name
Test status
Simulation time 61059485 ps
CPU time 1.28 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 219012 kb
Host smart-821ad18c-29d6-41cf-abaf-32a361d11782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832361711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1832361711
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4044850930
Short name T647
Test name
Test status
Simulation time 24516916 ps
CPU time 1.23 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 219596 kb
Host smart-efa01841-6f26-4f3b-95d8-205373a70507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044850930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4044850930
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1025505935
Short name T625
Test name
Test status
Simulation time 43342229 ps
CPU time 1.51 seconds
Started Jul 12 06:38:55 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 218908 kb
Host smart-90d14e1b-5346-4e1c-84bc-3cc02d16426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025505935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1025505935
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2103998201
Short name T728
Test name
Test status
Simulation time 224866228 ps
CPU time 1.17 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:05 PM PDT 24
Peak memory 220884 kb
Host smart-33f0bcf0-5199-4744-b12d-9effcf0d37a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103998201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2103998201
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2360799263
Short name T869
Test name
Test status
Simulation time 42061908 ps
CPU time 1.56 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:55 PM PDT 24
Peak memory 217712 kb
Host smart-0c24706e-5c52-4850-8659-c50195e3df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360799263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2360799263
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2590860635
Short name T828
Test name
Test status
Simulation time 21261575 ps
CPU time 1.13 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:04 PM PDT 24
Peak memory 217544 kb
Host smart-cf7fe405-52f2-42ee-9040-0c4fedd80d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590860635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2590860635
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3958044585
Short name T755
Test name
Test status
Simulation time 37037119 ps
CPU time 0.85 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 207032 kb
Host smart-8a5cd389-bf15-4a44-8362-102ab67ffc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958044585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3958044585
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1326847567
Short name T211
Test name
Test status
Simulation time 149804552 ps
CPU time 1.14 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 219776 kb
Host smart-a91d2c3a-2e5e-4563-b727-6b2a71fe1efc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326847567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1326847567
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.307226993
Short name T850
Test name
Test status
Simulation time 18134376 ps
CPU time 1.02 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 218860 kb
Host smart-d90f395d-2203-4362-9c31-aeb8fc106adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307226993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.307226993
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1156001464
Short name T294
Test name
Test status
Simulation time 56702904 ps
CPU time 1.68 seconds
Started Jul 12 06:37:13 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 218688 kb
Host smart-70c0ac36-d1cf-48d5-a722-705cfbd0bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156001464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1156001464
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1450162739
Short name T752
Test name
Test status
Simulation time 26552884 ps
CPU time 1.09 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 224304 kb
Host smart-26d12162-42cd-44da-83b6-3ca7fc5a8eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450162739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1450162739
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2083512850
Short name T483
Test name
Test status
Simulation time 26645691 ps
CPU time 0.92 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 215616 kb
Host smart-cc420e38-8a85-4c06-8fe0-517539a3b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083512850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2083512850
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1395362297
Short name T665
Test name
Test status
Simulation time 514761908 ps
CPU time 2.92 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 217560 kb
Host smart-4c308531-5af8-4be7-8ee1-ab1d914e6962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395362297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1395362297
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3045860964
Short name T907
Test name
Test status
Simulation time 188945406813 ps
CPU time 785.7 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:50:19 PM PDT 24
Peak memory 222596 kb
Host smart-68e9f9be-68f2-4b30-82a7-6321cccf8a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045860964 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3045860964
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.4266068994
Short name T501
Test name
Test status
Simulation time 52700702 ps
CPU time 1.24 seconds
Started Jul 12 06:38:53 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 216000 kb
Host smart-ff24cb7b-ec82-48bc-984f-ac6116b248ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266068994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.4266068994
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3377902675
Short name T590
Test name
Test status
Simulation time 101567097 ps
CPU time 1.15 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 217416 kb
Host smart-1b3132c5-dd8f-4365-9ad8-3357dc254f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377902675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3377902675
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.968796537
Short name T829
Test name
Test status
Simulation time 36891430 ps
CPU time 1.15 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 220632 kb
Host smart-f1ec9ac3-da03-44d6-a592-8fa9ffdcb14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968796537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.968796537
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1381591250
Short name T938
Test name
Test status
Simulation time 47644831 ps
CPU time 1.58 seconds
Started Jul 12 06:38:56 PM PDT 24
Finished Jul 12 06:38:59 PM PDT 24
Peak memory 218852 kb
Host smart-c74a4441-bc0b-4a7d-b2da-cb3c89ff1e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381591250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1381591250
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3157505215
Short name T913
Test name
Test status
Simulation time 72231434 ps
CPU time 1.22 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 221020 kb
Host smart-65d46b63-18bc-4e74-8380-0f42e584c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157505215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3157505215
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1470609436
Short name T627
Test name
Test status
Simulation time 50085384 ps
CPU time 1.42 seconds
Started Jul 12 06:38:56 PM PDT 24
Finished Jul 12 06:38:58 PM PDT 24
Peak memory 218720 kb
Host smart-00b45838-ff14-4087-9fdb-55342c5cdf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470609436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1470609436
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1132351279
Short name T113
Test name
Test status
Simulation time 24023638 ps
CPU time 1.25 seconds
Started Jul 12 06:38:59 PM PDT 24
Finished Jul 12 06:39:01 PM PDT 24
Peak memory 218952 kb
Host smart-b16147e8-b876-4237-854c-b5571ec3bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132351279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1132351279
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3413882301
Short name T404
Test name
Test status
Simulation time 37286249 ps
CPU time 1.35 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 220184 kb
Host smart-f3b2b644-e1a3-4a22-a0bf-9a0fc826ec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413882301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3413882301
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1865947240
Short name T342
Test name
Test status
Simulation time 24749230 ps
CPU time 1.14 seconds
Started Jul 12 06:38:55 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 218900 kb
Host smart-c9f551f5-d247-45d7-824c-392a89637b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865947240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1865947240
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1674305724
Short name T23
Test name
Test status
Simulation time 221858805 ps
CPU time 1.46 seconds
Started Jul 12 06:38:55 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 220288 kb
Host smart-412211d6-90de-45db-987f-79c1ce41e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674305724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1674305724
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1437825550
Short name T194
Test name
Test status
Simulation time 30251884 ps
CPU time 1.31 seconds
Started Jul 12 06:38:57 PM PDT 24
Finished Jul 12 06:38:59 PM PDT 24
Peak memory 221332 kb
Host smart-db348044-e690-43dc-ad46-e323a2b2e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437825550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1437825550
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2831365416
Short name T799
Test name
Test status
Simulation time 29214423 ps
CPU time 1.2 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:54 PM PDT 24
Peak memory 220016 kb
Host smart-52f71c66-cb52-4730-a1dc-50ce27d29db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831365416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2831365416
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3253778988
Short name T567
Test name
Test status
Simulation time 129505014 ps
CPU time 1.31 seconds
Started Jul 12 06:38:56 PM PDT 24
Finished Jul 12 06:38:58 PM PDT 24
Peak memory 219904 kb
Host smart-5698e32e-03d3-4e46-9cbd-8a2e6f824aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253778988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3253778988
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.297348689
Short name T770
Test name
Test status
Simulation time 67915431 ps
CPU time 1.37 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 219248 kb
Host smart-dcedc435-dc0f-445f-921e-b1a78f091f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297348689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.297348689
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.105085323
Short name T245
Test name
Test status
Simulation time 87998415 ps
CPU time 1.16 seconds
Started Jul 12 06:38:55 PM PDT 24
Finished Jul 12 06:38:57 PM PDT 24
Peak memory 219004 kb
Host smart-88c07bae-8095-4726-b221-8ee4f6a90297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105085323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.105085323
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3948025176
Short name T909
Test name
Test status
Simulation time 44047245 ps
CPU time 1.56 seconds
Started Jul 12 06:38:52 PM PDT 24
Finished Jul 12 06:38:55 PM PDT 24
Peak memory 220700 kb
Host smart-1ed293b5-7a7d-440f-9050-de8bf58890b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948025176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3948025176
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3158965073
Short name T786
Test name
Test status
Simulation time 44292353 ps
CPU time 1.24 seconds
Started Jul 12 06:38:54 PM PDT 24
Finished Jul 12 06:38:56 PM PDT 24
Peak memory 219948 kb
Host smart-a1577a94-97eb-4184-a952-9c615f9e6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158965073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3158965073
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1193519403
Short name T820
Test name
Test status
Simulation time 81898968 ps
CPU time 1.19 seconds
Started Jul 12 06:38:58 PM PDT 24
Finished Jul 12 06:39:00 PM PDT 24
Peak memory 217536 kb
Host smart-16f55291-e324-4da2-b2f9-a59939b212e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193519403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1193519403
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4031905357
Short name T427
Test name
Test status
Simulation time 65431345 ps
CPU time 1.19 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 220144 kb
Host smart-7c0c6fda-2c74-45e9-90fd-226c4dfad5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031905357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4031905357
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1492436128
Short name T746
Test name
Test status
Simulation time 234611263 ps
CPU time 3.59 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 219916 kb
Host smart-1b10fd2f-6fe6-4122-b34f-305fa87974c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492436128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1492436128
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2395333165
Short name T280
Test name
Test status
Simulation time 25912933 ps
CPU time 1.17 seconds
Started Jul 12 06:37:11 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 218756 kb
Host smart-a8d4525c-9a4d-4019-8307-378a63518d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395333165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2395333165
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3454823539
Short name T790
Test name
Test status
Simulation time 96610591 ps
CPU time 0.93 seconds
Started Jul 12 06:37:13 PM PDT 24
Finished Jul 12 06:37:18 PM PDT 24
Peak memory 206972 kb
Host smart-1c337d95-e475-4eda-b45a-12dbbb71a595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454823539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3454823539
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2659922717
Short name T890
Test name
Test status
Simulation time 21437211 ps
CPU time 0.85 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 216320 kb
Host smart-3fec7f26-8354-4df2-abbb-95062864789e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659922717 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2659922717
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.3615937696
Short name T200
Test name
Test status
Simulation time 23791281 ps
CPU time 1.01 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 229828 kb
Host smart-09b31b47-4191-4fd3-b089-bd2aa8393319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615937696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3615937696
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2737290802
Short name T315
Test name
Test status
Simulation time 280386912 ps
CPU time 3.96 seconds
Started Jul 12 06:37:11 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 218052 kb
Host smart-56ffa76e-8f1a-4c17-9541-83a3931e8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737290802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2737290802
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2371838620
Short name T467
Test name
Test status
Simulation time 27654672 ps
CPU time 0.86 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 215896 kb
Host smart-da55851b-cfc7-422b-ab0c-cd28b6ac0fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371838620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2371838620
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.762756275
Short name T893
Test name
Test status
Simulation time 16856686 ps
CPU time 0.97 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 215596 kb
Host smart-b47a62e6-0d9b-488c-8e82-92f1070982bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762756275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.762756275
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3900226782
Short name T758
Test name
Test status
Simulation time 310069320 ps
CPU time 2.61 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:15 PM PDT 24
Peak memory 215592 kb
Host smart-f8ac1fc3-399b-4fd5-a4cd-c87a04c75d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900226782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3900226782
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2310020780
Short name T234
Test name
Test status
Simulation time 453430221795 ps
CPU time 1519.27 seconds
Started Jul 12 06:37:11 PM PDT 24
Finished Jul 12 07:02:35 PM PDT 24
Peak memory 224320 kb
Host smart-0ef2d946-9f54-4498-a2c2-eab4a7b975d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310020780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2310020780
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3816355091
Short name T742
Test name
Test status
Simulation time 38766374 ps
CPU time 1.13 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 218912 kb
Host smart-74e3cad0-6d9d-4cd9-bdd5-74b8b0f55889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816355091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3816355091
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.427777501
Short name T825
Test name
Test status
Simulation time 90487524 ps
CPU time 1.23 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:02 PM PDT 24
Peak memory 217540 kb
Host smart-4fc2ee23-71d1-4e69-b31b-fb94ba05bcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427777501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.427777501
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.889145150
Short name T774
Test name
Test status
Simulation time 301387235 ps
CPU time 1.5 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:07 PM PDT 24
Peak memory 218876 kb
Host smart-f23a6804-bbbe-4d91-ab51-8947144c81e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889145150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.889145150
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1069516234
Short name T350
Test name
Test status
Simulation time 131333477 ps
CPU time 1.51 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 219344 kb
Host smart-2d14c9bb-c404-4530-a769-20956e700eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069516234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1069516234
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3514167961
Short name T720
Test name
Test status
Simulation time 41639019 ps
CPU time 1.21 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 219736 kb
Host smart-5b770e2f-ba64-4f51-9921-ae43e0695aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514167961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3514167961
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4054393945
Short name T614
Test name
Test status
Simulation time 36853307 ps
CPU time 1.4 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 219004 kb
Host smart-0fe9be9b-58a4-4274-861f-30809357cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054393945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4054393945
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1571994472
Short name T733
Test name
Test status
Simulation time 70941991 ps
CPU time 1.06 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:26 PM PDT 24
Peak memory 220140 kb
Host smart-0adcb6d3-a4b7-4a12-bc74-f9dc4ffbda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571994472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1571994472
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1228316285
Short name T307
Test name
Test status
Simulation time 116143079 ps
CPU time 1.23 seconds
Started Jul 12 06:39:06 PM PDT 24
Finished Jul 12 06:39:11 PM PDT 24
Peak memory 219320 kb
Host smart-9c68096c-2cf8-42c7-869e-c8993b512c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228316285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1228316285
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2770935453
Short name T944
Test name
Test status
Simulation time 97296440 ps
CPU time 1.21 seconds
Started Jul 12 06:39:04 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 219048 kb
Host smart-af98edda-d066-46c3-8ead-5c1d43cf7436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770935453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2770935453
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2881568891
Short name T460
Test name
Test status
Simulation time 106698035 ps
CPU time 1.29 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 217676 kb
Host smart-93ef60e5-d810-432e-a3d0-5d648292037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881568891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2881568891
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2914959691
Short name T539
Test name
Test status
Simulation time 23260637 ps
CPU time 1.25 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:02 PM PDT 24
Peak memory 220080 kb
Host smart-07259b83-8d86-4f02-8c67-ddec075b9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914959691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2914959691
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3305211863
Short name T902
Test name
Test status
Simulation time 40861036 ps
CPU time 1.54 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 218636 kb
Host smart-e6b8bbb2-0931-48e3-99f8-96262895d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305211863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3305211863
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.943211923
Short name T343
Test name
Test status
Simulation time 23962298 ps
CPU time 1.19 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:05 PM PDT 24
Peak memory 218728 kb
Host smart-72901e3b-9498-44f2-bcea-ae30f462228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943211923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.943211923
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1938607698
Short name T966
Test name
Test status
Simulation time 29165928 ps
CPU time 1.24 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 221096 kb
Host smart-50d9d73f-9cb2-4e1a-a079-7f71dcc1e5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938607698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1938607698
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1628715274
Short name T372
Test name
Test status
Simulation time 68735340 ps
CPU time 1.53 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 219188 kb
Host smart-ca821e6e-e736-49b3-87a9-70413c4682cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628715274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1628715274
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.151931202
Short name T686
Test name
Test status
Simulation time 66650973 ps
CPU time 1.3 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 219152 kb
Host smart-8b2e88b7-f85c-478f-9132-1204ebf74ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151931202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.151931202
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.424361040
Short name T465
Test name
Test status
Simulation time 60792162 ps
CPU time 1.07 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:04 PM PDT 24
Peak memory 219932 kb
Host smart-62076bff-9d8c-4275-896f-47d3fd70f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424361040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.424361040
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.603742711
Short name T546
Test name
Test status
Simulation time 44351296 ps
CPU time 1.66 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:07 PM PDT 24
Peak memory 219036 kb
Host smart-c9605e3d-6014-4cae-8723-9bda81b3c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603742711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.603742711
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3233445505
Short name T824
Test name
Test status
Simulation time 107146945 ps
CPU time 1.32 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 220092 kb
Host smart-75495795-4b4e-4234-8ec7-f8d749c7b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233445505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3233445505
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1106800624
Short name T510
Test name
Test status
Simulation time 288962175 ps
CPU time 0.97 seconds
Started Jul 12 06:37:09 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 207040 kb
Host smart-b42612d1-a3c6-4d83-adeb-ff401586b30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106800624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1106800624
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3952562035
Short name T224
Test name
Test status
Simulation time 11010165 ps
CPU time 0.89 seconds
Started Jul 12 06:37:11 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 215692 kb
Host smart-daf3985a-9042-4e9a-a993-4c817b392f6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952562035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3952562035
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2482129171
Short name T528
Test name
Test status
Simulation time 46776228 ps
CPU time 1 seconds
Started Jul 12 06:37:10 PM PDT 24
Finished Jul 12 06:37:16 PM PDT 24
Peak memory 218612 kb
Host smart-5d6aeead-9649-4899-ad47-ea92ba2fef8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482129171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2482129171
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1877353038
Short name T642
Test name
Test status
Simulation time 57069776 ps
CPU time 0.97 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 219968 kb
Host smart-5301b612-dcc8-4f2d-b626-a4b5629319df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877353038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1877353038
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2820855051
Short name T621
Test name
Test status
Simulation time 87085537 ps
CPU time 3.22 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:21 PM PDT 24
Peak memory 218112 kb
Host smart-c0408932-098a-49b1-b6d0-5a310271fcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820855051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2820855051
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2494171045
Short name T844
Test name
Test status
Simulation time 40320786 ps
CPU time 0.99 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:17 PM PDT 24
Peak memory 224080 kb
Host smart-d5095d55-f449-46c9-8083-974c01e1a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494171045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2494171045
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2387013706
Short name T863
Test name
Test status
Simulation time 45308051 ps
CPU time 0.89 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 215588 kb
Host smart-a0bdbe9b-ff95-4a17-83b2-6f74b1e765a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387013706 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2387013706
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4162277246
Short name T871
Test name
Test status
Simulation time 860998488 ps
CPU time 3.49 seconds
Started Jul 12 06:37:12 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 217572 kb
Host smart-d55230b5-45f2-4e8c-91d7-82a8ae18057d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162277246 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4162277246
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3643042198
Short name T950
Test name
Test status
Simulation time 68596533053 ps
CPU time 1777.99 seconds
Started Jul 12 06:37:11 PM PDT 24
Finished Jul 12 07:06:54 PM PDT 24
Peak memory 227572 kb
Host smart-a3b1a43c-23b4-476b-9b3b-b673d0072ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643042198 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3643042198
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.969112247
Short name T366
Test name
Test status
Simulation time 55137874 ps
CPU time 1.16 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219492 kb
Host smart-66b58754-7929-426b-98e5-367c1b3cf825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969112247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.969112247
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4074301489
Short name T46
Test name
Test status
Simulation time 106769264 ps
CPU time 1.42 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 217800 kb
Host smart-9f4e329d-7998-4bb1-9c7e-f01afd035c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074301489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4074301489
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3822626151
Short name T179
Test name
Test status
Simulation time 97703620 ps
CPU time 1.32 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 215848 kb
Host smart-4e002c1b-5653-46be-838b-e2196fdcd1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822626151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3822626151
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3893465380
Short name T589
Test name
Test status
Simulation time 102395351 ps
CPU time 1.23 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:02 PM PDT 24
Peak memory 217624 kb
Host smart-9de64e8d-0d6c-4377-8633-04a174968b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893465380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3893465380
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2756911610
Short name T180
Test name
Test status
Simulation time 345967756 ps
CPU time 1.21 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 219636 kb
Host smart-0a0c5ff6-c804-4506-a693-a07a0fef28e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756911610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2756911610
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1800594590
Short name T611
Test name
Test status
Simulation time 73864803 ps
CPU time 1.64 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 219080 kb
Host smart-f4f03636-5b9a-4d4c-8a09-30c54a5a50ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800594590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1800594590
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2178364671
Short name T221
Test name
Test status
Simulation time 49982497 ps
CPU time 1.19 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 220112 kb
Host smart-4fd8a645-3bb8-4fbf-a68d-3a3bd3a48acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178364671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2178364671
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2672893921
Short name T837
Test name
Test status
Simulation time 34919528 ps
CPU time 1.28 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 218660 kb
Host smart-7ca9c615-83a8-4f7e-a033-b745dd0124ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672893921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2672893921
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.560467540
Short name T564
Test name
Test status
Simulation time 24091978 ps
CPU time 1.21 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:06 PM PDT 24
Peak memory 219036 kb
Host smart-5c57f0e3-9518-4f2d-a941-53cb832aaf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560467540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.560467540
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3962297633
Short name T524
Test name
Test status
Simulation time 68935485 ps
CPU time 1.25 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 217620 kb
Host smart-37fff66e-1efe-45e3-a4a2-4c081d8e1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962297633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3962297633
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3225171779
Short name T249
Test name
Test status
Simulation time 61338618 ps
CPU time 1.38 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:05 PM PDT 24
Peak memory 222404 kb
Host smart-30b0cbc9-e17e-459f-97b1-aab5b70a4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225171779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3225171779
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.4230790987
Short name T942
Test name
Test status
Simulation time 42451657 ps
CPU time 1.18 seconds
Started Jul 12 06:39:04 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 218876 kb
Host smart-0d33f6d4-eb51-4fe5-bcc3-093983616d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230790987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4230790987
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1760145007
Short name T93
Test name
Test status
Simulation time 24575483 ps
CPU time 1.21 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219640 kb
Host smart-32eb987c-66df-47ee-bfd1-bfbf5ad469e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760145007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1760145007
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2373819216
Short name T377
Test name
Test status
Simulation time 49997368 ps
CPU time 1.29 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:10 PM PDT 24
Peak memory 219456 kb
Host smart-7359c88d-5aaf-4bb2-b930-fed23bf32926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373819216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2373819216
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.4143894359
Short name T325
Test name
Test status
Simulation time 39832958 ps
CPU time 1.25 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 220256 kb
Host smart-e482429d-d9f5-4aa3-916d-82f19c809697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143894359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.4143894359
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3023280964
Short name T281
Test name
Test status
Simulation time 39105622 ps
CPU time 1.18 seconds
Started Jul 12 06:39:04 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 215604 kb
Host smart-57f3e044-fa36-417d-8963-afb62de247ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023280964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3023280964
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1278306741
Short name T601
Test name
Test status
Simulation time 50826726 ps
CPU time 1.24 seconds
Started Jul 12 06:39:04 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 215960 kb
Host smart-5e6dd247-e168-48ee-804e-e3d16aacf21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278306741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1278306741
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3211916639
Short name T723
Test name
Test status
Simulation time 80781132 ps
CPU time 2.84 seconds
Started Jul 12 06:39:06 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 220392 kb
Host smart-66b9037b-2114-4d0e-97d3-421db8794b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211916639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3211916639
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1176094324
Short name T895
Test name
Test status
Simulation time 91823987 ps
CPU time 1.23 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:07 PM PDT 24
Peak memory 221852 kb
Host smart-1b07681f-b069-4e43-b3e5-f1ece1ba15f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176094324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1176094324
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3454278959
Short name T449
Test name
Test status
Simulation time 46541969 ps
CPU time 1.19 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219764 kb
Host smart-8cb8eb29-2f3e-4188-ac03-8b79ff729f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454278959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3454278959
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3034399176
Short name T187
Test name
Test status
Simulation time 39178234 ps
CPU time 1.06 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 220304 kb
Host smart-85d81b0a-5244-4d2f-97a4-3aadf0a6194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034399176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3034399176
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4176450950
Short name T401
Test name
Test status
Simulation time 41814911 ps
CPU time 0.85 seconds
Started Jul 12 06:37:16 PM PDT 24
Finished Jul 12 06:37:21 PM PDT 24
Peak memory 215444 kb
Host smart-115e5d2a-a0f7-440e-a9c8-e85643aac310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176450950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4176450950
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.582878926
Short name T811
Test name
Test status
Simulation time 22473822 ps
CPU time 0.87 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 216488 kb
Host smart-6b630845-ee08-44f2-95c4-736ee280a0bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582878926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.582878926
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2053480864
Short name T70
Test name
Test status
Simulation time 118986048 ps
CPU time 1.21 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 220048 kb
Host smart-eb50262b-71c3-4a9d-b5c8-2397ffb392b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053480864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2053480864
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3557481087
Short name T204
Test name
Test status
Simulation time 21273709 ps
CPU time 0.9 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 218400 kb
Host smart-c917b15a-35ce-4709-bcdd-dce5218d1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557481087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3557481087
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3606607883
Short name T337
Test name
Test status
Simulation time 37956945 ps
CPU time 1.35 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 215656 kb
Host smart-5c53d952-3616-498f-a878-d04dd7284eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606607883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3606607883
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2105147015
Short name T381
Test name
Test status
Simulation time 23135940 ps
CPU time 1.16 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 215940 kb
Host smart-aede2952-bfb7-4793-9b5c-a7006375a4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105147015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2105147015
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3891062042
Short name T353
Test name
Test status
Simulation time 113641951 ps
CPU time 0.97 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 215396 kb
Host smart-cea1a4af-5d71-412c-a5a8-d202f10d9254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891062042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3891062042
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1078560396
Short name T66
Test name
Test status
Simulation time 722041286 ps
CPU time 4.35 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:28 PM PDT 24
Peak memory 217692 kb
Host smart-b7c9de49-1bd0-4e11-855c-248e9c4a1eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078560396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1078560396
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2872999929
Short name T230
Test name
Test status
Simulation time 38816973869 ps
CPU time 931.33 seconds
Started Jul 12 06:37:23 PM PDT 24
Finished Jul 12 06:52:57 PM PDT 24
Peak memory 224048 kb
Host smart-e20f0cda-c9a6-4ca3-918b-1727299a4d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872999929 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2872999929
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1258850499
Short name T220
Test name
Test status
Simulation time 40760684 ps
CPU time 1.24 seconds
Started Jul 12 06:39:05 PM PDT 24
Finished Jul 12 06:39:10 PM PDT 24
Peak memory 219424 kb
Host smart-2e4dd863-a4f5-42bd-9431-d38ad6ed84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258850499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1258850499
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.4114343352
Short name T619
Test name
Test status
Simulation time 48926606 ps
CPU time 1.23 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 217788 kb
Host smart-c61b37ff-abc1-46f7-8adf-8243c3bcfbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114343352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4114343352
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2643739692
Short name T272
Test name
Test status
Simulation time 30716827 ps
CPU time 1.3 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 215992 kb
Host smart-e2133c13-7224-42aa-9f5c-c8cf8613a8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643739692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2643739692
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.160391471
Short name T345
Test name
Test status
Simulation time 66181465 ps
CPU time 1.61 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:03 PM PDT 24
Peak memory 218668 kb
Host smart-9c4ac6a4-69cb-4ca5-91df-28a1abfe6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160391471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.160391471
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3630196968
Short name T248
Test name
Test status
Simulation time 92603130 ps
CPU time 1.21 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:08 PM PDT 24
Peak memory 220716 kb
Host smart-cfe1b6b7-4828-46ff-ba43-14aaaf79d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630196968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3630196968
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2149692534
Short name T469
Test name
Test status
Simulation time 192559521 ps
CPU time 0.92 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 217824 kb
Host smart-424000f0-b2ea-41c4-9f7c-6173f7f0da5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149692534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2149692534
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3109713272
Short name T788
Test name
Test status
Simulation time 37785054 ps
CPU time 1.13 seconds
Started Jul 12 06:39:01 PM PDT 24
Finished Jul 12 06:39:05 PM PDT 24
Peak memory 220092 kb
Host smart-2261123b-cf54-49b5-b626-39f787301791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109713272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3109713272
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1746296165
Short name T312
Test name
Test status
Simulation time 29567057 ps
CPU time 1.2 seconds
Started Jul 12 06:39:02 PM PDT 24
Finished Jul 12 06:39:07 PM PDT 24
Peak memory 218616 kb
Host smart-40068e1f-5252-4d41-875e-db328f4466b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746296165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1746296165
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1788824173
Short name T384
Test name
Test status
Simulation time 86040605 ps
CPU time 2.43 seconds
Started Jul 12 06:39:03 PM PDT 24
Finished Jul 12 06:39:09 PM PDT 24
Peak memory 217860 kb
Host smart-184d6d31-9a81-475e-9e35-4ab09dabfbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788824173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1788824173
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.991587392
Short name T630
Test name
Test status
Simulation time 89483272 ps
CPU time 1.15 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219092 kb
Host smart-bec716a1-81aa-4d0e-bffb-7f5581700ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991587392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.991587392
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.4159663819
Short name T882
Test name
Test status
Simulation time 30162541 ps
CPU time 1.29 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 219012 kb
Host smart-96514510-1162-4a27-8c71-74c546e934e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159663819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.4159663819
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.703670691
Short name T726
Test name
Test status
Simulation time 158826852 ps
CPU time 1.01 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:13 PM PDT 24
Peak memory 217688 kb
Host smart-145ec23f-73f9-4c9d-8ecb-fde28a7974eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703670691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.703670691
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3929191534
Short name T145
Test name
Test status
Simulation time 27508218 ps
CPU time 1.12 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:11 PM PDT 24
Peak memory 218828 kb
Host smart-39479fc1-d872-4bd2-bc8e-4ef6238f6698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929191534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3929191534
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3445193523
Short name T22
Test name
Test status
Simulation time 389031509 ps
CPU time 1.65 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:13 PM PDT 24
Peak memory 220340 kb
Host smart-55432fbf-2507-4b2d-bfa6-0994de36cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445193523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3445193523
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3035652317
Short name T424
Test name
Test status
Simulation time 45663984 ps
CPU time 1.1 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 220016 kb
Host smart-7524aade-9e64-4430-9966-31f21273f6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035652317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3035652317
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2461448656
Short name T804
Test name
Test status
Simulation time 40561554 ps
CPU time 1.43 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 217596 kb
Host smart-c4316d30-b27a-4cbb-a698-587e52506a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461448656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2461448656
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.847751375
Short name T116
Test name
Test status
Simulation time 66859770 ps
CPU time 1.12 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219948 kb
Host smart-32b328be-11a9-4e18-8db1-2528b473bad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847751375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.847751375
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2809713565
Short name T334
Test name
Test status
Simulation time 59773947 ps
CPU time 1.43 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 218952 kb
Host smart-1b073d82-9f5c-43bc-80e8-6601a3ac17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809713565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2809713565
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1473266773
Short name T95
Test name
Test status
Simulation time 53399004 ps
CPU time 1.27 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 221020 kb
Host smart-bd9378c7-bce5-4db3-8711-9a17b595fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473266773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1473266773
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2777697364
Short name T949
Test name
Test status
Simulation time 17265979 ps
CPU time 0.94 seconds
Started Jul 12 06:37:16 PM PDT 24
Finished Jul 12 06:37:21 PM PDT 24
Peak memory 215248 kb
Host smart-0532dea0-a195-4704-b1f0-0aae0d55b2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777697364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2777697364
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2629980527
Short name T192
Test name
Test status
Simulation time 18984027 ps
CPU time 0.96 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 216700 kb
Host smart-e5b03933-ed5a-463a-ae9c-60313654aa60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629980527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2629980527
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2024277419
Short name T410
Test name
Test status
Simulation time 349201510 ps
CPU time 1.18 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 217088 kb
Host smart-c187cd80-4684-445d-90ff-2d77273562ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024277419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2024277419
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3020172027
Short name T144
Test name
Test status
Simulation time 23572683 ps
CPU time 1.03 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 224276 kb
Host smart-3f34d70c-371a-4109-a1f8-2fb8ba57a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020172027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3020172027
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2796068129
Short name T661
Test name
Test status
Simulation time 58917644 ps
CPU time 1.31 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 220204 kb
Host smart-ca1023be-efd5-4a70-ae74-ce87b64e5ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796068129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2796068129
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.78254551
Short name T550
Test name
Test status
Simulation time 15527929 ps
CPU time 0.97 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 215596 kb
Host smart-5eba4a9a-b083-4d8e-835e-74588b96694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78254551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.78254551
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1335533986
Short name T809
Test name
Test status
Simulation time 225890856 ps
CPU time 1.88 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 217520 kb
Host smart-ab359907-426f-41ab-956e-93abf4946bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335533986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1335533986
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3082002728
Short name T232
Test name
Test status
Simulation time 21991972603 ps
CPU time 512.54 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:45:54 PM PDT 24
Peak memory 223964 kb
Host smart-21fc413f-37fb-41bb-ad42-a177dc0e32fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082002728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3082002728
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3271112168
Short name T271
Test name
Test status
Simulation time 27828477 ps
CPU time 1.19 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219008 kb
Host smart-b24b1275-7f0b-424a-a0af-5e8748f857cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271112168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3271112168
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.4051509306
Short name T523
Test name
Test status
Simulation time 124968972 ps
CPU time 1.42 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:13 PM PDT 24
Peak memory 219020 kb
Host smart-a24039aa-1298-4146-8903-8132d9cc1e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051509306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4051509306
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1142164060
Short name T147
Test name
Test status
Simulation time 25553216 ps
CPU time 1.1 seconds
Started Jul 12 06:39:11 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 218692 kb
Host smart-417a5082-8bff-4156-b15e-07d5de484e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142164060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1142164060
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.4025952597
Short name T391
Test name
Test status
Simulation time 27354739 ps
CPU time 1.27 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 217444 kb
Host smart-001d5c47-ce99-4af5-bab9-27c31520ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025952597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4025952597
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1919986056
Short name T985
Test name
Test status
Simulation time 106950711 ps
CPU time 1.08 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 218840 kb
Host smart-8dd890f7-3cc1-4f75-8e61-746f602d9a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919986056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1919986056
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3280043890
Short name T605
Test name
Test status
Simulation time 82509886 ps
CPU time 1.2 seconds
Started Jul 12 06:39:17 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217640 kb
Host smart-abbdad3b-3b47-499a-8e05-92d7f75e0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280043890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3280043890
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2123586203
Short name T634
Test name
Test status
Simulation time 63196796 ps
CPU time 1.13 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 219120 kb
Host smart-9a75db2c-995c-402d-a658-1f4cd7f48cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123586203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2123586203
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2026852413
Short name T772
Test name
Test status
Simulation time 45992268 ps
CPU time 1.52 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 218924 kb
Host smart-3cbefe29-ead3-4522-a28a-300fa29dd653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026852413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2026852413
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.73763946
Short name T416
Test name
Test status
Simulation time 32945121 ps
CPU time 1.2 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 220180 kb
Host smart-6b928b58-eb97-4527-a570-a54519ab5abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73763946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.73763946
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2106056765
Short name T974
Test name
Test status
Simulation time 74169496 ps
CPU time 1.28 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:13 PM PDT 24
Peak memory 217660 kb
Host smart-8db6ccc0-09a7-4c91-aadc-ab379f513eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106056765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2106056765
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3942765934
Short name T461
Test name
Test status
Simulation time 27420582 ps
CPU time 1.21 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 220124 kb
Host smart-744060f5-b719-41a3-b90d-c4d645fed8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942765934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3942765934
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3410286648
Short name T731
Test name
Test status
Simulation time 124879672 ps
CPU time 1.62 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 219036 kb
Host smart-c864b358-015f-4b3d-b7be-25df0bc7b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410286648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3410286648
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1483157731
Short name T740
Test name
Test status
Simulation time 65806726 ps
CPU time 1.7 seconds
Started Jul 12 06:39:12 PM PDT 24
Finished Jul 12 06:39:17 PM PDT 24
Peak memory 219184 kb
Host smart-3af994a2-a6df-42ca-afca-4fb39b0ae193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483157731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1483157731
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.4292230233
Short name T130
Test name
Test status
Simulation time 72290148 ps
CPU time 1.15 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 219968 kb
Host smart-cbc61ae4-a07c-4cc3-8176-d57e3e11af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292230233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4292230233
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.986668906
Short name T602
Test name
Test status
Simulation time 80850895 ps
CPU time 1.04 seconds
Started Jul 12 06:39:11 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 217480 kb
Host smart-bd726b32-a702-44d6-a050-e0241cd2f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986668906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.986668906
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1732910023
Short name T199
Test name
Test status
Simulation time 75687632 ps
CPU time 1.17 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 219492 kb
Host smart-78d30654-f9b8-4195-a600-b2d96df2e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732910023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1732910023
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2968342285
Short name T314
Test name
Test status
Simulation time 100432950 ps
CPU time 1.41 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 219220 kb
Host smart-452275e4-16c4-4aef-87b8-0c2ce5a7afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968342285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2968342285
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.948004759
Short name T146
Test name
Test status
Simulation time 164284997 ps
CPU time 1.13 seconds
Started Jul 12 06:39:06 PM PDT 24
Finished Jul 12 06:39:10 PM PDT 24
Peak memory 221064 kb
Host smart-45b44a29-6b77-496c-bd46-74582aba5173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948004759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.948004759
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3122165698
Short name T918
Test name
Test status
Simulation time 54610076 ps
CPU time 1.98 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 218928 kb
Host smart-504ba256-7a25-47c6-8ec2-b3e551d52e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122165698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3122165698
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.622272223
Short name T322
Test name
Test status
Simulation time 22325631 ps
CPU time 1.09 seconds
Started Jul 12 06:36:48 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 220216 kb
Host smart-9198f463-04ac-4f23-9098-b106fd7aaf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622272223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.622272223
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1474363546
Short name T373
Test name
Test status
Simulation time 16333596 ps
CPU time 0.97 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 215432 kb
Host smart-02fbf991-ff1f-4c9a-9ebe-7fe9440c93cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474363546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1474363546
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2617854992
Short name T214
Test name
Test status
Simulation time 61004471 ps
CPU time 0.8 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 216572 kb
Host smart-3e3fd949-92ec-4acc-8e43-9722814f7b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617854992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2617854992
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1088217796
Short name T903
Test name
Test status
Simulation time 35901101 ps
CPU time 1.21 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 217428 kb
Host smart-6ba5a86f-fe61-4a55-ab10-e700c4c2f17d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088217796 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1088217796
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.785096525
Short name T168
Test name
Test status
Simulation time 19974771 ps
CPU time 1.05 seconds
Started Jul 12 06:36:48 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 218864 kb
Host smart-6ec03d4c-c063-4f2c-94e7-3475dafb9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785096525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.785096525
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3208344610
Short name T292
Test name
Test status
Simulation time 41333207 ps
CPU time 1.41 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 218792 kb
Host smart-2fa18911-834d-46fe-b0fb-4e12ff4eeeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208344610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3208344610
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1942635177
Short name T917
Test name
Test status
Simulation time 22532644 ps
CPU time 1.02 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:55 PM PDT 24
Peak memory 215872 kb
Host smart-d930a63e-e3c2-405c-bd52-77e1bafa5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942635177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1942635177
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2475965488
Short name T64
Test name
Test status
Simulation time 1390559408 ps
CPU time 20.35 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:37:07 PM PDT 24
Peak memory 236508 kb
Host smart-76235f7f-c2f2-4ef9-9d79-5d633e3f587b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475965488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2475965488
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.809626919
Short name T963
Test name
Test status
Simulation time 30897284 ps
CPU time 0.97 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 215560 kb
Host smart-2f834657-59b3-4770-a03a-4c6a0a109a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809626919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.809626919
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1564738718
Short name T238
Test name
Test status
Simulation time 181929511 ps
CPU time 2.3 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:47 PM PDT 24
Peak memory 217512 kb
Host smart-f1fe396b-9502-4b37-9b4d-95b310f1e306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564738718 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1564738718
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1185623545
Short name T477
Test name
Test status
Simulation time 44372344617 ps
CPU time 444.85 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:44:08 PM PDT 24
Peak memory 218116 kb
Host smart-575a217c-b010-4235-8b2b-437c5358146f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185623545 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1185623545
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.924956955
Short name T152
Test name
Test status
Simulation time 60336091 ps
CPU time 1.07 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 218924 kb
Host smart-8d163ca0-dd53-4173-818c-d2af26b70958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924956955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.924956955
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.361301116
Short name T406
Test name
Test status
Simulation time 33420128 ps
CPU time 0.82 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 206760 kb
Host smart-23a6d686-528d-4af9-b5a8-30918bec7aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361301116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.361301116
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.337307213
Short name T412
Test name
Test status
Simulation time 61160220 ps
CPU time 1.03 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 218736 kb
Host smart-2206d71c-3628-4138-a626-c813d498deff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337307213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.337307213
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3748770817
Short name T399
Test name
Test status
Simulation time 46737807 ps
CPU time 0.87 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 218472 kb
Host smart-2a075e86-85c2-4b72-8f04-6f54bb0dce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748770817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3748770817
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3151699332
Short name T970
Test name
Test status
Simulation time 71617514 ps
CPU time 1.23 seconds
Started Jul 12 06:37:17 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 217528 kb
Host smart-8e87f594-db07-49b7-896d-ffbcadab39d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151699332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3151699332
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.673852963
Short name T98
Test name
Test status
Simulation time 29825089 ps
CPU time 0.84 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 215980 kb
Host smart-def0b9fe-a5f9-4bfb-af31-1e7406b953ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673852963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.673852963
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1488868014
Short name T61
Test name
Test status
Simulation time 18397435 ps
CPU time 1.02 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:25 PM PDT 24
Peak memory 215584 kb
Host smart-7536e9f6-7539-42f7-a561-a105ef98dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488868014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1488868014
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2157075646
Short name T714
Test name
Test status
Simulation time 600008702 ps
CPU time 6.37 seconds
Started Jul 12 06:37:17 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 217468 kb
Host smart-09c11afb-7be4-4bab-ad9f-4c094bfb1033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157075646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2157075646
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.82527383
Short name T226
Test name
Test status
Simulation time 14895695704 ps
CPU time 331.96 seconds
Started Jul 12 06:37:16 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 217832 kb
Host smart-2313af10-b295-4a42-83bd-e133b936d42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82527383 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.82527383
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.652107674
Short name T417
Test name
Test status
Simulation time 30620395 ps
CPU time 1.02 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 220052 kb
Host smart-26df14b7-d7e7-4805-a55b-0890d45b0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652107674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.652107674
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2461970206
Short name T937
Test name
Test status
Simulation time 63579245 ps
CPU time 1.28 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 217996 kb
Host smart-2c64e1ec-8aed-4760-a518-2ac6848c17ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461970206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2461970206
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.757227454
Short name T727
Test name
Test status
Simulation time 67114376 ps
CPU time 1.47 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 220200 kb
Host smart-91eea160-9714-4a48-84f3-23fce91fd57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757227454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.757227454
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1639913527
Short name T407
Test name
Test status
Simulation time 44333702 ps
CPU time 1.14 seconds
Started Jul 12 06:39:17 PM PDT 24
Finished Jul 12 06:39:22 PM PDT 24
Peak memory 217732 kb
Host smart-7face700-6089-4346-954f-0dddd34fa987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639913527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1639913527
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.128155446
Short name T388
Test name
Test status
Simulation time 43507886 ps
CPU time 1.46 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 218832 kb
Host smart-cf06e22f-47c0-4f74-a36b-820056dad178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128155446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.128155446
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1868949728
Short name T354
Test name
Test status
Simulation time 309319356 ps
CPU time 1.12 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 217596 kb
Host smart-213a2791-dee0-4f7d-81f5-d5d4d5d84f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868949728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1868949728
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3079611888
Short name T683
Test name
Test status
Simulation time 82596872 ps
CPU time 1 seconds
Started Jul 12 06:39:06 PM PDT 24
Finished Jul 12 06:39:10 PM PDT 24
Peak memory 217640 kb
Host smart-00f43585-d4da-4c7e-964d-939bf9e34eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079611888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3079611888
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.279872565
Short name T45
Test name
Test status
Simulation time 60295784 ps
CPU time 1.34 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 217836 kb
Host smart-5374376b-871c-4750-a5ad-9f4de5fe275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279872565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.279872565
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.16000169
Short name T753
Test name
Test status
Simulation time 43626448 ps
CPU time 1.47 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 218628 kb
Host smart-395771be-850f-43e6-a8f3-ef9c5651df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16000169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.16000169
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1810269150
Short name T162
Test name
Test status
Simulation time 255305879 ps
CPU time 1.16 seconds
Started Jul 12 06:37:17 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 220904 kb
Host smart-d31a2792-b6f6-421c-a53d-565e80ace8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810269150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1810269150
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1188203158
Short name T355
Test name
Test status
Simulation time 17835401 ps
CPU time 1.03 seconds
Started Jul 12 06:37:20 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 215392 kb
Host smart-92cff77e-d9d4-45ca-a42d-6aa005307009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188203158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1188203158
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2763454054
Short name T632
Test name
Test status
Simulation time 139346383 ps
CPU time 1.09 seconds
Started Jul 12 06:37:27 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 218660 kb
Host smart-a8f64dfa-2327-4aad-aad8-c243444bcbc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763454054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2763454054
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1740786574
Short name T818
Test name
Test status
Simulation time 25372407 ps
CPU time 1.12 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:25 PM PDT 24
Peak memory 219812 kb
Host smart-f5fafb0e-006c-4139-9c04-d819d2d25d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740786574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1740786574
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3878268432
Short name T558
Test name
Test status
Simulation time 50992627 ps
CPU time 1.36 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 217620 kb
Host smart-446d5672-cd2e-4318-93a7-63797a1b5e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878268432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3878268432
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3076555089
Short name T475
Test name
Test status
Simulation time 26825423 ps
CPU time 0.95 seconds
Started Jul 12 06:37:21 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 216112 kb
Host smart-c67ad488-fa25-493c-9e17-cd67179ec256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076555089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3076555089
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.783683492
Short name T722
Test name
Test status
Simulation time 23238844 ps
CPU time 1.08 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 215596 kb
Host smart-b74f35ec-5743-400d-9eaa-93975a0175f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783683492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.783683492
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2446938092
Short name T586
Test name
Test status
Simulation time 768466687 ps
CPU time 4.62 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 217644 kb
Host smart-480af975-d359-43b0-bb65-763257bb2985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446938092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2446938092
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.52495402
Short name T41
Test name
Test status
Simulation time 332426416889 ps
CPU time 874.87 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:51:56 PM PDT 24
Peak memory 224012 kb
Host smart-d96cefe9-b963-45a9-b82f-88fa7d7ad634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52495402 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.52495402
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.97883523
Short name T911
Test name
Test status
Simulation time 119447438 ps
CPU time 1.67 seconds
Started Jul 12 06:39:06 PM PDT 24
Finished Jul 12 06:39:11 PM PDT 24
Peak memory 217620 kb
Host smart-335881aa-69db-4f3e-98d3-71494593974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97883523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.97883523
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2159268014
Short name T482
Test name
Test status
Simulation time 60895804 ps
CPU time 1.62 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 219100 kb
Host smart-a7ed8eac-362b-4141-8fcd-789ca2bf0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159268014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2159268014
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.888334707
Short name T96
Test name
Test status
Simulation time 83954091 ps
CPU time 2.63 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:30 PM PDT 24
Peak memory 218836 kb
Host smart-50b8c2ee-23f1-4974-8a5d-939bc13297bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888334707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.888334707
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2039246857
Short name T827
Test name
Test status
Simulation time 104370879 ps
CPU time 1.2 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 217480 kb
Host smart-931dca76-91fe-4790-918b-0bd6cb307dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039246857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2039246857
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3516471916
Short name T939
Test name
Test status
Simulation time 71974421 ps
CPU time 1.39 seconds
Started Jul 12 06:39:07 PM PDT 24
Finished Jul 12 06:39:12 PM PDT 24
Peak memory 217596 kb
Host smart-a27c03ac-8a68-45b8-b7a7-3f50a6e421ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516471916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3516471916
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3098092075
Short name T782
Test name
Test status
Simulation time 41980150 ps
CPU time 1.43 seconds
Started Jul 12 06:39:11 PM PDT 24
Finished Jul 12 06:39:16 PM PDT 24
Peak memory 220088 kb
Host smart-7925f16a-35ec-4186-825f-a79eacebd274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098092075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3098092075
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1830950909
Short name T86
Test name
Test status
Simulation time 171919399 ps
CPU time 1.29 seconds
Started Jul 12 06:39:08 PM PDT 24
Finished Jul 12 06:39:13 PM PDT 24
Peak memory 219592 kb
Host smart-2d7e1aa8-c337-4963-9e87-4fc9dd57abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830950909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1830950909
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3052499119
Short name T571
Test name
Test status
Simulation time 56820630 ps
CPU time 1.2 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 218556 kb
Host smart-4a0b1316-de76-4afc-a7c1-6a968cdb8c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052499119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3052499119
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.4129809154
Short name T598
Test name
Test status
Simulation time 48683007 ps
CPU time 1.51 seconds
Started Jul 12 06:39:12 PM PDT 24
Finished Jul 12 06:39:17 PM PDT 24
Peak memory 218704 kb
Host smart-ecd904b3-01d1-4810-bdc1-a0c4cda55479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129809154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.4129809154
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.925060331
Short name T843
Test name
Test status
Simulation time 112587682 ps
CPU time 2.8 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:17 PM PDT 24
Peak memory 218848 kb
Host smart-850307cf-6922-499b-b41f-5e45a340d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925060331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.925060331
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.139012321
Short name T766
Test name
Test status
Simulation time 43468553 ps
CPU time 1.25 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 216004 kb
Host smart-10f2c0a7-ff17-4fa7-8b21-4ef51bcb6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139012321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.139012321
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3519701880
Short name T603
Test name
Test status
Simulation time 33236893 ps
CPU time 0.86 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:23 PM PDT 24
Peak memory 206608 kb
Host smart-29928b63-b32d-4854-bef1-a133589cff97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519701880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3519701880
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.658041171
Short name T101
Test name
Test status
Simulation time 19756828 ps
CPU time 1.06 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 219896 kb
Host smart-a05c6965-e299-4192-b4b3-d2dd367257a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658041171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.658041171
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2902422857
Short name T881
Test name
Test status
Simulation time 45525797 ps
CPU time 1.58 seconds
Started Jul 12 06:37:23 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 218872 kb
Host smart-6147f345-7d34-4e34-be53-4346cf09c478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902422857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2902422857
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1984691100
Short name T36
Test name
Test status
Simulation time 36611444 ps
CPU time 0.91 seconds
Started Jul 12 06:37:17 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 215956 kb
Host smart-eda5a0e3-d970-4844-91a3-f31ed51ca052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984691100 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1984691100
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.78777411
Short name T641
Test name
Test status
Simulation time 15749573 ps
CPU time 1.01 seconds
Started Jul 12 06:37:18 PM PDT 24
Finished Jul 12 06:37:22 PM PDT 24
Peak memory 215676 kb
Host smart-692eb3b0-8956-4b54-aac4-7143fc5929fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78777411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.78777411
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1536966616
Short name T849
Test name
Test status
Simulation time 120307472 ps
CPU time 1.76 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 215608 kb
Host smart-7f527c52-02e6-4a79-8293-5f80980f8701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536966616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1536966616
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1684588415
Short name T77
Test name
Test status
Simulation time 158998649082 ps
CPU time 1948.66 seconds
Started Jul 12 06:37:19 PM PDT 24
Finished Jul 12 07:09:51 PM PDT 24
Peak memory 226780 kb
Host smart-aa93258d-d588-44d8-8a56-dba2262856bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684588415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1684588415
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.701578581
Short name T512
Test name
Test status
Simulation time 77199152 ps
CPU time 1.13 seconds
Started Jul 12 06:39:10 PM PDT 24
Finished Jul 12 06:39:15 PM PDT 24
Peak memory 217680 kb
Host smart-acd8cb8d-8146-4fd6-bec9-43163554659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701578581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.701578581
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4140960195
Short name T398
Test name
Test status
Simulation time 73555957 ps
CPU time 1.13 seconds
Started Jul 12 06:39:09 PM PDT 24
Finished Jul 12 06:39:14 PM PDT 24
Peak memory 217556 kb
Host smart-603d3b2b-5e11-4d98-81f1-65909badc4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140960195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4140960195
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2240339932
Short name T347
Test name
Test status
Simulation time 98511512 ps
CPU time 1.33 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 217632 kb
Host smart-cee3fbd6-6a2b-4981-9308-a9e854237f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240339932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2240339932
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.640700274
Short name T578
Test name
Test status
Simulation time 98206458 ps
CPU time 1.23 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:20 PM PDT 24
Peak memory 217776 kb
Host smart-5fa4b664-291c-4bff-b350-a2606b84922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640700274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.640700274
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.366226092
Short name T352
Test name
Test status
Simulation time 57895661 ps
CPU time 2.06 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217936 kb
Host smart-8210e3a8-dede-4337-83da-81f01c6a21d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366226092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.366226092
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2594880836
Short name T375
Test name
Test status
Simulation time 97971344 ps
CPU time 1.56 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 219140 kb
Host smart-35e5ca5a-8c7d-492b-8f4e-9a5c3faf28ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594880836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2594880836
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.277750931
Short name T368
Test name
Test status
Simulation time 69428568 ps
CPU time 1.3 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 218992 kb
Host smart-d6339e7d-96b5-4ff3-ad93-237a1b95b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277750931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.277750931
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.695417113
Short name T695
Test name
Test status
Simulation time 207082321 ps
CPU time 0.96 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:18 PM PDT 24
Peak memory 217656 kb
Host smart-ed894d8c-2ca5-4422-9a8b-df6ae1a44774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695417113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.695417113
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3576663004
Short name T283
Test name
Test status
Simulation time 56066987 ps
CPU time 1.17 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 217736 kb
Host smart-59ec6adc-41f2-4a59-b428-f02c3118c177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576663004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3576663004
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4154133742
Short name T855
Test name
Test status
Simulation time 73153545 ps
CPU time 1.1 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 220304 kb
Host smart-937d447b-fb1a-44b6-8f43-72d8c8e4c7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154133742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4154133742
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2422861222
Short name T60
Test name
Test status
Simulation time 19884872 ps
CPU time 1.03 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 207132 kb
Host smart-e02d8dd7-64c2-4b05-9058-f2392f0cb427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422861222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2422861222
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1691780061
Short name T488
Test name
Test status
Simulation time 19857617 ps
CPU time 0.87 seconds
Started Jul 12 06:37:30 PM PDT 24
Finished Jul 12 06:37:32 PM PDT 24
Peak memory 215704 kb
Host smart-618f25d1-730e-4091-a6bd-f1759e1d5407
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691780061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1691780061
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3437554015
Short name T447
Test name
Test status
Simulation time 39237265 ps
CPU time 1.24 seconds
Started Jul 12 06:37:29 PM PDT 24
Finished Jul 12 06:37:32 PM PDT 24
Peak memory 218768 kb
Host smart-17ae1092-d83c-4275-a202-e0d810bf8942
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437554015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3437554015
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3614949993
Short name T993
Test name
Test status
Simulation time 47606299 ps
CPU time 1.11 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 220744 kb
Host smart-41b79437-27cd-4caa-8ca0-6bb23f707b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614949993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3614949993
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.298049784
Short name T521
Test name
Test status
Simulation time 115675869 ps
CPU time 1.32 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 220092 kb
Host smart-84fb01f6-61fd-445e-be00-50620099e741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298049784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.298049784
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3469248549
Short name T745
Test name
Test status
Simulation time 20019545 ps
CPU time 1.06 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 216160 kb
Host smart-d31a3c32-2633-4ef0-850c-82d1f56771e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469248549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3469248549
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3004093760
Short name T716
Test name
Test status
Simulation time 16449058 ps
CPU time 0.97 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 215548 kb
Host smart-797c52bf-3548-491a-9558-55f1789eb771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004093760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3004093760
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.733000010
Short name T438
Test name
Test status
Simulation time 207237472 ps
CPU time 2.55 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 218876 kb
Host smart-bf610476-e55e-4488-ae3b-dac293962d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733000010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.733000010
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4255250820
Short name T677
Test name
Test status
Simulation time 146756248393 ps
CPU time 575.75 seconds
Started Jul 12 06:37:30 PM PDT 24
Finished Jul 12 06:47:07 PM PDT 24
Peak memory 223996 kb
Host smart-87410c63-79ce-42dd-b11b-4b9fa7f219bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255250820 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4255250820
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2555835166
Short name T385
Test name
Test status
Simulation time 231309723 ps
CPU time 1.15 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 217644 kb
Host smart-034d98c8-6467-49cd-91ab-99900b197e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555835166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2555835166
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3823732769
Short name T737
Test name
Test status
Simulation time 255244989 ps
CPU time 1.28 seconds
Started Jul 12 06:39:13 PM PDT 24
Finished Jul 12 06:39:18 PM PDT 24
Peak memory 217776 kb
Host smart-4ce4010a-44aa-4ef0-88ef-81ec1afcad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823732769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3823732769
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2180534514
Short name T336
Test name
Test status
Simulation time 112576291 ps
CPU time 1.67 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:20 PM PDT 24
Peak memory 220500 kb
Host smart-5536ce5a-bbca-440b-99f3-9deb81c3e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180534514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2180534514
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.4173434256
Short name T932
Test name
Test status
Simulation time 67558558 ps
CPU time 1.3 seconds
Started Jul 12 06:39:13 PM PDT 24
Finished Jul 12 06:39:18 PM PDT 24
Peak memory 217688 kb
Host smart-56d54799-f023-4bde-a089-1f6fd6b1f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173434256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.4173434256
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4247240031
Short name T735
Test name
Test status
Simulation time 91038084 ps
CPU time 1.61 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 217788 kb
Host smart-ba71e70c-87be-4da1-9cb1-bda008d0d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247240031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4247240031
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4086572362
Short name T702
Test name
Test status
Simulation time 142306476 ps
CPU time 1.28 seconds
Started Jul 12 06:39:17 PM PDT 24
Finished Jul 12 06:39:22 PM PDT 24
Peak memory 215684 kb
Host smart-b5de0af7-136d-408d-9e5d-73f8f6b9c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086572362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4086572362
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4275967129
Short name T371
Test name
Test status
Simulation time 48312681 ps
CPU time 1.56 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:23 PM PDT 24
Peak memory 218948 kb
Host smart-d14a5316-6841-4e05-b17c-8c58cb63f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275967129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4275967129
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1946684424
Short name T349
Test name
Test status
Simulation time 575859308 ps
CPU time 4.56 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 217808 kb
Host smart-2ba554ac-4e76-4bfa-a513-4ab820ec0183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946684424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1946684424
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2111146567
Short name T423
Test name
Test status
Simulation time 52687294 ps
CPU time 2.04 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217772 kb
Host smart-463a4379-c248-4f7d-a301-56bfe6b56775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111146567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2111146567
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3049888846
Short name T67
Test name
Test status
Simulation time 125970445 ps
CPU time 1.38 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 219264 kb
Host smart-81328a15-39c8-48da-a485-2810f1b79a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049888846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3049888846
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3636781249
Short name T508
Test name
Test status
Simulation time 91434512 ps
CPU time 1.19 seconds
Started Jul 12 06:37:25 PM PDT 24
Finished Jul 12 06:37:28 PM PDT 24
Peak memory 219052 kb
Host smart-6e5b1bf6-f177-4ebe-b4bc-e6e11d87ef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636781249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3636781249
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1102987662
Short name T878
Test name
Test status
Simulation time 67253416 ps
CPU time 0.93 seconds
Started Jul 12 06:37:31 PM PDT 24
Finished Jul 12 06:37:33 PM PDT 24
Peak memory 215468 kb
Host smart-a946bdb6-6506-4a25-b900-34961d6887ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102987662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1102987662
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.977530910
Short name T751
Test name
Test status
Simulation time 32072578 ps
CPU time 0.82 seconds
Started Jul 12 06:37:27 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 216224 kb
Host smart-da850053-3377-4b8e-bc7a-a51b6fe45a7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977530910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.977530910
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.557258455
Short name T206
Test name
Test status
Simulation time 33830832 ps
CPU time 1.71 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:31 PM PDT 24
Peak memory 225844 kb
Host smart-0c8c613d-9009-4ed2-8cac-579ef6ad7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557258455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.557258455
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3202200711
Short name T453
Test name
Test status
Simulation time 84823558 ps
CPU time 1.18 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 217700 kb
Host smart-c8c2bbe6-f864-47a6-9236-29814a4f4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202200711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3202200711
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3802064235
Short name T555
Test name
Test status
Simulation time 21813123 ps
CPU time 1.15 seconds
Started Jul 12 06:37:30 PM PDT 24
Finished Jul 12 06:37:32 PM PDT 24
Peak memory 215816 kb
Host smart-2ba87005-e4a4-4cdf-beb5-18612cf399f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802064235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3802064235
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1323745874
Short name T80
Test name
Test status
Simulation time 17148474 ps
CPU time 0.98 seconds
Started Jul 12 06:37:26 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 215600 kb
Host smart-26ae6699-2b53-442a-8e07-19514fc492f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323745874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1323745874
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1206022370
Short name T549
Test name
Test status
Simulation time 993290048 ps
CPU time 3.79 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 217572 kb
Host smart-b3c62f4d-cf86-4b29-aac7-201a0e28fea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206022370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1206022370
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3341378149
Short name T503
Test name
Test status
Simulation time 31677445874 ps
CPU time 771.13 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:50:20 PM PDT 24
Peak memory 224060 kb
Host smart-e8a77413-b4cc-488b-99d6-11830e4208bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341378149 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3341378149
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3923424214
Short name T744
Test name
Test status
Simulation time 27238096 ps
CPU time 1.2 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 217552 kb
Host smart-5cc71e60-517c-47ab-87af-75d7b2926fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923424214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3923424214
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2175037407
Short name T90
Test name
Test status
Simulation time 65558335 ps
CPU time 1.28 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:20 PM PDT 24
Peak memory 217352 kb
Host smart-246ceac9-cd60-45f6-9cc0-7d0a9c194a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175037407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2175037407
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1774143520
Short name T584
Test name
Test status
Simulation time 130873439 ps
CPU time 1.26 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:23 PM PDT 24
Peak memory 217660 kb
Host smart-a1d1f3c8-a1f1-45d8-a392-9fcaf7af9771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774143520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1774143520
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2963522702
Short name T947
Test name
Test status
Simulation time 58881991 ps
CPU time 1.4 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 219924 kb
Host smart-3b541254-98c9-4f5e-833a-a3d7e6a0f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963522702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2963522702
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4017134040
Short name T225
Test name
Test status
Simulation time 2303067922 ps
CPU time 74.37 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 219264 kb
Host smart-4dba473e-394a-4ee3-83d5-20662639d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017134040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4017134040
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1873327671
Short name T379
Test name
Test status
Simulation time 193127073 ps
CPU time 1.12 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:19 PM PDT 24
Peak memory 217744 kb
Host smart-bffc0823-6330-4b7b-9d2f-0efaaf724a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873327671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1873327671
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1080809113
Short name T426
Test name
Test status
Simulation time 102395446 ps
CPU time 1.25 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:23 PM PDT 24
Peak memory 217664 kb
Host smart-be35775b-35f8-4149-b5bc-b3e0fa36a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080809113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1080809113
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1186505275
Short name T652
Test name
Test status
Simulation time 53174633 ps
CPU time 1.27 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 217648 kb
Host smart-20fb5152-a146-4bcf-809a-b510833537d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186505275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1186505275
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2328366279
Short name T83
Test name
Test status
Simulation time 42491916 ps
CPU time 1.78 seconds
Started Jul 12 06:39:12 PM PDT 24
Finished Jul 12 06:39:17 PM PDT 24
Peak memory 218864 kb
Host smart-60432eb6-057b-44d4-8250-03a2ff53eb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328366279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2328366279
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.838763737
Short name T964
Test name
Test status
Simulation time 144976332 ps
CPU time 1.51 seconds
Started Jul 12 06:39:13 PM PDT 24
Finished Jul 12 06:39:17 PM PDT 24
Peak memory 219040 kb
Host smart-50ea7d60-e91f-460d-bcc8-96493a7ed8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838763737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.838763737
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.902483059
Short name T867
Test name
Test status
Simulation time 74969492 ps
CPU time 1.14 seconds
Started Jul 12 06:37:25 PM PDT 24
Finished Jul 12 06:37:28 PM PDT 24
Peak memory 220912 kb
Host smart-5aeb9f39-9e69-4a5f-904c-712192d3d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902483059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.902483059
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2380600327
Short name T403
Test name
Test status
Simulation time 20989331 ps
CPU time 0.99 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 207012 kb
Host smart-cc61ba67-19eb-4c6c-88ed-1b6e75eb0e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380600327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2380600327
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2889083089
Short name T84
Test name
Test status
Simulation time 18818753 ps
CPU time 0.95 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 215708 kb
Host smart-7fec8b2e-6465-47ab-9c95-67e1a03525d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889083089 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2889083089
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.848418811
Short name T648
Test name
Test status
Simulation time 22136843 ps
CPU time 1.02 seconds
Started Jul 12 06:37:27 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 217388 kb
Host smart-52edef5d-761b-4d7b-87ef-cecf81b660cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848418811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.848418811
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4014289076
Short name T114
Test name
Test status
Simulation time 26327458 ps
CPU time 1.19 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:31 PM PDT 24
Peak memory 217684 kb
Host smart-b90adf95-af28-4c15-950a-f24cf39eb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014289076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4014289076
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.69437244
Short name T303
Test name
Test status
Simulation time 56096394 ps
CPU time 1.2 seconds
Started Jul 12 06:37:27 PM PDT 24
Finished Jul 12 06:37:30 PM PDT 24
Peak memory 217692 kb
Host smart-8f032462-7d8e-4df3-ad0d-ca61d4327d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69437244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.69437244
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.424455386
Short name T35
Test name
Test status
Simulation time 23281583 ps
CPU time 1.01 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:31 PM PDT 24
Peak memory 216284 kb
Host smart-bdaa848b-1949-4625-b626-8650fef55396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424455386 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.424455386
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3340963202
Short name T513
Test name
Test status
Simulation time 21454684 ps
CPU time 0.98 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:31 PM PDT 24
Peak memory 215560 kb
Host smart-1bdcbb1f-be8e-4036-8939-268a25dbad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340963202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3340963202
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2609855898
Short name T591
Test name
Test status
Simulation time 1896094549 ps
CPU time 3.62 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:37:33 PM PDT 24
Peak memory 215632 kb
Host smart-237021e2-1ee4-4eee-9330-34943cfdf2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609855898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2609855898
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2451324479
Short name T235
Test name
Test status
Simulation time 250166146501 ps
CPU time 1169.2 seconds
Started Jul 12 06:37:28 PM PDT 24
Finished Jul 12 06:56:59 PM PDT 24
Peak memory 223272 kb
Host smart-becffaaa-a0eb-4e67-a752-d54b3cbb7f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451324479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2451324479
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1054738558
Short name T768
Test name
Test status
Simulation time 63335632 ps
CPU time 1.99 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:30 PM PDT 24
Peak memory 217728 kb
Host smart-d955402e-b519-4855-b5af-2414f62d4338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054738558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1054738558
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.338496329
Short name T395
Test name
Test status
Simulation time 59072921 ps
CPU time 1.37 seconds
Started Jul 12 06:39:14 PM PDT 24
Finished Jul 12 06:39:18 PM PDT 24
Peak memory 219132 kb
Host smart-4c546cac-4feb-4db2-af43-7c0af0c6c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338496329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.338496329
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2069410780
Short name T713
Test name
Test status
Simulation time 57717330 ps
CPU time 1.12 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217300 kb
Host smart-b3fcf8ec-2e2b-48cb-a00c-60cf5d6fb459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069410780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2069410780
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2117071544
Short name T495
Test name
Test status
Simulation time 143561375 ps
CPU time 1.9 seconds
Started Jul 12 06:39:17 PM PDT 24
Finished Jul 12 06:39:22 PM PDT 24
Peak memory 220328 kb
Host smart-992bb3e9-91b7-454f-b508-309d67705448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117071544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2117071544
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.510162502
Short name T419
Test name
Test status
Simulation time 93865005 ps
CPU time 1.43 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 219004 kb
Host smart-9e7d7105-cfcc-49ba-b47c-99bb0ab98dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510162502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.510162502
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1092655285
Short name T499
Test name
Test status
Simulation time 51123150 ps
CPU time 1.58 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 219540 kb
Host smart-eba7cfcc-1a9a-4bd7-987b-6f0b8f522cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092655285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1092655285
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4213471123
Short name T242
Test name
Test status
Simulation time 43815329 ps
CPU time 1.47 seconds
Started Jul 12 06:39:17 PM PDT 24
Finished Jul 12 06:39:22 PM PDT 24
Peak memory 218884 kb
Host smart-c6dea171-652f-4e8b-992c-61089e5e4636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213471123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4213471123
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3853963269
Short name T389
Test name
Test status
Simulation time 85244917 ps
CPU time 1.11 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:20 PM PDT 24
Peak memory 217668 kb
Host smart-aa950539-63bd-48d8-baf9-716b5fb9ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853963269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3853963269
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1443497033
Short name T566
Test name
Test status
Simulation time 38929541 ps
CPU time 1.55 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 218968 kb
Host smart-bd93eaa8-1393-4b64-9262-0047c52a826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443497033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1443497033
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1151087771
Short name T687
Test name
Test status
Simulation time 121214552 ps
CPU time 1.43 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217816 kb
Host smart-115b1b53-5d98-4e75-914b-36cd19387544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151087771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1151087771
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.307658719
Short name T861
Test name
Test status
Simulation time 27358822 ps
CPU time 1.23 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 219884 kb
Host smart-a70c3f8c-9056-415d-8f98-67850001ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307658719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.307658719
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.657744097
Short name T587
Test name
Test status
Simulation time 50885328 ps
CPU time 0.86 seconds
Started Jul 12 06:39:00 PM PDT 24
Finished Jul 12 06:39:01 PM PDT 24
Peak memory 207016 kb
Host smart-6a4674fc-8d4c-4c8d-bc63-3314d1b3ae81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657744097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.657744097
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2501129324
Short name T800
Test name
Test status
Simulation time 15132232 ps
CPU time 0.86 seconds
Started Jul 12 06:37:37 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 216228 kb
Host smart-cb2caa09-1492-41d8-b86c-16d18bc9a16c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501129324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2501129324
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1351295638
Short name T140
Test name
Test status
Simulation time 73604362 ps
CPU time 0.99 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 218732 kb
Host smart-b2b75227-315b-430d-8561-e5160ae8e797
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351295638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1351295638
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3545387212
Short name T56
Test name
Test status
Simulation time 19230087 ps
CPU time 1.19 seconds
Started Jul 12 06:37:30 PM PDT 24
Finished Jul 12 06:37:32 PM PDT 24
Peak memory 224336 kb
Host smart-5115172a-5199-40ab-82ff-8e90de8bfbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545387212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3545387212
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.136756120
Short name T493
Test name
Test status
Simulation time 40120918 ps
CPU time 1.2 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 217688 kb
Host smart-a8b902a7-0d97-4a28-a721-3b8a8976cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136756120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.136756120
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2599643190
Short name T854
Test name
Test status
Simulation time 21257476 ps
CPU time 1.21 seconds
Started Jul 12 06:37:35 PM PDT 24
Finished Jul 12 06:37:37 PM PDT 24
Peak memory 224304 kb
Host smart-b1e6d378-9681-421b-88f4-9465d54eadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599643190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2599643190
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.963194850
Short name T454
Test name
Test status
Simulation time 25953700 ps
CPU time 0.95 seconds
Started Jul 12 06:37:24 PM PDT 24
Finished Jul 12 06:37:27 PM PDT 24
Peak memory 215612 kb
Host smart-34fac94e-9053-4b38-a874-4364ef209402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963194850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.963194850
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1020280001
Short name T338
Test name
Test status
Simulation time 288650361 ps
CPU time 2.26 seconds
Started Jul 12 06:37:25 PM PDT 24
Finished Jul 12 06:37:29 PM PDT 24
Peak memory 217656 kb
Host smart-315fe49c-980a-4c21-878e-d2d14d7e15b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020280001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1020280001
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.3959056636
Short name T981
Test name
Test status
Simulation time 48331807 ps
CPU time 1.69 seconds
Started Jul 12 06:39:15 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 220444 kb
Host smart-9779bbb2-32ef-4833-beca-f880629c90a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959056636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3959056636
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2682879723
Short name T484
Test name
Test status
Simulation time 61126793 ps
CPU time 1.37 seconds
Started Jul 12 06:39:16 PM PDT 24
Finished Jul 12 06:39:21 PM PDT 24
Peak memory 217700 kb
Host smart-07728a62-2b19-441d-b27c-135302af6e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682879723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2682879723
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2911815639
Short name T497
Test name
Test status
Simulation time 62130223 ps
CPU time 1.28 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 219024 kb
Host smart-c173c203-fed9-4fd7-9b19-9ee7b84e2676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911815639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2911815639
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1408200325
Short name T296
Test name
Test status
Simulation time 56881406 ps
CPU time 1.12 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:31 PM PDT 24
Peak memory 219380 kb
Host smart-b7b1c2f5-ef70-4401-8d52-1d8a7f459c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408200325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1408200325
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.509977658
Short name T313
Test name
Test status
Simulation time 34046965 ps
CPU time 1.29 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:22 PM PDT 24
Peak memory 218664 kb
Host smart-13e57e7d-acbd-407c-ac4b-529a6778c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509977658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.509977658
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.354234179
Short name T693
Test name
Test status
Simulation time 66497247 ps
CPU time 1.17 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:23 PM PDT 24
Peak memory 220292 kb
Host smart-f2a4c401-f3bf-47cc-8936-cc817f671fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354234179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.354234179
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2580667908
Short name T89
Test name
Test status
Simulation time 48200384 ps
CPU time 1.6 seconds
Started Jul 12 06:39:18 PM PDT 24
Finished Jul 12 06:39:24 PM PDT 24
Peak memory 217696 kb
Host smart-88292684-e4b3-4ef6-af32-61eee36aef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580667908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2580667908
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1309825715
Short name T330
Test name
Test status
Simulation time 61430487 ps
CPU time 1.26 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:30 PM PDT 24
Peak memory 218908 kb
Host smart-2fadfc3c-e51c-4aee-b1be-a052ce8cc66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309825715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1309825715
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1300385832
Short name T291
Test name
Test status
Simulation time 75862359 ps
CPU time 1.19 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:26 PM PDT 24
Peak memory 219184 kb
Host smart-59146010-1dae-47cd-b96e-22004505e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300385832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1300385832
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2586957027
Short name T759
Test name
Test status
Simulation time 97698087 ps
CPU time 1.23 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 215980 kb
Host smart-1dc8c1c6-e0e0-4b51-8c42-6e1e69709865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586957027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2586957027
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1683984715
Short name T541
Test name
Test status
Simulation time 41997690 ps
CPU time 0.87 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 215180 kb
Host smart-48d29609-c974-49c4-991e-12c0cf30eb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683984715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1683984715
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2714960276
Short name T896
Test name
Test status
Simulation time 22079481 ps
CPU time 0.88 seconds
Started Jul 12 06:37:37 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 215688 kb
Host smart-ae243c87-76e9-4f7a-85fa-6a49776c007e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714960276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2714960276
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4223333432
Short name T157
Test name
Test status
Simulation time 53848603 ps
CPU time 1.03 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 217156 kb
Host smart-bf081f13-ad07-41dd-b851-79c943cedc60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223333432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4223333432
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2307463124
Short name T7
Test name
Test status
Simulation time 78469586 ps
CPU time 1.07 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 220780 kb
Host smart-9cc4e7d5-a646-48f5-840d-ea1bea07abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307463124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2307463124
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1379257785
Short name T519
Test name
Test status
Simulation time 78197786 ps
CPU time 1.19 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 217624 kb
Host smart-e4d4cb81-228f-45f0-8da5-e5ba05f90c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379257785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1379257785
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2774029119
Short name T785
Test name
Test status
Simulation time 21409615 ps
CPU time 1.06 seconds
Started Jul 12 06:37:35 PM PDT 24
Finished Jul 12 06:37:37 PM PDT 24
Peak memory 217044 kb
Host smart-1f80ca85-746c-4fa0-b3d1-58539f048499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774029119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2774029119
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1513313064
Short name T646
Test name
Test status
Simulation time 49505785 ps
CPU time 0.96 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:36 PM PDT 24
Peak memory 215588 kb
Host smart-50f7f32d-d2c1-4985-841c-77fb689b1184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513313064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1513313064
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4209622471
Short name T953
Test name
Test status
Simulation time 269699976 ps
CPU time 5.23 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 217320 kb
Host smart-61ba22cb-2c06-424e-87f8-93cf8f52d303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209622471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4209622471
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3622300653
Short name T227
Test name
Test status
Simulation time 269052390890 ps
CPU time 836.29 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:51:33 PM PDT 24
Peak memory 224052 kb
Host smart-712d3f78-004e-47df-8062-24bdc61165a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622300653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3622300653
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.253646228
Short name T657
Test name
Test status
Simulation time 65388698 ps
CPU time 1.49 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 219004 kb
Host smart-be3bffaa-3d66-4ff9-a44d-fc3b0145ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253646228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.253646228
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3712761354
Short name T748
Test name
Test status
Simulation time 32572647 ps
CPU time 1.26 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:31 PM PDT 24
Peak memory 218804 kb
Host smart-66dcba78-f5b3-4199-80ad-47a5366f4400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712761354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3712761354
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2229106310
Short name T302
Test name
Test status
Simulation time 104894183 ps
CPU time 1.52 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 219164 kb
Host smart-0dc4ff28-17ff-4d37-8296-c51dd03c62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229106310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2229106310
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2933540442
Short name T880
Test name
Test status
Simulation time 52916524 ps
CPU time 1.32 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 218664 kb
Host smart-dcb28230-4e88-4056-aee7-f4694f76b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933540442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2933540442
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3985472288
Short name T300
Test name
Test status
Simulation time 31172174 ps
CPU time 1.44 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 220516 kb
Host smart-2b6a0572-008c-4e88-b825-764f5a2f5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985472288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3985472288
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3402888310
Short name T638
Test name
Test status
Simulation time 63076290 ps
CPU time 1.28 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:26 PM PDT 24
Peak memory 218972 kb
Host smart-a3264821-aae8-4f73-bc9b-5ea37c1040de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402888310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3402888310
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3162289539
Short name T306
Test name
Test status
Simulation time 42367608 ps
CPU time 1.3 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 218744 kb
Host smart-c4399c0c-90d6-4aeb-875a-e81e87508407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162289539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3162289539
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2537382361
Short name T956
Test name
Test status
Simulation time 77018249 ps
CPU time 1.18 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 219040 kb
Host smart-3937fd75-6817-4655-b715-b8a09837fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537382361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2537382361
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3504986925
Short name T889
Test name
Test status
Simulation time 95343384 ps
CPU time 1.24 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 219664 kb
Host smart-2ec281d9-2f52-4378-bf0b-0f75a3a8bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504986925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3504986925
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1925405496
Short name T466
Test name
Test status
Simulation time 70624609 ps
CPU time 1.46 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:30 PM PDT 24
Peak memory 218924 kb
Host smart-b3b09b32-bfb2-47af-b112-edea93780c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925405496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1925405496
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2067262122
Short name T579
Test name
Test status
Simulation time 90545113 ps
CPU time 1.25 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:36 PM PDT 24
Peak memory 218788 kb
Host smart-8327fac3-e76f-4fdc-91d4-cedbc0f5cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067262122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2067262122
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3796983189
Short name T362
Test name
Test status
Simulation time 40379166 ps
CPU time 0.86 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 215136 kb
Host smart-b8a5410b-faa8-490b-acc0-ed9d84c7fb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796983189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3796983189
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3854102125
Short name T920
Test name
Test status
Simulation time 11305961 ps
CPU time 0.88 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:35 PM PDT 24
Peak memory 216732 kb
Host smart-2d708849-e955-4edd-9036-f011cecd82e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854102125 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3854102125
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2095480754
Short name T78
Test name
Test status
Simulation time 92480985 ps
CPU time 1.17 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 219764 kb
Host smart-08b8a7c6-3b86-4eae-9fa8-0f7b72d26650
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095480754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2095480754
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1925009322
Short name T190
Test name
Test status
Simulation time 22023817 ps
CPU time 0.92 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 218900 kb
Host smart-acaef38c-8487-4749-bd1f-dc2937a23d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925009322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1925009322
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1187386863
Short name T329
Test name
Test status
Simulation time 83755679 ps
CPU time 1.08 seconds
Started Jul 12 06:37:37 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 217560 kb
Host smart-ac6299a0-2970-47ce-b348-66723e31f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187386863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1187386863
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3517083327
Short name T551
Test name
Test status
Simulation time 29583804 ps
CPU time 0.87 seconds
Started Jul 12 06:37:31 PM PDT 24
Finished Jul 12 06:37:33 PM PDT 24
Peak memory 216076 kb
Host smart-14ae2a9f-680f-40d3-bc28-e96400e0c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517083327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3517083327
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3745077515
Short name T793
Test name
Test status
Simulation time 25921521 ps
CPU time 0.93 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 215600 kb
Host smart-77599037-2590-4f13-8169-1f2d3181a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745077515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3745077515
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.28315946
Short name T418
Test name
Test status
Simulation time 207960255 ps
CPU time 3.81 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 215596 kb
Host smart-c2924481-da6d-4cac-b750-fbf6383ab8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.28315946
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3740154000
Short name T40
Test name
Test status
Simulation time 386812403916 ps
CPU time 2280.43 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 07:15:35 PM PDT 24
Peak memory 227164 kb
Host smart-be73c29b-ee9b-491e-81c8-bef5688227c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740154000 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3740154000
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3594422467
Short name T374
Test name
Test status
Simulation time 52322649 ps
CPU time 1.86 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 218704 kb
Host smart-b67929d9-dc4e-4fa4-84c5-b92048ceccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594422467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3594422467
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.917714649
Short name T471
Test name
Test status
Simulation time 124641848 ps
CPU time 1.06 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 217720 kb
Host smart-b94317b4-1bc6-40ca-b989-212225459367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917714649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.917714649
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2941841056
Short name T360
Test name
Test status
Simulation time 58255228 ps
CPU time 1.07 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:31 PM PDT 24
Peak memory 217692 kb
Host smart-3b1b98db-96f4-46a5-8ed1-149be39eab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941841056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2941841056
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2044708345
Short name T615
Test name
Test status
Simulation time 54144995 ps
CPU time 1.83 seconds
Started Jul 12 06:39:19 PM PDT 24
Finished Jul 12 06:39:25 PM PDT 24
Peak memory 219072 kb
Host smart-d0c2eeb1-9b7d-46a3-a2a9-2931fc08bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044708345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2044708345
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.808907111
Short name T842
Test name
Test status
Simulation time 82332441 ps
CPU time 1.26 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 219068 kb
Host smart-5754803d-7a99-44ec-893e-41bf85a1ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808907111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.808907111
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3257682592
Short name T237
Test name
Test status
Simulation time 36055095 ps
CPU time 1.3 seconds
Started Jul 12 06:39:24 PM PDT 24
Finished Jul 12 06:39:32 PM PDT 24
Peak memory 215576 kb
Host smart-dc3e0e45-288d-4b09-875c-8a9815b1e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257682592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3257682592
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.741953492
Short name T821
Test name
Test status
Simulation time 35617705 ps
CPU time 1.63 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:31 PM PDT 24
Peak memory 219060 kb
Host smart-e132fc7b-0c51-42fe-aebb-ebd535206782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741953492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.741953492
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2588362949
Short name T952
Test name
Test status
Simulation time 66805666 ps
CPU time 1.16 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:26 PM PDT 24
Peak memory 218752 kb
Host smart-e4181132-43fb-4e14-b84b-abf534e418dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588362949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2588362949
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2248137346
Short name T414
Test name
Test status
Simulation time 89666435 ps
CPU time 1.29 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:31 PM PDT 24
Peak memory 217708 kb
Host smart-e18f2194-4c12-4dfc-b575-a1d4fa50a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248137346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2248137346
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1820612010
Short name T425
Test name
Test status
Simulation time 32678055 ps
CPU time 1.29 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 218860 kb
Host smart-202004f4-6a76-4c20-bb53-ca6e3bb1cbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820612010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1820612010
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3198084827
Short name T865
Test name
Test status
Simulation time 30757261 ps
CPU time 1.13 seconds
Started Jul 12 06:37:33 PM PDT 24
Finished Jul 12 06:37:36 PM PDT 24
Peak memory 215280 kb
Host smart-e6c06cfa-67f5-4859-a348-830f27c6072f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198084827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3198084827
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3091638328
Short name T562
Test name
Test status
Simulation time 125633296 ps
CPU time 1.06 seconds
Started Jul 12 06:37:32 PM PDT 24
Finished Jul 12 06:37:34 PM PDT 24
Peak memory 217128 kb
Host smart-34b81b7c-5db2-45ee-86bc-14efe42de55b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091638328 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3091638328
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.466093031
Short name T160
Test name
Test status
Simulation time 30055978 ps
CPU time 1.02 seconds
Started Jul 12 06:37:34 PM PDT 24
Finished Jul 12 06:37:36 PM PDT 24
Peak memory 224036 kb
Host smart-7b018e30-352f-4e27-99d4-b84d4da778c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466093031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.466093031
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3872839777
Short name T980
Test name
Test status
Simulation time 50145976 ps
CPU time 1.88 seconds
Started Jul 12 06:37:37 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 218660 kb
Host smart-b0dd154d-2a29-4799-9a48-9e1f5d75ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872839777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3872839777
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3193673604
Short name T689
Test name
Test status
Simulation time 59299449 ps
CPU time 0.79 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 215792 kb
Host smart-3340e270-9fbb-49de-99bf-008ec77d559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193673604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3193673604
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3670293394
Short name T356
Test name
Test status
Simulation time 51051745 ps
CPU time 0.93 seconds
Started Jul 12 06:37:36 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 215592 kb
Host smart-11f72e33-7102-450e-91d1-748efecf0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670293394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3670293394
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.579859407
Short name T515
Test name
Test status
Simulation time 401654692 ps
CPU time 3.46 seconds
Started Jul 12 06:37:34 PM PDT 24
Finished Jul 12 06:37:38 PM PDT 24
Peak memory 220324 kb
Host smart-1a91d2eb-1589-44db-9173-0bd9d31e6d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579859407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.579859407
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.3467089438
Short name T568
Test name
Test status
Simulation time 34243542 ps
CPU time 1.33 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:29 PM PDT 24
Peak memory 217644 kb
Host smart-9fe1f982-f6d4-4ac1-b7cb-8dd10debdb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467089438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3467089438
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.569984977
Short name T529
Test name
Test status
Simulation time 51149290 ps
CPU time 1.73 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 218052 kb
Host smart-9d2e0ff3-c668-48b1-8867-b32a06679d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569984977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.569984977
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.606703921
Short name T304
Test name
Test status
Simulation time 199366935 ps
CPU time 1.29 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:30 PM PDT 24
Peak memory 219100 kb
Host smart-370dd17d-8909-4532-abca-131f1acd5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606703921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.606703921
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2533368996
Short name T382
Test name
Test status
Simulation time 85043648 ps
CPU time 1.55 seconds
Started Jul 12 06:39:21 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 219068 kb
Host smart-dad620df-e0fb-4d81-8168-50ace7988f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533368996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2533368996
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2188139042
Short name T442
Test name
Test status
Simulation time 102881185 ps
CPU time 1.27 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 220512 kb
Host smart-a62d9b11-5bf9-430f-a4be-b39fa758632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188139042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2188139042
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3140804228
Short name T651
Test name
Test status
Simulation time 189472116 ps
CPU time 1.37 seconds
Started Jul 12 06:39:24 PM PDT 24
Finished Jul 12 06:39:33 PM PDT 24
Peak memory 219104 kb
Host smart-50429d23-2eea-49f4-a79d-2ffc10313ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140804228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3140804228
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3518715505
Short name T846
Test name
Test status
Simulation time 44505811 ps
CPU time 1.72 seconds
Started Jul 12 06:39:24 PM PDT 24
Finished Jul 12 06:39:33 PM PDT 24
Peak memory 217824 kb
Host smart-404b21a6-a9f3-424f-9d2e-4416464fc15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518715505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3518715505
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3222252994
Short name T502
Test name
Test status
Simulation time 103189182 ps
CPU time 1.7 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 219980 kb
Host smart-b9d3d7b0-62f1-447e-bafe-568a4ea69b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222252994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3222252994
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.160431825
Short name T660
Test name
Test status
Simulation time 50774104 ps
CPU time 1.45 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:28 PM PDT 24
Peak memory 218696 kb
Host smart-dc4ad239-8b54-4448-be59-5dcc4b34c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160431825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.160431825
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3486156455
Short name T279
Test name
Test status
Simulation time 73013800 ps
CPU time 1.43 seconds
Started Jul 12 06:39:23 PM PDT 24
Finished Jul 12 06:39:32 PM PDT 24
Peak memory 218836 kb
Host smart-d5bfe053-f6d2-4b84-920b-d0e0bcfaa9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486156455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3486156455
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3432156802
Short name T626
Test name
Test status
Simulation time 101587712 ps
CPU time 1.26 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 215956 kb
Host smart-0399565f-79fa-4e90-b3d4-d04fe06039c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432156802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3432156802
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1586022407
Short name T431
Test name
Test status
Simulation time 15418563 ps
CPU time 0.97 seconds
Started Jul 12 06:36:53 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 207032 kb
Host smart-945b837c-1e36-4410-bd4e-e72a9637be78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586022407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1586022407
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3437936374
Short name T879
Test name
Test status
Simulation time 16010616 ps
CPU time 0.83 seconds
Started Jul 12 06:36:48 PM PDT 24
Finished Jul 12 06:36:50 PM PDT 24
Peak memory 216536 kb
Host smart-16bceb73-e067-41b4-84dd-0dd03f4683a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437936374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3437936374
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2611384853
Short name T834
Test name
Test status
Simulation time 45156668 ps
CPU time 1.21 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:54 PM PDT 24
Peak memory 217284 kb
Host smart-ae680375-3a04-4192-b70f-515518b9ca4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611384853 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2611384853
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.1881446611
Short name T462
Test name
Test status
Simulation time 87741345 ps
CPU time 1.16 seconds
Started Jul 12 06:36:41 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 219856 kb
Host smart-40b22e63-8079-4dc7-8b6d-ee12054a420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881446611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1881446611
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.258184762
Short name T104
Test name
Test status
Simulation time 27594533 ps
CPU time 1 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:53 PM PDT 24
Peak memory 216124 kb
Host smart-058258fc-be1e-4043-bbb0-47db265f768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258184762 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.258184762
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2513179569
Short name T520
Test name
Test status
Simulation time 35523399 ps
CPU time 0.94 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:55 PM PDT 24
Peak memory 207388 kb
Host smart-70c5d4c5-e0cd-4dd2-9940-4b5479811b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513179569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2513179569
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.172176739
Short name T433
Test name
Test status
Simulation time 51391288 ps
CPU time 0.97 seconds
Started Jul 12 06:36:41 PM PDT 24
Finished Jul 12 06:36:43 PM PDT 24
Peak memory 215572 kb
Host smart-2eda9016-113d-468d-8e3b-ce754e832d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172176739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.172176739
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1363009395
Short name T934
Test name
Test status
Simulation time 61574819 ps
CPU time 1.28 seconds
Started Jul 12 06:36:49 PM PDT 24
Finished Jul 12 06:36:52 PM PDT 24
Peak memory 215532 kb
Host smart-6f452433-cd7b-4a9e-98db-6c86ca7602ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363009395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1363009395
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1611757146
Short name T228
Test name
Test status
Simulation time 37081021640 ps
CPU time 818.79 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:50:35 PM PDT 24
Peak memory 219352 kb
Host smart-bf7a684e-7a99-497a-b8dd-605d55f52fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611757146 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1611757146
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.4172959831
Short name T125
Test name
Test status
Simulation time 32129240 ps
CPU time 1.21 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 219680 kb
Host smart-83580b2d-42d7-4c8c-b674-5c5a3f28dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172959831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4172959831
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3980675749
Short name T443
Test name
Test status
Simulation time 36193056 ps
CPU time 0.84 seconds
Started Jul 12 06:37:39 PM PDT 24
Finished Jul 12 06:37:42 PM PDT 24
Peak memory 206948 kb
Host smart-ecc840a9-ba45-4dde-88fc-ea8f7f17a099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980675749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3980675749
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3059146522
Short name T884
Test name
Test status
Simulation time 33807575 ps
CPU time 0.82 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 216596 kb
Host smart-7fbbccea-bdd4-4ba1-8ea8-1a7f4cd01719
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059146522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3059146522
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1485551521
Short name T273
Test name
Test status
Simulation time 49102546 ps
CPU time 1.05 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 218780 kb
Host smart-bb4ff8b8-8a54-44df-bfda-124f304e3dd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485551521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1485551521
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.104594862
Short name T617
Test name
Test status
Simulation time 48847237 ps
CPU time 0.86 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 218652 kb
Host smart-fccd6b24-1b77-417e-92d9-6c3fabd9e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104594862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.104594862
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3444426355
Short name T807
Test name
Test status
Simulation time 104496208 ps
CPU time 1.34 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 219384 kb
Host smart-016914d5-6e54-4ec8-8bab-a80d0d3654f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444426355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3444426355
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1717409256
Short name T795
Test name
Test status
Simulation time 46554746 ps
CPU time 0.89 seconds
Started Jul 12 06:37:44 PM PDT 24
Finished Jul 12 06:37:46 PM PDT 24
Peak memory 215664 kb
Host smart-02b91729-eac1-42bc-aa82-73c667097bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717409256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1717409256
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4073982753
Short name T667
Test name
Test status
Simulation time 17194755 ps
CPU time 1.02 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:41 PM PDT 24
Peak memory 215580 kb
Host smart-25af5acb-7671-4e74-befe-a291077281c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073982753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4073982753
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4044186912
Short name T432
Test name
Test status
Simulation time 560582681 ps
CPU time 3.44 seconds
Started Jul 12 06:37:39 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 217732 kb
Host smart-494b9a8b-17c4-4006-8ef4-868b4f014de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044186912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4044186912
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1000552098
Short name T231
Test name
Test status
Simulation time 200400275514 ps
CPU time 1110.3 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:56:10 PM PDT 24
Peak memory 223424 kb
Host smart-bc8221fd-238d-4ff4-a3ff-f38e969c48e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000552098 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1000552098
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2940895621
Short name T124
Test name
Test status
Simulation time 52142924 ps
CPU time 1.3 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 219776 kb
Host smart-36342b34-957e-4845-8d12-aa43c28a4c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940895621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2940895621
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1182075101
Short name T437
Test name
Test status
Simulation time 127366658 ps
CPU time 0.9 seconds
Started Jul 12 06:37:46 PM PDT 24
Finished Jul 12 06:37:47 PM PDT 24
Peak memory 215164 kb
Host smart-994cd853-76d8-4bb0-b780-9aa93e07bc91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182075101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1182075101
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.38696844
Short name T210
Test name
Test status
Simulation time 11668301 ps
CPU time 0.86 seconds
Started Jul 12 06:37:44 PM PDT 24
Finished Jul 12 06:37:46 PM PDT 24
Peak memory 215736 kb
Host smart-9a847e64-885b-41d0-b0f2-fbc4c7558ead
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.38696844
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.693632393
Short name T725
Test name
Test status
Simulation time 84280450 ps
CPU time 1.12 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:42 PM PDT 24
Peak memory 217320 kb
Host smart-61297553-e6ba-48eb-8769-76b6309d06b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693632393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.693632393
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4260281645
Short name T181
Test name
Test status
Simulation time 19832600 ps
CPU time 1.09 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 218992 kb
Host smart-ae34ed63-8ae2-4451-b4be-2660ca29ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260281645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4260281645
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3703610566
Short name T333
Test name
Test status
Simulation time 35552771 ps
CPU time 1.24 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 217744 kb
Host smart-a816c713-299e-4f73-87a3-dbff97501af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703610566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3703610566
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1006543590
Short name T624
Test name
Test status
Simulation time 21636272 ps
CPU time 1.11 seconds
Started Jul 12 06:37:39 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 215720 kb
Host smart-1a69a3a5-09c5-467a-9986-ae9bc95f29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006543590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1006543590
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1591478816
Short name T74
Test name
Test status
Simulation time 143109721 ps
CPU time 0.96 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 215580 kb
Host smart-c82c90fd-71f0-48dd-9f2d-86b58d956bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591478816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1591478816
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4264146884
Short name T678
Test name
Test status
Simulation time 188866570 ps
CPU time 2.03 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 217504 kb
Host smart-d9f4841e-498c-415d-9985-bec5e524227b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264146884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4264146884
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2987105454
Short name T898
Test name
Test status
Simulation time 333650160089 ps
CPU time 1820.85 seconds
Started Jul 12 06:37:40 PM PDT 24
Finished Jul 12 07:08:03 PM PDT 24
Peak memory 225436 kb
Host smart-4974b55a-1443-46b0-98d6-eea09fad4f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987105454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2987105454
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.498706650
Short name T967
Test name
Test status
Simulation time 203447438 ps
CPU time 1.21 seconds
Started Jul 12 06:37:40 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 215992 kb
Host smart-dadb172d-23ce-487f-a689-d0b71c27116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498706650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.498706650
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3210447169
Short name T393
Test name
Test status
Simulation time 18551079 ps
CPU time 1.05 seconds
Started Jul 12 06:37:42 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 207124 kb
Host smart-f12dde9c-07f9-4206-ae55-93ce17cd5bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210447169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3210447169
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.418269112
Short name T166
Test name
Test status
Simulation time 36197814 ps
CPU time 0.85 seconds
Started Jul 12 06:37:40 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 216556 kb
Host smart-6c20c604-2c92-46ad-ac1e-c7ca2ded6832
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418269112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.418269112
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3228421757
Short name T756
Test name
Test status
Simulation time 29042616 ps
CPU time 1.07 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 217200 kb
Host smart-76bb50b6-16a7-45b9-bb95-a9b6cb27e88a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228421757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3228421757
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3384872703
Short name T68
Test name
Test status
Simulation time 32195692 ps
CPU time 0.85 seconds
Started Jul 12 06:37:42 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 218780 kb
Host smart-e29e15bc-66c5-4978-8ee3-095116019dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384872703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3384872703
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1457750228
Short name T623
Test name
Test status
Simulation time 72433890 ps
CPU time 1.06 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 215576 kb
Host smart-054382b9-7f6c-4aa7-a813-871fe661d734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457750228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1457750228
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.995127056
Short name T794
Test name
Test status
Simulation time 30895049 ps
CPU time 0.9 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:46 PM PDT 24
Peak memory 215944 kb
Host smart-9abbb663-a84c-4ef2-80b9-247b0957020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995127056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.995127056
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3245536089
Short name T711
Test name
Test status
Simulation time 41216389 ps
CPU time 0.94 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:40 PM PDT 24
Peak memory 215584 kb
Host smart-cf18a7b6-36d8-4107-b4d3-9b8ffc964c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245536089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3245536089
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.505331843
Short name T75
Test name
Test status
Simulation time 370422451 ps
CPU time 2.23 seconds
Started Jul 12 06:37:41 PM PDT 24
Finished Jul 12 06:37:45 PM PDT 24
Peak memory 217372 kb
Host smart-48cdb7ed-eb8b-4fb6-bed9-3b1df80a2471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505331843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.505331843
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.4034680003
Short name T543
Test name
Test status
Simulation time 77500490170 ps
CPU time 340.72 seconds
Started Jul 12 06:37:42 PM PDT 24
Finished Jul 12 06:43:24 PM PDT 24
Peak memory 218720 kb
Host smart-53d0adea-7563-4d28-90e0-9d8c61da0af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034680003 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.4034680003
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4046895847
Short name T136
Test name
Test status
Simulation time 74019708 ps
CPU time 1.17 seconds
Started Jul 12 06:37:38 PM PDT 24
Finished Jul 12 06:37:42 PM PDT 24
Peak memory 220112 kb
Host smart-c12a5da3-0462-4bbf-9089-c20c86bb0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046895847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4046895847
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2188016365
Short name T244
Test name
Test status
Simulation time 22604786 ps
CPU time 0.91 seconds
Started Jul 12 06:37:40 PM PDT 24
Finished Jul 12 06:37:42 PM PDT 24
Peak memory 207020 kb
Host smart-13acc3a6-d34a-44ad-9ead-3cc75030e79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188016365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2188016365
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2450502678
Short name T215
Test name
Test status
Simulation time 39613111 ps
CPU time 0.87 seconds
Started Jul 12 06:37:40 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 216512 kb
Host smart-86edbfeb-5324-4b52-a2bd-1ece282ce95d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450502678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2450502678
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2015713643
Short name T139
Test name
Test status
Simulation time 128403931 ps
CPU time 1.13 seconds
Started Jul 12 06:37:42 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 218820 kb
Host smart-4fdc64ef-8075-4b5c-9d3c-f3c79bbad3d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015713643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2015713643
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.4223869468
Short name T582
Test name
Test status
Simulation time 22451740 ps
CPU time 1.02 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:37:46 PM PDT 24
Peak memory 219836 kb
Host smart-c50b344c-b0a1-42e1-8c2c-ffc45ae16a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223869468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.4223869468
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2106948889
Short name T341
Test name
Test status
Simulation time 49096396 ps
CPU time 2.02 seconds
Started Jul 12 06:37:39 PM PDT 24
Finished Jul 12 06:37:43 PM PDT 24
Peak memory 218700 kb
Host smart-07b9686b-27ef-4990-b420-3ef2a0795257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106948889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2106948889
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1809142332
Short name T99
Test name
Test status
Simulation time 80339327 ps
CPU time 0.83 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 215592 kb
Host smart-ae08a860-3193-4343-bb0c-5a3a74596cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809142332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1809142332
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3507940843
Short name T331
Test name
Test status
Simulation time 22483243 ps
CPU time 0.97 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 215612 kb
Host smart-337e4ad8-9d20-4876-b7b2-57e138ce13e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507940843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3507940843
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2508377960
Short name T859
Test name
Test status
Simulation time 994265640 ps
CPU time 5.37 seconds
Started Jul 12 06:37:44 PM PDT 24
Finished Jul 12 06:37:50 PM PDT 24
Peak memory 217756 kb
Host smart-481be9a1-cdf1-45d4-a9fb-5d86c0b9d158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508377960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2508377960
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2692964046
Short name T684
Test name
Test status
Simulation time 27635500455 ps
CPU time 720.44 seconds
Started Jul 12 06:37:43 PM PDT 24
Finished Jul 12 06:49:45 PM PDT 24
Peak memory 218892 kb
Host smart-715fa748-a112-4029-94f2-a89140cdc12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692964046 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2692964046
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2732255333
Short name T326
Test name
Test status
Simulation time 27638971 ps
CPU time 1.22 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 221128 kb
Host smart-f970c46a-3fb0-4618-909e-fee48f0aa0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732255333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2732255333
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1299434136
Short name T383
Test name
Test status
Simulation time 24955764 ps
CPU time 0.88 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:50 PM PDT 24
Peak memory 215440 kb
Host smart-25def2cc-a625-434e-8f7f-c1eed99d37b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299434136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1299434136
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3351910383
Short name T622
Test name
Test status
Simulation time 17174414 ps
CPU time 0.86 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:49 PM PDT 24
Peak memory 216624 kb
Host smart-a5f4b150-31f1-4a7f-b5bc-d907682f5c73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351910383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3351910383
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.142027550
Short name T610
Test name
Test status
Simulation time 31640347 ps
CPU time 0.85 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:50 PM PDT 24
Peak memory 218240 kb
Host smart-874aaffc-fa97-4713-91ce-53183ccfae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142027550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.142027550
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3537264529
Short name T688
Test name
Test status
Simulation time 121446738 ps
CPU time 1.12 seconds
Started Jul 12 06:37:42 PM PDT 24
Finished Jul 12 06:37:44 PM PDT 24
Peak memory 217648 kb
Host smart-64e051ac-b6c1-47e7-b6f7-00052555c961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537264529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3537264529
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1316491758
Short name T32
Test name
Test status
Simulation time 24813431 ps
CPU time 0.95 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 216108 kb
Host smart-05a72a2d-2015-4c6f-be70-cbdc4f02ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316491758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1316491758
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4268377835
Short name T565
Test name
Test status
Simulation time 50415379 ps
CPU time 0.92 seconds
Started Jul 12 06:37:39 PM PDT 24
Finished Jul 12 06:37:42 PM PDT 24
Peak memory 215572 kb
Host smart-872c3c0a-e37f-4d4f-a62d-654108ff35e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268377835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4268377835
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3598479406
Short name T526
Test name
Test status
Simulation time 230034829 ps
CPU time 1.22 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 217480 kb
Host smart-ba8e32a8-448f-4238-a1e9-00869717d1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598479406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3598479406
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1222752471
Short name T784
Test name
Test status
Simulation time 74965161802 ps
CPU time 866.98 seconds
Started Jul 12 06:37:51 PM PDT 24
Finished Jul 12 06:52:20 PM PDT 24
Peak memory 220480 kb
Host smart-6fa761c0-5587-4290-9622-ea862421ed3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222752471 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1222752471
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.203874769
Short name T92
Test name
Test status
Simulation time 25499693 ps
CPU time 1.2 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:50 PM PDT 24
Peak memory 218880 kb
Host smart-05571fcb-dc77-4063-98df-abf8146ec63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203874769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.203874769
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2761513352
Short name T387
Test name
Test status
Simulation time 38964792 ps
CPU time 0.81 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:49 PM PDT 24
Peak memory 207076 kb
Host smart-0b6e19ca-abf1-4ecd-8f9a-3d8dc3da6597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761513352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2761513352
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.729171519
Short name T339
Test name
Test status
Simulation time 12119093 ps
CPU time 0.94 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:49 PM PDT 24
Peak memory 216076 kb
Host smart-986b8f84-8363-4f39-8a0e-8f9d86e3f224
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729171519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.729171519
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3767790078
Short name T839
Test name
Test status
Simulation time 95134260 ps
CPU time 1.18 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 217136 kb
Host smart-535a3b21-b466-44c4-889d-aa06df0a7826
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767790078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3767790078
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2024806445
Short name T992
Test name
Test status
Simulation time 18686159 ps
CPU time 1.16 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 224252 kb
Host smart-dc172883-b46e-4578-a7e0-87991890d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024806445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2024806445
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.670456504
Short name T492
Test name
Test status
Simulation time 52438291 ps
CPU time 1.63 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:50 PM PDT 24
Peak memory 218848 kb
Host smart-e55d938a-8f8a-4cbf-8a9e-185ff411ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670456504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.670456504
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1313678755
Short name T778
Test name
Test status
Simulation time 27554353 ps
CPU time 1.07 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 224480 kb
Host smart-4027a249-49b1-4a5b-aecb-2a2d82925b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313678755 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1313678755
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3620218689
Short name T450
Test name
Test status
Simulation time 46822198 ps
CPU time 0.96 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 215584 kb
Host smart-1217461b-806a-471f-a9d3-377974ff4527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620218689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3620218689
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2229109826
Short name T645
Test name
Test status
Simulation time 462518745 ps
CPU time 2.46 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 217520 kb
Host smart-89b8e532-b380-4906-aedb-eca1971ac1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229109826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2229109826
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2415426652
Short name T705
Test name
Test status
Simulation time 59810159500 ps
CPU time 1455.19 seconds
Started Jul 12 06:37:51 PM PDT 24
Finished Jul 12 07:02:08 PM PDT 24
Peak memory 225004 kb
Host smart-beba35af-9ed4-4d4b-bd7b-a325fb9f4b75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415426652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2415426652
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3782974885
Short name T635
Test name
Test status
Simulation time 211872272 ps
CPU time 1.18 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 220732 kb
Host smart-5c68a67a-0236-42c3-bca3-63eeff1881a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782974885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3782974885
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2051958832
Short name T940
Test name
Test status
Simulation time 46618111 ps
CPU time 1 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 207044 kb
Host smart-3adc7cc1-0c8c-4edf-aa53-9f51aedd585e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051958832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2051958832
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3248223453
Short name T21
Test name
Test status
Simulation time 112369691 ps
CPU time 1.2 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:48 PM PDT 24
Peak memory 217128 kb
Host smart-46d6030b-6c4a-497f-8446-8fad564d7c0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248223453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3248223453
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1387979862
Short name T877
Test name
Test status
Simulation time 24512705 ps
CPU time 1.13 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 229904 kb
Host smart-a50b3c11-00f3-4a4e-9107-5374ec9d99dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387979862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1387979862
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3899327662
Short name T311
Test name
Test status
Simulation time 30283850 ps
CPU time 1.33 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 219948 kb
Host smart-b9d347f5-b022-4569-8cc2-334a8bb84be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899327662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3899327662
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4128717209
Short name T823
Test name
Test status
Simulation time 40779495 ps
CPU time 0.96 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:53 PM PDT 24
Peak memory 215844 kb
Host smart-2e024b12-3c82-48f0-ae96-cc134596177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128717209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4128717209
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.542780403
Short name T608
Test name
Test status
Simulation time 21866176 ps
CPU time 0.95 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 215576 kb
Host smart-4b64f9c7-c808-40bc-b793-0ba1e7d8ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542780403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.542780403
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3389446928
Short name T764
Test name
Test status
Simulation time 63631309 ps
CPU time 1.23 seconds
Started Jul 12 06:37:47 PM PDT 24
Finished Jul 12 06:37:49 PM PDT 24
Peak memory 215564 kb
Host smart-537fa151-358a-4764-b00d-c0424c230eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389446928 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3389446928
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.154495692
Short name T971
Test name
Test status
Simulation time 73365578204 ps
CPU time 1858.9 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 07:08:50 PM PDT 24
Peak memory 228108 kb
Host smart-037b8ea9-48fb-4507-9401-d4c9fea86b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154495692 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.154495692
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3149808322
Short name T327
Test name
Test status
Simulation time 217621156 ps
CPU time 1.33 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:01 PM PDT 24
Peak memory 220116 kb
Host smart-86d15878-5b9e-426a-aea9-45c7ddf884e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149808322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3149808322
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.875025823
Short name T734
Test name
Test status
Simulation time 28635968 ps
CPU time 0.94 seconds
Started Jul 12 06:37:54 PM PDT 24
Finished Jul 12 06:37:56 PM PDT 24
Peak memory 207040 kb
Host smart-419e2d32-66b3-4208-af62-c3cb00238d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875025823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.875025823
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4016047379
Short name T866
Test name
Test status
Simulation time 18461204 ps
CPU time 0.86 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:58 PM PDT 24
Peak memory 216540 kb
Host smart-02b7391a-e328-4542-b8be-cb3ca2a5482f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016047379 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4016047379
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.125041284
Short name T655
Test name
Test status
Simulation time 99870512 ps
CPU time 1.09 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:58 PM PDT 24
Peak memory 219036 kb
Host smart-50c132c2-80d3-413b-9cce-4cc10ea84acf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125041284 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.125041284
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3327506729
Short name T138
Test name
Test status
Simulation time 24030884 ps
CPU time 1 seconds
Started Jul 12 06:37:52 PM PDT 24
Finished Jul 12 06:37:54 PM PDT 24
Peak memory 220092 kb
Host smart-c896c150-7ffa-4bda-bc1b-2119dda99651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327506729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3327506729
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2213175845
Short name T675
Test name
Test status
Simulation time 26096041 ps
CPU time 1.23 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 220172 kb
Host smart-4ed5e8e9-2db2-448d-bc31-d7e8dc7fab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213175845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2213175845
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2589250605
Short name T201
Test name
Test status
Simulation time 78354873 ps
CPU time 0.9 seconds
Started Jul 12 06:37:48 PM PDT 24
Finished Jul 12 06:37:51 PM PDT 24
Peak memory 215540 kb
Host smart-35eb6cc0-9cc0-4cea-baff-6e89edb2784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589250605 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2589250605
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.330746980
Short name T885
Test name
Test status
Simulation time 55275711 ps
CPU time 0.91 seconds
Started Jul 12 06:37:49 PM PDT 24
Finished Jul 12 06:37:52 PM PDT 24
Peak memory 215604 kb
Host smart-7da47201-cd73-4097-bf5f-abba3de695b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330746980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.330746980
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2982037760
Short name T507
Test name
Test status
Simulation time 340972498 ps
CPU time 3.75 seconds
Started Jul 12 06:37:50 PM PDT 24
Finished Jul 12 06:37:56 PM PDT 24
Peak memory 215572 kb
Host smart-4f62b19f-eede-4f8e-ab33-1c8cfab10040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982037760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2982037760
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.375898592
Short name T540
Test name
Test status
Simulation time 101659516339 ps
CPU time 1315.53 seconds
Started Jul 12 06:37:46 PM PDT 24
Finished Jul 12 06:59:43 PM PDT 24
Peak memory 225836 kb
Host smart-2078e669-c74c-48c9-8464-3039f0e0e366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375898592 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.375898592
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3632501593
Short name T188
Test name
Test status
Simulation time 67076208 ps
CPU time 1.17 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 219868 kb
Host smart-85a7b662-df3b-4662-86b4-46cb80254a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632501593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3632501593
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2970527722
Short name T757
Test name
Test status
Simulation time 39983791 ps
CPU time 0.91 seconds
Started Jul 12 06:37:54 PM PDT 24
Finished Jul 12 06:37:56 PM PDT 24
Peak memory 207080 kb
Host smart-19068048-1782-4646-9a99-a15c0f77c6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970527722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2970527722
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4058937593
Short name T478
Test name
Test status
Simulation time 23965189 ps
CPU time 0.89 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 215852 kb
Host smart-e04abfa5-cc83-48bf-a894-e9edb66f9926
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058937593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4058937593
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3300526471
Short name T361
Test name
Test status
Simulation time 51282437 ps
CPU time 1.17 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 218900 kb
Host smart-81652055-2c7c-49b3-9cdb-09fa37324bab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300526471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3300526471
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1520064297
Short name T120
Test name
Test status
Simulation time 34029770 ps
CPU time 0.93 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 219704 kb
Host smart-3e70d82c-fbbd-4a18-8d3a-0cd69b3020ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520064297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1520064297
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2894342293
Short name T47
Test name
Test status
Simulation time 72334826 ps
CPU time 1.25 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 217608 kb
Host smart-c5cce10f-29e8-4f77-a833-79e8c69454f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894342293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2894342293
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3641537738
Short name T103
Test name
Test status
Simulation time 35013727 ps
CPU time 1.35 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:58 PM PDT 24
Peak memory 216988 kb
Host smart-4b0278fa-4d37-4f6a-a4fd-795ebaaf8d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641537738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3641537738
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3205201064
Short name T663
Test name
Test status
Simulation time 77754706 ps
CPU time 0.93 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 215548 kb
Host smart-0ec785e2-0ed7-4d64-b891-b78406bfe63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205201064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3205201064
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2534970999
Short name T670
Test name
Test status
Simulation time 290639372 ps
CPU time 2.16 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 217436 kb
Host smart-bdeb03eb-63e8-4609-9fb3-be118d38fa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534970999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2534970999
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1462578760
Short name T514
Test name
Test status
Simulation time 136144008042 ps
CPU time 1759.42 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 07:07:19 PM PDT 24
Peak memory 226940 kb
Host smart-787bdf10-b88f-4b8f-b51c-a0d5e9989281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462578760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1462578760
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1260941565
Short name T321
Test name
Test status
Simulation time 52689775 ps
CPU time 1.13 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 220056 kb
Host smart-7871f75a-7864-43b2-9f3f-8c90b819f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260941565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1260941565
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1969019591
Short name T428
Test name
Test status
Simulation time 42282253 ps
CPU time 0.87 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 206652 kb
Host smart-e4561648-b625-4daa-9392-0de587db630b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969019591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1969019591
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3396363773
Short name T455
Test name
Test status
Simulation time 85279497 ps
CPU time 0.86 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 215692 kb
Host smart-56ccc448-d1ba-4c00-a76e-d8deecb89056
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396363773 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3396363773
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2651340752
Short name T792
Test name
Test status
Simulation time 119014786 ps
CPU time 1.15 seconds
Started Jul 12 06:38:00 PM PDT 24
Finished Jul 12 06:38:03 PM PDT 24
Peak memory 217208 kb
Host smart-667a2def-b62e-42b6-bfb8-c6d7b4f1fa5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651340752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2651340752
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1696527866
Short name T847
Test name
Test status
Simulation time 31204950 ps
CPU time 0.87 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 218576 kb
Host smart-98e631b7-3922-40dd-b4bd-415cabd56065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696527866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1696527866
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3618148761
Short name T441
Test name
Test status
Simulation time 27707258 ps
CPU time 1.28 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 219304 kb
Host smart-40d72314-fdb9-43c3-a403-85c0f033f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618148761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3618148761
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3294030482
Short name T511
Test name
Test status
Simulation time 23335138 ps
CPU time 1.12 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 215788 kb
Host smart-34823348-a04e-47ad-ad24-3b190d9caab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294030482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3294030482
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1925470632
Short name T421
Test name
Test status
Simulation time 17800349 ps
CPU time 0.98 seconds
Started Jul 12 06:37:53 PM PDT 24
Finished Jul 12 06:37:55 PM PDT 24
Peak memory 215608 kb
Host smart-71779da4-85ea-4bc2-acb0-6c47df4bbbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925470632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1925470632
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.638611263
Short name T832
Test name
Test status
Simulation time 45971308 ps
CPU time 1.09 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 215692 kb
Host smart-566991c7-7bc7-4f3f-bf23-99809f30abf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638611263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.638611263
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2879570413
Short name T930
Test name
Test status
Simulation time 52965642953 ps
CPU time 1100.69 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:56:18 PM PDT 24
Peak memory 220992 kb
Host smart-a9c8d11d-7db2-4a82-be2b-0d173f4cc86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879570413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2879570413
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3536957159
Short name T941
Test name
Test status
Simulation time 100402997 ps
CPU time 1.1 seconds
Started Jul 12 06:36:53 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 219840 kb
Host smart-9421e793-5e18-4cea-aab2-eba750c8ee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536957159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3536957159
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3003535437
Short name T569
Test name
Test status
Simulation time 21436193 ps
CPU time 0.84 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 215420 kb
Host smart-0d746d8e-8cdf-42c7-a053-2233961c65e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003535437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3003535437
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4110975726
Short name T664
Test name
Test status
Simulation time 17245376 ps
CPU time 0.86 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:53 PM PDT 24
Peak memory 216324 kb
Host smart-b82af570-9764-4712-82a9-bf730919e1bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110975726 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4110975726
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3834594920
Short name T409
Test name
Test status
Simulation time 35099981 ps
CPU time 1.15 seconds
Started Jul 12 06:36:49 PM PDT 24
Finished Jul 12 06:36:52 PM PDT 24
Peak memory 217280 kb
Host smart-30fee8ed-94bd-4b9e-8532-da95b9f9dc26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834594920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3834594920
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2534526778
Short name T628
Test name
Test status
Simulation time 35627977 ps
CPU time 1.19 seconds
Started Jul 12 06:36:53 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 224264 kb
Host smart-23a9b8d0-de40-45f5-89eb-21cf2cad6d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534526778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2534526778
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4147737587
Short name T498
Test name
Test status
Simulation time 96835449 ps
CPU time 1.53 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 218752 kb
Host smart-080a2fda-bec2-40a4-9053-40f33dce19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147737587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4147737587
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.739925799
Short name T446
Test name
Test status
Simulation time 48513879 ps
CPU time 0.86 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 215668 kb
Host smart-c994933c-f191-4c26-a6fe-ca2ddabbbc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739925799 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.739925799
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.847468468
Short name T763
Test name
Test status
Simulation time 100053795 ps
CPU time 0.95 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:53 PM PDT 24
Peak memory 207244 kb
Host smart-1b203fbf-a8b6-4e82-838e-8c595e935017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847468468 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.847468468
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3801001855
Short name T20
Test name
Test status
Simulation time 1877423450 ps
CPU time 7.09 seconds
Started Jul 12 06:36:55 PM PDT 24
Finished Jul 12 06:37:04 PM PDT 24
Peak memory 236712 kb
Host smart-7c49cc22-b2cf-49ba-b911-8f39f86eebd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801001855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3801001855
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1399402673
Short name T750
Test name
Test status
Simulation time 15242422 ps
CPU time 0.99 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 215556 kb
Host smart-5629edaa-093f-4196-a42a-e1d3a49d3196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399402673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1399402673
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.896495373
Short name T805
Test name
Test status
Simulation time 321268326 ps
CPU time 6.27 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:37:02 PM PDT 24
Peak memory 219488 kb
Host smart-506bba8f-a595-4c1f-8b97-c5c6bcaa5f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896495373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.896495373
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2725602846
Short name T848
Test name
Test status
Simulation time 56469162266 ps
CPU time 635.88 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:47:28 PM PDT 24
Peak memory 224016 kb
Host smart-3b589ae0-789d-42cb-b1d5-80fc78206582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725602846 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2725602846
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2335648901
Short name T240
Test name
Test status
Simulation time 27409419 ps
CPU time 1.26 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 219244 kb
Host smart-68617185-3a92-4cdd-9725-9a70b632f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335648901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2335648901
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.4107990705
Short name T415
Test name
Test status
Simulation time 89257139 ps
CPU time 0.84 seconds
Started Jul 12 06:37:54 PM PDT 24
Finished Jul 12 06:37:55 PM PDT 24
Peak memory 207040 kb
Host smart-e5f93e22-b12a-4650-8498-5a2142bdbe7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107990705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4107990705
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3095999363
Short name T91
Test name
Test status
Simulation time 14434232 ps
CPU time 0.94 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 216776 kb
Host smart-59e93825-2c12-4788-be0e-a300c59ab5bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095999363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3095999363
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3345348685
Short name T506
Test name
Test status
Simulation time 50487823 ps
CPU time 1.15 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:58 PM PDT 24
Peak memory 217232 kb
Host smart-f18d64fc-41a2-44b3-b884-53f07d58a732
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345348685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3345348685
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2226349862
Short name T54
Test name
Test status
Simulation time 34637035 ps
CPU time 1.03 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 229216 kb
Host smart-81baa03b-826c-42e7-a589-ba8010f1f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226349862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2226349862
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1990766024
Short name T780
Test name
Test status
Simulation time 69011145 ps
CPU time 1.55 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:58 PM PDT 24
Peak memory 219160 kb
Host smart-50f8c777-77d2-4155-b359-d86e76020cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990766024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1990766024
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.1712539704
Short name T402
Test name
Test status
Simulation time 26356211 ps
CPU time 0.95 seconds
Started Jul 12 06:37:53 PM PDT 24
Finished Jul 12 06:37:55 PM PDT 24
Peak memory 215596 kb
Host smart-26b37531-7f46-48a1-b8e4-4f12639618e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712539704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1712539704
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2161590844
Short name T835
Test name
Test status
Simulation time 148355240 ps
CPU time 2.78 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:02 PM PDT 24
Peak memory 218640 kb
Host smart-cc6347db-18ee-434e-b52b-0e97b1d62cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161590844 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2161590844
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1459231700
Short name T434
Test name
Test status
Simulation time 25630558327 ps
CPU time 619.37 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:48:18 PM PDT 24
Peak memory 223960 kb
Host smart-a8a63abe-36ac-48f1-8f8c-7ba6532e4066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459231700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1459231700
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1045263
Short name T806
Test name
Test status
Simulation time 75130356 ps
CPU time 1.14 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:37:59 PM PDT 24
Peak memory 219820 kb
Host smart-fa23b530-e15a-4140-9efd-9b11c4c48a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1045263
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2029342992
Short name T783
Test name
Test status
Simulation time 67911572 ps
CPU time 0.85 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 214996 kb
Host smart-47699693-c1ff-4b60-aad4-269ec34e82c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029342992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2029342992
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2163222698
Short name T717
Test name
Test status
Simulation time 29316474 ps
CPU time 0.8 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 216628 kb
Host smart-30519afa-2caa-471b-950f-3b42d647b0a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163222698 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2163222698
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.886679026
Short name T128
Test name
Test status
Simulation time 54401937 ps
CPU time 1.65 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 217240 kb
Host smart-8f823809-7aec-41b0-b09d-d650cace6d07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886679026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.886679026
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3079403544
Short name T143
Test name
Test status
Simulation time 24167552 ps
CPU time 1.06 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 224248 kb
Host smart-19caddf2-3559-43f8-a007-5ac77188aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079403544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3079403544
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2025166930
Short name T672
Test name
Test status
Simulation time 41951048 ps
CPU time 1.56 seconds
Started Jul 12 06:37:56 PM PDT 24
Finished Jul 12 06:38:00 PM PDT 24
Peak memory 218648 kb
Host smart-4f1338fa-ba12-400f-81c9-e5a0614ac594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025166930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2025166930
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.427806273
Short name T666
Test name
Test status
Simulation time 38780525 ps
CPU time 0.9 seconds
Started Jul 12 06:37:55 PM PDT 24
Finished Jul 12 06:37:57 PM PDT 24
Peak memory 215732 kb
Host smart-8f3dd7c9-c0fe-4f54-b303-240978c4fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427806273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.427806273
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3069688181
Short name T710
Test name
Test status
Simulation time 31158701 ps
CPU time 0.98 seconds
Started Jul 12 06:37:52 PM PDT 24
Finished Jul 12 06:37:54 PM PDT 24
Peak memory 215576 kb
Host smart-d2d7a248-b4b8-4289-b1a6-6b7423b06f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069688181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3069688181
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.62527631
Short name T4
Test name
Test status
Simulation time 342072434 ps
CPU time 6.15 seconds
Started Jul 12 06:37:57 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 217584 kb
Host smart-01eab2eb-cfee-4254-87ef-c74647d9d108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62527631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.62527631
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2351777320
Short name T229
Test name
Test status
Simulation time 239221956782 ps
CPU time 1005.99 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:54:49 PM PDT 24
Peak memory 221824 kb
Host smart-5eb80322-0e90-4914-891b-b016867a4342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351777320 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2351777320
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2274804752
Short name T222
Test name
Test status
Simulation time 180378884 ps
CPU time 1.23 seconds
Started Jul 12 06:38:00 PM PDT 24
Finished Jul 12 06:38:02 PM PDT 24
Peak memory 220740 kb
Host smart-099a7fd1-e900-42b8-935c-a4d064b975b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274804752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2274804752
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2914168315
Short name T803
Test name
Test status
Simulation time 54220535 ps
CPU time 0.88 seconds
Started Jul 12 06:38:05 PM PDT 24
Finished Jul 12 06:38:08 PM PDT 24
Peak memory 206916 kb
Host smart-2c62b96c-557f-43f0-9257-d59207afcf1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914168315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2914168315
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.668481779
Short name T935
Test name
Test status
Simulation time 42304566 ps
CPU time 0.88 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 216648 kb
Host smart-9d05d304-3b88-4f29-98f5-41a436a9dc8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668481779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.668481779
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.751184709
Short name T205
Test name
Test status
Simulation time 37705119 ps
CPU time 1.23 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:10 PM PDT 24
Peak memory 217228 kb
Host smart-c8908be5-87d9-4924-94cc-fd67769ccecf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751184709 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.751184709
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.142639497
Short name T148
Test name
Test status
Simulation time 38978605 ps
CPU time 1.26 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 229988 kb
Host smart-1d5c92de-bf12-4db3-b991-4820629c2ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142639497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.142639497
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2112616821
Short name T779
Test name
Test status
Simulation time 263014338 ps
CPU time 3.45 seconds
Started Jul 12 06:38:09 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 220660 kb
Host smart-b5610091-b1c4-4363-87b0-7d080d5be8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112616821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2112616821
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2035002624
Short name T796
Test name
Test status
Simulation time 51497403 ps
CPU time 0.89 seconds
Started Jul 12 06:38:00 PM PDT 24
Finished Jul 12 06:38:02 PM PDT 24
Peak memory 215876 kb
Host smart-3625a293-1484-43e5-9e36-ba67f0d30b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035002624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2035002624
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.157505394
Short name T435
Test name
Test status
Simulation time 47481028 ps
CPU time 0.99 seconds
Started Jul 12 06:38:03 PM PDT 24
Finished Jul 12 06:38:07 PM PDT 24
Peak memory 207408 kb
Host smart-5f805ab9-f100-46d0-856b-88a6039002e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157505394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.157505394
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4061596860
Short name T413
Test name
Test status
Simulation time 64912748 ps
CPU time 1.78 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 217504 kb
Host smart-e2da1aef-2966-4dfa-b8d7-cc382a6cc608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061596860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4061596860
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.644405853
Short name T851
Test name
Test status
Simulation time 165108827481 ps
CPU time 720.01 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:50:07 PM PDT 24
Peak memory 221216 kb
Host smart-e57f3ebf-5a30-4fbf-a52c-58d119b7a454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644405853 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.644405853
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1617548970
Short name T319
Test name
Test status
Simulation time 126669309 ps
CPU time 1.23 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 219508 kb
Host smart-a0700a6d-d939-4c75-a119-c32b7bd98858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617548970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1617548970
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1211096502
Short name T459
Test name
Test status
Simulation time 12468962 ps
CPU time 0.88 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 207248 kb
Host smart-4385b5f0-0052-479f-80dc-2b955880853b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211096502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1211096502
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3776216853
Short name T873
Test name
Test status
Simulation time 42534987 ps
CPU time 0.88 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 216616 kb
Host smart-0ff7ef44-14c4-4c35-93c1-4acc6c5d8ad5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776216853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3776216853
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3830371916
Short name T127
Test name
Test status
Simulation time 26559165 ps
CPU time 1.14 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 217220 kb
Host smart-b61ddad4-6cbb-478c-acdf-9ac2e0c52ef8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830371916 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3830371916
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1939362610
Short name T990
Test name
Test status
Simulation time 42404102 ps
CPU time 1.26 seconds
Started Jul 12 06:37:59 PM PDT 24
Finished Jul 12 06:38:02 PM PDT 24
Peak memory 226108 kb
Host smart-e0e99901-df9f-4dec-88cb-ae4e0a1a2937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939362610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1939362610
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4015679285
Short name T509
Test name
Test status
Simulation time 85726841 ps
CPU time 1.14 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 220392 kb
Host smart-dabfbf61-237e-41b1-9187-40b5bc55c0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015679285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4015679285
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3655272971
Short name T34
Test name
Test status
Simulation time 35803226 ps
CPU time 0.91 seconds
Started Jul 12 06:38:03 PM PDT 24
Finished Jul 12 06:38:07 PM PDT 24
Peak memory 215848 kb
Host smart-c9ad7706-ca4b-4ad3-9ed0-8cef40a67e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655272971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3655272971
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.409338299
Short name T585
Test name
Test status
Simulation time 17231463 ps
CPU time 1.02 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 215628 kb
Host smart-7018d70f-97bf-4277-b464-23d6d79b6496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409338299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.409338299
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1600881450
Short name T597
Test name
Test status
Simulation time 313438753 ps
CPU time 6.17 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:22 PM PDT 24
Peak memory 217436 kb
Host smart-cd7f5c26-3b81-480d-b1a7-acc5619c7a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600881450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1600881450
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4290463811
Short name T653
Test name
Test status
Simulation time 858136292509 ps
CPU time 1001.09 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:54:57 PM PDT 24
Peak memory 222844 kb
Host smart-16c967c5-a292-43da-9e6a-d553f5d7eb21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290463811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4290463811
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.479209775
Short name T535
Test name
Test status
Simulation time 39337393 ps
CPU time 1.18 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 219544 kb
Host smart-27d01df1-88d0-44f7-8d11-2921cf2762fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479209775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.479209775
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1754614941
Short name T464
Test name
Test status
Simulation time 43114980 ps
CPU time 0.92 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 207056 kb
Host smart-1d7226b5-32d3-4db0-ad75-a3452d58219f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754614941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1754614941
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2191191471
Short name T741
Test name
Test status
Simulation time 20483389 ps
CPU time 0.87 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 215700 kb
Host smart-0e4a8997-2a6b-447d-b49a-7195999e6116
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191191471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2191191471
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2481343664
Short name T816
Test name
Test status
Simulation time 59238502 ps
CPU time 1.15 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:38:08 PM PDT 24
Peak memory 217192 kb
Host smart-f3b9b93d-08c8-47a7-85c3-7834e3f04f30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481343664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2481343664
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.707591569
Short name T137
Test name
Test status
Simulation time 32148014 ps
CPU time 0.92 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 220040 kb
Host smart-1b47c28a-7436-4767-88c1-1e3d85378208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707591569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.707591569
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_intr.1333673360
Short name T544
Test name
Test status
Simulation time 22876212 ps
CPU time 1.25 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 224300 kb
Host smart-5546636b-5b15-4f78-9735-ac2bd7f753c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333673360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1333673360
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2838522656
Short name T620
Test name
Test status
Simulation time 17589434 ps
CPU time 1.02 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 215564 kb
Host smart-bbc5653b-c55a-492b-8a30-e2e4501b4f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838522656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2838522656
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1550309686
Short name T616
Test name
Test status
Simulation time 224741338 ps
CPU time 2.92 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:07 PM PDT 24
Peak memory 215448 kb
Host smart-d9561db5-9577-4fe1-9a95-e07e2c495061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550309686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1550309686
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2525745656
Short name T901
Test name
Test status
Simulation time 72901695481 ps
CPU time 1157.64 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:57:33 PM PDT 24
Peak memory 223976 kb
Host smart-aa1d5a9b-f46a-4881-8671-ac4f6fab80c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525745656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2525745656
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1011728057
Short name T473
Test name
Test status
Simulation time 25033872 ps
CPU time 1.23 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:04 PM PDT 24
Peak memory 220272 kb
Host smart-41dc61bc-50ef-42b6-94e6-0efe73e80ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011728057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1011728057
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.414035306
Short name T112
Test name
Test status
Simulation time 14741327 ps
CPU time 0.88 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:38:07 PM PDT 24
Peak memory 206996 kb
Host smart-6ed2c4c2-0f2b-484a-bdec-71cee7668dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414035306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.414035306
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.369976766
Short name T422
Test name
Test status
Simulation time 61411804 ps
CPU time 0.97 seconds
Started Jul 12 06:38:05 PM PDT 24
Finished Jul 12 06:38:08 PM PDT 24
Peak memory 218688 kb
Host smart-4565abaf-114a-4e0f-a6e3-f721dc5f65a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369976766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.369976766
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3364823229
Short name T175
Test name
Test status
Simulation time 31125602 ps
CPU time 0.9 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:38:07 PM PDT 24
Peak memory 218552 kb
Host smart-91aaa9d3-1061-49d7-87dc-f88f7d856afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364823229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3364823229
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4266255894
Short name T481
Test name
Test status
Simulation time 35535259 ps
CPU time 1.37 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 218600 kb
Host smart-74787187-757b-4478-a3c3-87bce89be207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266255894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4266255894
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3519942088
Short name T37
Test name
Test status
Simulation time 25398617 ps
CPU time 0.93 seconds
Started Jul 12 06:38:03 PM PDT 24
Finished Jul 12 06:38:06 PM PDT 24
Peak memory 216220 kb
Host smart-5054c7ad-f0e3-447f-859b-01a9ddeb8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519942088 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3519942088
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2042549092
Short name T976
Test name
Test status
Simulation time 44711696 ps
CPU time 0.95 seconds
Started Jul 12 06:38:05 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 215568 kb
Host smart-da2e3dce-c8ee-42ee-94c3-482c4eef67ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042549092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2042549092
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2189536077
Short name T775
Test name
Test status
Simulation time 699111671 ps
CPU time 4.02 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:06 PM PDT 24
Peak memory 220536 kb
Host smart-d96fa79d-990a-42a5-8585-df379f17b099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189536077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2189536077
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3808997421
Short name T706
Test name
Test status
Simulation time 317152352267 ps
CPU time 1876.56 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 07:09:20 PM PDT 24
Peak memory 226784 kb
Host smart-41da52c6-1016-4453-93ed-dde003230daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808997421 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3808997421
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3362073666
Short name T671
Test name
Test status
Simulation time 25364893 ps
CPU time 1.21 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 218896 kb
Host smart-51cd6bfd-f3e6-4e85-ac41-7bac809121c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362073666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3362073666
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2529522480
Short name T573
Test name
Test status
Simulation time 37888605 ps
CPU time 0.86 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 206812 kb
Host smart-d097294d-3900-4763-b784-c7bb7afe19f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529522480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2529522480
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1334401264
Short name T897
Test name
Test status
Simulation time 27339990 ps
CPU time 0.86 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 216232 kb
Host smart-d9d1d75c-e2c4-4d04-8b15-f65ec9baeb83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334401264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1334401264
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1589123431
Short name T712
Test name
Test status
Simulation time 20829095 ps
CPU time 0.98 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 217116 kb
Host smart-aefea76f-8e4e-47bf-8c89-4b3a0b75a756
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589123431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1589123431
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1084231796
Short name T165
Test name
Test status
Simulation time 19769760 ps
CPU time 1.18 seconds
Started Jul 12 06:37:59 PM PDT 24
Finished Jul 12 06:38:01 PM PDT 24
Peak memory 224252 kb
Host smart-1385a6d4-f45d-4ae4-8b10-20a81ee19ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084231796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1084231796
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1722922956
Short name T872
Test name
Test status
Simulation time 57580164 ps
CPU time 1.08 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:03 PM PDT 24
Peak memory 217576 kb
Host smart-57d0d5cd-a3c2-4947-ba7f-fca69ef398f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722922956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1722922956
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.975465216
Short name T489
Test name
Test status
Simulation time 33728087 ps
CPU time 0.84 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:38:08 PM PDT 24
Peak memory 216060 kb
Host smart-7dd2d013-70f5-4a0c-8394-c69b14c474dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975465216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.975465216
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1274514694
Short name T335
Test name
Test status
Simulation time 17837844 ps
CPU time 0.98 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 215568 kb
Host smart-0f7f7a13-afc8-499c-9416-262bcaa123a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274514694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1274514694
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2891999598
Short name T631
Test name
Test status
Simulation time 819331397 ps
CPU time 5.09 seconds
Started Jul 12 06:38:04 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 217448 kb
Host smart-0d1cc187-b8c1-4f7f-b831-1fdc3002c5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891999598 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2891999598
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2780140141
Short name T721
Test name
Test status
Simulation time 21027394810 ps
CPU time 331.4 seconds
Started Jul 12 06:38:05 PM PDT 24
Finished Jul 12 06:43:39 PM PDT 24
Peak memory 218200 kb
Host smart-4705b597-9fce-40a8-a6c6-afaeb93b1616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780140141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2780140141
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3769447625
Short name T767
Test name
Test status
Simulation time 26504820 ps
CPU time 1.22 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 218712 kb
Host smart-c4857e7a-01a0-4f51-8650-3826655f2d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769447625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3769447625
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2934889269
Short name T63
Test name
Test status
Simulation time 49329271 ps
CPU time 1.45 seconds
Started Jul 12 06:38:13 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 207072 kb
Host smart-3cc74ac5-cc5d-496d-9fc2-52f78df9704f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934889269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2934889269
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3628312530
Short name T563
Test name
Test status
Simulation time 12494875 ps
CPU time 0.91 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 216696 kb
Host smart-9f9dc5d2-df38-4de3-854c-ab2cc6a80185
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628312530 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3628312530
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4066100880
Short name T123
Test name
Test status
Simulation time 60747802 ps
CPU time 1.28 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 217156 kb
Host smart-91a83f51-fa93-42e2-a46a-1ec25f4d0415
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066100880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4066100880
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3146530828
Short name T167
Test name
Test status
Simulation time 79027483 ps
CPU time 1.19 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 226120 kb
Host smart-496b42b7-57f4-4451-83b0-da6db254d6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146530828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3146530828
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3183590493
Short name T530
Test name
Test status
Simulation time 60051410 ps
CPU time 1.21 seconds
Started Jul 12 06:38:01 PM PDT 24
Finished Jul 12 06:38:03 PM PDT 24
Peak memory 219640 kb
Host smart-37cfdcb8-3a1b-475a-8e1e-bf23928b5bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183590493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3183590493
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2525675264
Short name T583
Test name
Test status
Simulation time 37479850 ps
CPU time 0.88 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:13 PM PDT 24
Peak memory 215592 kb
Host smart-ec9a0622-d562-4ec8-a591-b52a2cdb4d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525675264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2525675264
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4103343589
Short name T738
Test name
Test status
Simulation time 15718382 ps
CPU time 0.96 seconds
Started Jul 12 06:38:03 PM PDT 24
Finished Jul 12 06:38:06 PM PDT 24
Peak memory 215596 kb
Host smart-68fe4a3f-40f7-43f5-977a-6666228fc927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103343589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4103343589
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2377296035
Short name T853
Test name
Test status
Simulation time 244384943 ps
CPU time 5.2 seconds
Started Jul 12 06:38:02 PM PDT 24
Finished Jul 12 06:38:09 PM PDT 24
Peak memory 217432 kb
Host smart-0af34ffa-0230-4b86-b381-7b356821bfaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377296035 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2377296035
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2744012088
Short name T640
Test name
Test status
Simulation time 181800248742 ps
CPU time 2038.67 seconds
Started Jul 12 06:38:05 PM PDT 24
Finished Jul 12 07:12:06 PM PDT 24
Peak memory 226780 kb
Host smart-9029a558-b460-40e1-8f78-b27c6aee431c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744012088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2744012088
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2335556278
Short name T320
Test name
Test status
Simulation time 75723995 ps
CPU time 1.11 seconds
Started Jul 12 06:38:20 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 220128 kb
Host smart-19b10c0f-7209-4d35-afef-837220f9eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335556278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2335556278
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2041438717
Short name T936
Test name
Test status
Simulation time 23627029 ps
CPU time 0.88 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 207012 kb
Host smart-9ed0bd64-71f3-420f-8355-cdfb49e2f2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041438717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2041438717
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1520910307
Short name T921
Test name
Test status
Simulation time 18196321 ps
CPU time 0.82 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 216632 kb
Host smart-fa8a3821-df13-41be-9bcf-17b41b6192c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520910307 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1520910307
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3500529045
Short name T593
Test name
Test status
Simulation time 50289207 ps
CPU time 1.22 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 218848 kb
Host smart-97a20837-efde-4026-bfb9-886161e915f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500529045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3500529045
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1289072348
Short name T15
Test name
Test status
Simulation time 44623916 ps
CPU time 1.22 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 226084 kb
Host smart-257ee61f-758c-48c3-bd20-18f8de62e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289072348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1289072348
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2365757946
Short name T485
Test name
Test status
Simulation time 42006905 ps
CPU time 1.41 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 217588 kb
Host smart-22150cef-8849-4492-90db-7ad7249f351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365757946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2365757946
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2413185565
Short name T852
Test name
Test status
Simulation time 51510453 ps
CPU time 0.85 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 215500 kb
Host smart-8bb755e5-f2cb-4365-b9e6-4f33e0adee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413185565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2413185565
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.912286630
Short name T875
Test name
Test status
Simulation time 16462463 ps
CPU time 0.99 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 215624 kb
Host smart-e1570175-db1a-4bee-acc7-72bd7d48abc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912286630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.912286630
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.904768005
Short name T681
Test name
Test status
Simulation time 534396824 ps
CPU time 3.33 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 217332 kb
Host smart-530ca892-16a1-4019-acaa-c76308c98ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904768005 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.904768005
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.529706766
Short name T233
Test name
Test status
Simulation time 420080802166 ps
CPU time 1228.98 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:58:39 PM PDT 24
Peak memory 224040 kb
Host smart-441fb766-2377-467b-8ffc-06c745d2e86b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529706766 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.529706766
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4151364196
Short name T117
Test name
Test status
Simulation time 28652735 ps
CPU time 1.29 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 215968 kb
Host smart-398b795a-f2b5-4fbf-83c3-10d99774dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151364196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4151364196
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.62941139
Short name T812
Test name
Test status
Simulation time 19803032 ps
CPU time 1.04 seconds
Started Jul 12 06:38:09 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 207240 kb
Host smart-19538e07-7d68-4546-9787-190db6331662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62941139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.62941139
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.735121382
Short name T122
Test name
Test status
Simulation time 63537642 ps
CPU time 1.21 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 217100 kb
Host smart-fce50eb1-ff40-4f39-a892-08ffe6e0d885
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735121382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.735121382
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3210553879
Short name T169
Test name
Test status
Simulation time 30826969 ps
CPU time 1.42 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:15 PM PDT 24
Peak memory 226028 kb
Host smart-3573df50-0ae1-4b68-b170-39ae20203d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210553879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3210553879
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1006574840
Short name T876
Test name
Test status
Simulation time 348952771 ps
CPU time 1.91 seconds
Started Jul 12 06:38:18 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 220256 kb
Host smart-728f6071-ffed-41d8-ba09-6fe21668561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006574840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1006574840
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1160082325
Short name T51
Test name
Test status
Simulation time 39923426 ps
CPU time 1.01 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 224136 kb
Host smart-21f8fe09-86ca-446b-8331-d504e4506f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160082325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1160082325
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4184042083
Short name T923
Test name
Test status
Simulation time 15240290 ps
CPU time 1.01 seconds
Started Jul 12 06:38:06 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 215584 kb
Host smart-5e074e87-3079-4bc7-a4c5-324e104b8f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184042083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4184042083
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3318106747
Short name T948
Test name
Test status
Simulation time 691017230 ps
CPU time 3.72 seconds
Started Jul 12 06:38:12 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 219940 kb
Host smart-77c997b1-3619-4338-96c2-6f5cf7d58c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318106747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3318106747
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2288610730
Short name T490
Test name
Test status
Simulation time 32751829848 ps
CPU time 406.15 seconds
Started Jul 12 06:38:09 PM PDT 24
Finished Jul 12 06:45:00 PM PDT 24
Peak memory 218584 kb
Host smart-2554546d-5357-482f-90bb-7541c3e9e079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288610730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2288610730
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3409868078
Short name T760
Test name
Test status
Simulation time 68112670 ps
CPU time 1.14 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 219164 kb
Host smart-ca258e72-361d-468c-832d-652e296b872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409868078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3409868078
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1032910954
Short name T798
Test name
Test status
Simulation time 19837360 ps
CPU time 0.84 seconds
Started Jul 12 06:46:06 PM PDT 24
Finished Jul 12 06:46:08 PM PDT 24
Peak memory 206844 kb
Host smart-cabf9ba2-8e04-478c-8be5-d9bc59801fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032910954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1032910954
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2365597115
Short name T452
Test name
Test status
Simulation time 12367000 ps
CPU time 0.93 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 215884 kb
Host smart-95a3100d-82a9-46d9-9b38-782536f71b98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365597115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2365597115
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.1562251606
Short name T155
Test name
Test status
Simulation time 33145020 ps
CPU time 1.02 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 220860 kb
Host smart-f43d2fad-ff6d-4cd3-82be-4bbfdc3ac9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562251606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1562251606
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2537072129
Short name T946
Test name
Test status
Simulation time 35039236 ps
CPU time 1.47 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:53 PM PDT 24
Peak memory 218860 kb
Host smart-bde71d08-c056-4aa3-900a-e01fa3223ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537072129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2537072129
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4038057070
Short name T57
Test name
Test status
Simulation time 26001856 ps
CPU time 1.1 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:53 PM PDT 24
Peak memory 224604 kb
Host smart-0239f751-4d01-424e-a977-dcf25521d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038057070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4038057070
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3353826328
Short name T28
Test name
Test status
Simulation time 45265842 ps
CPU time 0.95 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 207396 kb
Host smart-fef73786-4c8d-4293-8949-77858a662526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353826328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3353826328
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1035493317
Short name T919
Test name
Test status
Simulation time 35999530 ps
CPU time 0.95 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 215612 kb
Host smart-e6d0dc0c-bb3b-4b64-98a1-82c0b8ef0cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035493317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1035493317
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2503261714
Short name T390
Test name
Test status
Simulation time 41970304 ps
CPU time 1.05 seconds
Started Jul 12 06:36:50 PM PDT 24
Finished Jul 12 06:36:54 PM PDT 24
Peak memory 215584 kb
Host smart-bcc96a5d-74ee-4e0c-8c16-4c79f920a41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503261714 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2503261714
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2961564083
Short name T408
Test name
Test status
Simulation time 19292355705 ps
CPU time 497.08 seconds
Started Jul 12 06:36:49 PM PDT 24
Finished Jul 12 06:45:08 PM PDT 24
Peak memory 218676 kb
Host smart-915ba383-c895-4f26-b933-584e501c1a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961564083 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2961564083
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.405489186
Short name T826
Test name
Test status
Simulation time 88392307 ps
CPU time 1.29 seconds
Started Jul 12 06:38:13 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 218756 kb
Host smart-4b8e2f63-1bd7-4953-bf3f-fc6aa8d9f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405489186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.405489186
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.136666063
Short name T494
Test name
Test status
Simulation time 27161660 ps
CPU time 0.93 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:12 PM PDT 24
Peak memory 218364 kb
Host smart-7732cd98-06f3-4127-8f3d-e66c1d9f4dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136666063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.136666063
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3525348452
Short name T9
Test name
Test status
Simulation time 104129192 ps
CPU time 2.23 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 220452 kb
Host smart-81ec1c56-2b03-44a5-ac42-a1df25a8886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525348452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3525348452
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3184219824
Short name T184
Test name
Test status
Simulation time 24937357 ps
CPU time 1.22 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 219860 kb
Host smart-040d0204-150b-4bb2-95bc-418165882164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184219824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3184219824
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2598095610
Short name T988
Test name
Test status
Simulation time 54632617 ps
CPU time 1.03 seconds
Started Jul 12 06:38:13 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 218880 kb
Host smart-861685d2-ccc5-4770-8014-3bd757377d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598095610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2598095610
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1450317733
Short name T754
Test name
Test status
Simulation time 51515238 ps
CPU time 1.76 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:16 PM PDT 24
Peak memory 218852 kb
Host smart-5b960453-2d1d-44a1-9c15-da8519fd8e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450317733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1450317733
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3892507131
Short name T81
Test name
Test status
Simulation time 21144182 ps
CPU time 0.92 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 218816 kb
Host smart-4f3623fe-d2ec-4509-abac-b6aff57b819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892507131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3892507131
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1928272375
Short name T574
Test name
Test status
Simulation time 170589695 ps
CPU time 1.92 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 219480 kb
Host smart-172f7d58-28d7-41a8-a186-70c810a61438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928272375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1928272375
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.494951399
Short name T323
Test name
Test status
Simulation time 39656879 ps
CPU time 1.16 seconds
Started Jul 12 06:38:12 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 220120 kb
Host smart-96359190-8394-4cc9-a4fd-29ddc4094b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494951399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.494951399
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.588764800
Short name T679
Test name
Test status
Simulation time 52433428 ps
CPU time 0.88 seconds
Started Jul 12 06:38:07 PM PDT 24
Finished Jul 12 06:38:11 PM PDT 24
Peak memory 218756 kb
Host smart-077725df-0e78-4977-a2b4-15d594a9b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588764800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.588764800
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3337061919
Short name T858
Test name
Test status
Simulation time 130168034 ps
CPU time 2.05 seconds
Started Jul 12 06:38:10 PM PDT 24
Finished Jul 12 06:38:17 PM PDT 24
Peak memory 220552 kb
Host smart-4601318a-df5c-40ba-81ae-a63a5a0fd2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337061919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3337061919
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3554716189
Short name T158
Test name
Test status
Simulation time 116236769 ps
CPU time 1.19 seconds
Started Jul 12 06:38:08 PM PDT 24
Finished Jul 12 06:38:14 PM PDT 24
Peak memory 218720 kb
Host smart-3783ad15-8edd-4e6e-95d9-6d20e905a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554716189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3554716189
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2552469753
Short name T185
Test name
Test status
Simulation time 18934102 ps
CPU time 1.09 seconds
Started Jul 12 06:38:21 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 218768 kb
Host smart-b9d1e4e8-7724-44b0-a8a1-cf81099c756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552469753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2552469753
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1766948233
Short name T924
Test name
Test status
Simulation time 119357427 ps
CPU time 1.49 seconds
Started Jul 12 06:38:11 PM PDT 24
Finished Jul 12 06:38:18 PM PDT 24
Peak memory 217660 kb
Host smart-dcae6c3b-b31a-4c87-8efd-fda71b642c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766948233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1766948233
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1427610717
Short name T318
Test name
Test status
Simulation time 38708213 ps
CPU time 1.08 seconds
Started Jul 12 06:38:19 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218952 kb
Host smart-7555eec9-cae7-4be4-988c-a27dc024448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427610717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1427610717
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1400374080
Short name T933
Test name
Test status
Simulation time 55681212 ps
CPU time 1.23 seconds
Started Jul 12 06:38:20 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 219988 kb
Host smart-e7bbcad3-0122-4a56-8697-5fe47a203d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400374080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1400374080
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2129317539
Short name T440
Test name
Test status
Simulation time 41878695 ps
CPU time 1.51 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 217812 kb
Host smart-577eb1c3-1d6f-4fc5-99e3-09f0e7fb59c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129317539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2129317539
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2570175879
Short name T73
Test name
Test status
Simulation time 120495609 ps
CPU time 1.21 seconds
Started Jul 12 06:38:14 PM PDT 24
Finished Jul 12 06:38:19 PM PDT 24
Peak memory 219936 kb
Host smart-c9115478-0f95-4355-970f-c618344a3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570175879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2570175879
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1911765482
Short name T430
Test name
Test status
Simulation time 23016896 ps
CPU time 0.96 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 218772 kb
Host smart-98201c6d-cfdb-4c5e-8c0e-5e4958072eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911765482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1911765482
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2988902922
Short name T676
Test name
Test status
Simulation time 53114860 ps
CPU time 1.77 seconds
Started Jul 12 06:38:17 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218880 kb
Host smart-476d3f44-bd9b-45a0-8267-bcfd666dc0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988902922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2988902922
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.911648609
Short name T906
Test name
Test status
Simulation time 64770511 ps
CPU time 1.14 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 219064 kb
Host smart-7d829fc1-1011-4e77-b4ae-dc05dcf69b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911648609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.911648609
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.826432936
Short name T975
Test name
Test status
Simulation time 23674387 ps
CPU time 1.2 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 218824 kb
Host smart-5c31c9fb-eba3-432e-a2ec-9b2712bc474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826432936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.826432936
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1054265657
Short name T547
Test name
Test status
Simulation time 58227581 ps
CPU time 1.31 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 217452 kb
Host smart-13757ee0-5073-4297-90a5-066eacccea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054265657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1054265657
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.786084005
Short name T747
Test name
Test status
Simulation time 27779283 ps
CPU time 1.17 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 221012 kb
Host smart-ff9198c6-b2f4-4f4d-9b30-f6ee0bc97d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786084005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.786084005
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_genbits.3792934128
Short name T669
Test name
Test status
Simulation time 73335020 ps
CPU time 1.02 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 217436 kb
Host smart-07f5dfbb-98f4-4c56-a233-087fbfaa0c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792934128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3792934128
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1455143672
Short name T888
Test name
Test status
Simulation time 25641927 ps
CPU time 1.19 seconds
Started Jul 12 06:38:19 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218656 kb
Host smart-0774a487-8e9f-404d-988b-c8c046f7c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455143672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1455143672
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1536744996
Short name T572
Test name
Test status
Simulation time 25088210 ps
CPU time 0.94 seconds
Started Jul 12 06:38:19 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218908 kb
Host smart-262a5a80-a384-45f7-9483-975548c29db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536744996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1536744996
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3350785035
Short name T659
Test name
Test status
Simulation time 94259305 ps
CPU time 1.4 seconds
Started Jul 12 06:38:19 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218976 kb
Host smart-3a29d35f-b657-444c-ae5f-193039cf8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350785035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3350785035
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3116325876
Short name T62
Test name
Test status
Simulation time 333548602 ps
CPU time 1.26 seconds
Started Jul 12 06:36:56 PM PDT 24
Finished Jul 12 06:36:59 PM PDT 24
Peak memory 218760 kb
Host smart-4d56da53-c1a4-4161-83b5-d0c81500952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116325876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3116325876
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3959919585
Short name T730
Test name
Test status
Simulation time 145210370 ps
CPU time 0.88 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:02 PM PDT 24
Peak memory 206660 kb
Host smart-1d53d677-56ac-4dc1-8d11-210da69281d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959919585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3959919585
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2897231612
Short name T176
Test name
Test status
Simulation time 34232551 ps
CPU time 0.96 seconds
Started Jul 12 06:36:57 PM PDT 24
Finished Jul 12 06:37:00 PM PDT 24
Peak memory 216500 kb
Host smart-11e849c1-1a8c-4e6f-8e5c-19895aec0d71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897231612 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2897231612
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4212162192
Short name T553
Test name
Test status
Simulation time 65902632 ps
CPU time 1.27 seconds
Started Jul 12 06:37:01 PM PDT 24
Finished Jul 12 06:37:04 PM PDT 24
Peak memory 217220 kb
Host smart-f73e59fd-8ea0-4ddc-ab3b-2435c72a1777
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212162192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4212162192
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2374382942
Short name T536
Test name
Test status
Simulation time 23103146 ps
CPU time 1.02 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:02 PM PDT 24
Peak memory 224152 kb
Host smart-90219289-a297-4c3c-a2a4-76d570a755d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374382942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2374382942
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.540915507
Short name T472
Test name
Test status
Simulation time 44897625 ps
CPU time 1.05 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 217540 kb
Host smart-6e3b2747-c921-40f7-a6c7-dbb6e844369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540915507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.540915507
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.69447600
Short name T429
Test name
Test status
Simulation time 28222166 ps
CPU time 0.95 seconds
Started Jul 12 06:36:57 PM PDT 24
Finished Jul 12 06:36:59 PM PDT 24
Peak memory 215692 kb
Host smart-8890c15c-4cf4-40e0-a57b-991d83d233ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69447600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.69447600
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3325025132
Short name T830
Test name
Test status
Simulation time 125051702 ps
CPU time 0.89 seconds
Started Jul 12 06:36:49 PM PDT 24
Finished Jul 12 06:36:51 PM PDT 24
Peak memory 207396 kb
Host smart-8454bc2f-9c87-41a6-bc6c-7a1ce4b726f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325025132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3325025132
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1692160244
Short name T357
Test name
Test status
Simulation time 38361300 ps
CPU time 0.9 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 207340 kb
Host smart-8c897358-36ec-4c63-a236-e9759c73726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692160244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1692160244
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1490660564
Short name T729
Test name
Test status
Simulation time 2090787375 ps
CPU time 5.01 seconds
Started Jul 12 06:36:57 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 217464 kb
Host smart-04fcca61-edef-45e2-916a-2e5c0253c4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490660564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1490660564
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2765144770
Short name T910
Test name
Test status
Simulation time 626027514792 ps
CPU time 2514.5 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 07:18:55 PM PDT 24
Peak memory 232432 kb
Host smart-2b1ae6f6-d374-4830-9e72-b1bb87f8dae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765144770 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2765144770
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1525323828
Short name T761
Test name
Test status
Simulation time 95108060 ps
CPU time 1.1 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 220080 kb
Host smart-de9ddc3a-6545-4533-85bc-7ec2ede6665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525323828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1525323828
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.851164192
Short name T697
Test name
Test status
Simulation time 59727424 ps
CPU time 1.15 seconds
Started Jul 12 06:38:17 PM PDT 24
Finished Jul 12 06:38:22 PM PDT 24
Peak memory 220868 kb
Host smart-aad923de-e5b1-4af4-8c91-3b5db5b8b3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851164192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.851164192
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.336503318
Short name T945
Test name
Test status
Simulation time 233602500 ps
CPU time 1.46 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 219288 kb
Host smart-eb20f746-2f77-4d5a-b66a-d4e97cab5c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336503318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.336503318
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1984780091
Short name T868
Test name
Test status
Simulation time 111281530 ps
CPU time 1.14 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 218752 kb
Host smart-ddf03b6f-1141-44c6-98e3-1bd672ff2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984780091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1984780091
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3502917105
Short name T532
Test name
Test status
Simulation time 27265932 ps
CPU time 1.18 seconds
Started Jul 12 06:38:14 PM PDT 24
Finished Jul 12 06:38:19 PM PDT 24
Peak memory 224236 kb
Host smart-d97fad5e-3f40-490d-9632-089160061f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502917105 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3502917105
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.579058706
Short name T518
Test name
Test status
Simulation time 46914298 ps
CPU time 1.16 seconds
Started Jul 12 06:38:18 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 217816 kb
Host smart-9782ba43-0534-4eed-a603-32299cbcb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579058706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.579058706
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2020973997
Short name T26
Test name
Test status
Simulation time 78448535 ps
CPU time 1.22 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:22 PM PDT 24
Peak memory 220776 kb
Host smart-836c09b4-821c-4586-9728-401b25c72105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020973997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2020973997
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1259410565
Short name T170
Test name
Test status
Simulation time 35362224 ps
CPU time 1 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:20 PM PDT 24
Peak memory 223872 kb
Host smart-de78b2e0-2d33-4d46-a505-00d20e6eb7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259410565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1259410565
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2701059198
Short name T860
Test name
Test status
Simulation time 105936886 ps
CPU time 1.15 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 217508 kb
Host smart-51282952-849a-4339-aaf4-f46c623d6090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701059198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2701059198
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2784639583
Short name T274
Test name
Test status
Simulation time 82770662 ps
CPU time 1.22 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 218832 kb
Host smart-1286d474-1e4e-4d39-bf37-42ba620fb283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784639583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2784639583
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2579218966
Short name T173
Test name
Test status
Simulation time 18016639 ps
CPU time 1.09 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 218820 kb
Host smart-d43b2551-a156-4d87-a9fa-dd4d239ba2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579218966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2579218966
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3026776646
Short name T13
Test name
Test status
Simulation time 35105316 ps
CPU time 1.3 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 218824 kb
Host smart-76cc9e32-8b9a-4aa7-b0b6-07c33703fb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026776646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3026776646
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2035153379
Short name T886
Test name
Test status
Simulation time 28711582 ps
CPU time 1.26 seconds
Started Jul 12 06:38:20 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 218888 kb
Host smart-bbedb97a-b1b4-44ff-99a1-dc946c8a054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035153379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2035153379
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2172185912
Short name T588
Test name
Test status
Simulation time 28407964 ps
CPU time 0.89 seconds
Started Jul 12 06:38:17 PM PDT 24
Finished Jul 12 06:38:22 PM PDT 24
Peak memory 218256 kb
Host smart-98d16db2-71cf-4dde-b7a8-0989e4c90278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172185912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2172185912
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_alert.2636992284
Short name T178
Test name
Test status
Simulation time 27828917 ps
CPU time 1.26 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 221276 kb
Host smart-d8db5b5e-4400-4e81-8fbc-9930d0233dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636992284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2636992284
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.780391168
Short name T209
Test name
Test status
Simulation time 25057012 ps
CPU time 0.99 seconds
Started Jul 12 06:38:18 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 219956 kb
Host smart-ec7ab3d3-5e0c-4c71-8c48-8146bb73b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780391168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.780391168
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4284015416
Short name T534
Test name
Test status
Simulation time 29838028 ps
CPU time 1.38 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:26 PM PDT 24
Peak memory 218752 kb
Host smart-3ae37c94-ad13-408c-ad88-2842f9304302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284015416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4284015416
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3708020237
Short name T142
Test name
Test status
Simulation time 41156770 ps
CPU time 1.22 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 221072 kb
Host smart-7bee9d2c-22c6-4009-986b-8a1b78a51a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708020237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3708020237
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1223335410
Short name T685
Test name
Test status
Simulation time 19975496 ps
CPU time 1.05 seconds
Started Jul 12 06:38:16 PM PDT 24
Finished Jul 12 06:38:22 PM PDT 24
Peak memory 218672 kb
Host smart-039c5a69-2b0d-4346-a7d8-8db4cf1e35e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223335410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1223335410
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2971891074
Short name T787
Test name
Test status
Simulation time 42984994 ps
CPU time 1.5 seconds
Started Jul 12 06:38:18 PM PDT 24
Finished Jul 12 06:38:23 PM PDT 24
Peak memory 218920 kb
Host smart-d03bb439-0bcc-4f92-818c-b6fec0875ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971891074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2971891074
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.112748644
Short name T989
Test name
Test status
Simulation time 27779582 ps
CPU time 1.29 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 215980 kb
Host smart-3f3d3f3b-b45a-48ca-8f9e-db00ae5abd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112748644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.112748644
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1158306335
Short name T115
Test name
Test status
Simulation time 33212812 ps
CPU time 0.92 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:26 PM PDT 24
Peak memory 220108 kb
Host smart-1dcdcc42-b3e2-4060-80e8-96586bde37f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158306335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1158306335
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3411918586
Short name T977
Test name
Test status
Simulation time 83322199 ps
CPU time 1.68 seconds
Started Jul 12 06:38:15 PM PDT 24
Finished Jul 12 06:38:21 PM PDT 24
Peak memory 219168 kb
Host smart-0720b34d-f452-4530-9a84-eb6129758993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411918586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3411918586
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.537495972
Short name T594
Test name
Test status
Simulation time 88671257 ps
CPU time 1.19 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 218948 kb
Host smart-1d2e4e0e-ad72-4c39-b171-bbf169036194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537495972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.537495972
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1345866970
Short name T577
Test name
Test status
Simulation time 20807667 ps
CPU time 0.91 seconds
Started Jul 12 06:38:21 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 218776 kb
Host smart-c545d7d1-246e-4159-98a8-a671e05083d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345866970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1345866970
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.766621161
Short name T739
Test name
Test status
Simulation time 63048838 ps
CPU time 1.36 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 217672 kb
Host smart-7dead3f8-4c78-4053-9ca8-f3755c9722c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766621161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.766621161
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.518997336
Short name T30
Test name
Test status
Simulation time 25975389 ps
CPU time 1.27 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 220116 kb
Host smart-00aa2bd9-4035-410e-b188-cf52abd576a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518997336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.518997336
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3115674924
Short name T133
Test name
Test status
Simulation time 51837007 ps
CPU time 0.99 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 220976 kb
Host smart-68f2c2d1-6cd5-470c-81ed-8cb7aff77508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115674924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3115674924
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.1535260852
Short name T317
Test name
Test status
Simulation time 27608196 ps
CPU time 1.3 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 06:37:00 PM PDT 24
Peak memory 219760 kb
Host smart-d4a33327-9000-4237-94bd-b7e505bbbe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535260852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1535260852
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3674651924
Short name T364
Test name
Test status
Simulation time 24143559 ps
CPU time 0.87 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 06:37:01 PM PDT 24
Peak memory 206988 kb
Host smart-88c65d54-0309-4376-b366-c5edbf1342c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674651924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3674651924
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4037355287
Short name T191
Test name
Test status
Simulation time 35577734 ps
CPU time 0.86 seconds
Started Jul 12 06:36:57 PM PDT 24
Finished Jul 12 06:36:59 PM PDT 24
Peak memory 216592 kb
Host smart-dc6e5937-9933-41d5-99af-b5abfd0957f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037355287 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4037355287
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3434395562
Short name T456
Test name
Test status
Simulation time 24303930 ps
CPU time 1.09 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 218628 kb
Host smart-72908138-5fb6-4118-a1f2-987de02ac1f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434395562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3434395562
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2028535143
Short name T451
Test name
Test status
Simulation time 22846515 ps
CPU time 0.95 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 218520 kb
Host smart-36c19d3c-f423-41a1-8503-9a141ba84fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028535143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2028535143
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1787118498
Short name T595
Test name
Test status
Simulation time 42537207 ps
CPU time 1.14 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 217632 kb
Host smart-4b556211-4b40-471b-953f-d7c43c45700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787118498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1787118498
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4086632988
Short name T808
Test name
Test status
Simulation time 33332742 ps
CPU time 0.89 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:02 PM PDT 24
Peak memory 216016 kb
Host smart-86e98090-050e-4d3c-96df-e584ffcc9d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086632988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4086632988
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1293642733
Short name T857
Test name
Test status
Simulation time 34381649 ps
CPU time 0.94 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 06:37:01 PM PDT 24
Peak memory 207332 kb
Host smart-ec1a2845-6ca3-40de-9f21-7161494ad685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293642733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1293642733
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2749991516
Short name T396
Test name
Test status
Simulation time 45708132 ps
CPU time 0.97 seconds
Started Jul 12 06:37:02 PM PDT 24
Finished Jul 12 06:37:05 PM PDT 24
Peak memory 215620 kb
Host smart-f5fe501c-3265-4bba-ad44-c36ac7ed9d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749991516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2749991516
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1146582272
Short name T607
Test name
Test status
Simulation time 14584453413 ps
CPU time 363.37 seconds
Started Jul 12 06:36:55 PM PDT 24
Finished Jul 12 06:43:01 PM PDT 24
Peak memory 218340 kb
Host smart-9229fa50-01bc-4b26-bf53-9e86abb62af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146582272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1146582272
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3311211606
Short name T960
Test name
Test status
Simulation time 72576120 ps
CPU time 1.24 seconds
Started Jul 12 06:38:26 PM PDT 24
Finished Jul 12 06:38:29 PM PDT 24
Peak memory 219132 kb
Host smart-61e7e9f3-4357-4646-a4a6-6f8bba6558e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311211606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3311211606
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3938247688
Short name T984
Test name
Test status
Simulation time 21558590 ps
CPU time 0.93 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 218804 kb
Host smart-2c923ef9-26bc-417d-89f5-051cfff0e8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938247688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3938247688
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.492361926
Short name T656
Test name
Test status
Simulation time 43254016 ps
CPU time 1.77 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 220500 kb
Host smart-74cb9017-471e-40fd-bcd5-02753de09e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492361926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.492361926
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2636870879
Short name T111
Test name
Test status
Simulation time 41414466 ps
CPU time 1.12 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 218896 kb
Host smart-2fe1d440-3b5b-4ae7-b4c6-2a1f53e41e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636870879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2636870879
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1251444157
Short name T690
Test name
Test status
Simulation time 28763702 ps
CPU time 1.25 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 229916 kb
Host smart-8e0e704c-7b96-4a7d-b8e5-5a3f60d687f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251444157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1251444157
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3360074777
Short name T358
Test name
Test status
Simulation time 95398813 ps
CPU time 1.14 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 217656 kb
Host smart-e8c6f9c4-e68f-43df-95f9-52a17327bed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360074777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3360074777
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.4144865267
Short name T691
Test name
Test status
Simulation time 28566487 ps
CPU time 1.27 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:29 PM PDT 24
Peak memory 218968 kb
Host smart-9aadac93-2412-46bf-b637-cb17caa21519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144865267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.4144865267
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.765400079
Short name T599
Test name
Test status
Simulation time 37919973 ps
CPU time 0.93 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 218536 kb
Host smart-10fa8a6e-0e5b-4fbb-9f15-b990aaa23d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765400079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.765400079
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3307388121
Short name T436
Test name
Test status
Simulation time 78948485 ps
CPU time 1.11 seconds
Started Jul 12 06:38:29 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 217768 kb
Host smart-648f26cc-5c0b-4ec4-a688-47758e796ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307388121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3307388121
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3777144952
Short name T819
Test name
Test status
Simulation time 26508181 ps
CPU time 1.28 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 220672 kb
Host smart-1a8ab7e7-88a1-47c2-ad00-5668654ef940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777144952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3777144952
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3265706028
Short name T55
Test name
Test status
Simulation time 68257983 ps
CPU time 0.96 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 224060 kb
Host smart-fdf8ef8f-36f7-4bdd-a0d7-b607e2e53cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265706028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3265706028
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3852958824
Short name T791
Test name
Test status
Simulation time 73772031 ps
CPU time 1.38 seconds
Started Jul 12 06:38:22 PM PDT 24
Finished Jul 12 06:38:26 PM PDT 24
Peak memory 218792 kb
Host smart-0af4a2fb-4f9a-4cce-9a43-3a85a72abce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852958824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3852958824
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.4213248198
Short name T732
Test name
Test status
Simulation time 74365782 ps
CPU time 1.23 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 220272 kb
Host smart-ca18f370-e810-44a7-a302-3c78174e7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213248198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4213248198
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1370821408
Short name T119
Test name
Test status
Simulation time 25288353 ps
CPU time 1.24 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 229976 kb
Host smart-b9b1c0f8-d854-44b0-86c4-c3448998293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370821408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1370821408
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2474968178
Short name T912
Test name
Test status
Simulation time 81000703 ps
CPU time 2.44 seconds
Started Jul 12 06:38:25 PM PDT 24
Finished Jul 12 06:38:30 PM PDT 24
Peak memory 219612 kb
Host smart-41246b2a-28ff-4996-952d-eb188a4bfa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474968178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2474968178
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1148504549
Short name T134
Test name
Test status
Simulation time 24511764 ps
CPU time 1.18 seconds
Started Jul 12 06:38:26 PM PDT 24
Finished Jul 12 06:38:29 PM PDT 24
Peak memory 220828 kb
Host smart-c282b770-9635-40c5-8281-6e7178c65ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148504549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1148504549
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2015419769
Short name T197
Test name
Test status
Simulation time 39366617 ps
CPU time 0.91 seconds
Started Jul 12 06:38:29 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 218480 kb
Host smart-efe8546f-1056-4a47-a3d1-b0e6b1ac52da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015419769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2015419769
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2189474862
Short name T444
Test name
Test status
Simulation time 56021046 ps
CPU time 1.12 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 219292 kb
Host smart-a05fc75d-4926-4a2b-8cd4-ae4d8adce010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189474862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2189474862
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1952194240
Short name T457
Test name
Test status
Simulation time 29676124 ps
CPU time 1.28 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 215956 kb
Host smart-4dc944ee-0d19-4d6e-b506-34d2e3f9af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952194240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1952194240
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3276210729
Short name T189
Test name
Test status
Simulation time 22457953 ps
CPU time 0.99 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:26 PM PDT 24
Peak memory 218728 kb
Host smart-4b6210c0-8751-4cdb-9d9b-41d73b43df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276210729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3276210729
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2207097842
Short name T525
Test name
Test status
Simulation time 96967299 ps
CPU time 1.71 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:30 PM PDT 24
Peak memory 220368 kb
Host smart-4e887dd0-0886-4bc9-942c-64f8d7bc64fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207097842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2207097842
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.561527520
Short name T504
Test name
Test status
Simulation time 35841278 ps
CPU time 1.1 seconds
Started Jul 12 06:38:21 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 218868 kb
Host smart-70864933-6642-4620-ba71-a16efd6fd3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561527520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.561527520
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.801896014
Short name T696
Test name
Test status
Simulation time 18185674 ps
CPU time 1.17 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:31 PM PDT 24
Peak memory 224208 kb
Host smart-b9f82434-cc5e-4066-8484-752fa0018369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801896014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.801896014
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1330221258
Short name T736
Test name
Test status
Simulation time 70311508 ps
CPU time 1.67 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 218940 kb
Host smart-1d578586-43d7-4192-8659-fc07f6c47d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330221258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1330221258
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.224526853
Short name T196
Test name
Test status
Simulation time 33567269 ps
CPU time 0.87 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 218616 kb
Host smart-7245588a-3150-45ab-9f79-629a59baa049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224526853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.224526853
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3208943386
Short name T400
Test name
Test status
Simulation time 63600705 ps
CPU time 1.04 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 217808 kb
Host smart-59806971-9bb7-4efc-b5bf-97c089584c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208943386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3208943386
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2002844704
Short name T840
Test name
Test status
Simulation time 23589084 ps
CPU time 1.18 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:35 PM PDT 24
Peak memory 219192 kb
Host smart-d99c4c2f-5539-45c5-9a5e-80f3a4764124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002844704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2002844704
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1225243556
Short name T926
Test name
Test status
Simulation time 149821145 ps
CPU time 1.06 seconds
Started Jul 12 06:38:29 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 219752 kb
Host smart-34c6188d-0c16-4189-b7b3-1ed56068d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225243556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1225243556
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.913455342
Short name T241
Test name
Test status
Simulation time 47898206 ps
CPU time 1.13 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:31 PM PDT 24
Peak memory 217948 kb
Host smart-33925d57-66ff-4a51-bdb0-7b7bd95a3b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913455342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.913455342
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1487025323
Short name T856
Test name
Test status
Simulation time 48675563 ps
CPU time 1.22 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 06:37:02 PM PDT 24
Peak memory 220872 kb
Host smart-ab163f42-405b-48c9-9679-c54c9c57f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487025323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1487025323
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1493099030
Short name T704
Test name
Test status
Simulation time 47921395 ps
CPU time 1.04 seconds
Started Jul 12 06:37:03 PM PDT 24
Finished Jul 12 06:37:06 PM PDT 24
Peak memory 207164 kb
Host smart-74fd8310-447a-4373-b8c6-dcef5dae1c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493099030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1493099030
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2713133970
Short name T699
Test name
Test status
Simulation time 44910926 ps
CPU time 1.02 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 218672 kb
Host smart-0d633645-403b-458a-9c28-a5cbd4c59057
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713133970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2713133970
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3000210187
Short name T16
Test name
Test status
Simulation time 26968846 ps
CPU time 1.37 seconds
Started Jul 12 06:37:15 PM PDT 24
Finished Jul 12 06:37:20 PM PDT 24
Peak memory 229956 kb
Host smart-270f6111-5b7f-4d48-b532-980641b42a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000210187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3000210187
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3978326942
Short name T810
Test name
Test status
Simulation time 36916095 ps
CPU time 1.42 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:04 PM PDT 24
Peak memory 219860 kb
Host smart-17a666cc-1129-424d-8a85-0ae39fb6bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978326942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3978326942
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.157110269
Short name T82
Test name
Test status
Simulation time 36462324 ps
CPU time 0.86 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 215496 kb
Host smart-437ca118-b7dd-4477-841b-45c18c040641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157110269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.157110269
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2075823713
Short name T609
Test name
Test status
Simulation time 47036711 ps
CPU time 0.93 seconds
Started Jul 12 06:36:56 PM PDT 24
Finished Jul 12 06:36:58 PM PDT 24
Peak memory 207404 kb
Host smart-9b4fad5b-aa2c-4bf1-af11-419cfc264ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075823713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2075823713
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2932714657
Short name T680
Test name
Test status
Simulation time 27651769 ps
CPU time 0.97 seconds
Started Jul 12 06:36:59 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 215600 kb
Host smart-d56512ce-c1e9-4f8c-908f-ac30a1ddeb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932714657 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2932714657
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2074583843
Short name T106
Test name
Test status
Simulation time 174323837 ps
CPU time 2.39 seconds
Started Jul 12 06:37:02 PM PDT 24
Finished Jul 12 06:37:06 PM PDT 24
Peak memory 217496 kb
Host smart-ef39815d-4b6f-466c-ba40-39da71236be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074583843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2074583843
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.491335652
Short name T637
Test name
Test status
Simulation time 143735420143 ps
CPU time 432.06 seconds
Started Jul 12 06:36:57 PM PDT 24
Finished Jul 12 06:44:10 PM PDT 24
Peak memory 219116 kb
Host smart-d9b1c855-8277-4d44-b4ad-288bdfa63105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491335652 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.491335652
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1475270282
Short name T673
Test name
Test status
Simulation time 69186747 ps
CPU time 1.16 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 220036 kb
Host smart-db331132-d5a2-4633-941c-7073c6a5b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475270282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1475270282
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2891881070
Short name T218
Test name
Test status
Simulation time 22754344 ps
CPU time 0.95 seconds
Started Jul 12 06:38:26 PM PDT 24
Finished Jul 12 06:38:29 PM PDT 24
Peak memory 218912 kb
Host smart-ca95ccd1-67e9-41aa-9276-e44d5b9c3c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891881070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2891881070
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.996396975
Short name T929
Test name
Test status
Simulation time 38621835 ps
CPU time 1.06 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 217380 kb
Host smart-ff0e0718-87c2-4fce-9bc0-2ba18156b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996396975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.996396975
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2798972076
Short name T324
Test name
Test status
Simulation time 23840969 ps
CPU time 1.21 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:35 PM PDT 24
Peak memory 218928 kb
Host smart-b9db4bc4-847c-47f3-b5f1-88c3bfe670c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798972076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2798972076
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1543453238
Short name T126
Test name
Test status
Simulation time 35348859 ps
CPU time 1.14 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:31 PM PDT 24
Peak memory 220952 kb
Host smart-fc56e754-4a27-4024-8779-7a05e01a9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543453238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1543453238
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1413358989
Short name T972
Test name
Test status
Simulation time 95037356 ps
CPU time 1.42 seconds
Started Jul 12 06:38:20 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 219044 kb
Host smart-9153b8c8-e4a4-4676-a215-b3a08f473332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413358989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1413358989
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1399118659
Short name T958
Test name
Test status
Simulation time 23202628 ps
CPU time 1.18 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 218928 kb
Host smart-5624e35f-8832-4b16-97c9-6f3fa4458107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399118659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1399118659
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3653607896
Short name T100
Test name
Test status
Simulation time 41354317 ps
CPU time 1.01 seconds
Started Jul 12 06:38:20 PM PDT 24
Finished Jul 12 06:38:24 PM PDT 24
Peak memory 218936 kb
Host smart-f8675fea-859a-4ddb-bbe2-aca1ea1291fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653607896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3653607896
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1667408040
Short name T943
Test name
Test status
Simulation time 203548751 ps
CPU time 1.12 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:28 PM PDT 24
Peak memory 216940 kb
Host smart-180e758f-3f3a-4b74-b171-3890342abc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667408040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1667408040
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1486894152
Short name T887
Test name
Test status
Simulation time 49060692 ps
CPU time 1.23 seconds
Started Jul 12 06:38:21 PM PDT 24
Finished Jul 12 06:38:25 PM PDT 24
Peak memory 219292 kb
Host smart-9e300121-9f6a-4bdb-ac98-11edd4eac210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486894152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1486894152
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4029736266
Short name T892
Test name
Test status
Simulation time 72581781 ps
CPU time 1.12 seconds
Started Jul 12 06:38:24 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 229884 kb
Host smart-de6c28a7-ce52-45e0-9594-d0bd6a44a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029736266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4029736266
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.669629832
Short name T344
Test name
Test status
Simulation time 230179148 ps
CPU time 1.78 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 219152 kb
Host smart-998e4b65-9377-48b1-bc27-5d27b2d3d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669629832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.669629832
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.147547337
Short name T771
Test name
Test status
Simulation time 23363304 ps
CPU time 1.11 seconds
Started Jul 12 06:38:23 PM PDT 24
Finished Jul 12 06:38:27 PM PDT 24
Peak memory 218816 kb
Host smart-11690571-f741-413c-81a5-0861609e8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147547337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.147547337
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4241555756
Short name T174
Test name
Test status
Simulation time 24757008 ps
CPU time 1.02 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 224040 kb
Host smart-08e5798d-c4b6-4b4f-9500-ac8526b9b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241555756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4241555756
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1982593559
Short name T718
Test name
Test status
Simulation time 53761680 ps
CPU time 1.67 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 218904 kb
Host smart-f6354ba7-8ce9-42b3-b60e-b37a0a2142cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982593559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1982593559
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3444362549
Short name T72
Test name
Test status
Simulation time 50614964 ps
CPU time 1.13 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 220600 kb
Host smart-56b08bb2-5524-4182-b83b-bf28dc746399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444362549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3444362549
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1961047218
Short name T703
Test name
Test status
Simulation time 299900880 ps
CPU time 1.13 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:30 PM PDT 24
Peak memory 225976 kb
Host smart-bf0171cc-fa88-4c74-912d-cf2eaac4017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961047218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1961047218
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3790676370
Short name T348
Test name
Test status
Simulation time 45431368 ps
CPU time 1.38 seconds
Started Jul 12 06:38:34 PM PDT 24
Finished Jul 12 06:38:37 PM PDT 24
Peak memory 218848 kb
Host smart-f147ba3b-b638-4429-a8bb-c3d14e5b9847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790676370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3790676370
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2480188151
Short name T538
Test name
Test status
Simulation time 41678954 ps
CPU time 1.21 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:31 PM PDT 24
Peak memory 220376 kb
Host smart-b92e6ca1-2554-4c33-b518-eb7928a42a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480188151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2480188151
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2856212599
Short name T118
Test name
Test status
Simulation time 35078886 ps
CPU time 1.22 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 229992 kb
Host smart-a524e59b-a693-4466-af88-08c1d2fc94b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856212599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2856212599
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3365237266
Short name T332
Test name
Test status
Simulation time 68427826 ps
CPU time 1.12 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:37 PM PDT 24
Peak memory 218736 kb
Host smart-36133036-c88a-4c80-b9dd-8ac12c209a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365237266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3365237266
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1859966115
Short name T48
Test name
Test status
Simulation time 30234227 ps
CPU time 1.4 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 219496 kb
Host smart-3d2cf35f-844c-48f1-b46d-3bc6e6274530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859966115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1859966115
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3862614331
Short name T781
Test name
Test status
Simulation time 47820861 ps
CPU time 0.98 seconds
Started Jul 12 06:38:32 PM PDT 24
Finished Jul 12 06:38:35 PM PDT 24
Peak memory 220036 kb
Host smart-94484bc2-03ec-44a1-8b05-748698cda036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862614331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3862614331
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.546724249
Short name T2
Test name
Test status
Simulation time 26642023 ps
CPU time 1.29 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 217828 kb
Host smart-fc1be0fe-e3fc-4e12-a562-ecaf4f3cb2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546724249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.546724249
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1643998816
Short name T275
Test name
Test status
Simulation time 431296477 ps
CPU time 1.48 seconds
Started Jul 12 06:38:30 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 219992 kb
Host smart-a3a0ade9-dec8-4b7a-b532-be7900fd8cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643998816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1643998816
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1610986121
Short name T951
Test name
Test status
Simulation time 18457018 ps
CPU time 1.04 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:37 PM PDT 24
Peak memory 218568 kb
Host smart-851bd3dd-a273-4545-920a-9c270231852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610986121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1610986121
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1864048150
Short name T769
Test name
Test status
Simulation time 45622846 ps
CPU time 1.12 seconds
Started Jul 12 06:38:32 PM PDT 24
Finished Jul 12 06:38:36 PM PDT 24
Peak memory 217524 kb
Host smart-f8e674cd-59e5-41d7-9233-818562e9fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864048150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1864048150
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.271213190
Short name T556
Test name
Test status
Simulation time 44823696 ps
CPU time 1.21 seconds
Started Jul 12 06:38:31 PM PDT 24
Finished Jul 12 06:38:35 PM PDT 24
Peak memory 220588 kb
Host smart-61937735-bd05-40dc-8d89-aa55609b8ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271213190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.271213190
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1632786196
Short name T69
Test name
Test status
Simulation time 25815850 ps
CPU time 1.02 seconds
Started Jul 12 06:38:29 PM PDT 24
Finished Jul 12 06:38:34 PM PDT 24
Peak memory 220160 kb
Host smart-14231c58-58e0-43d8-a67b-fcc94bccb741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632786196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1632786196
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1622710755
Short name T965
Test name
Test status
Simulation time 45709790 ps
CPU time 1.3 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 217552 kb
Host smart-9377449a-f88e-4961-878b-9b757a4b81ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622710755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1622710755
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3805651736
Short name T708
Test name
Test status
Simulation time 24694824 ps
CPU time 1.23 seconds
Started Jul 12 06:37:04 PM PDT 24
Finished Jul 12 06:37:07 PM PDT 24
Peak memory 221272 kb
Host smart-d57026c8-1fc2-4ca0-9479-71b521b4b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805651736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3805651736
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.181773562
Short name T914
Test name
Test status
Simulation time 23952784 ps
CPU time 0.83 seconds
Started Jul 12 06:37:14 PM PDT 24
Finished Jul 12 06:37:19 PM PDT 24
Peak memory 206984 kb
Host smart-a6d7fdc0-442a-49f0-9cb8-f3243437066e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181773562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.181773562
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1527796092
Short name T439
Test name
Test status
Simulation time 10531958 ps
CPU time 0.88 seconds
Started Jul 12 06:37:03 PM PDT 24
Finished Jul 12 06:37:05 PM PDT 24
Peak memory 216256 kb
Host smart-95408cf0-c5e9-416c-a8cc-e502b2607203
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527796092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1527796092
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1478383044
Short name T776
Test name
Test status
Simulation time 59653221 ps
CPU time 1.24 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 217276 kb
Host smart-f5a42347-f603-4aaf-9a4d-fb14e74276dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478383044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1478383044
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.631459920
Short name T715
Test name
Test status
Simulation time 23878924 ps
CPU time 1.04 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:09 PM PDT 24
Peak memory 224224 kb
Host smart-ecb8524b-2c03-49df-99e8-fe68dbe67fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631459920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.631459920
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.844567773
Short name T639
Test name
Test status
Simulation time 46698822 ps
CPU time 1.08 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:13 PM PDT 24
Peak memory 217600 kb
Host smart-b10493c3-9cb2-4500-b908-23e2e3b3baec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844567773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.844567773
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2931990888
Short name T709
Test name
Test status
Simulation time 27045790 ps
CPU time 0.97 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:11 PM PDT 24
Peak memory 215832 kb
Host smart-2f27b74a-6a9b-41b8-b517-82d2adef0dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931990888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2931990888
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1745357835
Short name T612
Test name
Test status
Simulation time 236481779 ps
CPU time 0.96 seconds
Started Jul 12 06:37:05 PM PDT 24
Finished Jul 12 06:37:08 PM PDT 24
Peak memory 207388 kb
Host smart-89206b4e-6bcf-4ddd-894f-90614d73dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745357835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1745357835
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3563564437
Short name T883
Test name
Test status
Simulation time 38683218 ps
CPU time 1.01 seconds
Started Jul 12 06:37:08 PM PDT 24
Finished Jul 12 06:37:13 PM PDT 24
Peak memory 215552 kb
Host smart-cde8aa26-e862-4454-bb5a-a8c312328727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563564437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3563564437
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.884288401
Short name T724
Test name
Test status
Simulation time 281681835 ps
CPU time 2.12 seconds
Started Jul 12 06:37:07 PM PDT 24
Finished Jul 12 06:37:13 PM PDT 24
Peak memory 217708 kb
Host smart-88ed1bf7-a41b-4ccd-bb4e-ced3bb276c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884288401 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.884288401
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.388060944
Short name T762
Test name
Test status
Simulation time 60239106833 ps
CPU time 669.07 seconds
Started Jul 12 06:37:06 PM PDT 24
Finished Jul 12 06:48:17 PM PDT 24
Peak memory 219000 kb
Host smart-ba1a6053-fed8-4196-95b4-e35983b692fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388060944 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.388060944
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.405057146
Short name T183
Test name
Test status
Simulation time 158764927 ps
CPU time 1.09 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 218704 kb
Host smart-7e60f31b-a779-4073-a4c2-b9dc8d2d5546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405057146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.405057146
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2412960339
Short name T838
Test name
Test status
Simulation time 59292366 ps
CPU time 0.99 seconds
Started Jul 12 06:38:31 PM PDT 24
Finished Jul 12 06:38:35 PM PDT 24
Peak memory 219848 kb
Host smart-20e01330-bf3b-4b50-92f1-f47b38853c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412960339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2412960339
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_alert.210797416
Short name T802
Test name
Test status
Simulation time 37856446 ps
CPU time 1.14 seconds
Started Jul 12 06:38:32 PM PDT 24
Finished Jul 12 06:38:36 PM PDT 24
Peak memory 220620 kb
Host smart-3ea63a4e-65fb-48b2-b79c-6809b3ffb941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210797416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.210797416
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2621358501
Short name T212
Test name
Test status
Simulation time 27031922 ps
CPU time 1.01 seconds
Started Jul 12 06:38:29 PM PDT 24
Finished Jul 12 06:38:33 PM PDT 24
Peak memory 219000 kb
Host smart-eebe1de1-5928-4eba-b2d8-e379d9818eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621358501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2621358501
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3840952480
Short name T476
Test name
Test status
Simulation time 75793209 ps
CPU time 2.81 seconds
Started Jul 12 06:38:33 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 220364 kb
Host smart-9b37ed97-e785-4062-b5a8-c6876f5c0853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840952480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3840952480
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3774900709
Short name T132
Test name
Test status
Simulation time 44529807 ps
CPU time 1.26 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 220464 kb
Host smart-7f031a01-ba8d-4c34-aa66-a3439642cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774900709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3774900709
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3179566753
Short name T773
Test name
Test status
Simulation time 26310502 ps
CPU time 1.05 seconds
Started Jul 12 06:38:28 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 219788 kb
Host smart-b74cf2d1-4162-422b-a8a4-f8f1c70e112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179566753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3179566753
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3026664342
Short name T24
Test name
Test status
Simulation time 64776534 ps
CPU time 2.28 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:39 PM PDT 24
Peak memory 220248 kb
Host smart-d723aecc-8586-4ef2-96fd-e9fdeac7d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026664342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3026664342
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.998557904
Short name T662
Test name
Test status
Simulation time 38824086 ps
CPU time 1.23 seconds
Started Jul 12 06:38:39 PM PDT 24
Finished Jul 12 06:38:42 PM PDT 24
Peak memory 218952 kb
Host smart-66acdd79-25cd-4a21-8232-f5a1f4b5cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998557904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.998557904
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2924639884
Short name T527
Test name
Test status
Simulation time 26314297 ps
CPU time 0.94 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:40 PM PDT 24
Peak memory 218592 kb
Host smart-41fb891d-c666-49cc-b17a-7fed8c16a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924639884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2924639884
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1663018076
Short name T380
Test name
Test status
Simulation time 36919245 ps
CPU time 1.29 seconds
Started Jul 12 06:38:27 PM PDT 24
Finished Jul 12 06:38:31 PM PDT 24
Peak memory 218552 kb
Host smart-2e9e6f2a-7ead-4fcd-bc0c-0ccb3a1facab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663018076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1663018076
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3057239598
Short name T982
Test name
Test status
Simulation time 25437257 ps
CPU time 1.25 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:37 PM PDT 24
Peak memory 218900 kb
Host smart-113810b6-1b2d-470f-8444-8ff0ebf0c0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057239598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3057239598
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.252243461
Short name T986
Test name
Test status
Simulation time 20204810 ps
CPU time 1.23 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 224224 kb
Host smart-475bf2d0-da9f-4637-802b-f930f5629277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252243461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.252243461
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3162788897
Short name T957
Test name
Test status
Simulation time 141348769 ps
CPU time 1.36 seconds
Started Jul 12 06:38:38 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 220568 kb
Host smart-8e41e753-250c-4293-922a-c5dd66385c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162788897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3162788897
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1885381994
Short name T836
Test name
Test status
Simulation time 135228523 ps
CPU time 1.11 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 220964 kb
Host smart-d93c616f-9b10-48c4-82f7-675acb263a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885381994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1885381994
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_genbits.3494629622
Short name T801
Test name
Test status
Simulation time 50994155 ps
CPU time 1.35 seconds
Started Jul 12 06:38:38 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 219080 kb
Host smart-105a2aec-797c-476f-bf6d-e457fac6a8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494629622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3494629622
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1631780105
Short name T223
Test name
Test status
Simulation time 41908968 ps
CPU time 1.17 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:43 PM PDT 24
Peak memory 219200 kb
Host smart-13e65c1f-e05e-4497-a31e-f94cedf9a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631780105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1631780105
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1408042313
Short name T121
Test name
Test status
Simulation time 28057598 ps
CPU time 1.2 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:37 PM PDT 24
Peak memory 220784 kb
Host smart-634271a0-98f4-4a2c-a4e7-8ff81cc88e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408042313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1408042313
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.484418409
Short name T486
Test name
Test status
Simulation time 94926381 ps
CPU time 1.23 seconds
Started Jul 12 06:38:33 PM PDT 24
Finished Jul 12 06:38:36 PM PDT 24
Peak memory 219648 kb
Host smart-bf1e8e18-c968-455e-be12-705ec79af833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484418409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.484418409
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3729808142
Short name T195
Test name
Test status
Simulation time 67813204 ps
CPU time 1.15 seconds
Started Jul 12 06:38:39 PM PDT 24
Finished Jul 12 06:38:42 PM PDT 24
Peak memory 219308 kb
Host smart-88073eab-809d-4b68-901f-5a91a5b507c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729808142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3729808142
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2116386260
Short name T159
Test name
Test status
Simulation time 34318468 ps
CPU time 0.92 seconds
Started Jul 12 06:38:40 PM PDT 24
Finished Jul 12 06:38:43 PM PDT 24
Peak memory 218652 kb
Host smart-653e938d-2b18-464e-a3c2-0f3528f1cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116386260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2116386260
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2353649495
Short name T295
Test name
Test status
Simulation time 106948639 ps
CPU time 1.83 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 219348 kb
Host smart-91ecfe78-1825-464d-80aa-2b5095f0f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353649495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2353649495
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3864260354
Short name T411
Test name
Test status
Simulation time 50594068 ps
CPU time 1.26 seconds
Started Jul 12 06:38:35 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 220592 kb
Host smart-98a1c50f-e9b0-49f3-b296-b9a3f1794fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864260354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3864260354
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.4019489715
Short name T53
Test name
Test status
Simulation time 53011736 ps
CPU time 1.13 seconds
Started Jul 12 06:38:39 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 229940 kb
Host smart-b6e53c86-c980-4149-a706-975c2eedba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019489715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4019489715
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2180467033
Short name T894
Test name
Test status
Simulation time 41164315 ps
CPU time 1.73 seconds
Started Jul 12 06:38:42 PM PDT 24
Finished Jul 12 06:38:46 PM PDT 24
Peak memory 218748 kb
Host smart-dde68fa5-906e-490d-8ee1-2a24b3343fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180467033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2180467033
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2666614647
Short name T643
Test name
Test status
Simulation time 98755125 ps
CPU time 1.35 seconds
Started Jul 12 06:38:36 PM PDT 24
Finished Jul 12 06:38:38 PM PDT 24
Peak memory 220068 kb
Host smart-fcf2b343-dcfd-4df0-ad9b-cdb7b57241cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666614647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2666614647
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2963178499
Short name T154
Test name
Test status
Simulation time 21008537 ps
CPU time 1.16 seconds
Started Jul 12 06:38:38 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 219952 kb
Host smart-59491cb0-bb45-4628-8b51-84fc87cd48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963178499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2963178499
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3400773194
Short name T874
Test name
Test status
Simulation time 50511070 ps
CPU time 1.86 seconds
Started Jul 12 06:38:37 PM PDT 24
Finished Jul 12 06:38:41 PM PDT 24
Peak memory 220824 kb
Host smart-f2c4f10a-5ec6-4bfa-8ff6-966cc85bc492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400773194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3400773194
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%